diff --git a/Documentation/ABI/stable/sysfs-bus-fsl-mc b/Documentation/ABI/stable/sysfs-bus-fsl-mc new file mode 100644 index 00000000000000..e5c7f7fca0b3e7 --- /dev/null +++ b/Documentation/ABI/stable/sysfs-bus-fsl-mc @@ -0,0 +1,19 @@ +What: /sys/bus/fsl-mc/devices/dprc.*/rescan +Date: November 2018 +KernelVersion: 5.0 +Contact: Ioana Ciornei +Description: Writing a non-zero value to this attribute will + force a rescan of dprc.X container in the system and + synchronize the objects under dprc.X and the + Management Complex firmware. +Users: Userspace drivers and management tools + +What: /sys/bus/fsl-mc/rescan +Date: November 2018 +KernelVersion: 5.0 +Contact: Ioana Ciornei +Description: Writing a non-zero value to this attribute will + force a rescan of fsl-mc bus in the system and + synchronize the objects under fsl-mc bus and the + Management Complex firmware. +Users: Userspace drivers and management tools diff --git a/Documentation/ABI/testing/sysfs-devices-links b/Documentation/ABI/testing/sysfs-devices-links new file mode 100644 index 00000000000000..b4a649041f6a9e --- /dev/null +++ b/Documentation/ABI/testing/sysfs-devices-links @@ -0,0 +1,13 @@ +What: /sys/devices/.../consumers +Date: October 2018 +Contact: Ioana Ciornei +Description: + Read-only attribute that lists the current "consumers" of + a specific device. + +What: /sys/devices/.../suppliers +Date: October 2018 +Contact: Ioana Ciornei +Description: + Read-only attribute that lists the current "suppliers" of + a specific device. diff --git a/Documentation/ABI/testing/sysfs-platform-cadence-usb3 b/Documentation/ABI/testing/sysfs-platform-cadence-usb3 new file mode 100644 index 00000000000000..c969518dcc3076 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-platform-cadence-usb3 @@ -0,0 +1,9 @@ +What: /sys/bus/platform/devices/5b110000.usb3/role +Date: Jan 2019 +Contact: Peter Chen +Description: + It returns string "gadget", "host" and "none" when read it, + it indicates current controller role. + + It will do role switch when write "gadget" or "host" to it. + Only controller at dual-role configuration supports writing. diff --git a/Documentation/ABI/testing/usb-charger-uevent b/Documentation/ABI/testing/usb-charger-uevent new file mode 100644 index 00000000000000..93ffd3a54a7f6f --- /dev/null +++ b/Documentation/ABI/testing/usb-charger-uevent @@ -0,0 +1,45 @@ +What: Raise a uevent when a USB charger is inserted or removed +Date: 2019-11-11 +KernelVersion: 5.5 +Contact: linux-usb@vger.kernel.org +Description: There are two USB charger states: + USB_CHARGER_ABSENT + USB_CHARGER_PRESENT + There are five USB charger types: + USB_CHARGER_UNKNOWN_TYPE + USB_CHARGER_SDP_TYPE + USB_CHARGER_CDP_TYPE + USB_CHARGER_DCP_TYPE + USB_CHARGER_ACA_TYPE + + Here are two examples taken using udevadm monitor -p when + USB charger is online: + UDEV [227.425096] change /devices/soc0/usbphynop1 (platform) + ACTION=change + DEVPATH=/devices/soc0/usbphynop1 + DRIVER=usb_phy_generic + MODALIAS=of:Nusbphynop1T(null)Cusb-nop-xceiv + OF_COMPATIBLE_0=usb-nop-xceiv + OF_COMPATIBLE_N=1 + OF_FULLNAME=/usbphynop1 + OF_NAME=usbphynop1 + SEQNUM=2493 + SUBSYSTEM=platform + USB_CHARGER_STATE=USB_CHARGER_PRESENT + USB_CHARGER_TYPE=USB_CHARGER_SDP_TYPE + USEC_INITIALIZED=227422826 + + USB charger is offline: + KERNEL[229.533933] change /devices/soc0/usbphynop1 (platform) + ACTION=change + DEVPATH=/devices/soc0/usbphynop1 + DRIVER=usb_phy_generic + MODALIAS=of:Nusbphynop1T(null)Cusb-nop-xceiv + OF_COMPATIBLE_0=usb-nop-xceiv + OF_COMPATIBLE_N=1 + OF_FULLNAME=/usbphynop1 + OF_NAME=usbphynop1 + SEQNUM=2494 + SUBSYSTEM=platform + USB_CHARGER_STATE=USB_CHARGER_ABSENT + USB_CHARGER_TYPE=USB_CHARGER_UNKNOWN_TYPE diff --git a/Documentation/admin-guide/perf/imx-ddr.rst b/Documentation/admin-guide/perf/imx-ddr.rst index 517a205abad6bb..59fab27f62a17c 100644 --- a/Documentation/admin-guide/perf/imx-ddr.rst +++ b/Documentation/admin-guide/perf/imx-ddr.rst @@ -2,6 +2,8 @@ Freescale i.MX8 DDR Performance Monitoring Unit (PMU) ===================================================== +1. PMU in DRC (DDR Controller) + There are no performance counters inside the DRAM controller, so performance signals are brought out to the edge of the controller where a set of 4 x 32 bit counters is implemented. This is controlled by the CSV modes programed in counter @@ -13,40 +15,99 @@ is one register for each counter. Counter 0 is special in that it always counts interrupt is raised. If any other counter overflows, it continues counting, and no interrupt is raised. -The "format" directory describes format of the config (event ID) and config1 -(AXI filtering) fields of the perf_event_attr structure, see /sys/bus/event_source/ +The "format" directory describes format of the config (event ID) and config1/2 +(AXI filter setting) fields of the perf_event_attr structure, see /sys/bus/event_source/ devices/imx8_ddr0/format/. The "events" directory describes the events types hardware supported that can be used with perf tool, see /sys/bus/event_source/ -devices/imx8_ddr0/events/. - e.g.:: +devices/imx8_ddr0/events/. The "caps" directory describes filter features implemented +in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/. + + .. code-block:: bash + perf stat -a -e imx8_ddr0/cycles/ cmd perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write) to count reading or writing matches filter setting. Filter setting is various from different DRAM controller implementations, which is distinguished by quirks -in the driver. +in the driver. You also can dump info from userspace, "caps" directory show the +type of AXI filter (filter, enhanced_filter and super_filter). Value 0 for +un-supported, and value 1 for supported. -* With DDR_CAP_AXI_ID_FILTER quirk. +* With DDR_CAP_AXI_ID_FILTER quirk(filter: 1, enhanced_filter: 0, super_filter: 0). Filter is defined with two configuration parts: --AXI_ID defines AxID matching value. --AXI_MASKING defines which bits of AxID are meaningful for the matching. - 0：corresponding bit is masked. - 1: corresponding bit is not masked, i.e. used to do the matching. + + - 0: corresponding bit is masked. + - 1: corresponding bit is not masked, i.e. used to do the matching. AXI_ID and AXI_MASKING are mapped on DPCR1 register in performance counter. When non-masked bits are matching corresponding AXI_ID bits then counter is incremented. Perf counter is incremented if - AxID && AXI_MASKING == AXI_ID && AXI_MASKING + AxID && AXI_MASKING == AXI_ID && AXI_MASKING This filter doesn't support filter different AXI ID for axid-read and axid-write event at the same time as this filter is shared between counters. - e.g.:: - perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd - perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd - - NOTE: axi_mask is inverted in userspace(i.e. set bits are bits to mask), and - it will be reverted in driver automatically. so that the user can just specify - axi_id to monitor a specific id, rather than having to specify axi_mask. - e.g.:: - perf stat -a -e imx8_ddr0/axid-read,axi_id=0x12/ cmd, which will monitor ARID=0x12 + + .. code-block:: bash + + perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd + perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd + + .. note:: + + axi_mask is inverted in userspace(i.e. set bits are bits to mask), and + it will be reverted in driver automatically. so that the user can just specify + axi_id to monitor a specific id, rather than having to specify axi_mask. + + .. code-block:: bash + + perf stat -a -e imx8_ddr0/axid-read,axi_id=0x12/ cmd, which will monitor ARID=0x12 + +* With DDR_CAP_AXI_ID_FILTER_ENHANCED quirk(filter: 1, enhanced_filter: 1, super_filter: 0). + This is an extension to the DDR_CAP_AXI_ID_FILTER quirk which permits + counting the number of bytes (as opposed to the number of bursts) from DDR + read and write transactions concurrently with another set of data counters. + +* With DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER quirk(filter: 0, enhanced_filter: 0, super_filter: 1). + There is a limitation in previous AXI filter, it cannot filter different IDs + at the same time as the filter is shared between counters. This quirk is the + extension of AXI ID filter. One improvement is that counter 1-3 has their own + filter, means that it supports concurrently filter various IDs. Another + improvement is that counter 1-3 supports AXI PORT and CHANNEL selection. Support + selecting address channel or data channel. + + Filter is defined with 2 configuration registers per counter 1-3. + --Counter N MASK COMP register - including AXI_ID and AXI_MASKING. + --Counter N MUX CNTL register - including AXI CHANNEL and AXI PORT. + + - 0: address channel + - 1: data channel + + PMU in DDR subsystem, only one single port0 exists, so axi_port is reserved + which should be 0. + + .. code-block:: bash + + perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd + perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd + + .. note:: + + axi_channel is inverted in userspace, and it will be reverted in driver + automatically. So that users do not need specify axi_channel if want to + monitor data channel from DDR transactions, since data channel is more + meaningful. + +2. PMU in DB (DRAM Block) + + There is a performance counter function included in the DB which allows + statistics to be captured for the various ports. The module is similar to + the one deployed in the DRC but has the ability to select one of the incoming + ports to gather statistics on it. The AXI IDs used is the one seen at one PORT. + + .. code-block:: bash + + perf stat -a -e imx8_db0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD,axi_port=0xPP,axi_channel=0xH/ cmd + perf stat -a -e imx8_db0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD,axi_port=0xPP,axi_channel=0xH/ cmd diff --git a/Documentation/admin-guide/perf/index.rst b/Documentation/admin-guide/perf/index.rst index ee4bfd2a740f5d..47c99f40cc160b 100644 --- a/Documentation/admin-guide/perf/index.rst +++ b/Documentation/admin-guide/perf/index.rst @@ -8,6 +8,7 @@ Performance monitor support :maxdepth: 1 hisi-pmu + imx-ddr qcom_l2_pmu qcom_l3_pmu arm-ccn diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx-sc-secvio.yaml b/Documentation/devicetree/bindings/arm/freescale/fsl,imx-sc-secvio.yaml new file mode 100644 index 00000000000000..a3dc04ec9c54b6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx-sc-secvio.yaml @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/freescale/fsl,imx-sc-secvio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX Security Violation driver + +maintainers: + - Franck LENORMAND + +description: | + Receive security violation from the SNVS via the SCU firmware. Allow to + register notifier for additional processing + +properties: + compatible: + enum: + - fsl,imx-sc-secvio + +required: + - compatible diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt index b5cb374dc47d06..10a91cc8b9977d 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt @@ -8,7 +8,7 @@ Required properties: - compatible: Should contain a chip-specific compatible string, Chip-specific strings are of the form "fsl,-dcfg", The following s are known to be supported: - ls1012a, ls1021a, ls1043a, ls1046a, ls2080a. + ls1012a, ls1021a, ls1043a, ls1046a, ls2080a, lx2160a - reg : should contain base address and length of DCFG memory-mapped registers diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt index c149fadc6f47f3..fc5c22e81c6189 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt @@ -89,7 +89,7 @@ Required properties: "fsl,imx8qm-clock" "fsl,imx8qxp-clock" followed by "fsl,scu-clk" -- #clock-cells: Should be 1. Contains the Clock ID value. +- #clock-cells: Should be 2: Contains the Resource and Clock ID value. - clocks: List of clock specifiers, must contain an entry for each required entry in clock-names - clock-names: Should include entries "xtal_32KHz", "xtal_24MHz" @@ -97,9 +97,6 @@ Required properties: The clock consumer should specify the desired clock by having the clock ID in its "clocks" phandle cell. -See the full list of clock IDs from: -include/dt-bindings/clock/imx8qxp-clock.h - Pinctrl bindings based on SCU Message Protocol ------------------------------------------------------------ @@ -186,7 +183,7 @@ firmware { clk: clk { compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; - #clock-cells = <1>; + #clock-cells = <2>; }; iomuxc { @@ -231,8 +228,7 @@ serial@5a060000 { ... pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; - clocks = <&clk IMX8QXP_UART0_CLK>, - <&clk IMX8QXP_UART0_IPG_CLK>; - clock-names = "per", "ipg"; + clocks = <&uart0_clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>; + clock-names = "ipg"; power-domains = <&pd IMX_SC_R_UART_0>; }; diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,seco_mu.yaml b/Documentation/devicetree/bindings/arm/freescale/fsl,seco_mu.yaml new file mode 100644 index 00000000000000..c36bea2079c277 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,seco_mu.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/freescale/fsl,seco_mu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8 SECO MU driver + +maintainers: + - Aisheng Dong + +description: | + Create char devices in /dev as channels of the form /dev/seco_muXchY with X + the id of the driver and Y for each users. It allows to send and receive + messages to the SECO. + +properties: + compatible: + enum: + - fsl,imx-seco-mu + + mboxes: + description: + List of <&phandle type channel> - 4 channels for TX, 4 channels for RX, + 1 channel for TXDB (see mailbox/fsl,mu.txt) + maxItems: 9 + + mbox-names: + items: + - const: txdb + - const: rxdb + + fsl,seco_mu_id: + description: + Identify the driver instance, used to create the channels, default to 1 + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0,1,2,3] + + fsl,seco_max_users: + description: + Number of channels to create, default to 4 + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0,1,2,3,4,5,6,7,8,9] + + fsl,cmd_tag: + description: + Tag in message header for commands on this MU, default to 0x17 + allOf: + - $ref: /schemas/types.yaml#/definitions/uint8 + - enum: [0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e] + + fsl,rsp_tag: + description: + Tag in message header for responses on this MU, default to 0xe1 + allOf: + - $ref: /schemas/types.yaml#/definitions/uint8 + - enum: [0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8] + +required: + - compatible + - mboxes + - mbox-names + +examples: + - | + seco_mu: seco_mu { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&mu 2 0 + &mu 3 0>; + + fsl,seco_mu_id = <1>; + fsl,seco_max_users = <4>; + fsl,cmd_tag = /bits/ 8 <0x17>; + fsl,rsp_tag = /bits/ 8 <0xe1>; + }; diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 1b4b4e6573b59d..415ceaf673b41f 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -287,6 +287,7 @@ properties: - ebs-systart,oxalis - fsl,ls1012a-rdb - fsl,ls1012a-frdm + - fsl,ls1012a-frwy - fsl,ls1012a-qds - const: fsl,ls1012a @@ -335,4 +336,11 @@ properties: - fsl,ls2088a-rdb - const: fsl,ls2088a + - description: LX2160A based Boards + items: + - enum: + - fsl,lx2160a-qds + - fsl,lx2160a-rdb + - const: fsl,lx2160a + ... diff --git a/Documentation/devicetree/bindings/clock/fsl,plldig.yaml b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml new file mode 100644 index 00000000000000..ee5b5c61a47147 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/clock/fsl,plldig.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding + +maintainers: + - Wen He + +description: | + NXP LS1028A has a clock domain PXLCLK0 used for the Display output + interface in the display core, as implemented in TSMC CLN28HPM PLL. + which generate and offers pixel clocks to Display. + +properties: + compatible: + const: fsl,ls1028a-plldig + + reg: + maxItems: 1 + + '#clock-cells': + const: 0 + + vco-frequency: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: Optional for VCO frequency of the PLL in Hertz. + The VCO frequency of this PLL cannot be changed during runtime + only at startup. Therefore, the output frequencies are very + limited and might not even closely match the requested frequency. + To work around this restriction the user may specify its own + desired VCO frequency for the PLL. The frequency has to be in the + range of 650000000 to 1300000000. + If not set, the default frequency is 1188000000. + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +examples: + # Display PIXEL Clock node: + - | + dpclk: clock-display@f1f0000 { + compatible = "fsl,ls1028a-plldig"; + reg = <0x0 0xf1f0000 0x0 0xffff>; + #clock-cells = <0>; + clocks = <&osc_27m>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt index a4f8cd478f924d..93d89adb7afe7b 100644 --- a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt +++ b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt @@ -82,7 +82,6 @@ pcc2: pcc2@403f0000 { <&scg1 IMX7ULP_CLK_APLL_PFD0>, <&scg1 IMX7ULP_CLK_UPLL>, <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, - <&scg1 IMX7ULP_CLK_MIPI_PLL>, <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, <&scg1 IMX7ULP_CLK_ROSC>, <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; diff --git a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt index 965cfa42e02542..8faee11b20b460 100644 --- a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt +++ b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt @@ -11,32 +11,38 @@ enabled by these control bits, it might still not be running based on the base resource. Required properties: -- compatible: Should be one of: - "fsl,imx8qxp-lpcg-adma", - "fsl,imx8qxp-lpcg-conn", - "fsl,imx8qxp-lpcg-dc", - "fsl,imx8qxp-lpcg-dsp", - "fsl,imx8qxp-lpcg-gpu", - "fsl,imx8qxp-lpcg-hsio", - "fsl,imx8qxp-lpcg-img", - "fsl,imx8qxp-lpcg-lsio", - "fsl,imx8qxp-lpcg-vpu" -- reg: Address and length of the register set -- #clock-cells: Should be <1> +- compatible: Should be one of: + "fsl,imx8qxp-lpcg" + "fsl,imx8qm-lpcg" followed by "fsl,imx8qxp-lpcg". +- reg: Address and length of the register set. +- #clock-cells: Should be 1. One LPCG supports multiple clocks. +- clocks: Input parent clocks phandle array for each clock. +- bit-offset: An integer array indicating the bit offset for each clock. +- hw-autogate: Boolean array indicating whether supports HW autogate for + each clock. +- clock-output-names: Shall be the corresponding names of the outputs. + NOTE this property must be specified in the same order + as the clock bit-offset and hw-autogate property. +- power-domains: Should contain the power domain used by this clock. The clock consumer should specify the desired clock by having the clock ID in its "clocks" phandle cell. -See the full list of clock IDs from: -include/dt-bindings/clock/imx8qxp-clock.h Examples: #include -conn_lpcg: clock-controller@5b200000 { - compatible = "fsl,imx8qxp-lpcg-conn"; - reg = <0x5b200000 0xb0000>; +sdhc0_lpcg: clock-controller@5b200000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b200000 0x10000>; #clock-cells = <1>; + clocks = <&sdhc0_clk IMX_SC_PM_CLK_PER>, + <&conn_ipg_clk>, <&conn_axi_clk>; + bit-offset = <0 16 20>; + clock-output-names = "sdhc0_lpcg_per_clk", + "sdhc0_lpcg_ipg_clk", + "sdhc0_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_0>; }; usdhc1: mmc@5b010000 { @@ -44,8 +50,8 @@ usdhc1: mmc@5b010000 { interrupt-parent = <&gic>; interrupts = ; reg = <0x5b010000 0x10000>; - clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK>, - <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_PER_CLK>, - <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_HCLK>; + clocks = <&sdhc0_lpcg 1>, + <&sdhc0_lpcg 0>, + <&sdhc0_lpcg 2>; clock-names = "ipg", "per", "ahb"; }; diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt index f7d48f23da4447..10119d9ef4b11b 100644 --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt @@ -44,6 +44,7 @@ Required properties: * "fsl,ls1046a-clockgen" * "fsl,ls1088a-clockgen" * "fsl,ls2080a-clockgen" + * "fsl,lx2160a-clockgen" Chassis-version clock strings include: * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks diff --git a/Documentation/devicetree/bindings/clock/s32v234-mc_cgm.txt b/Documentation/devicetree/bindings/clock/s32v234-mc_cgm.txt new file mode 100644 index 00000000000000..d0d43e6ae597ce --- /dev/null +++ b/Documentation/devicetree/bindings/clock/s32v234-mc_cgm.txt @@ -0,0 +1,31 @@ +* NXP S32V234 Clock Generation Modules (MC_CGMs) + +The SoC supports four Clock Generation Modules, which provide registers for +system and peripherals clock source selection and division. See chapters 22 +("Clocking"), 23 ("Clock Generation Module (MC_CGM)") and 69 ("Mode Entry +Module (MC_ME)") in the reference manual[1]. + +This binding uses the common clock binding: + Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible: + Should be: + - "fsl,s32v234-mc_cgm0" for MC_CGM_0 + - "fsl,s32v234-mc_cgm1" for MC_CGM_1 + - "fsl,s32v234-mc_cgm2" for MC_CGM_2 + - "fsl,s32v234-mc_cgm3" for MC_CGM_3 +- reg: + Location and length of the register set +- #clock-cells (only for MC_CGM_0): + Should be <1>. See dt-bindings/clock/s32v234-clock.h for the clock + specifiers allowed in the clocks property of consumers. + +Example: +clks: mc_cgm0@4003c000 { + compatible = "fsl,s32v234-mc_cgm0"; + reg = <0x0 0x4003C000 0x0 0x1000>; + #clock-cells = <1>; +}; + +[1] https://www.nxp.com/webapp/Download?colCode=S32V234RM diff --git a/Documentation/devicetree/bindings/clock/s32v234-mc_me.txt b/Documentation/devicetree/bindings/clock/s32v234-mc_me.txt new file mode 100644 index 00000000000000..e9f4dcc3a257b6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/s32v234-mc_me.txt @@ -0,0 +1,16 @@ +* NXP S32V234 Mode Entry Module (MC_ME) + +See chapters 22 ("Clocking") and 69 ("Mode Entry Module (MC_ME)") in the +reference manual[1]. + +Required properties: +- compatible: Should be "fsl,s32v234-mc_me" +- reg: Location and length of the register set + +Example: +mc_me: mc_me@4004a000 { + compatible = "fsl,s32v234-mc_me"; + reg = <0x0 0x4004A000 0x0 0x1000>; +}; + +[1] https://www.nxp.com/webapp/Download?colCode=S32V234RM diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt index 2fe245ca816ac9..f38359231036f9 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt @@ -202,6 +202,26 @@ EXAMPLE }; +===================================================================== +Secure memory (SM) Node + + - compatible + Usage: required + Value type: + Definition: Must include "fsl,imx6q-caam-sm" + + - reg + Usage: required + Value type: + Definition: Specifies a two SM parameters: an offset from + the parent physical address and the length the SM registers. + +EXAMPLE + caam_sm: caam-sm@100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x4000>; + }; + ===================================================================== Run Time Integrity Check (RTIC) Node @@ -365,6 +385,91 @@ EXAMPLE interrupts = <93 2>; }; +===================================================================== +CAAM SNVS Node + Load the CAAM SNVS node. + + - compatible + Usage: required + Value type: + Definition: Must include "fsl,imx6q-caam-snvs". + + - reg + Usage: required + Value type: + Definition: A standard property. Specifies the physical + address and length of the SEC4 configuration + registers. + + - clocks + Usage: required if i.MX clk driver defines an SNVS clock + Value type: + Definition: Phandle and clock specifier pair describing + the clock required for enabling and disabling SNVS. + + - clock-names + Usage: required if i.MX clk driver defines an SNVS clock + Value type: + Definition: Clock name string corresponding to the clock + in the clocks property. + +===================================================================== +Security Violation (SECVIO) Node + Reports security violations. + + - compatible + Usage: required + Value type: + Definition: Must include "fsl,imx6q-caam-secvio". + + - interrupts + Usage: required + Value type: + Definition: Specifies the interrupts generated by this + device. The value of the interrupts property + consists of one interrupt specifier. The format + of the specifier is defined by the binding document + describing the node's interrupt parent. + + - jtag-tamper + Usage: optional-but-recommended + Value type: + Definition: + Security tamper on the JTAG + Must include "enabled" to enable. + + - watchdog-tamper + Usage: optional-but-recommended + Value type: + Definition: + Security tamper on the watchdog + Must include "enabled" to enable. + + - internal-boot-tamper + Usage: optional-but-recommended + Value type: + Definition: + Security tamper on the internal boot + Must include "enabled" to enable. + + - external-pin-tamper + Usage: optional-but-recommended + Value type: + Definition: + Security tamper on the external pin + Must include "enabled" to enable. + +EXAMPLE + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + ===================================================================== Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node @@ -394,18 +499,14 @@ Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node value type: Definition: LP register offset. default it is 0x34. - - clocks - Usage: optional, required if SNVS LP RTC requires explicit - enablement of clocks - Value type: - Definition: a clock specifier describing the clock required for - enabling and disabling SNVS LP RTC. - - - clock-names - Usage: optional, required if SNVS LP RTC requires explicit - enablement of clocks - Value type: - Definition: clock name string should be "snvs-rtc". + - clocks + Usage: optional + Value type: + Definition: A standard property. Specifies the source clock for + snvs register access. If i.MX clk driver defines the clock node, + it needs user to specify the clocks in device tree for all modules + with snvs LP/HP registers access. The modules involved snvs LP/HP + registers access are snvs-power key, snvs-rtc, and caam. EXAMPLE sec_mon_rtc_lp@1 { @@ -550,4 +651,18 @@ FULL EXAMPLE }; }; + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + }; + + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + ===================================================================== diff --git a/Documentation/devicetree/bindings/display/arm,malidp.txt b/Documentation/devicetree/bindings/display/arm,malidp.txt index 2f7870983ef184..7a97a2b48c2a21 100644 --- a/Documentation/devicetree/bindings/display/arm,malidp.txt +++ b/Documentation/devicetree/bindings/display/arm,malidp.txt @@ -37,6 +37,8 @@ Optional properties: Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) to be used for the framebuffer; if not present, the framebuffer may be located anywhere in memory. + - arm,malidp-arqos-high-level: integer of u32 value describing the ARQoS + levels of DP500's QoS signaling. Example: @@ -54,6 +56,7 @@ Example: clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>; clock-names = "pxlclk", "mclk", "aclk", "pclk"; arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; + arm,malidp-arqos-high-level = <0xd000d000>; port { dp0_output: endpoint { remote-endpoint = <&tda998x_2_input>; diff --git a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt index 2c887536258cfe..0c0b12e5884378 100644 --- a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt +++ b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt @@ -1,10 +1,10 @@ -Analog Device ADV7511(W)/13/33 HDMI Encoders +Analog Device ADV7511(W)/13/33/35 HDMI Encoders ----------------------------------------- -The ADV7511, ADV7511W, ADV7513 and ADV7533 are HDMI audio and video transmitters -compatible with HDMI 1.4 and DVI 1.0. They support color space conversion, -S/PDIF, CEC and HDCP. ADV7533 supports the DSI interface for input pixels, while -the others support RGB interface. +The ADV7511, ADV7511W, ADV7513, ADV7533 and ADV7535 are HDMI audio and video +transmitters compatible with HDMI 1.4 and DVI 1.0. They support color space +conversion, S/PDIF, CEC and HDCP. ADV7533 and ADV7535 support the DSI interface +for input pixels, while the others support RGB interface. Required properties: @@ -13,6 +13,7 @@ Required properties: "adi,adv7511w" "adi,adv7513" "adi,adv7533" + "adi,adv7535" - reg: I2C slave addresses The ADV7511 internal registers are split into four pages exposed through @@ -52,7 +53,7 @@ The following input format properties are required except in "rgb 1x" and - bgvdd-supply: A 1.8V supply that powers up the BGVDD pin. This is needed only for ADV7511. -The following properties are required for ADV7533: +The following properties are required for ADV7533 and ADV7535: - adi,dsi-lanes: Number of DSI data lanes connected to the DSI host. It should be one of 1, 2, 3 or 4. @@ -71,23 +72,31 @@ Optional properties: - adi,embedded-sync: The input uses synchronization signals embedded in the data stream (similar to BT.656). Defaults to separate H/V synchronization signals. -- adi,disable-timing-generator: Only for ADV7533. Disables the internal timing - generator. The chip will rely on the sync signals in the DSI data lanes, - rather than generate its own timings for HDMI output. +- adi,disable-timing-generator: Only for ADV7533 and ADV7535. Disables the + internal timing generator. The chip will rely on the sync signals in the DSI + data lanes, rather than generate its own timings for HDMI output. - clocks: from common clock binding: reference to the CEC clock. - clock-names: from common clock binding: must be "cec". - reg-names : Names of maps with programmable addresses. It can contain any map needing a non-default address. Possible maps names are : "main", "edid", "cec", "packet" +- adi,dsi-channel: Only for ADV7533 and ADV7535. DSI channel number to be used + when communicating with the DSI peripheral. It should be one of 0, 1, 2 or 3. +- adi,addr-cec: Only for ADV7533 and ADV7535. The I2C DSI-CEC register map + address to be programmed into the MAIN register map. +- adi,addr-edid: Only for ADV7533 and ADV7535. The I2C EDID register map + to be programmed into the MAIN register map. +- adi,addr-pkt: Only for ADV7533 and ADV7535. The I2C PACKET register map + to be programmed into the MAIN register map. Required nodes: The ADV7511 has two video ports. Their connections are modelled using the OF graph bindings specified in Documentation/devicetree/bindings/graph.txt. -- Video port 0 for the RGB, YUV or DSI input. In the case of ADV7533, the - remote endpoint phandle should be a reference to a valid mipi_dsi_host device - node. +- Video port 0 for the RGB, YUV or DSI input. In the case of ADV7533 and + ADV7535, the remote endpoint phandle should be a reference to a valid + mipi_dsi_host device node. - Video port 1 for the HDMI output - Audio port 2 for the HDMI audio input diff --git a/Documentation/devicetree/bindings/display/bridge/it6263.txt b/Documentation/devicetree/bindings/display/bridge/it6263.txt new file mode 100644 index 00000000000000..dc032dbdc6b387 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/it6263.txt @@ -0,0 +1,27 @@ +ITE IT6263 LVDS to HDMI bridge bindings + +Required properties: + - compatible: "ite,it6263" + - reg: i2c address of the bridge + - video input: this subnode can contain a video input port node + to connect the bridge to a LVDS output interface (See this + documentation [1]). + +Optional properties: + - split-mode: boolean. if this exists, split mode is enabled, + otherwise, single mode is enabled. + - reset-gpios: OF device-tree gpio specification for SYSRSTN pin. + +[1]: Documentation/devicetree/bindings/media/video-interfaces.txt + +Example: + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file mode 100644 index 00000000000000..eb01083da4908e --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml @@ -0,0 +1,163 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Northwest Logic MIPI-DSI controller on i.MX SoCs + +maintainers: + - Guido Gúnther + - Robert Chiras + +description: | + NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for + the SOCs NWL MIPI-DSI host controller. + +properties: + compatible: + const: fsl,imx8mq-nwl-dsi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: DSI core clock + - description: RX_ESC clock (used in escape mode) + - description: TX_ESC clock (used in escape mode) + - description: PHY_REF clock + - description: VIDEO_PLL clock + - description: PHY_PARENT clock (optional) + + clock-names: + items: + - const: core + - const: rx_esc + - const: tx_esc + - const: phy_ref + - const: video_pll + - const: phy_parent + + mux-controls: + description: + mux controller node to use for operating the input mux + + phys: + maxItems: 1 + description: + A phandle to the phy module representing the DPHY + + phy-names: + items: + - const: dphy + + power-domains: + maxItems: 1 + description: + A phandle to the power domain + + resets: + description: + phandles to the reset controller + items: + - description: dsi byte reset line + - description: dsi dpi reset line + - description: dsi esc reset line + - description: dsi pclk reset line + + reset-names: + items: + - const: byte + - const: dpi + - const: esc + - const: pclk + + ports: + type: object + description: + A node containing DSI input & output port nodes with endpoint + definitions as documented in + Documentation/devicetree/bindings/graph.txt. + + port@0: + type: object + description: + Input port node to receive pixel data from the + display controller + + port@1: + type: object + description: + DSI output port node to the panel or the next bridge + in the chain + + fsl,clock-drop-level: + description: + Specifies the level at wich the crtc_clock should be dropped + +patternProperties: + "^panel@[0-9]+$": true + +required: + - clock-names + - clocks + - compatible + - interrupts + - mux-controls + - phy-names + - phys + - ports + - reg + - reset-names + - resets + +examples: + - | + + mipi_dsi: mipi_dsi@30a00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mq-nwl-dsi"; + reg = <0x30A00000 0x300>; + clocks = <&clk 163>, <&clk 244>, <&clk 245>, <&clk 164>; + clock-names = "core", "rx_esc", "tx_esc", "phy_ref"; + interrupts = <0 34 4>; + mux-controls = <&mux 0>; + power-domains = <&pgc_mipi>; + resets = <&src 0>, <&src 1>, <&src 2>, <&src 3>; + reset-names = "byte", "dpi", "esc", "pclk"; + phys = <&dphy>; + phy-names = "dphy"; + + panel@0 { + compatible = "rocktech,jh057n00900"; + reg = <0>; + port@0 { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mipi_dsi_in: endpoint { + remote-endpoint = <&lcdif_mipi_dsi>; + }; + }; + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt b/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt new file mode 100644 index 00000000000000..fd4246136d3723 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt @@ -0,0 +1,60 @@ +Samsung MIPI DSIM bridge bindings + +The MIPI DSIM host controller drives the video signals from +display controller to video peripherals using DSI protocol. +This is an un-managed DSI bridge. In order to use this bridge, +an encoder or bridge must be implemented to manage the platform +specific initializations. + +Required properties: +- compatible: "fsl,imx8mm-mipi-dsim" +- reg: the register range of the MIPI DSIM controller +- interrupts: the interrupt number for this module +- clock, clock-names: phandles to the MIPI-DSI clocks described in + Documentation/devicetree/bindings/clock/clock-bindings.txt + "cfg" - DSIM access clock + "pll-ref" - DSIM PHY PLL reference clock +- assigned-clocks: phandles to clocks that requires initial configuration +- assigned-clock-rates: rates of the clocks that requires initial configuration +- pref-clk: Assign DPHY PLL reference clock frequency. If not exists, + DSIM bridge driver will use the default lock frequency + which is 27MHz. +- port: input and output port nodes with endpoint definitions as + defined in Documentation/devicetree/bindings/graph.txt; + the input port should be connected to an encoder or a + bridge that manages this MIPI DSIM host and the output + port should be connected to a panel or a bridge input + port + +Optional properties: +-dsi-gpr: a phandle which provides the MIPI DSIM control and gpr registers + +example: + mipi_dsi: mipi_dsi@32E10000 { + compatible = "fsl,imx8mm-mipi-dsim"; + reg = <0x0 0x32e10000 0x0 0x400>; + clocks = <&clk IMX8MM_CLK_DSI_CORE_DIV>, + <&clk IMX8MM_CLK_DSI_PHY_REF_DIV>; + clock-names = "cfg", "pll-ref"; + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE_SRC>, + <&clk IMX8MM_CLK_DSI_PHY_REF_SRC>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_VIDEO_PLL1_OUT>; + assigned-clock-rates = <266000000>, <594000000>; + interrupts = ; + dsi-gpr = <&dispmix_gpr>; + status = "disabled"; + + port@0 { + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + }; + }; + + }; diff --git a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt index 5bf77f6dd19db0..21cc79a3528f1b 100644 --- a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt +++ b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt @@ -110,6 +110,289 @@ prg@21cc000 { fsl,pres = <&pre1>, <&pre2>, <&pre3>; }; +Freescale i.MX DPU +==================== + +Required properties: +- compatible: Should be "fsl,-dpu" +- reg: should be register base and length as documented in the + datasheet +- interrupt-parent: phandle pointing to the parent interrupt controller. +- interrupts, interrupt-names: Should contain interrupts and names as + documented in the datasheet. +- clocks, clock-names: phandles to the DPU clocks described in + Documentation/devicetree/bindings/clock/clock-bindings.txt + The following clocks are expected on i.MX8qxp: + "pll0" - PLL clock for display interface 0 + "pll1" - PLL clock for display interface 1 + "disp0" - pixel clock for display interface 0 + "disp1" - pixel clock for display interface 1 + The needed clock numbers for each are documented in + Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt. +- power-domains: phandles pointing to power domain. +- power-domain-names: power domain names relevant to power-domains phandles. +- fsl,dpr-channels: phandles to the DPR channels attached to this DPU, + sorted by memory map addresses. +- fsl,pixel-combiner: phandle to the pixel combiner unit attached to this DPU. +Optional properties: +- port@[0-1]: Port nodes with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + ports 0 and 1 should correspond to display interface 0 and + display interface 1, respectively. + +example: + +dpu: dpu@56180000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-dpu"; + reg = <0x56180000 0x40000>; + interrupt-parent = <&irqsteer_dpu>; + interrupts = <448>, <449>, <450>, <64>, + <65>, <66>, <67>, <68>, + <69>, <70>, <193>, <194>, + <195>, <196>, <197>, <72>, + <73>, <74>, <75>, <76>, + <77>, <78>, <79>, <80>, + <81>, <199>, <200>, <201>, + <202>, <203>, <204>, <205>, + <206>, <207>, <208>, <0>, + <1>, <2>, <3>, <4>, + <82>, <83>, <84>, <85>, + <209>, <210>, <211>, <212>; + interrupt-names = "store9_shdload", + "store9_framecomplete", + "store9_seqcomplete", + "extdst0_shdload", + "extdst0_framecomplete", + "extdst0_seqcomplete", + "extdst4_shdload", + "extdst4_framecomplete", + "extdst4_seqcomplete", + "extdst1_shdload", + "extdst1_framecomplete", + "extdst1_seqcomplete", + "extdst5_shdload", + "extdst5_framecomplete", + "extdst5_seqcomplete", + "disengcfg_shdload0", + "disengcfg_framecomplete0", + "disengcfg_seqcomplete0", + "framegen0_int0", + "framegen0_int1", + "framegen0_int2", + "framegen0_int3", + "sig0_shdload", + "sig0_valid", + "sig0_error", + "disengcfg_shdload1", + "disengcfg_framecomplete1", + "disengcfg_seqcomplete1", + "framegen1_int0", + "framegen1_int1", + "framegen1_int2", + "framegen1_int3", + "sig1_shdload", + "sig1_valid", + "sig1_error", + "cmdseq_error", + "comctrl_sw0", + "comctrl_sw1", + "comctrl_sw2", + "comctrl_sw3", + "framegen0_primsync_on", + "framegen0_primsync_off", + "framegen0_secsync_on", + "framegen0_secsync_off", + "framegen1_primsync_on", + "framegen1_primsync_off", + "framegen1_secsync_on", + "framegen1_secsync_off"; + clocks = <&dc_lpcg IMX_DC0_PLL0_CLK>, + <&dc_lpcg IMX_DC0_PLL1_CLK>, + <&dc_lpcg IMX_DC0_DISP0_CLK>, + <&dc_lpcg IMX_DC0_DISP1_CLK>; + clock-names = "pll0", "pll1", "disp0", "disp1"; + power-domains = <&pd IMX_SC_R_DC_0>, + <&pd IMX_SC_R_DC_0_PLL_0>, + <&pd IMX_SC_R_DC_0_PLL_1>; + power-domain-names = "dc", "pll0", "pll1"; + fsl,dpr-channels = <&dc0_dpr1_channel1>, <&dc0_dpr1_channel2>, + <&dc0_dpr1_channel3>, <&dc0_dpr2_channel1>, + <&dc0_dpr2_channel2>, <&dc0_dpr2_channel3>; + fsl,pixel-combiner = <&dc0_pc>; + + dpu_disp0: port@0 { + reg = <0>; + + dpu_disp0_lvds0_ch0: endpoint@0 { + remote-endpoint = <&ldb1_ch0>; + }; + + dpu_disp0_lvds0_ch1: endpoint@1 { + remote-endpoint = <&ldb1_ch1>; + }; + + dpu_disp0_mipi_dsi: endpoint@2 { + }; + }; + + dpu_disp1: port@1 { + reg = <1>; + + dpu_disp1_lvds1_ch0: endpoint@0 { + remote-endpoint = <&ldb2_ch0>; + }; + + dpu_disp1_lvds1_ch1: endpoint@1 { + remote-endpoint = <&ldb2_ch1>; + }; + + dpu_disp1_mipi_dsi: endpoint@2 { + }; + }; +}; + +Freescale i.MX8 PC (Pixel Combiner) +============================================= +Required properties: +- compatible: should be "fsl,-pixel-combiner" +- reg: should be register base and length as documented in the + datasheet +- power-domains: phandle pointing to power domain + +example: + +pixel-combiner@56020000 { + compatible = "fsl,imx8qm-pixel-combiner"; + reg = <0x56020000 0x10000>; + power-domains = <&pd IMX_SC_R_DC_0>; +}; + +Freescale i.MX8 PRG (Prefetch Resolve Gasket) +============================================= +Required properties: +- compatible: should be "fsl,-prg" +- reg: should be register base and length as documented in the + datasheet +- clocks: phandles to the PRG apb and rtram clocks, as described in + Documentation/devicetree/bindings/clock/clock-bindings.txt and + Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt. +- clock-names: should be "apb" and "rtram" +- power-domains: phandle pointing to power domain + +example: + +prg@56040000 { + compatible = "fsl,imx8qm-prg"; + reg = <0x56040000 0x10000>; + clocks = <&dc0_prg0_lpcg 0>, <&dc0_prg0_lpcg 1>; + clock-names = "apb", "rtram"; + power-domains = <&pd IMX_SC_R_DC_0>; +}; + +Freescale i.MX8 DPRC (Display Prefetch Resolve Channel) +======================================================= +Required properties: +- compatible: should be "fsl,-dpr-channel" +- reg: should be register base and length as documented in the + datasheet +- fsl,sc-resource: SCU resource number as defined in + include/dt-bindings/firmware/imx/rsrc.h +- fsl,prgs: phandles to the PRG unit(s) attached to this DPRC, the first one + is the primary PRG and the second one(if available) is the auxiliary PRG + which is used to fetch luma chunk of a YUV frame with 2 planars. +- clocks: phandles to the DPRC apb, b and rtram clocks, as described in + Documentation/devicetree/bindings/clock/clock-bindings.txt and + Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt. +- clock-names: should be "apb", "b" and "rtram" +- power-domains: phandle pointing to power domain + +example: + +dpr-channel@560e0000 { + compatible = "fsl,imx8qm-dpr-channel"; + reg = <0x560e0000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc0_prg2>, <&dc0_prg1>; + clocks = <&dc0_dpr0_lpcg 0>, + <&dc0_dpr0_lpcg 1>, + <&dc0_rtram0_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_0>; +}; + +LCDIF mux display support +========================= + +Required properties: +- compatible: Should be "fsl,imx-lcdif-mux-display" +- #address-cells : should be <1> +- #size-cells : should be <0> +- pinctrl-names : should be "default" +- pinctrl-0 : phandle pointing to parallel display pin settings +- clocks : phandle to the LCD pixel bypass divider clock and the LCD pixel clock + as described in Documentation/devicetree/bindings/clock/clock-bindings.txt and + Documentation/devicetree/bindings/clock/imx8qxp-clock.txt. +- clock-names: should be "bypass_div" and "pixel" +- assigned-clocks: phandle to the LCD pixel selector clock +- assigned-clock-parents: phandle to the LCD pixel bypass divider clock +- fsl,lcdif-mux-regs: should be <&lcdif_mux_regs> on i.MX8qxp. + The phandle points to a syscon region containing + LCDIF mux control register. +- power-domains: phandle pointing to power domain +- port@[0-1]: Port nodes with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + Port 0 is the input port connected to the DPU display interface, + port 1 is the output port connected to a panel or a bridge. +Optional properties: +- fsl,interface-pix-fmt: How this display is connected to the + display interface, can be "rgb565", "rgb666" and "rgb888". + +example: + +display@disp1 { + compatible = "fsl,imx-lcdif-mux-display"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; + clock-names = "bypass_div", "pixel"; + assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; + assigned-clock-parents = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>; + fsl,lcdif-mux-regs = <&lcdif_mux_regs>; + fsl,interface-pix-fmt = "rgb666"; + power-domains = <&pd IMX_SC_R_LCD_0>; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&dpu_disp1_lcdif>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; +}; + +panel { + ... + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; +}; + Parallel display support ======================== diff --git a/Documentation/devicetree/bindings/display/imx/ldb.txt b/Documentation/devicetree/bindings/display/imx/ldb.txt index 38c637fa39ddf4..4b0e768589296b 100644 --- a/Documentation/devicetree/bindings/display/imx/ldb.txt +++ b/Documentation/devicetree/bindings/display/imx/ldb.txt @@ -9,15 +9,24 @@ nodes describing each of the two LVDS encoder channels of the bridge. Required properties: - #address-cells : should be <1> - #size-cells : should be <0> - - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb". - Both LDB versions are similar, but i.MX6 has an additional - multiplexer in the front to select any of the four IPU display - interfaces as input for each LVDS channel. + - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb" or + "fsl,imx8qm-ldb" or "fsl,imx8qxp-ldb" or "fsl,imx8mp-ldb". + All LDB versions are similar. + i.MX6q/dl has an additional multiplexer in the front to select + any of the two or four IPU display interfaces as input for each + LVDS channel. + i.MX8qm LDB supports 10bit RGB input and needs an additional + phy. + i.MX8qxp and i.MX8mp LDB only supports one LVDS encoder + channel(either channel0 or channel1). - gpr : should be <&gpr> on i.MX53 and i.MX6q. The phandle points to the iomuxc-gpr region containing the LVDS control register. + - fsl,auxldb : phandle to auxiliary LDB which is used in dual channel mode. + Only required by i.MX8qxp. - clocks, clock-names : phandles to the LDB divider and selector clocks and to - the display interface selector clocks, as described in + the display interface selector clocks or pixel and + bypass clocks as described in Documentation/devicetree/bindings/clock/clock-bindings.txt The following clocks are expected on i.MX53: "di0_pll" - LDB LVDS channel 0 mux @@ -29,14 +38,27 @@ Required properties: On i.MX6q the following additional clocks are needed: "di2_sel" - IPU2 DI0 mux "di3_sel" - IPU2 DI1 mux + The following clocks are expected on i.MX8qm and i.MX8qxp: + "pixel" - pixel clock + "bypass" - bypass clock + The following clocks are expected on i.MX8qxp: + "aux_pixel" - auxiliary pixel clock in dual channel mode + "aux_bypass" - auxiliary bypass clock in dual channel mode + The following clocks are expected on i.MX8mp: + "ldb" - ldb root clock The needed clock numbers for each are documented in Documentation/devicetree/bindings/clock/imx5-clock.txt, and in - Documentation/devicetree/bindings/clock/imx6q-clock.txt. + Documentation/devicetree/bindings/clock/imx6q-clock.txt, and in + Documentation/devicetree/bindings/clock/imx8qm-lpcg.txt, and in + Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt. +- power-domains : phandle pointing to power domain, only required by i.MX8qm and + i.MX8qxp. Optional properties: - - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q + - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q, i.MX8qm + i.MX8qxp and i.MX8mp - pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53, - not used on i.MX6q + not used on i.MX6q, i.MX8qm, i.MX8qxp and i.MX8mp - fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should be configured - one input will be distributed on both outputs in dual channel mode @@ -57,9 +79,16 @@ Required properties: (lvds-channel@[0,1], respectively). On i.MX6, there should be four input ports (port@[0-3]) that correspond to the four LVDS multiplexer inputs. - A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected - to a panel input port. Optionally, the output port can be left out if - display-timings are used instead. + On i.MX8qm, the two channels of LDB connect to one display interface of DPU. + On i.MX8mp, the two channels of LDB connect to LCDIFv3. + A single output port (port@2 on i.MX5, port@4 on i.MX6, port@1 on i.MX8qm, + i.MX8qxp and i.MX8mp) must be connected to a panel input port or a bridge + input port. + Optionally, the output port can be left out if display-timings are used + instead. + - phys: the phandle for the LVDS PHY device. Valid only on i.MX8qm, i.MX8qxp + and i.MX8mp. + - phy-names: should be "ldb_phy". Valid only on i.MX8qm, i.MX8qxp and i.MX8mp. Optional properties (required if display-timings are used): - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing @@ -69,6 +98,7 @@ Optional properties (required if display-timings are used): This describes how the color bits are laid out in the serialized LVDS signal. - fsl,data-width : should be <18> or <24> + Additionally, <30> for i.MX8qm. example: diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml new file mode 100644 index 00000000000000..04a8a3e21c7ba3 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 NXP +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: iMX8MQ Display Controller Subsystem (DCSS) + +maintainers: + - Laurentiu Palcu + +description: + + The DCSS (display controller sub system) is used to source up to three + display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP + 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10 + image processing capabilities are included to provide a solution capable of + driving next generation high dynamic range displays. + +properties: + compatible: + const: nxp,imx8mq-dcss + + reg: + maxItems: 2 + + interrupts: + maxItems: 3 + items: + - description: Context loader completion and error interrupt + - description: DTG interrupt used to signal context loader trigger time + - description: DTG interrupt for Vblank + + interrupt-names: + maxItems: 3 + items: + - const: ctx_ld + - const: ctxld_kick + - const: vblank + - const: dtrc_ch1 + - const: dtrc_ch2 + + clocks: + maxItems: 5 + items: + - description: Display APB clock for all peripheral PIO access interfaces + - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL + - description: RTRAM clock + - description: Pixel clock, can be driver either by HDMI phy clock or MIPI + - description: DTRC clock, needed by video decompressor + - description: PLL source clock, usually VIDEO2_PLL, used when output is HDMI; + - description: PLL PHY reference clock, used when output is HDMI; + + clock-names: + items: + - const: apb + - const: axi + - const: rtrm + - const: pix + - const: dtrc + - const: pll_src + - const: pll_phy_ref + + port@0: + type: object + description: A port node pointing to a hdmi_in or mipi_in port node. + +examples: + - | + dcss: display-controller@32e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mq-dcss"; + reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>; + interrupts = <6>, <8>, <9>, <16>, <17>; + interrupt-names = "ctx_ld", "ctxld_kick", "vblank", "dtrc_ch1", "dtrc_ch2"; + interrupt-parent = <&irqsteer>; + clocks = <&clk 248>, <&clk 247>, <&clk 249>, + <&clk 254>,<&clk 122>, <&clk 266>, <&clk 267>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc", + "pll_src", "pll_phy_ref"; + assigned-clocks = <&clk 107>, <&clk 109>, <&clk 266>; + assigned-clock-parents = <&clk 78>, <&clk 78>, <&clk 3>; + assigned-clock-rates = <800000000>, + <400000000>; + port@0 { + dcss_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/display/mxsfb.txt b/Documentation/devicetree/bindings/display/mxsfb.txt index 472e1ea6c591e8..c8dca5051066c2 100644 --- a/Documentation/devicetree/bindings/display/mxsfb.txt +++ b/Documentation/devicetree/bindings/display/mxsfb.txt @@ -14,6 +14,11 @@ Required properties: - "pix" for the LCDIF block clock - (MX6SX-only) "axi", "disp_axi" for the bus interface clock +Optional properties: +- max-memory-bandwidth: maximum bandwidth in bytes per second that the + controller can handle; if not present, the memory + interface is fast enough to handle all possible video modes + Required sub-nodes: - port: The connection to an encoder chip. diff --git a/Documentation/devicetree/bindings/display/panel/jdi,tx26d202vm0bwa.txt b/Documentation/devicetree/bindings/display/panel/jdi,tx26d202vm0bwa.txt new file mode 100644 index 00000000000000..b245b4d68d0f51 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/jdi,tx26d202vm0bwa.txt @@ -0,0 +1,9 @@ +Japan Display Inc. 10.1" WUXGA (1920x1200) TFT LCD panel + +The panel has dual LVDS channels. + +Required properties: +- compatible: should be "jdi,tx26d202vm0bwa" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt b/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt new file mode 100644 index 00000000000000..8fe82ce6363274 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt @@ -0,0 +1,82 @@ +* Freescale enhanced Direct Memory Access(eDMA-v3) Controller + + The eDMA-v3 controller is inherited from FSL eDMA, and firstly is intergrated + on Freescale i.MX8QM SOC chip. The eDMA channels have multiplex capability by + programmble memory-mapped registers. Specific DMA request source has fixed channel. + +* eDMA Controller +Required properties: +- compatible : + - "fsl,imx8qm-edma" for eDMA used similar to that on i.MX8QM SoC + - "fsl,imx8qm-adma" for audio eDMA used on i.MX8QM +- reg : Specifies base physical address(s) and size of the eDMA channel registers. + Each eDMA channel has separated register's address and size. +- interrupts : A list of interrupt-specifiers, each channel has one interrupt. +- interrupt-names : Should contain below template: + "edmaX-chanX-Xx" + | | |---> receive/transmit, r or t + | |---> channel id, the max number is 32 + |---> edma controller instance, 0, 1, 2,..etc + +- #dma-cells : Must be <3>. + The 1st cell specifies the channel ID. + The 2nd cell specifies the channel priority. + The 3rd cell specifies the channel attributes which include below: + BIT(0): transmit or receive: + 0: transmit, 1: receive. + BIT(1): local or remote access: + 0: local, 1: remote. + BIT(2): dualfifo case or not(only in Audio cyclic now): + 0: not dual fifo case, 1: dualfifo case. + See the SoC's reference manual for all the supported request sources. +- dma-channels : Number of channels supported by the controller +- power-domains: Power domains for edma channel used. +- power-domain-names: Power domains name for edma channel used. + +Examples: +edma0: dma-controller@40018000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */ + <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */ + <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */ + <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */ + #dma-cells = <3>; + dma-channels = <4>; + interrupts = , + , + , + ; + interrupt-names = "edma0-chan12-rx", "edma0-chan13-tx", + "edma0-chan14-rx", "edma0-chan15-tx"; + power-domains = <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>; + power-domain-names = "edma0-chan12", "edma0-chan13", + "edma0-chan14", "edma0-chan15"; + status = "okay"; +}; + +* DMA clients +DMA client drivers that uses the DMA function must use the format described +in the dma.txt file, using a three-cell specifier for each channel: the 1st +specifies the channel number, the 2nd specifies the priority, and the 3rd +specifies the channel type is for transmit or receive: 0: transmit, 1: receive. + +Examples: +lpuart1: serial@5a070000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a070000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_UART1_CLK>; + clock-names = "ipg"; + assigned-clock-names = <&clk IMX8QM_UART1_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd IMX_SC_R_UART_1>, + power-domain-names = "uart"; + dma-names = "tx","rx"; + dmas = <&edma0 15 0 0>, + <&edma0 14 0 1>; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/dma/fsl-edma.txt b/Documentation/devicetree/bindings/dma/fsl-edma.txt index 29dd3ccb1235c5..e77b08ebcd0650 100644 --- a/Documentation/devicetree/bindings/dma/fsl-edma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-edma.txt @@ -10,6 +10,7 @@ Required properties: - compatible : - "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC - "fsl,imx7ulp-edma" for eDMA2 used similar to that on i.mx7ulp + - "fsl,fsl,ls1028a-edma" for eDMA used similar to that on Vybrid vf610 SoC - reg : Specifies base physical address(s) and size of the eDMA registers. The 1st region is eDMA control register's address and size. The 2nd and the 3rd regions are programmable channel multiplexing diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt index 7bd8847d6394e6..d10a9c1d2ce676 100644 --- a/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt @@ -16,6 +16,21 @@ Optional properties: - #dma-channels : Number of DMA channels supported. Should be 16. - #dma-requests : Number of DMA requests supported. +* DMA capability limitation + +Specify the DMA capability limitations. +For example, some SoCs only support up to 32bit DMA capability, although +they are 64bit SoCs. + +- only-dma-mask32: 1 means that the SoCs only suppot up to 32bit DMA + capability. + +Example: + dma_cap: dma_cap { + compatible = "dma-capability"; + only-dma-mask32 = <1>; + }; + Example: dma: dma@10001000 { diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt index 9d8bbac27d8b9d..ebbf7cfb12418a 100644 --- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt @@ -9,6 +9,8 @@ Required properties: "fsl,imx53-sdma" "fsl,imx6q-sdma" "fsl,imx7d-sdma" + "fsl,imx6sx-sdma" + "fsl,imx6ul-sdma" "fsl,imx8mq-sdma" The -to variants should be preferred since they allow to determine the correct ROM script addresses needed for the driver to work without additional @@ -51,8 +53,14 @@ The full ID of peripheral types can be found below. 22 SSI Dual FIFO (needs firmware ver >= 2) 23 Shared ASRC 24 SAI + 25 HDMI Audio -The third cell specifies the transfer priority as below. +The third cell specifies the transfer priority and software done +as below. + + Bit31: sw_done + Bit15~Bit8: selector + Bit7~Bit0: priority level ID transfer priority ------------------------- @@ -60,6 +68,9 @@ The third cell specifies the transfer priority as below. 1 Medium 2 Low +For example: 0x80000000 means sw_done enabled for done0 sector and + High priority for PDM on i.mx8mm. + Optional properties: - gpr : The phandle to the General Purpose Register (GPR) node. diff --git a/Documentation/devicetree/bindings/gpio/gpio-imx-rpmsg.txt b/Documentation/devicetree/bindings/gpio/gpio-imx-rpmsg.txt new file mode 100644 index 00000000000000..25001da92da53a --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-imx-rpmsg.txt @@ -0,0 +1,57 @@ +Device-Tree bindings for drivers/gpio/gpio-imx-rpmsg.c gpio driver over +rpmsg. On i.mx7ULP PTA PTB are connected on M4 side, so rpmsg gpio driver +needed to get/set gpio status from M4 side by rpmsg. + +Required properties: +- compatible : Should be "fsl,imx-rpmsg-gpio". +- port_idx : Specify the GPIO PORT index, PTA:0, PTB:1. +- gpio-controller : Mark the device node as a gpio controller. +- #gpio-cells : Should be two. The first cell is the pin number and + the second cell is used to specify the gpio polarity: + 0 = active high + 1 = active low +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells : Should be 2. The first cell is the GPIO number. + The second cell bits[3:0] is used to specify trigger type and level flags: + 1 = low-to-high edge triggered. + 2 = high-to-low edge triggered. + 4 = active high level-sensitive. + 8 = active low level-sensitive. + +Note: Each GPIO port should have an alias correctly numbered in "aliases" +node. + +Examples: + +aliases { + gpio4 = &rpmsg_gpio0; + gpio5 = &rpmsg_gpio1; +}; + +rpmsg_gpio0: rpmsg-gpio0 { + compatible = "fsl,imx-rpmsg-gpio"; + port_idx = <0>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&rpmsg_gpio0>; + status = "okay"; +}; + +rpmsg_gpio1: rpmsg-gpio1 { + compatible = "fsl,imx-rpmsg-gpio"; + port_idx = <1>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&rpmsg_gpio1>; + status = "okay"; +}; + +&skeleton_node { + interrupt-parent = <&rpmsg_gpio1>; + interrupts = <7 2>; + wakeup-gpios = <&rpmsg_gpio1 7 GPIO_ACTIVE_LOW>; +}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-max732x.txt b/Documentation/devicetree/bindings/gpio/gpio-max732x.txt index b3a9c0c3282319..7f09979c047f89 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-max732x.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-max732x.txt @@ -31,6 +31,7 @@ Optional properties: - first cell is the pin number - second cell is used to specify flags - interrupts: Interrupt specifier for the controllers interrupt. + - out-default: set the output IO default voltage. Exp: out-default = /bits/ 16 ; Please refer to gpio.txt in this directory for details of the common GPIO bindings used by client devices. diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt index 30ac6a60f04195..7abda506b82861 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt @@ -25,6 +25,8 @@ Required Properties: Optional Properties: - reset-gpios: Reference to the GPIO connected to the reset input. + - idle-state: if present, overrides i2c-mux-idle-disconnect, + Please refer to Documentation/devicetree/bindings/mux/mux-controller.txt - i2c-mux-idle-disconnect: Boolean; if defined, forces mux to disconnect all children in idle state. This is necessary for example, if there are several multiplexers on the bus and the devices behind them use same I2C addresses. diff --git a/Documentation/devicetree/bindings/i2c/i2c-rpmsg-imx.txt b/Documentation/devicetree/bindings/i2c/i2c-rpmsg-imx.txt new file mode 100644 index 00000000000000..fce660d0f179d3 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-rpmsg-imx.txt @@ -0,0 +1,29 @@ +* Freescale Virtual I2C RPMSG bus driver for i.MX + +Required properties: +- compatible : + - "fsl,i2c-rpbus" for I2C bus over RPMSG compatible on i.MX8QXP/QM soc +The i2c-rpbus node should define its bus id (which is the node communicating +with M4) in alias. + +Examples: + +aliases { + ... + i2c1 = &i2c_rpbus_1; + ... +}; + +&i2c_rpbus_1 { + compatible = "fsl,i2c-rpbus"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + devs_in_this_i2c_bus__for_example: pca6416@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-xen.txt b/Documentation/devicetree/bindings/i2c/i2c-xen.txt new file mode 100644 index 00000000000000..26864a15c1b5bc --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-xen.txt @@ -0,0 +1,14 @@ +* XEN frontend i2c controller + +Required properties: +- compatible : + - "xen,i2c" for xen i2c frontend +- be-adapter : the backend i2c adapter name + +Examples: + +xen_i2c0: xen_i2c@0 { + compatible = "xen,i2c"; + be-adapter = "5a800000.i2c"; + status = "okay"; +}; diff --git a/Documentation/devicetree/bindings/input/imx-sc-pwrkey.txt b/Documentation/devicetree/bindings/input/imx-sc-pwrkey.txt new file mode 100644 index 00000000000000..1084baa48d4fe4 --- /dev/null +++ b/Documentation/devicetree/bindings/input/imx-sc-pwrkey.txt @@ -0,0 +1,22 @@ +Device-Tree bindings for input/keyboard/imx_sc_pwrkey.c poweron/off driver +over SCU. On i.mx8QM/QXP poweron/off key is connected on SCU side, so need +to get key event by MU. + +Required properties: + - compatible = "fsl,imx8-pwrkey"; + +Each button/key looked as the sub node: +Required properties: + - linux,code: the key value defined in + include/dt-bindings/input/input.h +Optional property: + - wakeup-source: wakeup feature, the keys can wakeup from + suspend if the keys with this property pressed. + +Example nodes: + sc_pwrkey: sc-powerkey { + compatible = "fsl,imx8-pwrkey"; + linux,keycode = ; + wakeup-source; + }; + diff --git a/Documentation/devicetree/bindings/input/rpmsg-keys.txt b/Documentation/devicetree/bindings/input/rpmsg-keys.txt new file mode 100644 index 00000000000000..d9279802cc9cbc --- /dev/null +++ b/Documentation/devicetree/bindings/input/rpmsg-keys.txt @@ -0,0 +1,33 @@ +Device-Tree bindings for input/keyboard/rpmsg-keys.c keys driver over +rpmsg. On i.mx7ULP keys are connected on M4 side, so rpmsg-keys driver +needed to get the key status from M4 side by rpmsg. + +Required properties: + - compatible = "fsl,rpmsg-keys"; + +Each button/key looked as the sub node: +Required properties: + - label: the key name + - linux,code: the key value defined in + include/dt-bindings/input/input.h +Optional property: + - rpmsg-key,wakeup: wakeup feature, the keys can wakeup from + suspend if the keys with this property pressed. + +Example nodes: + rpmsg_keys: rpmsg-keys { + compatible = "fsl,rpmsg-keys"; + + volume-up { + label = "Volume Up"; + rpmsg-key,wakeup; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + rpmsg-key,wakeup; + linux,code = ; + }; + }; + diff --git a/Documentation/devicetree/bindings/input/touchscreen/focaltech-ts.txt b/Documentation/devicetree/bindings/input/touchscreen/focaltech-ts.txt new file mode 100644 index 00000000000000..8e5257db88f6f0 --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/focaltech-ts.txt @@ -0,0 +1,48 @@ +FocalTech touch controller + +The focaltech controller is connected to host processor via i2c. +The controller generates interrupts when the user touches the panel. +The host controller is expected to read the touch coordinates over +i2c and pass the coordinates to the rest of the system. + +Required properties: + - compatible : should be "focaltech,fts" + - reg : i2c slave address of the device, should be <0x38> + - interrupt-parent : parent of interrupt + - interrupts : irq gpio, "0x02" stands for that the irq triggered by falling edge. + - focaltech,irq-gpio : irq gpio, same as "interrupts" node. + - focaltech,reset-gpio : reset gpio + - focaltech,num-max-touches : maximum number of touches support + - focaltech,display-coords : display resolution in pixels. A four tuple consisting of minX, minY, maxX and maxY. + +Optional properties: + - focaltech,have-key : specify if virtual keys are supported + - focaltech,key-number : number of keys + - focaltech,keys : virtual key codes mapping to the coords + - focaltech,key-y-coord : constant y coordinate of keys, depends on the y resolution + - focaltech,key-x-coords : constant x coordinates of keys, depends on the x resolution + - focaltech,swap-xy : swap x-y coordinates + - focaltech,panel-type : set panel type, default is FT5416 panel + - focaltech,scaling-down-half : scale down the x-y coordiantes to half + + +Example: + i2c@f9927000 { + focaltech@38{ + compatible = "focaltech,fts"; + reg = <0x38>; + interrupt-parent = <&msm_gpio>; + interrupts = <13 0x02>; + focaltech,reset-gpio = <&msm_gpio 12 0x01>; + focaltech,irq-gpio = <&msm_gpio 13 0x02>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 1920>; + + focaltech,have-key; + focaltech,key-number = <3>; + focaltech,keys = <139 102 158>; + focaltech,key-y-coord = <2000>; + focaltech,key-x-coords = <200 600 800>; + focaltech,swap-xy; + }; + }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/vtl_ts.txt b/Documentation/devicetree/bindings/input/touchscreen/vtl_ts.txt new file mode 100644 index 00000000000000..a41a0b9930064f --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/vtl_ts.txt @@ -0,0 +1,18 @@ +* VTL Touchscreen Controller + +Required properties: +- compatible: must be "vtl,ct365" +- reg: i2c slave address +- interrupt-parent: the phandle for the interrupt controller +- interrupts: touch controller interrupt +- gpios: the gpio pin to be used for reset + +Example: + + touchscreen@01 { + compatible = "vtl,ct365"; + reg = <0x01>; + interrupt-parent = <&gpio6>; + interrupts = <14 0>; + gpios = <&gpio4 10 0>; + }; diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt index f3cf77eb5ab41c..2dd64b63b10ccf 100644 --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt @@ -21,6 +21,10 @@ Required properties: imx6sx, imx7s, imx8qxp, imx8qm. The "fsl,imx6sx-mu" compatible is seen as generic and should be included together with SoC specific compatible. + There is a version 1.0 MU on imx7ulp, use "fsl,imx7ulp-mu" + compatible to support it. + To communicate with i.MX8 SCU, "fsl,imx8-mu-seco" could be + used for fast IPC - reg : Should contain the registers location and length - interrupts : Interrupt number. The interrupt specifier format depends on the interrupt controller parent. @@ -52,3 +56,10 @@ lsio_mu0: mailbox@5d1b0000 { interrupts = ; #mbox-cells = <2>; }; +sec_mu0: mailbox@31560000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x31560000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_SECO_MU_2>; +}; diff --git a/Documentation/devicetree/bindings/media/imx8-isi.txt b/Documentation/devicetree/bindings/media/imx8-isi.txt new file mode 100644 index 00000000000000..7739121f0ca68f --- /dev/null +++ b/Documentation/devicetree/bindings/media/imx8-isi.txt @@ -0,0 +1,33 @@ +NXP Image Sensor Interface +======================== + +The Image Sensor Interface (ISI) is used to obtain the image data for +processing in its pipeline channels. Each pipeline processes the image +line from a configured source and performs one or more functions that +are configured by software, such as down scaling, color space conversion, +de-interlacing, alpha insertion, cropping and rotation (horizontal and +vertical). The processed image is stored into programmable memory locations. + +Required properties: +- compatible: should be "fsl,imx8-isi", where SoC can be one of imx8qxp, imx8qm +- reg: the register base and size for the device registers +- interrupts: the ISI interrupt, high level active +- clock-names: should be "per" +- clocks: the ISI AXI clock +- interface: specify ISI input, virtual channel and output, + + Input : 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM + VCx : 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only + Output: 0-DC0, 1-DC1, 2-MEM + +Example: + isi_0: isi@58100000 { + compatible = "fsl,imx8-isi"; + reg = <0x58100000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&img_lpcg IMX_IMG_LPCG_PDMA0_CLK>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + interface = <2 0 2>; + }; diff --git a/Documentation/devicetree/bindings/media/imx8-jpeg.txt b/Documentation/devicetree/bindings/media/imx8-jpeg.txt new file mode 100644 index 00000000000000..16b01daa7a2a97 --- /dev/null +++ b/Documentation/devicetree/bindings/media/imx8-jpeg.txt @@ -0,0 +1,107 @@ +Freescale i.MX8QXP/QM JPEG encoder/decoder +========================= + +jpegdec node +-------------- + +This is the device node for the JPEG decoder in i.MXQXP/QM SoC, an +ISO/IEC 10918-1 JPEG standard compliant decoder, for Baseline +and Extended Sequential DCT modes. + +Required properties: + +- compatible : "fsl,imx8-jpgdec"; +- reg : base address and length of the register set for the device; +- interrupts : list of interrupts for jpeg decoder +- clocks : list of clock specifiers, see + Documentation/devicetree/bindings/clock/clock-bindings.txt for details; +- assigned-clock-rates : the value should be 200MHz; +- power-domains : a list of phandle to the power domain, see + Documentation/devicetree/bindings/power/power_domain.txt for details; + + +Optional properties: +- clock-names : must contain clock names to match entries in the + clock property; +- power-domain-name : must contain matching names for entries in the + the power-domains property. + + +example: + + jpegdec: jpegdec@58400000 { + compatible = "fsl,imx8-jpgdec"; + reg = <0x58400000 0x00050000 >; + interrupts = , + , + , + ; + clocks = <&img_jpeg_dec_clk 0>, + <&img_jpeg_dec_clk 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&img_jpeg_dec_clk 0>, + <&img_jpeg_dec_clk 1>; + assigned-clock-rates = <200000000>; + power-domains = <&pd IMX_SC_R_ISI_CH0>, + <&pd IMX_SC_R_MJPEG_DEC_MP>, + <&pd IMX_SC_R_MJPEG_DEC_S0>, + <&pd IMX_SC_R_MJPEG_DEC_S1>, + <&pd IMX_SC_R_MJPEG_DEC_S2>, + <&pd IMX_SC_R_MJPEG_DEC_S3>; + power-domain-names = "pd_isi_ch0", "pd_dec_mp", + "pd_dec_s0", "pd_dec_s1", + "pd_dec_s2", "pd_dec_s3"; + status = "disabled"; + + +jpegenc node +-------------- + +This is the device node for the JPEG encoder in i.MXQXP/QM SoC, +similar with the JPEG decoder above. + +Required properties: + +- compatible : "fsl,imx8-jpgenc"; +- reg : base address and length of the register set for the device; +- interrupts : list of interrupts for jpeg encoder +- clocks : list of clock specifiers, see + Documentation/devicetree/bindings/clock/clock-bindings.txt for details; +- assigned-clock-rates : the value should be 200MHz; +- power-domains : a list of phandle to the power domain, see + Documentation/devicetree/bindings/power/power_domain.txt for details; + + +Optional properties: +- clock-names : must contain clock names to match entries in the + clock property; +- power-domain-name : must contain matching names for entries in the + the power-domains property. + + +example: + + jpegenc: jpegenc@58450000 { + compatible = "fsl,imx8-jpgenc"; + reg = <0x58450000 0x00050000 >; + interrupts = , + , + , + ; + clocks = <&img_jpeg_enc_clk 0>, + <&img_jpeg_enc_clk 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&img_jpeg_enc_clk 0>, + <&img_jpeg_enc_clk 1>; + assigned-clock-rates = <200000000>; + power-domains = <&pd IMX_SC_R_ISI_CH0>, + <&pd IMX_SC_R_MJPEG_ENC_MP>, + <&pd IMX_SC_R_MJPEG_ENC_S0>, + <&pd IMX_SC_R_MJPEG_ENC_S1>, + <&pd IMX_SC_R_MJPEG_ENC_S2>, + <&pd IMX_SC_R_MJPEG_ENC_S3>; + power-domain-names = "pd_isi_ch0", "pd_enc_mp", + "pd_enc_s0", "pd_enc_s1", + "pd_enc_s2", "pd_enc_s3"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/media/imx8-media-dev.txt b/Documentation/devicetree/bindings/media/imx8-media-dev.txt new file mode 100644 index 00000000000000..dd7de1cbde445c --- /dev/null +++ b/Documentation/devicetree/bindings/media/imx8-media-dev.txt @@ -0,0 +1,38 @@ +Virtual Media device +------------------------------- + +Virtual Media device is used to manage all modules in image capture subsystem +of imx8qxp/qm platform. ISI(Image Sensor Interface), MIPI CSI, Parallel CSI +device node should be under it. + +Required properties: + - compatible : must be "fsl,mxc-md"; + - reg : Must contain an entry for each entry in reg-names; + - #address-cells: should be <1>; + - #size-cells : should be <1>; + - ranges : use to handle address space + +Optional properties: + - parallel_csi: indicate that camera sensor use parallel interface + + + +For example: + + cameradev: camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + isi@58100000 { + compatible = "fsl,imx8-isi"; + reg = <0x58100000 0x10000>; + ... + }; + csi@58227000 { + compatible = "fsl,mxc-mipi-csi2"; + ... + }; + ... + }; diff --git a/Documentation/devicetree/bindings/media/imx8-mipi-csi.txt b/Documentation/devicetree/bindings/media/imx8-mipi-csi.txt new file mode 100644 index 00000000000000..3c69e3e52b8c7a --- /dev/null +++ b/Documentation/devicetree/bindings/media/imx8-mipi-csi.txt @@ -0,0 +1,73 @@ +Freescale i.MX8QXP/QM MIPI CSI2 +========================= + +mipi_csi2 node +-------------- + +This is the device node for the MIPI CSI-2 receiver core in i.MXQXP/QM SoC. + +Required properties: + +- compatible : "fsl,mxc-mipi-csi2"; +- reg : base address and length of the register set for the device; +- clocks : list of clock specifiers, see + Documentation/devicetree/bindings/clock/clock-bindings.txt for details; +- clock-names : must contain "clk_core", "clk_esc" and "clk_pxl" entries, + matching entries in the clock property; +- assigned-clock-rates : the value should be 360MHz and 72MHz; +- power-domains : a phandle to the power domain, see + Documentation/devicetree/bindings/power/power_domain.txt for details; +- power-domain-name : must contain "pd_csi", "pd_isi_ch0". + +Optional properties: +- virtual-channel: whether use mipi csi virtual channel + +The device node should contain one 'port' child nodes with one child 'endpoint' +node, according to the bindings defined in: + Documentation/devicetree/bindings/ media/video-interfaces.txt. + The following are properties specific to those nodes. + +port node +--------- + +- reg : (required) can take the values 0 which mean the port is a + sink port; + +endpoint node +------------- + +- data-lanes : (required) an array specifying active physical MIPI-CSI2 + data input lanes and their mapping to logical lanes; this + shall only be applied to port 0 (sink port), the array's + content is unused only its length is meaningful, + in this case the maximum length supported is 2; + +example: + + mipi_csi: csi@58227000 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "fsl,mxc-mipi-csi2"; + reg = <0x58227000 0x1000>, + <0x58221000 0x1000>; + clocks = <&csi_lpcg IMX_CSI_LPCG_CSI0_CORE_CLK>, + <&csi_lpcg IMX_CSI_LPCG_CSI0_ESC_CLK>, + <&img_lpcg IMX_IMG_LPCG_CSI0_PXL_LINK_CLK>; + clock-names = "clk_core", "clk_esc", "clk_pxl"; + assigned-clocks = <&csi_lpcg IMX_CSI_LPCG_CSI0_CORE_CLK>, + <&csi_lpcg IMX_CSI_LPCG_CSI0_ESC_CLK>; + assigned-clock-rates = <360000000>, <72000000>; + power-domains = <&pd IMX_SC_R_CSI_0>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_csi", "pd_isi_ch0"; + status = "okay"; + + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <1 2>; + }; + }; + + }; diff --git a/Documentation/devicetree/bindings/media/imx8-parallel-csi.txt b/Documentation/devicetree/bindings/media/imx8-parallel-csi.txt new file mode 100644 index 00000000000000..af1ecb9e231842 --- /dev/null +++ b/Documentation/devicetree/bindings/media/imx8-parallel-csi.txt @@ -0,0 +1,48 @@ +Freescale i.MX8QXP Parallel Capture Interface +========================= + +parallel interface node +-------------- + +This is the device node for the parallel capture interface in i.MX8QXP SoC. + +Required properties: +- compatible : "fsl,mxc-parallel-csi"; +- reg : base address and length of the register set for the device; +- clocks : list of clock specifiers +- clock-names : must contain "pixel", "ipg", "div" and "dpll" entries, + matching entries in the clock property; +- assigned-clocks : need to set the parent of pixel clock; +- assigned-clock-parent: set the pll as the parent of pixel clock; +- assigned-clock-rates : the value should be 160MHz; +- power-domains : a phandle to the power domain, see +- power-domain-name : must contain "pd_pi", "pd_isi_ch0". + +port node +- reg : can take the values 0 which mean the port is a sink port + +example: + parallel_csi: pcsi@58261000 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "fsl,mxc-parallel-csi"; + reg = <0x58261000 0x1000>; + clocks = <&pi_lpcg IMX_PI_LPCG_PI0_PIXEL_CLK>, + <&pi_lpcg IMX_PI_LPCG_PI0_IPG_CLK>, + <&clk IMX_PARALLEL_PER_DIV_CLK>, + <&clk IMX_PARALLEL_DPLL_CLK>; + clock-names = "pixel", "ipg", "div", "dpll"; + assigned-clocks = <&clk IMX_PARALLEL_PER_DIV_CLK>; + assigned-clock-parents = <&clk IMX_PARALLEL_DPLL_CLK>; + assigned-clock-rates = <160000000>; /* 160MHz */ + power-domains = <&pd IMX_SC_R_PI_0>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_pi", "pd_isi_ch0"; + + port@0 { + reg = <0>; + parallel_csi_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt index 9d32762c47e1ba..88d701dea7c1eb 100644 --- a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt +++ b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt @@ -1,21 +1,22 @@ Binding for Synopsys IntelliDDR Multi Protocol Memory Controller -The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit -bus width configurations. +The ZynqMP and i.MX8MP DDR ECC controller has an optional ECC support in 64-bit +and 32-bit bus width configurations. The Zynq DDR ECC controller has an optional ECC support in half-bus width (16-bit) configuration. -These both ECC controllers correct single bit ECC errors and detect double bit +These all ECC controllers correct single bit ECC errors and detect double bit ECC errors. Required properties: - compatible: One of: - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller + - 'fsl,imx8mp-ddrc' : i.MX8MP DDR ECC controller - reg: Should contain DDR controller registers location and length. -Required properties for "xlnx,zynqmp-ddrc-2.40a": +Required properties for "xlnx,zynqmp-ddrc-2.40a" and "fsl,imx8mp-ddrc": - interrupts: Property with a value describing the interrupt number. Example: diff --git a/Documentation/devicetree/bindings/mfd/nxp,pca9450.txt b/Documentation/devicetree/bindings/mfd/nxp,pca9450.txt new file mode 100644 index 00000000000000..f296c7d2e6adf6 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/nxp,pca9450.txt @@ -0,0 +1,51 @@ +* NXP PCA9450 Power Management Integrated Circuit (PMIC) bindings + +Required properties: + - compatible : Should be "nxp,pca9450". + - reg : I2C slave address. + - pinctrl-0 : Pinctrl setting for pmic such as interrupt pin. + - gpio_intr : gpio pin used for interrupt pin. + - regulators: : List of child nodes that specify the regulator + initialization data. Including 6 buck regulators + and 5 ldo regulators. + +Example: + pmic: pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + pca9450,pmic-buck2-uses-i2c-dvs; + /* Run/Standby voltage */ + pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + ..... + + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/syscon.txt b/Documentation/devicetree/bindings/mfd/syscon.txt index 25d9e9c2fd53ae..543f319093fcf8 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.txt +++ b/Documentation/devicetree/bindings/mfd/syscon.txt @@ -14,6 +14,10 @@ Required properties: - reg: the register region can be accessed from syscon Optional property: +- compatible: + - "fsl,imx6q-iomuxc-gpr" + - "fsl,imx7d-iomuxc-gpr" + - "fsl,imx8mp-iomuxc-gpr" - reg-io-width: the size (in bytes) of the IO accesses that should be performed on the device. - hwlocks: reference to a phandle of a hardware spinlock provider node. diff --git a/Documentation/devicetree/bindings/mlb/mxc_mlb.txt b/Documentation/devicetree/bindings/mlb/mxc_mlb.txt new file mode 100644 index 00000000000000..e55d0083790ab0 --- /dev/null +++ b/Documentation/devicetree/bindings/mlb/mxc_mlb.txt @@ -0,0 +1,27 @@ +*MediaLB (MLB) for i.MX + +Required properties: +- compatible : + - "fsl,imx6sx-mlb50" for MLB compatible with the one integrated on i.MX6SX soc + - "fsl,imx6q-mlb150" for MLB compatible with the one integrated on i.MX6Q + - "fsl,imx8qxp-mlb150" for MLB compatible with the one integrated on i.MX8 soc +- reg : address and length for mlb registers +- interrupt-parent : core interrupt controller +- interrupts : MLB Break/Error interrupt and ahb interrupt + Two ahb interrupt for imx6, ahb_int[0] and ahb_int[1] + One ahb interrupt for imx8, ahb_int[0] +- clocks : mlb clock specifier + +Examples: + +mlb: mlb@5B060000 { + compatible = "fsl,imx6q-mlb150"; + reg = <0x0 0x5B060000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>, + <0 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_MLB_CLK>, + <&clk IMX8QM_MLB_HCLK>, + <&clk IMX8QM_MLB_IPG_CLK>; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt index f707b8bee30478..0da89a7a609724 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt @@ -19,6 +19,7 @@ Required properties: "fsl,imx7d-usdhc" "fsl,imx7ulp-usdhc" "fsl,imx8qxp-usdhc" + "fsl,imx8mm-usdhc" Optional properties: - fsl,wp-controller : Indicate to use controller internal write protection @@ -38,6 +39,19 @@ Optional properties: This property allows user to change the tuning step to more than one delay cells which is useful for some special boards or cards when the default tuning step can't find the proper delay window within limited tuning retries. +- fsl,strobe-dll-delay-target: Specify the strobe dll control slave delay target. + This delay target programming host controller loopback read clock, and this + property allows user to change the delay target for the strobe input read clock. + If not use this property, driver default set the delay target to value 7. + Only eMMC HS400 mode need to take care of this property. +- auto-cmd23-broken: disable the ACMD23 function of USDHC. + This is required for eMMC on imx6qpdl/imx6sx/imx7d when it use ADMA mode. Because + for these SoC, it do not support the ACMD23 completely, only take the 16 bit block + count from the 0x4 register (BLK_ATT) as argument for the ACMD23, the upper 16 bit + of the CMD23's argument is ignored. This will impact the reliable write operation + and the RPMB block write operation, because these operations need to set the bit 31 + of the CMD23's argument. SDMA mode will default disable the ACMD23 mode. SD card do + not has this limitation on these SoCs. Examples: diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml index 080754e0ef352f..c0e48a1cf5f14d 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml @@ -283,6 +283,12 @@ properties: description: SDIO only. Enables wake up of host system on SDIO IRQ assertion. + pm-ignore-notify: + $ref: /schemas/types.yaml#/definitions/flag + description: + Ignore mmc PM notify. This will prevent MMC core automatically + to re-detect cards after sysem resume back. + vmmc-supply: description: Supply for the card power diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt index 2cf3affa1be705..96c0b1440c9c5f 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt @@ -15,8 +15,15 @@ Required properties: - "nvidia,tegra210-sdhci": for Tegra210 - "nvidia,tegra186-sdhci": for Tegra186 - "nvidia,tegra194-sdhci": for Tegra194 -- clocks : Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. +- clocks: For Tegra210, Tegra186 and Tegra194 must contain two entries. + One for the module clock and one for the timeout clock. + For all other Tegra devices, must contain a single entry for + the module clock. See ../clocks/clock-bindings.txt for details. +- clock-names: For Tegra210, Tegra186 and Tegra194 must contain the + strings 'sdhci' and 'tmclk' to represent the module and + the timeout clocks, respectively. + For all other Tegra devices must contain the string 'sdhci' + to represent the module clock. - resets : Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. - reset-names : Must include the following entries: @@ -99,7 +106,7 @@ Optional properties for Tegra210, Tegra186 and Tegra194: Example: sdhci@700b0000 { - compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; + compatible = "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0000 0x0 0x200>; interrupts = ; clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; @@ -115,3 +122,22 @@ sdhci@700b0000 { nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; status = "disabled"; }; + +sdhci@700b0000 { + compatible = "nvidia,tegra210-sdhci"; + reg = <0x0 0x700b0000 0x0 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, + <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; + clock-names = "sdhci", "tmclk"; + resets = <&tegra_car 14>; + reset-names = "sdhci"; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; + pinctrl-0 = <&sdmmc1_3v3>; + pinctrl-1 = <&sdmmc1_1v8>; + nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; + nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; + nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; + nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/mtd/gpmi-nand.txt b/Documentation/devicetree/bindings/mtd/gpmi-nand.txt index 393588385c6e50..4fa19c874d5444 100644 --- a/Documentation/devicetree/bindings/mtd/gpmi-nand.txt +++ b/Documentation/devicetree/bindings/mtd/gpmi-nand.txt @@ -52,6 +52,7 @@ Optional properties: - nand-ecc-step-size: integer representing the number of data bytes that are covered by a single ECC step. The driver supports 512 and 1024. + - max-cs: maximum cs the board supports The device tree may optionally contain sub-nodes describing partitions of the address space. See partition.txt for more detail. diff --git a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt index 94c0f8bf4deb30..8e069adfa066e7 100644 --- a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt +++ b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt @@ -12,9 +12,42 @@ Required properties: - reg : Offset and length of the register set for this device - interrupts : Interrupt tuple for this device -Optional properties: +Clocking information is must for flexcan. please refer below info for +understanding clocking in flexcan: + +• The FLEXCAN module is divided into two blocks. Controller host interface + ("CHI") and Protocol Engine ("PE") +• Both these blocks require clock. +• CHI is responsible for registers read write including MB read/write. + While PE is responsible for Transfer/receive data on CAN bus. +• The clocks feeding to these two blocks can be synchronous (i.e. same clock) + or asynchronous (i.e. separate clocks). +• Selection is made in the CLK_SRC bit (bit 13) of Control 1 Register. + - CLK_SRC = 0, asynchronous i.e. separate clocks for CHI and PE + - CLK_SRC = 1, synchronous i.e. CHI clock is used for PE and PE + clock is not used. +• If this bit is not implemented in SOC, then SOC only supports asynchronous + clocks. +• Either of the clock can be generated by any of the clock source. +• When the two clocks are asynchronous, then following restrictions apply to + PE clock. + - PE clock must be less than CHI clock. +• If low jitter is required on CAN bus, dedicated oscillator can be used to + provide PE clock, but it must be less than CHI clock. + +Base on above information clocking info in flexcan can be defined in two ways: + +Method 1(Preferred): + - clocks: phandle to the clocks feeding the flexcan. Two can be given: + - "ipg": Protocol Engine clock + - "per": Controller host interface clock + - clock-names: Must contain the clock names described just above. -- clock-frequency : The oscillator frequency driving the flexcan device +Method 2(Not Preferred): + - clock-frequency : The synchronous clock frequency supplied to both + Controller host interface and Protocol Engine + +Optional properties: - xceiver-supply: Regulator that powers the CAN transceiver @@ -51,3 +84,12 @@ Example: clock-frequency = <200000000>; // filled in by bootloader fsl,clk-source = <0>; // select clock source 0 for PE }; + + can@2180000 { + compatible = "fsl,lx2160ar1-flexcan"; + reg = <0x0 0x2180000 0x0 0x10000>; + interrupts = ; + clocks = <&sysclk>, <&clockgen 4 7>; + clock-names = "ipg", "per"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml index 0e7c31794ae6c5..0bac41cc7ba188 100644 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml @@ -34,6 +34,15 @@ properties: to the device by the boot program is different from the local-mac-address property. + nvmem-mac-address: + allOf: + - $ref: /schemas/types.yaml#definitions/uint8-array + - minItems: 6 + maxItems: 6 + description: + Specifies the MAC address that was read from nvmem-cells and dynamically + add the property in device node; + max-frame-size: $ref: /schemas/types.yaml#definitions/uint32 description: @@ -54,6 +63,11 @@ properties: nvmem-cells-names: const: mac-address + nvmem_macaddr_swap: + $ref: /schemas/types.yaml#/definitions/flag + description: + swap bytes order for the 6 bytes of MAC address + phy-connection-type: description: Operation mode of the PHY interface diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt index 5b88fae0307d15..59e449ba2557a4 100644 --- a/Documentation/devicetree/bindings/net/fsl-fec.txt +++ b/Documentation/devicetree/bindings/net/fsl-fec.txt @@ -5,6 +5,19 @@ Required properties: - reg : Address and length of the register set for the device - interrupts : Should contain fec interrupt - phy-mode : See ethernet.txt file in the same directory +- clock-name: Should be the names of the clocks + - "ipg", for MAC ipg_clk_s, ipg_clk_mac_s that are for register accessing + - "ahb", for MAC ipg_clk, ipg_clk_mac that are bus clock + - "ptp"(option), for IEEE1588 timer clock that requires the clock + - "enet_clk_ref"(option), for MAC transmit/receiver reference clock like + RGMII TXC clock or RMII reference clock. It depends on board design, + the clock is required if RGMII TXC and RMII reference clock source from + SOC internal PLL. + - "enet_out"(option), output clock for external device, like supply clock + for PHY. The clock is required if PHY clock source from SOC. + - "enet_2x_txclk"(option), for RGMII sampleing clock which fixed at 250Mhz. + The clock is required if SOC RGMII enable clock delay. +- clocks: Phandles to input clocks. Optional properties: - phy-supply : regulator that powers the Ethernet PHY. @@ -35,6 +48,11 @@ Optional properties: For imx6sx, "int0" handles all 3 queues and ENET_MII. "pps" is for the pulse per second interrupt associated with 1588 precision time protocol(PTP). +- fsl,wakeup_irq : The property defines the wakeup irq index in enet irq source. +- stop-mode : If present, indicates soc need to set gpr bit to request stop mode. +- mii-exclusive: If present, each MAC has their exclusive MDIO bus in current board + design, otherwise multiple MACs share one MDIO bus to reduce Pins utilize. + Optional subnodes: - mdio : specifies the mdio bus in the FEC, used as a container for phy nodes according to phy.txt in the same directory diff --git a/Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt b/Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt new file mode 100644 index 00000000000000..4b38312c9b7fec --- /dev/null +++ b/Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt @@ -0,0 +1,199 @@ +============================================================================= +NXP Programmable Packet Forwarding Engine Device Bindings + +CONTENTS + - PFE Node + - Ethernet Node + +============================================================================= +PFE Node + +DESCRIPTION + +PFE Node has all the properties associated with Packet Forwarding Engine block. + +PROPERTIES + +- compatible + Usage: required + Value type: + Definition: Must include "fsl,pfe" + +- reg + Usage: required + Value type: + Definition: A standard property. + Specifies the offset of the following registers: + - PFE configuration registers + - DDR memory used by PFE + +- fsl,pfe-num-interfaces + Usage: required + Value type: + Definition: Must be present. Value can be either one or two. + +- interrupts + Usage: required + Value type: + Definition: Three interrupts are specified in this property. + - HIF interrupt + - HIF NO COPY interrupt + - Wake On LAN interrupt + +- interrupt-names + Usage: required + Value type: + Definition: Following strings are defined for the 3 interrupts. + "pfe_hif" - HIF interrupt + "pfe_hif_nocpy" - HIF NO COPY interrupt + "pfe_wol" - Wake On LAN interrupt + +- memory-region + Usage: required + Value type: + Definition: phandle to a node describing reserved memory used by pfe. + Refer:- Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt + +- fsl,pfe-scfg + Usage: required + Value type: + Definition: phandle for scfg. + +- fsl,rcpm-wakeup + Usage: required + Value type: + Definition: phandle for rcpm. + +- clocks + Usage: required + Value type: + Definition: phandle for clockgen. + +- clock-names + Usage: required + Value type: + Definition: phandle for clock name. + +EXAMPLE + +pfe: pfe@04000000 { + compatible = "fsl,pfe"; + reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */ + <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */ + reg-names = "pfe", "pfe-ddr"; + fsl,pfe-num-interfaces = <0x2>; + interrupts = <0 172 0x4>, /* HIF interrupt */ + <0 173 0x4>, /*HIF_NOCPY interrupt */ + <0 174 0x4>; /* WoL interrupt */ + interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol"; + memory-region = <&pfe_reserved>; + fsl,pfe-scfg = <&scfg 0>; + fsl,rcpm-wakeup = <&rcpm 0xf0000020>; + clocks = <&clockgen 4 0>; + clock-names = "pfe"; + + status = "okay"; + pfe_mac0: ethernet@0 { + }; + + pfe_mac1: ethernet@1 { + }; +}; + +============================================================================= +Ethernet Node + +DESCRIPTION + +Ethernet Node has all the properties associated with PFE used by platforms to +connect to PHY: + +PROPERTIES + +- compatible + Usage: required + Value type: + Definition: Must include "fsl,pfe-gemac-port" + +- reg + Usage: required + Value type: + Definition: A standard property. + Specifies the gemacid of the interface. + +- fsl,gemac-bus-id + Usage: required + Value type: + Definition: Must be present. Value should be the id of the bus + connected to gemac. + +- fsl,gemac-phy-id (deprecated binding) + Usage: required + Value type: + Definition: This binding shouldn't be used with new platforms. + Must be present. Value should be the id of the phy + connected to gemac. + +- fsl,mdio-mux-val + Usage: required + Value type: + Definition: Must be present. Value can be either 0 or 2 or 3. + This value is used to configure the mux to enable mdio. + +- phy-mode + Usage: required + Value type: + Definition: Must include "sgmii" + +- fsl,pfe-phy-if-flags (deprecated binding) + Usage: required + Value type: + Definition: This binding shouldn't be used with new platforms. + Must be present. Value should be 0 by default. + If there is not phy connected, this need to be 1. + +- phy-handle + Usage: optional + Value type: + Definition: phandle to the PHY device connected to this device. + +- mdio : A required subnode which specifies the mdio bus in the PFE and used as +a container for phy nodes according to ../phy.txt. + +EXAMPLE + +ethernet@0 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* GEM_ID */ + fsl,gemac-bus-id = <0x0>; /* BUS_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy1>; +}; + + +ethernet@1 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* GEM_ID */ + fsl,gemac-bus-id = <0x1>; /* BUS_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy2>; +}; + +mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy1: ethernet-phy@2 { + reg = <0x2>; + }; + + sgmii_phy2: ethernet-phy@1 { + reg = <0x1>; + }; +}; diff --git a/Documentation/devicetree/bindings/net/imx-dwmac.txt b/Documentation/devicetree/bindings/net/imx-dwmac.txt new file mode 100644 index 00000000000000..402885fc099220 --- /dev/null +++ b/Documentation/devicetree/bindings/net/imx-dwmac.txt @@ -0,0 +1,56 @@ +IMX8 glue layer controller, NXP imx8 families support Synopsys MAC 5.10a IP. + +This file documents platform glue layer for IMX. +Please see stmmac.txt for the other unchanged properties. + +The device node has following properties. + +Required properties: +- compatible: Should be "nxp,imx8mp-dwmac-eqos" to select glue layer + and "snps,dwmac-5.10a" to select IP version. +- clocks: Must contain a phandle for each entry in clock-names. +- clock-names: Should be "stmmaceth" for the host clock. + Should be "pclk" for the MAC apb clock. + Should be "ptp_ref" for the MAC timer clock. + Should be "tx" for the MAC RGMII TX clock: + Should be "mem" for EQOS MEM clock. + - required for imx8dxl platform. + - is not required for imx8mp platform. +- interrupt-names: Should contain a list of interrupt names corresponding to + the interrupts in the interrupts property, if available. + Should be "macirq" for the main MAC IRQ + Should be "eth_wake_irq" for the IT which wake up system +- intf_mode: Should be phandle/offset pair. The phandle to the syscon node which + encompases the GPR register, and the offset of the GPR register. + - required for imx8mp platform. + - is optional for imx8dxl platform. + +Optional properties: +- intf_mode: is optional for imx8dxl platform. +- snps,rmii_refclk_ext: to select RMII reference clock from external. + +Example: + eqos: ethernet@30bf0000 { + compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; + reg = <0x30bf0000 0x10000>; + interrupts = , + ; + interrupt-names = "eth_wake_irq", "macirq"; + clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, + <&clk IMX8MP_CLK_QOS_ENET_ROOT>, + <&clk IMX8MP_CLK_ENET_QOS_TIMER>, + <&clk IMX8MP_CLK_ENET_QOS>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; + assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, + <&clk IMX8MP_CLK_ENET_QOS_TIMER>, + <&clk IMX8MP_CLK_ENET_QOS>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_125M>; + assigned-clock-rates = <0>, <100000000>, <125000000>; + nvmem-cells = <ð_mac0>; + nvmem-cell-names = "mac-address"; + nvmem_macaddr_swap; + intf_mode = <&gpr 0x4>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/net/wireless/brcm,bcm43xx-fmac.txt b/Documentation/devicetree/bindings/net/wireless/brcm,bcm43xx-fmac.txt index cffb2d6876e349..66a7ba1f1c74ac 100644 --- a/Documentation/devicetree/bindings/net/wireless/brcm,bcm43xx-fmac.txt +++ b/Documentation/devicetree/bindings/net/wireless/brcm,bcm43xx-fmac.txt @@ -11,6 +11,7 @@ Required properties: Optional properties: - brcm,drive-strength : drive strength used for SDIO pins on device in mA (default = 6). + - brcm,use_board_type : suffix string for NVRAM - interrupts : specifies attributes for the out-of-band interrupt (host-wake). When not specified the device will use in-band SDIO interrupts. - interrupt-names : name of the out-of-band interrupt, which must be set diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index de4b2baf91e8ec..5584b5c747e52b 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -10,6 +10,10 @@ Required properties: - "fsl,imx6qp-pcie" - "fsl,imx7d-pcie" - "fsl,imx8mq-pcie" + - "fsl,imx8mm-pcie" + - "fsl,imx8qm-pcie" + - "fsl,imx8qxp-pcie" + - "fsl,imx8mp-pcie" - reg: base address and length of the PCIe controller - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. @@ -38,6 +42,15 @@ Optional properties: The regulator will be enabled when initializing the PCIe host and disabled either as part of the init process or when shutting down the host. +- ext_osc: use the external oscillator as ref clock( 1: external OSC is + used, 0 internal PLL is used). +- hard_wired: the PCIe port is hard wired to the EP device(0: one slot + is connected). +- reserved-region: one reserved no-map memory used by PCIe EP/RC + validation system. +- interrupt-names: Optional include the following entries: + - "dma": The interrupt that is asserted when an DMA interrupter + is received Additional required properties for imx6sx-pcie: - clock names: Must include the following additional entries: @@ -55,11 +68,23 @@ Additional required properties for imx7d-pcie and imx8mq-pcie: - "apps" - "turnoff" - fsl,imx7d-pcie-phy: A phandle to an fsl,imx7d-pcie-phy node. +- fsl,imx8mp-hsio-mix: A phandle to an fsl,imx8mp-hsio-mix node. Additional required properties for imx8mq-pcie: - clock-names: Must include the following additional entries: - "pcie_aux" +Additional required properties for imx8 pcie: +- hsio-cfg: hsio configration mode when the pcie node is supported. + mode 1: pciea 2 lanes and one sata ahci port. + mode 2: pciea 1 lane, pcieb 1 lane and one sata ahci port. + mode 3: pciea 2 lanes, pcieb 1 lane. +- local-addr: the local address used in hsio module. + Example: + hsio-cfg = ; + hsio = <&hsio>; + local-addr = <0x80000000>; + Example: pcie@01000000 { diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index e20ceaab9b38e9..992e917094b801 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -21,13 +21,18 @@ Required properties: "fsl,ls1046a-pcie" "fsl,ls1043a-pcie" "fsl,ls1012a-pcie" + "fsl,ls1028a-pcie" EP mode: "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep" - reg: base addresses and lengths of the PCIe controller register blocks. - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. -- interrupt-names: Must include the following entries: - "intr": The interrupt that is asserted for controller interrupts +- interrupt-names: It could include the following entries: + "aer": Asserted for aer interrupt when chip support the aer interrupt with + none MSI/MSI-X/INTx mode,but there is interrupt line for aer. + "pme": Asserted for pme interrupt when chip support the pme interrupt with + none MSI/MSI-X/INTx mode,but there is interrupt line for pme. + ...... - fsl,pcie-scfg: Must include two entries. The first entry must be a link to the SCFG device node The second entry must be '0' or '1' based on physical PCIe controller index. @@ -43,8 +48,9 @@ Example: reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; /* controller interrupt */ - interrupt-names = "intr"; + interrupts = , /* aer interrupt */ + ; /* pme interrupt */ + interrupt-names = "aer", "pme"; fsl,pcie-scfg = <&scfg 0>; #address-cells = <3>; #size-cells = <2>; diff --git a/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt b/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt new file mode 100644 index 00000000000000..414a86c9c6afac --- /dev/null +++ b/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt @@ -0,0 +1,78 @@ +NXP Layerscape PCIe Gen4 controller + +This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all +the common properties defined in mobiveil-pcie.txt. + +HOST MODE +========= +Required properties: +- compatible: should contain the platform identifier such as: + "fsl,lx2160a-pcie" +- reg: base addresses and lengths of the PCIe controller register blocks. + "csr_axi_slave": Bridge config registers + "config_axi_slave": PCIe controller registers +- interrupts: A list of interrupt outputs of the controller. Must contain an + entry for each entry in the interrupt-names property. +- interrupt-names: It could include the following entries: + "intr": The interrupt that is asserted for controller interrupts + "aer": Asserted for aer interrupt when chip support the aer interrupt with + none MSI/MSI-X/INTx mode,but there is interrupt line for aer. + "pme": Asserted for pme interrupt when chip support the pme interrupt with + none MSI/MSI-X/INTx mode,but there is interrupt line for pme. +- dma-coherent: Indicates that the hardware IP block can ensure the coherency + of the data transferred from/to the IP block. This can avoid the software + cache flush/invalid actions, and improve the performance significantly. +- msi-parent : See the generic MSI binding described in + Documentation/devicetree/bindings/interrupt-controller/msi.txt. + +DEVICE MODE +========= +Required properties: +- compatible: should contain the platform identifier such as: + "fsl,lx2160a-pcie-ep" +- reg: base addresses and lengths of the PCIe controller register blocks. + "regs": PCIe controller registers. + "addr_space" EP device CPU address. +- apio-wins: number of requested apio outbound windows. + +Optional Property: +- max-functions: Maximum number of functions that can be configured (default 1). + +RC Example: + + pcie@3400000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x80 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + apio-wins = <8>; + ppio-wins = <8>; + dma-coherent; + bus-range = <0x0 0xff>; + msi-parent = <&its>; + ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + }; + +EP Example: + + pcie_ep@3400000 { + compatible = "fsl,lx2160a-pcie-ep"; + reg = <0x00 0x03400000 0x0 0x00100000 + 0x80 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + apio-wins = <8>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt index d77e3f26f9e66e..45978a6da713f5 100644 --- a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt +++ b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt @@ -5,6 +5,9 @@ Required properties: - compatible: should be one of: "fsl,imx8-ddr-pmu" "fsl,imx8m-ddr-pmu" + "fsl,imx8mp-ddr-pmu" + "fsl,imx8dxl-ddr-pmu" + "fsl,imx8dxl-db-pmu" - reg: physical address and size diff --git a/Documentation/devicetree/bindings/phy/fsl,imx-pcie-phy.txt b/Documentation/devicetree/bindings/phy/fsl,imx-pcie-phy.txt new file mode 100644 index 00000000000000..627b508ecadc0c --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,imx-pcie-phy.txt @@ -0,0 +1,22 @@ +* Freescale i.MX PCIE PHY binding + +Required properties: +- compatible: Should be "fsl,imx-pcie-phy" +- #phys-cells: must be 0 (see phy-bindings.txt in this directory) +- reg: The base address and length of the registers +- clocks: Phandles to the clocks for each clock listed in clock-names +- clock-names: Must contain "phy" +- power-domains: Phandle to the power domain that the device is part of + +Example: + pcie_phy: pcie-phy@32f00000 { + compatible = "fsl,imx8mp-pcie-phy"; + reg = <0x0 0x32f00000 0x0 0x10000>; + clocks = <&clk IMX8MP_CLK_PCIE_PHY>; + clock-names = "phy"; + assigned-clocks = <&clk IMX8MP_CLK_PCIE_PHY>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + #phy-cells = <0>; + power-domains = <&pcie_pd>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mp-lvds-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mp-lvds-phy.yaml new file mode 100644 index 00000000000000..2dc5e0038365c3 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,imx8mp-lvds-phy.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright 2020 NXP +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,imx8mp-lvds-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8MP LVDS PHY Device Tree Bindings + +maintainers: + - Liu Ying + +description: | + LVDS PHY found on i.MX8MP SoC. The IP block contains two PHYs, each of + which supports a four data lane LVDS channel. + +properties: + compatible: + enum: + - fsl,imx8mp-lvds-phy + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + gpr: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to block control syscon + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb + + port@0: + type: object + description: A port node pointing to the PHY instance0's port node + properties: + reg: + maxItems: 1 + description: PHY instance number. + "#phy-cells": + const: 0 + + required: + - reg + - "#phy-cells" + + port@1: + type: object + description: A port node pointing to the PHY instance1's port node + properties: + reg: + maxItems: 1 + description: PHY instance number + "#phy-cells": + const: 0 + + required: + - reg + - "#phy-cells" + +required: + - compatible + - "#address-cells" + - "#size-cells" + - gpr + - port@0 + - port@1 + +additionalProperties: false + +examples: + - | + ldb_phy: phy@32ec0128 { + compatible = "fsl,imx8mp-lvds-phy"; + #address-cells = <1>; + #size-cells = <0>; + gpr = <&mediamix_blk_ctl>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "apb"; + + ldb_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt index ed47e5cd067e29..847eb2a4a5b842 100644 --- a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt @@ -1,7 +1,7 @@ * Freescale i.MX8MQ USB3 PHY binding Required properties: -- compatible: Should be "fsl,imx8mq-usb-phy" +- compatible: Should be "fsl,imx8mq-usb-phy" or "fsl,imx8mp-usb-phy" - #phys-cells: must be 0 (see phy-bindings.txt in this directory) - reg: The base address and length of the registers - clocks: phandles to the clocks for each clock listed in clock-names @@ -9,7 +9,48 @@ Required properties: Optional properties: - vbus-supply: A phandle to the regulator for USB VBUS. - +- fsl,phy-tx-vref-tune: Adjusts the high-speed DC level voltage. + - 1111: + 24% + - 1110: + 22% + ..... + - 0101: + 4% + - 0100: + 2% + - 0011: 0 (default on imx8mp) + - 0010: – 2% + - 0001: – 4% + - 0000: – 6% +- fsl,phy-tx-rise-tune: Adjusts the rise/fall times of the high-speed waveform. + - 11: – 3% + - 10: – 1% + - 01: 0 (default on imx8mp) + - 00: + 3% +- fsl,phy-tx-preemp-amp-tune: This property controls the amount of current + source to DP<#> and DM<#> after a J-to-K or K-to-J + transition. The HS Transmitter pre-emphasis current + is defined in terms of unit amounts. One unit + amount is approximately 600 μA and is defined as 1X + pre-emphasis current. + - 11: 3x pre-emphasis current + - 10: 2x pre-emphasis current + - 01: 1x pre-emphasis current + - 00: Disabled (default on imx8mp) +- fsl,phy-comp-dis-tune: Adjusts the voltage level for the threshold used to + detect a disconnect event at the host. + - 111: + 15.54% + - 110: + 11.86% + - 101: + 7.52% + - 100: + 4.08% + - 011: 0 (default on imx8mp) + - 010: – 3.04% + - 001: – 6.5% + - 000: – 9.01% +- fsl,pcs-tx-deemph-3p5db: This property sets the TX driver de-emphasis value + when pipeP_tx_deemph[1:0] is set to 2’b01 (according + to the PIPE3 specification), default value is 23 on + imx8mp. +- fsl,phy-pcs-tx-swing-full: This property sets the launch amplitude of the + transmitter, default value is 120 (7b'1111000) + on imx8mp. Example: usb3_phy0: phy@381f0040 { compatible = "fsl,imx8mq-usb-phy"; diff --git a/Documentation/devicetree/bindings/phy/phy-mixel-lvds-combo.txt b/Documentation/devicetree/bindings/phy/phy-mixel-lvds-combo.txt new file mode 100644 index 00000000000000..1694edb68956ca --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-mixel-lvds-combo.txt @@ -0,0 +1,19 @@ +Mixel LVDS combo PHY + +Required properties: +- compatible: must be "mixel,lvds-combo-phy". +- reg: offset and length of the register block. +- #phy-cells: see phy-bindings.txt in the same directory, must be <0>. +- clocks: clock phandle and specifier pair. +- clock-names: string, clock input name, must be "phy". +- power-domains: phandle pointing to power domain. + +Example: + ldb_phy@56221000 { + compatible = "mixel,lvds-combo-phy"; + reg = <0x0 0x56221000 0x0 0x100>, <0x0 0x56228000 0x0 0x1000>; + #phy-cells = <0>; + clocks = <&clk IMX_LVDS0_PHY_CLK>; + clock-names = "phy"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + }; diff --git a/Documentation/devicetree/bindings/phy/phy-mixel-lvds.txt b/Documentation/devicetree/bindings/phy/phy-mixel-lvds.txt new file mode 100644 index 00000000000000..27d0d342c53d26 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-mixel-lvds.txt @@ -0,0 +1,39 @@ +Mixel LVDS PHY + +This LVDS PHY supports two LVDS channels. + +Required properties: +- compatible: must be "mixel,lvds-phy". +- reg: offset and length of the register block. +- #address-cells: number of address cells for the LVDS channel subnodes, must + be <1>. +- #size-cells: number of size cells for the LVDS channel subnodes, must be <0>. +- clocks: clock phandle and specifier pair. +- clock-names: string, clock input name, must be "phy". +- power-domains: phandle pointing to power domain. + +The LVDS PHY device tree node should have the subnodes corresponding to the two +LVDS channels. These subnodes must contain the following properties: +- reg: the PHY ID. +- #phy-cells: see phy-bindings.txt in the same directory, must be <0>. + +Example: + ldb_phy@56241000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mixel,lvds-phy"; + reg = <0x0 0x56241000 0x0 0x100>; + clocks = <&clk IMX_LVDS0_PHY_CLK>; + clock-names = "phy"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + + ldb1_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb1_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.txt new file mode 100644 index 00000000000000..619104b34e36ff --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.txt @@ -0,0 +1,38 @@ +* Freescale IMX8MP IOMUX Controller + +Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory +for common binding part and usage. + +Required properties: +- compatible: "fsl,imx8mp-iomuxc" +- reg: should contain the base physical address and size of the iomuxc + registers. + +Required properties in sub-nodes: +- fsl,pins: each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in + . The last integer CONFIG is + the pad setting value like pull-up on this pin. Please refer to i.MX8M Plus + Reference Manual for detailed CONFIG settings. + +Examples: + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +iomuxc: pinctrl@30330000 { + compatible = "fsl,imx8mp-iomuxc"; + reg = <0x30330000 0x10000>; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 + >; + }; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,s32v234-siul2.txt b/Documentation/devicetree/bindings/pinctrl/fsl,s32v234-siul2.txt new file mode 100644 index 00000000000000..676357664a8c35 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,s32v234-siul2.txt @@ -0,0 +1,19 @@ +* Freescale SIUL2 iomux controller + +See chapter 20 ("System Integration Unit Lite2 (SIUL2)") in the reference +manual[1]. + +Based on fsl,imx-pincontrol implementation. + +Required properties: +- compatible: "fsl,s32v234-siul2" +- fsl,pins: two integers array, represents a group of pins mux and config + setting. The format is fsl,pins = + PIN_FUNC_ID - id of MSCR to be modified + CONFIG - configuration to be written in the MSCR/IMCR register + + Even though IMCR register should be used as input register, it can be + set and addressed in the same way as MSCR, only instead of passing the + IMCR index, IMCR_IDX + 512 is passed[1]. + +[1] https://www.nxp.com/webapp/Download?colCode=S32V234RM diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt index fcd37e93ed4da9..c42d8c241ad5c3 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt @@ -71,6 +71,13 @@ pinctrl-names: The list of names to assign states. List entry 0 defines the name for integer state ID 0, list entry 1 for state ID 1, and so on. +pinctrl-assert-gpios: + List of phandles, each pointing at a GPIO which is used by some + board design to steer pins between two peripherals on the board. + It plays like a board level pin multiplexer to choose different + functions for given pins by pulling up/down the GPIOs. See + bindings/gpio/gpio.txt for details of how to specify GPIO. + For example: /* For a client device requiring named states */ diff --git a/Documentation/devicetree/bindings/power/fsl,imx8m-genpd.txt b/Documentation/devicetree/bindings/power/fsl,imx8m-genpd.txt new file mode 100644 index 00000000000000..8f7d5f3e5d8a00 --- /dev/null +++ b/Documentation/devicetree/bindings/power/fsl,imx8m-genpd.txt @@ -0,0 +1,49 @@ +Device Tree Bindings for Freescale i.MX8M Generic Power Domain +============================================================== +The binding for the i.MX8M Generic power Domain[1]. + +[1] Documentation/devicetree/bindings/power/power_domain.txt + +Required properties: + + - compatible: should be of: + - "fsl,imx8m-power-domain" + - #power-domain-cells: Number of cells in a PM domain Specifier, must be 0 + - domain-index: should be the domain index number need to pass to TF-A + - domain-name: the name of this pm domain + +Optional properties: + - clocks: a number of phandles to clocks that need to be enabled during + domain power-up sequence to ensure reset propagation into devices + located inside this power domain + - power-supply: Power supply used to power the domain + - parent-domains: the phandle to the parent power domain + - active-wakeup: keep the PM domain powered in case the attached device wakeup + is enabled. + - rpm-always-on: keep the PM domain powered except for system suspend. + +example: + vpu_g1_pd: vpug1-pd { + compatible = "fsl,imx8mm-pm-domain"; + #power-domain-cells = <0>; + domain-index = <6>; + domain-name = "vpu_g1"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>; + }; + + +Specifying Power domain for IP modules +====================================== + +IP cores belonging to a power domain should contain a 'power-domains' +property that is a phandle for PGC node representing the domain. + +Example of a device that is part of the vpu_g1 power domain: + vpu_g1: vpu_g1@38300000 { + /* ... */ + interrupts = ; + interrupt-names = "irq_hantro"; + /* ... */ + power-domains = <&vpu_g1_pd>; + }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt index 07256b7ffcaab2..f1f749fc253e66 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt @@ -9,15 +9,20 @@ Properties: "fsl,mpc8548-pmc" should be listed for any chip whose PMC is compatible. "fsl,mpc8536-pmc" should also be listed for any chip - whose PMC is compatible, and implies deep-sleep capability. + whose PMC is compatible, and implies deep-sleep capability and + wake on user defined packet(wakeup on ARP). + + "fsl,p1022-pmc" should be listed for any chip whose PMC is + compatible, and implies lossless Ethernet capability during sleep. "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is compatible; all statements below that apply to "fsl,mpc8548-pmc" also apply to "fsl,mpc8641d-pmc". Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these - bit assignments are indicated via the sleep specifier in each device's - sleep property. + bit assignments are indicated via the clock nodes. Device which has a + controllable clock source should have a "fsl,pmc-handle" property pointing + to the clock node. - reg: For devices compatible with "fsl,mpc8349-pmc", the first resource is the PMC block, and the second resource is the Clock Configuration @@ -33,31 +38,35 @@ Properties: this is a phandle to an "fsl,gtm" node on which timer 4 can be used as a wakeup source from deep sleep. -Sleep specifiers: +Clock nodes: +The clock nodes are to describe the masks in PM controller registers for each +soc clock. +- fsl,pmcdr-mask: For "fsl,mpc8548-pmc"-compatible devices, the mask will be + ORed into PMCDR before suspend if the device using this clock is the wake-up + source and need to be running during low power mode; clear the mask if + otherwise. - fsl,mpc8349-pmc: Sleep specifiers consist of one cell. For each bit - that is set in the cell, the corresponding bit in SCCR will be saved - and cleared on suspend, and restored on resume. This sleep controller - supports disabling and resuming devices at any time. +- fsl,sccr-mask: For "fsl,mpc8349-pmc"-compatible devices, the corresponding + bit specified by the mask in SCCR will be saved and cleared on suspend, and + restored on resume. - fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of - which will be ORed into PMCDR upon suspend, and cleared from PMCDR - upon resume. The first two cells are as described for fsl,mpc8578-pmc. - This sleep controller only supports disabling devices during system - sleep, or permanently. - - fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the - first of which will be ORed into DEVDISR (and the second into - DEVDISR2, if present -- this cell should be zero or absent if the - hardware does not have DEVDISR2) upon a request for permanent device - disabling. This sleep controller does not support configuring devices - to disable during system sleep (unless supported by another compatible - match), or dynamically. +- fsl,devdisr-mask: Contain one or two cells, depending on the availability of + DEVDISR2 register. For compatible devices, the mask will be ORed into DEVDISR + or DEVDISR2 when the clock should be permenently disabled. Example: - power@b00 { - compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc"; - reg = <0xb00 0x100 0xa00 0x100>; - interrupts = <80 8>; + power@e0070 { + compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc"; + reg = <0xe0070 0x20>; + + etsec1_clk: soc-clk@24 { + fsl,pmcdr-mask = <0x00000080>; + }; + etsec2_clk: soc-clk@25 { + fsl,pmcdr-mask = <0x00000040>; + }; + etsec3_clk: soc-clk@26 { + fsl,pmcdr-mask = <0x00000020>; + }; }; diff --git a/Documentation/devicetree/bindings/regulator/fixed-regulator.yaml b/Documentation/devicetree/bindings/regulator/fixed-regulator.yaml index f3241696819722..59b4b73d405194 100644 --- a/Documentation/devicetree/bindings/regulator/fixed-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/fixed-regulator.yaml @@ -50,6 +50,10 @@ properties: description: startup time in microseconds $ref: /schemas/types.yaml#/definitions/uint32 + off-on-delay-us: + description: off delay time in microseconds + $ref: /schemas/types.yaml#/definitions/uint32 + enable-active-high: description: Polarity of GPIO is Active high. If this property is missing, diff --git a/Documentation/devicetree/bindings/regulator/pfuze100.txt b/Documentation/devicetree/bindings/regulator/pfuze100.txt index 4d3b12b92cb3c6..409cf209a0cbf2 100644 --- a/Documentation/devicetree/bindings/regulator/pfuze100.txt +++ b/Documentation/devicetree/bindings/regulator/pfuze100.txt @@ -3,6 +3,8 @@ PFUZE100 family of regulators Required properties: - compatible: "fsl,pfuze100", "fsl,pfuze200", "fsl,pfuze3000", "fsl,pfuze3001" - reg: I2C slave address +- fsl,lpsr-mode: some registers need to be saved and restored in lpsr mode + for pfuze3000 Optional properties: - fsl,pfuze-support-disable-sw: Boolean, if present disable all unused switch diff --git a/Documentation/devicetree/bindings/remoteproc/imx-rproc.txt b/Documentation/devicetree/bindings/remoteproc/imx-rproc.txt deleted file mode 100644 index fbcefd965dc42c..00000000000000 --- a/Documentation/devicetree/bindings/remoteproc/imx-rproc.txt +++ /dev/null @@ -1,33 +0,0 @@ -NXP iMX6SX/iMX7D Co-Processor Bindings ----------------------------------------- - -This binding provides support for ARM Cortex M4 Co-processor found on some -NXP iMX SoCs. - -Required properties: -- compatible Should be one of: - "fsl,imx7d-cm4" - "fsl,imx6sx-cm4" -- clocks Clock for co-processor (See: ../clock/clock-bindings.txt) -- syscon Phandle to syscon block which provide access to - System Reset Controller - -Optional properties: -- memory-region list of phandels to the reserved memory regions. - (See: ../reserved-memory/reserved-memory.txt) - -Example: - m4_reserved_sysmem1: cm4@80000000 { - reg = <0x80000000 0x80000>; - }; - - m4_reserved_sysmem2: cm4@81000000 { - reg = <0x81000000 0x80000>; - }; - - imx7d-cm4 { - compatible = "fsl,imx7d-cm4"; - memory-region = <&m4_reserved_sysmem1>, <&m4_reserved_sysmem2>; - syscon = <&src>; - clocks = <&clks IMX7D_ARM_M4_ROOT_CLK>; - }; diff --git a/Documentation/devicetree/bindings/remoteproc/imx-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/imx-rproc.yaml new file mode 100644 index 00000000000000..b0cfb48e60cfeb --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/imx-rproc.yaml @@ -0,0 +1,165 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/remoteproc/imx-rproc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: NXP iMX6SX/iMX7D Co-Processor Bindings + +description: + This binding provides support for ARM Cortex M4 Co-processor found on + some NXP iMX SoCs. + +maintainers: + - Oleksij Rempel + - Peng Fan + +properties: + compatible: + enum: + - "fsl,imx7d-cm4" + - "fsl,imx6sx-cm4" + - "fsl,imx7ulp-cm4" + - "fsl,imx8mm-cm4" + - "fsl,imx8qm-cm4" + - "fsl,imx8qxp-cm4" + + early-booted: true + + clocks: + items: + Clock for co-processor (See: ../clock/clock-bindings.txt) + + syscon: + description: + Phandle to syscon block which provide access to System Reset Controller + allOf: + - $ref: "/schemas/types.yaml#/definitions/phandle" + + mboxes: + description: + This property is required only if the rpmsg/virtio functionality is used. + List of <&phandle type channel> - 1 channel for TX, 1 channel for RX, + 1 channel for RXDB. + (see mailbox/fsl,mu.txt) + maxItems: 3 + + mbox-names: + items: + - const: tx + - const: rx + - const: rxdb + maxItems: 3 + + memory-region: + description: + List of phandles to the reserved memory regions. + (see ../reserved-memory/reserved-memory.txt) + + mub-partition: + description: + The remote Co-processor hardware partition which is only valid for + i.MX SoCs with hardware partition feature. + $ref: /schemas/types.yaml#/definitions/uint32 + + rsrc-table: + description: + Resource table array is required only if the rpmsg/virtio + functionality is used. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + + rsrc-da: + description: + Resource table address is required only if the rpmsg/virtio + functionality is used, rsrc-table has high priority. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - clocks + - syscon + +examples: + - | + #include + m4_reserved_sysmem1: cm4@80000000 { + reg = <0x80000000 0x80000>; + }; + + m4_reserved_sysmem2: cm4@81000000 { + reg = <0x81000000 0x80000>; + }; + + imx7d-cm4 { + compatible = "fsl,imx7d-cm4"; + memory-region = <&m4_reserved_sysmem1>, <&m4_reserved_sysmem2>; + syscon = <&src>; + clocks = <&clks IMX7D_ARM_M4_ROOT_CLK>; + }; + + imx8x-cm4 { + compatible = "fsl,imx8qxp-cm4"; + rsrc-table = < + 0x1 0x2 0x0 0x0 0x18 0x5c + 3 + /*fw_rsc_vdev*/ + 7 0 1 0 0 0x200 + /*fw_rsc_vdev_vring*/ + 0x90000000 4096 256 1 0 + 0x90008000 4096 256 2 0 + 3 + /*fw_rsc_vdev*/ + 7 1 1 0 0 0x200 + /*fw_rsc_vdev_vring*/ + 0x90010000 4096 256 1 0 + 0x90018000 4096 256 2 0 + >; + early-booted; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu5 0 1 + &lsio_mu5 1 1 + &lsio_mu5 3 1>; + mub-partition = <3>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, + <&vdev1vring0>, <&vdev1vring1>, <&vdev0buffer>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + vdev0vring0: vdev0vring0@90000000 { + compatible = "shared-dma-pool"; + reg = <0 0x90000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@90008000 { + compatible = "shared-dma-pool"; + reg = <0 0x90008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@90010000 { + compatible = "shared-dma-pool"; + reg = <0 0x90010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@90018000 { + compatible = "shared-dma-pool"; + reg = <0 0x90018000 0 0x8000>; + no-map; + }; + + vdev0buffer: vdev0buffer { + compatible = "shared-dma-pool"; + reg = <0 0x90400000 0 0x100000>; + no-map; + }; +}; + +... diff --git a/Documentation/devicetree/bindings/reset/gpio-reset.txt b/Documentation/devicetree/bindings/reset/gpio-reset.txt new file mode 100644 index 00000000000000..7d45d8b810ea68 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/gpio-reset.txt @@ -0,0 +1,36 @@ +GPIO reset controller +===================== + +A GPIO reset controller controls a single GPIO that is connected to the reset +pin of a peripheral IC. Please also refer to reset.txt in this directory for +common reset controller binding usage. + +Required properties: +- compatible: Should be "gpio-reset" +- reset-gpios: A gpio used as reset line. The gpio specifier for this property + depends on the gpio controller that provides the gpio. +- #reset-cells: 0, see below + +Optional properties: +- reset-delay-us: delay in microseconds. The gpio reset line will be asserted for + this duration to reset. +- reset-post-delay-ms: delay in milliseconds to wait after reset. +- initially-in-reset: boolean. If not set, the initial state should be a + deasserted reset line. If this property exists, the + reset line should be kept in reset. + +example: + +sii902x_reset: gpio-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + reset-delay-us = <10000>; + initially-in-reset; + #reset-cells = <0>; +}; + +/* Device with nRESET pin connected to GPIO5_0 */ +sii902x@39 { + /* ... */ + resets = <&sii902x_reset>; /* active-low GPIO5_0, 10 ms delay */ +}; diff --git a/Documentation/devicetree/bindings/reset/nxp,dispmix-clk-en.txt b/Documentation/devicetree/bindings/reset/nxp,dispmix-clk-en.txt new file mode 100644 index 00000000000000..4375039eb07298 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/nxp,dispmix-clk-en.txt @@ -0,0 +1,58 @@ +NXP Display Mix clk-en Reset Controller +======================================= + +This binding describes a reset controller device that is used to enable +or disable the internal clocks for all the submodules(such as, LCDIF, +MIPI DSI, MIPI CSI, ISI and etc) included by the Display Mix subsystem +on IMX8MM and IMX8MN platforms. Like sft-rstn, only assert and deassert +functions are required for submodule internal clocks enable or disable, +that means the clk-en can be treated as a real reset controller. + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required properties: +- compatible: Should be "fsl,imx8mm-dispmix-clk-en" or + "fsl,imx8mn-dispmix-clk-en". +- reg: should be register base and length as documented in the datasheet. +- clocks: phandle and clock specifier to disp apb clock for register access. +- clock-names: should be "disp-apb". +- power-domains: phandle to dispmix power domain. +- reset-cells: 1, see below. + +example: + + dispmix_clk_en: dispmix-clk-en@32e28004 { + compatible = "fsl,imx8mn-dispmix-clk-en"; + reg = <0x0 0x32e28004 0x0 0x4>; + clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "disp-apb"; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + +Specifying clk-en control of devices +==================================== + +Device nodes in Display Mix should specify the reset channel required in +their "resets" property, containing a phandle to the clk-en device node +and an index to specify which channel to use, as described in +Documentation/devicetree/bindings/reset/reset.txt. + +example: + + lcdif_resets: lcdif-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + lcdif-clk-enable { + compatible = "lcdif,clk-enable"; + resets = <&dispmix_clk_en IMX8MN_LCDIF_APB_CLK_EN>, + <&dispmix_clk_en IMX8MN_LCDIF_PIXEL_CLK_EN>; + }; + }; + +Macro definitions for the supported reset channels can be found in: +include/dt-bindings/reset/imx8mm-dispmix.h and +include/dt-bindings/reset/imx8mn-dispmix.h. diff --git a/Documentation/devicetree/bindings/reset/nxp,dispmix-mipi-rst.txt b/Documentation/devicetree/bindings/reset/nxp,dispmix-mipi-rst.txt new file mode 100644 index 00000000000000..c47bfd4842ed9c --- /dev/null +++ b/Documentation/devicetree/bindings/reset/nxp,dispmix-mipi-rst.txt @@ -0,0 +1,57 @@ +NXP Display Mix mipi-rst Reset Controller +========================================= + +This binding describes a reset controller device that is used to reset +or de-reset the MIPI DPHY master direction(for MIPI DSI) and slave +direction(for MIPI CSI) included by the Display Mix subsystem on IMX8MM +and IMX8MN platforms. Like sft-rstn, only assert and deassert functions +are required for PHY reset or de-reset. + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required properties: +- compatible: Should be "fsl,imx8mm-dispmix-mipi-rst" or + "fsl,imx8mn-dispmix-mipi-rst". +- reg: should be register base and length as documented in the datasheet. +- clocks: phandle and clock specifier to disp apb clock for register access. +- clock-names: should be "disp-apb". +- power-domains: phandle to dispmix power domain. +- reset-cells: 1, see below. + +example: + + dispmix_mipi_rst: dispmix-mipi-rst@32e28008 { + compatible = "fsl,imx8mn-dispmix-mipi-rst"; + reg = <0x0 0x32e28008 0x0 0x4>; + clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "disp-apb"; + active_low; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + +Specifying mipi-rst control of devices +====================================== + +Device nodes in Display Mix should specify the reset channel required in +their "resets" property, containing a phandle to the mipi-rst device node +and an index to specify which channel to use, as described in +Documentation/devicetree/bindings/reset/reset.txt. + +example: + + mipi_dsi_resets: mipi-dsi-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + dsi-mipi-reset { + compatible = "dsi,mipi-reset"; + resets = <&dispmix_mipi_rst IMX8MN_MIPI_M_RESET>; + }; + }; + +Macro definitions for the supported reset channels can be found in: +include/dt-bindings/reset/imx8mm-dispmix.h and +include/dt-bindings/reset/imx8mn-dispmix.h. diff --git a/Documentation/devicetree/bindings/reset/nxp,dispmix-sft-rstn.txt b/Documentation/devicetree/bindings/reset/nxp,dispmix-sft-rstn.txt new file mode 100644 index 00000000000000..7867018a409bbe --- /dev/null +++ b/Documentation/devicetree/bindings/reset/nxp,dispmix-sft-rstn.txt @@ -0,0 +1,58 @@ +NXP Display Mix sft-rstn Reset Controller +========================================= + +This binding describes a reset controller device that is used to reset +or de-reset all the submodules(such as, LCDIF, MIPI DSI, MIPI CSI, ISI +and etc) included by the Display Mix subsystem on IMX8MM and IMX8MN +platforms. Only assert and deassert functions are required for submodule +reset or de-reset. + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required properties: +- compatible: Should be "fsl,imx8mm-dispmix-sft-rstn" or + "fsl,imx8mn-dispmix-sft-rstn". +- reg: should be register base and length as documented in the datasheet. +- clocks: phandle and clock specifier to disp apb clock for register access. +- clock-names: should be "disp-apb". +- power-domains: phandle to dispmix power domain. +- reset-cells: 1, see below. + +example: + + dispmix_sft_rstn: dispmix-sft-rstn@32e28000 { + compatible = "fsl,imx8mm-dispmix-sft-rstn"; + reg = <0x0 0x32e28000 0x0 0x4>; + clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "disp-apb"; + active_low; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + +Specifying sft-rstn control of devices +====================================== + +Device nodes in Display Mix should specify the reset channel required in +their "resets" property, containing a phandle to the sft-rstn device node +and an index to specify which channel to use, as described in +Documentation/devicetree/bindings/reset/reset.txt. + +example: + + lcdif_resets: lcdif-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + lcdif-soft-resetn { + compatible = "lcdif,soft-resetn"; + resets = <&dispmix_sft_rstn IMX8MN_LCDIF_APB_CLK_RESET>, + <&dispmix_sft_rstn IMX8MN_LCDIF_PIXEL_CLK_RESET>; + }; + }; + +Macro definitions for the supported reset channels can be found in: +include/dt-bindings/reset/imx8mm-dispmix.h and +include/dt-bindings/reset/imx8mn-dispmix.h. diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,rpmsg.txt b/Documentation/devicetree/bindings/soc/fsl/fsl,rpmsg.txt new file mode 100644 index 00000000000000..f27e843a8d8220 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,rpmsg.txt @@ -0,0 +1,77 @@ +i.MX RPMSG platform implementations + +Distributed framework is used in IMX RPMSG implementation, refer to the +following requirements: + - The CAN functions contained in M core and RTOS should be ready and + complete functional in 50ms after AMP system is turned on. + - Partition reset. System wouldn't be stalled by the exceptions (e.x + the reset triggered by the system hang) occurred at the other side. + And the RPMSG mechanism should be recovered automactilly after the + partition reset is completed. +In this scenario, the M core and RTOS would be kicked off by bootloader +firstly, then A core and Linux would be loaded later. Both M core/RTOS +and A core/Linux are running independly. +One physical memory region used to store the vring is mandatory required +to pre-reserved and well-knowned by both A core and M core + +Required properties: +- compatible: "fsl,imx8qxp-rpmsg", "fsl,imx8mq-rpmsg", "fsl,imx8mm-rpmsg", + "fsl,imx8qm-rpmsg", "fsl,imx7ulp-rpmsg", "fsl,imx7d-rpmsg", + "fsl,imx6sx-rpmsg". +- vdev-nums: The number of the remote virtual devices. +- reg: The reserved phisical DDR memory used to store vring descriptors. + +Optional properties: +- rpmsg_dma_reserved: The reserved per device dma pool, that used to + allocate the shared memory buffers from the per device. + And it is optional for some platforms, since the system dma pool + is used to allocate the shared memory buffers directly on them. +- mub-partition: The partition ID of muB side, that's optional + and used on i.mx8qm/8qxp for partition reset. The default + value is 3 in driver without this property. + +===================================================================== +Mailbox used by iMX RPMSG + +- mboxes: mailboxes used in the RPMSG transactions. +- mbox-names: names of the mailboxes used in RPMSG. + - "tx":TX channel with 32bit transmit register and IRQ transmit + - "rx":RX channel with 32bit receive register and IRQ support + - "rxdb":RX doorbell channel. + +Example: +Rpmsg node in board dts file. +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + status = "okay"; +}; + +SOC level dts node definitions: +rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; +}; +rpmsg_dma_reserved:rpmsg_dma@0x90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x1C00000>; +}; +rpmsg: rpmsg{ + compatible = "fsl,imx8qxp-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu5 0 1 + &lsio_mu5 1 1 + &lsio_mu5 3 1>; + mub-partition = <3>; + memory-region = <&rpmsg_dma_reserved>; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt index e284e4e1ccd543..751a7655b6945d 100644 --- a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt +++ b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt @@ -5,7 +5,7 @@ and power management. Required properites: - reg : Offset and length of the register set of the RCPM block. - - fsl,#rcpm-wakeup-cells : The number of IPPDEXPCR register cells in the + - #fsl,rcpm-wakeup-cells : The number of IPPDEXPCR register cells in the fsl,rcpm-wakeup property. - compatible : Must contain a chip-specific RCPM block compatible string and (if applicable) may contain a chassis-version RCPM compatible @@ -20,6 +20,7 @@ Required properites: * "fsl,qoriq-rcpm-1.0": for chassis 1.0 rcpm * "fsl,qoriq-rcpm-2.0": for chassis 2.0 rcpm * "fsl,qoriq-rcpm-2.1": for chassis 2.1 rcpm + * "fsl,qoriq-rcpm-2.1+": for chassis 2.1+ rcpm All references to "1.0" and "2.0" refer to the QorIQ chassis version to which the chip complies. @@ -27,16 +28,42 @@ Chassis Version Example Chips --------------- ------------------------------- 1.0 p4080, p5020, p5040, p2041, p3041 2.0 t4240, b4860, b4420 -2.1 t1040, ls1021 +2.1 t1040, +2.1+ ls1021a, ls1012a, ls1043a, ls1046a + +Optional properties: + - little-endian : RCPM register block is Little Endian. Without it RCPM + will be Big Endian (default case). + - fsl,ippdexpcr1-alt-addr : The property is related to a hardware issue + on SoC LS1021A and only needed on SoC LS1021A. + Must include 1 + 2 entries. + The first entry must be a link to the SCFG device node. + The non-first entry must be offset of registers of SCFG. + The second and third entry compose an alt offset address + for IPPDEXPCR1(SCFG_SPARECR8) Example: The RCPM node for T4240: rcpm: global-utilities@e2000 { compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0"; reg = <0xe2000 0x1000>; - fsl,#rcpm-wakeup-cells = <2>; + #fsl,rcpm-wakeup-cells = <2>; }; +The RCPM node for LS1021A: + rcpm: rcpm@1ee2140 { + compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+"; + reg = <0x0 0x1ee2140 0x0 0x8>; + #fsl,rcpm-wakeup-cells = <2>; + + /* + * The second and third entry compose an alt offset + * address for IPPDEXPCR1(SCFG_SPARECR8) + */ + fsl,ippdexpcr1-alt-addr = <&scfg 0x0 0x51c>; + }; + + * Freescale RCPM Wakeup Source Device Tree Bindings ------------------------------------------- Required fsl,rcpm-wakeup property should be added to a device node if the device @@ -44,7 +71,7 @@ can be used as a wakeup source. - fsl,rcpm-wakeup: Consists of a phandle to the rcpm node and the IPPDEXPCR register cells. The number of IPPDEXPCR register cells is defined in - "fsl,#rcpm-wakeup-cells" in the rcpm node. The first register cell is + "#fsl,rcpm-wakeup-cells" in the rcpm node. The first register cell is the bit mask that should be set in IPPDEXPCR0, and the second register cell is for IPPDEXPCR1, and so on. diff --git a/Documentation/devicetree/bindings/sound/fsl,asrc.txt b/Documentation/devicetree/bindings/sound/fsl,asrc.txt index 1d4d9f938689f3..cd2bd3daa7e184 100644 --- a/Documentation/devicetree/bindings/sound/fsl,asrc.txt +++ b/Documentation/devicetree/bindings/sound/fsl,asrc.txt @@ -8,7 +8,8 @@ three substreams within totally 10 channels. Required properties: - - compatible : Contains "fsl,imx35-asrc" or "fsl,imx53-asrc". + - compatible : Contains "fsl,imx35-asrc", "fsl,imx53-asrc", + "fsl,imx8qm-asrc0" or "fsl,imx8qm-asrc1". - reg : Offset and length of the register set for the device. diff --git a/Documentation/devicetree/bindings/sound/fsl,aud2htx.txt b/Documentation/devicetree/bindings/sound/fsl,aud2htx.txt new file mode 100644 index 00000000000000..a9eaa055e6b489 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl,aud2htx.txt @@ -0,0 +1,35 @@ +fsl,aud2htx The AUD2HTX is a digital module that provides a bridge between +the Audio Subsystem and the HDMI RTX Subsystem. + +Required properties: + +- compatible: Must contain one of "fsl,imx8mp-aud2htx". +- reg: Offset and length of the register set for the device. +- interrupts: where a is the interrupt number and b is a + field that represents an encoding of the sense and + level information for the interrupt. This should be + encoded based on the information in section 2) + depending on the type of interrupt controller you + have. +- clocks: A list of phandles + clock-specifiers, one for each + entry in clock-names +- clock-names: Must contain "bus" + +Optional properties: +- dmas: Generic dma devicetree binding as described in + Documentation/devicetree/bindings/dma/dma.txt. +- dma-names: One dmas have to be defined, "tx". + +Example: + +aud2htx: aud2htx@30cb0000 { + compatible = "fsl,imx8mp-aud2htx"; + reg = <0x30cb0000 0x10000>; + interrupts = ; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG>; + clock-names = "bus"; + dmas = <&sdma2 26 2 0>; + dma-names = "tx"; + power-domains = <&audiomix_pd>; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/sound/fsl,dsp.txt b/Documentation/devicetree/bindings/sound/fsl,dsp.txt new file mode 100644 index 00000000000000..84bc228b4e3221 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl,dsp.txt @@ -0,0 +1,16 @@ +NXP DSP + +The IP is from Cadence. + +Required properties: + + - compatible : Contains "fsl,imx8qxp-dsp". + - reg : Offset and length of the register set for the device. + +Example: + +dsp: dsp@596e8000 { + compatible = "fsl,imx8qxp-dsp"; + reg = <0x0 0x596e8000 0x0 0x88000>; + status = "okay"; +}; diff --git a/Documentation/devicetree/bindings/sound/fsl,easrc.txt b/Documentation/devicetree/bindings/sound/fsl,easrc.txt new file mode 100644 index 00000000000000..569ff3f503178a --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl,easrc.txt @@ -0,0 +1,53 @@ +Freescale Asynchronous Sample Rate Converter (ASRC) Controller + +The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a +signal associated with an input clock into a signal associated with a different +output clock. The driver currently works as a Front End of DPCM with other Back +Ends Audio controller such as ESAI, SSI and SAI. It has four context to support +four substreams within totally 32 channels. + +Required properties: + + - compatible : Contains "fsl,imx8mn-easrc". + + - reg : Offset and length of the register set for the device. + + - interrupts : Contains the asrc interrupt. + + - dmas : Generic dma devicetree binding as described in + Documentation/devicetree/bindings/dma/dma.txt. + + - dma-names : Contains "ctx0_rx", "ctx0_tx", "ctx1_rx", "ctx1_tx", + "ctx2_rx", "ctx2_tx", "ctx3_rx", "ctx3_tx". + + - clocks : Contains an entry for each entry in clock-names. + + - clock-names : Contains the following entries + "mem" Peripheral clock to driver module. + + - fsl,easrc-ram-script-name : The coefficient table for the filters + - fsl,asrc-rate : Defines a mutual sample rate used by DPCM Back Ends. + + - fsl,asrc-width : Defines a mutual sample width used by DPCM Back Ends. + +Example: + +easrc: easrc@300C0000 { + compatible = "fsl,imx8mn-easrc"; + reg = <0x0 0x300C0000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_ASRC_ROOT>; + clock-names = "mem"; + dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, + <&sdma2 18 23 0> , <&sdma2 19 23 0>, + <&sdma2 20 23 0> , <&sdma2 21 23 0>, + <&sdma2 22 23 0> , <&sdma2 23 23 0>; + dma-names = "ctx0_rx", "ctx0_tx", + "ctx1_rx", "ctx1_tx", + "ctx2_rx", "ctx2_tx", + "ctx3_rx", "ctx3_tx"; + fsl,easrc-ram-script-name = "imx/easrc/easrc-imx8mn.bin"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/sound/fsl,mqs.txt b/Documentation/devicetree/bindings/sound/fsl,mqs.txt new file mode 100644 index 00000000000000..092083d3a33595 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl,mqs.txt @@ -0,0 +1,23 @@ +fsl,mqs audio CODEC + +Required properties: + + - compatible : must contain one of "fsl,imx6sx-mqs", "fsl,codec-mqs" + "fsl,imx8qm-mqs". + + - clocks : a list of phandles + clock-specifiers, one for each entry in + clock-names + + - clock-names : must contain "mclk" + + - gpr : the gpr node. + +Example: + +mqs: mqs { + compatible = "fsl,imx6sx-mqs"; + gpr = <&gpr>; + clocks = <&clks IMX6SX_CLK_SAI1>; + clock-names = "mclk"; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/sound/fsl,rpmsg-i2s.txt b/Documentation/devicetree/bindings/sound/fsl,rpmsg-i2s.txt new file mode 100644 index 00000000000000..27de48eb2519b6 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl,rpmsg-i2s.txt @@ -0,0 +1,22 @@ +Freescale rpmsg i2s interface. + +The rpmsg i2s is based on RPMSG that used communicating with M4 core, +which provides a synchronous audio interface that supports fullduplex +serial interfaces with frame synchronization such as I2S. + +Required properties: + + - compatible : Compatible list, contains "fsl,imx7ulp-rpmsg-i2s". + "fsl,imx8mq-rpmsg-i2s", "fsl,imx8qxp-rpmsg-i2s" + "fsl,imx8qm-rpmsg-i2s" + + - fsl,audioindex : This is an index indicating the audio device index in + the M4 side. + +Example: +rpmsg_i2s: rpmsg-i2s { + compatible = "fsl,imx7ulp-rpmsg-i2s"; + /* the audio device index in m4 domain */ + fsl,audioindex = <0> ; + status = "okay"; +}; diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.txt b/Documentation/devicetree/bindings/sound/fsl,spdif.txt index 8b324f82a78280..cf3c3556c8010e 100644 --- a/Documentation/devicetree/bindings/sound/fsl,spdif.txt +++ b/Documentation/devicetree/bindings/sound/fsl,spdif.txt @@ -6,7 +6,9 @@ a fibre cable. Required properties: - - compatible : Compatible list, must contain "fsl,imx35-spdif". + - compatible : Compatible list, must contain "fsl,imx35-spdif", + "fsl,vf610-spdif", "fsl,imx8qm-spdif", + "fsl,imx8mm-spdif" - reg : Offset and length of the register set for the device. diff --git a/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt b/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt index c60a5732d29c15..f749e2744824d8 100644 --- a/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt +++ b/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt @@ -28,6 +28,7 @@ The compatible list for this generic sound card currently: (compatible with CS4271 and CS4272) "fsl,imx-audio-wm8962" + (compatible with Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt) "fsl,imx-audio-sgtl5000" (compatible with Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt) diff --git a/Documentation/devicetree/bindings/sound/imx-audio-ak4458.txt b/Documentation/devicetree/bindings/sound/imx-audio-ak4458.txt new file mode 100644 index 00000000000000..a442d3edd62d1b --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-ak4458.txt @@ -0,0 +1,30 @@ +Freescale i.MX audio complex with AK4458 DAC + +Required properties: + +- compatible : "fsl,imx-audio-ak4458", "fsl,imx-audio-ak4458-mq" +- model : The user-visible name of this sound complex +- audio-cpu : The phandle of CPU DAI +- audio-codec : The phandle of the AK4458 audio DAC +- audio-routing : A list of the connections between audio components. Each entry + is a pair of strings, the first being the connection's sink, the second being + the connection's source. Valid names could be power supplies, AK4458 pins, + and the jacks on the board. + +Example: + +sound { + compatible = "fsl,imx-audio-ak4458"; + model = "ak4458-audio"; + audio-cpu = <&sai1>; + audio-codec = <&codec>; + audio-routing = + "AOUTL1", "Playback", + "AOUTR1", "Playback", + "AOUTL2", "Playback", + "AOUTR2", "Playback", + "AOUTL3", "Playback", + "AOUTR3", "Playback", + "AOUTL4", "Playback", + "AOUTR4", "Playback"; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-ak4497.txt b/Documentation/devicetree/bindings/sound/imx-audio-ak4497.txt new file mode 100644 index 00000000000000..7eeeeeda74f500 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-ak4497.txt @@ -0,0 +1,27 @@ +Freescale i.MX audio complex with AK4497 DAC + +Required properties: + +- compatible : "fsl,imx-audio-ak4497", "fsl,imx-audio-ak4497-mq" +- model : The user-visible name of this sound complex +- audio-cpu : The phandle of CPU DAI +- audio-codec : The phandle of the ak4497 audio DAC +- audio-routing : A list of the connections between audio components. Each entry + is a pair of strings, the first being the connection's sink, the second being + the connection's source. Valid names could be power supplies, ak4497 pins, + and the jacks on the board. + +Example: + +sound { + compatible = "fsl,imx-audio-ak4497"; + model = "ak4497-audio"; + audio-cpu = <&sai3>; + audio-codec = <&codec>; + audio-routing = + "AOUTLN", "Playback", + "AOUTLP", "Playback", + "AOUTRN", "Playback", + "AOUTRP", "Playback", +}; + diff --git a/Documentation/devicetree/bindings/sound/imx-audio-ak5558.txt b/Documentation/devicetree/bindings/sound/imx-audio-ak5558.txt new file mode 100644 index 00000000000000..7b62fbb14f8d6a --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-ak5558.txt @@ -0,0 +1,30 @@ +Freescale i.MX audio complex with AK5558 ADC + +Required properties: + +- compatible : "fsl,imx-audio-ak5558", "fsl,imx-audio-ak5558-mq" +- model : The user-visible name of this sound complex +- audio-cpu : The phandle of CPU DAI +- audio-codec : The phandle of the AK5558 audio ADC +- audio-routing : A list of the connections between audio components. Each entry + is a pair of strings, the first being the connection's sink, the second being + the connection's source. Valid names could be power supplies, AK5558 pins, + and the jacks on the board. + +Example: + +sound { + compatible = "fsl,imx-audio-ak5558"; + model = "ak5558-audio"; + audio-cpu = <&sai1>; + audio-codec = <&codec>; + audio-routing = + "AIN1", "Capture", + "AIN2", "Capture", + "AIN3", "Capture", + "AIN4", "Capture", + "AIN5", "Capture", + "AIN6", "Capture", + "AIN7", "Capture", + "AIN8", "Capture"; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-cdnhdmi.txt b/Documentation/devicetree/bindings/sound/imx-audio-cdnhdmi.txt new file mode 100644 index 00000000000000..6d41217dd7be67 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-cdnhdmi.txt @@ -0,0 +1,16 @@ +Freescale i.MX audio complex with Cadence HDMI + +Required properties: +- compatible : "fsl,imx-audio-cdnhdmi", "fsl,imx8mq-evk-cdnhdmi" +- model : The user-visible name of this sound complex +- audio-cpu : The phandle of the i.MX SAI controller +- protocol : 0 is hdmi, 1 is dp. + +Example: + +sound-hdmi { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-hdmi"; + audio-cpu = <&sai4>; + protocol = <0>; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-cs42888.txt b/Documentation/devicetree/bindings/sound/imx-audio-cs42888.txt new file mode 100644 index 00000000000000..af746c4c81df21 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-cs42888.txt @@ -0,0 +1,25 @@ +Freescale i.MX audio complex with CS42888 codec + +Required properties: +- compatible : "fsl,imx-audio-cs42888" +- model : The user-visible name of this sound complex +- esai-controller : The phandle of the i.MX SSI controller +- audio-codec : The phandle of the CS42888 audio codec + +Optional properties: +- asrc-controller : The phandle of the i.MX ASRC controller +- audio-routing : A list of the connections between audio components. + Each entry is a pair of strings, the first being the connection's sink, + the second being the connection's source. Valid names could be power + supplies, CS42888 pins, and the jacks on the board: + +Example: + +sound { + compatible = "fsl,imx6q-sabresd-wm8962", + "fsl,imx-audio-wm8962"; + model = "cs42888-audio"; + esai-controller = <&esai>; + asrc-controller = <&asrc_p2p>; + audio-codec = <&codec>; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-mqs.txt b/Documentation/devicetree/bindings/sound/imx-audio-mqs.txt new file mode 100644 index 00000000000000..c0195c2028940b --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-mqs.txt @@ -0,0 +1,18 @@ +Freescale i.MX audio complex with mqs codec + +Required properties: +- compatible : "fsl,imx-audio-mqs", "fsl,imx8qm-lpddr4-arm2-mqs". +- model : The user-visible name of this sound complex +- cpu-dai : The phandle of the i.MX sai controller +- audio-codec : The phandle of the mqs audio codec + +Example: + +sound-mqs { + compatible = "fsl,imx6sx-sdb-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + cpu-dai = <&sai1>; + audio-codec = <&mqs>; +}; + diff --git a/Documentation/devicetree/bindings/sound/imx-audio-rpmsg.txt b/Documentation/devicetree/bindings/sound/imx-audio-rpmsg.txt new file mode 100644 index 00000000000000..3f015974ffebca --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-rpmsg.txt @@ -0,0 +1,13 @@ +Freescale i.MX audio complex with rpmsg devices + +Required properties: +- compatible : "fsl,imx-audio-rpmsg" +- model : The user-visible name of this sound complex +- cpu-dai : The phandle of the i.MX rpmsg i2s device. + +Example: +sound-rpmsg { + compatible = "fsl,imx-audio-rpmsg"; + model = "rpmsg-audio"; + cpu-dai = <&rpmsg_i2s>; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-si476x.txt b/Documentation/devicetree/bindings/sound/imx-audio-si476x.txt new file mode 100644 index 00000000000000..53cd34afe6b897 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-si476x.txt @@ -0,0 +1,24 @@ +Freescale i.MX audio complex with si476x codec + +Required properties: +- compatible : "fsl,imx-audio-si476x" +- model : The user-visible name of this sound complex +- ssi-controller : The phandle of the i.MX SSI controller + +- mux-int-port : The internal port of the i.MX audio muxer (AUDMUX) +- mux-ext-port : The external port of the i.MX audio muxer + +Note: The AUDMUX port numbering should start at 1, which is consistent with +hardware manual. + +Example: + +sound { + compatible = "fsl,imx-audio-si476x", + "fsl,imx-tuner-si476x"; + model = "imx-radio-si476x"; + + ssi-controller = <&ssi1>; + mux-int-port = <2>; + mux-ext-port = <5>; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-wm8524.txt b/Documentation/devicetree/bindings/sound/imx-audio-wm8524.txt new file mode 100644 index 00000000000000..b3e3c01464bd62 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-wm8524.txt @@ -0,0 +1,29 @@ +Freescale i.MX audio complex with WM8524 codec + +Required properties: + + - compatible : "fsl,imx-audio-wm8524" + + - model : The user-visible name of this sound complex + + - audio-cpu : The phandle of CPU DAI + + - audio-codec : The phandle of the WM8962 audio codec + + - audio-routing : A list of the connections between audio components. + Each entry is a pair of strings, the first being the + connection's sink, the second being the connection's + source. Valid names could be power supplies, WM8524 + pins, and the jacks on the board: + +Example: + +sound { + compatible = "fsl,imx-audio-wm8524"; + model = "wm8524-audio"; + audio-cpu = <&sai2>; + audio-codec = <&codec>; + audio-routing = + "Line Out Jack", "LINEVOUTL", + "Line Out Jack", "LINEVOUTR"; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt b/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt new file mode 100644 index 00000000000000..06bc12d4cc76ee --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt @@ -0,0 +1,61 @@ +Freescale i.MX audio complex with WM8962 codec + +Required properties: + + - compatible : "fsl,imx-audio-wm8962" + + - model : The user-visible name of this sound complex + + - cpu-dai : The phandle of CPU DAI + + - audio-codec : The phandle of the WM8962 audio codec + + - audio-routing : A list of the connections between audio components. + Each entry is a pair of strings, the first being the + connection's sink, the second being the connection's + source. Valid names could be power supplies, WM8962 + pins, and the jacks on the board: + + Power supplies: + * Mic Bias + + Board connectors: + * Mic Jack + * Headphone Jack + * Ext Spk + + - mux-int-port : The internal port of the i.MX audio muxer (AUDMUX) + + - mux-ext-port : The external port of the i.MX audio muxer + +Note: The AUDMUX port numbering should start at 1, which is consistent with +hardware manual. + +Optional properties: +- hp-det-gpios : The gpio pin to detect plug in/out event that happens to + Headphone jack. +- mic-det-gpios: The gpio pin to detect plug in/out event that happens to + Microphone jack. + +Example: + +sound { + compatible = "fsl,imx6q-sabresd-wm8962", + "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + cpu-dai = <&ssi2>; + audio-codec = <&codec>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "MICBIAS", "AMIC", + "IN3R", "MICBIAS", + "DMIC", "MICBIAS", + "DMICDAT", "DMIC"; + mux-int-port = <2>; + mux-ext-port = <3>; + hp-det-gpios = <&gpio7 8 1>; + mic-det-gpios = <&gpio1 9 1>; +}; diff --git a/Documentation/devicetree/bindings/sound/wm8962.txt b/Documentation/devicetree/bindings/sound/wm8962.txt index dcfa9a3369fde6..c624cebc53721b 100644 --- a/Documentation/devicetree/bindings/sound/wm8962.txt +++ b/Documentation/devicetree/bindings/sound/wm8962.txt @@ -13,6 +13,14 @@ Optional properties: of R51 (Class D Control 2) gets set, indicating that the speaker is in mono mode. + - amic-mono: This is a boolean property. If present, indicating that the + analog micphone is hardware mono input, the driver would enable monomix + for it. + + - dmic-mono: This is a boolean property. If present, indicating that the + digital micphone is hardware mono input, the driver would enable monomix + for it. + - mic-cfg : Default register value for R48 (Additional Control 4). If absent, the default should be the register default. diff --git a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt index 2d3264140cc5c5..32c4263daaaa43 100644 --- a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt +++ b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt @@ -10,6 +10,8 @@ Required properties: - "fsl,imx35-cspi" for SPI compatible with the one integrated on i.MX35 - "fsl,imx51-ecspi" for SPI compatible with the one integrated on i.MX51 - "fsl,imx53-ecspi" for SPI compatible with the one integrated on i.MX53 and later Soc + - "fsl,imx6ul-ecspi" ERR009165 fixed on i.MX6UL and later Soc + (https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf) - "fsl,imx8mq-ecspi" for SPI compatible with the one integrated on i.MX8M - reg : Offset and length of the register set for the device - interrupts : Should contain CSPI/eCSPI interrupt diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt index e71b81a41ac0e2..bdb771abc2fdab 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt @@ -14,6 +14,10 @@ Required properties: to fill the "ipg" blank. - spi-slave : spi slave mode support. In slave mode, add this attribute without value. In master mode, remove it. +- fsl,spi-only-use-cs1-sel : spi common code does not support use of CS signals + discontinuously. i.MX8DXL-EVK board only uses CS1 + without using CS0. Therefore, add this property to + re-config the chipselect value in the LPSPI driver. Examples: diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt index 69dc5d57b1efbe..7ba0472170e1b4 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt @@ -6,6 +6,8 @@ Required properties: "fsl,ls1021a-qspi", "fsl,ls2080a-qspi" or "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi" + "fsl,ls1012a-qspi" followed by "fsl,ls1021a-qspi" + "fsl,ls1088a-qspi" followed by "fsl,ls2080a-qspi" - reg : the first contains the register location and length, the second contains the memory mapping address and length - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory" diff --git a/Documentation/devicetree/bindings/thermal/imx8mm-thermal.txt b/Documentation/devicetree/bindings/thermal/imx8mm-thermal.txt new file mode 100644 index 00000000000000..06071dca7a005a --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/imx8mm-thermal.txt @@ -0,0 +1,18 @@ +* Thermal Monitoring Unit (TMU) on Freescale i.MX8MM SoC + +Required properties: +- compatible : Must be one of the following: + - "fsl,imx8mm-tmu", + - "fsl,imx8mp-tmu". +- reg : Address range of TMU registers. +- clocks : TMU's clock source. +- #thermal-sensor-cells : Should be 1 for SoC that supports multi-site sensor, + otherwise, should be 0. See ./thermal.txt for a description. + +Example: +tmu: tmu@30260000 { + compatible = "fsl,imx8mm-tmu"; + reg = <0x30260000 0x10000>; + clocks = <&clk IMX8MM_CLK_TMU_ROOT>; + #thermal-sensor-cells = <0>; +}; diff --git a/Documentation/devicetree/bindings/usb/cdns-usb3.txt b/Documentation/devicetree/bindings/usb/cdns-usb3.txt index b7dc606d37b524..13daee1b053b8d 100644 --- a/Documentation/devicetree/bindings/usb/cdns-usb3.txt +++ b/Documentation/devicetree/bindings/usb/cdns-usb3.txt @@ -1,45 +1,39 @@ -Binding for the Cadence USBSS-DRD controller +* Cadence USB3 Controller Required properties: - - reg: Physical base address and size of the controller's register areas. - Controller has 3 different regions: - - HOST registers area - - DEVICE registers area - - OTG/DRD registers area - - reg-names - register memory area names: - "xhci" - for HOST registers space - "dev" - for DEVICE registers space - "otg" - for OTG/DRD registers space - - compatible: Should contain: "cdns,usb3" - - interrupts: Interrupts used by cdns3 controller: - "host" - interrupt used by XHCI driver. - "peripheral" - interrupt used by device driver - "otg" - interrupt used by DRD/OTG part of driver +- compatible: "Cadence,usb3"; +- reg: base address and length of the registers +- interrupts: interrupt for the USB controller +- interrupt-parent: the interrupt parent for this module +- clocks: reference to the USB clock +- clock-names: the name of clocks +- cdns3,usbphy: reference to the USB PHY Optional properties: - - maximum-speed : valid arguments are "super-speed", "high-speed" and - "full-speed"; refer to usb/generic.txt - - dr_mode: Should be one of "host", "peripheral" or "otg". - - phys: reference to the USB PHY - - phy-names: from the *Generic PHY* bindings; - Supported names are: - - cdns3,usb2-phy - - cdns3,usb3-phy +- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg" +- extcon: extcon phandler for cdns3 device +- power-domains: the power domain for cdns3 controller and phy - - cdns,on-chip-buff-size : size of memory intended as internal memory for endpoints - buffers expressed in KB +Examples: -Example: - usb@f3000000 { - compatible = "cdns,usb3"; - interrupts = , - , - ; - interrupt-names = "host", "peripheral", "otg"; - reg = <0xf3000000 0x10000>, /* memory area for HOST registers */ - <0xf3010000 0x10000>, /* memory area for DEVICE registers */ - <0xf3020000 0x10000>; /* memory area for OTG/DRD registers */ - reg-names = "xhci", "dev", "otg"; - phys = <&usb2_phy>, <&usb3_phy>; - phy-names = "cdns3,usb2-phy", "cnds3,usb3-phy"; - }; +usbotg3: cdns3@5b110000 { + compatible = "Cadence,usb3"; + reg = <0x0 0x5B110000 0x0 0x10000>, + <0x0 0x5B130000 0x0 0x10000>, + <0x0 0x5B140000 0x0 0x10000>, + <0x0 0x5B160000 0x0 0x40000>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&clk IMX8QM_USB3_LPM_CLK>, + <&clk IMX8QM_USB3_BUS_CLK>, + <&clk IMX8QM_USB3_ACLK>, + <&clk IMX8QM_USB3_IPG_CLK>, + <&clk IMX8QM_USB3_CORE_PCLK>; + clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk", + "usb3_ipg_clk", "usb3_core_pclk"; + power-domains = <&pd_conn_usb2>; + cdns3,usbphy = <&usbphynop1>; + dr_mode = "otg"; + extcon = <&typec_ptn5150>; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt index cfc9f40ab64198..5dc237f5994028 100644 --- a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt +++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt @@ -86,6 +86,7 @@ Optional properties: case, the "idle" state needs to pull down the data and strobe pin and the "active" state needs to pull up the strobe pin. - pinctrl-n: alternate pin modes +- ci-disable-lpm: Some chipidea hardware need to disable low power mode i.mx specific properties - fsl,usbmisc: phandler of non-core register device, with one @@ -96,6 +97,13 @@ i.mx specific properties It's recommended to specify the over current polarity. - power-active-high: power signal polarity is active high - external-vbus-divider: enables off-chip resistor divider for Vbus +- picophy,pre-emp-curr-control: HS Transmitter Pre-Emphasis Current + Control. This signal controls the amount of current sourced to the + USB_OTG*_DP and USB_OTG*_DN pins after a J-to-K or K-to-J transition. + Details can refer to TXPREEMPAMPTUNE0 bits of USBNC_n_PHY_CFG1. +- picophy,dc-vol-level-adjust: HS DC Voltage Level Adjustment. + Adjust the high-speed transmitter DC level voltage, details can refer + to TXVREFTUNE0 bits of USBNC_n_PHY_CFG1. Example: diff --git a/Documentation/devicetree/bindings/usb/dwc3-imx8mp.txt b/Documentation/devicetree/bindings/usb/dwc3-imx8mp.txt new file mode 100644 index 00000000000000..bf7b2de9015b11 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/dwc3-imx8mp.txt @@ -0,0 +1,54 @@ +NXP imx8M Plus DWC3 glue logic + +This file documents the parameters for the dwc3-imx8mp driver. +This driver controls the glue logic used to configure the dwc3 core on +imx8mp based platforms. + +Required properties: + - compatible : must be "fsl,imx8mp-dwc3" + - reg : glue logic base address and size + - clocks : A list of phandle + clock-specifier pairs for the + clocks listed in clock-names + - clock-names : Should contain the following: + "hsio" hsio root clock + "bus" System bus AXI clock + "suspend" Suspend clock, used for wakeup. + - interrupts : specifies interrupt from controller wrapper used + to wakeup from low power/susepnd state. + +Sub-nodes: +The dwc3 core should be added as subnode to imx8mp DWC3 glue as shown in the +example below. The DT binding details of dwc3 can be found in: +Documentation/devicetree/bindings/usb/dwc3.txt + +Example: + + usb3_0: usb@32f10100 { + compatible = "fsl,imx8mp-dwc3"; + reg = <0 0x32f10100 0 0x8>; + clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>, + <&clk IMX8MP_CLK_USB_ROOT>; + clock-names = "bus", "sleep"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; + interrupts = ; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_dwc3_0: dwc3@38100000 { + compatible = "snps,dwc3"; + reg = <0 0x38100000 0 0x10000>; + interrupts = ; + phys = <&usb3_phy0>, <&usb3_phy0>; + phy-names = "usb2-phy", "usb3-phy"; + xhci-no-64bit-support; + usb3-resume-missing-cas; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + status = "disabled"; + }; + + }; diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index c977a3ba2f35c0..70876c55a11c36 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -4,7 +4,21 @@ DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties as described in 'usb/generic.txt' Required properties: - - compatible: must be "snps,dwc3" + - compatible: must be "snps,dwc3" and (if applicable) may contain a + chip-specific compatible string in front of it to allow dwc3 driver be + able to update cache type configuration accordingly, otherwise + Layerscape SoC will encounter USB init failure when adding property + dma-coherent on device tree. + Example: + * "fsl,ls1012a-dwc3", "snps,dwc3" + * "fsl,ls1021a-dwc3", "snps,dwc3" + * "fsl,ls1028a-dwc3", "snps,dwc3" + * "fsl,ls1043a-dwc3", "snps,dwc3" + * "fsl,ls1046a-dwc3", "snps,dwc3" + * "fsl,ls1088a-dwc3", "snps,dwc3" + * "fsl,ls2088a-dwc3", "snps,dwc3" + * "fsl,lx2160a-dwc3", "snps,dwc3" + - reg : Address and length of the register set for the device - interrupts: Interrupts used by the dwc3 controller. - clock-names: should contain "ref", "bus_early", "suspend" @@ -111,6 +125,10 @@ Optional properties: more than one value, which means undefined length INCR burst type enabled. The values can be 1, 4, 8, 16, 32, 64, 128 and 256. + - snps,host-vbus-glitches: Power off all Root Hub ports immediately after + setting host mode to avoid vbus (negative) glitch happen in later + xhci reset. And the vbus will back to 5V automatically when reset done. + - in addition all properties from usb-xhci.txt from the current directory are supported as well diff --git a/Documentation/devicetree/bindings/usb/typec-switch-gpio.txt b/Documentation/devicetree/bindings/usb/typec-switch-gpio.txt new file mode 100644 index 00000000000000..6288867c365f4e --- /dev/null +++ b/Documentation/devicetree/bindings/usb/typec-switch-gpio.txt @@ -0,0 +1,31 @@ +Typec orientation switch via a GPIO +----------------------------------- + +Required properties: +- compatible: should be set one of following: + - "nxp,ptn36043" or "nxp,cbtl04gp" for NXP Type-C SuperSpeed + active switch. + +- gpios: the GPIO used to switch the super speed active channel, + GPIO_ACTIVE_HIGH: GPIO state high for cc1; + GPIO_ACTIVE_LOW: GPIO state low for cc1. +- orientation-switch: must be present. + +Required sub-node: +- port: specify the remote endpoint of typec switch consumer. + +Example: + +ptn36043 { + compatible = "nxp,ptn36043"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ss_sel>; + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + orientation-switch; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt index b49b819571f9c5..170c56477c974a 100644 --- a/Documentation/devicetree/bindings/usb/usb-xhci.txt +++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt @@ -42,6 +42,8 @@ Optional properties: - quirk-broken-port-ped: set if the controller has broken port disable mechanism - imod-interval-ns: default interrupt moderation interval is 5000ns - phys : see usb-hcd.yaml in the current directory + - usb3-resume-missing-cas: set if the CAS(Cold Attach Status) may lose in case + device plugged in while system sleep. additionally the properties from usb-hcd.yaml (in the current directory) are supported. diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 967e78c5ec0a12..fa5e531928df8c 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -461,6 +461,8 @@ patternProperties: description: Intersil "^issi,.*": description: Integrated Silicon Solutions Inc. + "^ite,.*": + description: ITE Tech. Inc. "^itead,.*": description: ITEAD Intelligent Systems Co.Ltd "^iwave,.*": @@ -603,6 +605,8 @@ patternProperties: description: MiraMEMS Sensing Technology Co., Ltd. "^mitsubishi,.*": description: Mitsubishi Electric Corporation + "^mixel,.*": + description: Mixel, Inc "^mosaixtech,.*": description: Mosaix Technologies, Inc. "^motorola,.*": diff --git a/Documentation/ioctl/ioctl-number.rst b/Documentation/ioctl/ioctl-number.rst index bef79cd4c6b4d3..c1f0d574fec680 100644 --- a/Documentation/ioctl/ioctl-number.rst +++ b/Documentation/ioctl/ioctl-number.rst @@ -180,6 +180,7 @@ Code Seq# Include File Comments 'R' 00-1F linux/random.h conflict! 'R' 01 linux/rfkill.h conflict! 'R' C0-DF net/bluetooth/rfcomm.h +'R' E0 uapi/linux/fsl_mc.h 'S' all linux/cdrom.h conflict! 'S' 80-81 scsi/scsi_ioctl.h conflict! 'S' 82-FF scsi/scsi.h conflict! diff --git a/Documentation/media/uapi/v4l/pixfmt-packed-yuv.rst b/Documentation/media/uapi/v4l/pixfmt-packed-yuv.rst index 41b60fae703a70..9af6976b578cb2 100644 --- a/Documentation/media/uapi/v4l/pixfmt-packed-yuv.rst +++ b/Documentation/media/uapi/v4l/pixfmt-packed-yuv.rst @@ -17,7 +17,8 @@ Description =========== Similar to the packed RGB formats these formats store the Y, Cb and Cr -component of each pixel in one 16 or 32 bit word. +component of each pixel next to each other in memory. They occupy 16, 24 or 32 +bits per pixel. .. raw:: latex @@ -154,9 +155,40 @@ component of each pixel in one 16 or 32 bit word. - Cb\ :sub:`5` - Cb\ :sub:`4` - Cb\ :sub:`3` - - :cspan:`15` + - + * .. _V4L2-PIX-FMT-YUV24: + + - ``V4L2_PIX_FMT_YUV24`` + - 'YUV3' + + - Y'\ :sub:`7` + - Y'\ :sub:`6` + - Y'\ :sub:`5` + - Y'\ :sub:`4` + - Y'\ :sub:`3` + - Y'\ :sub:`2` + - Y'\ :sub:`1` + - Y'\ :sub:`0` + + - Cb\ :sub:`7` + - Cb\ :sub:`6` + - Cb\ :sub:`5` + - Cb\ :sub:`4` + - Cb\ :sub:`3` + - Cb\ :sub:`2` + - Cb\ :sub:`1` + - Cb\ :sub:`0` + - Cr\ :sub:`7` + - Cr\ :sub:`6` + - Cr\ :sub:`5` + - Cr\ :sub:`4` + - Cr\ :sub:`3` + - Cr\ :sub:`2` + - Cr\ :sub:`1` + - Cr\ :sub:`0` + - * .. _V4L2-PIX-FMT-YUV32: - ``V4L2_PIX_FMT_YUV32`` diff --git a/Documentation/networking/sfp-phylink.rst b/Documentation/networking/sfp-phylink.rst index a5e00a159d214e..d753a309f9d120 100644 --- a/Documentation/networking/sfp-phylink.rst +++ b/Documentation/networking/sfp-phylink.rst @@ -251,7 +251,8 @@ this documentation. phylink_mac_change(priv->phylink, link_is_up); where ``link_is_up`` is true if the link is currently up or false - otherwise. + otherwise. If a MAC is unable to provide these interrupts, then + it should set ``priv->phylink_config.pcs_poll = true;`` in step 9. 11. Verify that the driver does not call:: diff --git a/Documentation/security/keys/secure-key.rst b/Documentation/security/keys/secure-key.rst new file mode 100644 index 00000000000000..a33ffd09d7bdd6 --- /dev/null +++ b/Documentation/security/keys/secure-key.rst @@ -0,0 +1,67 @@ +========== +Secure Key +========== + +Secure key is the new type added to kernel key ring service. +Secure key is a symmetric type key of minimum length 32 bytes +and with maximum possible length to be 128 bytes. It is produced +in kernel using the CAAM crypto engine. Userspace can only see +the blob for the corresponding key. All the blobs are displayed +or loaded in hex ascii. + +Secure key can be created on platforms which supports CAAM +hardware block. Secure key can also be used as a master key to +create the encrypted keys along with the existing key types in +kernel. + +Secure key uses CAAM hardware to generate the key and blobify its +content for userspace. Generated blobs are tied up with the hardware +secret key stored in CAAM, hence the same blob will not be able to +de-blobify with the different secret key on another machine. + +Usage:: + + keyctl add secure "new " + keyctl load secure "load " + keyctl print + +"keyctl add secure" option will create the random data of the +specified key len using CAAM and store it as a key in kernel. +Key contents will be displayed as blobs to the user in hex ascii. +User can input key len from 32 bytes to 128 bytes. + +"keyctl load secure" option will load the blob contents. In kernel, +key will be deirved using input blob and CAAM, along with the secret +key stored in CAAM. + +"keyctl print" will return the hex string of the blob corresponding to +key_id. Returned blob will be of key_len + 48 bytes. Extra 48 bytes are +the header bytes added by the CAAM. + +Example of secure key usage:: + +1. Create the secure key with name kmk-master of length 32 bytes:: + + $ keyctl add secure kmk-master "new 32" @u + 46001928 + + $keyctl show + Session Keyring + 1030783626 --alswrv 0 65534 keyring: _uid_ses.0 + 695927745 --alswrv 0 65534 \_ keyring: _uid.0 + 46001928 --als-rv 0 0 \_ secure: kmk-master + +2. Print the blob contents for the kmk-master key:: + + $ keyctl print 46001928 + d9743445b640f3d59c1670dddc0bc9c2 + 34fc9aab7dd05c965e6120025012f029b + 07faa4776c4f6ed02899e35a135531e9a + 6e5c2b51132f9d5aef28f68738e658296 + 3fe583177cfe50d2542b659a13039 + + $ keyctl pipe 46001928 > secure_key.blob + +3. Load the blob in the user key ring:: + + $ keyctl load secure kmk-master "load 'cat secure_key.blob'" @u diff --git a/MAINTAINERS b/MAINTAINERS index 1407008df74914..b47719da52b723 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6575,6 +6575,14 @@ F: drivers/ptp/ptp_qoriq_debugfs.c F: include/linux/fsl/ptp_qoriq.h F: Documentation/devicetree/bindings/ptp/ptp-qoriq.txt +FREESCALE QORIQ PPFE ETHERNET DRIVER +M: Anji Jagarlmudi +M: Calvin Johnson +L: netdev@vger.kernel.org +S: Maintained +F: drivers/staging/fsl_ppfe +F: Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt + FREESCALE QUAD SPI DRIVER M: Han Xu L: linux-spi@vger.kernel.org @@ -6589,6 +6597,12 @@ F: drivers/soc/fsl/qe/ F: include/soc/fsl/*qe*.h F: include/soc/fsl/*ucc*.h +FREESCALE QEIC DRIVERS +M: Qiang Zhao +L: linux-kernel@vger.kernel.org +S: Maintained +F: drivers/irqchip/irq-qeic.c + FREESCALE QUICC ENGINE UCC ETHERNET DRIVER M: Li Yang L: netdev@vger.kernel.org @@ -8765,6 +8779,7 @@ L: jailhouse-dev@googlegroups.com S: Maintained F: arch/x86/kernel/jailhouse.c F: arch/x86/include/asm/jailhouse_para.h +F: drivers/virt/jailhouse_dbgcon.c JC42.4 TEMPERATURE SENSOR DRIVER M: Guenter Roeck @@ -9065,6 +9080,18 @@ F: include/keys/trusted-type.h F: security/keys/trusted.c F: include/keys/trusted.h +KEYS-SECURE +M: Udit Agarwal +R: Sahil Malhotra +L: linux-security-module@vger.kernel.org +L: keyrings@vger.kernel.org +S: Supported +F: include/keys/secure-type.h +F: security/keys/secure_key.c +F: security/keys/securekey_desc.c +F: security/keys/securekey_desc.h +F: security/keys/encrypted-keys/masterkey_secure.c + KEYS/KEYRINGS: M: David Howells M: Jarkko Sakkinen @@ -10825,6 +10852,7 @@ M: Microchip Linux Driver Support L: netdev@vger.kernel.org S: Supported F: drivers/net/ethernet/mscc/ +F: include/soc/mscc/ocelot* MICROSOFT SURFACE PRO 3 BUTTON DRIVER M: Chen Yu @@ -12438,6 +12466,16 @@ L: linux-arm-kernel@lists.infradead.org S: Maintained F: drivers/pci/controller/dwc/*layerscape* +PCI DRIVER FOR NXP LAYERSCAPE GEN4 CONTROLLER +M: Hou Zhiqiang +M: Xiaowei Bao +L: linux-pci@vger.kernel.org +L: linux-arm-kernel@lists.infradead.org +S: Maintained +F: Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt +F: drivers/pci/controller/mobibeil/pcie-layerscape-gen4.c +F: drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c + PCI DRIVER FOR GENERIC OF HOSTS M: Will Deacon L: linux-pci@vger.kernel.org @@ -12478,10 +12516,11 @@ F: drivers/ntb/hw/mscc/ PCI DRIVER FOR MOBIVEIL PCIE IP M: Karthikeyan Mitran M: Hou Zhiqiang +M: Xiaowei Bao L: linux-pci@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/pci/mobiveil-pcie.txt -F: drivers/pci/controller/pcie-mobiveil.c +F: drivers/pci/controller/mobiveil/pcie-mobiveil* PCI DRIVER FOR MVEBU (Marvell Armada 370 and Armada XP SOC support) M: Thomas Petazzoni @@ -13437,6 +13476,9 @@ S: Maintained F: drivers/bus/fsl-mc/ F: Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt F: Documentation/networking/device_drivers/freescale/dpaa2/overview.rst +F: Documentation/networking/dpaa2/overview.rst +F: include/uapi/linux/fsl_mc.h +F: Documentation/ABI/stable/sysfs-bus-fsl-mc QT1010 MEDIA DRIVER M: Antti Palosaari @@ -17351,6 +17393,14 @@ S: Maintained F: drivers/input/serio/userio.c F: include/uapi/linux/userio.h +VITESSE FELIX ETHERNET SWITCH DRIVER +M: Vladimir Oltean +M: Claudiu Manoil +L: netdev@vger.kernel.org +S: Maintained +F: drivers/net/dsa/ocelot/* +F: net/dsa/tag_ocelot.c + VIVID VIRTUAL VIDEO DRIVER M: Hans Verkuil L: linux-media@vger.kernel.org diff --git a/Makefile b/Makefile index aece56450bd9df..418814b108ae64 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 5 PATCHLEVEL = 4 -SUBLEVEL = 62 +SUBLEVEL = 63 EXTRAVERSION = NAME = Kleptomaniac Octopus diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b21b3a64641a76..70250bd6f9615c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -435,8 +435,18 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-rex-basic.dtb \ imx6dl-riotboard.dtb \ imx6dl-sabreauto.dtb \ + imx6dl-sabreauto-enetirq.dtb \ + imx6dl-sabreauto-flexcan1.dtb \ + imx6dl-sabreauto-ecspi.dtb \ + imx6dl-sabreauto-gpmi-weim.dtb \ + imx6dl-sabreauto-pcie.dtb \ imx6dl-sabrelite.dtb \ imx6dl-sabresd.dtb \ + imx6dl-sabresd-ldo.dtb \ + imx6dl-sabresd-btwifi.dtb \ + imx6dl-sabresd-hdcp.dtb \ + imx6dl-sabresd-enetirq.dtb \ + imx6dl-sabresd-pcie.dtb \ imx6dl-savageboard.dtb \ imx6dl-ts4900.dtb \ imx6dl-ts7970.dtb \ @@ -514,8 +524,19 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-pistachio.dtb \ imx6q-rex-pro.dtb \ imx6q-sabreauto.dtb \ + imx6q-sabreauto-enetirq.dtb \ + imx6q-sabreauto-flexcan1.dtb \ + imx6q-sabreauto-ecspi.dtb \ + imx6q-sabreauto-gpmi-weim.dtb \ + imx6q-sabreauto-pcie.dtb \ imx6q-sabrelite.dtb \ imx6q-sabresd.dtb \ + imx6q-sabresd-ldo.dtb \ + imx6q-sabresd-btwifi.dtb \ + imx6q-sabresd-hdcp.dtb \ + imx6q-sabresd-uart.dtb \ + imx6q-sabresd-enetirq.dtb \ + imx6q-sabresd-pcie.dtb \ imx6q-savageboard.dtb \ imx6q-sbc6x.dtb \ imx6q-tbs2910.dtb \ @@ -541,7 +562,13 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6qp-nitrogen6_som2.dtb \ imx6qp-phytec-mira-rdk-nand.dtb \ imx6qp-sabreauto.dtb \ + imx6qp-sabreauto-flexcan1.dtb \ + imx6qp-sabreauto-ecspi.dtb \ + imx6qp-sabreauto-gpmi-weim.dtb \ imx6qp-sabresd.dtb \ + imx6qp-sabresd-ldo.dtb \ + imx6qp-sabresd-btwifi.dtb \ + imx6qp-sabresd-hdcp.dtb \ imx6qp-tx6qp-8037.dtb \ imx6qp-tx6qp-8037-mb7.dtb \ imx6qp-tx6qp-8137.dtb \ @@ -550,21 +577,45 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6qp-zii-rdu2.dtb dtb-$(CONFIG_SOC_IMX6SL) += \ imx6sl-evk.dtb \ + imx6sl-evk-ldo.dtb \ + imx6sl-evk-csi.dtb \ + imx6sl-evk-uart.dtb \ + imx6sl-evk-btwifi.dtb \ imx6sl-warp.dtb dtb-$(CONFIG_SOC_IMX6SLL) += \ - imx6sll-evk.dtb + imx6sll-evk.dtb \ + imx6sll-evk-reva.dtb \ + imx6sll-evk-btwifi.dtb dtb-$(CONFIG_SOC_IMX6SX) += \ imx6sx-nitrogen6sx.dtb \ imx6sx-sabreauto.dtb \ imx6sx-sdb-reva.dtb \ + imx6sx-sdb-reva-ldo.dtb \ imx6sx-sdb-sai.dtb \ imx6sx-sdb.dtb \ + imx6sx-sdb-ldo.dtb \ + imx6sx-sdb-emmc.dtb \ + imx6sx-sdb-lcdif1.dtb \ + imx6sx-sdb-m4.dtb \ + imx6sx-sdb-mqs.dtb \ + imx6sx-sdb-btwifi.dtb \ imx6sx-softing-vining-2000.dtb \ imx6sx-udoo-neo-basic.dtb \ imx6sx-udoo-neo-extended.dtb \ imx6sx-udoo-neo-full.dtb dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-14x14-evk.dtb \ + imx6ul-14x14-evk-csi.dtb \ + imx6ul-14x14-evk-emmc.dtb \ + imx6ul-14x14-evk-btwifi.dtb \ + imx6ul-14x14-evk-btwifi-oob.dtb \ + imx6ul-14x14-evk-ecspi-slave.dtb \ + imx6ul-14x14-evk-ecspi.dtb \ + imx6ul-14x14-evk-gpmi-weim.dtb \ + imx6ul-9x9-evk.dtb \ + imx6ul-9x9-evk-ldo.dtb \ + imx6ul-9x9-evk-btwifi.dtb \ + imx6ul-9x9-evk-btwifi-oob.dtb \ imx6ul-ccimx6ulsbcexpress.dtb \ imx6ul-ccimx6ulsbcpro.dtb \ imx6ul-geam.dtb \ @@ -581,12 +632,23 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-tx6ul-0011.dtb \ imx6ul-tx6ul-mainboard.dtb \ imx6ull-14x14-evk.dtb \ + imx6ull-14x14-evk-emmc.dtb \ + imx6ull-14x14-evk-btwifi.dtb \ + imx6ull-14x14-evk-btwifi-oob.dtb \ + imx6ull-14x14-evk-gpmi-weim.dtb \ + imx6ull-9x9-evk.dtb \ + imx6ull-9x9-evk-ldo.dtb \ + imx6ull-9x9-evk-btwifi.dtb \ + imx6ull-9x9-evk-btwifi-oob.dtb \ imx6ull-colibri-eval-v3.dtb \ imx6ull-colibri-wifi-eval-v3.dtb \ imx6ull-phytec-segin-ff-rdk-nand.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-phytec-segin-lc-rdk-nand.dtb \ - imx6ulz-14x14-evk.dtb + imx6ulz-14x14-evk.dtb \ + imx6ulz-14x14-evk-btwifi.dtb \ + imx6ulz-14x14-evk-gpmi-weim.dtb \ + imx6ulz-14x14-evk-emmc.dtb dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-cl-som-imx7.dtb \ imx7d-colibri-emmc-eval-v3.dtb \ @@ -598,15 +660,34 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-pico-pi.dtb \ imx7d-sbc-imx7.dtb \ imx7d-sdb.dtb \ + imx7d-sdb-epdc.dtb \ + imx7d-sdb-mipi-dsi.dtb \ + imx7d-sdb-gpmi-weim.dtb \ + imx7d-sdb-m4.dtb \ + imx7d-sdb-qspi.dtb \ imx7d-sdb-reva.dtb \ imx7d-sdb-sht11.dtb \ + imx7d-sdb-usd-wifi.dtb \ + imx7d-12x12-lpddr3-val.dtb \ + imx7d-12x12-lpddr3-val-sai.dtb \ imx7d-zii-rmu2.dtb \ imx7d-zii-rpu2.dtb \ imx7s-colibri-eval-v3.dtb \ imx7s-mba7.dtb \ imx7s-warp.dtb dtb-$(CONFIG_SOC_IMX7ULP) += \ - imx7ulp-evk.dtb + imx7ulp-evk.dtb \ + imx7ulp-evk-ft5416.dtb \ + imx7ulp-evk-mipi.dtb \ + imx7ulp-evkb.dtb \ + imx7ulp-evkb-emmc.dtb \ + imx7ulp-evkb-sd1.dtb \ + imx7ulp-evkb-spi-slave.dtb \ + imx7ulp-evkb-sensors-to-i2c5.dtb \ + imx7ulp-evkb-lpuart.dtb \ + imx7ulp-evkb-mipi.dtb \ + imx7ulp-evkb-rm68200-wxga.dtb \ + imx7ulp-evkb-rm68191-qhd.dtb dtb-$(CONFIG_SOC_LS1021A) += \ ls1021a-moxa-uc-8410a.dtb \ ls1021a-qds.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-sabreauto-ecspi.dts b/arch/arm/boot/dts/imx6dl-sabreauto-ecspi.dts new file mode 100644 index 00000000000000..d468a553565786 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-sabreauto-ecspi.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2014 Freescale Semiconductor, Inc. + + +#include "imx6dl-sabreauto.dts" + +&ecspi1 { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&i2c3 { + /* pin conflict with ecspi1 */ + status = "disabled"; +}; + +&uart3 { + /* the uart3 depends on the i2c3, so disable it too. */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-sabreauto-enetirq.dts b/arch/arm/boot/dts/imx6dl-sabreauto-enetirq.dts new file mode 100644 index 00000000000000..75c798f7616a9f --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-sabreauto-enetirq.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2013 Freescale Semiconductor, Inc. +// Copyright 2019 NXP + +#include "imx6dl-sabreauto.dts" + +&fec { + pinctrl-0 = <&pinctrl_enet &pinctrl_enet_irq>; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; +}; + +&mlb { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6dl-sabreauto-flexcan1.dts b/arch/arm/boot/dts/imx6dl-sabreauto-flexcan1.dts new file mode 100644 index 00000000000000..f101f7c7b7b0df --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-sabreauto-flexcan1.dts @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dl-sabreauto.dts" + +&can1{ + status = "okay"; +}; + +&fec { + /* pin conflict with flexcan1 */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6dl-sabreauto-gpmi-weim.dts b/arch/arm/boot/dts/imx6dl-sabreauto-gpmi-weim.dts new file mode 100644 index 00000000000000..8990519be86170 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-sabreauto-gpmi-weim.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2014 Freescale Semiconductor, Inc. + + +#include "imx6dl-sabreauto.dts" + +&ecspi1 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&gpmi { + status = "okay"; +}; + +&i2c3 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&uart3 { + /* pin conflict with gpmi and weim */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&weim { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-sabreauto-pcie.dts b/arch/arm/boot/dts/imx6dl-sabreauto-pcie.dts new file mode 100644 index 00000000000000..88fc15b1a9de3b --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-sabreauto-pcie.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx6dl-sabreauto.dts" + +&pcie { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts index ff3283c83a3944..be38a92c6a90e0 100644 --- a/arch/arm/boot/dts/imx6dl-sabreauto.dts +++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts @@ -26,3 +26,21 @@ 396000 1175000 >; }; + +&ldb { + lvds-channel@0 { + crtc = "ipu1-di0"; + }; + + lvds-channel@1 { + crtc = "ipu1-di1"; + }; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-sabresd-btwifi.dts b/arch/arm/boot/dts/imx6dl-sabresd-btwifi.dts new file mode 100644 index 00000000000000..ac57fffe74c7a0 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-sabresd-btwifi.dts @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dl-sabresd.dts" +#include "imx6qdl-sabresd-btwifi.dtsi" diff --git a/arch/arm/boot/dts/imx6dl-sabresd-enetirq.dts b/arch/arm/boot/dts/imx6dl-sabresd-enetirq.dts new file mode 100644 index 00000000000000..5aee10ff88b908 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-sabresd-enetirq.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2014 Freescale Semiconductor, Inc. +// Copyright 2019 NXP + +#include "imx6dl-sabresd.dts" + +&fec { + pinctrl-0 = <&pinctrl_enet &pinctrl_enet_irq>; + interrupts-extended = <&gpio1 6 0x4>, <&gpc 0 119 0x4>; + fsl,err006687-workaround-present; +}; + +&i2c3 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6dl-sabresd-hdcp.dts b/arch/arm/boot/dts/imx6dl-sabresd-hdcp.dts new file mode 100644 index 00000000000000..2c7f04456cbbad --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-sabresd-hdcp.dts @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2013-2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dl-sabresd.dts" + +&gpc { + /* use ldo-enable, u-boot will check it and configure */ + fsl,ldo-bypass = <0>; +}; + +&hdmi_video { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_hdcp>; + fsl,hdcp; +}; + +&i2c2 { + status = "disable"; +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_pu { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff --git a/arch/arm/boot/dts/imx6dl-sabresd-ldo.dts b/arch/arm/boot/dts/imx6dl-sabresd-ldo.dts new file mode 100644 index 00000000000000..e5c623d85e4e35 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-sabresd-ldo.dts @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dl-sabresd.dts" + +&gpc { + /* use ldo-enable, u-boot will check it and configure */ + fsl,ldo-bypass = <0>; +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_pu { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; + +&wdog1 { + status = "okay"; +}; + +&wdog2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6dl-sabresd-pcie.dts b/arch/arm/boot/dts/imx6dl-sabresd-pcie.dts new file mode 100644 index 00000000000000..c57558c815d9f2 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-sabresd-pcie.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx6dl-sabresd.dts" + +&pcie { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts index cd6bbf22a16f08..7b253d13b02dc4 100644 --- a/arch/arm/boot/dts/imx6dl-sabresd.dts +++ b/arch/arm/boot/dts/imx6dl-sabresd.dts @@ -12,7 +12,163 @@ compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl"; }; +&battery { + offset-charger = <1485>; + offset-discharger = <1464>; + offset-usb-charger = <1285>; +}; + +&iomuxc { + epdc { + pinctrl_epdc_elan_touch: epdc_elan_touch_grp { + fsl,pins = < + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x80000000 + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x80000000 + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 + >; + }; + + pinctrl_epdc_0: epdcgrp-0 { + fsl,pins = < + MX6QDL_PAD_EIM_A16__EPDC_DATA00 0x80000000 + MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0x80000000 + MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x80000000 + MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0x80000000 + MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0x80000000 + MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0x80000000 + MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0x80000000 + MX6QDL_PAD_EIM_RW__EPDC_DATA07 0x80000000 + MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0x80000000 + MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x80000000 + MX6QDL_PAD_EIM_A23__EPDC_GDOE 0x80000000 + MX6QDL_PAD_EIM_A24__EPDC_GDRL 0x80000000 + MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0x80000000 + MX6QDL_PAD_EIM_D27__EPDC_SDOE 0x80000000 + MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0x80000000 + MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x80000000 + MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0x80000000 + MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0x80000000 + MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0x80000000 + MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0x80000000 + >; + }; + }; +}; + +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc_0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "okay"; +}; + +&i2c3 { + elan@10 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc_elan_touch>; + compatible = "elan,elan-touch"; + reg = <0x10>; + interrupt-parent = <&gpio3>; + interrupts = <28 IRQ_TYPE_EDGE_FALLING>; + gpio_elan_cs = <&gpio2 18 0>; + gpio_elan_rst = <&gpio3 8 0>; + gpio_intr = <&gpio3 28 0>; + status = "okay"; + }; + + max17135@48 { + compatible = "maxim,max17135"; + reg = <0x48>; + vneg_pwrup = <1>; + gvee_pwrup = <1>; + vpos_pwrup = <2>; + gvdd_pwrup = <1>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <1>; + vneg_pwrdn = <1>; + SENSOR-supply = <®_sensors>; + gpio_pmic_pwrgood = <&gpio2 21 0>; + gpio_pmic_vcom_ctrl = <&gpio3 17 0>; + gpio_pmic_wakeup = <&gpio3 20 0>; + gpio_pmic_v3p3 = <&gpio2 20 0>; + gpio_pmic_intr = <&gpio2 25 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* Real max: -500000 */ + regulator-max-microvolt = <4325000>; + /* Real min: -4325000 */ + regulator-min-microvolt = <500000>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; +}; + &ipu1_csi1_from_ipu1_csi1_mux { clock-lanes = <0>; data-lanes = <1 2>; }; + +&ldb { + lvds-channel@0 { + crtc = "ipu1-di0"; + }; + + lvds-channel@1 { + crtc = "ipu1-di1"; + }; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&pxp { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi old mode 100644 new mode 100755 index 2ed10310a7b7b7..845adeed678557 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -38,9 +38,13 @@ <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, <&clks IMX6QDL_CLK_STEP>, <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; + <&clks IMX6QDL_CLK_PLL1_SYS>, + <&clks IMX6QDL_CLK_PLL1>, + <&clks IMX6QDL_PLL1_BYPASS>, + <&clks IMX6QDL_PLL1_BYPASS_SRC>; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1", + "pll1_bypass", "pll1_bypass_src"; arm-supply = <®_arm>; pu-supply = <®_pu>; soc-supply = <®_soc>; @@ -77,30 +81,105 @@ }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + soc { - ocram: sram@900000 { + busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6QDL_CLK_PLL2_BUS>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_PLL2_198M>, <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>, <&clks IMX6QDL_CLK_PERIPH>, + <&clks IMX6QDL_CLK_PERIPH_PRE>, <&clks IMX6QDL_CLK_PERIPH_CLK2>, + <&clks IMX6QDL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6QDL_CLK_OSC>, + <&clks IMX6QDL_CLK_AXI_ALT_SEL>, <&clks IMX6QDL_CLK_AXI_SEL> , + <&clks IMX6QDL_CLK_PLL3_PFD1_540M>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", + "pll3_usb_otg", "periph", "periph_pre", "periph_clk2", + "periph_clk2_sel", "osc", "axi_alt_sel", "axi_sel", + "pll3_pfd1_540m"; + interrupts = <0 107 0x4>, <0 112 0x4>; + interrupt-names = "irq_busfreq_0", "irq_busfreq_1"; + fsl,max_ddr_freq = <400000000>; + }; + + ocram: sram@905000 { compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; + reg = <0x905000 0x1B000>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; + ocram_optee: sram@918000 { + compatible = "fsl,optee-lpm-sram"; + reg = <0x918000 0x8000>; + overw_reg = <&ocram 0x905000 0x13000>; + }; + + gpu: gpu@00130000 { + compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu"; + reg = <0x00130000 0x4000>, <0x00134000 0x4000>, + <0x10000000 0x0>, <0x0 0x8000000>; + reg-names = "iobase_3d", "iobase_2d", + "phys_baseaddr", "contiguous_mem"; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>, + <0 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_3d", "irq_2d"; + clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, <&clks IMX6QDL_CLK_GPU3D_AXI>, + <&clks IMX6QDL_CLK_GPU2D_CORE>, <&clks IMX6QDL_CLK_GPU3D_CORE>, + <&clks IMX6QDL_CLK_DUMMY>; + clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk", + "gpu2d_clk", "gpu3d_clk", + "gpu3d_shader_clk"; + resets = <&src 0>, <&src 3>; + reset-names = "gpu3d", "gpu2d"; + power-domains = <&pd_pu>; + }; + aips1: aips-bus@2000000 { iomuxc: iomuxc@20e0000 { compatible = "fsl,imx6dl-iomuxc"; }; pxp: pxp@20f0000 { - reg = <0x020f0000 0x4000>; + compatible = "fsl,imx6dl-pxp-dma"; + reg = <0x20f0000 0x4000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_DUMMY>; + clock-names = "pxp-axi", "disp-axi"; + status = "disabled"; }; epdc: epdc@20f4000 { - reg = <0x020f4000 0x4000>; + compatible = "fsl,imx6dl-epdc"; + reg = <0x20f4000 0x4000>; interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_IPU2_DI1>; + clock-names = "epdc_axi", "epdc_pix"; }; }; aips2: aips-bus@2100000 { + mipi_dsi: mipi@21e0000 { + compatible = "fsl,imx6dl-mipi-dsi"; + reg = <0x21e0000 0x4000>; + interrupts = <0 102 0x4>; + gpr = <&gpr>; + clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>; + clock-names = "mipi_pllref_clk", "mipi_cfg_clk"; + status = "disabled"; + }; + i2c4: i2c@21f8000 { #address-cells = <1>; #size-cells = <0>; @@ -124,6 +203,12 @@ }; }; +&dcic2 { + clocks = <&clks IMX6QDL_CLK_DCIC1 >, + <&clks IMX6QDL_CLK_DCIC2>; /* DCIC2 depend on DCIC1 clock in imx6dl*/ + clock-names = "dcic", "disp-axi"; +}; + &gpio1 { gpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>, <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>, @@ -302,12 +387,19 @@ }; &ldb { - clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + compatible = "fsl,imx6dl-ldb", "fsl,imx53-ldb"; + clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>, <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; - clock-names = "di0_pll", "di1_pll", + <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>; + clock-names = "ldb_di0", "ldb_di1", "di0_sel", "di1_sel", - "di0", "di1"; + "di2_sel", + "ldb_di0_div_3_5", "ldb_di1_div_3_5", + "ldb_di0_div_7", "ldb_di1_div_7", + "ldb_di0_div_sel", "ldb_di1_div_sel"; }; &mipi_csi { @@ -389,3 +481,7 @@ &vpu { compatible = "fsl,imx6dl-vpu", "cnm,coda960"; }; + +&vpu_fsl { + iramsize = <0>; +}; diff --git a/arch/arm/boot/dts/imx6q-sabreauto-ecspi.dts b/arch/arm/boot/dts/imx6q-sabreauto-ecspi.dts new file mode 100644 index 00000000000000..44a31e56d8f29d --- /dev/null +++ b/arch/arm/boot/dts/imx6q-sabreauto-ecspi.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2014 Freescale Semiconductor, Inc. + +#include "imx6q-sabreauto.dts" + +&ecspi1 { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&i2c3 { + /* pin conflict with ecspi1 */ + status = "disabled"; +}; + +&uart3 { + /* the uart3 depends on the i2c3, so disable it too. */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + /* max7310_c on i2c3 is gone */ + status = "okay"; + dr_mode = "peripheral"; +}; diff --git a/arch/arm/boot/dts/imx6q-sabreauto-enetirq.dts b/arch/arm/boot/dts/imx6q-sabreauto-enetirq.dts new file mode 100644 index 00000000000000..04351f1feed4a9 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-sabreauto-enetirq.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2019 NXP + +#include "imx6q-sabreauto.dts" + +&fec { + pinctrl-0 = <&pinctrl_enet &pinctrl_enet_irq>; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; +}; + +&mlb { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6q-sabreauto-flexcan1.dts b/arch/arm/boot/dts/imx6q-sabreauto-flexcan1.dts new file mode 100644 index 00000000000000..71dd589448013f --- /dev/null +++ b/arch/arm/boot/dts/imx6q-sabreauto-flexcan1.dts @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6q-sabreauto.dts" + +&can1{ + status = "okay"; +}; + +&fec { + /* pin conflict with flexcan1 */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6q-sabreauto-gpmi-weim.dts b/arch/arm/boot/dts/imx6q-sabreauto-gpmi-weim.dts new file mode 100644 index 00000000000000..bbeb10557cbc7f --- /dev/null +++ b/arch/arm/boot/dts/imx6q-sabreauto-gpmi-weim.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2014 Freescale Semiconductor, Inc. + + +#include "imx6q-sabreauto.dts" + +&ecspi1 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&gpmi { + status = "okay"; +}; + +&i2c3 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&uart3 { + /* pin conflict with gpmi and weim */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + /* max7310_c on i2c3 is gone */ + status = "okay"; + dr_mode = "peripheral"; +}; + +&weim { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-sabreauto-pcie.dts b/arch/arm/boot/dts/imx6q-sabreauto-pcie.dts new file mode 100644 index 00000000000000..769a2cf4a6ac26 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-sabreauto-pcie.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx6q-sabreauto.dts" + +&pcie { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts index 6e981a3e0a8390..e6493858c30e74 100644 --- a/arch/arm/boot/dts/imx6q-sabreauto.dts +++ b/arch/arm/boot/dts/imx6q-sabreauto.dts @@ -13,6 +13,31 @@ compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; }; +&ldb { + lvds-channel@0 { + crtc = "ipu2-di0"; + }; + lvds-channel@1 { + crtc = "ipu2-di1"; + }; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&mxcfb3 { + status = "okay"; +}; + +&mxcfb4 { + status = "okay"; +}; + &sata { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-sabresd-btwifi.dts b/arch/arm/boot/dts/imx6q-sabresd-btwifi.dts new file mode 100644 index 00000000000000..5f55b7df294245 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-sabresd-btwifi.dts @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6q-sabresd.dts" +#include "imx6qdl-sabresd-btwifi.dtsi" diff --git a/arch/arm/boot/dts/imx6q-sabresd-enetirq.dts b/arch/arm/boot/dts/imx6q-sabresd-enetirq.dts new file mode 100644 index 00000000000000..4c9e62779c47d9 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-sabresd-enetirq.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2014 Freescale Semiconductor, Inc. +// Copyright 2019 NXP + +#include "imx6q-sabresd.dts" + +&fec { + pinctrl-0 = <&pinctrl_enet &pinctrl_enet_irq>; + interrupts-extended = <&gpio1 6 0x4>, <&gpc 0 119 0x4>; + fsl,err006687-workaround-present; +}; + +&i2c3 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6q-sabresd-hdcp.dts b/arch/arm/boot/dts/imx6q-sabresd-hdcp.dts new file mode 100644 index 00000000000000..3116e3efb835fa --- /dev/null +++ b/arch/arm/boot/dts/imx6q-sabresd-hdcp.dts @@ -0,0 +1,40 @@ +/* + * Copyright 2012-2014 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx6q-sabresd.dts" + +&gpc { + /* use ldo-enable, u-boot will check it and configure */ + fsl,ldo-bypass = <0>; +}; + +&hdmi_video { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_hdcp>; + fsl,hdcp; +}; + +&i2c2 { + status = "disable"; +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_pu { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff --git a/arch/arm/boot/dts/imx6q-sabresd-ldo.dts b/arch/arm/boot/dts/imx6q-sabresd-ldo.dts new file mode 100644 index 00000000000000..8363302dca3548 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-sabresd-ldo.dts @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6q-sabresd.dts" + +&gpc { + /* use ldo-enable, u-boot will check it and configure */ + fsl,ldo-bypass = <0>; +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_pu { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; + +&wdog1 { + status = "okay"; +}; + +&wdog2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6q-sabresd-pcie.dts b/arch/arm/boot/dts/imx6q-sabresd-pcie.dts new file mode 100644 index 00000000000000..2ff88f6a1d52f4 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-sabresd-pcie.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx6q-sabresd.dts" + +&pcie { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-sabresd-uart.dts b/arch/arm/boot/dts/imx6q-sabresd-uart.dts new file mode 100644 index 00000000000000..800479da5941a3 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-sabresd-uart.dts @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6q-sabresd.dts" + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5_1>; + fsl,uart-has-rtscts; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart5dte_1>; */ +}; + +&ecspi1 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts index eec944673c0bf8..ca8c7d1a29cbd7 100644 --- a/arch/arm/boot/dts/imx6q-sabresd.dts +++ b/arch/arm/boot/dts/imx6q-sabresd.dts @@ -13,6 +13,38 @@ compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; }; +&battery { + offset-charger = <1900>; + offset-discharger = <1694>; + offset-usb-charger = <1685>; +}; + +&ldb { + lvds-channel@0 { + crtc = "ipu2-di0"; + }; + + lvds-channel@1 { + crtc = "ipu2-di1"; + }; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&mxcfb3 { + status = "okay"; +}; + +&mxcfb4 { + status = "okay"; +}; + &sata { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index d038f411702460..2d3e137fc1fc32 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -43,9 +43,13 @@ <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, <&clks IMX6QDL_CLK_STEP>, <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; + <&clks IMX6QDL_CLK_PLL1_SYS>, + <&clks IMX6QDL_CLK_PLL1>, + <&clks IMX6QDL_PLL1_BYPASS>, + <&clks IMX6QDL_PLL1_BYPASS_SRC>; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1", + "pll1_bypass", "pll1_bypass_src"; arm-supply = <®_arm>; pu-supply = <®_pu>; soc-supply = <®_soc>; @@ -154,13 +158,44 @@ }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + soc { - ocram: sram@900000 { + busfreq: busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>, + <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", + "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc"; + interrupts = <0 107 0x04>, <0 112 0x4>, <0 113 0x4>, <0 114 0x4>; + interrupt-names = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3"; + fsl,max_ddr_freq = <528000000>; + }; + + ocram: sram@905000 { compatible = "mmio-sram"; - reg = <0x00900000 0x40000>; + reg = <0x905000 0x3B000>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; + ocram_optee: sram@938000 { + compatible = "fsl,optee-lpm-sram"; + reg = <0x938000 0x8000>; + overw_reg = <&ocram 0x905000 0x33000>; + }; + aips-bus@2000000 { /* AIPS1 */ spba-bus@2000000 { ecspi5: spi@2018000 { @@ -172,7 +207,7 @@ clocks = <&clks IMX6Q_CLK_ECSPI5>, <&clks IMX6Q_CLK_ECSPI5>; clock-names = "ipg", "per"; - dmas = <&sdma 11 8 1>, <&sdma 12 8 2>; + dmas = <&sdma 11 7 1>, <&sdma 12 7 2>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -183,6 +218,18 @@ }; }; + aips-bus@2100000 { /* AIPS2 */ + mipi_dsi: mipi@21e0000 { + compatible = "fsl,imx6q-mipi-dsi"; + reg = <0x21e0000 0x4000>; + interrupts = <0 102 0x4>; + gpr = <&gpr>; + clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>; + clock-names = "mipi_pllref_clk", "mipi_cfg_clk"; + status = "disabled"; + }; + }; + sata: sata@2200000 { compatible = "fsl,imx6q-ahci"; reg = <0x02200000 0x4000>; @@ -203,6 +250,30 @@ clock-names = "bus", "core"; power-domains = <&pd_pu>; #cooling-cells = <2>; + status = "disabled"; + }; + + gpu: gpu@00130000 { + compatible = "fsl,imx6q-gpu"; + reg = <0x00130000 0x4000>, <0x00134000 0x4000>, + <0x02204000 0x4000>, <0x10000000 0x0>, + <0x0 0x8000000>; + reg-names = "iobase_3d", "iobase_2d", + "iobase_vg", "phys_baseaddr", + "contiguous_mem"; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>, + <0 10 IRQ_TYPE_LEVEL_HIGH>, + <0 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_3d", "irq_2d", "irq_vg"; + clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, <&clks IMX6QDL_CLK_OPENVG_AXI>, + <&clks IMX6QDL_CLK_GPU3D_AXI>, <&clks IMX6QDL_CLK_GPU2D_CORE>, + <&clks IMX6QDL_CLK_GPU3D_CORE>, <&clks IMX6QDL_CLK_GPU3D_SHADER>; + clock-names = "gpu2d_axi_clk", "openvg_axi_clk", + "gpu3d_axi_clk", "gpu2d_clk", + "gpu3d_clk", "gpu3d_shader_clk"; + resets = <&src 0>, <&src 3>, <&src 3>; + reset-names = "gpu3d", "gpu2d", "gpuvg"; + power-domains = <&pd_pu>; }; ipu2: ipu@2800000 { @@ -214,9 +285,17 @@ <0 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_IPU2_DI0>, - <&clks IMX6QDL_CLK_IPU2_DI1>; - clock-names = "bus", "di0", "di1"; + <&clks IMX6QDL_CLK_IPU2_DI1>, + <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, + <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0>, + <&clks IMX6QDL_CLK_LDB_DI1>; + clock-names = "bus", + "di0", "di1", + "di0_sel", "di1_sel", + "ldb_di0", "ldb_di1"; resets = <&src 4>; + bypass_reset = <0>; ipu2_csi0: port@0 { reg = <0>; @@ -429,13 +508,19 @@ }; &ldb { - clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; + clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>, <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", "di2_sel", "di3_sel", - "di0", "di1"; + <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>; + clock-names = "ldb_di0", "ldb_di1", + "di0_sel", "di1_sel", + "di2_sel", "di3_sel", + "ldb_di0_div_3_5", "ldb_di1_div_3_5", + "ldb_di0_div_7", "ldb_di1_div_7", + "ldb_di0_div_sel", "ldb_di1_div_sel"; lvds-channel@0 { port@2 { diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index cf628465cd0a39..e213ae47e44182 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -11,7 +11,14 @@ stdout-path = &uart4; }; - memory@10000000 { + aliases { + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + mxcfb2 = &mxcfb3; + mxcfb3 = &mxcfb4; + }; + + memory: memory@10000000 { device_type = "memory"; reg = <0x10000000 0x80000000>; }; @@ -84,6 +91,14 @@ regulator-always-on; }; + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + reg_usb_h1_vbus: regulator-usb-h1-vbus { compatible = "regulator-fixed"; regulator-name = "usb_h1_vbus"; @@ -121,26 +136,113 @@ vin-supply = <®_can_en>; }; + reg_si4763_vio1: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "vio1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_si4763_vio2: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "vio2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_si4763_vd: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "vd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_si4763_va: regulator@6 { + compatible = "regulator-fixed"; + regulator-name = "va"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_hdmi: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "hdmi-5v-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + hdmi-5v-supply = <&swbst_reg>; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb3: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB565"; + mode_str ="CLAA-WVGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb4: fb@3 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + sound-cs42888 { compatible = "fsl,imx6-sabreauto-cs42888", - "fsl,imx-audio-cs42888"; + "fsl,imx-audio-cs42888"; model = "imx-cs42888"; - audio-cpu = <&esai>; - audio-asrc = <&asrc>; + esai-controller = <&esai>; + asrc-controller = <&asrc>; audio-codec = <&codec>; - audio-routing = - "Line Out Jack", "AOUT1L", - "Line Out Jack", "AOUT1R", - "Line Out Jack", "AOUT2L", - "Line Out Jack", "AOUT2R", - "Line Out Jack", "AOUT3L", - "Line Out Jack", "AOUT3R", - "Line Out Jack", "AOUT4L", - "Line Out Jack", "AOUT4R", - "AIN1L", "Line In Jack", - "AIN1R", "Line In Jack", - "AIN2L", "Line In Jack", - "AIN2R", "Line In Jack"; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + sound-fm { + compatible = "fsl,imx-audio-si476x", + "fsl,imx-tuner-si476x"; + model = "imx-radio-si4763"; + ssi-controller = <&ssi2>; + fm-controller = <&si476x_codec>; + mux-int-port = <2>; + mux-ext-port = <5>; }; sound-spdif { @@ -174,19 +276,22 @@ #size-cells = <0>; reg = <1>; - adv7180: camera@21 { - compatible = "adi,adv7180"; + adv7180: adv7180@21 { + compatible = "adv,adv7180"; reg = <0x21>; - powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio1>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - - port { - adv7180_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - bus-width = <8>; - }; - }; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_1>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */ + AVDD-supply = <®_3p3v>; /* 1.8v */ + DVDD-supply = <®_3p3v>; /* 1.8v */ + PVDD-supply = <®_3p3v>; /* 1.8v */ + pwn-gpios = <&max7310_b 2 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + cvbs = <1>; }; max7310_a: gpio@30 { @@ -214,8 +319,9 @@ }; light-sensor@44 { - compatible = "isil,isl29023"; + compatible = "fsl,isl29023"; reg = <0x44>; + rext = <499>; interrupt-parent = <&gpio5>; interrupts = <17 IRQ_TYPE_EDGE_FALLING>; }; @@ -237,6 +343,25 @@ }; }; }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; }; &ipu1_csi0_from_ipu1_csi0_mux { @@ -244,7 +369,10 @@ }; &ipu1_csi0_mux_from_parallel_sensor { + /* Downstream driver doesn't use endpoints */ + /* remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; + */ bus-width = <8>; }; @@ -261,11 +389,23 @@ <&clks IMX6QDL_CLK_PLL4_POST_DIV>; assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>, <&clks IMX6QDL_PLL4_BYPASS_SRC>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>; }; +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-hdmi"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds0"; + status = "okay"; +}; + &ecspi1 { cs-gpios = <&gpio3 19 0>; pinctrl-names = "default"; @@ -295,15 +435,14 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; + fsl,magic-packet; status = "okay"; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; + pinctrl-assert-gpios = <&max7310_b 3 GPIO_ACTIVE_HIGH>; /* TX */ xceiver-supply = <®_can_stby>; status = "disabled"; /* pin conflict with fec */ }; @@ -318,13 +457,31 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; + /* enable at -gpmi-weim.dts due to pin conflict */ + status = "disabled"; + nand-on-flash-bbt; +}; + +&hdmi_audio { status = "okay"; }; -&hdmi { +&hdmi_cec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hdmi_cec>; - ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <1>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x294>; + fsl,phy_reg_cksymtx = <0x800d>; + HDMI-supply = <®_hdmi>; status = "okay"; }; @@ -453,6 +610,25 @@ interrupts = <28 IRQ_TYPE_EDGE_FALLING>; wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; }; + + si4763: si4763@63 { + compatible = "si4761"; + reg = <0x63>; + va-supply = <®_si4763_va>; + vd-supply = <®_si4763_vd>; + vio1-supply = <®_si4763_vio1>; + vio2-supply = <®_si4763_vio2>; + revision-a10; /* set to default A10 compatible command set */ + + si476x_codec: si476x-codec { + compatible = "si476x-codec"; + }; + }; + + hdmi_edid: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; }; &i2c3 { @@ -474,6 +650,14 @@ >; }; + pinctrl_audmux: audmux { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 @@ -511,6 +695,12 @@ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_enet_irq: enetirqgrp { + fsl,pins = < MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 >; }; @@ -595,6 +785,30 @@ >; }; + pinctrl_ipu1_1: ipu1grp-1 { /* parallel port 16-bit */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000 + MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000 + MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000 + MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000 + MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000 + MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000 + MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000 + MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 @@ -636,6 +850,14 @@ >; }; + pinctrl_mlb: mlb { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x80000000 + MX6QDL_PAD_GPIO_6__MLB_SIG 0x80000000 + MX6QDL_PAD_GPIO_2__MLB_DATA 0x80000000 + >; + }; + pinctrl_pwm3: pwm1grp { fsl,pins = < MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 @@ -660,6 +882,24 @@ >; }; + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart3dte_1: uart3dtegrp-1 { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1b0b1 + >; + }; + pinctrl_uart4: uart4grp { fsl,pins = < MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 @@ -673,6 +913,17 @@ >; }; + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 @@ -780,6 +1031,7 @@ lvds-channel@0 { fsl,data-mapping = "spwg"; fsl,data-width = <18>; + primary; status = "okay"; display-timings { @@ -797,15 +1049,38 @@ }; }; }; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing1>; + timing1: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; }; -&pwm3 { +&mlb { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; + pinctrl-0 = <&pinctrl_mlb>; status = "okay"; }; -&pcie { +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; status = "okay"; }; @@ -815,6 +1090,26 @@ status = "okay"; }; +&ssi2 { + assigned-clocks = <&clks IMX6QDL_CLK_SSI2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>; + fsl,mode = "i2s-master"; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_1>; + pinctrl-assert-gpios = <&max7310_b 4 GPIO_ACTIVE_HIGH>, /* CTS */ + <&max7310_c 3 GPIO_ACTIVE_HIGH>; /* RXD and TXD */ + fsl,uart-has-rtscts; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart3dte_1>; */ +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; @@ -833,6 +1128,14 @@ status = "okay"; }; +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + status = "okay"; +}; + &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd-btwifi.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd-btwifi.dtsi new file mode 100644 index 00000000000000..cf8604181d329e --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-sabresd-btwifi.dtsi @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * NOTE: This DTS file is wrote for plugging in Murata 1MW M.2 + * into SD2 slot by using Murata uSD-to-M.2 Adapter. + * + * By default, OOB IRQ is enabled with below HW rework. + * HW rework: + * Install R209,R210,R211,R212,R213,R214,R215 on SDB board. + */ + +/ { + leds { + compatible = "gpio-leds"; + status = "disabled"; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + }; +}; + +&ecspi1 { + status = "disabled"; +}; + +&iomuxc { + imx6qdl-sabresd-murata-v2 { + pinctrl_btreg: btreggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + + /* add MUXing entry for SD2 4-bit interface and configure control pins */ + pinctrl_wifi: wifigrp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x13069 /* WL_REG_ON */ + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0b001 /* WL_HOST_WAKE */ + >; + }; + }; +}; + +&pinctrl_gpio_leds { + fsl,pins = < + >; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5_1 + &pinctrl_btreg>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart5dte_1>; */ +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + bus-width = <4>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + mmc-pwrseq = <&usdhc1_pwrseq>; + pm-ignore-notify; + cap-power-off-card; + /delete-property/ enable-sdio-wakeup; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio4>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index fe59dde41b649c..96a4993e84a1cb 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -8,11 +8,31 @@ #include / { + aliases { + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + mxcfb2 = &mxcfb3; + mxcfb3 = &mxcfb4; + }; + chosen { stdout-path = &uart1; }; - memory@10000000 { + battery: max8903@0 { + compatible = "fsl,max8903-charger"; + pinctrl-names = "default"; + dok_input = <&gpio2 24 1>; + uok_input = <&gpio1 27 1>; + chg_input = <&gpio3 23 1>; + flt_input = <&gpio5 2 1>; + fsl,dcm_always_high; + fsl,dc_valid; + fsl,usb_valid; + status = "okay"; + }; + + memory: memory@10000000 { device_type = "memory"; reg = <0x10000000 0x40000000>; }; @@ -66,6 +86,22 @@ enable-active-high; }; + reg_hdmi: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "hdmi-5v-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + hdmi-5v-supply = <&swbst_reg>; + }; + + reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on { + compatible = "regulator-fixed"; + regulator-name = "mipi_dsi_pwr_on"; + gpio = <&gpio6 14 0>; + enable-active-high; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -97,17 +133,86 @@ compatible = "fsl,imx6q-sabresd-wm8962", "fsl,imx-audio-wm8962"; model = "wm8962-audio"; - ssi-controller = <&ssi2>; + audio-cpu = <&ssi2>; audio-codec = <&codec>; + asrc-controller = <&asrc>; audio-routing = "Headphone Jack", "HPOUTL", "Headphone Jack", "HPOUTR", "Ext Spk", "SPKOUTL", "Ext Spk", "SPKOUTR", "AMIC", "MICBIAS", - "IN3R", "AMIC"; + "IN3R", "AMIC", + "DMIC", "MICBIAS", + "DMICDAT", "DMIC", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; mux-int-port = <2>; mux-ext-port = <3>; + codec-master; + hp-det-gpios = <&gpio7 8 1>; + mic-det-gpios = <&gpio1 9 1>; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb3: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB565"; + mode_str ="CLAA-WVGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb4: fb@3 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB565"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1>; + status = "okay"; }; backlight_lvds: backlight-lvds { @@ -123,21 +228,33 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; - red { + charger-led { gpios = <&gpio1 2 0>; - default-state = "on"; + linux,default-trigger = "max8903-charger-charging"; + retain-state-suspended; + default-state = "off"; }; }; - panel { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds>; + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; + status = "okay"; + }; - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; + v4l2_cap_1 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; }; }; @@ -149,7 +266,9 @@ }; &ipu1_csi0_mux_from_parallel_sensor { +#if 0 remote-endpoint = <&ov5642_to_ipu1_csi0_mux>; +#endif }; &ipu1_csi0 { @@ -160,6 +279,11 @@ &mipi_csi { status = "okay"; + ipu_id = <0>; + csi_id = <1>; + v_channel = <0>; + lanes = <2>; +#if 0 port@0 { reg = <0>; @@ -169,6 +293,17 @@ data-lanes = <1 2>; }; }; +#endif +}; + +&mipi_dsi { + dev_id = <0>; + disp_id = <1>; + lcd_panel = "TRULY-WVGA"; + disp-power-on-supply = <®_mipi_dsi_pwr_on>; + reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + reset-delay-us = <50>; + status = "okay"; }; &audmux { @@ -180,8 +315,20 @@ &clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; +}; + +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-hdmi"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds1"; + status = "okay"; }; &ecspi1 { @@ -204,20 +351,44 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + fsl,magic-packet; status = "okay"; }; -&hdmi { +&gpc { + fsl,ldo-bypass = <1>; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hdmi_cec>; - ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x294>; + fsl,phy_reg_cksymtx = <0x800d>; + HDMI-supply = <®_hdmi>; status = "okay"; }; &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; status = "okay"; codec: wm8962@1a { @@ -253,6 +424,7 @@ vddio-supply = <®_sensors>; }; +#if 0 ov5642: camera@3c { compatible = "ovti,ov5642"; pinctrl-names = "default"; @@ -277,12 +449,32 @@ }; }; }; +#endif + ov564x: ov564x@3c { + compatible = "ovti,ov564x"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_2>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "csi_mclk"; + DOVDD-supply = <&vgen4_reg>; /* 1.8v */ + AVDD-supply = <&vgen3_reg>; /* 2.8v, on rev C board is VGEN3, on rev B board is VGEN5 */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio1 16 1>; /* active low: SD1_DAT0 */ + rst-gpios = <&gpio1 17 0>; /* active high: SD1_DAT1 */ + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + }; }; &i2c2 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; status = "okay"; touchscreen@4 { @@ -295,6 +487,15 @@ wakeup-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; }; + max11801@48 { + compatible = "maxim,max11801"; + reg = <0x48>; + interrupt-parent = <&gpio3>; + interrupts = <26 2>; + work-mode = <1>;/*DCM mode*/ + }; + +#if 0 ov5640: camera@3c { compatible = "ovti,ov5640"; pinctrl-names = "default"; @@ -317,6 +518,22 @@ }; }; }; +#endif + + ov564x_mipi: ov564x_mipi@3c { /* i2c2 driver */ + compatible = "ovti,ov564x_mipi"; + reg = <0x3c>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "csi_mclk"; + DOVDD-supply = <&vgen4_reg>; /* 1.8v */ + AVDD-supply = <&vgen3_reg>; /* 2.8v rev C board is VGEN3 rev B board is VGEN5 */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio1 19 1>; /* active low: SD1_CLK */ + rst-gpios = <&gpio1 20 0>; /* active high: SD1_DAT2 */ + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + }; pmic: pfuze100@8 { compatible = "fsl,pfuze100"; @@ -418,12 +635,20 @@ }; }; }; + + hdmi_edid: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; }; &i2c3 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; status = "okay"; egalax_ts@4 { @@ -446,13 +671,14 @@ }; light-sensor@44 { - compatible = "isil,isl29023"; + compatible = "fsl,isl29023"; reg = <0x44>; + rext = <499>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3_isl29023_int>; interrupt-parent = <&gpio3>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - vcc-supply = <®_sensors>; + vdd-supply = <®_sensors>; }; }; @@ -472,6 +698,13 @@ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 >; }; @@ -514,6 +747,12 @@ >; }; + pinctrl_enet_irq: enetirqgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + pinctrl_gpio_keys: gpio_keysgrp { fsl,pins = < MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 @@ -524,7 +763,14 @@ pinctrl_hdmi_cec: hdmicecgrp { fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x108b0 + >; + }; + + pinctrl_hdmi_hdcp: hdmihdcpgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 >; }; @@ -535,6 +781,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1_gpio_grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b8b0 + >; + }; + pinctrl_i2c1_mma8451_int: i2c1mma8451intgrp { fsl,pins = < MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0xb0b1 @@ -548,6 +801,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2_gpio_grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b8b0 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 + >; + }; + pinctrl_i2c2_egalax_int: i2c2egalaxintgrp { fsl,pins = < MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 @@ -561,6 +821,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3_gpio_grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b8b0 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 + >; + }; + pinctrl_i2c3_isl29023_int: i2c3isl29023intgrp { fsl,pins = < MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0xb0b1 @@ -573,6 +840,59 @@ >; }; + pinctrl_ipu1: ipu1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 + MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000 + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 + >; + }; + pinctrl_ipu1_csi0: ipu1csi0grp { fsl,pins = < MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 @@ -634,6 +954,24 @@ >; }; + pinctrl_uart5_1: uart5grp-1 { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x1b0b1 + MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x1b0b1 + >; + }; + pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 @@ -704,16 +1042,45 @@ &ldb { status = "okay"; - lvds-channel@1 { + lvds-channel@0 { fsl,data-mapping = "spwg"; fsl,data-width = <18>; status = "okay"; - port@4 { - reg = <4>; + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + primary; + status = "okay"; - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; + display-timings { + native-mode = <&timing1>; + timing1: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; }; }; }; @@ -724,7 +1091,7 @@ pinctrl-0 = <&pinctrl_pcie>; reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; vpcie-supply = <®_pcie>; - status = "okay"; + epdev_on-supply = <&vgen3_reg>; }; &pwm1 { @@ -757,11 +1124,14 @@ status = "okay"; }; -&snvs_pwrkey { - status = "okay"; -}; - &ssi2 { + assigned-clocks = <&clks IMX6QDL_CLK_PLL4>, + <&clks IMX6QDL_PLL4_BYPASS>, + <&clks IMX6QDL_CLK_SSI2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>, + <&clks IMX6QDL_CLK_PLL4>, + <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <737280000>, <0>, <0>; status = "okay"; }; @@ -808,6 +1178,7 @@ bus-width = <8>; non-removable; no-1-8-v; + auto-cmd23-broken; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index bc488df315117b..a8d043e21b4855 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -156,6 +156,11 @@ interrupt-parent = <&gpc>; ranges; + caam_sm: caam-sm@100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x4000>; + }; + dma_apbh: dma-apbh@110000 { compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x00110000 0x2000>; @@ -215,6 +220,45 @@ }; }; + hdmi_core: hdmi_core@120000 { + compatible = "fsl,imx6q-hdmi-core"; + reg = <0x120000 0x9000>; + clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>, + <&clks IMX6QDL_CLK_HDMI_IAHB>, + <&clks IMX6QDL_CLK_HSI_TX>; + clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core"; + status = "disabled"; + }; + + hdmi_video: hdmi_video@20e0000 { + compatible = "fsl,imx6q-hdmi-video"; + reg = <0x20e0000 0x1000>; + reg-names = "hdmi_gpr"; + interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>, + <&clks IMX6QDL_CLK_HDMI_IAHB>, + <&clks IMX6QDL_CLK_HSI_TX>; + clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core"; + status = "disabled"; + }; + + hdmi_audio: hdmi_audio@120000 { + compatible = "fsl,imx6q-hdmi-audio"; + clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>, + <&clks IMX6QDL_CLK_HDMI_IAHB>, + <&clks IMX6QDL_CLK_HSI_TX>; + clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core"; + dmas = <&sdma 2 26 0>; + dma-names = "tx"; + status = "disabled"; + }; + + hdmi_cec: hdmi_cec@120000 { + compatible = "fsl,imx6q-hdmi-cec"; + interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + gpu_3d: gpu@130000 { compatible = "vivante,gc"; reg = <0x00130000 0x4000>; @@ -225,6 +269,7 @@ clock-names = "bus", "core", "shader"; power-domains = <&pd_pu>; #cooling-cells = <2>; + status = "disabled"; }; gpu_2d: gpu@134000 { @@ -236,6 +281,19 @@ clock-names = "bus", "core"; power-domains = <&pd_pu>; #cooling-cells = <2>; + status = "disabled"; + }; + + ocrams: sram@00900000 { + compatible = "fsl,lpm-sram"; + reg = <0x00900000 0x4000>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; + }; + + ocrams_ddr: sram@00904000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x00904000 0x1000>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; }; timer@a00600 { @@ -318,7 +376,7 @@ clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>, <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>, <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>, - <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>, + <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_MLB>, <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>; clock-names = "core", "rxtx0", "rxtx1", "rxtx2", @@ -337,7 +395,7 @@ clocks = <&clks IMX6QDL_CLK_ECSPI1>, <&clks IMX6QDL_CLK_ECSPI1>; clock-names = "ipg", "per"; - dmas = <&sdma 3 8 1>, <&sdma 4 8 2>; + dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -351,7 +409,7 @@ clocks = <&clks IMX6QDL_CLK_ECSPI2>, <&clks IMX6QDL_CLK_ECSPI2>; clock-names = "ipg", "per"; - dmas = <&sdma 5 8 1>, <&sdma 6 8 2>; + dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -365,7 +423,7 @@ clocks = <&clks IMX6QDL_CLK_ECSPI3>, <&clks IMX6QDL_CLK_ECSPI3>; clock-names = "ipg", "per"; - dmas = <&sdma 7 8 1>, <&sdma 8 8 2>; + dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -379,7 +437,7 @@ clocks = <&clks IMX6QDL_CLK_ECSPI4>, <&clks IMX6QDL_CLK_ECSPI4>; clock-names = "ipg", "per"; - dmas = <&sdma 9 8 1>, <&sdma 10 8 2>; + dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -502,6 +560,24 @@ power-domains = <&pd_pu>; resets = <&src 1>; iram = <&ocram>; + status = "disabled"; + }; + + vpu_fsl: vpu_fsl@2040000 { + compatible = "fsl,imx6-vpu"; + reg = <0x2040000 0x3c000>; + reg-names = "vpu_regs"; + interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>, + <0 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vpu_jpu_irq", "vpu_ipi_irq"; + clocks = <&clks IMX6QDL_CLK_VPU_AXI>, + <&clks IMX6QDL_CLK_MMDC_CH0_AXI>, + <&clks IMX6QDL_CLK_OCRAM>; + clock-names = "vpu_clk", "mmdc_ch0_axi", "ocram"; + iramsize = <0x21000>; + iram = <&ocram>; + resets = <&src 1>; + power-domains = <&pd_pu>; }; aipstz@207c000 { /* AIPSTZ1 */ @@ -759,6 +835,7 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; reg_pu: regulator-vddpu { @@ -776,6 +853,7 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; reg_soc: regulator-vddsoc { @@ -793,6 +871,7 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; }; @@ -812,6 +891,20 @@ fsl,anatop = <&anatop>; }; + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@20cc000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x20cc000 0x4000>; + }; + snvs: snvs@20cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -914,13 +1007,23 @@ }; dcic1: dcic@20e4000 { - reg = <0x020e4000 0x4000>; + compatible = "fsl,imx6q-dcic"; + reg = <0x20e4000 0x4000>; interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_DCIC1>, <&clks IMX6QDL_CLK_DCIC1>; + clock-names = "dcic", "disp-axi"; + gpr = <&gpr>; + status = "disabled"; }; dcic2: dcic@20e8000 { - reg = <0x020e8000 0x4000>; + compatible = "fsl,imx6q-dcic"; + reg = <0x20e8000 0x4000>; interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_DCIC2>, <&clks IMX6QDL_CLK_DCIC2>; + clock-names = "dcic", "disp-axi"; + gpr = <&gpr>; + status = "disabled"; }; sdma: sdma@20ec000 { @@ -1039,20 +1142,28 @@ compatible = "fsl,imx6q-fec"; reg = <0x02188000 0x4000>; interrupt-names = "int0", "pps"; - interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>, - <0 119 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = + <&gpc 0 118 IRQ_TYPE_LEVEL_HIGH>, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET_REF>; clock-names = "ipg", "ahb", "ptp"; + stop-mode = <&gpr 0x34 27>; + fsl,wakeup_irq = <0>; status = "disabled"; }; - mlb@218c000 { + mlb: mlb@218c000 { + compatible = "fsl,imx6q-mlb150"; reg = <0x0218c000 0x4000>; interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, <0 117 IRQ_TYPE_LEVEL_HIGH>, <0 126 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_MLB>; + clock-names = "mlb"; + iram = <&ocram>; + status = "disabled"; }; usdhc1: usdhc@2190000 { @@ -1137,6 +1248,11 @@ reg = <0x021ac000 0x4000>; }; + mmdc0-1@021b0000 { /* MMDC0-1 */ + compatible = "fsl,imx6q-mmdc-combine"; + reg = <0x021b0000 0x8000>; + }; + mmdc0: memory-controller@21b0000 { /* MMDC0 */ compatible = "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; @@ -1183,15 +1299,15 @@ }; mipi_csi: mipi@21dc000 { - compatible = "fsl,imx6-mipi-csi2"; + compatible = "fsl,imx6q-mipi-csi2"; reg = <0x021dc000 0x4000>; #address-cells = <1>; #size-cells = <0>; interrupts = <0 100 0x04>, <0 101 0x04>; clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>, - <&clks IMX6QDL_CLK_EIM_PODF>; - clock-names = "dphy", "ref", "pix"; + <&clks IMX6QDL_CLK_EIM_SEL>; + clock-names = "dphy_clk", "cfg_clk", "pixel_clk"; status = "disabled"; }; @@ -1226,6 +1342,7 @@ reg = <0x021e4000 0x4000>; interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_VDOA>; + iram = <&ocram>; }; uart2: serial@21e8000 { @@ -1285,10 +1402,15 @@ interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, <0 5 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_IPU1>, - <&clks IMX6QDL_CLK_IPU1_DI0>, - <&clks IMX6QDL_CLK_IPU1_DI1>; - clock-names = "bus", "di0", "di1"; + <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>, + <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; + clock-names = "bus", + "di0", "di1", + "di0_sel", "di1_sel", + "ldb_di0", "ldb_di1"; resets = <&src 2>; + bypass_reset = <0>; ipu1_csi0: port@0 { reg = <0>; diff --git a/arch/arm/boot/dts/imx6qp-sabreauto-ecspi.dts b/arch/arm/boot/dts/imx6qp-sabreauto-ecspi.dts new file mode 100644 index 00000000000000..b69e758b36ec14 --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-sabreauto-ecspi.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015 Freescale Semiconductor, Inc. + + +#include "imx6qp-sabreauto.dts" + +&ecspi1 { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&i2c3 { + /* pin conflict with ecspi1 */ + status = "disabled"; +}; + +&uart3 { + /* the uart3 depends on the i2c3, so disable it too. */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + /* max7310_c on i2c3 is gone */ + status = "okay"; + dr_mode = "peripheral"; +}; diff --git a/arch/arm/boot/dts/imx6qp-sabreauto-flexcan1.dts b/arch/arm/boot/dts/imx6qp-sabreauto-flexcan1.dts new file mode 100644 index 00000000000000..b57607b0c22280 --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-sabreauto-flexcan1.dts @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6qp-sabreauto.dts" + +&can1{ + status = "okay"; +}; + +&fec { + /* pin conflict with flexcan1 */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6qp-sabreauto-gpmi-weim.dts b/arch/arm/boot/dts/imx6qp-sabreauto-gpmi-weim.dts new file mode 100644 index 00000000000000..1ca09d7dfca577 --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-sabreauto-gpmi-weim.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015 Freescale Semiconductor, Inc. + +#include "imx6qp-sabreauto.dts" + +&ecspi1 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&gpmi { + compatible = "fsl,imx6qp-gpmi-nand"; + status = "okay"; +}; + +&i2c3 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&uart3 { + /* pin conflict with gpmi and weim */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + /* max7310_c on i2c3 is gone */ + status = "okay"; + dr_mode = "peripheral"; +}; + +&weim { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qp-sabreauto.dts b/arch/arm/boot/dts/imx6qp-sabreauto.dts index d4caeeb0af703e..e6a69467a4bbd4 100644 --- a/arch/arm/boot/dts/imx6qp-sabreauto.dts +++ b/arch/arm/boot/dts/imx6qp-sabreauto.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ OR MIT // // Copyright 2016 Freescale Semiconductor, Inc. +// Copyright 2020 NXP /dts-v1/; @@ -12,6 +13,62 @@ compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp"; }; +&pre1 { + status = "okay"; +}; + +&pre2 { + status = "okay"; +}; + +&pre3 { + status = "okay"; +}; + +&pre4 { + status = "okay"; +}; + +&prg1 { + memory-region = <&memory>; + status = "okay"; +}; + +&prg2 { + memory-region = <&memory>; + status = "okay"; +}; + +&mxcfb1 { + prefetch; + status = "okay"; +}; + +&mxcfb2 { + prefetch; + status = "okay"; +}; + +&mxcfb3 { + prefetch; + status = "okay"; +}; + +&mxcfb4 { + prefetch; + status = "okay"; +}; + +&ldb { + lvds-channel@0 { + crtc = "ipu2-di0"; + }; + + lvds-channel@1 { + crtc = "ipu2-di1"; + }; +}; + &i2c2 { max7322: gpio@68 { compatible = "maxim,max7322"; @@ -21,33 +78,13 @@ }; }; -&iomuxc { - imx6qdl-sabreauto { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b018 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b018 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b018 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b018 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b018 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b018 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b018 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b018 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b018 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b018 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b018 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b018 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - }; +&pcie { + reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>; + status = "okay"; }; -&pcie { - status = "disabled"; +&sata { + status = "okay"; }; &vgen3_reg { diff --git a/arch/arm/boot/dts/imx6qp-sabresd-btwifi.dts b/arch/arm/boot/dts/imx6qp-sabresd-btwifi.dts new file mode 100644 index 00000000000000..e83d04f146008c --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-sabresd-btwifi.dts @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6qp-sabresd.dts" +#include "imx6qdl-sabresd-btwifi.dtsi" diff --git a/arch/arm/boot/dts/imx6qp-sabresd-hdcp.dts b/arch/arm/boot/dts/imx6qp-sabresd-hdcp.dts new file mode 100644 index 00000000000000..e19ff136c226af --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-sabresd-hdcp.dts @@ -0,0 +1,39 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx6qp-sabresd.dts" + +&gpc { + /* use ldo-enable, u-boot will check it and configure */ + fsl,ldo-bypass = <0>; +}; + +&hdmi_video { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_hdcp>; + fsl,hdcp; +}; + +&i2c2 { + status = "disable"; +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_pu { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff --git a/arch/arm/boot/dts/imx6qp-sabresd-ldo.dts b/arch/arm/boot/dts/imx6qp-sabresd-ldo.dts new file mode 100644 index 00000000000000..f33eb65a793e46 --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-sabresd-ldo.dts @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6qp-sabresd.dts" + +&wdog1 { + status = "okay"; +}; + +&wdog2 { + status = "disabled"; +}; + +&gpc { + /* use ldo-enable, u-boot will check it and configure */ + fsl,ldo-bypass = <0>; +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_pu { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; + +&wdog1 { + status = "okay"; +}; + +&wdog2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6qp-sabresd.dts b/arch/arm/boot/dts/imx6qp-sabresd.dts index f1b9cb104fddc0..03320e210e2412 100644 --- a/arch/arm/boot/dts/imx6qp-sabresd.dts +++ b/arch/arm/boot/dts/imx6qp-sabresd.dts @@ -50,6 +50,76 @@ }; }; +&ov564x { + AVDD-supply = <&vgen6_reg>; /* 2.8v */ + DOVDD-supply = <&sw4_reg>; /* 1.8v */ +}; + +&ov564x_mipi { + AVDD-supply = <&vgen6_reg>; /* 2.8v */ + DOVDD-supply = <&sw4_reg>; /* 1.8v */ +}; + &pcie { - status = "disabled"; + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&pre1 { + status = "okay"; +}; + +&pre2 { + status = "okay"; +}; + +&pre3 { + status = "okay"; +}; + +&pre4 { + status = "okay"; +}; + +&prg1 { + memory-region = <&memory>; + status = "okay"; +}; + +&prg2 { + memory-region = <&memory>; + status = "okay"; +}; + +&mxcfb1 { + prefetch; + status = "okay"; +}; + +&mxcfb2 { + prefetch; + status = "okay"; +}; + +&mxcfb3 { + prefetch; + status = "okay"; +}; + +&mxcfb4 { + prefetch; + status = "okay"; +}; + +&ldb { + lvds-channel@0 { + crtc = "ipu2-di0"; + }; + + lvds-channel@1 { + crtc = "ipu2-di1"; + }; }; diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi index d91f92f944c53e..88bafed79411eb 100644 --- a/arch/arm/boot/dts/imx6qp.dtsi +++ b/arch/arm/boot/dts/imx6qp.dtsi @@ -5,6 +5,15 @@ #include "imx6q.dtsi" / { + aliases { + pre0 = &pre1; + pre1 = &pre2; + pre2 = &pre3; + pre3 = &pre4; + prg0 = &prg1; + prg1 = &prg2; + }; + soc { ocram2: sram@940000 { compatible = "mmio-sram"; @@ -20,57 +29,63 @@ aips-bus@2100000 { pre1: pre@21c8000 { - compatible = "fsl,imx6qp-pre"; + compatible = "fsl,imx6q-pre"; reg = <0x021c8000 0x1000>; interrupts = ; clocks = <&clks IMX6QDL_CLK_PRE0>; clock-names = "axi"; - fsl,iram = <&ocram2>; + ocram = <&ocram2>; + status = "disabled"; }; pre2: pre@21c9000 { - compatible = "fsl,imx6qp-pre"; + compatible = "fsl,imx6q-pre"; reg = <0x021c9000 0x1000>; interrupts = ; clocks = <&clks IMX6QDL_CLK_PRE1>; clock-names = "axi"; - fsl,iram = <&ocram2>; + ocram = <&ocram2>; + status = "disabled"; }; pre3: pre@21ca000 { - compatible = "fsl,imx6qp-pre"; + compatible = "fsl,imx6q-pre"; reg = <0x021ca000 0x1000>; interrupts = ; clocks = <&clks IMX6QDL_CLK_PRE2>; clock-names = "axi"; - fsl,iram = <&ocram3>; + ocram = <&ocram3>; + status = "disabled"; }; pre4: pre@21cb000 { - compatible = "fsl,imx6qp-pre"; + compatible = "fsl,imx6q-pre"; reg = <0x021cb000 0x1000>; interrupts = ; clocks = <&clks IMX6QDL_CLK_PRE3>; clock-names = "axi"; - fsl,iram = <&ocram3>; + ocram = <&ocram3>; + status = "disabled"; }; prg1: prg@21cc000 { - compatible = "fsl,imx6qp-prg"; + compatible = "fsl,imx6q-prg"; reg = <0x021cc000 0x1000>; clocks = <&clks IMX6QDL_CLK_PRG0_APB>, <&clks IMX6QDL_CLK_PRG0_AXI>; - clock-names = "ipg", "axi"; - fsl,pres = <&pre1>, <&pre2>, <&pre3>; + clock-names = "apb", "axi"; + gpr = <&gpr>; + status = "disabled"; }; prg2: prg@21cd000 { - compatible = "fsl,imx6qp-prg"; + compatible = "fsl,imx6q-prg"; reg = <0x021cd000 0x1000>; clocks = <&clks IMX6QDL_CLK_PRG1_APB>, <&clks IMX6QDL_CLK_PRG1_AXI>; - clock-names = "ipg", "axi"; - fsl,pres = <&pre4>, <&pre2>, <&pre3>; + clock-names = "apb", "axi"; + gpr = <&gpr>; + status = "disabled"; }; }; }; @@ -87,22 +102,34 @@ &ipu1 { compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; + clocks = <&clks IMX6QDL_CLK_IPU1>, + <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>, + <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>, + <&clks IMX6QDL_CLK_PRG0_APB>; + clock-names = "bus", + "di0", "di1", + "di0_sel", "di1_sel", + "ldb_di0", "ldb_di1", "prg"; fsl,prg = <&prg1>; }; &ipu2 { compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; + clocks = <&clks IMX6QDL_CLK_IPU2>, + <&clks IMX6QDL_CLK_IPU2_DI0>, <&clks IMX6QDL_CLK_IPU2_DI1>, + <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>, + <&clks IMX6QDL_CLK_PRG1_APB>; + clock-names = "bus", + "di0", "di1", + "di0_sel", "di1_sel", + "ldb_di0", "ldb_di1", "prg"; fsl,prg = <&prg2>; }; &ldb { - clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", "di2_sel", "di3_sel", - "di0", "di1"; + compatible = "fsl,imx6qp-ldb", "fsl,imx6q-ldb", "fsl,imx53-ldb"; }; &mmdc0 { diff --git a/arch/arm/boot/dts/imx6sl-evk-btwifi.dts b/arch/arm/boot/dts/imx6sl-evk-btwifi.dts new file mode 100644 index 00000000000000..01867f57d41a0d --- /dev/null +++ b/arch/arm/boot/dts/imx6sl-evk-btwifi.dts @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* NOTE: This DTS file is written for plugging in Murata Wi-Fi/BT EVK into SD1 + * slot using Murata i.MX InterConnect Ver 1.0 Adapter AND wiring in control + * signals with SD Card Extender on SD3 slot. + * Bluetooth UART connect via SD1 EMMC/MMC Plus pinout. + * WL_REG_ON/BT_REG_ON/WL_HOST_WAKE are connected from SD Card Extender on SD3 + * slot. + */ +#include "imx6sl-evk.dts" + +/ { + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio5 16 GPIO_ACTIVE_LOW>; + }; +}; + +&iomuxc { + imx6sl-evk-murata-v1_sdext { + /* Only MUX SD1_DAT0..3 lines so UART4 can be MUXed on higher data lines. */ + pinctrl_btreg: btreggrp { + fsl,pins = < + MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x13069 /* BT_REG_ON */ + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x13069 /* WL_HOST_WAKE */ + MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x13069 /* WL_REG_ON */ + >; + }; + + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + >; + }; + }; +}; +/* Murata: declare UART4 interface for Bluetooth. */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4_1 + &pinctrl_btreg>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart4dte_1>; */ +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + bus-width = <4>; + no-1-8-v; + non-removable; + mmc-pwrseq = <&usdhc1_pwrseq>; + pm-ignore-notify; + cap-power-off-card; + /delete-property/ enable-sdio-wakeup; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_1>; + bus-width = <1>; + no-1-8-v; +}; diff --git a/arch/arm/boot/dts/imx6sl-evk-csi.dts b/arch/arm/boot/dts/imx6sl-evk-csi.dts new file mode 100644 index 00000000000000..589d33f715d47c --- /dev/null +++ b/arch/arm/boot/dts/imx6sl-evk-csi.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +// +//Copyright (C) 2013 Freescale Semiconductor, Inc. + +#include "imx6sl-evk.dts" + +&csi { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&epdc { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6sl-evk-ldo.dts b/arch/arm/boot/dts/imx6sl-evk-ldo.dts new file mode 100644 index 00000000000000..5ca3a09df2b948 --- /dev/null +++ b/arch/arm/boot/dts/imx6sl-evk-ldo.dts @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sl-evk.dts" + +&gpc { + /* use ldo-enable, u-boot will check it and configure */ + fsl,ldo-bypass = <0>; +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_pu { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff --git a/arch/arm/boot/dts/imx6sl-evk-uart.dts b/arch/arm/boot/dts/imx6sl-evk-uart.dts new file mode 100644 index 00000000000000..6179842731a7f5 --- /dev/null +++ b/arch/arm/boot/dts/imx6sl-evk-uart.dts @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sl-evk.dts" + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4_1>; + fsl,uart-has-rtscts; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart4dte_1>; */ +}; + +&usdhc1 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index bc86cfaaa9c270..319c881d631d92 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -12,6 +12,19 @@ model = "Freescale i.MX6 SoloLite EVK Board"; compatible = "fsl,imx6sl-evk", "fsl,imx6sl"; + battery: max8903@0 { + compatible = "fsl,max8903-charger"; + pinctrl-names = "default"; + dok_input = <&gpio4 13 1>; + uok_input = <&gpio4 13 1>; + chg_input = <&gpio4 15 1>; + flt_input = <&gpio4 14 1>; + fsl,dcm_always_high; + fsl,dc_valid; + fsl,adc_disable; + status = "okay"; + }; + chosen { stdout-path = &uart1; }; @@ -21,6 +34,19 @@ reg = <0x80000000 0x40000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + backlight_display: backlight_display { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; @@ -40,6 +66,11 @@ }; }; + pxp_v4l2_out { + compatible = "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { compatible = "regulator-fixed"; regulator-name = "usb_otg1_vbus"; @@ -95,7 +126,7 @@ sound { compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; model = "wm8962-audio"; - ssi-controller = <&ssi2>; + audio-cpu = <&ssi2>; audio-codec = <&codec>; audio-routing = "Headphone Jack", "HPOUTL", @@ -106,6 +137,8 @@ "IN3R", "AMIC"; mux-int-port = <2>; mux-ext-port = <3>; + codec-master; + hp-det-gpios = <&gpio4 19 1>; }; panel { @@ -128,6 +161,14 @@ status = "okay"; }; +&csi { + port { + csi_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + &ecspi1 { cs-gpios = <&gpio4 11 0>; pinctrl-names = "default"; @@ -143,6 +184,15 @@ }; }; +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc_0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "okay"; +}; + &fec { pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_fec>; @@ -151,6 +201,10 @@ status = "okay"; }; +&gpc { + fsl,ldo-bypass = <1>; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -257,6 +311,89 @@ }; }; }; + + elan@10 { + compatible = "elan,elan-touch"; + reg = <0x10>; + interrupt-parent = <&gpio2>; + interrupts = <10 2>; + gpio_elan_cs = <&gpio2 9 0>; + gpio_elan_rst = <&gpio4 4 0>; + gpio_intr = <&gpio2 10 0>; + status = "okay"; + }; + + ma8450@1c { + compatible = "fsl,mma8450"; + reg = <0x1c>; + }; + + max17135@48 { + compatible = "maxim,max17135"; + reg = <0x48>; + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio2 13 0>; + gpio_pmic_vcom_ctrl = <&gpio2 3 0>; + gpio_pmic_wakeup = <&gpio2 14 0>; + gpio_pmic_v3p3 = <&gpio2 7 0>; + gpio_pmic_intr = <&gpio2 12 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* Real max value: -500000 */ + regulator-max-microvolt = <4325000>; + /* Real min value: -4325000 */ + regulator-min-microvolt = <500000>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; + }; &i2c2 { @@ -280,6 +417,34 @@ }; }; +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "disabled"; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_0>; + clocks = <&clks IMX6SL_CLK_CSI>; + clock-names = "csi_mclk"; + AVDD-supply = <&vgen6_reg>; /* 2.8v */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio1 25 1>; + rst-gpios = <&gpio1 26 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi_ep>; + }; + }; + }; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; @@ -295,6 +460,13 @@ MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000 MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000 MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 + MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x17000 + MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x80000000 + MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x110b0 + MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000 + MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000 + MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000 + MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b0b0 >; }; @@ -316,6 +488,39 @@ >; }; + pinctrl_epdc_0: epdcgrp-0 { + fsl,pins = < + MX6SL_PAD_EPDC_D0__EPDC_DATA00 0x80000000 + MX6SL_PAD_EPDC_D1__EPDC_DATA01 0x80000000 + MX6SL_PAD_EPDC_D2__EPDC_DATA02 0x80000000 + MX6SL_PAD_EPDC_D3__EPDC_DATA03 0x80000000 + MX6SL_PAD_EPDC_D4__EPDC_DATA04 0x80000000 + MX6SL_PAD_EPDC_D5__EPDC_DATA05 0x80000000 + MX6SL_PAD_EPDC_D6__EPDC_DATA06 0x80000000 + MX6SL_PAD_EPDC_D7__EPDC_DATA07 0x80000000 + MX6SL_PAD_EPDC_D8__EPDC_DATA08 0x80000000 + MX6SL_PAD_EPDC_D9__EPDC_DATA09 0x80000000 + MX6SL_PAD_EPDC_D10__EPDC_DATA10 0x80000000 + MX6SL_PAD_EPDC_D11__EPDC_DATA11 0x80000000 + MX6SL_PAD_EPDC_D12__EPDC_DATA12 0x80000000 + MX6SL_PAD_EPDC_D13__EPDC_DATA13 0x80000000 + MX6SL_PAD_EPDC_D14__EPDC_DATA14 0x80000000 + MX6SL_PAD_EPDC_D15__EPDC_DATA15 0x80000000 + MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x80000000 + MX6SL_PAD_EPDC_GDSP__EPDC_GDSP 0x80000000 + MX6SL_PAD_EPDC_GDOE__EPDC_GDOE 0x80000000 + MX6SL_PAD_EPDC_GDRL__EPDC_GDRL 0x80000000 + MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x80000000 + MX6SL_PAD_EPDC_SDOE__EPDC_SDOE 0x80000000 + MX6SL_PAD_EPDC_SDLE__EPDC_SDLE 0x80000000 + MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x80000000 + MX6SL_PAD_EPDC_BDR0__EPDC_BDR0 0x80000000 + MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x80000000 + MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x80000000 + MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x80000000 + >; + }; + pinctrl_fec: fecgrp { fsl,pins = < MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0 @@ -358,6 +563,13 @@ >; }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SL_PAD_EPDC_SDCE2__I2C3_SCL 0x4001b8b1 + MX6SL_PAD_EPDC_SDCE3__I2C3_SDA 0x4001b8b1 + >; + }; + pinctrl_kpp: kppgrp { fsl,pins = < MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010 @@ -427,6 +639,24 @@ >; }; + pinctrl_uart4_1: uart4grp-1 { + fsl,pins = < + MX6SL_PAD_SD1_DAT4__UART4_RX_DATA 0x1b0b1 + MX6SL_PAD_SD1_DAT5__UART4_TX_DATA 0x1b0b1 + MX6SL_PAD_SD1_DAT7__UART4_CTS_B 0x1b0b1 + MX6SL_PAD_SD1_DAT6__UART4_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4dte_1: uart4dtegrp-1 { + fsl,pins = < + MX6SL_PAD_SD1_DAT5__UART4_RX_DATA 0x1b0b1 + MX6SL_PAD_SD1_DAT4__UART4_TX_DATA 0x1b0b1 + MX6SL_PAD_SD1_DAT6__UART4_CTS_B 0x1b0b1 + MX6SL_PAD_SD1_DAT7__UART4_RTS_B 0x1b0b1 + >; + }; + pinctrl_usbotg1: usbotg1grp { fsl,pins = < MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 @@ -543,9 +773,34 @@ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 >; }; + + pinctrl_csi_0: csigrp-0 { + fsl,pins = < + MX6SL_PAD_EPDC_GDRL__CSI_MCLK 0x110b0 + MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x110b0 + MX6SL_PAD_EPDC_GDSP__CSI_VSYNC 0x110b0 + MX6SL_PAD_EPDC_GDOE__CSI_HSYNC 0x110b0 + MX6SL_PAD_EPDC_SDLE__CSI_DATA09 0x110b0 + MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110b0 + MX6SL_PAD_EPDC_D7__CSI_DATA07 0x110b0 + MX6SL_PAD_EPDC_D6__CSI_DATA06 0x110b0 + MX6SL_PAD_EPDC_D5__CSI_DATA05 0x110b0 + MX6SL_PAD_EPDC_D4__CSI_DATA04 0x110b0 + MX6SL_PAD_EPDC_D3__CSI_DATA03 0x110b0 + MX6SL_PAD_EPDC_D2__CSI_DATA02 0x110b0 + MX6SL_PAD_EPDC_D1__CSI_DATA01 0x110b0 + MX6SL_PAD_EPDC_D0__CSI_DATA00 0x110b0 + MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000 + MX6SL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000 + >; + }; }; }; +&pxp { + status = "okay"; +}; + &kpp { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_kpp>; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 3a96b5538a2a14..2a1c686244a4dd 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -66,11 +66,17 @@ >; clock-latency = <61036>; /* two CLK32 periods */ #cooling-cells = <2>; - clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, - <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>, - <&clks IMX6SL_CLK_PLL1_SYS>; + clocks = <&clks IMX6SL_CLK_ARM>, + <&clks IMX6SL_CLK_PLL2_PFD2>, + <&clks IMX6SL_CLK_STEP>, + <&clks IMX6SL_CLK_PLL1_SW>, + <&clks IMX6SL_CLK_PLL1_SYS>, + <&clks IMX6SL_CLK_PLL1>, + <&clks IMX6SL_PLL1_BYPASS>, + <&clks IMX6SL_PLL1_BYPASS_SRC>; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1", "pll1_bypass", + "pll1_bypass_src"; arm-supply = <®_arm>; pu-supply = <®_pu>; soc-supply = <®_soc>; @@ -118,12 +124,51 @@ interrupt-parent = <&gpc>; ranges; - ocram: sram@900000 { + busfreq { /* BUSFREQ */ + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6SL_CLK_PLL2_BUS>, <&clks IMX6SL_CLK_PLL2_PFD2>, + <&clks IMX6SL_CLK_PLL2_198M>, <&clks IMX6SL_CLK_ARM>, + <&clks IMX6SL_CLK_PLL3_USB_OTG>, <&clks IMX6SL_CLK_PERIPH>, + <&clks IMX6SL_CLK_PRE_PERIPH_SEL>, <&clks IMX6SL_CLK_PERIPH_CLK2_PODF>, + <&clks IMX6SL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SL_CLK_OSC>, + <&clks IMX6SL_CLK_PLL1_SYS>, <&clks IMX6SL_CLK_PERIPH2>, + <&clks IMX6SL_CLK_AHB>, <&clks IMX6SL_CLK_OCRAM_PODF>, + <&clks IMX6SL_CLK_PLL1_SW>, <&clks IMX6SL_CLK_PRE_PERIPH2_SEL>, + <&clks IMX6SL_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SL_CLK_PERIPH2_CLK2_PODF>, + <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_PLL2_BYPASS_SRC>, <&clks IMX6SL_PLL2_BYPASS>, + <&clks IMX6SL_CLK_PLL2>, <&clks IMX6SL_CLK_PLL1>, <&clks IMX6SL_PLL1_BYPASS>, + <&clks IMX6SL_PLL1_BYPASS_SRC>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph", + "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "pll1_sys", "periph2", "ahb", + "ocram", "pll1_sw", "periph2_pre", "periph2_clk2_sel", "periph2_clk2", "step", "pll2_bypass_src", + "pll2_bypass", "pll2", "pll1", "pll1_bypass", "pll1_bypass_src"; + fsl,max_ddr_freq = <400000000>; + }; + + ocrams: sram@900000 { + compatible = "fsl,lpm-sram"; + reg = <0x900000 0x4000>; + clocks = <&clks IMX6SL_CLK_OCRAM>; + }; + + ocrams_ddr: sram@904000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x904000 0x1000>; + clocks = <&clks IMX6SL_CLK_OCRAM>; + }; + + ocram: sram@905000 { compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; + reg = <0x905000 0x1B000>; clocks = <&clks IMX6SL_CLK_OCRAM>; }; + ocram_optee: sram@918000 { + compatible = "fsl,optee-lpm-sram"; + reg = <0x918000 0x8000>; + overw_reg = <&ocram 0x905000 0x13000>; + }; + intc: interrupt-controller@a01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -591,6 +636,7 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; reg_pu: regulator-vddpu { @@ -607,6 +653,7 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; reg_soc: regulator-vddsoc { @@ -624,6 +671,7 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; }; @@ -734,8 +782,14 @@ }; csi: csi@20e4000 { - reg = <0x020e4000 0x4000>; + compatible = "fsl,imx6sl-csi"; + reg = <0x20e4000 0x4000>; interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_DUMMY>, + <&clks IMX6SL_CLK_DUMMY>, + <&clks IMX6SL_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; }; spdc: spdc@20e8000 { @@ -756,13 +810,20 @@ }; pxp: pxp@20f0000 { - reg = <0x020f0000 0x4000>; + compatible = "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma"; + reg = <0x20f0000 0x4000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_PXP_AXI>, <&clks IMX6SL_CLK_DUMMY>; + clock-names = "pxp-axi", "disp-axi"; + status = "disabled"; }; epdc: epdc@20f4000 { - reg = <0x020f4000 0x4000>; + compatible = "fsl,imx6sl-epdc", "fsl,imx6dl-epdc"; + reg = <0x20f4000 0x4000>; interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_EPDC_AXI>, <&clks IMX6SL_CLK_EPDC_PIX>; + clock-names = "epdc_axi", "epdc_pix"; }; lcdif: lcdif@20f8000 { @@ -936,8 +997,10 @@ }; rngb: rngb@21b4000 { + compatible = "fsl,imx25-rngb"; reg = <0x021b4000 0x4000>; interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_DUMMY>; }; weim: weim@21b8000 { diff --git a/arch/arm/boot/dts/imx6sll-evk-btwifi.dts b/arch/arm/boot/dts/imx6sll-evk-btwifi.dts new file mode 100644 index 00000000000000..f025c76cb4c17b --- /dev/null +++ b/arch/arm/boot/dts/imx6sll-evk-btwifi.dts @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * NOTE: This DTS file is wrote for plugging in Murata 1MW M.2 + * into SD3 slot by using Murata uSD-to-M.2 Adapter. + * + * By default, OOB IRQ is not enabled since i.MX6SLL EVK board needs to rework. + * How to enable OOB IRQ ? + * HW rework: + * Install R127 on i.MX6SLL EVK board. + * SW change: add below pin for WL_HOST_WAKE + * pinctrl_wifi: wifigrp { + * fsl,pins = < + * ... + * MX6SLL_PAD_KEY_COL1__GPIO3_IO26 0x0b001 + * >; + * }; + * brcmf: bcrmf@1 { + * reg = <1>; + * compatible = "brcm,bcm4329-fmac"; + * interrupt-parent = <&gpio3>; + * interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + * interrupt-names = "host-wake"; + * }; + */ + +#include "imx6sll-evk.dts" + +/ { + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; + }; +}; + +&iomuxc { + pinctrl_wifi: wifigrp { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130b9 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9 + + MX6SLL_PAD_KEY_COL0__GPIO3_IO24 0x17059 /* WL_REG_ON */ + MX6SLL_PAD_KEY_COL1__GPIO3_IO26 0x0b001 + >; + }; +}; + +&lcdif { + status = "disabled"; +}; + +®_sd3_vmmc { + regulator-always-on; +}; + +&uart5 { + resets = <&modem_reset>; + status = "okay"; +}; + +&usdhc3 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + bus-width = <4>; + no-1-8-v; + non-removable; + mmc-pwrseq = <&usdhc1_pwrseq>; + pm-ignore-notify; + cap-power-off-card; + /delete-property/ cd-gpios; + /delete-property/ vmmc-supply; + /delete-property/ enable-sdio-wakeup; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; diff --git a/arch/arm/boot/dts/imx6sll-evk-reva.dts b/arch/arm/boot/dts/imx6sll-evk-reva.dts new file mode 100644 index 00000000000000..3704e8543f6f56 --- /dev/null +++ b/arch/arm/boot/dts/imx6sll-evk-reva.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP. + * + */ + +/dts-v1/; + +#include "imx6sll-evk.dts" + +&usdhc2 { + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; +}; + diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts index 5ace9e6acf85ca..8755d69c499ad1 100644 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -24,6 +24,19 @@ reg = <0x80000000 0x80000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + backlight_display: backlight-display { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; @@ -32,6 +45,19 @@ status = "okay"; }; + battery: max8903@0 { + compatible = "fsl,max8903-charger"; + pinctrl-names = "default"; + dok_input = <&gpio4 13 1>; + uok_input = <&gpio4 13 1>; + chg_input = <&gpio4 15 1>; + flt_input = <&gpio4 14 1>; + fsl,dcm_always_high; + fsl,dc_valid; + fsl,adc_disable; + status = "okay"; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -44,6 +70,11 @@ }; }; + pxp_v4l2_out { + compatible = "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + reg_usb_otg1_vbus: regulator-otg1-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -106,9 +137,18 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; enable-active-high; }; + reg_sd2_vmmc: regulator-sd2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "eMMC-VCCQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + reg_sd3_vmmc: regulator-sd3-vmmc { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -117,28 +157,53 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; enable-active-high; }; - panel { - compatible = "sii,43wvf1g"; - backlight = <&backlight_display>; - dvdd-supply = <®_lcd_3v3>; - avdd-supply = <®_lcd_5v>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; + sound { + compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + audio-cpu = <&ssi2>; + audio-codec = <&codec>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC"; + mux-int-port = <2>; + mux-ext-port = <3>; + codec-master; + hp-det-gpios = <&gpio4 24 1>; }; }; +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux3>; + status = "okay"; +}; + &cpu0 { arm-supply = <&sw1a_reg>; soc-supply = <&sw1c_reg>; }; +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "okay"; +}; + +&gpc { + fsl,ldo-bypass = <1>; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -245,6 +310,98 @@ }; }; }; + + max17135: max17135@48 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_max17135>; + compatible = "maxim,max17135"; + reg = <0x48>; + status = "okay"; + + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio2 13 0>; + gpio_pmic_vcom_ctrl = <&gpio2 3 0>; + gpio_pmic_wakeup = <&gpio2 14 0>; + gpio_pmic_v3p3 = <&gpio2 7 0>; + gpio_pmic_intr = <&gpio2 12 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* Real max value: -500000 */ + regulator-max-microvolt = <4325000>; + /* Real min value: -4325000 */ + regulator-min-microvolt = <500000>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>; + DCVDD-supply = <&vgen3_reg>; + DBVDD-supply = <®_aud3v>; + AVDD-supply = <&vgen3_reg>; + CPVDD-supply = <&vgen3_reg>; + MICVDD-supply = <®_aud3v>; + PLLVDD-supply = <&vgen3_reg>; + SPKVDD1-supply = <®_aud4v>; + SPKVDD2-supply = <®_aud4v>; + amic-mono; + }; }; &lcdif { @@ -252,9 +409,30 @@ pinctrl-0 = <&pinctrl_lcd>; status = "okay"; - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; + lcd-supply = <®_lcd_3v3>; + display = <&display0>; + + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; }; }; }; @@ -265,6 +443,10 @@ status = "okay"; }; +&pxp { + status = "okay"; +}; + &snvs_poweroff { status = "okay"; }; @@ -273,12 +455,26 @@ status = "okay"; }; +&ssi2 { + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + fsl,uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart5dte>; */ + status = "disabled"; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -292,6 +488,17 @@ status = "okay"; }; +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <8>; + non-removable; + vqmmc-supply = <®_sd2_vmmc>; + status = "okay"; +}; + &usbotg1 { vbus-supply = <®_usb_otg1_vbus>; pinctrl-names = "default"; @@ -329,6 +536,69 @@ }; &iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */ + /* CHG_FLT, CHG_UOK/DOK, CHG_STATUS */ + MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000 + MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000 + MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000 + >; + }; + + pinctrl_audmux3: audmux3grp { + fsl,pins = < + MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x4130b0 + MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0 + MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x4110b0 + MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x4130b0 + MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 + >; + }; + + pinctrl_epdc0: epdcgrp0 { + fsl,pins = < + MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x100b1 + MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x100b1 + MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x100b1 + MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x100b1 + MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x100b1 + MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x100b1 + MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x100b1 + MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x100b1 + MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x100b1 + MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x100b1 + MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x100b1 + MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x100b1 + MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x100b1 + MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x100b1 + MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x100b1 + MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x100b1 + MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x100b1 + MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x100b1 + MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x100b1 + MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x100b1 + MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100b1 + MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x100b1 + MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x100b1 + MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x100b1 + MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x100b1 + >; + }; + + pinctrl_max17135: max17135grp-1 { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x80000000 /* pwrgood */ + MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x80000000 /* vcom_ctrl */ + MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x80000000 /* wakeup */ + MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x80000000 /* v3p3 */ + MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x80000000 /* pwr int */ + >; + }; + pinctrl_reg_sd3_vmmc: sd3vmmcgrp { fsl,pins = < MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 @@ -366,6 +636,25 @@ >; }; + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x1b0b1 /* bt reg on */ + MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x1b0b1 + MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x1b0b1 + MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x1b0b1 + MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart5dte: uart5dtegrp { + fsl,pins = < + MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x1b0b1 + MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x1b0b1 + MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x1b0b1 + MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x1b0b1 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059 @@ -399,6 +688,54 @@ >; }; + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x17059 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x17059 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x17059 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x17059 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x413059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170b9 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170b9 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170b9 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170b9 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170f9 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170f9 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170f9 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170f9 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130f9 + >; + }; + pinctrl_usbotg1: usbotg1grp { fsl,pins = < MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 @@ -448,6 +785,13 @@ >; }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x4041b8b1 + MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x4041b8b1 + >; + }; + pinctrl_lcd: lcdgrp { fsl,pins = < MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79 diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index 13c7ba7fa6bc9e..73decc1b5c9ece 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -65,13 +65,18 @@ >; clock-latency = <61036>; /* two CLK32 periods */ #cooling-cells = <2>; + fsl,low-power-run; clocks = <&clks IMX6SLL_CLK_ARM>, <&clks IMX6SLL_CLK_PLL2_PFD2>, <&clks IMX6SLL_CLK_STEP>, <&clks IMX6SLL_CLK_PLL1_SW>, - <&clks IMX6SLL_CLK_PLL1_SYS>; + <&clks IMX6SLL_CLK_PLL1_SYS>, + <&clks IMX6SLL_CLK_PLL1>, + <&clks IMX6SLL_PLL1_BYPASS>, + <&clks IMX6SLL_PLL1_BYPASS_SRC>; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1", "pll1_bypass", + "pll1_bypass_src"; }; }; @@ -120,9 +125,45 @@ interrupt-parent = <&gpc>; ranges; - ocram: sram@900000 { + busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6SLL_CLK_PLL2_PFD2>, <&clks IMX6SLL_CLK_PLL2_198M>, + <&clks IMX6SLL_CLK_PLL2_BUS>, <&clks IMX6SLL_CLK_ARM>, + <&clks IMX6SLL_CLK_PLL3_USB_OTG>, <&clks IMX6SLL_CLK_PERIPH>, + <&clks IMX6SLL_CLK_PERIPH_PRE>, <&clks IMX6SLL_CLK_PERIPH_CLK2>, + <&clks IMX6SLL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SLL_CLK_OSC>, + <&clks IMX6SLL_CLK_AHB>, <&clks IMX6SLL_CLK_AXI_PODF>, + <&clks IMX6SLL_CLK_PERIPH2>, <&clks IMX6SLL_CLK_PERIPH2_PRE>, + <&clks IMX6SLL_CLK_PERIPH2_CLK2>, <&clks IMX6SLL_CLK_PERIPH2_CLK2_SEL>, + <&clks IMX6SLL_CLK_STEP>, <&clks IMX6SLL_CLK_MMDC_P0_FAST>, <&clks IMX6SLL_PLL1_BYPASS_SRC>, + <&clks IMX6SLL_PLL1_BYPASS>, <&clks IMX6SLL_CLK_PLL1_SYS>, <&clks IMX6SLL_CLK_PLL1_SW>, + <&clks IMX6SLL_CLK_PLL1>; + clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg", + "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", + "ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel", + "step", "mmdc", "pll1_bypass_src", "pll1_bypass", "pll1_sys", "pll1_sw", "pll1"; + fsl,max_ddr_freq = <400000000>; + }; + + ocrams: sram@900000 { + compatible = "fsl,lpm-sram"; + reg = <0x900000 0x4000>; + }; + + ocrams_ddr: sram@904000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x904000 0x1000>; + }; + + ocram: sram@905000 { compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; + reg = <0x905000 0x1B000>; + }; + + ocram_optee: sram@918000 { + compatible = "fsl,optee-lpm-sram"; + reg = <0x918000 0x8000>; + overw_reg = <&ocram 0x905000 0x13000>; }; intc: interrupt-controller@a01000 { @@ -183,7 +224,7 @@ }; ecspi1: spi@2008000 { - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + compatible ="fsl,imx51-ecspi"; reg = <0x02008000 0x4000>; interrupts = ; dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; @@ -195,7 +236,7 @@ }; ecspi2: spi@200c000 { - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + compatible = "fsl,imx51-ecspi"; reg = <0x0200c000 0x4000>; interrupts = ; dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; @@ -207,7 +248,7 @@ }; ecspi3: spi@2010000 { - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + compatible = "fsl,imx51-ecspi"; reg = <0x02010000 0x4000>; interrupts = ; dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; @@ -219,7 +260,7 @@ }; ecspi4: spi@2014000 { - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + compatible = "fsl,imx51-ecspi"; reg = <0x02014000 0x4000>; interrupts = ; dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; @@ -596,6 +637,7 @@ #interrupt-cells = <3>; interrupts = ; interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00 0x0 0x1400640>; }; iomuxc: pinctrl@20e0000 { @@ -621,7 +663,7 @@ }; sdma: dma-controller@20ec000 { - compatible = "fsl,imx6sll-sdma", "fsl,imx6ul-sdma"; + compatible = "fsl,imx6ul-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; interrupts = ; clocks = <&clks IMX6SLL_CLK_IPG>, @@ -632,6 +674,26 @@ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; }; + pxp: pxp@20f0000 { + compatible = "fsl,imx6ull-pxp-dma", "fsl,imx7d-pxp-dma"; + reg = <0x20f0000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_PXP>; + clock-names = "pxp_ipg", "pxp_axi"; + status = "disabled"; + }; + + epdc: epdc@20f4000 { + compatible = "fsl,imx6sll-epdc", "fsl,imx7d-epdc"; + reg = <0x20f4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_EPDC_AXI>, <&clks IMX6SLL_CLK_EPDC_PIX>; + clock-names = "epdc_axi", "epdc_pix"; + status = "disabled"; + }; + lcdif: lcd-controller@20f8000 { compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif"; reg = <0x020f8000 0x4000>; @@ -698,7 +760,7 @@ }; usdhc1: mmc@2190000 { - compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc"; reg = <0x02190000 0x4000>; interrupts = ; clocks = <&clks IMX6SLL_CLK_USDHC1>, @@ -712,7 +774,7 @@ }; usdhc2: mmc@2194000 { - compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc"; reg = <0x02194000 0x4000>; interrupts = ; clocks = <&clks IMX6SLL_CLK_USDHC2>, @@ -726,7 +788,7 @@ }; usdhc3: mmc@2198000 { - compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc"; reg = <0x02198000 0x4000>; interrupts = ; clocks = <&clks IMX6SLL_CLK_USDHC3>, @@ -775,6 +837,13 @@ clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>; }; + rngb: rng@21b4000 { + compatible = "fsl,imx25-rngb"; + reg = <0x021b4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_DUMMY>; + }; + ocotp: ocotp-ctrl@21bc000 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx6sx-pinfunc.h b/arch/arm/boot/dts/imx6sx-pinfunc.h index aa194a2fdd5350..df9a6c5b5adab7 100644 --- a/arch/arm/boot/dts/imx6sx-pinfunc.h +++ b/arch/arm/boot/dts/imx6sx-pinfunc.h @@ -66,6 +66,7 @@ #define MX6SX_PAD_GPIO1_IO06__ENET2_MDC 0x002C 0x0374 0x0000 0x2 0x0 #define MX6SX_PAD_GPIO1_IO06__CSI1_MCLK 0x002C 0x0374 0x0000 0x3 0x0 #define MX6SX_PAD_GPIO1_IO06__UART1_RTS_B 0x002C 0x0374 0x082C 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO06__UART1_CTS_B 0x002C 0x0374 0x0000 0x4 0x0 #define MX6SX_PAD_GPIO1_IO06__GPIO1_IO_6 0x002C 0x0374 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO06__SRC_ANY_PU_RESET 0x002C 0x0374 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x002C 0x0374 0x0000 0x7 0x0 @@ -75,6 +76,7 @@ #define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0 #define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0 #define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B 0x0030 0x0378 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO07__UART1_RTS_B 0x0030 0x0378 0x082C 0x4 0x1 #define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0 @@ -84,6 +86,7 @@ #define MX6SX_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 0x0034 0x037C 0x081C 0x2 0x0 #define MX6SX_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x0034 0x037C 0x069C 0x3 0x1 #define MX6SX_PAD_GPIO1_IO08__UART2_RTS_B 0x0034 0x037C 0x0834 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO08__UART2_CTS_B 0x0034 0x037C 0x0000 0x4 0x0 #define MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x0034 0x037C 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO08__SRC_SYSTEM_RESET 0x0034 0x037C 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO08__DCIC1_OUT 0x0034 0x037C 0x0000 0x7 0x0 @@ -93,6 +96,7 @@ #define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0 #define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0 #define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B 0x0038 0x0380 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO09__UART2_RTS_B 0x0038 0x0380 0x0834 0x4 0x1 #define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0 @@ -200,6 +204,7 @@ #define MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x0064 0x03AC 0x07C0 0x2 0x2 #define MX6SX_PAD_CSI_DATA06__KPP_COL_7 0x0064 0x03AC 0x07D0 0x3 0x0 #define MX6SX_PAD_CSI_DATA06__UART6_RTS_B 0x0064 0x03AC 0x0854 0x4 0x0 +#define MX6SX_PAD_CSI_DATA06__UART6_CTS_B 0x0064 0x03AC 0x0000 0x4 0x0 #define MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x0064 0x03AC 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_DATA06__WEIM_DATA_17 0x0064 0x03AC 0x0000 0x6 0x0 #define MX6SX_PAD_CSI_DATA06__DCIC2_OUT 0x0064 0x03AC 0x0000 0x7 0x0 @@ -210,6 +215,7 @@ #define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2 #define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0 #define MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x0068 0x03B0 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_DATA07__UART6_RTS_B 0x0068 0x03B0 0x0854 0x4 0x1 #define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0 #define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0 @@ -219,6 +225,7 @@ #define MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x006C 0x03B4 0x0790 0x1 0x1 #define MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x006C 0x03B4 0x0678 0x2 0x1 #define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B 0x006C 0x03B4 0x0844 0x3 0x2 +#define MX6SX_PAD_CSI_HSYNC__UART4_CTS_B 0x006C 0x03B4 0x0000 0x3 0x0 #define MX6SX_PAD_CSI_HSYNC__MQS_LEFT 0x006C 0x03B4 0x0000 0x4 0x0 #define MX6SX_PAD_CSI_HSYNC__GPIO1_IO_22 0x006C 0x03B4 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_HSYNC__WEIM_DATA_25 0x006C 0x03B4 0x0000 0x6 0x0 @@ -251,6 +258,7 @@ #define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1 #define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1 #define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B 0x0078 0x03C0 0x0000 0x3 0x0 +#define MX6SX_PAD_CSI_VSYNC__UART4_RTS_B 0x0078 0x03C0 0x0844 0x3 0x3 #define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0 #define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0 @@ -353,6 +361,7 @@ #define MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x009C 0x03E4 0x0000 0x1 0x0 #define MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL 0x009C 0x03E4 0x07B8 0x2 0x1 #define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B 0x009C 0x03E4 0x082C 0x3 0x2 +#define MX6SX_PAD_ENET2_RX_CLK__UART1_CTS_B 0x009C 0x03E4 0x0000 0x3 0x0 #define MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x009C 0x03E4 0x07EC 0x4 0x1 #define MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0x009C 0x03E4 0x0000 0x5 0x0 #define MX6SX_PAD_ENET2_RX_CLK__USB_OTG2_OC 0x009C 0x03E4 0x085C 0x6 0x1 @@ -363,6 +372,7 @@ #define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1 #define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1 #define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x00A0 0x03E8 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET2_TX_CLK__UART1_RTS_B 0x00A0 0x03E8 0x082C 0x3 0x3 #define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1 #define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0 #define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0 @@ -372,6 +382,7 @@ #define MX6SX_PAD_KEY_COL0__KPP_COL_0 0x00A4 0x03EC 0x0000 0x0 0x0 #define MX6SX_PAD_KEY_COL0__USDHC3_CD_B 0x00A4 0x03EC 0x0000 0x1 0x0 #define MX6SX_PAD_KEY_COL0__UART6_RTS_B 0x00A4 0x03EC 0x0854 0x2 0x2 +#define MX6SX_PAD_KEY_COL0__UART6_CTS_B 0x00A4 0x03EC 0x0000 0x2 0x0 #define MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x00A4 0x03EC 0x0710 0x3 0x0 #define MX6SX_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x00A4 0x03EC 0x066C 0x4 0x0 #define MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x00A4 0x03EC 0x0000 0x5 0x0 @@ -390,6 +401,7 @@ #define MX6SX_PAD_KEY_COL2__KPP_COL_2 0x00AC 0x03F4 0x0000 0x0 0x0 #define MX6SX_PAD_KEY_COL2__USDHC4_CD_B 0x00AC 0x03F4 0x0874 0x1 0x1 #define MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x00AC 0x03F4 0x084C 0x2 0x2 +#define MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x00AC 0x03F4 0x0000 0x2 0x0 #define MX6SX_PAD_KEY_COL2__CAN1_TX 0x00AC 0x03F4 0x0000 0x3 0x0 #define MX6SX_PAD_KEY_COL2__CANFD_TX1 0x00AC 0x03F4 0x0000 0x4 0x0 #define MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x00AC 0x03F4 0x0000 0x5 0x0 @@ -415,6 +427,7 @@ #define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0 #define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0 #define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8 0x0400 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_ROW0__UART6_RTS_B 0x00B8 0x0400 0x0854 0x2 0x3 #define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0 #define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0 #define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0 @@ -434,6 +447,7 @@ #define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0 #define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1 #define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0 0x0408 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x00C0 0x0408 0x084C 0x2 0x3 #define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1 #define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1 #define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0 @@ -816,6 +830,7 @@ #define MX6SX_PAD_NAND_DATA04__USDHC2_DATA4 0x0160 0x04A8 0x0000 0x1 0x0 #define MX6SX_PAD_NAND_DATA04__QSPI2_B_SS1_B 0x0160 0x04A8 0x0000 0x2 0x0 #define MX6SX_PAD_NAND_DATA04__UART3_RTS_B 0x0160 0x04A8 0x083C 0x3 0x0 +#define MX6SX_PAD_NAND_DATA04__UART3_CTS_B 0x0160 0x04A8 0x0000 0x3 0x0 #define MX6SX_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS 0x0160 0x04A8 0x0650 0x4 0x0 #define MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x0160 0x04A8 0x0000 0x5 0x0 #define MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0x0160 0x04A8 0x0000 0x6 0x0 @@ -826,6 +841,7 @@ #define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0 #define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0 #define MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x0164 0x04AC 0x0000 0x3 0x0 +#define MX6SX_PAD_NAND_DATA05__UART3_RTS_B 0x0164 0x04AC 0x083C 0x3 0x1 #define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0 #define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0 #define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0 @@ -968,6 +984,7 @@ #define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0 #define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0 #define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B 0x01A0 0x04E8 0x0000 0x1 0x0 +#define MX6SX_PAD_QSPI1B_DATA0__UART3_RTS_B 0x01A0 0x04E8 0x083C 0x1 0x4 #define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1 #define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2 #define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1 @@ -976,6 +993,7 @@ #define MX6SX_PAD_QSPI1B_DATA0__SIM_M_HADDR_9 0x01A0 0x04E8 0x0000 0x7 0x0 #define MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x01A4 0x04EC 0x0000 0x0 0x0 #define MX6SX_PAD_QSPI1B_DATA1__UART3_RTS_B 0x01A4 0x04EC 0x083C 0x1 0x5 +#define MX6SX_PAD_QSPI1B_DATA1__UART3_CTS_B 0x01A4 0x04EC 0x0000 0x1 0x0 #define MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO 0x01A4 0x04EC 0x0734 0x2 0x1 #define MX6SX_PAD_QSPI1B_DATA1__ESAI_RX_CLK 0x01A4 0x04EC 0x0788 0x3 0x2 #define MX6SX_PAD_QSPI1B_DATA1__CSI1_DATA_21 0x01A4 0x04EC 0x06F0 0x4 0x1 @@ -1247,6 +1265,7 @@ #define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0 #define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0 #define MX6SX_PAD_SD1_DATA2__UART2_CTS_B 0x0230 0x0578 0x0000 0x4 0x0 +#define MX6SX_PAD_SD1_DATA2__UART2_RTS_B 0x0230 0x0578 0x0834 0x4 0x2 #define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0 #define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0 #define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0 @@ -1256,6 +1275,7 @@ #define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x0234 0x057C 0x065C 0x2 0x2 #define MX6SX_PAD_SD1_DATA3__GPT_COMPARE3 0x0234 0x057C 0x0000 0x3 0x0 #define MX6SX_PAD_SD1_DATA3__UART2_RTS_B 0x0234 0x057C 0x0834 0x4 0x3 +#define MX6SX_PAD_SD1_DATA3__UART2_CTS_B 0x0234 0x057C 0x0000 0x4 0x0 #define MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0x0234 0x057C 0x0000 0x5 0x0 #define MX6SX_PAD_SD1_DATA3__ECSPI4_SS1 0x0234 0x057C 0x0000 0x6 0x0 #define MX6SX_PAD_SD1_DATA3__CCM_PMIC_RDY 0x0234 0x057C 0x069C 0x7 0x2 @@ -1326,6 +1346,7 @@ #define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0 #define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0 #define MX6SX_PAD_SD3_CLK__UART4_CTS_B 0x0250 0x0598 0x0000 0x1 0x0 +#define MX6SX_PAD_SD3_CLK__UART4_RTS_B 0x0250 0x0598 0x0844 0x1 0x0 #define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0 #define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0 #define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0 @@ -1365,6 +1386,7 @@ #define MX6SX_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1 0x025C 0x05A4 0x0000 0x9 0x0 #define MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x0260 0x05A8 0x0000 0x0 0x0 #define MX6SX_PAD_SD3_DATA2__UART4_RTS_B 0x0260 0x05A8 0x0844 0x1 0x1 +#define MX6SX_PAD_SD3_DATA2__UART4_CTS_B 0x0260 0x05A8 0x0000 0x1 0x0 #define MX6SX_PAD_SD3_DATA2__ECSPI4_SS0 0x0260 0x05A8 0x074C 0x2 0x0 #define MX6SX_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS 0x0260 0x05A8 0x0688 0x3 0x0 #define MX6SX_PAD_SD3_DATA2__LCDIF2_CLK 0x0260 0x05A8 0x0000 0x4 0x0 @@ -1410,6 +1432,7 @@ #define MX6SX_PAD_SD3_DATA6__CAN2_TX 0x0270 0x05B8 0x0000 0x1 0x0 #define MX6SX_PAD_SD3_DATA6__CANFD_TX2 0x0270 0x05B8 0x0000 0x2 0x0 #define MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x0270 0x05B8 0x083C 0x3 0x2 +#define MX6SX_PAD_SD3_DATA6__UART3_CTS_B 0x0270 0x05B8 0x0000 0x3 0x0 #define MX6SX_PAD_SD3_DATA6__LCDIF2_DATA_4 0x0270 0x05B8 0x0000 0x4 0x0 #define MX6SX_PAD_SD3_DATA6__GPIO7_IO_8 0x0270 0x05B8 0x0000 0x5 0x0 #define MX6SX_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT 0x0270 0x05B8 0x0000 0x6 0x0 @@ -1420,6 +1443,7 @@ #define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0 #define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0 #define MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x0274 0x05BC 0x0000 0x3 0x0 +#define MX6SX_PAD_SD3_DATA7__UART3_RTS_B 0x0274 0x05BC 0x083C 0x3 0x3 #define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0 #define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0 #define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0 @@ -1511,6 +1535,7 @@ #define MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x0298 0x05E0 0x0000 0x0 0x0 #define MX6SX_PAD_SD4_DATA6__RAWNAND_CE3_B 0x0298 0x05E0 0x0000 0x1 0x0 #define MX6SX_PAD_SD4_DATA6__UART5_RTS_B 0x0298 0x05E0 0x084C 0x2 0x0 +#define MX6SX_PAD_SD4_DATA6__UART5_CTS_B 0x0298 0x05E0 0x0000 0x2 0x0 #define MX6SX_PAD_SD4_DATA6__ECSPI3_MISO 0x0298 0x05E0 0x0734 0x3 0x0 #define MX6SX_PAD_SD4_DATA6__LCDIF2_DATA_6 0x0298 0x05E0 0x0000 0x4 0x0 #define MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x0298 0x05E0 0x0000 0x5 0x0 @@ -1521,6 +1546,7 @@ #define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0 #define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0 #define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C 0x05E4 0x0000 0x2 0x0 +#define MX6SX_PAD_SD4_DATA7__UART5_RTS_B 0x029C 0x05E4 0x084C 0x2 0x1 #define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0 #define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0 #define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0 diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts index e4719566133c88..8131116c2186cb 100644 --- a/arch/arm/boot/dts/imx6sx-sabreauto.dts +++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts @@ -66,12 +66,153 @@ enable-active-high; vin-supply = <®_can_en>; }; + + reg_vref_3v3: regulator-adc-verf { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_audio: cs42888_supply { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + si4763_vio1: vio1_tnr { + compatible = "regulator-fixed"; + regulator-name = "vio1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + si4763_vio2: vio2_tnr { + compatible = "regulator-fixed"; + regulator-name = "vio2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + si4763_vd: f3v3_tnr { + compatible = "regulator-fixed"; + regulator-name = "vd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + si4763_va: f5v_tnr { + compatible = "regulator-fixed"; + regulator-name = "va"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + sound-cs42888 { + compatible = "fsl,imx6-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai>; + asrc-controller = <&asrc>; + audio-codec = <&codec>; + }; + + sound-fm { + compatible = "fsl,imx-audio-si476x", + "fsl,imx-tuner-si476x"; + model = "imx-radio-si4763"; + + ssi-controller = <&ssi2>; + fm-controller = <&si476x_codec>; + mux-int-port = <2>; + mux-ext-port = <5>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-in; + }; +}; + +&adc1 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_3v3>; + status = "okay"; }; &anaclk2 { clock-frequency = <24576000>; }; +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_3>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6SX_PLL4_BYPASS_SRC>, + <&clks IMX6SX_PLL4_BYPASS>, + <&clks IMX6SX_CLK_PLL4_POST_DIV>; + assigned-clock-parents = <&clks IMX6SX_CLK_LVDS2_IN>, + <&clks IMX6SX_PLL4_BYPASS_SRC>; + assigned-clock-rates = <0>, <0>, <24576000>; +}; + +&esai { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai_2>; + assigned-clocks = <&clks IMX6SX_CLK_ESAI_SEL>, + <&clks IMX6SX_CLK_ESAI_EXTAL>; + assigned-clock-parents = <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <24576000>; + status = "okay"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif_3>; + status = "okay"; +}; + +&ssi2 { + fsl,mode = "i2s-master"; + status = "okay"; +}; + +&csi2 { + status = "okay"; + port { + csi2_ep: endpoint { + remote-endpoint = <&vadc_ep>; + }; + }; +}; + +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-lcdif1"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds"; + status = "okay"; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; @@ -87,11 +228,13 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + at803x,eee-disabled; }; ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; + at803x,eee-disabled; }; }; }; @@ -119,12 +262,62 @@ status = "okay"; }; +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + nand-on-flash-bbt; + status = "okay"; +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_1>; + status = "okay"; + ddrsmp=<2>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + reg = <0>; + }; + + flash1: n25q256a@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + reg = <2>; + }; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { /* for bluetooth */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + fsl,uart-has-rtscts; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode;*/ + /* pinctrl-0 = <&pinctrl_uart5dte>; */ +}; + &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; @@ -151,6 +344,14 @@ }; &iomuxc { + pinctrl_audmux_3: audmux-3 { + fsl,pins = < + MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x130b0 + MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x130b0 + MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x130b0 + >; + }; + pinctrl_egalax_int: egalax-intgrp { fsl,pins = < MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x10b0 @@ -193,6 +394,27 @@ >; }; + pinctrl_esai_2: esaigrp-2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 + MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 + MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 + MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 + MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 + MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 + MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 + MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 + >; + }; + + pinctrl_spdif_3: spdifgrp-3 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 + >; + }; + pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 @@ -207,6 +429,27 @@ >; }; + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 @@ -227,6 +470,23 @@ >; }; + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x70a1 + MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x70a1 + MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x70a1 + MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x70a1 + MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x70a1 + MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x70a1 + MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x70a1 + MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x70a1 + MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x70a1 + MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x70a1 + MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x70a1 + MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x70a1 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 @@ -234,6 +494,31 @@ >; }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5dte: uart5dtegrp { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 @@ -313,6 +598,31 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + codec: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&anaclk2 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + }; + + si4763: si4763@63 { + compatible = "si4761"; + reg = <0x63>; + va-supply = <&si4763_va>; + vd-supply = <&si4763_vd>; + vio1-supply = <&si4763_vio1>; + vio2-supply = <&si4763_vio2>; + revision-a10; /* set to default A10 compatible command set */ + + si476x_codec: si476x-codec { + compatible = "si476x-codec"; + }; + }; + touchscreen@4 { compatible = "eeti,egalax_ts"; reg = <0x04>; @@ -452,6 +762,42 @@ gpio-controller; #gpio-cells = <2>; }; + + mma8451@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + position = <7>; + interrupt-parent = <&gpio3>; + interrupts = <24 8>; + interrupt-route = <1>; + }; + + mag3110@e { + compatible = "fsl,mag3110"; + reg = <0xe>; + position = <2>; + interrupt-parent = <&gpio6>; + interrupts = <6 1>; + }; + + isl29023@44 { + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&gpio3>; + interrupts = <23 2>; + }; +}; + +&vadc { + vadc_in = <0>; + csi_id = <1>; + status = "okay"; + port { + vadc_ep: endpoint { + remote-endpoint = <&csi2_ep>; + }; + }; }; &wdog1 { diff --git a/arch/arm/boot/dts/imx6sx-sdb-btwifi.dts b/arch/arm/boot/dts/imx6sx-sdb-btwifi.dts new file mode 100644 index 00000000000000..ab4cde5fe76b22 --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-sdb-btwifi.dts @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * NOTE: This DTS file is wrote for plugging in Murata 1MW M.2 + * into SD2 slot by using Murata uSD-to-M.2 Adapter. + * + * By default, OOB IRQ is not enabled since i.MX6SX SDB board needs to rework. + * How to enable OOB IRQ ? + * HW rework: + * Install R328 on i.MX6SX SDB board. + * SW change: + * pinctrl_wifi: wifigrp { + * fsl,pins = < + * MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0x0b001 + * >; + * }; + * brcmf: bcrmf@1 { + * reg = <1>; + * compatible = "brcm,bcm4329-fmac"; + * interrupt-parent = <&gpio2>; + * interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + * interrupt-names = "host-wake"; + * }; + */ + +#include "imx6sx-sdb.dts" + +/ { + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + + usdhc2_pwrseq: usdhc2_pwrseq { + compatible = "mmc-pwrseq-simple"; + }; +}; + +&iomuxc { + imx6sx-sdb-murata-wifibt { + pinctrl_bt: btgrp { + fsl,pins = < + MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0x13069 /* BT_REG_ON */ + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + >; + }; + }; +}; + +&uart5 { /* for bluetooth */ + pinctrl-0 = <&pinctrl_uart5 &pinctrl_bt>; + resets = <&modem_reset>; +}; + + +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi>; + bus-width = <4>; + no-1-8-v; /* force 3.3V VIO */ + non-removable; + mmc-pwrseq = <&usdhc2_pwrseq>; + pm-ignore-notify; + cap-power-off-card; + /delete-property/ wakeup-source; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; diff --git a/arch/arm/boot/dts/imx6sx-sdb-emmc.dts b/arch/arm/boot/dts/imx6sx-sdb-emmc.dts new file mode 100644 index 00000000000000..b829d7dbe368ac --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-sdb-emmc.dts @@ -0,0 +1,33 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + */ + +#include "imx6sx-sdb.dts" + +/* + * The eMMC chip on imx6sx sdb board is DNP by default. + * Need do hw rework to burn the eMMC4.5 chip on the eMMC socket on uSDHC4 + * and connect eMMC signals as well as disconnect BOOT SD CARD slot signals + */ +&usdhc4 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc4_1>; + pinctrl-1 = <&pinctrl_usdhc4_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc4_1_200mhz>; + bus-width = <8>; + auto-cmd23-broken; + /* + * overwrite cd-gpios and wp-gpios since they are reused as eMMC DATA + * signals after rework + */ + cd-gpios = <>; + wp-gpios = <>; + non-removable; + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/imx6sx-sdb-lcdif1.dts b/arch/arm/boot/dts/imx6sx-sdb-lcdif1.dts new file mode 100644 index 00000000000000..23f69ef9b1e6ec --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-sdb-lcdif1.dts @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + */ + +#include "imx6sx-sdb.dts" + +/ { + sii902x_reset: sii902x-reset { + status = "okay"; + }; +}; + +&csi1 { + status = "disabled"; +}; + +&lcdif1 { + status = "okay"; +}; + +&i2c1 { + sii902x@39 { + status = "okay"; + }; +}; + +&ov5640 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6sx-sdb-ldo.dts b/arch/arm/boot/dts/imx6sx-sdb-ldo.dts new file mode 100644 index 00000000000000..3a8c194ba2d6c4 --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-sdb-ldo.dts @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-sdb.dts" + +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1075000 + 198000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <0>; +}; + +&gpc { + fsl,ldo-bypass = <0>; /* use ldo-enable, u-boot will check it and configure */ +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff --git a/arch/arm/boot/dts/imx6sx-sdb-m4.dts b/arch/arm/boot/dts/imx6sx-sdb-m4.dts new file mode 100644 index 00000000000000..80db8b9dbef6dd --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-sdb-m4.dts @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-sdb.dts" + +/{ + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + m4_reserved: m4@0x9ff00000 { + no-map; + reg = <0x9ff00000 0x100000>; + }; + + rpmsg_reserved: rpmsg@0xbff00000 { + no-map; + reg = <0xbff00000 0x100000>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; +}; + +/* + * The flollowing modules are conflicting with M4, disable them when m4 + * is running. + */ +&adc1 { + status = "disabled"; +}; + +&adc2 { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&i2c3 { + status = "disabled"; +}; + +&ocram { + reg = <0x00901000 0xf000>; +}; + +&qspi2 { + status = "disabled"; +}; + +&qspi_m4 { + status = "okay"; +}; + +&rpmsg{ + vdev-nums = <1>; + reg = <0xbfff0000 0x10000>; + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&clks { + fsl,shared-clks-number = <0x23>; + fsl,shared-clks-index = ; + fsl,shared-mem-addr = <0x91F000>; + fsl,shared-mem-size = <0x1000>; +}; diff --git a/arch/arm/boot/dts/imx6sx-sdb-mqs.dts b/arch/arm/boot/dts/imx6sx-sdb-mqs.dts new file mode 100644 index 00000000000000..3aae33f7f1446e --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-sdb-mqs.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2014 Freescale Semiconductor, Inc. + +#include "imx6sx-sdb.dts" +/ { + + sound { + status = "disabled"; + }; + + sound-mqs { + compatible = "fsl,imx6sx-sdb-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + cpu-dai = <&sai1>; + asrc-controller = <&asrc>; + audio-codec = <&mqs>; + }; +}; + +&usdhc2 { + /* pin conflict with mqs*/ + status = "disabled"; +}; + +&mqs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs>; + clocks = <&clks IMX6SX_CLK_SAI1>; + clock-names = "mclk"; + status = "okay"; +}; + +&sai1 { + pinctrl-0 = <>; + status = "okay"; +}; + +&ssi2 { + status = "disabled"; +}; + +&sdma { + gpr = <&gpr>; + /* SDMA event remap for SAI1 */ + fsl,sdma-event-remap = <0 15 1>, <0 16 1>; +}; diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva-ldo.dts b/arch/arm/boot/dts/imx6sx-sdb-reva-ldo.dts new file mode 100644 index 00000000000000..86719991523650 --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-sdb-reva-ldo.dts @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-sdb-reva.dts" + +&gpc { + fsl,ldo-bypass = <0>; /* use ldo-enable, u-boot will check it and configure */ +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index 5a63ca6157229c..6a1dba0fb699d3 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -103,6 +103,23 @@ }; }; +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; + + fsl,arm-soc-shared = <1>; +}; + &qspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi2>; @@ -131,10 +148,12 @@ ®_arm { vin-supply = <&sw1a_reg>; + regulator-allow-bypass; }; ®_soc { vin-supply = <&sw1a_reg>; + regulator-allow-bypass; }; ®_vdd1p1 { diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi index 865528b134d808..fbae20d2a2c041 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dtsi +++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi @@ -28,6 +28,14 @@ default-brightness-level = <6>; }; + backlight2 { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + fb-names = "mxs-lcdif1"; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -56,6 +64,7 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; enable-active-high; }; @@ -93,6 +102,7 @@ regulator-name = "lcd-3v3"; gpio = <&gpio3 27 0>; enable-active-high; + status = "disabled"; }; reg_peri_3v3: regulator-peri-3v3 { @@ -151,10 +161,22 @@ regulator-max-microvolt = <3300000>; }; + reg_vref_3v3: regulator-adc-verf { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + pxp_v4l2_out { + compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + sound { compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962"; model = "wm8962-audio"; - ssi-controller = <&ssi2>; + audio-cpu = <&ssi2>; audio-codec = <&codec>; audio-routing = "Headphone Jack", "HPOUTL", @@ -165,28 +187,78 @@ "IN3R", "AMIC"; mux-int-port = <2>; mux-ext-port = <6>; + codec-master; + hp-det-gpios = <&gpio1 17 1>; }; - panel { - compatible = "sii,43wvf1g"; - backlight = <&backlight_display>; - dvdd-supply = <®_lcd_3v3>; - avdd-supply = <®_lcd_5v>; + sound-spdif { + compatible = "fsl,imx-audio-spdif", + "fsl,imx6sx-sdb-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-out; + }; - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; + sii902x_reset: sii902x-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio3 27 1>; + reset-delay-us = <100000>; + #reset-cells = <0>; + status = "disabled"; }; }; +&adc1 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + &audmux { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; status = "okay"; }; +&csi1 { + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&csi2 { + status = "okay"; + port { + csi2_ep: endpoint { + remote-endpoint = <&vadc_ep>; + }; + }; +}; + +&gpc { + fsl,ldo-bypass = <1>; +}; + +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-lcdif1"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds"; + status = "okay"; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; @@ -202,10 +274,12 @@ ethphy1: ethernet-phy@1 { reg = <1>; + at803x,eee-disabled; }; ethphy2: ethernet-phy@2 { reg = <2>; + at803x,eee-disabled; }; }; }; @@ -232,11 +306,99 @@ status = "okay"; }; +&gpc { + fsl,ldo-bypass = <1>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_0>; + clocks = <&clks IMX6SX_CLK_CSI>; + clock-names = "csi_mclk"; + AVDD-supply = <&vgen3_reg>; /* 2.8v */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio3 28 1>; + rst-gpios = <&gpio3 27 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; + + sii902x@39 { + compatible = "SiI,sii902x"; + interrupt-parent = <&gpio4>; + interrupts = <21 2>; + mode_str ="1280x720M@60"; + bits-per-pixel = <16>; + resets = <&sii902x_reset>; + reg = <0x39>; + status = "disabled"; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + egalax_ts@4 { + compatible = "eeti,egalax_ts"; + reg = <0x4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_egalax_int>; + interrupt-parent = <&gpio4>; + interrupts = <19 2>; + wakeup-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; + }; +}; + + &i2c3 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; + + isl29023@44 { + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&gpio6>; + interrupts = <5 1>; + shared-interrupt; + }; + + mag3110@e { + compatible = "fsl,mag3110"; + reg = <0xe>; + position = <2>; + interrupt-parent = <&gpio6>; + interrupts = <5 1>; + shared-interrupt; + }; + + mma8451@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + position = <1>; + interrupt-parent = <&gpio6>; + interrupts = <2 8>; + interrupt-route = <2>; + }; }; &i2c4 { @@ -271,11 +433,65 @@ &lcdif1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcd>; + lcd-supply = <®_lcd_3v3>; + display = <&display0>; + status = "disabled"; + + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&lcdif2 { + display = <&display1>; + disp-dev = "ldb"; status = "okay"; + display1: display@1 { + bits-per-pixel = <16>; + bus-width = <18>; + }; +}; - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; +&ldb { + status = "okay"; + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + crtc = "lcdif2"; + status = "okay"; + display-timings { + native-mode = <&timing1>; + timing1: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; }; }; }; @@ -286,6 +502,16 @@ status = "okay"; }; +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + &snvs_poweroff { status = "okay"; }; @@ -296,7 +522,20 @@ status = "disabled"; }; +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + status = "okay"; +}; + &ssi2 { + assigned-clocks = <&clks IMX6SX_CLK_PLL4>, + <&clks IMX6SX_PLL4_BYPASS>, + <&clks IMX6SX_CLK_SSI2_SEL>; + assigned-clock-parents = <&clks IMX6SX_CLK_OSC>, + <&clks IMX6SX_CLK_PLL4>, + <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <737280000>, <0>, <0>; status = "okay"; }; @@ -311,6 +550,9 @@ pinctrl-0 = <&pinctrl_uart5>; uart-has-rtscts; status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode;*/ + /* pinctrl-0 = <&pinctrl_uart5dte_1>; */ }; &usbotg1 { @@ -374,6 +616,24 @@ &iomuxc { imx6x-sdb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog &pinctrl_can_gpios>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x17059 + MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0xb000 + MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059 + >; + }; + + pinctrl_can_gpios: can-gpios { + fsl,pins = < + MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059 + MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059 + >; + }; + pinctrl_audmux: audmuxgrp { fsl,pins = < MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0 @@ -384,11 +644,38 @@ >; }; + pinctrl_csi_0: csigrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0 + MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0 + MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0 + MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0 + MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0 + MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0 + MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0 + MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0 + MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0 + MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0 + MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000 + MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000 + >; + }; + + pinctrl_egalax_int: egalax_intgrp { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x80000000 + >; + }; + pinctrl_enet1: enet1grp { fsl,pins = < MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 - MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 @@ -457,6 +744,13 @@ >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 @@ -529,6 +823,12 @@ >; }; + pinctrl_pwm4: pwm4grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0 + >; + }; + pinctrl_qspi2: qspi2grp { fsl,pins = < MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1 @@ -552,6 +852,13 @@ >; }; + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0 + MX6SX_PAD_SD2_CMD__MQS_LEFT 0x120b0 + >; + }; + pinctrl_sai1: sai1grp { fsl,pins = < MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0 @@ -562,6 +869,12 @@ >; }; + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 @@ -578,6 +891,15 @@ >; }; + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 + >; + }; + pinctrl_usb_otg1: usbotg1grp { fsl,pins = < MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 @@ -667,6 +989,51 @@ >; }; + pinctrl_usdhc4_1: usdhc4grp-1 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 + >; + }; + + pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 @@ -674,3 +1041,14 @@ }; }; }; + +&vadc { + vadc_in = <0>; + csi_id = <1>; + status = "okay"; + port { + vadc_ep: endpoint { + remote-endpoint = <&csi2_ep>; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 531a52c1e987e5..26912390f88225 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -82,14 +82,32 @@ <&clks IMX6SX_CLK_PLL2_PFD2>, <&clks IMX6SX_CLK_STEP>, <&clks IMX6SX_CLK_PLL1_SW>, - <&clks IMX6SX_CLK_PLL1_SYS>; + <&clks IMX6SX_CLK_PLL1_SYS>, + <&clks IMX6SX_CLK_PLL1>, + <&clks IMX6SX_PLL1_BYPASS>, + <&clks IMX6SX_PLL1_BYPASS_SRC>; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1", + "pll1_bypass", "pll1_bypass_src"; arm-supply = <®_arm>; soc-supply = <®_soc>; }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + ckil: clock-ckil { compatible = "fixed-clock"; #clock-cells = <0>; @@ -160,18 +178,61 @@ interrupt-parent = <&gpc>; ranges; - ocram_s: sram@8f8000 { - compatible = "mmio-sram"; - reg = <0x008f8000 0x4000>; + busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6SX_CLK_PLL2_BUS>, <&clks IMX6SX_CLK_PLL2_PFD2>, + <&clks IMX6SX_CLK_PLL2_198M>, <&clks IMX6SX_CLK_ARM>, + <&clks IMX6SX_CLK_PLL3_USB_OTG>, <&clks IMX6SX_CLK_PERIPH>, + <&clks IMX6SX_CLK_PERIPH_PRE>, <&clks IMX6SX_CLK_PERIPH_CLK2>, + <&clks IMX6SX_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SX_CLK_OSC>, + <&clks IMX6SX_CLK_PLL1_SYS>, <&clks IMX6SX_CLK_PERIPH2>, + <&clks IMX6SX_CLK_AHB>, <&clks IMX6SX_CLK_OCRAM_PODF>, + <&clks IMX6SX_CLK_PLL1_SW>, <&clks IMX6SX_CLK_PERIPH2_PRE>, + <&clks IMX6SX_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SX_CLK_PERIPH2_CLK2>, + <&clks IMX6SX_CLK_STEP>, <&clks IMX6SX_CLK_MMDC_PODF>, + <&clks IMX6SX_CLK_M4>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", + "pll3_usb_otg", "periph", "periph_pre", "periph_clk2", + "periph_clk2_sel", "osc", "pll1_sys", "periph2", + "ahb", "ocram", "pll1_sw", "periph2_pre", + "periph2_clk2_sel", "periph2_clk2", "step", "mmdc", + "m4"; + fsl,max_ddr_freq = <400000000>; + }; + + ocrams: sram@8f8000 { + compatible = "fsl,lpm-sram"; + reg = <0x8f8000 0x4000>; clocks = <&clks IMX6SX_CLK_OCRAM_S>; }; - ocram: sram@900000 { + ocrams_ddr: sram@900000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x900000 0x1000>; + clocks = <&clks IMX6SX_CLK_OCRAM>; + }; + + ocram: sram@901000 { compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; + reg = <0x901000 0x1F000>; clocks = <&clks IMX6SX_CLK_OCRAM>; }; + ocram_mf: sram-mf@900000 { + compatible = "fsl,mega-fast-sram"; + reg = <0x900000 0x20000>; + clocks = <&clks IMX6SX_CLK_OCRAM>; + }; + + ocram_optee { + compatible = "fsl,optee-lpm-sram"; + reg = <0x8f8000 0x4000>; + overw_reg = <&ocrams_ddr 0x904000 0x1000>, + <&ocram 0x905000 0x1b000>, + <&ocrams 0x900000 0x4000>; + overw_clock = <&ocrams &clks IMX6SX_CLK_OCRAM>; + }; + intc: interrupt-controller@a01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -200,6 +261,23 @@ <&clks IMX6SX_CLK_GPU>; clock-names = "bus", "core", "shader"; power-domains = <&pd_pu>; + status = "disabled"; + }; + + gpu3d: gpu3d@1800000 { + compatible = "fsl,imx6sx-gpu", "fsl,imx6q-gpu"; + reg = <0x1800000 0x4000>, <0x80000000 0x0>, + <0x0 0x8000000>; + reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem"; + interrupts = ; + interrupt-names = "irq_3d"; + clocks = <&clks IMX6SX_CLK_GPU_AXI_PODF>, <&clks IMX6SX_CLK_GPU>, + <&clks 0>; + clock-names = "gpu3d_axi_clk", "gpu3d_clk", + "gpu3d_shader_clk"; + resets = <&src 0>; + reset-names = "gpu3d"; + power-domains = <&pd_pu>; }; dma_apbh: dma-apbh@1804000 { @@ -215,6 +293,11 @@ clocks = <&clks IMX6SX_CLK_APBH_DMA>; }; + caam_sm: caam-sm@100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + gpmi: gpmi-nand@1806000{ compatible = "fsl,imx6sx-gpmi-nand"; #address-cells = <1>; @@ -333,6 +416,7 @@ }; esai: esai@2024000 { + compatible = "fsl,imx35-esai"; reg = <0x02024000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_ESAI_IPG>, @@ -342,6 +426,9 @@ <&clks IMX6SX_CLK_SPBA>; clock-names = "core", "mem", "extal", "fsys", "spba"; + dmas = <&sdma 23 21 0>, + <&sdma 24 21 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -388,18 +475,27 @@ }; asrc: asrc@2034000 { + compatible = "fsl,imx53-asrc"; reg = <0x02034000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_ASRC_MEM>, - <&clks IMX6SX_CLK_ASRC_IPG>, - <&clks IMX6SX_CLK_SPDIF>, - <&clks IMX6SX_CLK_SPBA>; - clock-names = "mem", "ipg", "asrck", "spba"; - dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, - <&sdma 19 20 1>, <&sdma 20 20 1>, - <&sdma 21 20 1>, <&sdma 22 20 1>; + interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SX_CLK_ASRC_IPG>, + <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>, + <&clks IMX6SX_CLK_SPBA>; + clock-names = "mem", "ipg", "asrck_0", + "asrck_1", "asrck_2", "asrck_3", "asrck_4", + "asrck_5", "asrck_6", "asrck_7", "asrck_8", + "asrck_9", "asrck_a", "asrck_b", "asrck_c", + "asrck_d", "asrck_e", "asrck_f", "spba"; + dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, + <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; dma-names = "rxa", "rxb", "rxc", - "txa", "txb", "txc"; + "txa", "txb", "txc"; + fsl,asrc-rate = <48000>; + fsl,asrc-width = <16>; status = "okay"; }; }; @@ -559,6 +655,12 @@ gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>; }; + mqs: mqs { + compatible = "fsl,imx6sx-mqs"; + gpr = <&gpr>; + status = "disabled"; + }; + kpp: kpp@20b8000 { compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>; @@ -712,6 +814,20 @@ fsl,anatop = <&anatop>; }; + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@20cc000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x20cc000 0x4000>; + }; + snvs: snvs@20cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -767,6 +883,7 @@ #interrupt-cells = <3>; interrupts = ; interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x7c00000 0x3d00 0x0 0x400240>; clocks = <&clks IMX6SX_CLK_IPG>; clock-names = "ipg"; @@ -817,6 +934,30 @@ reg = <0x020e4000 0x4000>; }; + ldb: ldb@20e0014 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-ldb", "fsl,imx53-ldb"; + gpr = <&gpr>; + status = "disabled"; + clocks = <&clks IMX6SX_CLK_LDB_DI0>, + <&clks IMX6SX_CLK_LCDIF1_SEL>, + <&clks IMX6SX_CLK_LCDIF2_SEL>, + <&clks IMX6SX_CLK_LDB_DI0_DIV_3_5>, + <&clks IMX6SX_CLK_LDB_DI0_DIV_7>, + <&clks IMX6SX_CLK_LDB_DI0_DIV_SEL>; + clock-names = "ldb_di0", + "di0_sel", + "di1_sel", + "ldb_di0_div_3_5", + "ldb_di0_div_7", + "ldb_di0_div_sel"; + lvds-channel@0 { + reg = <0>; + status = "disabled"; + }; + }; + sdma: sdma@20ec000 { compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; reg = <0x020ec000 0x4000>; @@ -928,6 +1069,8 @@ "enet_clk_ref", "enet_out"; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; + stop-mode = <&gpr 0x10 3>; + fsl,wakeup_irq = <0>; status = "disabled"; }; @@ -949,6 +1092,8 @@ <&clks IMX6SX_CLK_USDHC1>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; status = "disabled"; }; @@ -961,6 +1106,8 @@ <&clks IMX6SX_CLK_USDHC2>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; status = "disabled"; }; @@ -973,6 +1120,8 @@ <&clks IMX6SX_CLK_USDHC3>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; status = "disabled"; }; @@ -985,6 +1134,8 @@ <&clks IMX6SX_CLK_USDHC4>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; status = "disabled"; }; @@ -1037,6 +1188,10 @@ <&clks IMX6SX_CLK_ENET_PTP>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + stop-mode = <&gpr 0x10 4>; + fsl,wakeup_irq = <0>; status = "disabled"; }; @@ -1125,6 +1280,12 @@ status = "disabled"; }; + qspi_m4: qspi-m4 { + compatible = "fsl,imx6sx-qspi-m4-restore"; + reg = <0x021e4000 0x4000>; + status = "disabled"; + }; + uart2: serial@21e8000 { compatible = "fsl,imx6sx-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; @@ -1203,21 +1364,46 @@ ranges; csi1: csi@2214000 { + compatible = "fsl,imx6s-csi"; reg = <0x02214000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, <&clks IMX6SX_CLK_CSI>, <&clks IMX6SX_CLK_DCIC1>; - clock-names = "disp-axi", "csi_mclk", "dcic"; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + power-domains = <&pd_disp>; + status = "disabled"; + }; + + dcic1: dcic@220c000 { + compatible = "fsl,imx6sx-dcic"; + reg = <0x220c000 0x4000>; + interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SX_CLK_DCIC1>, + <&clks IMX6SX_CLK_DISPLAY_AXI>; + clock-names = "dcic", "disp-axi"; + gpr = <&gpr>; + status = "disabled"; + }; + + dcic2: dcic@2210000 { + compatible = "fsl,imx6sx-dcic"; + reg = <0x2210000 0x4000>; + interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SX_CLK_DCIC2>, + <&clks IMX6SX_CLK_DISPLAY_AXI>; + clock-names = "dcic", "disp-axi"; + gpr = <&gpr>; status = "disabled"; }; pxp: pxp@2218000 { - compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp"; + compatible = "fsl,imx6sx-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma"; reg = <0x02218000 0x4000>; interrupts = ; - clocks = <&clks IMX6SX_CLK_PXP_AXI>; - clock-names = "axi"; + clocks = <&clks IMX6SX_CLK_PXP_AXI>, + <&clks IMX6SX_CLK_DISPLAY_AXI>; + clock-names = "pxp-axi", "disp-axi"; power-domains = <&pd_disp>; status = "disabled"; }; @@ -1273,6 +1459,7 @@ interrupts = ; clocks = <&clks IMX6SX_CLK_IPG>; clock-names = "adc"; + num-channels = <4>; fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>; status = "disabled"; @@ -1284,6 +1471,7 @@ interrupts = ; clocks = <&clks IMX6SX_CLK_IPG>; clock-names = "adc"; + num-channels = <4>; fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>; status = "disabled"; @@ -1309,6 +1497,27 @@ status = "disabled"; }; + sema4: sema4@02290000 { /* sema4 */ + compatible = "fsl,imx6sx-sema4"; + reg = <0x02290000 0x4000>; + interrupts = <0 116 0x04>; + status = "okay"; + }; + + mu: mu@02294000 { /* mu */ + compatible = "fsl,imx6sx-mu"; + reg = <0x02294000 0x4000>; + interrupts = <0 90 0x04>; + #mbox-cells = <2>; + }; + + mu_lp: mu_lp@02294000 { /* mu */ + compatible = "fsl,imx6sx-mu-lp"; + reg = <0x02294000 0x4000>; + interrupts = <0 90 0x04>; + status = "okay"; + }; + uart6: serial@22a0000 { compatible = "fsl,imx6sx-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; @@ -1392,4 +1601,18 @@ status = "disabled"; }; }; + + rpmsg: rpmsg{ + compatible = "fsl,imx6sx-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + status = "disabled"; + }; }; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk-btwifi-oob.dts b/arch/arm/boot/dts/imx6ul-14x14-evk-btwifi-oob.dts new file mode 100644 index 00000000000000..90e0045fa2e4ee --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-14x14-evk-btwifi-oob.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-14x14-evk-btwifi.dts" +#include "imx6ul-evk-btwifi-oob.dtsi" diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk-btwifi.dts b/arch/arm/boot/dts/imx6ul-14x14-evk-btwifi.dts new file mode 100644 index 00000000000000..4613799a97c75a --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-14x14-evk-btwifi.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-14x14-evk.dts" +#include "imx6ul-evk-btwifi.dtsi" diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk-csi.dts b/arch/arm/boot/dts/imx6ul-14x14-evk-csi.dts new file mode 100644 index 00000000000000..9a1f453551d669 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-14x14-evk-csi.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015 Freescale Semiconductor, Inc. + +#include "imx6ul-14x14-evk.dts" + + +&csi { + status = "okay"; +}; + +&ov5640 { + status = "okay"; +}; + +&sim2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk-ecspi-slave.dts b/arch/arm/boot/dts/imx6ul-14x14-evk-ecspi-slave.dts new file mode 100644 index 00000000000000..16f82a32c2e2ce --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-14x14-evk-ecspi-slave.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2018 NXP + +/* + * DTS file for ECSPI Slave Certification at i.mx6ul 14x14 evk board. + * NOTE: Because Ethernet2 use the same pins with ecspi4, so disable + * fec1/fec2 for ECSPI4 test. + */ + +#include "imx6ul-14x14-evk-ecspi.dts" + +/delete-node/&spidev0; + +&ecspi4 { + #address-cells = <0>; + spi-slave; +}; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk-ecspi.dts b/arch/arm/boot/dts/imx6ul-14x14-evk-ecspi.dts new file mode 100644 index 00000000000000..7ca5e422435730 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-14x14-evk-ecspi.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2018 NXP + +/* + * DTS file for ECSPI Certification at i.mx6ul 14x14 evk board. + * NOTE: Because Ethernet2 use the same pins with ecspi4, so disable + * fec1/fec2 for ECSPI4 test. + */ + +#include "imx6ul-14x14-evk.dts" + +&iomuxc { + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x70a1 + MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x70a1 + MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x70a1 + MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x70a1 + >; + }; +}; + +&ecspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <20000000>; + }; +}; + +&fec1 { + status = "disabled"; +}; + +&fec2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk-emmc.dts b/arch/arm/boot/dts/imx6ul-14x14-evk-emmc.dts new file mode 100644 index 00000000000000..bc4e53f255659a --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-14x14-evk-emmc.dts @@ -0,0 +1,21 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + */ + +#include "imx6ul-14x14-evk.dts" + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_8bit>; + pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk-gpmi-weim.dts b/arch/arm/boot/dts/imx6ul-14x14-evk-gpmi-weim.dts new file mode 100644 index 00000000000000..b7fe014619d459 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-14x14-evk-gpmi-weim.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015 Freescale Semiconductor, Inc. + +#include "imx6ul-14x14-evk.dts" + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +&iomuxc { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; +}; + +&qspi { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi index aa86341adaaa43..9c8e1c9383406b 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi @@ -12,6 +12,19 @@ reg = <0x80000000 0x20000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0xa000000>; + linux,cma-default; + }; + }; + backlight_display: backlight-display { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; @@ -20,6 +33,10 @@ status = "okay"; }; + pxp_v4l2 { + compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; reg_sd1_vmmc: regulator-sd1-vmmc { compatible = "regulator-fixed"; @@ -27,6 +44,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; enable-active-high; }; @@ -61,22 +79,63 @@ "LINPUT3", "Mic Jack", "RINPUT1", "Mic Jack", "RINPUT2", "Mic Jack"; + status = "disabled"; simple-audio-card,cpu { sound-dai = <&sai2>; + status = "disabled"; }; dailink_master: simple-audio-card,codec { sound-dai = <&codec>; clocks = <&clks IMX6UL_CLK_SAI2>; + status = "disabled"; }; }; + sound-wm8960 { + compatible = "fsl,imx6ul-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai2>; + audio-codec = <&codec>; + asrc-controller = <&asrc>; + codec-master; + gpr = <&gpr 4 0x100000 0x100000>; + /* + * hp-det = ; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <3 0>; + hp-det-gpios = <&gpio5 4 0>; + mic-det-gpios = <&gpio5 4 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Main MIC", + "RINPUT2", "Main MIC", + "Mic Jack", "MICB", + "Main MIC", "MICB", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + }; + spi4 { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi4>; status = "okay"; + pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; gpio-sck = <&gpio5 11 0>; gpio-mosi = <&gpio5 10 0>; cs-gpios = <&gpio5 7 0>; @@ -90,20 +149,10 @@ #gpio-cells = <2>; reg = <0>; registers-number = <1>; + registers-default = /bits/ 8 <0x57>; spi-max-frequency = <100000>; }; }; - - panel { - compatible = "innolux,at043tn24"; - backlight = <&backlight_display>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; }; &clks { @@ -111,6 +160,16 @@ assigned-clock-rates = <786432000>; }; +&csi { + status = "disabled"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + &i2c2 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -122,6 +181,28 @@ compatible = "wlf,wm8960"; reg = <0x1a>; wlf,shared-lrclk; + clocks = <&clks IMX6UL_CLK_SAI2>; + clock-names = "mclk"; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clks IMX6UL_CLK_CSI>; + clock-names = "csi_mclk"; + pwn-gpios = <&gpio_spi 6 1>; + rst-gpios = <&gpio_spi 5 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "disabled"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; }; }; @@ -183,6 +264,15 @@ mag3110@e { compatible = "fsl,mag3110"; reg = <0x0e>; + position = <2>; + }; + + fxls8471@1e { + compatible = "fsl,fxls8471"; + reg = <0x1e>; + position = <0>; + interrupt-parent = <&gpio5>; + interrupts = <0 8>; }; }; @@ -192,11 +282,31 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; + display = <&display0>; status = "okay"; - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; }; }; }; @@ -207,6 +317,10 @@ status = "okay"; }; +&pxp { + status = "okay"; +}; + &qspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi>; @@ -242,6 +356,22 @@ status = "okay"; }; +&sim2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sim2>; + assigned-clocks = <&clks IMX6UL_CLK_SIM_SEL>; + assigned-clock-parents = <&clks IMX6UL_CLK_SIM_PODF>; + assigned-clock-rates = <240000000>; + /* GPIO_ACTIVE_HIGH/LOW:sim card voltage control + * NCN8025:Vcc = ACTIVE_HIGH?5V:3V + * TDA8035:Vcc = ACTIVE_HIGH?5V:1.8V + */ + pinctrl-assert-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; + port = <1>; + sven_low_active; + status = "okay"; +}; + &tsc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tsc>; @@ -261,11 +391,16 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart2dte>; */ status = "okay"; }; &usbotg1 { dr_mode = "otg"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; status = "okay"; }; @@ -298,7 +433,7 @@ &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; - no-1-8-v; + non-removable; keep-power-in-suspend; wakeup-source; status = "okay"; @@ -499,10 +634,25 @@ >; }; + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 @@ -547,6 +697,51 @@ >; }; + pinctrl_usdhc2_8bit: usdhc2grp_8bit { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 diff --git a/arch/arm/boot/dts/imx6ul-9x9-evk-btwifi-oob.dts b/arch/arm/boot/dts/imx6ul-9x9-evk-btwifi-oob.dts new file mode 100644 index 00000000000000..8a8ece34d775d2 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-9x9-evk-btwifi-oob.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-9x9-evk-btwifi.dts" +#include "imx6ul-evk-btwifi-oob.dtsi" diff --git a/arch/arm/boot/dts/imx6ul-9x9-evk-btwifi.dts b/arch/arm/boot/dts/imx6ul-9x9-evk-btwifi.dts new file mode 100644 index 00000000000000..de89052d97fc5b --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-9x9-evk-btwifi.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-9x9-evk.dts" +#include "imx6ul-evk-btwifi.dtsi" diff --git a/arch/arm/boot/dts/imx6ul-9x9-evk-ldo.dts b/arch/arm/boot/dts/imx6ul-9x9-evk-ldo.dts new file mode 100644 index 00000000000000..715efcb9512eaf --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-9x9-evk-ldo.dts @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-9x9-evk.dts" + +&cpu0 { + operating-points = < + /* kHz uV */ + 696000 1275000 + 528000 1175000 + 396000 1025000 + 198000 950000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 696000 1275000 + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <0>; +}; + +&gpc { + fsl,ldo-bypass = <0>; /* use ldo-enable, u-boot will check it and configure */ +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff --git a/arch/arm/boot/dts/imx6ul-9x9-evk.dts b/arch/arm/boot/dts/imx6ul-9x9-evk.dts new file mode 100644 index 00000000000000..4350a2f4b25757 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-9x9-evk.dts @@ -0,0 +1,813 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx6ul.dtsi" + +/ { + model = "Freescale i.MX6 UltraLite 9x9 EVK Board"; + compatible = "fsl,imx6ul-9x9-evk", "fsl,imx6ul"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x10000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0xa000000>; + linux,cma-default; + }; + }; + + pxp_v4l2 { + compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_can_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; + }; + + reg_gpio_dvfs: regulator-gpio { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvfs>; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + states = <1300000 0x1 1400000 0x0>; + }; + + reg_sd1_vmmc: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx6ul-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai2>; + audio-codec = <&codec>; + asrc-controller = <&asrc>; + codec-master; + gpr = <&gpr 4 0x100000 0x100000>; + /* + * hp-det = ; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <3 0>; + hp-det-gpios = <&gpio5 4 0>; + mic-det-gpios = <&gpio5 4 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Main MIC", + "RINPUT2", "Main MIC", + "Mic Jack", "MICB", + "Main MIC", "MICB", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + }; + + spi4 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi4>; + pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + status = "okay"; + gpio-sck = <&gpio5 11 0>; + gpio-mosi = <&gpio5 10 0>; + cs-gpios = <&gpio5 7 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_spi: gpio_spi@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + registers-default = /bits/ 8 <0x57>; + spi-max-frequency = <100000>; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&cpu0 { + /* + * on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN, + * to align with other platform and use the same cpufreq + * driver, still use the seperated OPP define for arm + * and soc. + */ + operating-points = < + /* kHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <1>; +}; + +®_arm { + vin-supply = <&sw1c_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1c_reg>; + regulator-allow-bypass; +}; + +&csi { + status = "disabled"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0xf>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <1>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze3000@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + mag3110@e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + }; + + fxls8471@1e { + compatible = "fsl,fxls8471"; + reg = <0x1e>; + position = <0>; + interrupt-parent = <&gpio5>; + interrupts = <0 8>; + }; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clks IMX6UL_CLK_SAI2>; + clock-names = "mclk"; + wlf,shared-lrclk; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clks IMX6UL_CLK_CSI>; + clock-names = "csi_mclk"; + pwn-gpios = <&gpio_spi 6 1>; + rst-gpios = <&gpio_spi 5 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "disabled"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + imx6ul-evk { + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 + MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 + MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 + MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 + MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 + MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 + MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 + MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 + MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 + MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 + MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 + MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 + >; + }; + + pinctrl_dvfs: dvfsgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + /* used for lcd reset */ + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 + >; + }; + + pinctrl_sim2_1: sim2grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 + MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 + MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 + MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 + MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 + >; + }; + + pinctrl_spi4: spi4grp { + fsl,pins = < + MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 + MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <12288000>; + + status = "okay"; +}; + +&sim2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sim2_1>; + assigned-clocks = <&clks IMX6UL_CLK_SIM_SEL>; + assigned-clock-parents = <&clks IMX6UL_CLK_SIM_PODF>; + assigned-clock-rates = <240000000>; + pinctrl-assert-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; + port = <1>; + sven_low_active; + status = "okay"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure_delay_time = <0xffff>; + pre_charge_time = <0xfff>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart2dte>; */ + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; diff --git a/arch/arm/boot/dts/imx6ul-evk-btwifi-oob.dtsi b/arch/arm/boot/dts/imx6ul-evk-btwifi-oob.dtsi new file mode 100644 index 00000000000000..e1f16574a24e08 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-evk-btwifi-oob.dtsi @@ -0,0 +1,30 @@ +/* + * Copyright 2017-2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&pinctrl_wifi { + fsl,pins = < + /* MUXing for WL_HOST_WAKE */ + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0b001 /* input: 100K Pull-up */ + >; +}; + +/* + * For WL_HOST_WAKE (OOB_IRQ) to function correctly, we must disable + * the secondary ethernet port (FEC2). Hardware re-work is to remove + * R1633 and populate R1704 with 0 Ohm resistor. + * Refer to Murata Hardware Reference Manual for more details. + */ +&fec2 { + status = "disabled"; +}; + +&brcmf { + interrupt-parent = <&gpio2>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; /* M.2 WL_HOST_WAKE is active low */ + interrupt-names = "host-wake"; +}; diff --git a/arch/arm/boot/dts/imx6ul-evk-btwifi.dtsi b/arch/arm/boot/dts/imx6ul-evk-btwifi.dtsi new file mode 100644 index 00000000000000..b3dfefec7fae94 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-evk-btwifi.dtsi @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * NOTE: This DTS file is written for plugging in Murata Wi-Fi/BT EVK into Slot + * SD1 and using Murata i.MX InterConnect Ver 2.0 Adapter. Bluetooth UART & + * control signals are connected via ribbon cable (J1701 connector). + */ + +/ { + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio_spi 4 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + + usdhc1_pwrseq: usdhc1_pwrseq { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + }; +}; + +&iomuxc { + pinctrl_wifi: wifigrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x03029 + >; + }; +}; + +®_sd1_vmmc { + regulator-always-on; +}; + +&uart2 { + resets = <&modem_reset>; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + no-1-8-v; + non-removable; + pm-ignore-notify; + mmc-pwrseq = <&usdhc1_pwrseq>; + cap-power-off-card; + /delete-property/ wakeup-source; + /delete-property/ enable-sdio-wakeup; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&gpio_spi { + /* Murata: modify default setting so that BT_nPWD/BT_REG_ON + * is low (0V) during kernel boot. + */ + registers-default = /bits/ 8 <0x47>; +}; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts b/arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts index 4e99e6c79a68b8..5a3e06d6219b4a 100644 --- a/arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts +++ b/arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts @@ -8,409 +8,10 @@ /dts-v1/; #include "imx6ul-kontron-n6310-som.dtsi" +#include "imx6ul-kontron-n6x1x-s.dtsi" / { model = "Kontron N6310 S"; compatible = "kontron,imx6ul-n6310-s", "kontron,imx6ul-n6310-som", "fsl,imx6ul"; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led1 { - label = "debug-led1"; - gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - - led2 { - label = "debug-led2"; - gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led3 { - label = "debug-led3"; - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - pwm-beeper { - compatible = "pwm-beeper"; - pwms = <&pwm8 0 5000>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vref_adc: regulator-vref-adc { - compatible = "regulator-fixed"; - regulator-name = "vref-adc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&adc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc1>; - num-channels = <3>; - vref-supply = <®_vref_adc>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - eeprom@0 { - compatible = "anvo,anv32e61w", "atmel,at25"; - reg = <0>; - spi-max-frequency = <20000000>; - spi-cpha; - spi-cpol; - pagesize = <1>; - size = <8192>; - address-width = <16>; - }; -}; - -&fec1 { - pinctrl-0 = <&pinctrl_enet1>; - /delete-node/ mdio; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>; - phy-mode = "rmii"; - phy-handle = <ðphy2>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - micrel,led-mode = <0>; - clocks = <&clks IMX6UL_CLK_ENET_REF>; - clock-names = "rmii-ref"; - }; - - ethphy2: ethernet-phy@2 { - reg = <2>; - micrel,led-mode = <0>; - clocks = <&clks IMX6UL_CLK_ENET2_REF>; - clock-names = "rmii-ref"; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - rtc@32 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; -}; - -&pwm8 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm8>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - linux,rs485-enabled-at-boot-time; - rs485-rx-during-tx; - rs485-rts-active-low; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - fsl,uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - dr_mode = "otg"; - srp-disable; - hnp-disable; - adp-disable; - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_3v3>; - voltage-ranges = <3300 3300>; - no-1-8-v; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - non-removable; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_3v3>; - voltage-ranges = <3300 3300>; - no-1-8-v; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>; - - pinctrl_adc1: adc1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 - MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0 - >; - }; - - /* FRAM */ - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1 - MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1 - MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1 - MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */ - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009 - >; - }; - - pinctrl_enet2_mdio: enet2mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp{ - fsl,pins = < - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */ - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */ - MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */ - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */ - MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */ - MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0 - MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0 - >; - }; - - pinctrl_pwm8: pwm8grp { - fsl,pins = < - MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1 - MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1 - MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1 - /* - * mux unused RTS to make sure it doesn't cause - * any interrupts when it is undefined - */ - MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 - MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 - MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 - MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 - MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usbotg1: usbotg1 { - fsl,pins = < - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0 - >; - }; }; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi index a896b2348dd2fd..47d3ce5d255fa9 100644 --- a/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi +++ b/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi @@ -6,7 +6,7 @@ */ #include "imx6ul.dtsi" -#include +#include "imx6ul-kontron-n6x1x-som-common.dtsi" / { model = "Kontron N6310 SOM"; @@ -18,49 +18,7 @@ }; }; -&ecspi2 { - cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; - - spi-flash@0 { - compatible = "mxicy,mx25v8035f", "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - micrel,led-mode = <0>; - clocks = <&clks IMX6UL_CLK_ENET_REF>; - clock-names = "rmii-ref"; - }; - }; -}; - -&fec2 { - phy-mode = "rmii"; - status = "disabled"; -}; - &qspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; - spi-flash@0 { #address-cells = <1>; #size-cells = <1>; @@ -81,54 +39,3 @@ }; }; }; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reset_out>; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1 - MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1 - MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1 - MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009 - >; - }; - - pinctrl_enet1_mdio: enet1mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - >; - }; - - pinctrl_qspi: qspigrp { - fsl,pins = < - MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 - MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 - MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 - MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 - MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 - MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 - >; - }; - - pinctrl_reset_out: rstoutgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6311-s.dts b/arch/arm/boot/dts/imx6ul-kontron-n6311-s.dts new file mode 100644 index 00000000000000..239a1af3aeaaad --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-kontron-n6311-s.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + */ + +/dts-v1/; + +#include "imx6ul-kontron-n6311-som.dtsi" +#include "imx6ul-kontron-n6x1x-s.dtsi" + +/ { + model = "Kontron N6311 S"; + compatible = "kontron,imx6ul-n6311-s", "kontron,imx6ul-n6311-som", + "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6311-som.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6311-som.dtsi new file mode 100644 index 00000000000000..a095a7654ac65e --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-kontron-n6311-som.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + */ + +#include "imx6ul.dtsi" +#include "imx6ul-kontron-n6x1x-som-common.dtsi" + +/ { + model = "Kontron N6311 SOM"; + compatible = "kontron,imx6ul-n6311-som", "fsl,imx6ul"; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + device_type = "memory"; + }; +}; + +&qspi { + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + spi-max-frequency = <104000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + reg = <0>; + + partition@0 { + label = "ubi1"; + reg = <0x00000000 0x08000000>; + }; + + partition@8000000 { + label = "ubi2"; + reg = <0x08000000 0x18000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi new file mode 100644 index 00000000000000..f05e9184120274 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi @@ -0,0 +1,418 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + * Copyright (c) 2019 Krzysztof Kozlowski + */ + +#include + +/ { + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led1 { + label = "debug-led1"; + gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + + led2 { + label = "debug-led2"; + gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led3 { + label = "debug-led3"; + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + pwm-beeper { + compatible = "pwm-beeper"; + pwms = <&pwm8 0 5000>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_adc: regulator-vref-adc { + compatible = "regulator-fixed"; + regulator-name = "vref-adc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; + num-channels = <3>; + vref-supply = <®_vref_adc>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + eeprom@0 { + compatible = "anvo,anv32e61w", "atmel,at25"; + reg = <0>; + spi-max-frequency = <20000000>; + spi-cpha; + spi-cpol; + pagesize = <1>; + size = <8192>; + address-width = <16>; + }; +}; + +&fec1 { + pinctrl-0 = <&pinctrl_enet1>; + /delete-node/ mdio; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + micrel,led-mode = <0>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + + ethphy2: ethernet-phy@2 { + reg = <2>; + micrel,led-mode = <0>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; +}; + +&pwm8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm8>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + rs485-rx-during-tx; + rs485-rts-active-low; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + over-current-active-low; + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_3v3>; + voltage-ranges = <3300 3300>; + no-1-8-v; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + non-removable; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_3v3>; + voltage-ranges = <3300 3300>; + no-1-8-v; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>; + + pinctrl_adc1: adc1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1 + MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1 + MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1 + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */ + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009 + >; + }; + + pinctrl_enet2_mdio: enet2mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */ + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */ + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */ + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */ + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */ + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0 + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0 + >; + }; + + pinctrl_pwm8: pwm8grp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1 + /* + * mux unused RTS to make sure it doesn't cause + * any interrupts when it is undefined + */ + MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi new file mode 100644 index 00000000000000..a17af4d9bfdf91 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + * Copyright (c) 2019 Krzysztof Kozlowski + */ + +#include + +/ { + chosen { + stdout-path = &uart4; + }; +}; + +&ecspi2 { + cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; + + spi-flash@0 { + compatible = "mxicy,mx25v8035f", "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + micrel,led-mode = <0>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&fec2 { + phy-mode = "rmii"; + status = "disabled"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_out>; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1 + MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1 + MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1 + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009 + >; + }; + + pinctrl_enet1_mdio: enet1mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; + + pinctrl_reset_out: rstoutgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index f008036e929482..3a9985cb0dd924 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -82,10 +82,15 @@ <&clks IMX6UL_CA7_SECONDARY_SEL>, <&clks IMX6UL_CLK_STEP>, <&clks IMX6UL_CLK_PLL1_SW>, - <&clks IMX6UL_CLK_PLL1_SYS>; + <&clks IMX6UL_CLK_PLL1_SYS>, + <&clks IMX6UL_PLL1_BYPASS>, + <&clks IMX6UL_CLK_PLL1>, + <&clks IMX6UL_PLL1_BYPASS_SRC>, + <&clks IMX6UL_CLK_OSC>; clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", "secondary_sel", "step", "pll1_sw", - "pll1_sys"; + "pll1_sys", "pll1_bypass", "pll1", + "pll1_bypass_src", "osc"; arm-supply = <®_arm>; soc-supply = <®_soc>; nvmem-cells = <&cpu_speed_grade>; @@ -154,9 +159,43 @@ interrupt-parent = <&gpc>; ranges; - ocram: sram@900000 { + busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6UL_CLK_PLL2_PFD2>, <&clks IMX6UL_CLK_PLL2_198M>, + <&clks IMX6UL_CLK_PLL2_BUS>, <&clks IMX6UL_CLK_ARM>, + <&clks IMX6UL_CLK_PLL3_USB_OTG>, <&clks IMX6UL_CLK_PERIPH>, + <&clks IMX6UL_CLK_PERIPH_PRE>, <&clks IMX6UL_CLK_PERIPH_CLK2>, + <&clks IMX6UL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6UL_CLK_OSC>, + <&clks IMX6UL_CLK_AHB>, <&clks IMX6UL_CLK_AXI>, + <&clks IMX6UL_CLK_PERIPH2>, <&clks IMX6UL_CLK_PERIPH2_PRE>, + <&clks IMX6UL_CLK_PERIPH2_CLK2>, <&clks IMX6UL_CLK_PERIPH2_CLK2_SEL>, + <&clks IMX6UL_CLK_STEP>, <&clks IMX6UL_CLK_MMDC_P0_FAST>; + clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg", + "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", + "ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel", + "step", "mmdc"; + fsl,max_ddr_freq = <400000000>; + }; + + ocrams: sram@900000 { + compatible = "fsl,lpm-sram"; + reg = <0x900000 0x4000>; + }; + + ocrams_ddr: sram@904000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x904000 0x1000>; + }; + + ocram: sram@905000 { compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; + reg = <0x00905000 0x1B000>; + }; + + ocram_optee: sram@918000 { + compatible = "fsl,optee-lpm-sram"; + reg = <0x918000 0x8000>; + overw_reg = <&ocram 0x905000 0x13000>; }; intc: interrupt-controller@a01000 { @@ -184,6 +223,11 @@ clocks = <&clks IMX6UL_CLK_APBHDMA>; }; + caam_sm: caam-sm@100000 { + compatible = "fsl,imx7d-caam-sm", "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + gpmi: gpmi-nand@1806000 { compatible = "fsl,imx6q-gpmi-nand"; #address-cells = <1>; @@ -351,6 +395,31 @@ dma-names = "rx", "tx"; status = "disabled"; }; + + asrc: asrc@2034000 { + compatible = "fsl,imx53-asrc"; + reg = <0x2034000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_ASRC_IPG>, + <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>, + <&clks IMX6UL_CLK_SPBA>; + clock-names = "mem", "ipg", "asrck_0", + "asrck_1", "asrck_2", "asrck_3", "asrck_4", + "asrck_5", "asrck_6", "asrck_7", "asrck_8", + "asrck_9", "asrck_a", "asrck_b", "asrck_c", + "asrck_d", "asrck_e", "asrck_f", "spba"; + dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, + <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <48000>; + fsl,asrc-width = <16>; + status = "okay"; + }; }; tsc: tsc@2040000 { @@ -520,6 +589,9 @@ "enet_clk_ref", "enet_out"; fsl,num-tx-queues = <1>; fsl,num-rx-queues = <1>; + stop-mode = <&gpr 0x10 4>; + fsl,magic-packet; + fsl,wakeup_irq = <0>; status = "disabled"; }; @@ -631,6 +703,20 @@ fsl,anatop = <&anatop>; }; + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@20cc000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x20cc000 0x4000>; + }; + snvs: snvs@20cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -691,6 +777,7 @@ #interrupt-cells = <3>; interrupts = ; interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00 0x0 0x1400640>; }; iomuxc: iomuxc@20e0000 { @@ -855,6 +942,16 @@ "enet_clk_ref", "enet_out"; fsl,num-tx-queues = <1>; fsl,num-rx-queues = <1>; + stop-mode = <&gpr 0x10 3>; + fsl,magic-packet; + fsl,wakeup_irq = <0>; + status = "disabled"; + }; + + sim1: sim@0218c000 { + compatible = "fsl,imx6ul-sim"; + reg = <0x0218c000 0x4000>; + interrupts = ; status = "disabled"; }; @@ -934,6 +1031,15 @@ clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>; }; + sim2: sim@021b4000 { + compatible = "fsl,imx6ul-sim"; + reg = <0x021b4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_SIM2>; + clock-names = "sim"; + status = "disabled"; + }; + weim: weim@21b8000 { #address-cells = <2>; #size-cells = <1>; @@ -966,11 +1072,13 @@ }; csi: csi@21c4000 { - compatible = "fsl,imx6ul-csi", "fsl,imx7-csi"; + compatible = "fsl,imx6ul-csi", "fsl,imx7-csi", "fsl,imx6s-csi"; reg = <0x021c4000 0x4000>; interrupts = ; - clocks = <&clks IMX6UL_CLK_CSI>; - clock-names = "mclk"; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_CSI>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; status = "disabled"; }; @@ -986,11 +1094,13 @@ }; pxp: pxp@21cc000 { - compatible = "fsl,imx6ul-pxp"; - reg = <0x021cc000 0x4000>; + compatible = "fsl,imx6ul-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma"; + reg = <0x21cc000 0x4000>; interrupts = ; - clocks = <&clks IMX6UL_CLK_PXP>; - clock-names = "axi"; + clocks = <&clks IMX6UL_CLK_PXP>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "pxp-axi", "disp-axi"; + status = "disabled"; }; qspi: spi@21e0000 { diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk-btwifi-oob.dts b/arch/arm/boot/dts/imx6ull-14x14-evk-btwifi-oob.dts new file mode 100644 index 00000000000000..85ea147de16f68 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-evk-btwifi-oob.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-evk-btwifi.dts" +#include "imx6ul-evk-btwifi-oob.dtsi" diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk-btwifi.dts b/arch/arm/boot/dts/imx6ull-14x14-evk-btwifi.dts new file mode 100644 index 00000000000000..8a0a85d2e19753 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-evk-btwifi.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-evk.dts" +#include "imx6ul-evk-btwifi.dtsi" diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk-emmc.dts b/arch/arm/boot/dts/imx6ull-14x14-evk-emmc.dts new file mode 100644 index 00000000000000..d6dc9121b7473c --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-evk-emmc.dts @@ -0,0 +1,21 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + */ + +#include "imx6ull-14x14-evk.dts" + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_8bit>; + pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk-gpmi-weim.dts b/arch/arm/boot/dts/imx6ull-14x14-evk-gpmi-weim.dts new file mode 100644 index 00000000000000..4391182e613c29 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-evk-gpmi-weim.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2016 Freescale Semiconductor, Inc. + +#include "imx6ull-14x14-evk.dts" + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +&iomuxc { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; +}; + +&qspi { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk.dts b/arch/arm/boot/dts/imx6ull-14x14-evk.dts index 74aaa8a56a3de8..bb8f91034db4de 100644 --- a/arch/arm/boot/dts/imx6ull-14x14-evk.dts +++ b/arch/arm/boot/dts/imx6ull-14x14-evk.dts @@ -8,11 +8,22 @@ #include "imx6ul-14x14-evk.dtsi" / { - model = "Freescale i.MX6 UltraLiteLite 14x14 EVK Board"; + model = "Freescale i.MX6 ULL 14x14 EVK Board"; compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; }; &clks { - assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>; - assigned-clock-rates = <320000000>; + assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>, + <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <320000000>, <786432000>; }; + +&csi { + status = "okay"; +}; + +&ov5640 { + status = "okay"; +}; + +/delete-node/ &sim2; diff --git a/arch/arm/boot/dts/imx6ull-9x9-evk-btwifi-oob.dts b/arch/arm/boot/dts/imx6ull-9x9-evk-btwifi-oob.dts new file mode 100644 index 00000000000000..8d00a908ee94aa --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-9x9-evk-btwifi-oob.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-9x9-evk-btwifi.dts" +#include "imx6ul-evk-btwifi-oob.dtsi" diff --git a/arch/arm/boot/dts/imx6ull-9x9-evk-btwifi.dts b/arch/arm/boot/dts/imx6ull-9x9-evk-btwifi.dts new file mode 100644 index 00000000000000..c8a51006213f24 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-9x9-evk-btwifi.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-9x9-evk.dts" +#include "imx6ul-evk-btwifi.dtsi" diff --git a/arch/arm/boot/dts/imx6ull-9x9-evk-ldo.dts b/arch/arm/boot/dts/imx6ull-9x9-evk-ldo.dts new file mode 100644 index 00000000000000..a878fe5bbb78c8 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-9x9-evk-ldo.dts @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2017 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-9x9-evk.dts" +&cpu0 { + operating-points = < + /* kHz uV */ + 528000 1175000 + 396000 1025000 + 198000 950000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <0>; +}; + +&gpc { + fsl,ldo-bypass = <0>; /* use ldo-enable, u-boot will check it and configure */ +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff --git a/arch/arm/boot/dts/imx6ull-9x9-evk.dts b/arch/arm/boot/dts/imx6ull-9x9-evk.dts new file mode 100644 index 00000000000000..9514086b21c814 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-9x9-evk.dts @@ -0,0 +1,813 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx6ull.dtsi" + +/ { + model = "Freescale i.MX6 ULL 9x9 EVK Board"; + compatible = "fsl,imx6ull-9x9-evk", "fsl,imx6ull"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x10000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0xa000000>; + linux,cma-default; + }; + }; + + pxp_v4l2 { + compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_can_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; + }; + + reg_gpio_dvfs: regulator-gpio { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvfs>; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + states = <1300000 0x1 1400000 0x0>; + }; + + reg_sd1_vmmc: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx6ul-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai2>; + audio-codec = <&codec>; + asrc-controller = <&asrc>; + codec-master; + gpr = <&gpr 4 0x100000 0x100000>; + /* + * hp-det = ; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <3 0>; + hp-det-gpios = <&gpio5 4 0>; + mic-det-gpios = <&gpio5 4 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Main MIC", + "RINPUT2", "Main MIC", + "Mic Jack", "MICB", + "Main MIC", "MICB", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + }; + + spi4 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi4>; + pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + status = "okay"; + gpio-sck = <&gpio5 11 0>; + gpio-mosi = <&gpio5 10 0>; + cs-gpios = <&gpio5 7 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_spi: gpio_spi@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + registers-default = /bits/ 8 <0x57>; + spi-max-frequency = <100000>; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&cpu0 { + /* + * on i.MX6ULL, no seperated VDD_ARM_IN and VDD_SOC_IN, + * to align with other platform and use the same cpufreq + * driver, still use the seperated OPP define for arm + * and soc. + */ + operating-points = < + /* kHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <1>; +}; + +®_arm { + vin-supply = <&sw1c_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1c_reg>; + regulator-allow-bypass; +}; + +&csi { + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0xf>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <1>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze3000@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + mag3110@e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + }; + + fxls8471@1e { + compatible = "fsl,fxls8471"; + reg = <0x1e>; + position = <0>; + interrupt-parent = <&gpio5>; + interrupts = <0 8>; + }; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clks IMX6UL_CLK_SAI2>; + clock-names = "mclk"; + wlf,shared-lrclk; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clks IMX6UL_CLK_CSI>; + clock-names = "csi_mclk"; + pwn-gpios = <&gpio_spi 6 1>; + rst-gpios = <&gpio_spi 5 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + imx6ul-evk { + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 + MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 + MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 + MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 + MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 + MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 + MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 + MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 + MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 + MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 + MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 + MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; + }; +}; + +&iomuxc_snvs { + pinctrl-names = "default_snvs"; + pinctrl-0 = <&pinctrl_hog_2>; + imx6ull-evk { + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 + >; + }; + + pinctrl_dvfs: dvfsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 + >; + }; + + pinctrl_lcdif_reset: lcdifresetgrp { + fsl,pins = < + /* used for lcd reset */ + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; + + pinctrl_spi4: spi4grp { + fsl,pins = < + MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 + MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 + >; + }; + + pinctrl_sai2_hp_det_b: sai2_hp_det_grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl + &pinctrl_lcdif_reset>; + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2 + &pinctrl_sai2_hp_det_b>; + + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <12288000>; + + status = "okay"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure_delay_time = <0xffff>; + pre_charge_time = <0xfff>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart2dte>; */ + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; diff --git a/arch/arm/boot/dts/imx6ull-kontron-n6411-s.dts b/arch/arm/boot/dts/imx6ull-kontron-n6411-s.dts new file mode 100644 index 00000000000000..57588a5e1e342a --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-kontron-n6411-s.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2019 Kontron Electronics GmbH + */ + +/dts-v1/; + +#include "imx6ull-kontron-n6411-som.dtsi" +#include "imx6ul-kontron-n6x1x-s.dtsi" + +/ { + model = "Kontron N6411 S"; + compatible = "kontron,imx6ull-n6411-s", "kontron,imx6ull-n6411-som", + "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-kontron-n6411-som.dtsi b/arch/arm/boot/dts/imx6ull-kontron-n6411-som.dtsi new file mode 100644 index 00000000000000..b7e984284e1ad3 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-kontron-n6411-som.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + */ + +#include "imx6ull.dtsi" +#include "imx6ul-kontron-n6x1x-som-common.dtsi" + +/ { + model = "Kontron N6411 SOM"; + compatible = "kontron,imx6ull-n6311-som", "fsl,imx6ull"; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + device_type = "memory"; + }; +}; + +&qspi { + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + spi-max-frequency = <104000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + reg = <0>; + + partition@0 { + label = "ubi1"; + reg = <0x00000000 0x08000000>; + }; + + partition@8000000 { + label = "ubi2"; + reg = <0x08000000 0x18000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi index b7e67d1213229d..f9ce39bf55be5d 100644 --- a/arch/arm/boot/dts/imx6ull.dtsi +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -13,6 +13,7 @@ &cpu0 { clock-frequency = <900000000>; + fsl,low-power-run; operating-points = < /* kHz uV */ 900000 1275000 @@ -36,21 +37,50 @@ }; &pxp { - compatible = "fsl,imx6ull-pxp"; + compatible = "fsl,imx6ull-pxp-dma", "fsl,imx7d-pxp-dma"; interrupts = , - ; + ; + clocks = <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_PXP>; + clock-names = "pxp_ipg", "pxp_axi"; + status = "disabled"; }; &usdhc1 { compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; + assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <132000000>; }; &usdhc2 { compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <132000000>; }; / { soc { + busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6UL_CLK_PLL2_PFD2>, <&clks IMX6UL_CLK_PLL2_198M>, + <&clks IMX6UL_CLK_PLL2_BUS>, <&clks IMX6UL_CLK_ARM>, + <&clks IMX6UL_CLK_PLL3_USB_OTG>, <&clks IMX6UL_CLK_PERIPH>, + <&clks IMX6UL_CLK_PERIPH_PRE>, <&clks IMX6UL_CLK_PERIPH_CLK2>, + <&clks IMX6UL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6UL_CLK_OSC>, + <&clks IMX6UL_CLK_AHB>, <&clks IMX6UL_CLK_AXI>, + <&clks IMX6UL_CLK_PERIPH2>, <&clks IMX6UL_CLK_PERIPH2_PRE>, + <&clks IMX6UL_CLK_PERIPH2_CLK2>, <&clks IMX6UL_CLK_PERIPH2_CLK2_SEL>, + <&clks IMX6UL_CLK_STEP>, <&clks IMX6UL_CLK_MMDC_P0_FAST>, <&clks IMX6UL_PLL1_BYPASS_SRC>, + <&clks IMX6UL_PLL1_BYPASS>, <&clks IMX6UL_CLK_PLL1_SYS>, <&clks IMX6UL_CLK_PLL1_SW>, + <&clks IMX6UL_CLK_PLL1>; + clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg", + "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", + "ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel", + "step", "mmdc", "pll1_bypass_src", "pll1_bypass", "pll1_sys", "pll1_sw", "pll1"; + fsl,max_ddr_freq = <400000000>; + }; + aips3: aips-bus@2200000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; @@ -68,6 +98,13 @@ clock-names = "dcp"; }; + rngb: rng@2284000 { + compatible = "fsl,imx25-rngb"; + reg = <0x02284000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_DUMMY>; + }; + iomuxc_snvs: iomuxc-snvs@2290000 { compatible = "fsl,imx6ull-iomuxc-snvs"; reg = <0x02290000 0x4000>; @@ -83,6 +120,18 @@ clock-names = "ipg", "per"; status = "disabled"; }; + + epdc: epdc@228c000 { + compatible = "fsl,imx7d-epdc"; + interrupts = ; + reg = <0x228c000 0x4000>; + clocks = <&clks IMX6ULL_CLK_EPDC_ACLK>, + <&clks IMX6ULL_CLK_EPDC_PIX>; + clock-names = "epdc_axi", "epdc_pix"; + /* Need to fix epdc-ram */ + /* epdc-ram = <&gpr 0x4 30>; */ + status = "disabled"; + }; }; }; }; diff --git a/arch/arm/boot/dts/imx6ulz-14x14-evk-btwifi.dts b/arch/arm/boot/dts/imx6ulz-14x14-evk-btwifi.dts new file mode 100644 index 00000000000000..bac48ee3ae9502 --- /dev/null +++ b/arch/arm/boot/dts/imx6ulz-14x14-evk-btwifi.dts @@ -0,0 +1,16 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx6ulz-14x14-evk.dts" +#include "imx6ul-evk-btwifi.dtsi" diff --git a/arch/arm/boot/dts/imx6ulz-14x14-evk-emmc.dts b/arch/arm/boot/dts/imx6ulz-14x14-evk-emmc.dts new file mode 100644 index 00000000000000..e477952759ea51 --- /dev/null +++ b/arch/arm/boot/dts/imx6ulz-14x14-evk-emmc.dts @@ -0,0 +1,25 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx6ulz-14x14-evk.dts" + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_8bit>; + pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ulz-14x14-evk-gpmi-weim.dts b/arch/arm/boot/dts/imx6ulz-14x14-evk-gpmi-weim.dts new file mode 100644 index 00000000000000..12635e83e3480c --- /dev/null +++ b/arch/arm/boot/dts/imx6ulz-14x14-evk-gpmi-weim.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2018 NXP + +#include "imx6ulz-14x14-evk.dts" + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +&iomuxc { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; +}; + +&qspi { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ulz-14x14-evk.dts b/arch/arm/boot/dts/imx6ulz-14x14-evk.dts index 483d9732c00231..7deda307425baf 100644 --- a/arch/arm/boot/dts/imx6ulz-14x14-evk.dts +++ b/arch/arm/boot/dts/imx6ulz-14x14-evk.dts @@ -20,3 +20,20 @@ /delete-node/ panel; }; + +&iomuxc { + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + >; + }; +}; + diff --git a/arch/arm/boot/dts/imx7d-12x12-lpddr3-val-sai.dts b/arch/arm/boot/dts/imx7d-12x12-lpddr3-val-sai.dts new file mode 100644 index 00000000000000..a256004559c4a4 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-12x12-lpddr3-val-sai.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + */ + +#include "imx7d-12x12-lpddr3-val.dts" + +/ { + sound { + compatible = "fsl,imx7d-12x12-lpddr3-arm2-wm8958", + "fsl,imx-audio-wm8958"; + model = "wm8958-audio"; + cpu-dai = <&sai1>; + audio-codec = <&codec>; + codec-master; + hp-det-gpios = <&gpio1 12 1>; + }; +}; + +&iomuxc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_headphone_det>; + pinctrl-1 = <&pinctrl_hog_1 &pinctrl_hog_sd2_vselect>; +}; + +&sai1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-1 = <&pinctrl_sai1>; + status = "okay"; +}; + +&sdma { + status = "okay"; +}; + +&sim1 { + status = "disabled"; +}; + +&usdhc2 { + no-1-8-v; +}; diff --git a/arch/arm/boot/dts/imx7d-12x12-lpddr3-val.dts b/arch/arm/boot/dts/imx7d-12x12-lpddr3-val.dts new file mode 100644 index 00000000000000..422e60865b1a14 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-12x12-lpddr3-val.dts @@ -0,0 +1,1015 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + */ + +/dts-v1/; + +#include "imx7d.dtsi" + +/ { + model = "Freescale i.MX7D LPDDR3 12x12 Validation Board"; + compatible = "fsl,imx7d-12x12-lpddr3-val", "fsl,imx7d"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_gpio_keys>; + pinctrl-1 = <&pinctrl_gpio_keys_sleep>; + + volume-up { + label = "Volume Up"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + pxp_v4l2_out { + compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_aud_1v8: aud_1v8 { + compatible = "regulator-fixed"; + regulator-name = "AUD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can1_3v3: can1-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can1-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; + + reg_can2_3v3: can2-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; + + reg_coedc_5v: coedc_5v { + compatible = "regulator-fixed"; + regulator-name = "CODEC_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd1_vmmc: sd1_vmmc{ + compatible = "regulator-fixed"; + regulator-name = "VCC_SD1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd2_vmmc: sd2_vmmc{ + compatible = "regulator-fixed"; + regulator-name = "VCC_SD2"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on { + compatible = "regulator-fixed"; + regulator-name = "mipi_dsi_pwr_on"; + gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + memory { + reg = <0x80000000 0x80000000>; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; +}; + +&epdc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_epdc_0>; + pinctrl-1 = <&pinctrl_epdc_0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "okay"; +}; + +&epxp { + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 19 0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>; + pinctrl-1 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>; + status = "disabled"; + + spi_flash1: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_enet1>; + pinctrl-1 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_enet2>; + pinctrl-1 = <&pinctrl_enet2>; + pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>; + assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "disabled"; +}; + +&flexcan1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexcan1>; + pinctrl-1 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_3v3>; + status = "disabled"; +}; + +&flexcan2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-1 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_3v3>; + status = "disabled"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_i2c1_1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + status = "okay"; + + pmic: pfuze3000@8 { + compatible = "fsl,pfuze3000"; + reg = <0x8>; + fsl,lpsr-mode; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_i2c3_1>; + pinctrl-1 = <&pinctrl_i2c3_1>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + max17135@48 { + compatible = "maxim,max17135"; + reg = <0x48>; + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio2 31 0>; + gpio_pmic_vcom_ctrl = <&gpio4 14 0>; + gpio_pmic_wakeup = <&gpio4 23 0>; + gpio_pmic_v3p3 = <&gpio4 20 0>; + gpio_pmic_intr = <&gpio4 18 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* Real max value: -500000 */ + regulator-max-microvolt = <4325000>; + /* Real min value: -4325000 */ + regulator-min-microvolt = <500000>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; + + codec: wm8958@1a { + compatible = "wlf,wm8958"; + reg = <0x1a>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "mclk1", "mclk2"; + + DBVDD1-supply = <®_aud_1v8>; + DBVDD2-supply = <®_aud_1v8>; + DBVDD3-supply = <®_aud_1v8>; + AVDD2-supply = <®_aud_1v8>; + CPVDD-supply = <®_aud_1v8>; + SPKVDD1-supply = <®_coedc_5v>; + SPKVDD2-supply = <®_coedc_5v>; + wlf,ldo1ena; + wlf,ldo2ena; + }; +}; + +&iomuxc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_sd2_vselect &pinctrl_hog_mipi>; + pinctrl-1 = <&pinctrl_hog_1 &pinctrl_hog_sd2_vselect &pinctrl_hog_mipi>; + + imx7d-12x12-lpddr3-arm2 { + + pinctrl_bt: btgrp-1 { + fsl,pins = < + MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x80000000 /* BT REG on */ + >; + }; + + pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 { + fsl,pins = < + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x2 + >; + }; + + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2 + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2 + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_epdc_0: epdcgrp-0 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x2 + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x2 + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x2 + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x2 + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x2 + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x2 + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x2 + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x2 + MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x2 + MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x2 + MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x2 + MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x2 + MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x2 + MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x2 + MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x2 + MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x2 + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x2 + MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x2 + MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x2 + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x2 + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x2 + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x2 + MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 0x2 + MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 0x2 + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x2 + MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x2 + MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x2 + MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x2 + MX7D_PAD_EPDC_BDR0__EPDC_BDR0 0x2 + MX7D_PAD_EPDC_BDR1__EPDC_BDR1 0x2 + MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x80000000 /* pwr int */ + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x59 + MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x59 + MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x59 /* STBY */ + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x59 + MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x59 + MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x59 /* STBY */ + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x32 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x32 + >; + }; + + pinctrl_gpio_keys_sleep: gpio_keysgrp_sleep { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 + >; + }; + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x80000000 + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x80000000 + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x80000000 + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x80000000 + MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x80000000 + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x80000000 + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 + MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59 + MX7D_PAD_SD2_WP__GPIO5_IO10 0x59 + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 + >; + }; + + pinctrl_hog_mipi: hoggrp_mipi { + fsl,pins = < + MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59 + MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x59 + >; + }; + + pinctrl_hog_sd2_vselect: hoggrp_sd2vselect { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__SD2_VSELECT 0x59 + >; + }; + + pinctrl_hog_headphone_det: hoggrp_headphone_det { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 + >; + }; + + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c4_1: i2c4grp-1 { + fsl,pins = < + MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f + MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT 0x0 + MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT 0x0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x2 + MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x2 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f + MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC 0x1f + MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f + MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f + MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f + MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f + MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0 + >; + }; + + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79 + >; + }; + + pinctrl_uart3dte_1: uart3dtegrp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS 0x79 + >; + }; + + pinctrl_usdhc1_1: usdhc1grp-1 { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + >; + }; + + pinctrl_usdhc2_1_100mhz: usdhc2grp-1_100mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5a + MX7D_PAD_SD2_CLK__SD2_CLK 0x1a + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a + >; + }; + + pinctrl_usdhc2_1_200mhz: usdhc2grp-1_200mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5b + MX7D_PAD_SD2_CLK__SD2_CLK 0x1b + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b + >; + }; + + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; + + pinctrl_usdhc3_1_100mhz: usdhc3grp-1_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a + >; + }; + + pinctrl_usdhc3_1_200mhz: usdhc3grp-1_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b + >; + }; + + pinctrl_sim1_1: sim1grp-1 { + fsl,pins = < + MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B 0x77 + MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD 0x77 + MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN 0x77 + MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK 0x73 + MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD 0x73 + >; + }; + + }; +}; + +&iomuxc_lpsr { + imx7d-12x12-lpddr3-arm2 { + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30 + >; + }; + }; + + imx7d-sdb { + pinctrl_usbotg1_vbus: usbotg1vbusgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 + >; + }; + + pinctrl_usbotg2_vbus: usbotg2vbusgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + pinctrl-1 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; + status = "okay"; + + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&ocrams { + fsl,enable-lpsr; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio6 21 GPIO_ACTIVE_LOW>; + power-on-gpio = <&gpio6 19 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&sim1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sim1_1>; + pinctrl-1 = <&pinctrl_sim1_1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_uart1_1>; + pinctrl-1 = <&pinctrl_uart1_1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_uart3_1 + &pinctrl_bt>; + pinctrl-1 = <&pinctrl_uart3_1 + &pinctrl_bt>; + fsl,uart-has-rtscts; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode;*/ + /* pinctrl-0 = <&pinctrl_uart3dte_1>; */ +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2_vbus>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1_1>; + pinctrl-1 = <&pinctrl_usdhc1_1>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2_1>; + pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc2_1>; + cd-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3_1>; + pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_1>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + auto-cmd23-broken; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; diff --git a/arch/arm/boot/dts/imx7d-sdb-epdc.dts b/arch/arm/boot/dts/imx7d-sdb-epdc.dts new file mode 100644 index 00000000000000..2d3df3dcd5f8b8 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-epdc.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + */ +#include "imx7d-sdb.dts" +#include "imx7d-sdb-epdc.dtsi" diff --git a/arch/arm/boot/dts/imx7d-sdb-epdc.dtsi b/arch/arm/boot/dts/imx7d-sdb-epdc.dtsi new file mode 100644 index 00000000000000..8dda20b53c5a5e --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-epdc.dtsi @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + */ + +&epdc { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&fec2 { + status = "disabled"; +}; + +®_can2_3v3 { + status = "disabled"; +}; + +®_fec2_3v3 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&max17135 { + status = "okay"; +}; + +&sii902x { + status = "disabled"; +}; + +&sim1 { + status = "disabled"; +}; + +&uart5 { + status = "disabled"; +}; + +&i2c3 { + elan@10 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc_elan_touch>; + compatible = "elan,elan-touch"; + reg = <0x10>; + interrupt-parent = <&gpio6>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + gpio_elan_cs = <&gpio6 13 0>; + gpio_elan_rst = <&gpio6 15 0>; + gpio_intr = <&gpio6 12 0>; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/imx7d-sdb-gpmi-weim.dts b/arch/arm/boot/dts/imx7d-sdb-gpmi-weim.dts new file mode 100644 index 00000000000000..346e38cca609c5 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-gpmi-weim.dts @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "imx7d-sdb.dts" +#include "imx7d-sdb-gpmi-weim.dtsi" diff --git a/arch/arm/boot/dts/imx7d-sdb-gpmi-weim.dtsi b/arch/arm/boot/dts/imx7d-sdb-gpmi-weim.dtsi new file mode 100644 index 00000000000000..a614cbf05aa8ec --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-gpmi-weim.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&gpmi{ + status = "okay"; +}; + +/* &sai1{ */ + /* status = "disabled"; */ +/* }; */ + +&usdhc3{ + status = "disabled"; +}; + +&uart5{ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx7d-sdb-m4.dts b/arch/arm/boot/dts/imx7d-sdb-m4.dts new file mode 100644 index 00000000000000..7aa803559ef59a --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-m4.dts @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "imx7d-sdb.dts" +#include "imx7d-sdb-m4.dtsi" diff --git a/arch/arm/boot/dts/imx7d-sdb-m4.dtsi b/arch/arm/boot/dts/imx7d-sdb-m4.dtsi new file mode 100644 index 00000000000000..601a236f537221 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-m4.dtsi @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + m4_reserved: m4@0x9ff00000 { + no-map; + reg = <0x9ff00000 0x100000>; + }; + + rpmsg_reserved: rpmsg@0xbff00000 { + no-map; + reg = <0xbff00000 0x100000>; + }; + }; + m4_tcm: tcml@007f8000 { + compatible = "fsl, m4_tcml"; + reg = <0x007f8000 0x8000>; + }; +}; + +&adc1 { + status = "disabled"; +}; + +&adc2 { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&i2c2 { + status = "disabled"; +}; + +&gpt3 { + status = "disabled"; +}; + +&gpt4 { + status = "disabled"; +}; + +&ocram { + reg = <0x00901000 0xf000>; +}; + +®_can2_3v3 { + status = "disabled"; +}; + +&rpmsg{ + vdev-nums = <1>; + reg = <0xbfff0000 0x10000>; + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&wdog3{ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx7d-sdb-mipi-dsi.dts b/arch/arm/boot/dts/imx7d-sdb-mipi-dsi.dts new file mode 100644 index 00000000000000..327d976e40660f --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-mipi-dsi.dts @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7d-sdb.dts" + +/ { + mipi_dsi_reset: mipi-dsi-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; +}; + +&lcdif { + disp-dev = "mipi_dsi_samsung"; + disp-videomode = "TRUULY-WVGA-SYNC-LOW"; +}; + +&mipi_dsi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_dsi_reset>; + lcd_panel = "TRULY-WVGA-TFT3P5581E"; + resets = <&mipi_dsi_reset>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-sdb-qspi.dts b/arch/arm/boot/dts/imx7d-sdb-qspi.dts new file mode 100644 index 00000000000000..a46990554d28ed --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-qspi.dts @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "imx7d-sdb.dts" +#include "imx7d-sdb-qspi.dtsi" diff --git a/arch/arm/boot/dts/imx7d-sdb-qspi.dtsi b/arch/arm/boot/dts/imx7d-sdb-qspi.dtsi new file mode 100644 index 00000000000000..513c597ff0786b --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-qspi.dtsi @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* disable epdc, conflict with qspi */ +&epdc { + status = "disabled"; +}; + +&iomuxc { + qspi1 { + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51 + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51 + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51 + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51 + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51 + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51 + >; + }; + }; +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_1>; + status = "okay"; + ddrsmp=<0>; + + flash0: mx25l51245g@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + reg = <0>; + }; +}; diff --git a/arch/arm/boot/dts/imx7d-sdb-usd-wifi.dts b/arch/arm/boot/dts/imx7d-sdb-usd-wifi.dts new file mode 100644 index 00000000000000..9c0642fdff4154 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-usd-wifi.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx7d-sdb.dts" + +/ { + reg_sd2_vmmc: regulator-sd2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VDD_SD2"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_brcm_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; +}; + +®_sd1_vmmc { + regulator-always-on; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + /delete-property/ cd-gpios; + /delete-property/ wp-gpios; + no-1-8-v; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; + + brcmf2: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&usdhc2 { + status = "disabled"; +}; + +&usdhc2_pwrseq { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 869efbc4af42c7..096cc16697b70c 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -19,6 +19,26 @@ reg = <0x80000000 0x80000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -56,6 +76,7 @@ #gpio-cells = <2>; reg = <0>; registers-number = <1>; + registers-default = /bits/ 8 <0x74>; /* Enable PERI_3V3, SENSOR_RST_B and HDMI_RST*/ spi-max-frequency = <100000>; }; }; @@ -87,16 +108,15 @@ regulator-max-microvolt = <1800000>; }; - reg_brcm: regulator-brcm { + reg_sd1_vmmc: regulator-sd1-vmmc { compatible = "regulator-fixed"; - gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-name = "brcm_reg"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_brcm_reg>; + regulator-name = "VDD_SD1"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; startup-delay-us = <200000>; + off-on-delay-us = <20000>; + enable-active-high; }; reg_lcd_3v3: regulator-lcd-3v3 { @@ -135,16 +155,48 @@ status = "okay"; }; - panel { - compatible = "innolux,at043tn24"; - backlight = <&backlight>; - power-supply = <®_lcd_3v3>; + pxp_v4l2_out { + compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; + sound { + compatible = "fsl,imx7d-evk-wm8960", "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai1>; + audio-codec = <&codec>; + codec-master; + /* JD2: hp detect high for headphone*/ + hp-det = <2 0>; + hp-det-gpios = <&gpio2 28 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Main MIC", + "Main MIC", "MICB"; + assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, + <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <12288000>; + }; + + sound-hdmi { + compatible = "fsl,imx7d-sdb-sii902x", + "fsl,imx-audio-sii902x"; + model = "sii902x-audio"; + cpu-dai = <&sai3>; + hdmi-controller = <&sii902x>; + }; + + usdhc2_pwrseq: usdhc2_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_brcm_reg>; + reset-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; }; }; @@ -162,6 +214,23 @@ cpu-supply = <&sw1a_reg>; }; +&clks { + assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <884736000>; +}; + +&csi1 { + csi-mux-mipi = <&gpr 0x14 4>; + fsl,mipi-mode; + status = "okay"; + + port { + csi_ep: endpoint { + remote-endpoint = <&csi_mipi_ep>; + }; + }; +}; + &ecspi3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; @@ -187,13 +256,32 @@ }; }; +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc0 &pinctrl_enet2_reg>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + en-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&epxp { + status = "okay"; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; + assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>, + <&clks IMX7D_ENET_AXI_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>; phy-mode = "rgmii"; phy-handle = <ðphy0>; fsl,magic-packet; @@ -217,10 +305,15 @@ &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2>; - assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, - <&clks IMX7D_ENET2_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; + assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>, + <&clks IMX7D_ENET_AXI_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>; phy-mode = "rgmii"; phy-handle = <ðphy1>; phy-supply = <®_fec2_3v3>; @@ -235,6 +328,31 @@ status = "okay"; }; +&mipi_csi { + clock-frequency = <240000000>; + status = "okay"; + port { + mipi_sensor_ep: endpoint@1 { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + }; + + csi_mipi_ep: endpoint@2 { + remote-endpoint = <&csi_ep>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; + nand-on-flash-bbt; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; @@ -336,6 +454,16 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + fxas2100x@20 { + compatible = "fsl,fxas2100x"; + reg = <0x20>; + }; + + fxos8700@1e { + compatible = "fsl,fxos8700"; + reg = <0x1e>; + }; + mpl3115@60 { compatible = "fsl,mpl3115"; reg = <0x60>; @@ -346,6 +474,88 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; + + sii902x: sii902x@39 { + compatible = "SiI,sii902x"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sii902x>; + interrupt-parent = <&gpio2>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + mode_str ="1280x720M@60"; + bits-per-pixel = <16>; + reg = <0x39>; + status = "okay"; + }; + + max17135: max17135@48 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_max17135>; + compatible = "maxim,max17135"; + reg = <0x48>; + status = "disabled"; + + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio2 31 0>; + gpio_pmic_vcom_ctrl = <&gpio4 14 0>; + gpio_pmic_wakeup = <&gpio2 23 0>; + gpio_pmic_v3p3 = <&gpio2 30 0>; + gpio_pmic_intr = <&gpio2 22 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* Real max value: -500000 */ + regulator-max-microvolt = <4325000>; + /* Real min value: -4325000 */ + regulator-min-microvolt = <500000>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; }; &i2c4 { @@ -360,16 +570,54 @@ clock-names = "mclk"; wlf,shared-lrclk; }; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + clocks = <&clks IMX7D_CLK_DUMMY>; + clock-names = "csi_mclk"; + csi_id = <0>; + pwn-gpios = <&extended_io 6 GPIO_ACTIVE_HIGH>; + AVDD-supply = <&vgen6_reg>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5640_mipi_ep: endpoint { + remote-endpoint = <&mipi_sensor_ep>; + }; + }; + }; }; &lcdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif>; + lcd-supply = <®_lcd_3v3>; + display = <&display0>; status = "okay"; - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; }; }; }; @@ -387,6 +635,38 @@ vin-supply = <&sw2_reg>; }; +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>; + assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>, + <&clks IMX7D_SAI3_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + +&sim1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sim1_1>; + port = <0>; + sven_low_active; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -395,7 +675,18 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart5dte>; */ status = "okay"; }; @@ -405,6 +696,7 @@ assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; uart-has-rtscts; + resets = <&modem_reset>; status = "okay"; }; @@ -420,26 +712,35 @@ }; &usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - wakeup-source; - keep-power-in-suspend; + vmmc-supply = <®_sd1_vmmc>; status = "okay"; }; &usdhc2 { + #address-cells = <1>; + #size-cells = <0>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - wakeup-source; + pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz &pinctrl_wifi>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz &pinctrl_wifi>; keep-power-in-suspend; non-removable; - vmmc-supply = <®_brcm>; + mmc-pwrseq = <&usdhc2_pwrseq>; fsl,tuning-step = <2>; + pm-ignore-notify; + cap-power-off-card; status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; }; &usdhc3 { @@ -450,8 +751,8 @@ assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; assigned-clock-rates = <400000000>; bus-width = <8>; - fsl,tuning-step = <2>; non-removable; + auto-cmd23-broken; status = "okay"; }; @@ -472,6 +773,19 @@ >; }; + pinctrl_epdc_elan_touch: epdc_elan_touch_grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x59 + MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x1b + MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x80000000 + >; + }; + pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x1b + >; + }; + pinctrl_ecspi3: ecspi3grp { fsl,pins = < MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 @@ -517,9 +831,34 @@ >; }; - pinctrl_enet2_reg: enet2reggrp { + pinctrl_epdc0: epdcgrp0 { fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x14 + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x2 + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x2 + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x2 + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x2 + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x2 + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x2 + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x2 + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x2 + MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x2 + MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x2 + MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x2 + MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x2 + MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x2 + MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x2 + MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x2 + MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x2 + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x2 + MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x2 + MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x2 + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x2 + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x2 + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x2 + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x2 + MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x2 + MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x2 + MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x2 >; }; @@ -543,6 +882,27 @@ >; }; + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX7D_PAD_SD3_CLK__NAND_CLE 0x71 + MX7D_PAD_SD3_CMD__NAND_ALE 0x71 + MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x71 + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71 + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 + MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 + MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 + MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 + MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 + MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 + MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71 + MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71 + MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 + MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 + MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 + >; + }; + pinctrl_hog: hoggrp { fsl,pins = < MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ @@ -611,6 +971,43 @@ >; }; + pinctrl_max17135: max17135grp-1 { + fsl,pins = < + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x80000000 /* pwrgood */ + MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x80000000 /* vcom_ctrl */ + MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x80000000 /* wakeup */ + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x80000000 /* v3p3 */ + MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x80000000 /* pwr int */ + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f + MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 + MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f + MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f + MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30 + MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f + MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f + MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30 + >; + }; + pinctrl_spi4: spi4grp { fsl,pins = < MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 @@ -625,6 +1022,22 @@ >; }; + pinctrl_sii902x: hdmigrp-1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x59 + >; + }; + + pinctrl_sim1_1: sim1grp-1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B 0x77 + MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD 0x77 + MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN 0x77 + MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK 0x73 + MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD 0x73 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 @@ -636,8 +1049,13 @@ fsl,pins = < MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 - MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79 - MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79 + >; + }; + + pinctrl_uart5dte: uart5dtegrp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x79 + MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x79 >; }; @@ -650,6 +1068,15 @@ >; }; + pinctrl_usdhc1_gpio: usdhc1_gpiogrp { + fsl,pins = < + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX7D_PAD_SD1_CMD__SD1_CMD 0x59 @@ -658,9 +1085,28 @@ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b >; }; @@ -745,6 +1191,12 @@ MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b >; }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x19 /* WL_HOST_WAKE */ + >; + }; }; }; @@ -755,6 +1207,12 @@ }; &iomuxc_lpsr { + pinctrl_enet2_reg: enet2reggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x80000000 + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 @@ -772,4 +1230,11 @@ MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 >; }; + + pinctrl_sai3_mclk: sai3grp_mclk { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x1f + >; + }; + }; diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 9c8dd32cc035f8..b620366fb01c05 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -22,7 +22,6 @@ reg = <1>; clock-frequency = <996000000>; operating-points-v2 = <&cpu0_opp_table>; - cpu-idle-states = <&cpu_sleep_wait>; }; }; @@ -69,6 +68,56 @@ }; soc { + busfreq { + compatible = "fsl,imx_busfreq"; + fsl,max_ddr_freq = <533000000>; + clocks = <&clks IMX7D_OSC_24M_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_SRC>, + <&clks IMX7D_AHB_CHANNEL_ROOT_SRC>, <&clks IMX7D_PLL_SYS_PFD0_392M_CLK>, + <&clks IMX7D_DRAM_ROOT_SRC>, <&clks IMX7D_DRAM_ALT_ROOT_SRC>, + <&clks IMX7D_PLL_DRAM_MAIN_CLK>, <&clks IMX7D_DRAM_ALT_ROOT_CLK>, + <&clks IMX7D_PLL_SYS_PFD2_270M_CLK>, <&clks IMX7D_PLL_SYS_PFD1_332M_CLK>, + <&clks IMX7D_AHB_CHANNEL_ROOT_DIV>, <&clks IMX7D_MAIN_AXI_ROOT_DIV>; + clock-names = "osc", "axi_sel", "ahb_sel", "pfd0_392m", "dram_root", + "dram_alt_sel", "pll_dram", "dram_alt_root", "pfd2_270m", + "pfd1_332m", "ahb", "axi"; + interrupts = <0 112 0x04>, <0 113 0x04>; + interrupt-names = "irq_busfreq_0", "irq_busfreq_1"; + }; + + ocrams_ddr: sram@900000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x900000 0x1000>; + clocks = <&clks IMX7D_OCRAM_CLK>; + }; + + ocram: sram@901000 { + compatible = "mmio-sram"; + reg = <0x901000 0x1f000>; + clocks = <&clks IMX7D_OCRAM_CLK>; + }; + + ocrams: sram@180000 { + compatible = "fsl,lpm-sram"; + reg = <0x180000 0x8000>; + clocks = <&clks IMX7D_OCRAM_S_CLK>; + status = "disabled"; + }; + + ocram_optee { + compatible = "fsl,optee-lpm-sram"; + reg = <0x180000 0x8000>; + overw_reg = <&ocrams_ddr 0x904000 0x1000>, + <&ocram 0x905000 0x1b000>, + <&ocrams 0x900000 0x4000>; + overw_clock = <&ocrams &clks IMX7D_OCRAM_CLK>; + }; + + ocrams_mf: sram-mf@900000 { + compatible = "fsl,mega-fast-sram"; + reg = <0x900000 0x20000>; + clocks = <&clks IMX7D_OCRAM_CLK>; + }; + etm@3007d000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0x3007d000 0x1000>; @@ -106,15 +155,157 @@ }; }; +/delete-node/&csi; +/delete-node/&video_mux; + &aips2 { pcie_phy: pcie-phy@306d0000 { compatible = "fsl,imx7d-pcie-phy"; reg = <0x306d0000 0x10000>; status = "disabled"; }; + + system_counter_rd: system-counter-rd@306a0000 { + compatible = "fsl,imx7d-system-counter-rd"; + reg = <0x306a0000 0x10000>; + status = "disabled"; + }; + + system_counter_cmp: system-counter-cmp@306b0000 { + compatible = "fsl,imx7d-system-counter-cmp"; + reg = <0x306b0000 0x10000>; + status = "disabled"; + }; + + system_counter_ctrl: system-counter-ctrl@306c0000 { + compatible = "fsl,imx7d-system-counter-ctrl"; + reg = <0x306c0000 0x10000>; + interrupts = , + ; + status = "disabled"; + }; + + epdc: epdc@306f0000 { + compatible = "fsl,imx7d-epdc"; + interrupts = ; + reg = <0x306f0000 0x10000>; + clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_EPDC_PIXEL_ROOT_CLK>; + clock-names = "epdc_axi", "epdc_pix"; + epdc-ram = <&gpr 0x4 30>; + qos = <&qosc>; + status = "disabled"; + }; + + epxp: epxp@30700000 { + compatible = "fsl,imx7d-pxp-dma"; + interrupts = , + ; + reg = <0x30700000 0x10000>; + clocks = <&clks IMX7D_PXP_IPG_CLK>, <&clks IMX7D_PXP_AXI_CLK>; + clock-names = "pxp_ipg", "pxp_axi"; + status = "disabled"; + }; + + csi1: csi1@30710000 { + compatible = "fsl,imx7d-csi", "fsl,imx6s-csi"; + reg = <0x30710000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CSI_MCLK_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + + mipi_csi: mipi-csi@30750000 { + compatible = "fsl,imx7d-mipi-csi"; + reg = <0x30750000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_MIPI_CSI_ROOT_CLK>, + <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; + clock-names = "mipi_clk", "phy_clk"; + mipi-phy-supply = <®_1p0d>; + csis-phy-reset = <&src 0x28 2>; + bus-width = <4>; + status = "disabled"; + /delete-node/ port@0; + /delete-node/ port@1; + }; + + mipi_dsi: mipi-dsi@30760000 { + compatible = "fsl,imx7d-mipi-dsi"; + reg = <0x30760000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>, + <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; + clock-names = "mipi_cfg_clk", "mipi_pllref_clk"; + power-domains = <&pgc_mipi_phy>; + status = "disabled"; + }; + + qosc: qosc@307f0000 { + compatible = "fsl,imx7d-qosc", "syscon"; + reg = <0x307f0000 0x4000>; + }; }; &aips3 { + mu: mu@30aa0000 { + compatible = "fsl,imx7d-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_MU_ROOT_CLK>; + clock-names = "mu"; + #mbox-cells = <2>; + }; + + mu_lp: mu_lp@30aa0000 { + compatible = "fsl,imx7d-mu-lp", "fsl,imx6sx-mu-lp"; + reg = <0x30aa0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_MU_ROOT_CLK>; + clock-names = "mu"; + status = "okay"; + }; + + sema4: sema4@30ac0000 { + compatible = "fsl,imx7d-sema4"; + reg = <0x30ac0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_SEMA4_HS_ROOT_CLK>; + clock-names = "sema4"; + status = "okay"; + }; + + sim1: sim@30b90000 { + compatible = "fsl,imx7d-sim"; + reg = <0x30b90000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_SIM1_ROOT_CLK>; + clock-names = "sim"; + status = "disabled"; + }; + + qspi1: spi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-qspi"; + reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = ; + clocks = <&clks IMX7D_QSPI_ROOT_CLK>, + <&clks IMX7D_QSPI_ROOT_CLK>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + sim2: sim@30ba0000 { + compatible = "fsl,imx7d-sim"; + reg = <0x30ba0000 0x10000>; + interrupts = ; + status = "disabled"; + }; + usbotg2: usb@30b20000 { compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x30b20000 0x200>; @@ -144,7 +335,7 @@ <&clks IMX7D_ENET_AXI_ROOT_CLK>, <&clks IMX7D_ENET2_TIME_ROOT_CLK>, <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, - <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; + <&clks IMX7D_ENET_PHY_REF_ROOT_DIV>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; fsl,num-tx-queues = <3>; @@ -195,6 +386,20 @@ fsl,imx7d-pcie-phy = <&pcie_phy>; status = "disabled"; }; + + rpmsg: rpmsg{ + compatible = "fsl,imx7d-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + status = "disabled"; + }; }; &ca_funnel_in_ports { diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index e2e604d6ba0b45..0f428e36dac8a9 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -53,19 +53,6 @@ #address-cells = <1>; #size-cells = <0>; - idle-states { - entry-method = "psci"; - - cpu_sleep_wait: cpu-sleep-wait { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <100>; - exit-latency-us = <50>; - min-residency-us = <1000>; - }; - }; - cpu0: cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; @@ -73,7 +60,6 @@ clock-frequency = <792000000>; clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clks IMX7D_CLK_ARM>; - cpu-idle-states = <&cpu_sleep_wait>; }; }; @@ -158,15 +144,6 @@ clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; }; - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&intc>; - interrupts = , - , - , - ; - }; - soc { #address-cells = <1>; #size-cells = <1>; @@ -216,6 +193,11 @@ }; }; + caam_sm: caam-sm@100000 { + compatible = "fsl,imx7d-caam-sm", "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + funnel@30083000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x30083000 0x1000>; @@ -316,6 +298,17 @@ <0x31006000 0x2000>; }; + timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; + interrupt-parent = <&intc>; + interrupts = , + , + , + ; + clock-frequency = <8000000>; + }; + aips1: aips-bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; @@ -449,8 +442,9 @@ reg = <0x302d0000 0x10000>; interrupts = ; clocks = <&clks IMX7D_GPT1_ROOT_CLK>, - <&clks IMX7D_GPT1_ROOT_CLK>; - clock-names = "ipg", "per"; + <&clks IMX7D_GPT1_ROOT_CLK>, + <&clks IMX7D_GPT_3M_CLK>; + clock-names = "ipg", "per", "osc_per"; }; gpt2: gpt@302e0000 { @@ -593,6 +587,20 @@ }; }; + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + }; + snvs: snvs@30370000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x30370000 0x10000>; @@ -607,10 +615,21 @@ clock-names = "snvs-rtc"; }; + snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; + value = <0x60>; + mask = <0x60>; + status = "disabled"; + }; + snvs_pwrkey: snvs-powerkey { compatible = "fsl,sec-v4.0-pwrkey"; regmap = <&snvs>; interrupts = ; + clocks = <&clks IMX7D_SNVS_CLK>; + clock-names = "snvs"; linux,keycode = ; wakeup-source; status = "disabled"; @@ -628,7 +647,7 @@ }; src: src@30390000 { - compatible = "fsl,imx7d-src", "syscon"; + compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon"; reg = <0x30390000 0x10000>; interrupts = ; #reset-cells = <1>; @@ -641,6 +660,7 @@ interrupts = ; #interrupt-cells = <3>; interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x54010000 0xc00 0x0 0x1040640>; #power-domain-cells = <1>; pgc { @@ -658,6 +678,12 @@ reg = <1>; power-supply = <®_1p0d>; }; + + pgc_hsic_phy: power-domain@2 { + #power-domain-cells = <0>; + reg = <2>; + power-supply = <®_1p2>; + }; }; }; }; @@ -767,8 +793,9 @@ reg = <0x30730000 0x10000>; interrupts = ; clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, - <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; - clock-names = "pix", "axi"; + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "pix", "axi", "disp_axi"; status = "disabled"; }; @@ -800,6 +827,11 @@ }; }; }; + + ddrc: ddrc@307a0000 { + compatible = "fsl,imx7-ddrc"; + reg = <0x307a0000 0x10000>; + }; }; aips3: aips-bus@30800000 { @@ -871,6 +903,8 @@ clocks = <&clks IMX7D_UART2_ROOT_CLK>, <&clks IMX7D_UART2_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 24 4 0>, <&sdma 25 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -882,6 +916,8 @@ clocks = <&clks IMX7D_UART3_ROOT_CLK>, <&clks IMX7D_UART3_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 26 4 0>, <&sdma 27 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -1031,6 +1067,8 @@ clocks = <&clks IMX7D_UART4_ROOT_CLK>, <&clks IMX7D_UART4_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 28 4 0>, <&sdma 29 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -1042,6 +1080,8 @@ clocks = <&clks IMX7D_UART5_ROOT_CLK>, <&clks IMX7D_UART5_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 30 4 0>, <&sdma 31 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -1053,6 +1093,8 @@ clocks = <&clks IMX7D_UART6_ROOT_CLK>, <&clks IMX7D_UART6_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 32 4 0>, <&sdma 33 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -1064,6 +1106,8 @@ clocks = <&clks IMX7D_UART7_ROOT_CLK>, <&clks IMX7D_UART7_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 34 4 0>, <&sdma 35 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -1101,6 +1145,7 @@ compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x30b30000 0x200>; interrupts = ; + power-domains = <&pgc_hsic_phy>; clocks = <&clks IMX7D_USB_CTRL_CLK>; fsl,usbphy = <&usbphynop3>; fsl,usbmisc = <&usbmisc3 0>; @@ -1131,6 +1176,8 @@ <&clks IMX7D_USDHC1_ROOT_CLK>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; status = "disabled"; }; @@ -1143,6 +1190,8 @@ <&clks IMX7D_USDHC2_ROOT_CLK>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; status = "disabled"; }; @@ -1155,6 +1204,8 @@ <&clks IMX7D_USDHC3_ROOT_CLK>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; status = "disabled"; }; @@ -1181,7 +1232,7 @@ <&clks IMX7D_ENET_AXI_ROOT_CLK>, <&clks IMX7D_ENET1_TIME_ROOT_CLK>, <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, - <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; + <&clks IMX7D_ENET_PHY_REF_ROOT_DIV>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; fsl,num-tx-queues = <3>; diff --git a/arch/arm/boot/dts/imx7ulp-evk-ft5416.dts b/arch/arm/boot/dts/imx7ulp-evk-ft5416.dts new file mode 100644 index 00000000000000..b959c6852f9a12 --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-evk-ft5416.dts @@ -0,0 +1,15 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evk.dts" +&lpi2c7 { + focaltech@38 { + focaltech,panel-type = ; + focaltech,swap-xy; + }; +}; diff --git a/arch/arm/boot/dts/imx7ulp-evk-mipi.dts b/arch/arm/boot/dts/imx7ulp-evk-mipi.dts new file mode 100644 index 00000000000000..a467fad79846d3 --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-evk-mipi.dts @@ -0,0 +1,10 @@ +/* + * Copyright 2017-2018 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evk.dts" +#include "imx7ulp-evk-mipi.dtsi" diff --git a/arch/arm/boot/dts/imx7ulp-evk-mipi.dtsi b/arch/arm/boot/dts/imx7ulp-evk-mipi.dtsi new file mode 100644 index 00000000000000..4caeefbf3b68d7 --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-evk-mipi.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright 2018 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&adv7535 { + status = "disabled"; + + /delete-node/ port; +}; + +&mipi_dsi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_mipi_dsi_reset>; + pinctrl-1 = <&pinctrl_mipi_dsi_reset>; + lcd_panel = "TRULY-WVGA-TFT3P5581E"; + resets = <&mipi_dsi_reset>; + + /delete-node/ port; +}; diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts index 4245b33bb45185..c62c6222cca7fc 100644 --- a/arch/arm/boot/dts/imx7ulp-evk.dts +++ b/arch/arm/boot/dts/imx7ulp-evk.dts @@ -8,11 +8,17 @@ /dts-v1/; #include "imx7ulp.dtsi" +#include / { model = "NXP i.MX7ULP EVK"; compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp"; + aliases { + gpio4 = &rpmsg_gpio0; + gpio5 = &rpmsg_gpio1; + }; + chosen { stdout-path = &lpuart4; }; @@ -22,6 +28,38 @@ reg = <0x60000000 0x40000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vdev0vring0: vdev0vring0@9ff00000 { + compatible = "shared-dma-pool"; + reg = <0x9ff00000 0x8000>; + no-map; + }; + vdev0vring1: vdev0vring1@9ff08000 { + compatible = "shared-dma-pool"; + reg = <0x9ff08000 0x8000>; + no-map; + }; + vdev1vring0: vdev1vring0@9ff10000 { + compatible = "shared-dma-pool"; + reg = <0x9ff10000 0x8000>; + no-map; + }; + vdev1vring1: vdev1vring1@9ff18000 { + compatible = "shared-dma-pool"; + reg = <0x9ff18000 0x8000>; + no-map; + }; + vdev1vring3 { + compatible = "shared-dma-pool"; + reg = <0x9ff20000 0xe0000>; + no-map; + }; + }; + backlight { compatible = "pwm-backlight"; pwms = <&tpm4 1 50000 0>; @@ -30,35 +68,365 @@ status = "okay"; }; - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_vbus>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio_ptc 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vsd_3v3: regulator-vsd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + mipi_dsi_reset: mipi-dsi-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio_ptc 19 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&rpmsg_gpio0 15 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + + pf1550-rpmsg { + compatible = "fsl,pf1550-rpmsg"; + sw1_reg: SW1 { + regulator-name = "SW1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1387500>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: SW2 { + regulator-name = "SW2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1387500>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: SW3 { + regulator-name = "SW3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: VREFDDR { + regulator-name = "VREFDDR"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + vldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cell = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usbotg1_vbus>; + pinctrl-1 = <&pinctrl_usbotg1_vbus>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio_ptc 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vsd_3v3: regulator-vsd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc0_rst>; + gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + enable-active-high; + }; + + reg_sd1_vmmc: sd1_regulator { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&rpmsg_gpio0 14 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + off-on-delay-us = <20000>; + enable-active-high; + }; + }; + + rpmsg_gpio0: rpmsg-gpio0 { + compatible = "fsl,imx-rpmsg-gpio"; + port_idx = <0>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&rpmsg_gpio0>; + status = "okay"; + }; + + rpmsg_gpio1: rpmsg-gpio1 { + compatible = "fsl,imx-rpmsg-gpio"; + port_idx = <1>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&rpmsg_gpio1>; + status = "okay"; + }; + + rpmsg_keys: rpmsg-keys { + compatible = "fsl,rpmsg-keys"; + + volume-up { + label = "Volume Up"; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + linux,code = ; + }; + + power-on { + label = "PowerOn"; + linux,code = ; + rpmsg-key,wakeup; + }; + }; + + rpmsg_sensor: rpmsg-sensor { + compatible = "fsl,rpmsg-input"; + }; + + rpmsg_i2s: rpmsg-i2s { + compatible = "fsl,imx7ulp-rpmsg-i2s"; + /* the audio device index in m4 domain */ + fsl,audioindex = <0> ; + status = "okay"; + }; + + sound-rpmsg { + compatible = "fsl,imx-audio-rpmsg"; + model = "wm8960-audio"; + cpu-dai = <&rpmsg_i2s>; + rpmsg-out; + rpmsg-in; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Main MIC", + "RINPUT2", "Main MIC", + "Mic Jack", "MICB", + "Main MIC", "MICB", + "Playback", "CPU-Playback", + "CPU-Capture", "Capture"; + }; + + imx7ulp-cm4 { + compatible = "fsl,imx7ulp-cm4"; + ipc-only; + rsc-da=<0x1fff8000>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>; + }; +}; + +&cpu0 { + arm-supply= <&sw1_reg>; +}; + +&lpspi3 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpspi3>; + pinctrl-1 = <&pinctrl_lpspi3>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <1000000>; + }; +}; + +&lpi2c5 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c5>; + pinctrl-1 = <&pinctrl_lpi2c5>; + status = "okay"; + + adv7535: adv7535@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; /* PD pin is low */ pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc0_rst>; - gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>; - enable-active-high; + pinctrl-0 = <&pinctrl_dsi_hdmi>; + interrupt-parent = <&gpio_ptc>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + video-mode = <1>; /* + * Only support CEA modes. + * Reference mxc_edid.c + */ + dsi-traffic-mode = <0>; + bpp = <24>; + status = "disabled"; + }; +}; + +&lcdif { + status = "okay"; + disp-dev = "mipi_dsi_northwest"; + display = <&display0>; + + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; }; }; &lpuart4 { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_lpuart4>; + pinctrl-1 = <&pinctrl_lpuart4>; + status = "okay"; +}; + +&lpuart6 { /* BT */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpuart6>; + pinctrl-1 = <&pinctrl_lpuart6>; + resets = <&modem_reset>; status = "okay"; }; +&lpuart7 { /* Uart test */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpuart7>; + pinctrl-1 = <&pinctrl_lpuart7>; + status = "disabled"; +}; + +&lpi2c7 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c7 &pinctrl_touch_io>; + pinctrl-1 = <&pinctrl_lpi2c7 &pinctrl_touch_io>; + status = "okay"; + + focaltech@38 { + compatible = "focaltech,fts"; + reg = <0x38>; + interrupt-parent = <&gpio_ptf>; + interrupts = <0 0x2>; + focaltech,panel-type = ; + focaltech,reset-gpio = <&gpio_ptf 1 0x1>; + focaltech,irq-gpio = <&gpio_ptf 0 0x2>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 480 854>; + + focaltech,have-key; + focaltech,key-number = <3>; + focaltech,keys = <139 102 158>; + focaltech,key-y-coord = <2000>; + focaltech,key-x-coords = <200 600 800>; + }; +}; + +&adv7535 { + status = "okay"; + + port { + dsi_to_hdmi: endpoint { + remote-endpoint = <&mipi_dsi_ep>; + }; + }; +}; + +&mipi_dsi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_mipi_dsi_reset>; + pinctrl-1 = <&pinctrl_mipi_dsi_reset>; + lcd_panel = "TRULY-WVGA-TFT3P5581E"; + resets = <&mipi_dsi_reset>; + status = "okay"; + + port { + mipi_dsi_ep: endpoint { + remote-endpoint = <&dsi_to_hdmi>; + }; + }; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance, default using 2 rpmsg instances: + * --0x9FF00000~0x9FF0FFFF: pmic,pm,audio,keys,gpio,sensor + * --0x9FF10000~0x9FF1FFFF: pingpong,virtual tty + */ + vdev-nums = <2>; + reg = <0x9FF00000 0x20000>; + status = "disabled"; +}; + &tpm4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm0>; @@ -67,24 +435,56 @@ &usbotg1 { vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_usbotg1_id>; + pinctrl-1 = <&pinctrl_usbotg1_id>; srp-disable; hnp-disable; adp-disable; - over-current-active-low; + disable-over-current; status = "okay"; }; &usdhc0 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0>; + pinctrl-2 = <&pinctrl_usdhc0>; + pinctrl-3 = <&pinctrl_usdhc0>; + fsl,delay-line = <15>; cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>; vmmc-supply = <®_vsd_3v3>; + vqmmc-supply = <&vldo2_reg>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + bus-width = <4>; + no-1-8-v; + vmmc-supply = <®_sd1_vmmc>; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; status = "okay"; }; &iomuxc1 { + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = < + IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x27 + IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x27 + >; + }; + + pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp { + fsl,pins = < + IMX7ULP_PAD_PTC19__PTC19 0x20003 + >; + }; + pinctrl_lpuart4: lpuart4grp { fsl,pins = < IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 @@ -93,12 +493,54 @@ bias-pull-up; }; + pinctrl_lpuart6: lpuart6grp { + fsl,pins = < + IMX7ULP_PAD_PTE10__LPUART6_TX 0x3 + IMX7ULP_PAD_PTE11__LPUART6_RX 0x3 + IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x3 + IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x3 + IMX7ULP_PAD_PTE7__PTE7 0x20000 /* BT_REG_ON */ + >; + }; + + pinctrl_lpuart7: lpuart7grp { + fsl,pins = < + IMX7ULP_PAD_PTF14__LPUART7_TX 0x3 + IMX7ULP_PAD_PTF15__LPUART7_RX 0x3 + IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x3 + IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x3 + >; + }; + + pinctrl_lpi2c7: lpi2c7grp { + fsl,pins = < + IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x27 + IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x27 + >; + }; + + pinctrl_touch_io: touchiogrp { + fsl,pins = < + IMX7ULP_PAD_PTF0__PTF0 0x10043 + IMX7ULP_PAD_PTF1__PTF1 0x20043 + >; + }; + pinctrl_pwm0: pwm0grp { fsl,pins = < IMX7ULP_PAD_PTF2__TPM4_CH1 0x2 >; }; + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x0 + IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x0 + IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x0 + IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x0 + >; + }; + pinctrl_usbotg1_vbus: otg1vbusgrp { fsl,pins = < IMX7ULP_PAD_PTC0__PTC0 0x20000 @@ -108,7 +550,6 @@ pinctrl_usbotg1_id: otg1idgrp { fsl,pins = < IMX7ULP_PAD_PTC13__USB0_ID 0x10003 - IMX7ULP_PAD_PTC16__USB1_OC2 0x10003 >; }; @@ -124,9 +565,51 @@ >; }; + pinctrl_usdhc0_8bit: usdhc0grp_8bit { + fsl,pins = < + IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 + IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042 + IMX7ULP_PAD_PTD3__SDHC0_D7 0x43 + IMX7ULP_PAD_PTD4__SDHC0_D6 0x43 + IMX7ULP_PAD_PTD5__SDHC0_D5 0x43 + IMX7ULP_PAD_PTD6__SDHC0_D4 0x43 + IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 + IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 + IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 + IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 + IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42 + >; + }; + pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp { fsl,pins = < IMX7ULP_PAD_PTD0__PTD0 0x3 >; }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX7ULP_PAD_PTE3__SDHC1_CMD 0x43 + IMX7ULP_PAD_PTE2__SDHC1_CLK 0x10042 + IMX7ULP_PAD_PTE1__SDHC1_D0 0x43 + IMX7ULP_PAD_PTE0__SDHC1_D1 0x43 + IMX7ULP_PAD_PTE5__SDHC1_D2 0x43 + IMX7ULP_PAD_PTE4__SDHC1_D3 0x43 + >; + }; + + pinctrl_usdhc1_rst: usdhc1grp_rst { + fsl,pins = < + IMX7ULP_PAD_PTE11__PTE11 0x20000 /* USDHC1 RST */ + IMX7ULP_PAD_PTE13__PTE13 0x10003 /* USDHC1 CD */ + IMX7ULP_PAD_PTE12__PTE12 0x10003 /* USDHC1 WP */ + IMX7ULP_PAD_PTE14__SDHC1_VS 0x43 /* USDHC1 VSEL */ + >; + }; + + pinctrl_dsi_hdmi: dsi_hdmi_grp { + fsl,pins = < + IMX7ULP_PAD_PTC18__PTC18 0x10003 /* DSI_HDMI_INT */ + >; + }; }; diff --git a/arch/arm/boot/dts/imx7ulp-evkb-emmc.dts b/arch/arm/boot/dts/imx7ulp-evkb-emmc.dts new file mode 100644 index 00000000000000..ca6acd44de1943 --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-evkb-emmc.dts @@ -0,0 +1,26 @@ +/* + * Copyright 2019 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evkb.dts" + +/* To support eMMC HS200/HS400, need to do the following reowrk: + * 1,remove TF sd slot, replace eMMC chip + * 2,fix eMMC I/O voltage to 1.8v, remove R183, short TP3 and TP89 + * 3,add R107, make eMMC boot work + */ +&usdhc0 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0_8bit>; + pinctrl-1 = <&pinctrl_usdhc0_8bit>; + pinctrl-2 = <&pinctrl_usdhc0_8bit>; + pinctrl-3 = <&pinctrl_usdhc0_8bit>; + non-removable; + bus-width = <8>; + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/imx7ulp-evkb-lpuart.dts b/arch/arm/boot/dts/imx7ulp-evkb-lpuart.dts new file mode 100644 index 00000000000000..1a5da007edf615 --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-evkb-lpuart.dts @@ -0,0 +1,17 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evkb.dts" + +&lpi2c7 { + status = "disabled"; +}; + +&lpuart7 { /* Uart test */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7ulp-evkb-mipi.dts b/arch/arm/boot/dts/imx7ulp-evkb-mipi.dts new file mode 100644 index 00000000000000..0ebf73f2618a43 --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-evkb-mipi.dts @@ -0,0 +1,25 @@ +/* + * Copyright 2018 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evkb.dts" +#include "imx7ulp-evk-mipi.dtsi" + +&lpi2c7 { + focaltech@38 { + status = "disabled"; + }; + + goodix@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + interrupt-parent = <&gpio_ptf>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&gpio_ptf 0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio_ptf 1 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/boot/dts/imx7ulp-evkb-rm68191-qhd.dts b/arch/arm/boot/dts/imx7ulp-evkb-rm68191-qhd.dts new file mode 100644 index 00000000000000..c482087c08e07b --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-evkb-rm68191-qhd.dts @@ -0,0 +1,13 @@ +/* + * Copyright 2018 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evkb-mipi.dts" + +&mipi_dsi { + lcd_panel = "ROCKTECH-QHD-RK055IQH042"; +}; diff --git a/arch/arm/boot/dts/imx7ulp-evkb-rm68200-wxga.dts b/arch/arm/boot/dts/imx7ulp-evkb-rm68200-wxga.dts new file mode 100644 index 00000000000000..28b83c3881016d --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-evkb-rm68200-wxga.dts @@ -0,0 +1,13 @@ +/* + * Copyright 2018 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evkb-mipi.dts" + +&mipi_dsi { + lcd_panel = "ROCKTECH-WXGA-RK055AHD042"; +}; diff --git a/arch/arm/boot/dts/imx7ulp-evkb-sd1.dts b/arch/arm/boot/dts/imx7ulp-evkb-sd1.dts new file mode 100644 index 00000000000000..8984a6ace291f5 --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-evkb-sd1.dts @@ -0,0 +1,45 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evkb.dts" + +/ { + regulators { + reg_vsd_3v3b: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3B"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio_pte 11 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + enable-active-high; + }; + }; +}; + +&lpuart6 { + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_rst>; + pinctrl-1 = <&pinctrl_usdhc1 &pinctrl_usdhc1_rst>; + pinctrl-2 = <&pinctrl_usdhc1 &pinctrl_usdhc1_rst>; + pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_usdhc1_rst>; + cd-gpios = <&gpio_pte 13 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio_pte 12 GPIO_ACTIVE_HIGH>; + fsl,delay-line = <15>; + vmmc-supply = <®_vsd_3v3b>; + /delete-property/non-removable; + /delete-property/pm-ignore-notify; + /delete-property/keep-power-in-suspend; + /delete-property/non-removable; + /delete-property/no-1-8-v; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7ulp-evkb-sensors-to-i2c5.dts b/arch/arm/boot/dts/imx7ulp-evkb-sensors-to-i2c5.dts new file mode 100644 index 00000000000000..83a712b9b4f3f8 --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-evkb-sensors-to-i2c5.dts @@ -0,0 +1,21 @@ + +#include "imx7ulp-evkb.dts" + +&lpi2c5 { + + fxas2100x@20 { + compatible = "fsl,fxas2100x"; + reg = <0x20>; + }; + + fxos8700@1e { + compatible = "fsl,fxos8700"; + reg = <0x1e>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; + +}; diff --git a/arch/arm/boot/dts/imx7ulp-evkb-spi-slave.dts b/arch/arm/boot/dts/imx7ulp-evkb-spi-slave.dts new file mode 100644 index 00000000000000..83cb121ff50a90 --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-evkb-spi-slave.dts @@ -0,0 +1,30 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evkb.dts" + +/delete-node/&spidev0; + +&pinctrl_lpspi3 { + fsl,pins = < + IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x0 + IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x0 + IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x0 + IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x0 + >; +}; + +&lpspi3 { + #address-cells = <0>; + pinctrl-0 = <&pinctrl_lpspi3>; + pinctrl-1 = <&pinctrl_lpspi3>; + /delete-property/ cs-gpios; + + spi-slave; +}; diff --git a/arch/arm/boot/dts/imx7ulp-evkb.dts b/arch/arm/boot/dts/imx7ulp-evkb.dts new file mode 100644 index 00000000000000..37df895583497a --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-evkb.dts @@ -0,0 +1,39 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evk.dts" + +/ { + model = "NXP i.MX7ULP EVKB"; + compatible = "fsl,imx7ulp-evkb", "fsl,imx7ulp", "Generic DT based system"; + + regulators { + reg_sd1_vmmc: sd1_regulator { + status = "disabled"; + }; + }; + + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&rpmsg_gpio0 14 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <80>; + }; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + /delete-property/ vmmc-supply; + mmc-pwrseq = <&usdhc1_pwrseq>; + cap-power-off-card; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index 3dac6898cdc57e..89f7b251603d7d 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -41,9 +41,41 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0xf00>; + operating-points = < + /* KHz uV */ + 720000 1125000 + 500210 1025000 + >; + clocks = <&smc1 IMX7ULP_CLK_ARM>, + <&scg1 IMX7ULP_CLK_CORE_DIV>, + <&scg1 IMX7ULP_CLK_SYS_SEL>, + <&scg1 IMX7ULP_CLK_HSRUN_SYS_SEL>, + <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>, + <&scg1 IMX7ULP_CLK_SPLL_PFD0>, + <&scg1 IMX7ULP_CLK_SPLL_SEL>, + <&scg1 IMX7ULP_CLK_FIRC>, + <&scg1 IMX7ULP_CLK_SPLL>; + clock-names = "arm", "core_div", "sys_sel", "hsrun_sys_sel", + "hsrun_core", "spll_pfd0", "spll_sel", "firc", + "spll"; }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0xC000000>; + alignment = <0x2000>; + linux,cma-default; + }; + }; + intc: interrupt-controller@40021000 { compatible = "arm,cortex-a7-gic"; #interrupt-cells = <3>; @@ -87,11 +119,14 @@ #clock-cells = <0>; }; - mpll: clock-mpll { - compatible = "fixed-clock"; - clock-frequency = <480000000>; - clock-output-names = "mpll"; - #clock-cells = <0>; + sram: sram@20000000 { + compatible = "fsl,lpm-sram"; + reg = <0x1fffc000 0x4000>; + }; + + caam_sm: caam-sm@26000000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x26000000 0x8000>; }; ahbbridge0: bus@40000000 { @@ -129,6 +164,62 @@ <&pcc2 IMX7ULP_CLK_DMA_MUX1>; }; + mu: mu@40220000 { + compatible = "fsl,imx7ulp-mu"; + reg = <0x40220000 0x1000>; + interrupts = ; + #mbox-cells = <2>; + }; + + nmi: nmi@40220000 { + compatible = "fsl,imx7ulp-nmi"; + reg = <0x40220000 0x1000>; + interrupts = ; + status = "okay"; + }; + + mu_lp: mu_lp@40220000 { + compatible = "fsl,imx7ulp-mu-lp", "fsl,imx6sx-mu-lp"; + reg = <0x40220000 0x1000>; + interrupts = , + ; + status = "okay"; + }; + + lpspi2: spi@40290000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7ulp-spi"; + reg = <0x40290000 0x10000>; + interrupts = ; + clocks = <&pcc2 IMX7ULP_CLK_LPSPI2>, + <&pcc2 IMX7ULP_CLK_DUMMY>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPSPI2>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; + assigned-clock-rates = <48000000>; + dmas = <&edma1 0 26>, <&edma1 0 25>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi3: spi@402A0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7ulp-spi"; + reg = <0x402A0000 0x10000>; + interrupts = ; + clocks = <&pcc2 IMX7ULP_CLK_LPSPI3>, + <&pcc2 IMX7ULP_CLK_DUMMY>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPSPI3>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; + assigned-clock-rates = <48000000>; + dmas = <&edma1 0 28>, <&edma1 0 27>; + dma-names = "tx","rx"; + status = "disabled"; + }; + crypto: crypto@40240000 { compatible = "fsl,sec-v4.0"; #address-cells = <1>; @@ -152,6 +243,31 @@ }; }; + lpi2c4: lpi2c4@402b0000 { + compatible = "fsl,imx7ulp-lpi2c"; + reg = <0x402b0000 0x10000>; + interrupts = ; + clocks = <&pcc2 IMX7ULP_CLK_LPI2C4>, + <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPI2C4>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpi2c5: lpi2c5@402c0000 { + compatible = "fsl,imx7ulp-lpi2c"; + reg = <0x402c0000 0x10000>; + interrupts = ; + clocks = <&pcc2 IMX7ULP_CLK_LPI2C5>, + <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPI2C5>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; + assigned-clock-rates = <48000000>; + }; + lpuart4: serial@402d0000 { compatible = "fsl,imx7ulp-lpuart"; reg = <0x402d0000 0x1000>; @@ -171,8 +287,10 @@ clocks = <&pcc2 IMX7ULP_CLK_LPUART5>; clock-names = "ipg"; assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; assigned-clock-rates = <48000000>; + dmas = <&edma1 0 20>, <&edma1 0 19>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -220,6 +338,7 @@ interrupts = ; clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>; #phy-cells = <0>; + nxp,sim = <&sim>; }; usdhc0: mmc@40370000 { @@ -230,8 +349,9 @@ <&scg1 IMX7ULP_CLK_NIC1_DIV>, <&pcc2 IMX7ULP_CLK_USDHC0>; clock-names = "ipg", "ahb", "per"; - assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>; + assigned-clocks = <&scg1 IMX7ULP_CLK_APLL_PFD1>, <&pcc2 IMX7ULP_CLK_USDHC0>; + assigned-clock-parents = <0>, <&scg1 IMX7ULP_CLK_APLL_PFD1>; + assigned-clock-rates = <0>, <352800000>; bus-width = <4>; fsl,tuning-start-tap = <20>; fsl,tuning-step = <2>; @@ -246,8 +366,9 @@ <&scg1 IMX7ULP_CLK_NIC1_DIV>, <&pcc2 IMX7ULP_CLK_USDHC1>; clock-names = "ipg", "ahb", "per"; - assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>; + assigned-clocks = <&scg1 IMX7ULP_CLK_APLL_PFD1>, <&pcc2 IMX7ULP_CLK_USDHC1>; + assigned-clock-parents = <0>, <&scg1 IMX7ULP_CLK_APLL_PFD1>; + assigned-clock-rates = <0>, <352800000>; bus-width = <4>; fsl,tuning-start-tap = <20>; fsl,tuning-step = <2>; @@ -258,12 +379,37 @@ compatible = "fsl,imx7ulp-scg1"; reg = <0x403e0000 0x10000>; clocks = <&rosc>, <&sosc>, <&sirc>, - <&firc>, <&upll>, <&mpll>; + <&firc>, <&upll>; clock-names = "rosc", "sosc", "sirc", - "firc", "upll", "mpll"; + "firc", "upll"; #clock-cells = <1>; }; + wdog1: wdog@403D0000 { + compatible = "fsl,imx7ulp-wdt"; + reg = <0x403D0000 0x10000>; + interrupts = ; + clocks = <&pcc2 IMX7ULP_CLK_WDG1>; + assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>; + assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; + /* + * As the 1KHz LPO clock rate is not trimed,the actually clock + * is about 667Hz, so the init timeout 60s should set 40*1000 + * in the TOVAL register. + */ + timeout-sec = <40>; + }; + + wdog2: wdog@40430000 { + compatible = "fsl,imx7ulp-wdt"; + reg = <0x40430000 0x10000>; + interrupts = ; + clocks = <&pcc2 IMX7ULP_CLK_WDG2>; + assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG2>; + assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; + timeout-sec = <40>; + }; + pcc2: clock-controller@403f0000 { compatible = "fsl,imx7ulp-pcc2"; reg = <0x403f0000 0x10000>; @@ -276,18 +422,22 @@ <&scg1 IMX7ULP_CLK_APLL_PFD0>, <&scg1 IMX7ULP_CLK_UPLL>, <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, - <&scg1 IMX7ULP_CLK_MIPI_PLL>, <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, <&scg1 IMX7ULP_CLK_ROSC>, <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", - "upll", "sosc_bus_clk", "mpll", + "upll", "sosc_bus_clk", "firc_bus_clk", "rosc", "spll_bus_clk"; assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>; assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; }; + pmc1: pmc1@40400000 { + compatible = "fsl,imx7ulp-pmc1"; + reg = <0x40400000 0x1000>; + }; + smc1: clock-controller@40410000 { compatible = "fsl,imx7ulp-smc1"; reg = <0x40410000 0x1000>; @@ -309,13 +459,12 @@ <&scg1 IMX7ULP_CLK_APLL_PFD0>, <&scg1 IMX7ULP_CLK_UPLL>, <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, - <&scg1 IMX7ULP_CLK_MIPI_PLL>, <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, <&scg1 IMX7ULP_CLK_ROSC>, <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", - "upll", "sosc_bus_clk", "mpll", + "upll", "sosc_bus_clk", "firc_bus_clk", "rosc", "spll_bus_clk"; }; }; @@ -331,10 +480,11 @@ compatible = "fsl,imx7ulp-lpi2c"; reg = <0x40a40000 0x10000>; interrupts = ; - clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>; - clock-names = "ipg"; + clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>, + <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; + clock-names = "per", "ipg"; assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; assigned-clock-rates = <48000000>; status = "disabled"; }; @@ -343,10 +493,11 @@ compatible = "fsl,imx7ulp-lpi2c"; reg = <0x40a50000 0x10000>; interrupts = ; - clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>; - clock-names = "ipg"; + clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>, + <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; + clock-names = "per", "ipg"; assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; assigned-clock-rates = <48000000>; status = "disabled"; }; @@ -358,8 +509,10 @@ clocks = <&pcc3 IMX7ULP_CLK_LPUART6>; clock-names = "ipg"; assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; assigned-clock-rates = <48000000>; + dmas = <&edma1 0 22>, <&edma1 0 21>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -370,8 +523,34 @@ clocks = <&pcc3 IMX7ULP_CLK_LPUART7>; clock-names = "ipg"; assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; assigned-clock-rates = <48000000>; + dmas = <&edma1 0 24>, <&edma1 0 23>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + mipi_dsi: mipi_dsi@40a90000 { + compatible = "fsl,imx7ulp-mipi-dsi"; + reg = <0x40a90000 0x1000>; + interrupts = ; + clocks = <&pcc3 IMX7ULP_CLK_DSI>; + clock-names = "mipi_dsi_clk"; + data-lanes-num = <2>; + phy-ref-clkfreq = <24000000>; + max-data-rate = <800000000>; + sim = <&sim>; + status = "disabled"; + }; + + lcdif: lcdif@40aa0000 { + compatible = "fsl,imx7ulp-lcdif"; + reg = <0x40aa0000 0x1000>; + interrupts = ; + clocks = <&scg1 IMX7ULP_CLK_DUMMY>, + <&pcc3 IMX7ULP_CLK_LCDIF>, + <&scg1 IMX7ULP_CLK_DUMMY>; + clock-names = "axi", "pix", "disp_axi"; status = "disabled"; }; @@ -441,6 +620,28 @@ clock-names = "gpio", "port"; gpio-ranges = <&iomuxc1 0 96 32>; }; + + gpu: gpu@41800000 { + compatible = "fsl,imx7ulp-gpu", "fsl,imx6q-gpu"; + reg = <0x41800000 0x80000>, <0x41880000 0x80000>, + <0x60000000 0x40000000>, <0x0 0x4000000>; + reg-names = "iobase_3d", "iobase_2d", + "phys_baseaddr", "contiguous_mem"; + interrupts = , + ; + interrupt-names = "irq_3d", "irq_2d"; + clocks = <&pcc3 IMX7ULP_CLK_GPU3D>, + <&scg1 IMX7ULP_CLK_DUMMY>, + <&scg1 IMX7ULP_CLK_GPU_DIV>, + <&pcc3 IMX7ULP_CLK_GPU2D>, + <&scg1 IMX7ULP_CLK_NIC1_DIV>; + clock-names = "gpu3d_clk", "gpu3d_shader_clk", + "gpu3d_axi_clk", "gpu2d_clk", + "gpu2d_axi_clk"; + assigned-clocks = <&scg1 IMX7ULP_CLK_APLL_PFD2>, <&pcc3 IMX7ULP_CLK_GPU3D>, <&pcc3 IMX7ULP_CLK_GPU2D>; + assigned-clock-parents = <0>, <&scg1 IMX7ULP_CLK_APLL_PFD2>, <&scg1 IMX7ULP_CLK_APLL_PFD2>; + assigned-clock-rates = <400000000>, <400000000>, <400000000>; + }; }; m4aips1: bus@41080000 { @@ -450,6 +651,11 @@ reg = <0x41080000 0x80000>; ranges; + pmc0: pmc0@410a1000 { + compatible = "fsl,imx7ulp-pmc0"; + reg = <0x410a1000 0x1000>; + }; + sim: sim@410a3000 { compatible = "fsl,imx7ulp-sim", "syscon"; reg = <0x410a3000 0x1000>; @@ -461,4 +667,27 @@ clocks = <&scg1 IMX7ULP_CLK_DUMMY>; }; }; + + rpmsg: rpmsg{ + compatible = "fsl,imx7ulp-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + status = "disabled"; + }; + + heartbeat-rpmsg { + compatible = "fsl,heartbeat-rpmsg"; + }; + + rtc-rpmsg { + compatible = "fsl,imx-rpmsg-rtc"; + }; + }; diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts index 74a67604876c83..ee718b5b7b0e10 100644 --- a/arch/arm/boot/dts/ls1021a-qds.dts +++ b/arch/arm/boot/dts/ls1021a-qds.dts @@ -126,6 +126,21 @@ }; }; +&qspi { + num-cs = <2>; + status = "okay"; + + qflash0: s25fl128s@0 { + compatible = "spansion,m25p80"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + &enet0 { tbi-handle = <&tbi0>; phy-handle = <&sgmii_phy1c>; @@ -150,6 +165,10 @@ status = "okay"; }; +&esdhc { + status = "okay"; +}; + &i2c0 { status = "okay"; diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts index 9b1fe99d55b1e6..0ca4ebfc030411 100644 --- a/arch/arm/boot/dts/ls1021a-twr.dts +++ b/arch/arm/boot/dts/ls1021a-twr.dts @@ -144,6 +144,21 @@ }; }; +&qspi { + num-cs = <2>; + status = "okay"; + + qflash0: n25q128a13@0 { + compatible = "n25q128a13", "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + &enet0 { tbi-handle = <&tbi0>; phy-handle = <&sgmii_phy2>; diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 5a8e58b6634207..3ba67beabacb22 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -66,6 +66,7 @@ serial4 = &lpuart4; serial5 = &lpuart5; sysclk = &sysclk; + rtc1 = &ftm_alarm0; }; cpus { @@ -167,12 +168,13 @@ ifc: ifc@1530000 { compatible = "fsl,ifc", "simple-bus"; reg = <0x0 0x1530000 0x0 0x10000>; + big-endian; interrupts = ; }; dcfg: dcfg@1ee0000 { compatible = "fsl,ls1021a-dcfg", "syscon"; - reg = <0x0 0x1ee0000 0x0 0x10000>; + reg = <0x0 0x1ee0000 0x0 0x1000>; big-endian; }; @@ -371,7 +373,7 @@ }; i2c0: i2c@2180000 { - compatible = "fsl,vf610-i2c"; + compatible = "fsl,vf610-i2c", "fsl,ls1021a-vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2180000 0x0 0x10000>; @@ -380,11 +382,12 @@ clocks = <&clockgen 4 1>; dma-names = "tx", "rx"; dmas = <&edma0 1 39>, <&edma0 1 38>; + fsl-scl-gpio = <&gpio3 23 0>; status = "disabled"; }; i2c1: i2c@2190000 { - compatible = "fsl,vf610-i2c"; + compatible = "fsl,vf610-i2c", "fsl,ls1021a-vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2190000 0x0 0x10000>; @@ -393,6 +396,7 @@ clocks = <&clockgen 4 1>; dma-names = "tx", "rx"; dmas = <&edma0 1 37>, <&edma0 1 36>; + fsl-scl-gpio = <&gpio3 23 0>; status = "disabled"; }; @@ -678,8 +682,9 @@ reg = <0x0 0x2b50000 0x0 0x10000>; interrupts = ; clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 47>, <&edma0 1 46>; @@ -692,8 +697,9 @@ reg = <0x0 0x2b60000 0x0 0x10000>; interrupts = ; clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 45>, <&edma0 1 44>; @@ -861,7 +867,10 @@ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; + usb3-lpm-capable; + snps,dis-u1u2-when-u3-quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; }; pcie@3400000 { @@ -869,7 +878,9 @@ reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; /* controller interrupt */ + interrupts = , + ; /* aer interrupt */ + interrupt-names = "pme", "aer"; fsl,pcie-scfg = <&scfg 0>; #address-cells = <3>; #size-cells = <2>; @@ -893,7 +904,9 @@ reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; + interrupts = , + ; /* aer interrupt */ + interrupt-names = "pme", "aer"; fsl,pcie-scfg = <&scfg 1>; #address-cells = <3>; #size-cells = <2>; @@ -983,5 +996,24 @@ big-endian; }; + rcpm: rcpm@1ee2140 { + compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+"; + reg = <0x0 0x1ee2140 0x0 0x8>; + #fsl,rcpm-wakeup-cells = <2>; + + /* + * The second and third entry compose an alt offset + * address for IPPDEXPCR1(SCFG_SPARECR8) + */ + fsl,ippdexpcr1-alt-addr = <&scfg 0x0 0x51c>; + }; + + ftm_alarm0: timer0@29d0000 { + compatible = "fsl,ls1021a-ftm-alarm"; + reg = <0x0 0x29d0000 0x0 0x10000>; + fsl,rcpm-wakeup = <&rcpm 0x0 0x20000000>; + interrupts = ; + big-endian; + }; }; }; diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index dabb8045324952..8233e5a4f6157b 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -2,7 +2,7 @@ CONFIG_KERNEL_LZO=y CONFIG_SYSVIPC=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_PREEMPT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=18 @@ -40,9 +40,6 @@ CONFIG_SOC_IMX6UL=y CONFIG_SOC_IMX7D=y CONFIG_SOC_IMX7ULP=y CONFIG_SOC_VF610=y -CONFIG_PCI=y -CONFIG_PCI_MSI=y -CONFIG_PCI_IMX6=y CONFIG_SMP=y CONFIG_ARM_PSCI=y CONFIG_HIGHMEM=y @@ -58,6 +55,7 @@ CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y CONFIG_CPUFREQ_DT=y CONFIG_ARM_IMX6Q_CPUFREQ=y CONFIG_ARM_IMX_CPUFREQ_DT=y +CONFIG_ARM_IMX7ULP_CPUFREQ=y CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y CONFIG_ARM_PSCI_CPUIDLE=y @@ -71,33 +69,47 @@ CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y # CONFIG_BLK_DEV_BSG is not set CONFIG_BINFMT_MISC=m +CONFIG_CMA=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_INET=y +CONFIG_IP_MULTICAST=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set CONFIG_NETFILTER=y +CONFIG_VLAN_8021Q=m +CONFIG_LLC2=y CONFIG_CAN=y CONFIG_CAN_FLEXCAN=y CONFIG_BT=y -CONFIG_BT_BNEP=m +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +CONFIG_BT_HCIBTUSB=y CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_BCSP=y CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_HCIVHCI=y +CONFIG_BT_MRVL=y +CONFIG_BT_MRVL_SDIO=y CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y CONFIG_CFG80211_WEXT=y CONFIG_MAC80211=y -CONFIG_RFKILL=y -CONFIG_RFKILL_INPUT=y +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_IMX6=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set CONFIG_FW_LOADER_USER_HELPER=y CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y -CONFIG_CMA_SIZE_MBYTES=64 CONFIG_IMX_WEIM=y CONFIG_CONNECTOR=y CONFIG_MTD=y @@ -108,16 +120,14 @@ CONFIG_MTD_JEDECPROBE=y CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_DATAFLASH=y -CONFIG_MTD_M25P80=y CONFIG_MTD_SST25L=y CONFIG_MTD_RAW_NAND=y CONFIG_MTD_NAND_GPMI_NAND=y CONFIG_MTD_NAND_VF610_NFC=y CONFIG_MTD_NAND_MXC=y CONFIG_MTD_SPI_NOR=y -CONFIG_SPI_FSL_QUADSPI=y +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set CONFIG_MTD_UBI=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_BLOCK=y @@ -163,9 +173,7 @@ CONFIG_USB_NET_CDC_EEM=m CONFIG_USB_NET_SMSC95XX=y CONFIG_USB_NET_MCS7830=y CONFIG_BRCMFMAC=m -CONFIG_MWIFIEX=m -CONFIG_MWIFIEX_SDIO=m -CONFIG_MWIFIEX_PCIE=m +CONFIG_HOSTAP=y CONFIG_WL12XX=m CONFIG_WL18XX=m CONFIG_WLCORE_SDIO=m @@ -173,6 +181,7 @@ CONFIG_WLCORE_SDIO=m CONFIG_INPUT_EVDEV=y CONFIG_INPUT_EVBUG=m CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_RPMSG=y CONFIG_KEYBOARD_SNVS_PWRKEY=y CONFIG_KEYBOARD_IMX=y CONFIG_MOUSE_PS2=m @@ -181,6 +190,8 @@ CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ADS7846=y CONFIG_TOUCHSCREEN_EGALAX=y CONFIG_TOUCHSCREEN_GOODIX=y +CONFIG_TOUCHSCREEN_ELAN_TS=y +CONFIG_TOUCHSCREEN_FTS=y CONFIG_TOUCHSCREEN_MAX11801=y CONFIG_TOUCHSCREEN_IMX6UL_TSC=y CONFIG_TOUCHSCREEN_EDT_FT5X06=y @@ -192,6 +203,8 @@ CONFIG_TOUCHSCREEN_SX8654=y CONFIG_TOUCHSCREEN_COLIBRI_VF50=y CONFIG_INPUT_MISC=y CONFIG_INPUT_MMA8450=y +CONFIG_INPUT_MPL3115=y +CONFIG_INPUT_ISL29023=y CONFIG_SERIO_SERPORT=m # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_IMX=y @@ -208,11 +221,19 @@ CONFIG_I2C_ALGOPCF=m CONFIG_I2C_ALGOPCA=m CONFIG_I2C_GPIO=y CONFIG_I2C_IMX=y +CONFIG_I2C_IMX_LPI2C=y CONFIG_SPI=y +CONFIG_SPI_FSL_QUADSPI=y +CONFIG_SPI_FSL_LPSPI=y CONFIG_SPI_GPIO=y CONFIG_SPI_IMX=y +CONFIG_SPI_SPIDEV=y CONFIG_SPI_FSL_DSPI=y +CONFIG_SPI_SLAVE=y +CONFIG_SPI_SLAVE_TIME=y +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_IMX_RPMSG=y CONFIG_GPIO_SIOX=m CONFIG_GPIO_MAX732X=y CONFIG_GPIO_MC9S08DZ60=y @@ -224,24 +245,35 @@ CONFIG_POWER_RESET=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_SYSCON_POWEROFF=y CONFIG_POWER_SUPPLY=y +CONFIG_SABRESD_MAX8903=y +CONFIG_SENSORS_FXOS8700=y +CONFIG_SENSORS_FXAS2100X=y +CONFIG_SENSOR_FXLS8471=y +CONFIG_SENSOR_IMX_RPMSG=y CONFIG_SENSORS_MC13783_ADC=y CONFIG_SENSORS_GPIO_FAN=y +CONFIG_SENSORS_MAX17135=y CONFIG_SENSORS_IIO_HWMON=y +CONFIG_THERMAL=y CONFIG_THERMAL_STATISTICS=y CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_CPU_THERMAL=y CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y CONFIG_WATCHDOG=y -CONFIG_DA9062_WATCHDOG=y CONFIG_DA9063_WATCHDOG=m +CONFIG_DA9062_WATCHDOG=y CONFIG_RN5T618_WATCHDOG=y CONFIG_IMX2_WDT=y +CONFIG_IMX7ULP_WDT=y CONFIG_MFD_DA9052_I2C=y CONFIG_MFD_DA9062=y CONFIG_MFD_DA9063=y CONFIG_MFD_MC13XXX_SPI=y CONFIG_MFD_MC13XXX_I2C=y +CONFIG_MFD_MAX17135=y CONFIG_MFD_RN5T618=y +CONFIG_MFD_SI476X_CORE=y CONFIG_MFD_STMPE=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y @@ -250,8 +282,10 @@ CONFIG_REGULATOR_DA9052=y CONFIG_REGULATOR_DA9062=y CONFIG_REGULATOR_DA9063=y CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_MAX17135=y CONFIG_REGULATOR_MC13783=y CONFIG_REGULATOR_MC13892=y +CONFIG_REGULATOR_PF1550_RPMSG=y CONFIG_REGULATOR_PFUZE100=y CONFIG_REGULATOR_RN5T618=y CONFIG_RC_CORE=y @@ -259,37 +293,54 @@ CONFIG_RC_DEVICES=y CONFIG_IR_GPIO_CIR=y CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y CONFIG_MEDIA_CONTROLLER=y CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_MEDIA_USB_SUPPORT=y CONFIG_USB_VIDEO_CLASS=m CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_VIDEO_MUX=y -CONFIG_SOC_CAMERA=y +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_CAPTURE=m +CONFIG_VIDEO_MXC_CSI_CAMERA=m +CONFIG_MXC_VADC=m +CONFIG_MXC_MIPI_CSI=m +CONFIG_MXC_CAMERA_OV5640=m +CONFIG_MXC_CAMERA_OV5640_V2=m +CONFIG_MXC_CAMERA_OV5640_MIPI=m +CONFIG_MXC_CAMERA_OV5640_MIPI_V2=m +CONFIG_MXC_TVIN_ADV7180=m +CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +CONFIG_VIDEO_MXC_PXP_V4L2=y CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_CODA=m CONFIG_VIDEO_IMX_PXP=y -# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set CONFIG_VIDEO_ADV7180=m CONFIG_VIDEO_OV2680=m -CONFIG_VIDEO_OV5640=m CONFIG_VIDEO_OV5645=m -CONFIG_IMX_IPUV3_CORE=y +CONFIG_RADIO_SI476X=y CONFIG_DRM=y CONFIG_DRM_MSM=y CONFIG_DRM_PANEL_LVDS=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_SEIKO_43WVF1G=y -CONFIG_DRM_DW_HDMI_AHB_AUDIO=m -CONFIG_DRM_DW_HDMI_CEC=y -CONFIG_DRM_IMX=y -CONFIG_DRM_IMX_PARALLEL_DISPLAY=y -CONFIG_DRM_IMX_TVE=y -CONFIG_DRM_IMX_LDB=y -CONFIG_DRM_IMX_HDMI=y -CONFIG_DRM_ETNAVIV=y -CONFIG_DRM_MXSFB=y -CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_MXS=y +CONFIG_FB_MXC_EINK_PANEL=y +CONFIG_FB_MXC_EINK_V2_PANEL=y +CONFIG_FB_MXC_MIPI_DSI=y +CONFIG_FB_MXC_MIPI_DSI_NORTHWEST=y +CONFIG_FB_MXC_MIPI_DSI_SAMSUNG=y +CONFIG_FB_MXC_ADV7535=y +CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y +CONFIG_FB_MXC_TRULY_PANEL_TFT3P5581E=y +CONFIG_FB_MXC_RK_PANEL_RK055AHD042=y +CONFIG_FB_MXC_RK_PANEL_RK055IQH042=y +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_FB_MXC_LDB=y +CONFIG_FB_MXC_HDMI=y +CONFIG_FB_MXS_SII902X=y +CONFIG_FB_MXC_DCIC=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y CONFIG_LCD_PLATFORM=y @@ -301,26 +352,31 @@ CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_USB_AUDIO=m CONFIG_SND_SOC=y -CONFIG_SND_SOC_FSL_ASRC=y CONFIG_SND_IMX_SOC=y CONFIG_SND_SOC_PHYCORE_AC97=y CONFIG_SND_SOC_EUKREA_TLV320=y +CONFIG_SND_SOC_IMX_WM8960=y +CONFIG_SND_SOC_IMX_SII902X=y +CONFIG_SND_SOC_IMX_WM8958=y +CONFIG_SND_SOC_IMX_CS42888=y +CONFIG_SND_SOC_IMX_WM8962=y +CONFIG_SND_SOC_IMX_RPMSG=y CONFIG_SND_SOC_IMX_ES8328=y CONFIG_SND_SOC_IMX_SGTL5000=y +CONFIG_SND_SOC_IMX_MQS=y CONFIG_SND_SOC_IMX_SPDIF=y CONFIG_SND_SOC_IMX_MC13783=y -CONFIG_SND_SOC_FSL_ASOC_CARD=y +CONFIG_SND_SOC_IMX_SI476X=y +CONFIG_SND_SOC_IMX_HDMI=y CONFIG_SND_SOC_AC97_CODEC=y -CONFIG_SND_SOC_CS42XX8_I2C=y CONFIG_SND_SOC_TLV320AIC3X=y -CONFIG_SND_SOC_WM8960=y -CONFIG_SND_SOC_WM8962=y CONFIG_SND_SIMPLE_CARD=y CONFIG_HID_MULTITOUCH=y CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_MXC=y +CONFIG_USB_ACM=m CONFIG_USB_STORAGE=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_UDC=y @@ -335,7 +391,7 @@ CONFIG_NOP_USB_XCEIV=y CONFIG_USB_MXS_PHY=y CONFIG_USB_GADGET=y CONFIG_USB_FSL_USB2=y -CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS=y CONFIG_USB_CONFIGFS_SERIAL=y CONFIG_USB_CONFIGFS_ACM=y CONFIG_USB_CONFIGFS_OBEX=y @@ -365,6 +421,8 @@ CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MXC_SIM=y +CONFIG_MXC_SIMv2=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y @@ -388,26 +446,29 @@ CONFIG_RTC_DRV_MC13XXX=y CONFIG_RTC_DRV_MXC=y CONFIG_RTC_DRV_MXC_V2=y CONFIG_RTC_DRV_SNVS=y +CONFIG_RTC_DRV_IMX_RPMSG=y CONFIG_DMADEVICES=y CONFIG_FSL_EDMA=y CONFIG_IMX_SDMA=y CONFIG_MXS_DMA=y +CONFIG_MXC_PXP_V2=y +CONFIG_MXC_PXP_V3=y CONFIG_DMATEST=m CONFIG_STAGING=y CONFIG_STAGING_MEDIA=y -CONFIG_VIDEO_IMX_MEDIA=y CONFIG_COMMON_CLK_PWM=y CONFIG_IIO=y -CONFIG_MMA8452=y CONFIG_IMX7D_ADC=y CONFIG_VF610_ADC=y -CONFIG_SENSORS_ISL29018=y -CONFIG_MAG3110=y -CONFIG_MPL3115=y +CONFIG_SENSORS_MAG3110=y CONFIG_PWM=y CONFIG_PWM_FSL_FTM=y CONFIG_PWM_IMX27=y CONFIG_PWM_IMX_TPM=y +CONFIG_PHY_MIXEL_LVDS=y +CONFIG_PHY_MIXEL_LVDS_COMBO=y +CONFIG_MAILBOX=y +CONFIG_IMX_MBOX=y CONFIG_NVMEM_IMX_OCOTP=y CONFIG_NVMEM_VF610_OCOTP=y CONFIG_NVMEM_SNVS_LPGPR=y @@ -416,6 +477,11 @@ CONFIG_OPTEE=y CONFIG_MUX_MMIO=y CONFIG_SIOX=m CONFIG_SIOX_BUS_GPIO=m +CONFIG_MXC_IPU=y +CONFIG_MXC_IPU_V3_PRE=y +CONFIG_MXC_MLB150=y +CONFIG_MXC_MIPI_CSI2=y +CONFIG_MXC_HDMI_CEC=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y @@ -434,6 +500,7 @@ CONFIG_ZISOFS=y CONFIG_UDF_FS=m CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=y +CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_JFFS2_FS=y CONFIG_UBIFS_FS=y @@ -448,13 +515,40 @@ CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_15=m CONFIG_NLS_UTF8=y CONFIG_SECURITYFS=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_ECHAINIV=m +CONFIG_CRYPTO_TLS=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y CONFIG_CRYPTO_DEV_SAHARA=y CONFIG_CRYPTO_DEV_MXS_DCP=y CONFIG_CRC_CCITT=m CONFIG_CRC_T10DIF=y CONFIG_CRC7=m CONFIG_LIBCRC32C=m +CONFIG_DMA_CMA=y CONFIG_FONTS=y CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig new file mode 100644 index 00000000000000..30792d23507251 --- /dev/null +++ b/arch/arm/configs/imx_v7_defconfig @@ -0,0 +1,579 @@ +CONFIG_KERNEL_LZO=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_MEMCG=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_DEVICE=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_KALLSYMS_ALL=y +CONFIG_PERF_EVENTS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_ARCH_MXC=y +CONFIG_SOC_IMX50=y +CONFIG_SOC_IMX51=y +CONFIG_SOC_IMX53=y +CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +CONFIG_SOC_IMX6SLL=y +CONFIG_SOC_IMX6SX=y +CONFIG_SOC_IMX6UL=y +CONFIG_SOC_IMX7D=y +CONFIG_SOC_IMX7ULP=y +CONFIG_SOC_VF610=y +CONFIG_SMP=y +CONFIG_VMSPLIT_2G=y +CONFIG_ARM_PSCI=y +CONFIG_HIGHMEM=y +CONFIG_FORCE_MAX_ZONEORDER=14 +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_KEXEC=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_ARM_IMX_CPUFREQ_DT=y +CONFIG_ARM_IMX7ULP_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_ARM_CPUIDLE=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_BINFMT_MISC=m +CONFIG_CMA=y +CONFIG_SECCOMP=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_NETFILTER=y +CONFIG_VLAN_8021Q=m +CONFIG_LLC2=y +CONFIG_CAN=y +CONFIG_CAN_FLEXCAN=y +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +CONFIG_BT_HCIBTUSB=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_HCIVHCI=y +CONFIG_BT_MRVL=y +CONFIG_BT_MRVL_SDIO=y +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=y +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_IMX6=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y +CONFIG_IMX_WEIM=y +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_NAND_GPMI_NAND=y +CONFIG_MTD_NAND_VF610_NFC=y +CONFIG_MTD_NAND_MXC=y +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_BLOCK=y +CONFIG_OF_OVERLAY=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_SENSORS_FXOS8700=y +CONFIG_SENSORS_FXAS2100X=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +CONFIG_PATA_IMX=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_BROADCOM is not set +CONFIG_CS89x0=y +CONFIG_CS89x0_PLATFORM=y +# CONFIG_NET_VENDOR_FARADAY is not set +CONFIG_E1000E=y +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_SMC91X=y +CONFIG_SMC911X=y +CONFIG_SMSC911X=y +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_AT803X_PHY=y +CONFIG_MICREL_PHY=y +CONFIG_SMSC_PHY=y +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=y +CONFIG_USB_LAN78XX=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_SMSC95XX=y +CONFIG_USB_NET_MCS7830=y +CONFIG_BRCMFMAC=m +CONFIG_HOSTAP=y +CONFIG_MXMWIFIEX=m +CONFIG_WL12XX=m +CONFIG_WL18XX=m +CONFIG_WLCORE_SDIO=m +# CONFIG_WILINK_PLATFORM_DATA is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=m +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_RPMSG=y +CONFIG_KEYBOARD_IMX=y +CONFIG_MOUSE_PS2=m +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=y +CONFIG_TOUCHSCREEN_EGALAX=y +CONFIG_TOUCHSCREEN_ELAN_TS=y +CONFIG_TOUCHSCREEN_GOODIX=y +CONFIG_TOUCHSCREEN_MAX11801=y +CONFIG_TOUCHSCREEN_IMX6UL_TSC=y +CONFIG_TOUCHSCREEN_EDT_FT5X06=y +CONFIG_TOUCHSCREEN_MC13783=y +CONFIG_TOUCHSCREEN_TSC2004=y +CONFIG_TOUCHSCREEN_TSC2007=y +CONFIG_TOUCHSCREEN_STMPE=y +CONFIG_TOUCHSCREEN_SX8654=y +CONFIG_TOUCHSCREEN_COLIBRI_VF50=y +CONFIG_TOUCHSCREEN_FTS=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_MMA8450=y +CONFIG_INPUT_MPL3115=y +CONFIG_SENSOR_FXLS8471=y +CONFIG_SENSOR_IMX_RPMSG=y +CONFIG_INPUT_ISL29023=y +CONFIG_SERIO_SERPORT=m +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_GPIO=y +CONFIG_I2C_IMX=y +CONFIG_I2C_IMX_LPI2C=y +CONFIG_SPI=y +CONFIG_SPI_FSL_LPSPI=y +CONFIG_SPI_FSL_QUADSPI=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_IMX=y +CONFIG_SPI_FSL_DSPI=y +CONFIG_SPI_SPIDEV=y +CONFIG_SPI_SLAVE=y +CONFIG_SPI_SLAVE_TIME=y +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_SIOX=m +CONFIG_GPIO_IMX_RPMSG=y +CONFIG_GPIO_MAX732X=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCF857X=y +CONFIG_GPIO_STMPE=y +CONFIG_GPIO_74X164=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_POWER_SUPPLY=y +CONFIG_SABRESD_MAX8903=y +CONFIG_SENSORS_MC13783_ADC=y +CONFIG_SENSORS_GPIO_FAN=y +CONFIG_SENSORS_IIO_HWMON=y +CONFIG_SENSORS_MAX17135=y +CONFIG_SENSORS_MAG3110=y +CONFIG_THERMAL=y +CONFIG_THERMAL_STATISTICS=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_DA9063_WATCHDOG=m +CONFIG_DA9062_WATCHDOG=y +CONFIG_RN5T618_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_IMX7ULP_WDT=y +CONFIG_MFD_DA9052_I2C=y +CONFIG_MFD_DA9062=y +CONFIG_MFD_DA9063=y +CONFIG_MFD_MC13XXX_SPI=y +CONFIG_MFD_MC13XXX_I2C=y +CONFIG_MFD_MAX17135=y +CONFIG_MFD_RN5T618=y +CONFIG_MFD_SI476X_CORE=y +CONFIG_MFD_STMPE=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_REGULATOR_DA9052=y +CONFIG_REGULATOR_DA9062=y +CONFIG_REGULATOR_DA9063=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_MAX17135=y +CONFIG_REGULATOR_MC13783=y +CONFIG_REGULATOR_MC13892=y +CONFIG_REGULATOR_PF1550_RPMSG=y +CONFIG_REGULATOR_PFUZE100=y +CONFIG_REGULATOR_RN5T618=y +CONFIG_RC_CORE=y +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MUX=y +CONFIG_VIDEO_MXC_CAPTURE=m +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_CSI_CAMERA=m +CONFIG_MXC_VADC=m +CONFIG_MXC_MIPI_CSI=m +CONFIG_MXC_CAMERA_OV5640=m +CONFIG_MXC_CAMERA_OV5640_V2=m +CONFIG_MXC_CAMERA_OV5640_MIPI=m +CONFIG_MXC_CAMERA_OV5640_MIPI_V2=m +CONFIG_MXC_TVIN_ADV7180=m +CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +CONFIG_VIDEO_MXC_PXP_V4L2=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_CODA=m +CONFIG_VIDEO_IMX_PXP=y +CONFIG_RADIO_SI476X=y +CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_OV2680=m +CONFIG_VIDEO_OV5645=m +CONFIG_DRM=y +CONFIG_DRM_MSM=y +CONFIG_DRM_PANEL_LVDS=y +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_PANEL_SEIKO_43WVF1G=y +CONFIG_FB_MXS=y +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_FB_MXC_OVERLAY=y +CONFIG_FB_MXC_MIPI_DSI_NORTHWEST=y +CONFIG_FB_MXC_ADV7535=y +CONFIG_FB_MXC_TRULY_PANEL_TFT3P5581E=y +CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y +CONFIG_FB_MXC_RK_PANEL_RK055AHD042=y +CONFIG_FB_MXC_RK_PANEL_RK055IQH042=y +CONFIG_FB_MXC_MIPI_DSI_SAMSUNG=y +CONFIG_FB_MXC_MIPI_DSI=y +CONFIG_FB_MXC_LDB=y +CONFIG_FB_MXC_EINK_PANEL=y +CONFIG_FB_MXC_EINK_V2_PANEL=y +CONFIG_FB_MXC_HDMI=y +CONFIG_FB_MXS_SII902X=y +CONFIG_FB_MXC_DCIC=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_L4F00242T03=y +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_SOC=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_EUKREA_TLV320=y +CONFIG_SND_SOC_IMX_WM8960=y +CONFIG_SND_SOC_IMX_SII902X=y +CONFIG_SND_SOC_IMX_WM8958=y +CONFIG_SND_SOC_IMX_CS42888=y +CONFIG_SND_SOC_IMX_WM8962=y +CONFIG_SND_SOC_IMX_RPMSG=y +CONFIG_SND_SOC_IMX_ES8328=y +CONFIG_SND_SOC_IMX_SGTL5000=y +CONFIG_SND_SOC_IMX_MQS=y +CONFIG_SND_SOC_IMX_SPDIF=y +CONFIG_SND_SOC_IMX_MC13783=y +CONFIG_SND_SOC_IMX_SI476X=y +CONFIG_SND_SOC_IMX_HDMI=y +CONFIG_SND_SOC_AC97_CODEC=y +CONFIG_SND_SOC_TLV320AIC3X=y +CONFIG_SND_SIMPLE_CARD=y +CONFIG_HID_MULTITOUCH=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_OTG_WHITELIST=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MXC=y +CONFIG_USB_HCD_TEST_MODE=y +CONFIG_USB_ACM=m +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_TEST=m +CONFIG_USB_EHSET_TEST_FIXTURE=m +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_FSL_USB2=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_CONFIGFS_F_PRINTER=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_USB_ETH=m +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_ISL1208=y +CONFIG_RTC_DRV_PCF8523=y +CONFIG_RTC_DRV_PCF8563=y +CONFIG_RTC_DRV_M41T80=y +CONFIG_RTC_DRV_DA9063=y +CONFIG_RTC_DRV_MC13XXX=y +CONFIG_RTC_DRV_MXC=y +CONFIG_RTC_DRV_MXC_V2=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_RTC_DRV_IMX_RPMSG=y +CONFIG_DMADEVICES=y +CONFIG_FSL_EDMA=y +CONFIG_IMX_SDMA=y +CONFIG_MXS_DMA=y +CONFIG_MXC_PXP_V2=y +CONFIG_MXC_PXP_V3=y +CONFIG_DMATEST=m +CONFIG_STAGING=y +CONFIG_STAGING_MEDIA=y +CONFIG_COMMON_CLK_PWM=y +CONFIG_MAILBOX=y +CONFIG_IMX_MBOX=y +CONFIG_REMOTEPROC=y +CONFIG_IMX_REMOTEPROC=y +CONFIG_EXTCON_USB_GPIO=y +CONFIG_IIO=y +CONFIG_IMX7D_ADC=y +CONFIG_VF610_ADC=y +CONFIG_PWM=y +CONFIG_PWM_FSL_FTM=y +CONFIG_PWM_IMX27=y +CONFIG_PWM_IMX_TPM=y +CONFIG_PHY_MIXEL_LVDS=y +CONFIG_PHY_MIXEL_LVDS_COMBO=y +CONFIG_NVMEM_IMX_OCOTP=y +CONFIG_NVMEM_VF610_OCOTP=y +CONFIG_NVMEM_SNVS_LPGPR=y +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_MUX_MMIO=y +CONFIG_SIOX=m +CONFIG_SIOX_BUS_GPIO=m +CONFIG_MXC_SIM=y +CONFIG_MXC_IPU=y +CONFIG_MXC_SIMv2=y +CONFIG_MXC_MLB150=y +CONFIG_MXC_IPU_V3_PRE=y +CONFIG_MXC_HDMI_CEC=y +CONFIG_MXC_MIPI_CSI2=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_OVERLAY_FS=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_UTF8=y +CONFIG_SECURITYFS=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_ECHAINIV=m +CONFIG_CRYPTO_TLS=m +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y +CONFIG_CRYPTO_DEV_SAHARA=y +CONFIG_CRYPTO_DEV_MXS_DCP=y +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_STREEBOG=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRC_CCITT=m +CONFIG_CRC_T10DIF=y +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +CONFIG_DMA_CMA=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set diff --git a/arch/arm/configs/lsdk.config b/arch/arm/configs/lsdk.config new file mode 100644 index 00000000000000..0a21b724367bf0 --- /dev/null +++ b/arch/arm/configs/lsdk.config @@ -0,0 +1,88 @@ +# general +CONFIG_ARM_MODULE_PLTS=y +CONFIG_CHECKPOINT_RESTORE=y + +# virtualization +CONFIG_KVM=y +CONFIG_KVM_ARM_MAX_VCPUS=8 +CONFIG_VHOST_NET=y +CONFIG_BRIDGE=y +CONFIG_TUN=y + +# containers +CONFIG_UNIX_DIAG=y +CONFIG_PACKET_DIAG=y +CONFIG_NETLINK_DIAG=y +CONFIG_OVERLAY_FS=y + +# network and misc +CONFIG_INET_ESP=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_VETH=y +CONFIG_NETFILTER=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_NAT_IPV4=y +CONFIG_NF_NAT_IPV6=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP6_NF_TARGET_MASQUERADE=y +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=y +CONFIG_MACVLAN=y +CONFIG_MACVTAP=y +CONFIG_VLAN_8021Q=y + +# namespaces +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y + +# cgroups +CONFIG_CPUSETS=y +CGROUP_DEVICE=y +CGROUP_SCHED=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_MEMCG=y +CONFIG_CGROUP_FREEZER=y + +# iptables +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_IP_NF_FILTER=y +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y +CONFIG_IP_VS=y +CONFIG_NETFILTER_XT_MATCH_IPVS=y +CONFIG_POSIX_MQUEUE=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_NAT=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_MASQUERADE=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y + +# filesystems +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_FUSE_FS=y + +# /proc/config.gz +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y + +# disable unneeded options and override default options set by defconfig to deduce the size of modules +# CONFIG_DRM_TEGRA is not set +# CONFIG_DRM_EXYNOS is not set +# CONFIG_DRM_MSM is not set +# CONFIG_DRM_VC4 is not set +# CONFIG_DRM_ROCKCHIP is not set +# CONFIG_DRM_RCAR_DU is not set +# CONFIG_USB_RENESAS_USBHS is not set +# CONFIG_TEGRA_HOST1X is not set +# CONFIG_SND_SOC_ROCKCHIP is not set diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index e4c8def9a0a578..930c662b761a21 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -128,8 +128,8 @@ CONFIG_CRYPTO_AES_ARM_CE=m CONFIG_CRYPTO_GHASH_ARM_CE=m CONFIG_CRYPTO_CRC32_ARM_CE=m CONFIG_CRYPTO_CHACHA20_NEON=m -CONFIG_GCC_PLUGINS=y -CONFIG_GCC_PLUGIN_STRUCTLEAK=y +CONFIG_VIRTUALIZATION=y +CONFIG_VHOST_NET=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_PARTITION_ADVANCED=y @@ -174,7 +174,7 @@ CONFIG_PCI_TEGRA=y CONFIG_PCI_RCAR_GEN2=y CONFIG_PCIE_RCAR=y CONFIG_PCI_DRA7XX_EP=y -CONFIG_PCI_KEYSTONE=y +CONFIG_PCI_LAYERSCAPE=y CONFIG_PCI_ENDPOINT=y CONFIG_PCI_ENDPOINT_CONFIGFS=y CONFIG_PCI_EPF_TEST=m @@ -186,18 +186,24 @@ CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP_OF=y -CONFIG_MTD_M25P80=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_SST25L=y CONFIG_MTD_RAW_NAND=y CONFIG_MTD_NAND_DENALI_DT=y CONFIG_MTD_NAND_OMAP2=y CONFIG_MTD_NAND_OMAP_BCH=y CONFIG_MTD_NAND_ATMEL=y CONFIG_MTD_NAND_MARVELL=y -CONFIG_MTD_NAND_GPMI_NAND=y CONFIG_MTD_NAND_BRCMNAND=y +CONFIG_MTD_NAND_GPMI_NAND=y +CONFIG_MTD_NAND_FSL_IFC=y CONFIG_MTD_NAND_VF610_NFC=y CONFIG_MTD_NAND_DAVINCI=y CONFIG_MTD_NAND_STM32_FMC2=y @@ -220,6 +226,7 @@ CONFIG_PCI_ENDPOINT_TEST=m CONFIG_EEPROM_AT24=y CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=y CONFIG_ATA=y CONFIG_SATA_AHCI=y CONFIG_SATA_AHCI_PLATFORM=y @@ -229,6 +236,8 @@ CONFIG_AHCI_ST=y CONFIG_AHCI_IMX=y CONFIG_AHCI_SUNXI=y CONFIG_AHCI_TEGRA=y +CONFIG_AHCI_QORIQ=y +CONFIG_SATA_SIL24=y CONFIG_SATA_HIGHBANK=y CONFIG_SATA_MV=y CONFIG_SATA_RCAR=y @@ -244,7 +253,9 @@ CONFIG_BGMAC_BCMA=y CONFIG_SYSTEMPORT=m CONFIG_MACB=y CONFIG_NET_CALXEDA_XGMAC=y +CONFIG_FSL_XGMAC_MDIO=y CONFIG_GIANFAR=y +CONFIG_FSL_SDK_DPAA_ETH=y CONFIG_HIX5HD2_GMAC=y CONFIG_E1000E=y CONFIG_IGB=y @@ -260,13 +271,16 @@ CONFIG_STMMAC_ETH=y CONFIG_DWMAC_DWC_QOS_ETH=y CONFIG_TI_CPSW=y CONFIG_XILINX_EMACLITE=y +CONFIG_AQUANTIA_PHY=y CONFIG_AT803X_PHY=y CONFIG_BROADCOM_PHY=y CONFIG_ICPLUS_PHY=y CONFIG_MARVELL_PHY=y CONFIG_MICREL_PHY=y +CONFIG_NATIONAL_PHY=y CONFIG_ROCKCHIP_PHY=y CONFIG_SMSC_PHY=y +CONFIG_VITESSE_PHY=y CONFIG_USB_PEGASUS=y CONFIG_USB_RTL8152=m CONFIG_USB_LAN78XX=m @@ -467,8 +481,8 @@ CONFIG_BATTERY_BQ27XXX=m CONFIG_AXP20X_POWER=m CONFIG_BATTERY_MAX17040=m CONFIG_BATTERY_MAX17042=m -CONFIG_CHARGER_GPIO=m CONFIG_CHARGER_CPCAP=m +CONFIG_CHARGER_GPIO=m CONFIG_CHARGER_MAX14577=m CONFIG_CHARGER_MAX77693=m CONFIG_CHARGER_MAX8997=m @@ -491,7 +505,6 @@ CONFIG_BCM2835_THERMAL=m CONFIG_BRCMSTB_THERMAL=m CONFIG_ST_THERMAL_MEMMAP=y CONFIG_UNIPHIER_THERMAL=y -CONFIG_WATCHDOG=y CONFIG_DA9063_WATCHDOG=m CONFIG_XILINX_WATCHDOG=y CONFIG_ARM_SP805_WATCHDOG=y @@ -525,10 +538,6 @@ CONFIG_MFD_BCM590XX=y CONFIG_MFD_AC100=y CONFIG_MFD_AXP20X_I2C=y CONFIG_MFD_AXP20X_RSB=y -CONFIG_MFD_CROS_EC=m -CONFIG_CROS_EC_I2C=m -CONFIG_CROS_EC_SPI=m -CONFIG_MFD_CROS_EC_CHARDEV=m CONFIG_MFD_DA9063=m CONFIG_MFD_MAX14577=y CONFIG_MFD_MAX77686=y @@ -628,7 +637,6 @@ CONFIG_V4L_TEST_DRIVERS=y CONFIG_VIDEO_VIVID=m CONFIG_CEC_PLATFORM_DRIVERS=y CONFIG_VIDEO_SAMSUNG_S5P_CEC=m -# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set CONFIG_VIDEO_ADV7180=m CONFIG_VIDEO_ML86V7667=m CONFIG_DRM=y @@ -677,16 +685,17 @@ CONFIG_DRM_PL111=m CONFIG_DRM_LIMA=m CONFIG_DRM_PANFROST=m CONFIG_DRM_ASPEED_GFX=m +CONFIG_FB_ARMCLCD=y CONFIG_FB_EFI=y CONFIG_FB_WM8505=y CONFIG_FB_SH_MOBILE_LCDC=y CONFIG_FB_SIMPLE=y -CONFIG_LCD_PLATFORM=m CONFIG_BACKLIGHT_PWM=y CONFIG_BACKLIGHT_AS3711=y CONFIG_BACKLIGHT_GPIO=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_LOGO=y CONFIG_SOUND=m CONFIG_SND=m CONFIG_SND_HDA_TEGRA=m @@ -871,6 +880,7 @@ CONFIG_RTC_DRV_S35390A=m CONFIG_RTC_DRV_RX8581=m CONFIG_RTC_DRV_EM3027=y CONFIG_RTC_DRV_S5M=m +CONFIG_RTC_DRV_DS3232=y CONFIG_RTC_DRV_DA9063=m CONFIG_RTC_DRV_EFI=m CONFIG_RTC_DRV_DIGICOLOR=m @@ -919,6 +929,10 @@ CONFIG_SERIO_NVEC_PS2=y CONFIG_NVEC_POWER=y CONFIG_NVEC_PAZ00=y CONFIG_STAGING_BOARD=y +CONFIG_FSL_SDK_DPA=y +CONFIG_MFD_CROS_EC=m +CONFIG_CROS_EC_I2C=m +CONFIG_CROS_EC_SPI=m CONFIG_COMMON_CLK_MAX77686=y CONFIG_COMMON_CLK_RK808=m CONFIG_COMMON_CLK_S2MPS11=m @@ -978,16 +992,15 @@ CONFIG_BERLIN2_ADC=m CONFIG_CPCAP_ADC=m CONFIG_EXYNOS_ADC=m CONFIG_MESON_SARADC=m +CONFIG_ROCKCHIP_SARADC=m CONFIG_STM32_ADC_CORE=m CONFIG_STM32_ADC=m CONFIG_STM32_DFSDM_ADC=m CONFIG_VF610_ADC=m CONFIG_XILINX_XADC=y -CONFIG_STM32_LPTIMER_CNT=m -CONFIG_STM32_DAC=m -CONFIG_ROCKCHIP_SARADC=m CONFIG_IIO_CROS_EC_SENSORS_CORE=m CONFIG_IIO_CROS_EC_SENSORS=m +CONFIG_STM32_DAC=m CONFIG_MPU3050_I2C=y CONFIG_CM36651=m CONFIG_IIO_CROS_EC_LIGHT_PROX=m @@ -1036,11 +1049,11 @@ CONFIG_PHY_DM816X_USB=m CONFIG_OMAP_USB2=y CONFIG_TI_PIPE3=y CONFIG_TWL4030_USB=m -CONFIG_MESON_MX_EFUSE=m -CONFIG_ROCKCHIP_EFUSE=m CONFIG_NVMEM_IMX_OCOTP=y +CONFIG_ROCKCHIP_EFUSE=m CONFIG_NVMEM_SUNXI_SID=y CONFIG_NVMEM_VF610_OCOTP=y +CONFIG_MESON_MX_EFUSE=m CONFIG_EXT4_FS=y CONFIG_AUTOFS4_FS=y CONFIG_MSDOS_FS=y @@ -1068,6 +1081,7 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=m CONFIG_CRYPTO_USER_API_RNG=m CONFIG_CRYPTO_USER_API_AEAD=m CONFIG_CRYPTO_DEV_MARVELL_CESA=m +CONFIG_CRYPTO_DEV_FSL_CAAM=m CONFIG_CRYPTO_DEV_EXYNOS_RNG=m CONFIG_CRYPTO_DEV_S5P=m CONFIG_CRYPTO_DEV_ATMEL_AES=m diff --git a/arch/arm/configs/multi_v7_lpae.config b/arch/arm/configs/multi_v7_lpae.config new file mode 100644 index 00000000000000..cd13d2df5fd597 --- /dev/null +++ b/arch/arm/configs/multi_v7_lpae.config @@ -0,0 +1,2 @@ +# Support for the Large Physical Address Extension +CONFIG_ARM_LPAE=y diff --git a/arch/arm/configs/multi_v8.config b/arch/arm/configs/multi_v8.config new file mode 100644 index 00000000000000..2203dabebc4402 --- /dev/null +++ b/arch/arm/configs/multi_v8.config @@ -0,0 +1,23 @@ +# ppfe +CONFIG_FSL_PPFE=y +CONFIG_FSL_PPFE_UTIL_DISABLED=y +# DPAA 1 +CONFIG_HAS_FSL_QBMAN=y +# network +CONFIG_BRIDGE=m +CONFIG_MACVLAN=y +CONFIG_FSL_SDK_FMAN=y +CONFIG_FMAN_ARM=y +CONFIG_FSL_SDK_DPAA_ETH=y +# mdio +CONFIG_FSL_XGMAC_MDIO=y +CONFIG_MDIO_BUS_MUX_MMIOREG=y +# phy +CONFIG_AQUANTIA_PHY=y +CONFIG_VITESSE_PHY=y +# NVMe +CONFIG_BLK_DEV_NVME=y +# vfio +CONFIG_VFIO=y +CONFIG_VFIO_PCI=y +CONFIG_VFIO_FSL_MC=y diff --git a/arch/arm/include/asm/delay.h b/arch/arm/include/asm/delay.h index 4f80b72372b416..f1aebe735321be 100644 --- a/arch/arm/include/asm/delay.h +++ b/arch/arm/include/asm/delay.h @@ -85,6 +85,22 @@ extern void __bad_udelay(void); __const_udelay((n) * UDELAY_MULT)) : \ __udelay(n)) +#define spin_event_timeout(condition, timeout, delay) \ +({ \ + typeof(condition) __ret; \ + int i = 0; \ + while (!(__ret = (condition)) && (i++ < timeout)) { \ + if (delay) \ + udelay(delay); \ + else \ + cpu_relax(); \ + udelay(1); \ + } \ + if (!__ret) \ + __ret = (condition); \ + __ret; \ +}) + /* Loop-based definitions for assembly code. */ extern void __loop_delay(unsigned long loops); extern void __loop_udelay(unsigned long usecs); diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 7a0596fcb2e77e..b026d499e42d8e 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -123,6 +123,7 @@ static inline u32 __raw_readl(const volatile void __iomem *addr) #define MT_DEVICE_NONSHARED 1 #define MT_DEVICE_CACHED 2 #define MT_DEVICE_WC 3 +#define MT_MEMORY_RW_NS 4 /* * types 4 onwards can be found in asm/mach/map.h and are undefined * for ioremap @@ -224,6 +225,34 @@ void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size); #endif #endif +/* access ports */ +#define setbits32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr)) +#define clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr)) + +#define setbits16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr)) +#define clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr)) + +#define setbits8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr)) +#define clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr)) + +/* Clear and set bits in one shot. These macros can be used to clear and + * set multiple bits in a register using a single read-modify-write. These + * macros can also be used to set a multiple-bit bit pattern using a mask, + * by specifying the mask in the 'clear' parameter and the new bit pattern + * in the 'set' parameter. + */ + +#define clrsetbits_be32(addr, clear, set) \ + iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr)) +#define clrsetbits_le32(addr, clear, set) \ + iowrite32le((ioread32le(addr) & ~(clear)) | (set), (addr)) +#define clrsetbits_be16(addr, clear, set) \ + iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr)) +#define clrsetbits_le16(addr, clear, set) \ + iowrite16le((ioread16le(addr) & ~(clear)) | (set), (addr)) +#define clrsetbits_8(addr, clear, set) \ + iowrite8((ioread8(addr) & ~(clear)) | (set), (addr)) + /* * IO port access primitives * ------------------------- @@ -410,6 +439,8 @@ void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size); #define ioremap_wc ioremap_wc #define ioremap_wt ioremap_wc +void __iomem *ioremap_cache_ns(resource_size_t res_cookie, size_t size); + void iounmap(volatile void __iomem *iomem_cookie); #define iounmap iounmap diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h index 0d84d50bf9ba8a..d18f3ef336338e 100644 --- a/arch/arm/include/asm/kvm_mmu.h +++ b/arch/arm/include/asm/kvm_mmu.h @@ -55,7 +55,8 @@ void stage2_unmap_vm(struct kvm *kvm); int kvm_alloc_stage2_pgd(struct kvm *kvm); void kvm_free_stage2_pgd(struct kvm *kvm); int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa, - phys_addr_t pa, unsigned long size, bool writable); + phys_addr_t pa, unsigned long size, bool writable, + pgprot_t prot); int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run); diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h index 92282558caf7cd..05e1af2179f94a 100644 --- a/arch/arm/include/asm/mach/map.h +++ b/arch/arm/include/asm/mach/map.h @@ -18,9 +18,9 @@ struct map_desc { unsigned int type; }; -/* types 0-3 are defined in asm/io.h */ +/* types 0-4 are defined in asm/io.h */ enum { - MT_UNCACHED = 4, + MT_UNCACHED = 5, MT_CACHECLEAN, MT_MINICLEAN, MT_LOW_VECTORS, diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index 3ae120cd1715fb..ea5c29c11bc807 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h @@ -116,6 +116,13 @@ extern pgprot_t pgprot_s2_device; #define pgprot_noncached(prot) \ __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED) +#define pgprot_cached(prot) \ + __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED) + +#define pgprot_cached_ns(prot) \ + __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED | \ + L_PTE_MT_DEV_NONSHARED) + #define pgprot_writecombine(prot) \ __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE) diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index ed46ca69813d3a..cc9e5b3cdbcfcb 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -12,11 +12,14 @@ #include #include #include +#include #include #include #include +#include "../../../drivers/pci/pcie/portdrv.h" + static int debug_pci; /* @@ -64,6 +67,47 @@ void pcibios_report_status(u_int status_mask, int warn) pcibios_bus_report_status(bus, status_mask, warn); } +/* + * Check device tree if the service interrupts are there + */ +int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask) +{ + int ret, count = 0; + struct device_node *np = NULL; + + if (dev->bus->dev.of_node) + np = dev->bus->dev.of_node; + + if (np == NULL) + return 0; + + if (!IS_ENABLED(CONFIG_OF_IRQ)) + return 0; + + /* If root port doesn't support MSI/MSI-X/INTx in RC mode, + * request irq for aer + */ + if (mask & PCIE_PORT_SERVICE_AER) { + ret = of_irq_get_byname(np, "aer"); + if (ret > 0) { + irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret; + count++; + } + } + + if (mask & PCIE_PORT_SERVICE_PME) { + ret = of_irq_get_byname(np, "pme"); + if (ret > 0) { + irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret; + count++; + } + } + + /* TODO: add more service interrupts if there it is in the device tree*/ + + return count; +} + /* * We don't use this to fix the device, but initialisation of it. * It's not the correct use for this, but it works. diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index b996b2cf070387..a148421cf48230 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c @@ -9,6 +9,7 @@ * reading the RTC at bootup, etc... */ #include +#include #include #include #include @@ -107,5 +108,7 @@ void __init time_init(void) of_clk_init(NULL); #endif timer_probe(); + + tick_setup_hrtimer_broadcast(); } } diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 95584ee02b559f..b80a060a0a7f9b 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -40,9 +40,29 @@ config HAVE_IMX_GPC bool select PM_GENERIC_DOMAINS if PM +config HAVE_IMX_GPCV2 + bool + select PM_GENERIC_DOMAINS if PM + config HAVE_IMX_MMDC bool +config HAVE_IMX_AMP + bool + +config HAVE_IMX_DDRC + bool + select HAVE_IMX_BUSFREQ + +config HAVE_IMX_BUSFREQ + bool + +config HAVE_IMX_MU + bool + +config HAVE_IMX_RPMSG + bool + config HAVE_IMX_SRC def_bool y if SMP select ARCH_HAS_RESET_CONTROLLER @@ -475,6 +495,7 @@ config SOC_IMX6 select ARM_ERRATA_775420 select ARM_GIC select HAVE_IMX_ANATOP + select HAVE_IMX_BUSFREQ select HAVE_IMX_GPC select HAVE_IMX_MMDC select HAVE_IMX_SRC @@ -511,7 +532,12 @@ config SOC_IMX6SLL config SOC_IMX6SX bool "i.MX6 SoloX support" select PINCTRL_IMX6SX + select HAVE_IMX_AMP select SOC_IMX6 + select HAVE_IMX_MU + select HAVE_IMX_RPMSG + select IMX_SEMA4 + select KEYBOARD_SNVS_PWRKEY help This enables support for Freescale i.MX6 SoloX processor. @@ -547,6 +573,11 @@ config SOC_IMX7D_CA7 select HAVE_IMX_MMDC select HAVE_IMX_SRC select IMX_GPCV2 + select HAVE_IMX_DDRC + select HAVE_IMX_MU + select HAVE_IMX_RPMSG + select HAVE_IMX_GPCV2 + select KEYBOARD_SNVS_PWRKEY config SOC_IMX7D_CM4 bool @@ -557,7 +588,7 @@ config SOC_IMX7D select PINCTRL_IMX7D select SOC_IMX7D_CA7 if ARCH_MULTI_V7 select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M - select ARM_ERRATA_814220 if ARCH_MULTI_V7 + select ARM_ERRATA_814220 help This enables support for Freescale i.MX7 Dual processor. diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index e7364e6c8c6b02..e4cd47d2a14414 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -obj-y := cpu.o system.o irq-common.o +obj-y := cpu.o system.o irq-common.o common.o obj-$(CONFIG_SOC_IMX21) += mm-imx21.o @@ -25,11 +25,18 @@ obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o -obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o -obj-$(CONFIG_SOC_IMX6SLL) += cpuidle-imx6sx.o -obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6sx.o -obj-$(CONFIG_SOC_IMX6UL) += cpuidle-imx6sx.o -obj-$(CONFIG_SOC_IMX7ULP) += cpuidle-imx7ulp.o +AFLAGS_imx6sl_low_power_idle.o :=-Wa,-march=armv7-a +obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o imx6sl_low_power_idle.o +AFLAGS_imx6sll_low_power_idle.o :=-Wa,-march=armv7-a +obj-$(CONFIG_SOC_IMX6SLL) += cpuidle-imx6sll.o imx6sll_low_power_idle.o +obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6sx.o imx6sx_low_power_idle.o +AFLAGS_imx6sx_low_power_idle.o :=-Wa,-march=armv7-a +AFLAGS_imx6ul_low_power_idle.o :=-Wa,-march=armv7-a +AFLAGS_imx6ull_low_power_idle.o :=-Wa,-march=armv7-a +obj-$(CONFIG_SOC_IMX6UL) += cpuidle-imx6ul.o imx6ul_low_power_idle.o imx6ull_low_power_idle.o +obj-$(CONFIG_SOC_IMX7ULP) += cpuidle-imx7ulp.o pm-rpmsg.o +AFLAGS_imx7d_low_power_idle.o :=-Wa,-march=armv7-a +obj-$(CONFIG_SOC_IMX7D_CA7) += cpuidle-imx7d.o imx7d_low_power_idle.o endif ifdef CONFIG_SND_SOC_IMX_PCM_FIQ @@ -70,26 +77,46 @@ obj-$(CONFIG_MACH_IMX35_DT) += imx35-dt.o obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o +obj-$(CONFIG_HAVE_IMX_GPCV2) += gpcv2.o obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o obj-$(CONFIG_HAVE_IMX_SRC) += src.o +obj-$(CONFIG_HAVE_IMX_DDRC) += ddrc.o +obj-$(CONFIG_HAVE_IMX_MU) += mu.o ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A),) AFLAGS_headsmp.o :=-Wa,-march=armv7-a obj-$(CONFIG_SMP) += headsmp.o platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o endif -obj-$(CONFIG_SOC_IMX6Q) += mach-imx6q.o -obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o -obj-$(CONFIG_SOC_IMX6SLL) += mach-imx6sl.o -obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o -obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o -obj-$(CONFIG_SOC_IMX7D_CA7) += mach-imx7d.o +obj-$(CONFIG_SOC_IMX6Q) += mach-imx6q.o ddr3_freq_imx6.o smp_wfe_imx6.o \ + lpddr2_freq_imx6q.o +obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o lpddr2_freq_imx6.o +obj-$(CONFIG_SOC_IMX6SLL) += mach-imx6sl.o lpddr2_freq_imx6sll.o +obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o ddr3_freq_imx6sx.o lpddr2_freq_imx6sx.o +obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o ddr3_freq_imx6sx.o lpddr2_freq_imx6sx.o +obj-$(CONFIG_SOC_IMX7D_CA7) += mach-imx7d.o pm-imx7.o ddr3_freq_imx7d.o smp_wfe.o \ + lpddr3_freq_imx.o suspend-imx7.o obj-$(CONFIG_SOC_IMX7D_CM4) += mach-imx7d-cm4.o obj-$(CONFIG_SOC_IMX7ULP) += mach-imx7ulp.o pm-imx7ulp.o +obj-$(CONFIG_HAVE_IMX_BUSFREQ) += busfreq-imx.o busfreq_ddr3.o busfreq_lpddr2.o +AFLAGS_smp_wfe.o :=-Wa,-march=armv7-a +AFLAGS_smp_wfe_imx6.o :=-Wa,-march=armv7-a +AFLAGS_ddr3_freq_imx7d.o :=-Wa,-march=armv7-a +AFLAGS_lpddr3_freq_imx.o :=-Wa,-march=armv7-a +AFLAGS_ddr3_freq_imx6.o :=-Wa,-march=armv7-a +AFLAGS_lpddr2_freq_imx6.o :=-Wa,-march=armv7-a +AFLAGS_lpddr2_freq_imx6q.o :=-Wa,-march=armv7-a +AFLAGS_lpddr2_freq_imx6sx.o :=-Wa,-march=armv7-a +AFLAGS_lpddr2_freq_imx6sll.o :=-Wa,-march=armv7-a +AFLAGS_ddr3_freq_imx6sx.o :=-Wa,-march=armv7-a + ifeq ($(CONFIG_SUSPEND),y) AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a +AFLAGS_suspend-imx7.o :=-Wa,-march=armv7-a +AFLAGS_suspend-imx7ulp.o :=-Wa,-march=armv7-a obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o obj-$(CONFIG_SOC_IMX53) += suspend-imx53.o +obj-$(CONFIG_SOC_IMX7ULP) += suspend-imx7ulp.o endif ifeq ($(CONFIG_ARM_CPU_SUSPEND),y) AFLAGS_resume-imx6.o :=-Wa,-march=armv7-a diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c index 777d8c25550110..a9ec0159b8f080 100644 --- a/arch/arm/mach-imx/anatop.c +++ b/arch/arm/mach-imx/anatop.c @@ -4,6 +4,7 @@ * Copyright 2017-2018 NXP. */ +#include #include #include #include @@ -16,38 +17,63 @@ #define REG_SET 0x4 #define REG_CLR 0x8 +#define ANADIG_ARM_PLL 0x60 +#define ANADIG_DDR_PLL 0x70 +#define ANADIG_SYS_PLL 0xb0 +#define ANADIG_ENET_PLL 0xe0 +#define ANADIG_AUDIO_PLL 0xf0 +#define ANADIG_VIDEO_PLL 0x130 + #define ANADIG_REG_2P5 0x130 #define ANADIG_REG_CORE 0x140 #define ANADIG_ANA_MISC0 0x150 #define ANADIG_USB1_CHRG_DETECT 0x1b0 #define ANADIG_USB2_CHRG_DETECT 0x210 +#define ANADIG_ANA_MISC2 0x170 #define ANADIG_DIGPROG 0x260 #define ANADIG_DIGPROG_IMX6SL 0x280 #define ANADIG_DIGPROG_IMX7D 0x800 -#define SRC_SBMR2 0x1c - #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000 #define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x8 #define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000 +#define BM_ANADIG_REG_CORE_REG1 (0x1f << 9) +#define BM_ANADIG_REG_CORE_REG2 (0x1f << 18) +#define BP_ANADIG_REG_CORE_REG2 (18) #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000 +#define BM_ANADIG_ANA_MISC0_V2_STOP_MODE_CONFIG 0x800 +#define BM_ANADIG_ANA_MISC0_V3_STOP_MODE_CONFIG 0xc00 +#define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME (0x3 << 26) +#define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME (26) /* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */ #define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS 0x2000 +/* Since i.MX6SX, DISCON_HIGH_SNVS is changed to bit 12 */ +#define BM_ANADIG_ANA_MISC0_V2_DISCON_HIGH_SNVS 0x1000 #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x80000 #define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x100000 +#define LDO_RAMP_UP_UNIT_IN_CYCLES 64 /* 64 cycles per step */ +#define LDO_RAMP_UP_FREQ_IN_MHZ 24 /* cycle based on 24M OSC */ + static struct regmap *anatop; static void imx_anatop_enable_weak2p5(bool enable) { - u32 reg, val; + u32 reg, val, mask; regmap_read(anatop, ANADIG_ANA_MISC0, &val); + if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || + cpu_is_imx6ulz() || cpu_is_imx6sll()) + mask = BM_ANADIG_ANA_MISC0_V3_STOP_MODE_CONFIG; + else if (cpu_is_imx6sl()) + mask = BM_ANADIG_ANA_MISC0_V2_STOP_MODE_CONFIG; + else + mask = BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG; + /* can only be enabled when stop_mode_config is clear. */ reg = ANADIG_REG_2P5; - reg += (enable && (val & BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) ? - REG_SET : REG_CLR; + reg += (enable && (val & mask) == 0) ? REG_SET : REG_CLR; regmap_write(anatop, reg, BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG); } @@ -65,35 +91,89 @@ static inline void imx_anatop_enable_2p5_pulldown(bool enable) static inline void imx_anatop_disconnect_high_snvs(bool enable) { - regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR), - BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS); + if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || + cpu_is_imx6ulz() || cpu_is_imx6sll()) + regmap_write(anatop, ANADIG_ANA_MISC0 + + (enable ? REG_SET : REG_CLR), + BM_ANADIG_ANA_MISC0_V2_DISCON_HIGH_SNVS); + else + regmap_write(anatop, ANADIG_ANA_MISC0 + + (enable ? REG_SET : REG_CLR), + BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS); +} + +static void imx_anatop_disable_pu(bool off) +{ + u32 val, soc, delay; + if (off) { + regmap_read(anatop, ANADIG_REG_CORE, &val); + val &= ~BM_ANADIG_REG_CORE_REG1; + regmap_write(anatop, ANADIG_REG_CORE, val); + } else { + /* track vddpu with vddsoc */ + regmap_read(anatop, ANADIG_REG_CORE, &val); + soc = val & BM_ANADIG_REG_CORE_REG2; + val &= ~BM_ANADIG_REG_CORE_REG1; + val |= soc >> 9; + regmap_write(anatop, ANADIG_REG_CORE, val); + /* wait PU LDO ramp */ + regmap_read(anatop, ANADIG_ANA_MISC2, &val); + val &= BM_ANADIG_ANA_MISC2_REG1_STEP_TIME; + val >>= BP_ANADIG_ANA_MISC2_REG1_STEP_TIME; + delay = (soc >> BP_ANADIG_REG_CORE_REG2) * + (LDO_RAMP_UP_UNIT_IN_CYCLES << val) / + LDO_RAMP_UP_FREQ_IN_MHZ + 1; + udelay(delay); + } } void imx_anatop_pre_suspend(void) { - if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) - imx_anatop_enable_2p5_pulldown(true); - else - imx_anatop_enable_weak2p5(true); + if (cpu_is_imx7d()) { + /* PLL and PFDs overwrite set */ + regmap_write(anatop, ANADIG_ARM_PLL + REG_SET, 1 << 20); + regmap_write(anatop, ANADIG_DDR_PLL + REG_SET, 1 << 19); + regmap_write(anatop, ANADIG_SYS_PLL + REG_SET, 0x1ff << 17); + regmap_write(anatop, ANADIG_ENET_PLL + REG_SET, 1 << 13); + regmap_write(anatop, ANADIG_AUDIO_PLL + REG_SET, 1 << 24); + regmap_write(anatop, ANADIG_VIDEO_PLL + REG_SET, 1 << 24); + return; + } + + if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) + imx_anatop_disable_pu(true); + imx_anatop_enable_weak2p5(true); imx_anatop_enable_fet_odrive(true); - if (cpu_is_imx6sl()) + if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || + cpu_is_imx6ull() || cpu_is_imx6ulz() || cpu_is_imx6sll()) imx_anatop_disconnect_high_snvs(true); } void imx_anatop_post_resume(void) { - if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) - imx_anatop_enable_2p5_pulldown(false); - else - imx_anatop_enable_weak2p5(false); + if (cpu_is_imx7d()) { + /* PLL and PFDs overwrite clear */ + regmap_write(anatop, ANADIG_ARM_PLL + REG_CLR, 1 << 20); + regmap_write(anatop, ANADIG_DDR_PLL + REG_CLR, 1 << 19); + regmap_write(anatop, ANADIG_SYS_PLL + REG_CLR, 0x1ff << 17); + regmap_write(anatop, ANADIG_ENET_PLL + REG_CLR, 1 << 13); + regmap_write(anatop, ANADIG_AUDIO_PLL + REG_CLR, 1 << 24); + regmap_write(anatop, ANADIG_VIDEO_PLL + REG_CLR, 1 << 24); + return; + } + + if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) + imx_anatop_disable_pu(false); + + imx_anatop_enable_weak2p5(false); imx_anatop_enable_fet_odrive(false); - if (cpu_is_imx6sl()) + if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || + cpu_is_imx6ull() || cpu_is_imx6ulz() || cpu_is_imx6sll()) imx_anatop_disconnect_high_snvs(false); - } static void imx_anatop_usb_chrg_detect_disable(void) @@ -110,10 +190,11 @@ void __init imx_init_revision_from_anatop(void) { struct device_node *np; void __iomem *anatop_base; + void __iomem *src_base; unsigned int revision; - u32 digprog; + u32 digprog, sbmr2 = 0; u16 offset = ANADIG_DIGPROG; - u8 major_part, minor_part; + u16 major_part, minor_part; np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); anatop_base = of_iomap(np, 0); @@ -125,6 +206,20 @@ void __init imx_init_revision_from_anatop(void) digprog = readl_relaxed(anatop_base + offset); iounmap(anatop_base); + if ((digprog >> 16) == MXC_CPU_IMX6ULL) { + np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-src"); + if (np) { + src_base = of_iomap(np, 0); + WARN_ON(!src_base); + sbmr2 = readl_relaxed(src_base + 0x1c); + iounmap(src_base); + } + if (sbmr2 & (1 << 6)) { + digprog &= ~(0xff << 16); + digprog |= (MXC_CPU_IMX6ULZ << 16); + } + } + /* * On i.MX7D digprog value match linux version format, so * it needn't map again and we can use register value directly. @@ -144,24 +239,6 @@ void __init imx_init_revision_from_anatop(void) major_part = (digprog >> 8) & 0xf; minor_part = digprog & 0xf; revision = ((major_part + 1) << 4) | minor_part; - - if ((digprog >> 16) == MXC_CPU_IMX6ULL) { - void __iomem *src_base; - u32 sbmr2; - - np = of_find_compatible_node(NULL, NULL, - "fsl,imx6ul-src"); - src_base = of_iomap(np, 0); - WARN_ON(!src_base); - sbmr2 = readl_relaxed(src_base + SRC_SBMR2); - iounmap(src_base); - - /* src_sbmr2 bit 6 is to identify if it is i.MX6ULZ */ - if (sbmr2 & (1 << 6)) { - digprog &= ~(0xff << 16); - digprog |= (MXC_CPU_IMX6ULZ << 16); - } - } } mxc_set_cpu_type(digprog >> 16 & 0xff); diff --git a/arch/arm/mach-imx/busfreq-imx.c b/arch/arm/mach-imx/busfreq-imx.c new file mode 100644 index 00000000000000..026f9a8090aee8 --- /dev/null +++ b/arch/arm/mach-imx/busfreq-imx.c @@ -0,0 +1,1407 @@ +/* + * Copyright (C) 2011-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP. + * Copyright 2018 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "hardware.h" +#include "common.h" + +#define LPAPM_CLK 24000000 +#define LOW_AUDIO_CLK 50000000 +#define HIGH_AUDIO_CLK 100000000 + +#define LOW_POWER_RUN_VOLTAGE 950000 + +#define MMDC_MDMISC_DDR_TYPE_DDR3 0 +#define MMDC_MDMISC_DDR_TYPE_LPDDR2 1 + +unsigned int ddr_med_rate; +unsigned int ddr_normal_rate; +unsigned long ddr_freq_change_total_size; +unsigned long ddr_freq_change_iram_base; +unsigned long ddr_freq_change_iram_phys; + +static int ddr_type; +static int low_bus_freq_mode; +static int audio_bus_freq_mode; +static int ultra_low_bus_freq_mode; +static int high_bus_freq_mode; +static int med_bus_freq_mode; +static int bus_freq_scaling_initialized; +static bool cancel_reduce_bus_freq; +static struct device *busfreq_dev; +static int busfreq_suspended; +static int bus_freq_scaling_is_active; +static int high_bus_count, med_bus_count, audio_bus_count, low_bus_count; +static unsigned int ddr_low_rate; +static int cur_bus_freq_mode; +static u32 org_arm_rate; + +extern unsigned long iram_tlb_phys_addr; +extern int unsigned long iram_tlb_base_addr; + +/* + * Bus frequency management by Linux + */ +extern int init_mmdc_lpddr2_settings(struct platform_device *dev); +extern int init_mmdc_lpddr2_settings_mx6q(struct platform_device *dev); +extern int init_mmdc_ddr3_settings_imx6_up(struct platform_device *dev); +extern int init_mmdc_ddr3_settings_imx6_smp(struct platform_device *dev); +extern int init_ddrc_ddr_settings(struct platform_device *dev); +extern int update_ddr_freq_imx_smp(int ddr_rate); +extern int update_ddr_freq_imx6_up(int ddr_rate); +extern int update_lpddr2_freq(int ddr_rate); +extern int update_lpddr2_freq_smp(int ddr_rate); + + +/** + * @brief Functions to init and update the busfreq function of + * device and memory type + */ +static struct busfreq_func { + int (*init)(struct platform_device *dev); + int (*update)(int ddr_rate); +} busfreq_func = {NULL, NULL}; + +DEFINE_MUTEX(bus_freq_mutex); + +static struct clk *osc_clk; +static struct clk *ahb_clk; +static struct clk *axi_sel_clk; +static struct clk *dram_root; +static struct clk *dram_alt_sel; +static struct clk *dram_alt_root; +static struct clk *pfd0_392m; +static struct clk *pfd2_270m; +static struct clk *pfd1_332m; +static struct clk *pll_dram; +static struct clk *ahb_sel_clk; +static struct clk *axi_clk; + +static struct clk *m4_clk; +static struct clk *pll3_clk; +static struct clk *pll2_400_clk; +static struct clk *periph_clk2_sel_clk; +static struct clk *periph_pre_clk; +static struct clk *pll2_200_clk; +static struct clk *periph_clk; +static struct clk *mmdc_clk; +static struct clk *periph_clk2_clk; +static struct clk *pll2_bus_clk; + +static struct clk *pll2_bypass_src_clk; +static struct clk *pll2_bypass_clk; +static struct clk *pll2_clk; +static struct clk *arm_clk; +static struct clk *step_clk; +static struct clk *pll1_clk; +static struct clk *pll1_bypass_src_clk; +static struct clk *pll1_bypass_clk; +static struct clk *pll1_sys_clk; +static struct clk *pll1_sw_clk; + +static struct clk *axi_alt_sel_clk; +static struct clk *pll3_pfd1_540m_clk; + +static struct clk *ocram_clk; +static struct clk *periph2_clk; +static struct clk *periph2_pre_clk; +static struct clk *periph2_clk2_clk; +static struct clk *periph2_clk2_sel_clk; + +static struct delayed_work low_bus_freq_handler; +static struct delayed_work bus_freq_daemon; + +static RAW_NOTIFIER_HEAD(busfreq_notifier_chain); + +static bool check_m4_sleep(void) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(500); + + while (imx_gpc_is_m4_sleeping() == 0) + if (time_after(jiffies, timeout)) + return false; + return true; +} + +static bool busfreq_notified_low = false; + +static int busfreq_notify(enum busfreq_event event) +{ + int ret; + + if (event == LOW_BUSFREQ_ENTER) { + WARN_ON(busfreq_notified_low); + busfreq_notified_low = true; + } else if (event == LOW_BUSFREQ_EXIT) { + WARN_ON(!busfreq_notified_low); + busfreq_notified_low = false; + } + ret = raw_notifier_call_chain(&busfreq_notifier_chain, event, NULL); + + return notifier_to_errno(ret); +} + +int register_busfreq_notifier(struct notifier_block *nb) +{ + return raw_notifier_chain_register(&busfreq_notifier_chain, nb); +} +EXPORT_SYMBOL(register_busfreq_notifier); + +int unregister_busfreq_notifier(struct notifier_block *nb) +{ + return raw_notifier_chain_unregister(&busfreq_notifier_chain, nb); +} +EXPORT_SYMBOL(unregister_busfreq_notifier); + +static struct clk *origin_step_parent; + +/* + * on i.MX6ULL, when entering low bus mode, the ARM core + * can run at 24MHz to support the low power run mode per + * to design team. + */ +static void imx6ull_lower_cpu_rate(bool enter) +{ + if (enter) { + org_arm_rate = clk_get_rate(arm_clk); + } + + clk_set_parent(pll1_bypass_clk, pll1_bypass_src_clk); + clk_set_parent(pll1_sw_clk, pll1_sys_clk); + + if (enter) { + origin_step_parent = clk_get_parent(step_clk); + clk_set_parent(step_clk, osc_clk); + clk_set_parent(pll1_sw_clk, step_clk); + clk_set_rate(arm_clk, LPAPM_CLK); + } else { + clk_set_parent(step_clk, origin_step_parent); + clk_set_parent(pll1_sw_clk, step_clk); + clk_set_rate(arm_clk, org_arm_rate); + clk_set_parent(pll1_bypass_clk, pll1_clk); + } +} + +/* + * enter_lpm_imx6_up and exit_lpm_imx6_up is used by + * i.MX6SX/i.MX6UL for entering and exiting lpm mode. + */ +static void enter_lpm_imx6_up(void) +{ + if (cpu_is_imx6sx() && imx_src_is_m4_enabled()) + if (!check_m4_sleep()) + pr_err("M4 is NOT in sleep!!!\n"); + + /* set periph_clk2 to source from OSC for periph */ + clk_set_parent(periph_clk2_sel_clk, osc_clk); + clk_set_parent(periph_clk, periph_clk2_clk); + /* set ahb/ocram to 24MHz */ + clk_set_rate(ahb_clk, LPAPM_CLK); + clk_set_rate(ocram_clk, LPAPM_CLK); + + if (audio_bus_count) { + /* Need to ensure that PLL2_PFD_400M is kept ON. */ + clk_prepare_enable(pll2_400_clk); + if (ddr_type == IMX_DDR_TYPE_DDR3) + busfreq_func.update(LOW_AUDIO_CLK); + else if (ddr_type == IMX_DDR_TYPE_LPDDR2 || + ddr_type == IMX_MMDC_DDR_TYPE_LPDDR3) + busfreq_func.update(HIGH_AUDIO_CLK); + clk_set_parent(periph2_clk2_sel_clk, pll3_clk); + clk_set_parent(periph2_pre_clk, pll2_400_clk); + clk_set_parent(periph2_clk, periph2_pre_clk); + /* + * As periph2_clk's parent is not changed from + * high mode to audio mode, so clk framework + * will not update its children's freq, but we + * change the mmdc's podf in asm code, so here + * need to update mmdc rate to make sure clk + * tree is right, although it will not do any + * change to hardware. + */ + if (high_bus_freq_mode) { + if (ddr_type == IMX_DDR_TYPE_DDR3) + clk_set_rate(mmdc_clk, LOW_AUDIO_CLK); + else if (ddr_type == IMX_DDR_TYPE_LPDDR2 || + ddr_type == IMX_MMDC_DDR_TYPE_LPDDR3) + clk_set_rate(mmdc_clk, HIGH_AUDIO_CLK); + } + + if ((cpu_is_imx6ull() || cpu_is_imx6ulz() || cpu_is_imx6sll()) && low_bus_freq_mode) + imx6ull_lower_cpu_rate(false); + + audio_bus_freq_mode = 1; + low_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_AUDIO; + } else { + busfreq_func.update(LPAPM_CLK); + + clk_set_parent(periph2_clk2_sel_clk, osc_clk); + clk_set_parent(periph2_clk, periph2_clk2_clk); + + if (audio_bus_freq_mode) + clk_disable_unprepare(pll2_400_clk); + + if (cpu_is_imx6ull() || cpu_is_imx6ulz() || cpu_is_imx6sll()) + imx6ull_lower_cpu_rate(true); + + low_bus_freq_mode = 1; + audio_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_LOW; + } +} + +static void enter_lpm_imx6_smp(void) +{ + if (cpu_is_imx6dl()) + /* Set axi to periph_clk */ + clk_set_parent(axi_sel_clk, periph_clk); + + if (audio_bus_count) { + /* Need to ensure that PLL2_PFD_400M is kept ON. */ + clk_prepare_enable(pll2_400_clk); + if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3) + busfreq_func.update(LOW_AUDIO_CLK); + else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2) + busfreq_func.update(HIGH_AUDIO_CLK); + /* Make sure periph clk's parent also got updated */ + clk_set_parent(periph_clk2_sel_clk, pll3_clk); + if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3) + clk_set_parent(periph_pre_clk, pll2_200_clk); + else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2) + clk_set_parent(periph_pre_clk, pll2_400_clk); + clk_set_parent(periph_clk, periph_pre_clk); + + /* + * As periph_pre_clk's parent is not changed from + * high mode to audio mode on lpddr2, the clk framework + * will not update its children's freq, but we + * change the mmdc_ch0_axi podf in asm code, so here + * need to update mmdc rate to make sure clk + * tree is right, although it will not do any + * change to hardware. Calling get_rate will only call + * the .rate_recalc which is all we need. + */ + if (high_bus_freq_mode && mmdc_clk) + if (ddr_type == IMX_DDR_TYPE_LPDDR2) + clk_get_rate(mmdc_clk); + + audio_bus_freq_mode = 1; + low_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_AUDIO; + } else { + busfreq_func.update(LPAPM_CLK); + + /* Make sure periph clk's parent also got updated */ + clk_set_parent(periph_clk2_sel_clk, osc_clk); + /* Set periph_clk parent to OSC via periph_clk2_sel */ + clk_set_parent(periph_clk, periph_clk2_clk); + if (audio_bus_freq_mode) + clk_disable_unprepare(pll2_400_clk); + low_bus_freq_mode = 1; + audio_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_LOW; + } +} + +static void exit_lpm_imx6_up(void) +{ + if ((cpu_is_imx6ull() || cpu_is_imx6ulz() || cpu_is_imx6sll()) && low_bus_freq_mode) + imx6ull_lower_cpu_rate(false); + + clk_prepare_enable(pll2_400_clk); + + /* + * lower ahb/ocram's freq first to avoid too high + * freq during parent switch from OSC to pll3. + */ + if (cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx6ulz() + || cpu_is_imx6sll()) + clk_set_rate(ahb_clk, LPAPM_CLK / 4); + else + clk_set_rate(ahb_clk, LPAPM_CLK / 3); + + clk_set_rate(ocram_clk, LPAPM_CLK / 2); + /* set periph clk to from pll2_bus on i.MX6UL */ + if (cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx6ulz() || cpu_is_imx6sll()) + clk_set_parent(periph_pre_clk, pll2_bus_clk); + /* set periph clk to from pll2_400 */ + else + clk_set_parent(periph_pre_clk, pll2_400_clk); + clk_set_parent(periph_clk, periph_pre_clk); + /* set periph_clk2 to pll3 */ + clk_set_parent(periph_clk2_sel_clk, pll3_clk); + + busfreq_func.update(ddr_normal_rate); + + /* correct parent info after ddr freq change in asm code */ + clk_set_parent(periph2_pre_clk, pll2_400_clk); + clk_set_parent(periph2_clk, periph2_pre_clk); + clk_set_parent(periph2_clk2_sel_clk, pll3_clk); + + /* + * As periph2_clk's parent is not changed from + * audio mode to high mode, so clk framework + * will not update its children's freq, but we + * change the mmdc's podf in asm code, so here + * need to update mmdc rate to make sure clk + * tree is right, although it will not do any + * change to hardware. + */ + if (audio_bus_freq_mode) + clk_set_rate(mmdc_clk, ddr_normal_rate); + + clk_disable_unprepare(pll2_400_clk); + + if (audio_bus_freq_mode) + clk_disable_unprepare(pll2_400_clk); +} + +static void exit_lpm_imx6_smp(void) +{ + struct clk *periph_clk_parent; + + if (cpu_is_imx6q() && ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3) + periph_clk_parent = pll2_bus_clk; + else + periph_clk_parent = pll2_400_clk; + + clk_prepare_enable(pll2_400_clk); + + busfreq_func.update(ddr_normal_rate); + + /* Make sure periph clk's parent also got updated */ + clk_set_parent(periph_clk2_sel_clk, pll3_clk); + clk_set_parent(periph_pre_clk, periph_clk_parent); + clk_set_parent(periph_clk, periph_pre_clk); + if (cpu_is_imx6dl()) { + /* Set axi to pll3_pfd1_540m */ + clk_set_parent(axi_alt_sel_clk, pll3_pfd1_540m_clk); + clk_set_parent(axi_sel_clk, axi_alt_sel_clk); + } + /* + * As periph_pre_clk's parent is not changed from + * high mode to audio mode on lpddr2, the clk framework + * will not update its children's freq, but we + * change the mmdc_ch0_axi podf in asm code, so here + * need to update mmdc rate to make sure clk + * tree is right, although it will not do any + * change to hardware. Calling get_rate will only call + * the .rate_recalc which is all we need. + */ + if (audio_bus_freq_mode && mmdc_clk) + if (ddr_type == IMX_DDR_TYPE_LPDDR2) + clk_get_rate(mmdc_clk); + + clk_disable_unprepare(pll2_400_clk); + if (audio_bus_freq_mode) + clk_disable_unprepare(pll2_400_clk); +} + +static void enter_lpm_imx6sl(void) +{ + if (high_bus_freq_mode) { + /* Set periph_clk to be sourced from OSC_CLK */ + clk_set_parent(periph_clk2_sel_clk, osc_clk); + clk_set_parent(periph_clk, periph_clk2_clk); + /* Ensure AHB/AXI clks are at 24MHz. */ + clk_set_rate(ahb_clk, LPAPM_CLK); + clk_set_rate(ocram_clk, LPAPM_CLK); + } + if (audio_bus_count) { + /* Set AHB to 8MHz to lower pwer.*/ + clk_set_rate(ahb_clk, LPAPM_CLK / 3); + + /* Set up DDR to 100MHz. */ + busfreq_func.update(HIGH_AUDIO_CLK); + + /* Fix the clock tree in kernel */ + clk_set_parent(periph2_pre_clk, pll2_200_clk); + clk_set_parent(periph2_clk, periph2_pre_clk); + + if (low_bus_freq_mode || ultra_low_bus_freq_mode) { + /* + * Fix the clock tree in kernel, make sure + * pll2_bypass is updated as it is + * sourced from PLL2. + */ + clk_set_parent(pll2_bypass_clk, pll2_clk); + /* + * Swtich ARM to run off PLL2_PFD2_400MHz + * since DDR is anyway at 100MHz. + */ + clk_set_parent(step_clk, pll2_400_clk); + clk_set_parent(pll1_sw_clk, step_clk); + + /* + * Need to ensure that PLL1 is bypassed and enabled + * before ARM-PODF is set. + */ + clk_set_parent(pll1_bypass_clk, pll1_bypass_src_clk); + + /* + * Ensure that the clock will be + * at original speed. + */ + clk_set_rate(arm_clk, org_arm_rate); + } + low_bus_freq_mode = 0; + ultra_low_bus_freq_mode = 0; + audio_bus_freq_mode = 1; + cur_bus_freq_mode = BUS_FREQ_AUDIO; + } else { + u32 arm_div, pll1_rate; + org_arm_rate = clk_get_rate(arm_clk); + if (org_arm_rate == 0) { + WARN_ON(1); + return; + } + if (low_bus_freq_mode && low_bus_count == 0) { + /* + * We are already in DDR @ 24MHz state, but + * no one but ARM needs the DDR. In this case, + * we can lower the DDR freq to 1MHz when ARM + * enters WFI in this state. Keep track of this state. + */ + ultra_low_bus_freq_mode = 1; + low_bus_freq_mode = 0; + audio_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_ULTRA_LOW; + } else { + if (!ultra_low_bus_freq_mode && !low_bus_freq_mode) { + /* + * Anyway, make sure the AHB is running at 24MHz + * in low_bus_freq_mode. + */ + if (audio_bus_freq_mode) + clk_set_rate(ahb_clk, LPAPM_CLK); + /* + * Set DDR to 24MHz. + * Since we are going to bypass PLL2, + * we need to move ARM clk off PLL2_PFD2 + * to PLL1. Make sure the PLL1 is running + * at the lowest possible freq. + * To work well with CPUFREQ we want to ensure that + * the CPU freq does not change, so attempt to + * get a freq as close to 396MHz as possible. + */ + clk_set_rate(pll1_clk, + clk_round_rate(pll1_clk, (org_arm_rate * 2))); + pll1_rate = clk_get_rate(pll1_clk); + arm_div = pll1_rate / org_arm_rate; + if (pll1_rate / arm_div > org_arm_rate) + arm_div++; + /* + * Need to ensure that PLL1 is bypassed and enabled + * before ARM-PODF is set. + */ + clk_set_parent(pll1_bypass_clk, pll1_clk); + /* + * Ensure ARM CLK is lower before + * changing the parent. + */ + clk_set_rate(arm_clk, org_arm_rate / arm_div); + /* Now set the ARM clk parent to PLL1_SYS. */ + clk_set_parent(pll1_sw_clk, pll1_sys_clk); + + /* + * Set STEP_CLK back to OSC to save power and + * also to maintain the parent.The WFI iram code + * will switch step_clk to osc, but the clock API + * is not aware of the change and when a new request + * to change the step_clk parent to pll2_pfd2_400M + * is requested sometime later, the change is ignored. + */ + clk_set_parent(step_clk, osc_clk); + + /* Now set DDR to 24MHz. */ + busfreq_func.update(LPAPM_CLK); + + /* + * Fix the clock tree in kernel. + * Make sure PLL2 rate is updated as it gets + * bypassed in the DDR freq change code. + */ + clk_set_parent(pll2_bypass_clk, pll2_bypass_src_clk); + clk_set_parent(periph2_clk2_sel_clk, pll2_bus_clk); + clk_set_parent(periph2_clk, periph2_clk2_clk); + } + if (low_bus_count == 0) { + ultra_low_bus_freq_mode = 1; + low_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_ULTRA_LOW; + } else { + ultra_low_bus_freq_mode = 0; + low_bus_freq_mode = 1; + cur_bus_freq_mode = BUS_FREQ_LOW; + } + audio_bus_freq_mode = 0; + } + } +} + +static void exit_lpm_imx6sl(void) +{ + /* Change DDR freq in IRAM. */ + busfreq_func.update(ddr_normal_rate); + + /* + * Fix the clock tree in kernel. + * Make sure PLL2 rate is updated as it gets + * un-bypassed in the DDR freq change code. + */ + clk_set_parent(pll2_bypass_clk, pll2_clk); + clk_set_parent(periph2_pre_clk, pll2_400_clk); + clk_set_parent(periph2_clk, periph2_pre_clk); + + /* Ensure that periph_clk is sourced from PLL2_400. */ + clk_set_parent(periph_pre_clk, pll2_400_clk); + /* + * Before switching the perhiph_clk, ensure that the + * AHB/AXI will not be too fast. + */ + clk_set_rate(ahb_clk, LPAPM_CLK / 3); + clk_set_rate(ocram_clk, LPAPM_CLK / 2); + clk_set_parent(periph_clk, periph_pre_clk); + + if (low_bus_freq_mode || ultra_low_bus_freq_mode) { + /* Move ARM from PLL1_SW_CLK to PLL2_400. */ + clk_set_parent(step_clk, pll2_400_clk); + clk_set_parent(pll1_sw_clk, step_clk); + /* + * Need to ensure that PLL1 is bypassed and enabled + * before ARM-PODF is set. + */ + clk_set_parent(pll1_bypass_clk, pll1_bypass_src_clk); + clk_set_rate(arm_clk, org_arm_rate); + ultra_low_bus_freq_mode = 0; + } +} + +static void enter_lpm_imx7d(void) +{ + /* + * The AHB clock parent switch and divider change + * needs to keep previous/current parent enabled + * per design requirement, but when we switch the + * clock parent, previous AHB clock parent may be + * disabled by common clock framework, so here we + * have to make sure AHB's previous parent pfd2_270m + * is enabled during AHB set rate. + */ + clk_prepare_enable(pfd2_270m); + if (audio_bus_count) { + clk_prepare_enable(pfd0_392m); + busfreq_func.update(HIGH_AUDIO_CLK); + + clk_set_parent(dram_alt_sel, pfd0_392m); + clk_set_parent(dram_root, dram_alt_root); + if (high_bus_freq_mode) { + clk_set_parent(axi_sel_clk, osc_clk); + clk_set_parent(ahb_sel_clk, osc_clk); + clk_set_rate(ahb_clk, LPAPM_CLK); + } + clk_disable_unprepare(pfd0_392m); + audio_bus_freq_mode = 1; + low_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_AUDIO; + } else { + busfreq_func.update(LPAPM_CLK); + + clk_set_parent(dram_alt_sel, osc_clk); + clk_set_parent(dram_root, dram_alt_root); + if (high_bus_freq_mode) { + clk_set_parent(axi_sel_clk, osc_clk); + clk_set_parent(ahb_sel_clk, osc_clk); + clk_set_rate(ahb_clk, LPAPM_CLK); + } + low_bus_freq_mode = 1; + audio_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_LOW; + } + clk_disable_unprepare(pfd2_270m); +} + +static void exit_lpm_imx7d(void) +{ + clk_set_parent(axi_sel_clk, pfd1_332m); + clk_set_rate(ahb_clk, LPAPM_CLK / 2); + clk_set_parent(ahb_sel_clk, pfd2_270m); + + busfreq_func.update(ddr_normal_rate); + + clk_set_parent(dram_root, pll_dram); +} + +static void reduce_bus_freq(void) +{ + if (cpu_is_imx6()) + clk_prepare_enable(pll3_clk); + + if (audio_bus_count && (low_bus_freq_mode || ultra_low_bus_freq_mode)) + busfreq_notify(LOW_BUSFREQ_EXIT); + else if (!audio_bus_count) + busfreq_notify(LOW_BUSFREQ_ENTER); + + if (cpu_is_imx7d()) + enter_lpm_imx7d(); + else if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || + cpu_is_imx6ulz() || cpu_is_imx6sll()) + enter_lpm_imx6_up(); + else if (cpu_is_imx6q() || cpu_is_imx6dl()) + enter_lpm_imx6_smp(); + else if (cpu_is_imx6sl()) + enter_lpm_imx6sl(); + + med_bus_freq_mode = 0; + high_bus_freq_mode = 0; + + if (cpu_is_imx6()) + clk_disable_unprepare(pll3_clk); + + if (audio_bus_freq_mode) + dev_dbg(busfreq_dev, + "Bus freq set to audio mode. Count: high %d, med %d, audio %d\n", + high_bus_count, med_bus_count, audio_bus_count); + if (low_bus_freq_mode) + dev_dbg(busfreq_dev, + "Bus freq set to low mode. Count: high %d, med %d, audio %d\n", + high_bus_count, med_bus_count, audio_bus_count); +} + +static inline void cancel_low_bus_freq_handler(void) +{ + cancel_delayed_work(&low_bus_freq_handler); + cancel_reduce_bus_freq = true; +} + +static void reduce_bus_freq_handler(struct work_struct *work) +{ + mutex_lock(&bus_freq_mutex); + + if (!cancel_reduce_bus_freq) { + reduce_bus_freq(); + cancel_low_bus_freq_handler(); + } + + mutex_unlock(&bus_freq_mutex); +} + +/* + * Set the DDR, AHB to 24MHz. + * This mode will be activated only when none of the modules that + * need a higher DDR or AHB frequency are active. + */ +static int set_low_bus_freq(void) +{ + if (busfreq_suspended) + return 0; + + if (!bus_freq_scaling_initialized || !bus_freq_scaling_is_active) + return 0; + + cancel_reduce_bus_freq = false; + + /* + * Check to see if we need to got from + * low bus freq mode to audio bus freq mode. + * If so, the change needs to be done immediately. + */ + if (audio_bus_count && (low_bus_freq_mode || ultra_low_bus_freq_mode)) + reduce_bus_freq(); + else + /* + * Don't lower the frequency immediately. Instead + * scheduled a delayed work and drop the freq if + * the conditions still remain the same. + */ + schedule_delayed_work(&low_bus_freq_handler, + usecs_to_jiffies(3000000)); + return 0; +} + +/* + * Set the DDR to either 528MHz or 400MHz for iMX6qd + * or 400MHz for iMX6dl. + */ +static int set_high_bus_freq(int high_bus_freq) +{ + if (bus_freq_scaling_initialized && bus_freq_scaling_is_active) + cancel_low_bus_freq_handler(); + + if (busfreq_suspended) + return 0; + + if (!bus_freq_scaling_initialized || !bus_freq_scaling_is_active) + return 0; + + if (high_bus_freq_mode) + return 0; + + /* medium bus freq is only supported for MX6DQ */ + if (med_bus_freq_mode && !high_bus_freq) + return 0; + + if (low_bus_freq_mode || ultra_low_bus_freq_mode) + busfreq_notify(LOW_BUSFREQ_EXIT); + + if (cpu_is_imx6()) + clk_prepare_enable(pll3_clk); + + if (cpu_is_imx7d()) + exit_lpm_imx7d(); + else if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || + cpu_is_imx6ulz() || cpu_is_imx6sll()) + exit_lpm_imx6_up(); + else if (cpu_is_imx6q() || cpu_is_imx6dl()) + exit_lpm_imx6_smp(); + else if (cpu_is_imx6sl()) + exit_lpm_imx6sl(); + + high_bus_freq_mode = 1; + med_bus_freq_mode = 0; + low_bus_freq_mode = 0; + audio_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_HIGH; + + if (cpu_is_imx6()) + clk_disable_unprepare(pll3_clk); + + if (high_bus_freq_mode) + dev_dbg(busfreq_dev, + "Bus freq set to high mode. Count: high %d, med %d, audio %d\n", + high_bus_count, med_bus_count, audio_bus_count); + if (med_bus_freq_mode) + dev_dbg(busfreq_dev, + "Bus freq set to med mode. Count: high %d, med %d, audio %d\n", + high_bus_count, med_bus_count, audio_bus_count); + + return 0; +} + +void request_bus_freq(enum bus_freq_mode mode) +{ + mutex_lock(&bus_freq_mutex); + + if (mode == BUS_FREQ_ULTRA_LOW) { + dev_dbg(busfreq_dev, "This mode cannot be requested!\n"); + mutex_unlock(&bus_freq_mutex); + return; + } + + if (mode == BUS_FREQ_HIGH) + high_bus_count++; + else if (mode == BUS_FREQ_MED) + med_bus_count++; + else if (mode == BUS_FREQ_AUDIO) + audio_bus_count++; + else if (mode == BUS_FREQ_LOW) + low_bus_count++; + + if (busfreq_suspended || !bus_freq_scaling_initialized || + !bus_freq_scaling_is_active) { + mutex_unlock(&bus_freq_mutex); + return; + } + + cancel_low_bus_freq_handler(); + + if ((mode == BUS_FREQ_HIGH) && (!high_bus_freq_mode)) { + set_high_bus_freq(1); + mutex_unlock(&bus_freq_mutex); + return; + } + + if ((mode == BUS_FREQ_MED) && (!high_bus_freq_mode) && + (!med_bus_freq_mode)) { + set_high_bus_freq(0); + mutex_unlock(&bus_freq_mutex); + return; + } + if ((mode == BUS_FREQ_AUDIO) && (!high_bus_freq_mode) && + (!med_bus_freq_mode) && (!audio_bus_freq_mode)) { + set_low_bus_freq(); + mutex_unlock(&bus_freq_mutex); + return; + } + mutex_unlock(&bus_freq_mutex); +} +EXPORT_SYMBOL(request_bus_freq); + +void release_bus_freq(enum bus_freq_mode mode) +{ + mutex_lock(&bus_freq_mutex); + + if (mode == BUS_FREQ_ULTRA_LOW) { + dev_dbg(busfreq_dev, + "This mode cannot be released!\n"); + mutex_unlock(&bus_freq_mutex); + return; + } + + if (mode == BUS_FREQ_HIGH) { + if (high_bus_count == 0) { + dev_err(busfreq_dev, "high bus count mismatch!\n"); + dump_stack(); + mutex_unlock(&bus_freq_mutex); + return; + } + high_bus_count--; + } else if (mode == BUS_FREQ_MED) { + if (med_bus_count == 0) { + dev_err(busfreq_dev, "med bus count mismatch!\n"); + dump_stack(); + mutex_unlock(&bus_freq_mutex); + return; + } + med_bus_count--; + } else if (mode == BUS_FREQ_AUDIO) { + if (audio_bus_count == 0) { + dev_err(busfreq_dev, "audio bus count mismatch!\n"); + dump_stack(); + mutex_unlock(&bus_freq_mutex); + return; + } + audio_bus_count--; + } else if (mode == BUS_FREQ_LOW) { + if (low_bus_count == 0) { + dev_err(busfreq_dev, "low bus count mismatch!\n"); + dump_stack(); + mutex_unlock(&bus_freq_mutex); + return; + } + low_bus_count--; + } + + if (busfreq_suspended || !bus_freq_scaling_initialized || + !bus_freq_scaling_is_active) { + mutex_unlock(&bus_freq_mutex); + return; + } + + if ((!audio_bus_freq_mode) && (high_bus_count == 0) && + (med_bus_count == 0) && (audio_bus_count != 0)) { + set_low_bus_freq(); + mutex_unlock(&bus_freq_mutex); + return; + } + if ((!low_bus_freq_mode) && (high_bus_count == 0) && + (med_bus_count == 0) && (audio_bus_count == 0) && + (low_bus_count != 0)) { + set_low_bus_freq(); + mutex_unlock(&bus_freq_mutex); + return; + } + if ((!ultra_low_bus_freq_mode) && (high_bus_count == 0) && + (med_bus_count == 0) && (audio_bus_count == 0) && + (low_bus_count == 0)) { + set_low_bus_freq(); + mutex_unlock(&bus_freq_mutex); + return; + } + + mutex_unlock(&bus_freq_mutex); +} +EXPORT_SYMBOL(release_bus_freq); + +int get_bus_freq_mode(void) +{ + return cur_bus_freq_mode; +} +EXPORT_SYMBOL(get_bus_freq_mode); + +static struct map_desc ddr_iram_io_desc __initdata = { + /* .virtual and .pfn are run-time assigned */ + .length = SZ_1M, + .type = MT_MEMORY_RWX_NONCACHED, +}; + +const static char *ddr_freq_iram_match[] __initconst = { + "fsl,ddr-lpm-sram", + NULL +}; + +static int __init imx_dt_find_ddr_sram(unsigned long node, + const char *uname, int depth, void *data) +{ + unsigned long ddr_iram_addr; + const __be32 *prop; + + if (of_flat_dt_match(node, ddr_freq_iram_match)) { + unsigned int len; + + prop = of_get_flat_dt_prop(node, "reg", &len); + if (prop == NULL || len != (sizeof(unsigned long) * 2)) + return -EINVAL; + ddr_iram_addr = be32_to_cpu(prop[0]); + ddr_freq_change_total_size = be32_to_cpu(prop[1]); + ddr_freq_change_iram_phys = ddr_iram_addr; + + /* Make sure ddr_freq_change_iram_phys is 8 byte aligned. */ + if ((uintptr_t)(ddr_freq_change_iram_phys) & (FNCPY_ALIGN - 1)) + ddr_freq_change_iram_phys += FNCPY_ALIGN - + ((uintptr_t)ddr_freq_change_iram_phys % + (FNCPY_ALIGN)); + } + return 0; +} + +void __init imx_busfreq_map_io(void) +{ + /* + * Get the address of IRAM to be used by the ddr frequency + * change code from the device tree. + */ + WARN_ON(of_scan_flat_dt(imx_dt_find_ddr_sram, NULL)); + if (ddr_freq_change_iram_phys) { + ddr_freq_change_iram_base = IMX_IO_P2V( + ddr_freq_change_iram_phys); + if ((iram_tlb_phys_addr & 0xFFF00000) != + (ddr_freq_change_iram_phys & 0xFFF00000)) { + /* We need to create a 1M page table entry. */ + ddr_iram_io_desc.virtual = IMX_IO_P2V( + ddr_freq_change_iram_phys & 0xFFF00000); + ddr_iram_io_desc.pfn = __phys_to_pfn( + ddr_freq_change_iram_phys & 0xFFF00000); + iotable_init(&ddr_iram_io_desc, 1); + } + memset((void *)ddr_freq_change_iram_base, 0, + ddr_freq_change_total_size); + } +} + +static void bus_freq_daemon_handler(struct work_struct *work) +{ + mutex_lock(&bus_freq_mutex); + if ((!low_bus_freq_mode) && (!ultra_low_bus_freq_mode) + && (high_bus_count == 0) && + (med_bus_count == 0) && (audio_bus_count == 0)) + set_low_bus_freq(); + mutex_unlock(&bus_freq_mutex); +} + +static ssize_t bus_freq_scaling_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + if (bus_freq_scaling_is_active) + return sprintf(buf, "Bus frequency scaling is enabled\n"); + else + return sprintf(buf, "Bus frequency scaling is disabled\n"); +} + +static ssize_t bus_freq_scaling_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + if (strncmp(buf, "1", 1) == 0) { + bus_freq_scaling_is_active = 1; + set_high_bus_freq(1); + /* + * We set bus freq to highest at the beginning, + * so we use this daemon thread to make sure system + * can enter low bus mode if + * there is no high bus request pending + */ + schedule_delayed_work(&bus_freq_daemon, + usecs_to_jiffies(5000000)); + } else if (strncmp(buf, "0", 1) == 0) { + if (bus_freq_scaling_is_active) + set_high_bus_freq(1); + bus_freq_scaling_is_active = 0; + } + return size; +} + +static int bus_freq_pm_notify(struct notifier_block *nb, unsigned long event, + void *dummy) +{ + mutex_lock(&bus_freq_mutex); + + if (event == PM_SUSPEND_PREPARE) { + if (cpu_is_imx7d() && imx_src_is_m4_enabled()) + imx_mu_lpm_ready(false); + high_bus_count++; + set_high_bus_freq(1); + busfreq_suspended = 1; + } else if (event == PM_POST_SUSPEND) { + busfreq_suspended = 0; + high_bus_count--; + if (cpu_is_imx7d() && imx_src_is_m4_enabled()) + imx_mu_lpm_ready(true); + schedule_delayed_work(&bus_freq_daemon, + usecs_to_jiffies(5000000)); + } + + mutex_unlock(&bus_freq_mutex); + + return NOTIFY_OK; +} + +static int busfreq_reboot_notifier_event(struct notifier_block *this, + unsigned long event, void *ptr) +{ + /* System is rebooting. Set the system into high_bus_freq_mode. */ + request_bus_freq(BUS_FREQ_HIGH); + + return 0; +} + +static struct notifier_block imx_bus_freq_pm_notifier = { + .notifier_call = bus_freq_pm_notify, +}; + +static struct notifier_block imx_busfreq_reboot_notifier = { + .notifier_call = busfreq_reboot_notifier_event, +}; + + +static DEVICE_ATTR(enable, 0644, bus_freq_scaling_enable_show, + bus_freq_scaling_enable_store); + +/*! + * This is the probe routine for the bus frequency driver. + * + * @param pdev The platform device structure + * + * @return The function returns 0 on success + * + */ + +static int busfreq_probe(struct platform_device *pdev) +{ + u32 err; + + busfreq_dev = &pdev->dev; + + /* Return if no IRAM space is allocated for ddr freq change code. */ + if (!ddr_freq_change_iram_base) + return -ENOMEM; + + if (cpu_is_imx6()) { + osc_clk = devm_clk_get(&pdev->dev, "osc"); + pll2_400_clk = devm_clk_get(&pdev->dev, "pll2_pfd2_396m"); + pll2_200_clk = devm_clk_get(&pdev->dev, "pll2_198m"); + pll2_bus_clk = devm_clk_get(&pdev->dev, "pll2_bus"); + pll3_clk = devm_clk_get(&pdev->dev, "pll3_usb_otg"); + periph_clk = devm_clk_get(&pdev->dev, "periph"); + periph_pre_clk = devm_clk_get(&pdev->dev, "periph_pre"); + periph_clk2_clk = devm_clk_get(&pdev->dev, "periph_clk2"); + periph_clk2_sel_clk = devm_clk_get(&pdev->dev, + "periph_clk2_sel"); + if (IS_ERR(osc_clk) || IS_ERR(pll2_400_clk) + || IS_ERR(pll2_200_clk) || IS_ERR(pll2_bus_clk) + || IS_ERR(pll3_clk) || IS_ERR(periph_clk) + || IS_ERR(periph_pre_clk) || IS_ERR(periph_clk2_clk) + || IS_ERR(periph_clk2_sel_clk)) { + dev_err(busfreq_dev, + "%s: failed to get busfreq clk\n", __func__); + return -EINVAL; + } + } + + if (cpu_is_imx6dl()) { + axi_alt_sel_clk = devm_clk_get(&pdev->dev, "axi_alt_sel"); + axi_sel_clk = devm_clk_get(&pdev->dev, "axi_sel"); + pll3_pfd1_540m_clk = devm_clk_get(&pdev->dev, "pll3_pfd1_540m"); + if (IS_ERR(axi_alt_sel_clk) || IS_ERR(axi_sel_clk) + || IS_ERR(pll3_pfd1_540m_clk)) { + dev_err(busfreq_dev, + "%s: failed to get busfreq clk\n", __func__); + return -EINVAL; + } + } + + if (cpu_is_imx6sx() || cpu_is_imx6sl() || cpu_is_imx6ul() || + cpu_is_imx6ull() || cpu_is_imx6ulz() || cpu_is_imx6sll()) { + ahb_clk = devm_clk_get(&pdev->dev, "ahb"); + ocram_clk = devm_clk_get(&pdev->dev, "ocram"); + periph2_clk = devm_clk_get(&pdev->dev, "periph2"); + periph2_pre_clk = devm_clk_get(&pdev->dev, "periph2_pre"); + periph2_clk2_clk = devm_clk_get(&pdev->dev, "periph2_clk2"); + periph2_clk2_sel_clk = + devm_clk_get(&pdev->dev, "periph2_clk2_sel"); + if (IS_ERR(ahb_clk) || IS_ERR(ocram_clk) + || IS_ERR(periph2_clk) || IS_ERR(periph2_pre_clk) + || IS_ERR(periph2_clk2_clk) + || IS_ERR(periph2_clk2_sel_clk)) { + dev_err(busfreq_dev, + "%s: failed to get busfreq clk for imx6ul/sx/sl.\n", __func__); + return -EINVAL; + } + } + + if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || + cpu_is_imx6ulz() || cpu_is_imx6sll()) { + mmdc_clk = devm_clk_get(&pdev->dev, "mmdc"); + if (IS_ERR(mmdc_clk)) { + dev_err(busfreq_dev, + "%s: failed to get mmdc clk for imx6sx/ul.\n", __func__); + return -EINVAL; + } + } + + if (cpu_is_imx6q()) { + mmdc_clk = devm_clk_get(&pdev->dev, "mmdc"); + if (IS_ERR(mmdc_clk)) { + mmdc_clk = NULL; + } + } + + if (cpu_is_imx6sx()) { + m4_clk = devm_clk_get(&pdev->dev, "m4"); + if (IS_ERR(m4_clk)) { + dev_err(busfreq_dev, "%s: failed to get m4 clk.\n", __func__); + return -EINVAL; + } + } + + if (cpu_is_imx6sl()) { + pll2_bypass_src_clk = devm_clk_get(&pdev->dev, "pll2_bypass_src"); + pll2_bypass_clk = devm_clk_get(&pdev->dev, "pll2_bypass"); + pll2_clk = devm_clk_get(&pdev->dev, "pll2"); + if (IS_ERR(pll2_bypass_src_clk) || IS_ERR(pll2_bypass_clk) + || IS_ERR(pll2_clk)) { + dev_err(busfreq_dev, + "%s failed to get busfreq clk for imx6sl.\n", __func__); + return -EINVAL; + } + } + + if (cpu_is_imx6sl() || cpu_is_imx6ull() || cpu_is_imx6ulz() || cpu_is_imx6sll()) { + arm_clk = devm_clk_get(&pdev->dev, "arm"); + step_clk = devm_clk_get(&pdev->dev, "step"); + pll1_clk = devm_clk_get(&pdev->dev, "pll1"); + pll1_bypass_src_clk = devm_clk_get(&pdev->dev, "pll1_bypass_src"); + pll1_bypass_clk = devm_clk_get(&pdev->dev, "pll1_bypass"); + pll1_sys_clk = devm_clk_get(&pdev->dev, "pll1_sys"); + pll1_sw_clk = devm_clk_get(&pdev->dev, "pll1_sw"); + if (IS_ERR(arm_clk) || IS_ERR(step_clk) || IS_ERR(pll1_clk) + || IS_ERR(pll1_bypass_src_clk) || IS_ERR(pll1_bypass_clk) + || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk)) { + dev_err(busfreq_dev, "%s failed to get busfreq clk for imx6ull/sl.\n", __func__); + return -EINVAL; + } + } + + if (cpu_is_imx7d()) { + osc_clk = devm_clk_get(&pdev->dev, "osc"); + axi_sel_clk = devm_clk_get(&pdev->dev, "axi_sel"); + ahb_sel_clk = devm_clk_get(&pdev->dev, "ahb_sel"); + pfd0_392m = devm_clk_get(&pdev->dev, "pfd0_392m"); + dram_root = devm_clk_get(&pdev->dev, "dram_root"); + dram_alt_sel = devm_clk_get(&pdev->dev, "dram_alt_sel"); + pll_dram = devm_clk_get(&pdev->dev, "pll_dram"); + dram_alt_root = devm_clk_get(&pdev->dev, "dram_alt_root"); + pfd1_332m = devm_clk_get(&pdev->dev, "pfd1_332m"); + pfd2_270m = devm_clk_get(&pdev->dev, "pfd2_270m"); + ahb_clk = devm_clk_get(&pdev->dev, "ahb"); + axi_clk = devm_clk_get(&pdev->dev, "axi"); + if (IS_ERR(osc_clk) || IS_ERR(axi_sel_clk) || IS_ERR(ahb_clk) + || IS_ERR(pfd0_392m) || IS_ERR(dram_root) + || IS_ERR(dram_alt_sel) || IS_ERR(pll_dram) + || IS_ERR(dram_alt_root) || IS_ERR(pfd1_332m) + || IS_ERR(ahb_clk) || IS_ERR(axi_clk) + || IS_ERR(pfd2_270m)) { + dev_err(busfreq_dev, + "%s: failed to get busfreq clk\n", __func__); + return -EINVAL; + } + } + + err = sysfs_create_file(&busfreq_dev->kobj, &dev_attr_enable.attr); + if (err) { + dev_err(busfreq_dev, + "Unable to register sysdev entry for BUSFREQ"); + return err; + } + + if (of_property_read_u32(pdev->dev.of_node, "fsl,max_ddr_freq", + &ddr_normal_rate)) { + dev_err(busfreq_dev, "max_ddr_freq entry missing\n"); + return -EINVAL; + } + + high_bus_freq_mode = 1; + med_bus_freq_mode = 0; + low_bus_freq_mode = 0; + audio_bus_freq_mode = 0; + ultra_low_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_HIGH; + + bus_freq_scaling_is_active = 1; + bus_freq_scaling_initialized = 1; + + ddr_low_rate = LPAPM_CLK; + + INIT_DELAYED_WORK(&low_bus_freq_handler, reduce_bus_freq_handler); + INIT_DELAYED_WORK(&bus_freq_daemon, bus_freq_daemon_handler); + register_pm_notifier(&imx_bus_freq_pm_notifier); + register_reboot_notifier(&imx_busfreq_reboot_notifier); + + /* enter low bus mode if no high speed device enabled */ + schedule_delayed_work(&bus_freq_daemon, + msecs_to_jiffies(20000)); + + /* + * Need to make sure to an entry for the ddr freq change code + * address in the IRAM page table. + * This is only required if the DDR freq code and suspend/idle + * code are in different OCRAM spaces. + */ + if ((iram_tlb_phys_addr & 0xFFF00000) != + (ddr_freq_change_iram_phys & 0xFFF00000)) { + unsigned long i; + + /* + * Make sure the ddr_iram virtual address has a mapping + * in the IRAM page table. + */ + i = ((IMX_IO_P2V(ddr_freq_change_iram_phys) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + i) = + (ddr_freq_change_iram_phys & 0xFFF00000) | + TT_ATTRIB_NON_CACHEABLE_1M; + } + + if (cpu_is_imx7d()) { + ddr_type = imx_ddrc_get_ddr_type(); + /* reduce ddr3 normal rate to 400M due to CKE issue on TO1.1 */ + if (imx_get_soc_revision() == IMX_CHIP_REVISION_1_1 && + ddr_type == IMX_DDR_TYPE_DDR3) { + ddr_normal_rate = 400000000; + pr_info("ddr3 normal rate changed to 400MHz for TO1.1.\n"); + } + busfreq_func.init = &init_ddrc_ddr_settings; + busfreq_func.update = &update_ddr_freq_imx_smp; + } else if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx6ulz() || + cpu_is_imx6sll()) { + ddr_type = imx_mmdc_get_ddr_type(); + if (ddr_type == IMX_DDR_TYPE_DDR3) { + busfreq_func.init = &init_mmdc_ddr3_settings_imx6_up; + busfreq_func.update = &update_ddr_freq_imx6_up; + } else if (ddr_type == IMX_DDR_TYPE_LPDDR2 || + ddr_type == IMX_MMDC_DDR_TYPE_LPDDR3) { + busfreq_func.init = &init_mmdc_lpddr2_settings; + busfreq_func.update = &update_lpddr2_freq; + } + } else if (cpu_is_imx6q() || cpu_is_imx6dl()) { + ddr_type = imx_mmdc_get_ddr_type(); + if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3) { + busfreq_func.init = &init_mmdc_ddr3_settings_imx6_smp; + busfreq_func.update = &update_ddr_freq_imx_smp; + } else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2) { + busfreq_func.init = &init_mmdc_lpddr2_settings_mx6q; + busfreq_func.update = &update_lpddr2_freq_smp; + } + } else if (cpu_is_imx6sl()) { + busfreq_func.init = &init_mmdc_lpddr2_settings; + busfreq_func.update = &update_lpddr2_freq; + } + + if (busfreq_func.init) + err = busfreq_func.init(pdev); + else + err = -EINVAL; + + if (!err) { + if (cpu_is_imx6sx()) { + /* + * If M4 is enabled and rate > 24MHz, + * add high bus count + */ + if (imx_src_is_m4_enabled() && + (clk_get_rate(m4_clk) > LPAPM_CLK)) + high_bus_count++; + } + + if (cpu_is_imx7d() && imx_src_is_m4_enabled()) { + high_bus_count++; + imx_mu_lpm_ready(true); + } + } + + if (err) { + dev_err(busfreq_dev, "Busfreq init of ddr controller failed\n"); + return err; + } + + return 0; +} + +static const struct of_device_id imx_busfreq_ids[] = { + { .compatible = "fsl,imx_busfreq", }, + { /* sentinel */ } +}; + +static struct platform_driver busfreq_driver = { + .driver = { + .name = "imx_busfreq", + .owner = THIS_MODULE, + .of_match_table = imx_busfreq_ids, + }, + .probe = busfreq_probe, +}; + +/*! + * Initialise the busfreq_driver. + * + * @return The function always returns 0. + */ + +static int __init busfreq_init(void) +{ +#ifndef CONFIG_MX6_VPU_352M + if (platform_driver_register(&busfreq_driver) != 0) + return -ENODEV; + + pr_info("Bus freq driver module loaded\n"); +#endif + return 0; +} + +static void __exit busfreq_cleanup(void) +{ + sysfs_remove_file(&busfreq_dev->kobj, &dev_attr_enable.attr); + + /* Unregister the device structure */ + platform_driver_unregister(&busfreq_driver); + bus_freq_scaling_initialized = 0; +} + +module_init(busfreq_init); +module_exit(busfreq_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("BusFreq driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-imx/busfreq_ddr3.c b/arch/arm/mach-imx/busfreq_ddr3.c new file mode 100644 index 00000000000000..0088a5d8073633 --- /dev/null +++ b/arch/arm/mach-imx/busfreq_ddr3.c @@ -0,0 +1,772 @@ +/* + * Copyright (C) 2011-2016 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file busfreq_ddr3.c + * + * @brief iMX6 DDR3 frequency change specific file. + * + * @ingroup PM + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hardware.h" +#include "common.h" + +#define SMP_WFE_CODE_SIZE 0x400 + +#define MIN_DLL_ON_FREQ 333000000 +#define MAX_DLL_OFF_FREQ 125000000 +#define MMDC0_MPMUR0 0x8b8 +#define MMDC0_MPMUR0_OFFSET 16 +#define MMDC0_MPMUR0_MASK 0x3ff + +/* + * This structure is for passing necessary data for low level ocram + * busfreq code(arch/arm/mach-imx/ddr3_freq_imx6.S), if this struct + * definition is changed, the offset definition in + * arch/arm/mach-imx/ddr3_freq_imx6.S must be also changed accordingly, + * otherwise, the busfreq change function will be broken! + * + * This structure will be placed in front of the asm code on ocram. + */ +struct imx6_busfreq_info { + u32 freq; + void *ddr_settings; + u32 dll_off; + void *iomux_offsets; + u32 mu_delay_val; +} __aligned(8); + +static struct imx6_busfreq_info *imx6_busfreq_info; + +/* DDR settings */ +static unsigned long (*iram_ddr_settings)[2]; +static unsigned long (*normal_mmdc_settings)[2]; +static unsigned long (*iram_iomux_settings)[2]; + +static void __iomem *mmdc_base; +static void __iomem *iomux_base; +static void __iomem *gic_dist_base; + +static int ddr_settings_size; +static int iomux_settings_size; +static int curr_ddr_rate; + +void (*imx6_up_change_ddr_freq)(struct imx6_busfreq_info *busfreq_info); +extern void imx6_up_ddr3_freq_change(struct imx6_busfreq_info *busfreq_info); +void (*imx7d_change_ddr_freq)(u32 freq) = NULL; +extern void imx7d_ddr3_freq_change(u32 freq); +extern void imx_lpddr3_freq_change(u32 freq); + +void (*mx6_change_ddr_freq)(u32 freq, void *ddr_settings, + bool dll_mode, void *iomux_offsets) = NULL; + +extern unsigned int ddr_normal_rate; +extern int low_bus_freq_mode; +extern int audio_bus_freq_mode; +extern void mx6_ddr3_freq_change(u32 freq, void *ddr_settings, + bool dll_mode, void *iomux_offsets); + +extern unsigned long save_ttbr1(void); +extern void restore_ttbr1(unsigned long ttbr1); +extern unsigned long ddr_freq_change_iram_base; + +extern unsigned long ddr_freq_change_total_size; +extern unsigned long iram_tlb_phys_addr; + +extern unsigned long mx6_ddr3_freq_change_start asm("mx6_ddr3_freq_change_start"); +extern unsigned long mx6_ddr3_freq_change_end asm("mx6_ddr3_freq_change_end"); +extern unsigned long imx6_up_ddr3_freq_change_start asm("imx6_up_ddr3_freq_change_start"); +extern unsigned long imx6_up_ddr3_freq_change_end asm("imx6_up_ddr3_freq_change_end"); + +#ifdef CONFIG_SMP +static unsigned long wfe_freq_change_iram_base; +volatile u32 *wait_for_ddr_freq_update; +static unsigned int online_cpus; +static u32 *irqs_used; + +void (*wfe_change_ddr_freq)(u32 cpuid, u32 *ddr_freq_change_done); +void (*imx7_wfe_change_ddr_freq)(u32 cpuid, u32 ocram_base); +extern void wfe_smp_freq_change(u32 cpuid, u32 *ddr_freq_change_done); +extern void imx7_smp_wfe(u32 cpuid, u32 ocram_base); +extern unsigned long wfe_smp_freq_change_start asm("wfe_smp_freq_change_start"); +extern unsigned long wfe_smp_freq_change_end asm("wfe_smp_freq_change_end"); +extern void __iomem *scu_base; +#endif + +unsigned long ddr3_dll_mx6sx[][2] = { + {0x0c, 0x0}, + {0x10, 0x0}, + {0x1C, 0x04008032}, + {0x1C, 0x00048031}, + {0x1C, 0x05208030}, + {0x1C, 0x04008040}, + {0x818, 0x0}, + {0x18, 0x0}, +}; + +unsigned long ddr3_calibration_mx6sx[][2] = { + {0x83c, 0x0}, + {0x840, 0x0}, + {0x848, 0x0}, + {0x850, 0x0}, +}; + +unsigned long iomux_offsets_mx6sx[][2] = { + {0x330, 0x0}, + {0x334, 0x0}, + {0x338, 0x0}, + {0x33c, 0x0}, +}; + +unsigned long iomux_offsets_mx6ul[][2] = { + {0x280, 0x0}, + {0x284, 0x0}, +}; + +unsigned long ddr3_dll_mx6q[][2] = { + {0x0c, 0x0}, + {0x10, 0x0}, + {0x1C, 0x04088032}, + {0x1C, 0x0408803a}, + {0x1C, 0x08408030}, + {0x1C, 0x08408038}, + {0x818, 0x0}, + {0x18, 0x0}, +}; + +unsigned long ddr3_calibration[][2] = { + {0x83c, 0x0}, + {0x840, 0x0}, + {0x483c, 0x0}, + {0x4840, 0x0}, + {0x848, 0x0}, + {0x4848, 0x0}, + {0x850, 0x0}, + {0x4850, 0x0}, +}; + +unsigned long iomux_offsets_mx6q[][2] = { + {0x5A8, 0x0}, + {0x5B0, 0x0}, + {0x524, 0x0}, + {0x51C, 0x0}, + {0x518, 0x0}, + {0x50C, 0x0}, + {0x5B8, 0x0}, + {0x5C0, 0x0}, +}; + +unsigned long ddr3_dll_mx6dl[][2] = { + {0x0c, 0x0}, + {0x10, 0x0}, + {0x1C, 0x04008032}, + {0x1C, 0x0400803a}, + {0x1C, 0x07208030}, + {0x1C, 0x07208038}, + {0x818, 0x0}, + {0x18, 0x0}, +}; + +unsigned long iomux_offsets_mx6dl[][2] = { + {0x4BC, 0x0}, + {0x4C0, 0x0}, + {0x4C4, 0x0}, + {0x4C8, 0x0}, + {0x4CC, 0x0}, + {0x4D0, 0x0}, + {0x4D4, 0x0}, + {0x4D8, 0x0}, +}; + +int can_change_ddr_freq(void) +{ + return 1; +} + +#ifdef CONFIG_SMP +/* + * each active core apart from the one changing + * the DDR frequency will execute this function. + * the rest of the cores have to remain in WFE + * state until the frequency is changed. + */ +static irqreturn_t wait_in_wfe_irq(int irq, void *dev_id) +{ + u32 me; + + me = smp_processor_id(); +#ifdef CONFIG_LOCAL_TIMERS + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, + &me); +#endif + if (cpu_is_imx7d()) + imx7_wfe_change_ddr_freq(0x8 * me, + (u32)ddr_freq_change_iram_base); + else + wfe_change_ddr_freq(0xff << (me * 8), + (u32 *)&iram_iomux_settings[0][1]); +#ifdef CONFIG_LOCAL_TIMERS + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, + &me); +#endif + + return IRQ_HANDLED; +} +#endif + +/* change the DDR frequency. */ +int update_ddr_freq_imx_smp(int ddr_rate) +{ + int me = 0; + unsigned long ttbr1; + bool dll_off = false; + int i; +#ifdef CONFIG_SMP + unsigned int reg = 0; + int cpu = 0; +#endif + int mode = get_bus_freq_mode(); + + if (!can_change_ddr_freq()) + return -1; + + if (ddr_rate == curr_ddr_rate) + return 0; + + printk(KERN_DEBUG "\nBus freq set to %d start...\n", ddr_rate); + + if (cpu_is_imx6()) { + if ((mode == BUS_FREQ_LOW) || (mode == BUS_FREQ_AUDIO)) + dll_off = true; + + iram_ddr_settings[0][0] = ddr_settings_size; + iram_iomux_settings[0][0] = iomux_settings_size; + if (ddr_rate == ddr_normal_rate) { + for (i = 0; i < iram_ddr_settings[0][0]; i++) { + iram_ddr_settings[i + 1][0] = + normal_mmdc_settings[i][0]; + iram_ddr_settings[i + 1][1] = + normal_mmdc_settings[i][1]; + } + } + } + + /* ensure that all Cores are in WFE. */ + local_irq_disable(); + +#ifdef CONFIG_SMP + me = smp_processor_id(); + + /* Make sure all the online cores are active */ + while (1) { + bool not_exited_busfreq = false; + u32 reg = 0; + + for_each_online_cpu(cpu) { + if (cpu_is_imx7d()) + reg = *(wait_for_ddr_freq_update + 1); + else if (cpu_is_imx6()) + reg = __raw_readl(scu_base + 0x08); + + if (reg & (0x02 << (cpu * 8))) + not_exited_busfreq = true; + } + if (!not_exited_busfreq) + break; + } + + wmb(); + *wait_for_ddr_freq_update = 1; + dsb(); + if (cpu_is_imx7d()) + online_cpus = *(wait_for_ddr_freq_update + 1); + else if (cpu_is_imx6()) + online_cpus = readl_relaxed(scu_base + 0x08); + for_each_online_cpu(cpu) { + *((char *)(&online_cpus) + (u8)cpu) = 0x02; + if (cpu != me) { + /* set the interrupt to be pending in the GIC. */ + reg = 1 << (irqs_used[cpu] % 32); + writel_relaxed(reg, gic_dist_base + GIC_DIST_PENDING_SET + + (irqs_used[cpu] / 32) * 4); + } + } + /* Wait for the other active CPUs to idle */ + while (1) { + u32 reg = 0; + + if (cpu_is_imx7d()) + reg = *(wait_for_ddr_freq_update + 1); + else if (cpu_is_imx6()) + reg = readl_relaxed(scu_base + 0x08); + reg |= (0x02 << (me * 8)); + if (reg == online_cpus) + break; + } +#endif + + /* Ensure iram_tlb_phys_addr is flushed to DDR. */ + __cpuc_flush_dcache_area(&iram_tlb_phys_addr, + sizeof(iram_tlb_phys_addr)); + if (cpu_is_imx6()) + outer_clean_range(__pa(&iram_tlb_phys_addr), + __pa(&iram_tlb_phys_addr + 1)); + + ttbr1 = save_ttbr1(); + /* Now we can change the DDR frequency. */ + if (cpu_is_imx7d()) + imx7d_change_ddr_freq(ddr_rate); + else if (cpu_is_imx6()) + mx6_change_ddr_freq(ddr_rate, iram_ddr_settings, + dll_off, iram_iomux_settings); + restore_ttbr1(ttbr1); + curr_ddr_rate = ddr_rate; + +#ifdef CONFIG_SMP + wmb(); + /* DDR frequency change is done . */ + *wait_for_ddr_freq_update = 0; + dsb(); + + /* wake up all the cores. */ + sev(); +#endif + + local_irq_enable(); + + printk(KERN_DEBUG "Bus freq set to %d done! cpu=%d\n", ddr_rate, me); + + return 0; +} + +/* Used by i.MX6SX/i.MX6UL for updating the ddr frequency */ +int update_ddr_freq_imx6_up(int ddr_rate) +{ + int i; + bool dll_off = false; + unsigned long ttbr1; + int mode = get_bus_freq_mode(); + + if (ddr_rate == curr_ddr_rate) + return 0; + + printk(KERN_DEBUG "\nBus freq set to %d start...\n", ddr_rate); + + if ((mode == BUS_FREQ_LOW) || (mode == BUS_FREQ_AUDIO)) + dll_off = true; + + imx6_busfreq_info->dll_off = dll_off; + iram_ddr_settings[0][0] = ddr_settings_size; + iram_iomux_settings[0][0] = iomux_settings_size; + for (i = 0; i < iram_ddr_settings[0][0]; i++) { + iram_ddr_settings[i + 1][0] = + normal_mmdc_settings[i][0]; + iram_ddr_settings[i + 1][1] = + normal_mmdc_settings[i][1]; + } + + local_irq_disable(); + + ttbr1 = save_ttbr1(); + imx6_busfreq_info->freq = ddr_rate; + imx6_busfreq_info->ddr_settings = iram_ddr_settings; + imx6_busfreq_info->iomux_offsets = iram_iomux_settings; + imx6_busfreq_info->mu_delay_val = ((readl_relaxed(mmdc_base + MMDC0_MPMUR0) + >> MMDC0_MPMUR0_OFFSET) & MMDC0_MPMUR0_MASK); + + imx6_up_change_ddr_freq(imx6_busfreq_info); + restore_ttbr1(ttbr1); + curr_ddr_rate = ddr_rate; + + local_irq_enable(); + + printk(KERN_DEBUG "Bus freq set to %d done!\n", ddr_rate); + + return 0; +} + +int init_ddrc_ddr_settings(struct platform_device *busfreq_pdev) +{ + int ddr_type = imx_ddrc_get_ddr_type(); +#ifdef CONFIG_SMP + struct device_node *node; + u32 cpu; + struct device *dev = &busfreq_pdev->dev; + int err; + struct irq_data *d; + + node = of_find_compatible_node(NULL, NULL, "arm,cortex-a7-gic"); + if (!node) { + printk(KERN_ERR "failed to find imx7d-a7-gic device tree data!\n"); + return -EINVAL; + } + gic_dist_base = of_iomap(node, 0); + WARN(!gic_dist_base, "unable to map gic dist registers\n"); + + irqs_used = devm_kzalloc(dev, sizeof(u32) * num_present_cpus(), + GFP_KERNEL); + for_each_online_cpu(cpu) { + int irq; + /* + * set up a reserved interrupt to get all + * the active cores into a WFE state + * before changing the DDR frequency. + */ + irq = platform_get_irq(busfreq_pdev, cpu); + err = request_irq(irq, wait_in_wfe_irq, + IRQF_PERCPU, "ddrc", NULL); + if (err) { + dev_err(dev, + "Busfreq:request_irq failed %d, err = %d\n", + irq, err); + return err; + } + err = irq_set_affinity(irq, cpumask_of(cpu)); + if (err) { + dev_err(dev, + "Busfreq: Cannot set irq affinity irq=%d\n", + irq); + return err; + } + d = irq_get_irq_data(irq); + irqs_used[cpu] = d->hwirq + 32; + } + + /* Store the variable used to communicate between cores */ + wait_for_ddr_freq_update = (u32 *)ddr_freq_change_iram_base; + imx7_wfe_change_ddr_freq = (void *)fncpy( + (void *)ddr_freq_change_iram_base + 0x8, + &imx7_smp_wfe, SMP_WFE_CODE_SIZE - 0x8); +#endif + if (ddr_type == IMX_DDR_TYPE_DDR3) + imx7d_change_ddr_freq = (void *)fncpy( + (void *)ddr_freq_change_iram_base + SMP_WFE_CODE_SIZE, + &imx7d_ddr3_freq_change, + MX7_BUSFREQ_OCRAM_SIZE - SMP_WFE_CODE_SIZE); + else if (ddr_type == IMX_DDR_TYPE_LPDDR3 + || ddr_type == IMX_DDR_TYPE_LPDDR2) + imx7d_change_ddr_freq = (void *)fncpy( + (void *)ddr_freq_change_iram_base + + SMP_WFE_CODE_SIZE, + &imx_lpddr3_freq_change, + MX7_BUSFREQ_OCRAM_SIZE - SMP_WFE_CODE_SIZE); + + curr_ddr_rate = ddr_normal_rate; + + return 0; +} + +/* Used by i.MX6SX/i.MX6UL for mmdc setting init. */ +int init_mmdc_ddr3_settings_imx6_up(struct platform_device *busfreq_pdev) +{ + int i; + struct device_node *node; + unsigned long ddr_code_size; + + node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-mmdc"); + if (!node) { + printk(KERN_ERR "failed to find mmdc device tree data!\n"); + return -EINVAL; + } + mmdc_base = of_iomap(node, 0); + WARN(!mmdc_base, "unable to map mmdc registers\n"); + + if (cpu_is_imx6sx()) + node = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-iomuxc"); + else + node = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-iomuxc"); + if (!node) { + printk(KERN_ERR "failed to find iomuxc device tree data!\n"); + return -EINVAL; + } + iomux_base = of_iomap(node, 0); + WARN(!iomux_base, "unable to map iomux registers\n"); + + ddr_settings_size = ARRAY_SIZE(ddr3_dll_mx6sx) + + ARRAY_SIZE(ddr3_calibration_mx6sx); + + normal_mmdc_settings = kmalloc((ddr_settings_size * 8), GFP_KERNEL); + memcpy(normal_mmdc_settings, ddr3_dll_mx6sx, + sizeof(ddr3_dll_mx6sx)); + memcpy(((char *)normal_mmdc_settings + sizeof(ddr3_dll_mx6sx)), + ddr3_calibration_mx6sx, sizeof(ddr3_calibration_mx6sx)); + + /* store the original DDR settings at boot. */ + for (i = 0; i < ddr_settings_size; i++) { + /* + * writes via command mode register cannot be read back. + * hence hardcode them in the initial static array. + * this may require modification on a per customer basis. + */ + if (normal_mmdc_settings[i][0] != 0x1C) + normal_mmdc_settings[i][1] = + readl_relaxed(mmdc_base + + normal_mmdc_settings[i][0]); + } + + if (cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx6ulz()) + iomux_settings_size = ARRAY_SIZE(iomux_offsets_mx6ul); + else + iomux_settings_size = ARRAY_SIZE(iomux_offsets_mx6sx); + + ddr_code_size = (&imx6_up_ddr3_freq_change_end -&imx6_up_ddr3_freq_change_start) *4 + + sizeof(*imx6_busfreq_info); + imx6_busfreq_info = (struct imx6_busfreq_info *)ddr_freq_change_iram_base; + + imx6_up_change_ddr_freq = (void *)fncpy((void *)ddr_freq_change_iram_base + sizeof(*imx6_busfreq_info), + &imx6_up_ddr3_freq_change, ddr_code_size - sizeof(*imx6_busfreq_info)); + + /* + * Store the size of the array in iRAM also, + * increase the size by 8 bytes. + */ + iram_iomux_settings = (void *)(ddr_freq_change_iram_base + ddr_code_size); + iram_ddr_settings = iram_iomux_settings + (iomux_settings_size * 8) + 8; + + if ((ddr_code_size + (iomux_settings_size + ddr_settings_size) * 8 + 16) + > ddr_freq_change_total_size) { + printk(KERN_ERR "Not enough memory allocated for DDR Frequency change code.\n"); + return EINVAL; + } + + for (i = 0; i < iomux_settings_size; i++) { + if (cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx6ulz()) { + iomux_offsets_mx6ul[i][1] = + readl_relaxed(iomux_base + + iomux_offsets_mx6ul[i][0]); + iram_iomux_settings[i + 1][0] = + iomux_offsets_mx6ul[i][0]; + iram_iomux_settings[i + 1][1] = + iomux_offsets_mx6ul[i][1]; + } else { + iomux_offsets_mx6sx[i][1] = + readl_relaxed(iomux_base + + iomux_offsets_mx6sx[i][0]); + iram_iomux_settings[i + 1][0] = + iomux_offsets_mx6sx[i][0]; + iram_iomux_settings[i + 1][1] = + iomux_offsets_mx6sx[i][1]; + } + } + + curr_ddr_rate = ddr_normal_rate; + + return 0; +} + +int init_mmdc_ddr3_settings_imx6_smp(struct platform_device *busfreq_pdev) +{ + int i; + struct device_node *node; + unsigned long ddr_code_size; + unsigned long wfe_code_size = 0; +#ifdef CONFIG_SMP + u32 cpu; + struct device *dev = &busfreq_pdev->dev; + int err; + struct irq_data *d; +#endif + + node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-mmdc-combine"); + if (!node) { + printk(KERN_ERR "failed to find imx6q-mmdc device tree data!\n"); + return -EINVAL; + } + mmdc_base = of_iomap(node, 0); + WARN(!mmdc_base, "unable to map mmdc registers\n"); + + node = NULL; + if (cpu_is_imx6q()) + node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-iomuxc"); + if (cpu_is_imx6dl()) + node = of_find_compatible_node(NULL, NULL, + "fsl,imx6dl-iomuxc"); + if (!node) { + printk(KERN_ERR "failed to find imx6q-iomux device tree data!\n"); + return -EINVAL; + } + iomux_base = of_iomap(node, 0); + WARN(!iomux_base, "unable to map iomux registers\n"); + + node = NULL; + node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic"); + if (!node) { + printk(KERN_ERR "failed to find imx6q-a9-gic device tree data!\n"); + return -EINVAL; + } + gic_dist_base = of_iomap(node, 0); + WARN(!gic_dist_base, "unable to map gic dist registers\n"); + + if (cpu_is_imx6q()) + ddr_settings_size = ARRAY_SIZE(ddr3_dll_mx6q) + + ARRAY_SIZE(ddr3_calibration); + if (cpu_is_imx6dl()) + ddr_settings_size = ARRAY_SIZE(ddr3_dll_mx6dl) + + ARRAY_SIZE(ddr3_calibration); + + normal_mmdc_settings = kmalloc((ddr_settings_size * 8), GFP_KERNEL); + if (cpu_is_imx6q()) { + memcpy(normal_mmdc_settings, ddr3_dll_mx6q, + sizeof(ddr3_dll_mx6q)); + memcpy(((char *)normal_mmdc_settings + sizeof(ddr3_dll_mx6q)), + ddr3_calibration, sizeof(ddr3_calibration)); + } + if (cpu_is_imx6dl()) { + memcpy(normal_mmdc_settings, ddr3_dll_mx6dl, + sizeof(ddr3_dll_mx6dl)); + memcpy(((char *)normal_mmdc_settings + sizeof(ddr3_dll_mx6dl)), + ddr3_calibration, sizeof(ddr3_calibration)); + } + /* store the original DDR settings at boot. */ + for (i = 0; i < ddr_settings_size; i++) { + /* + * writes via command mode register cannot be read back. + * hence hardcode them in the initial static array. + * this may require modification on a per customer basis. + */ + if (normal_mmdc_settings[i][0] != 0x1C) + normal_mmdc_settings[i][1] = + readl_relaxed(mmdc_base + + normal_mmdc_settings[i][0]); + } + +#ifdef CONFIG_SMP + irqs_used = devm_kzalloc(dev, sizeof(u32) * num_present_cpus(), + GFP_KERNEL); + + for_each_online_cpu(cpu) { + int irq; + + /* + * set up a reserved interrupt to get all + * the active cores into a WFE state + * before changing the DDR frequency. + */ + irq = platform_get_irq(busfreq_pdev, cpu); + err = request_irq(irq, wait_in_wfe_irq, + IRQF_PERCPU, "mmdc_1", NULL); + if (err) { + dev_err(dev, + "Busfreq:request_irq failed %d, err = %d\n", + irq, err); + return err; + } + err = irq_set_affinity(irq, cpumask_of(cpu)); + if (err) { + dev_err(dev, + "Busfreq: Cannot set irq affinity irq=%d,\n", + irq); + return err; + } + d = irq_get_irq_data(irq); + irqs_used[cpu] = d->hwirq + 32; + } +#endif + iomux_settings_size = ARRAY_SIZE(iomux_offsets_mx6q); + + ddr_code_size = (&mx6_ddr3_freq_change_end - + &mx6_ddr3_freq_change_start) * 4; + + mx6_change_ddr_freq = (void *)fncpy((void *)ddr_freq_change_iram_base, + &mx6_ddr3_freq_change, ddr_code_size); + + /* + * Store the size of the array in iRAM also, + * increase the size by 8 bytes. + */ + iram_iomux_settings = (void *)(ddr_freq_change_iram_base + + ddr_code_size); + iram_ddr_settings = iram_iomux_settings + (iomux_settings_size * 8) + 8; +#ifdef CONFIG_SMP + wfe_freq_change_iram_base = (unsigned long)((u32 *)iram_ddr_settings + + (ddr_settings_size * 8) + 8); + + if (wfe_freq_change_iram_base & (FNCPY_ALIGN - 1)) + wfe_freq_change_iram_base += FNCPY_ALIGN - + ((uintptr_t)wfe_freq_change_iram_base % (FNCPY_ALIGN)); + + wfe_code_size = (&wfe_smp_freq_change_end - + &wfe_smp_freq_change_start) *4; + + wfe_change_ddr_freq = (void *)fncpy((void *)wfe_freq_change_iram_base, + &wfe_smp_freq_change, wfe_code_size); + + /* + * Store the variable used to communicate + * between cores in a non-cacheable IRAM area + */ + wait_for_ddr_freq_update = (u32 *)&iram_iomux_settings[0][1]; +#endif + + if ((ddr_code_size + wfe_code_size + (iomux_settings_size + + ddr_settings_size) * 8 + 16) + > ddr_freq_change_total_size) { + printk(KERN_ERR "Not enough memory for DDR Freq scale.\n"); + return EINVAL; + } + + if (cpu_is_imx6q()) { + /* store the IOMUX settings at boot. */ + for (i = 0; i < iomux_settings_size; i++) { + iomux_offsets_mx6q[i][1] = + readl_relaxed(iomux_base + + iomux_offsets_mx6q[i][0]); + iram_iomux_settings[i + 1][0] = + iomux_offsets_mx6q[i][0]; + iram_iomux_settings[i + 1][1] = + iomux_offsets_mx6q[i][1]; + } + } + + if (cpu_is_imx6dl()) { + for (i = 0; i < iomux_settings_size; i++) { + iomux_offsets_mx6dl[i][1] = + readl_relaxed(iomux_base + + iomux_offsets_mx6dl[i][0]); + iram_iomux_settings[i + 1][0] = + iomux_offsets_mx6dl[i][0]; + iram_iomux_settings[i + 1][1] = + iomux_offsets_mx6dl[i][1]; + } + } + + curr_ddr_rate = ddr_normal_rate; + + return 0; +} diff --git a/arch/arm/mach-imx/busfreq_lpddr2.c b/arch/arm/mach-imx/busfreq_lpddr2.c new file mode 100644 index 00000000000000..f5b3caa4364539 --- /dev/null +++ b/arch/arm/mach-imx/busfreq_lpddr2.c @@ -0,0 +1,374 @@ +/* + * Copyright (C) 2011-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file busfreq_lpddr2.c + * + * @brief iMX6 LPDDR2 frequency change specific file. + * + * @ingroup PM + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" +#include "hardware.h" + +static struct device *busfreq_dev; +static int curr_ddr_rate; +static DEFINE_SPINLOCK(freq_lock); + +void (*mx6_change_lpddr2_freq)(u32 ddr_freq, int bus_freq_mode) = NULL; + +extern unsigned int ddr_normal_rate; +extern void mx6_lpddr2_freq_change(u32 freq, int bus_freq_mode); +extern void imx6_up_lpddr2_freq_change(u32 freq, int bus_freq_mode); +extern void imx6sll_lpddr2_freq_change(u32 freq, int bus_freq_mode); +extern unsigned long save_ttbr1(void); +extern void restore_ttbr1(unsigned long ttbr1); +extern void mx6q_lpddr2_freq_change(u32 freq, void *ddr_settings); +extern unsigned long ddr_freq_change_iram_base; +extern unsigned long imx6_lpddr2_freq_change_start asm("imx6_lpddr2_freq_change_start"); +extern unsigned long imx6_lpddr2_freq_change_end asm("imx6_lpddr2_freq_change_end"); +extern unsigned long mx6q_lpddr2_freq_change_start asm("mx6q_lpddr2_freq_change_start"); +extern unsigned long mx6q_lpddr2_freq_change_end asm("mx6q_lpddr2_freq_change_end"); +extern unsigned long iram_tlb_phys_addr; + +struct mmdc_settings_info { + u32 size; + void *settings; + int freq; +} __aligned(8); +static struct mmdc_settings_info *mmdc_settings_info; +void (*mx6_change_lpddr2_freq_smp)(u32 ddr_freq, struct mmdc_settings_info + *mmdc_settings_info) = NULL; + +static int mmdc_settings_size; +static unsigned long (*mmdc_settings)[2]; +static unsigned long (*iram_mmdc_settings)[2]; +static unsigned long *iram_settings_size; +static unsigned long *iram_ddr_freq_chage; +unsigned long mmdc_timing_settings[][2] = { + {0x0C, 0x0}, /* mmdc_mdcfg0 */ + {0x10, 0x0}, /* mmdc_mdcfg1 */ + {0x14, 0x0}, /* mmdc_mdcfg2 */ + {0x18, 0x0}, /* mmdc_mdmisc */ + {0x38, 0x0}, /* mmdc_mdcfg3lp */ +}; + +#ifdef CONFIG_SMP +volatile u32 *wait_for_lpddr2_freq_update; +static unsigned int online_cpus; +static u32 *irqs_used; +void (*wfe_change_lpddr2_freq)(u32 cpuid, u32 *ddr_freq_change_done); +extern void wfe_smp_freq_change(u32 cpuid, u32 *ddr_freq_change_done); +extern unsigned long wfe_smp_freq_change_start asm("wfe_smp_freq_change_start"); +extern unsigned long wfe_smp_freq_change_end asm("wfe_smp_freq_change_end"); +extern void __iomem *scu_base; +static void __iomem *gic_dist_base; +#endif + +#ifdef CONFIG_SMP +static irqreturn_t wait_in_wfe_irq(int irq, void *dev_id) +{ + u32 me; + + me = smp_processor_id(); +#ifdef CONFIG_LOCAL_TIMERS + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &me); +#endif + wfe_change_lpddr2_freq(0xff << (me * 8), + (u32 *)ddr_freq_change_iram_base); +#ifdef CONFIG_LOCAL_TIMERS + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &me); +#endif + return IRQ_HANDLED; +} +#endif + +/* change the DDR frequency. */ +int update_lpddr2_freq(int ddr_rate) +{ + unsigned long ttbr1, flags; + int mode = get_bus_freq_mode(); + + if (ddr_rate == curr_ddr_rate) + return 0; + + printk(KERN_DEBUG "\nBus freq set to %d start...\n", ddr_rate); + + spin_lock_irqsave(&freq_lock, flags); + /* + * Flush the TLB, to ensure no TLB maintenance occurs + * when DDR is in self-refresh. + */ + ttbr1 = save_ttbr1(); + + /* Now change DDR frequency. */ + if (cpu_is_imx6sl()) + mx6_change_lpddr2_freq(ddr_rate, + (mode == BUS_FREQ_LOW || mode == BUS_FREQ_ULTRA_LOW) ? 1 : 0); + else + mx6_change_lpddr2_freq(ddr_rate, + (mode == BUS_FREQ_LOW || mode == BUS_FREQ_AUDIO) ? 1 : 0); + + restore_ttbr1(ttbr1); + + curr_ddr_rate = ddr_rate; + spin_unlock_irqrestore(&freq_lock, flags); + + printk(KERN_DEBUG "\nBus freq set to %d done...\n", ddr_rate); + + return 0; +} + +int init_mmdc_lpddr2_settings(struct platform_device *busfreq_pdev) +{ + unsigned long ddr_code_size; + busfreq_dev = &busfreq_pdev->dev; + + ddr_code_size = SZ_4K; + + if (cpu_is_imx6sl()) + mx6_change_lpddr2_freq = (void *)fncpy( + (void *)ddr_freq_change_iram_base, + &mx6_lpddr2_freq_change, ddr_code_size); + if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || + cpu_is_imx6ulz()) + mx6_change_lpddr2_freq = (void *)fncpy( + (void *)ddr_freq_change_iram_base, + &imx6_up_lpddr2_freq_change, ddr_code_size); + if (cpu_is_imx6sll()) + mx6_change_lpddr2_freq = (void *)fncpy( + (void *)ddr_freq_change_iram_base, + &imx6sll_lpddr2_freq_change, ddr_code_size); + + curr_ddr_rate = ddr_normal_rate; + + return 0; +} + +int update_lpddr2_freq_smp(int ddr_rate) +{ + unsigned long ttbr1; + int i, me = 0; +#ifdef CONFIG_SMP + int cpu = 0; + u32 reg = 0; +#endif + + if (ddr_rate == curr_ddr_rate) + return 0; + + printk(KERN_DEBUG "Bus freq set to %d start...\n", ddr_rate); + + for (i=0; i < mmdc_settings_size; i++) { + iram_mmdc_settings[i][0] = mmdc_settings[i][0]; + iram_mmdc_settings[i][1] = mmdc_settings[i][1]; + } + + mmdc_settings_info->size = mmdc_settings_size; + mmdc_settings_info->settings = iram_mmdc_settings; + mmdc_settings_info->freq = curr_ddr_rate; + + /* ensure that all Cores are in WFE. */ + local_irq_disable(); + +#ifdef CONFIG_SMP + me = smp_processor_id(); + + /* Make sure all the online cores are active */ + while (1) { + bool not_exited_busfreq = false; + for_each_online_cpu(cpu) { + reg = __raw_readl(scu_base + 0x08); + if (reg & (0x02 << (cpu * 8))) + not_exited_busfreq = true; + } + if (!not_exited_busfreq) + break; + } + + wmb(); + *wait_for_lpddr2_freq_update = 1; + dsb(); + online_cpus = readl_relaxed(scu_base + 0x08); + for_each_online_cpu(cpu) { + *((char *)(&online_cpus) + (u8)cpu) = 0x02; + if (cpu != me) { + reg = 1 << (irqs_used[cpu] % 32); + writel_relaxed(reg, gic_dist_base + GIC_DIST_PENDING_SET + + (irqs_used[cpu] / 32) * 4); + } + } + + /* Wait for the other active CPUs to idle */ + while (1) { + reg = 0; + reg = readl_relaxed(scu_base + 0x08); + reg |= (0x02 << (me * 8)); + if (reg == online_cpus) + break; + } +#endif + + /* Ensure iram_tlb_phys_addr is flushed to DDR. */ + __cpuc_flush_dcache_area(&iram_tlb_phys_addr, + sizeof(iram_tlb_phys_addr)); + outer_clean_range(__pa(&iram_tlb_phys_addr), + __pa(&iram_tlb_phys_addr + 1)); + /* + * Flush the TLB, to ensure no TLB maintenance occurs + * when DDR is in self-refresh. + */ + ttbr1 = save_ttbr1(); + + curr_ddr_rate = ddr_rate; + + /* Now change DDR frequency. */ + mx6_change_lpddr2_freq_smp(ddr_rate, mmdc_settings_info); + + restore_ttbr1(ttbr1); + +#ifdef CONFIG_SMP + wmb(); + /* DDR frequency change is done . */ + *wait_for_lpddr2_freq_update = 0; + dsb(); + /* wake up all the cores. */ + sev(); +#endif + + local_irq_enable(); + + printk(KERN_DEBUG "Bus freq set to %d done! cpu=%d\n", ddr_rate, me); + + return 0; +} + +int init_mmdc_lpddr2_settings_mx6q(struct platform_device *busfreq_pdev) +{ + struct device *dev = &busfreq_pdev->dev; + unsigned long ddr_code_size = 0; + unsigned long wfe_code_size = 0; + struct device_node *node; + void __iomem *mmdc_base; + int i; +#ifdef CONFIG_SMP + struct irq_data *d; + u32 cpu; + int err; +#endif + + node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-mmdc"); + if (!node) { + printk(KERN_ERR "failed to find mmdc device tree data!\n"); + return -EINVAL; + } + + mmdc_base = of_iomap(node, 0); + if (!mmdc_base) { + dev_err(dev, "unable to map mmdc registers\n"); + return -EINVAL; + } + + mmdc_settings_size = ARRAY_SIZE(mmdc_timing_settings); + mmdc_settings = kmalloc((mmdc_settings_size * 8), GFP_KERNEL); + memcpy(mmdc_settings, mmdc_timing_settings, + sizeof(mmdc_timing_settings)); + +#ifdef CONFIG_SMP + node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic"); + if (!node) { + printk(KERN_ERR "failed to find imx6q-a9-gic device tree data!\n"); + return -EINVAL; + } + + gic_dist_base = of_iomap(node, 0); + WARN(!gic_dist_base, "unable to map gic dist registers\n"); + + irqs_used = devm_kzalloc(dev, sizeof(u32) * num_present_cpus(), + GFP_KERNEL); + + for_each_online_cpu(cpu) { + int irq = platform_get_irq(busfreq_pdev, cpu); + err = request_irq(irq, wait_in_wfe_irq, IRQF_PERCPU, + "mmdc_1", NULL); + if (err) { + dev_err(dev, + "Busfreq:request_irq failed %d, err = %d\n", + irq, err); + return err; + } + err = irq_set_affinity(irq, cpumask_of(cpu)); + if (err) { + dev_err(dev, + "Busfreq: Cannot set irq affinity irq=%d,\n", + irq); + return err; + } + d = irq_get_irq_data(irq); + irqs_used[cpu] = d->hwirq + 32; + } + + /* Stoange_iram_basee the variable used to communicate between cores in + * a non-cacheable IRAM area */ + wait_for_lpddr2_freq_update = (u32 *)ddr_freq_change_iram_base; + wfe_code_size = (&wfe_smp_freq_change_end - &wfe_smp_freq_change_start) *4; + + wfe_change_lpddr2_freq = (void *)fncpy((void *)ddr_freq_change_iram_base + 0x8, + &wfe_smp_freq_change, wfe_code_size); +#endif + iram_settings_size = (void *)ddr_freq_change_iram_base + wfe_code_size + 0x8; + iram_mmdc_settings = (void *)iram_settings_size + sizeof(*mmdc_settings_info); + iram_ddr_freq_chage = (void *)iram_mmdc_settings + (mmdc_settings_size * 8) + 0x8; + mmdc_settings_info = (struct mmdc_settings_info *)iram_settings_size; + + ddr_code_size = (&mx6q_lpddr2_freq_change_end -&mx6q_lpddr2_freq_change_start) *4; + + mx6_change_lpddr2_freq_smp = (void *)fncpy(iram_ddr_freq_chage, + &mx6q_lpddr2_freq_change, ddr_code_size); + + /* save initial mmdc boot timing settings */ + for (i=0; i < mmdc_settings_size; i++) + mmdc_settings[i][1] = readl_relaxed(mmdc_base + + mmdc_settings[i][0]); + + curr_ddr_rate = ddr_normal_rate; + + return 0; +} diff --git a/arch/arm/mach-imx/common.c b/arch/arm/mach-imx/common.c new file mode 100644 index 00000000000000..2f644c6b2c28c7 --- /dev/null +++ b/arch/arm/mach-imx/common.c @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include + +#include "hardware.h" + +unsigned long iram_tlb_base_addr; +unsigned long iram_tlb_phys_addr; + +unsigned long save_ttbr1(void) +{ + unsigned long lttbr1; + asm volatile( + ".align 4\n" + "mrc p15, 0, %0, c2, c0, 1\n" + : "=r" (lttbr1) + ); + return lttbr1; +} + +void restore_ttbr1(unsigned long ttbr1) +{ + asm volatile( + ".align 4\n" + "mcr p15, 0, %0, c2, c0, 1\n" + : : "r" (ttbr1) + ); +} + +#define OCOTP_MAC_OFF (cpu_is_imx7d() ? 0x640 : 0x620) +#define OCOTP_MACn(n) (OCOTP_MAC_OFF + (n) * 0x10) +void __init imx6_enet_mac_init(const char *enet_compat, const char *ocotp_compat) +{ + struct device_node *ocotp_np, *enet_np, *from = NULL; + void __iomem *base; + struct property *newmac; + u32 macaddr_low; + u32 macaddr_high = 0; + u32 macaddr1_high = 0; + u8 *macaddr; + int i, id; + + for (i = 0; i < 2; i++) { + enet_np = of_find_compatible_node(from, NULL, enet_compat); + if (!enet_np) + return; + + from = enet_np; + + if (of_get_mac_address(enet_np)) + goto put_enet_node; + + id = of_alias_get_id(enet_np, "ethernet"); + if (id < 0) + id = i; + + ocotp_np = of_find_compatible_node(NULL, NULL, ocotp_compat); + if (!ocotp_np) { + pr_warn("failed to find ocotp node\n"); + goto put_enet_node; + } + + base = of_iomap(ocotp_np, 0); + if (!base) { + pr_warn("failed to map ocotp\n"); + goto put_ocotp_node; + } + + macaddr_low = readl_relaxed(base + OCOTP_MACn(1)); + if (id) + macaddr1_high = readl_relaxed(base + OCOTP_MACn(2)); + else + macaddr_high = readl_relaxed(base + OCOTP_MACn(0)); + + newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL); + if (!newmac) + goto put_ocotp_node; + + newmac->value = newmac + 1; + newmac->length = 6; + newmac->name = kstrdup("local-mac-address", GFP_KERNEL); + if (!newmac->name) { + kfree(newmac); + goto put_ocotp_node; + } + + macaddr = newmac->value; + if (id) { + macaddr[5] = (macaddr_low >> 16) & 0xff; + macaddr[4] = (macaddr_low >> 24) & 0xff; + macaddr[3] = macaddr1_high & 0xff; + macaddr[2] = (macaddr1_high >> 8) & 0xff; + macaddr[1] = (macaddr1_high >> 16) & 0xff; + macaddr[0] = (macaddr1_high >> 24) & 0xff; + } else { + macaddr[5] = macaddr_high & 0xff; + macaddr[4] = (macaddr_high >> 8) & 0xff; + macaddr[3] = (macaddr_high >> 16) & 0xff; + macaddr[2] = (macaddr_high >> 24) & 0xff; + macaddr[1] = macaddr_low & 0xff; + macaddr[0] = (macaddr_low >> 8) & 0xff; + } + + of_update_property(enet_np, newmac); + +put_ocotp_node: + of_node_put(ocotp_np); +put_enet_node: + of_node_put(enet_np); + } +} + +#ifndef CONFIG_HAVE_IMX_GPC +int imx_gpc_mf_request_on(unsigned int irq, unsigned int on) { return 0; } +EXPORT_SYMBOL_GPL(imx_gpc_mf_request_on); +#endif + +#if !defined(CONFIG_SOC_IMX6SL) +u32 imx6_lpddr2_freq_change_start, imx6_lpddr2_freq_change_end; +void mx6_lpddr2_freq_change(u32 freq, int bus_freq_mode) {} +#endif + +#if !defined(CONFIG_SOC_IMX6SLL) +void imx6sll_lpddr2_freq_change(u32 freq, int bus_freq_mode) {} +#endif + +#if !defined(CONFIG_SOC_IMX6SX) && !defined(CONFIG_SOC_IMX6UL) +u32 imx6_up_ddr3_freq_change_start, imx6_up_ddr3_freq_change_end; +struct imx6_busfreq_info { +} __aligned(8); +void imx6_up_ddr3_freq_change(struct imx6_busfreq_info *busfreq_info) {} +void imx6_up_lpddr2_freq_change(u32 freq, int bus_freq_mode) {} +#endif + +#if !defined(CONFIG_SOC_IMX6Q) +u32 mx6_ddr3_freq_change_start, mx6_ddr3_freq_change_end; +u32 mx6q_lpddr2_freq_change_start, mx6q_lpddr2_freq_change_end; +u32 wfe_smp_freq_change_start, wfe_smp_freq_change_end; +void mx6_ddr3_freq_change(u32 freq, void *ddr_settings, + bool dll_mode, void *iomux_offsets) {} +void mx6q_lpddr2_freq_change(u32 freq, void *ddr_settings) {} +void wfe_smp_freq_change(u32 cpuid, u32 *ddr_freq_change_done) {} +#endif + +#if !defined(CONFIG_SOC_IMX7D) +void imx7_smp_wfe(u32 cpuid, u32 ocram_base) {} +void imx7d_ddr3_freq_change(u32 freq) {} +#endif + diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 5aa5796cff0e19..303df4381dedf8 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -8,6 +8,7 @@ #define __ASM_ARCH_MXC_COMMON_H__ #include +#include struct irq_data; struct platform_device; @@ -56,9 +57,19 @@ void imx_gpc_set_arm_power_in_lpm(bool power_off); void imx_gpc_set_l2_mem_power_in_lpm(bool power_off); void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw); void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw); +void imx_gpcv2_pre_suspend(bool arm_power_off); +void imx_gpcv2_post_resume(void); +unsigned int imx_gpcv2_is_mf_mix_off(void); +void imx_gpcv2_enable_wakeup_for_m4(void); +void imx_gpcv2_disable_wakeup_for_m4(void); void imx25_pm_init(void); void imx27_pm_init(void); void imx5_pmu_init(void); +#ifdef CONFIG_HAVE_IMX_MU +int imx_mu_lpm_ready(bool ready); +#else +static inline int imx_mu_lpm_ready(bool ready) { return 0; } +#endif enum mxc_cpu_pwr_mode { WAIT_CLOCKED, /* wfi only */ @@ -89,33 +100,97 @@ void imx_smp_prepare(void); static inline void imx_scu_map_io(void) {} static inline void imx_smp_prepare(void) {} #endif +void imx6sx_set_m4_highfreq(bool high_freq); +void imx_mu_enable_m4_irqs_in_gic(bool enable); +#ifdef CONFIG_HAVE_IMX_GPC +void imx_gpc_add_m4_wake_up_irq(u32 irq, bool enable); +unsigned int imx_gpc_is_m4_sleeping(void); +#else +static inline void imx_gpc_add_m4_wake_up_irq(u32 irq, bool enable) {} +static inline unsigned int imx_gpc_is_m4_sleeping(void) { return 0; } +#endif +#ifdef CONFIG_HAVE_IMX_GPCV2 +int imx_gpcv2_mf_power_on(unsigned int irq, unsigned int on); +void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn); +void imx_gpcv2_add_m4_wake_up_irq(u32 hwirq, bool enable); +#else +static inline int imx_gpcv2_mf_power_on(unsigned int irq, unsigned int on) { return 0; } +static inline void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn) {} +static inline void imx_gpcv2_add_m4_wake_up_irq(u32 hwirq, bool enable) {} +#endif +void imx_gpc_hold_m4_in_sleep(void); +void imx_gpc_release_m4_in_sleep(void); +void __init imx_gpcv2_check_dt(void); +void imx_gpcv2_set_lpm_mode(enum mxc_cpu_pwr_mode mode); +void imx_gpcv2_set_cpu_power_gate_in_idle(bool pdn); +void imx_gpcv2_enable_rbc(bool enable); +bool imx_mu_is_m4_in_low_freq(void); +bool imx_mu_is_m4_in_stop(void); +void imx_mu_set_m4_run_mode(void); void imx_src_init(void); void imx_gpc_pre_suspend(bool arm_power_off); void imx_gpc_post_resume(void); +void imx_gpc_switch_pupscr_clk(bool flag); void imx_gpc_mask_all(void); void imx_gpc_restore_all(void); void imx_gpc_hwirq_mask(unsigned int hwirq); void imx_gpc_hwirq_unmask(unsigned int hwirq); +unsigned int imx_gpc_is_mf_mix_off(void); void imx_anatop_init(void); void imx_anatop_pre_suspend(void); void imx_anatop_post_resume(void); int imx6_set_lpm(enum mxc_cpu_pwr_mode mode); void imx6_set_int_mem_clk_lpm(bool enable); void imx6sl_set_wait_clk(bool enter); +void imx6_enet_mac_init(const char *enet_compat, const char *ocotp_compat); +void imx6sl_low_power_idle(void); +void imx6sll_low_power_idle(void); +void imx6sx_low_power_idle(void); +void imx6ul_low_power_idle(void); +void imx6ull_low_power_idle(void); +void imx7d_low_power_idle(void); +#ifdef CONFIG_HAVE_IMX_MMDC int imx_mmdc_get_ddr_type(void); +int imx_mmdc_get_lpddr2_2ch_mode(void); +#else +static inline int imx_mmdc_get_ddr_type(void) { return 0; } +static inline int imx_mmdc_get_lpddr2_2ch_mode(void) { return 0; } +#endif int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode); +void imx_busfreq_map_io(void); +void imx7_pm_map_io(void); +void imx6_pm_map_io(void); +void imx7ulp_pm_map_io(void); +void imx7ulp_enable_nmi(void); +void imx7ulp_poweroff(void); void imx_cpu_die(unsigned int cpu); int imx_cpu_kill(unsigned int cpu); #ifdef CONFIG_SUSPEND +void v7_cpu_resume(void); +void ca7_cpu_resume(void); void imx53_suspend(void __iomem *ocram_vbase); extern const u32 imx53_suspend_sz; void imx6_suspend(void __iomem *ocram_vbase); +void imx7_suspend(void __iomem *ocram_vbase); +void imx7ulp_cpu_resume(void); +void imx7ulp_suspend(void __iomem *ocram_vbase); #else +static inline void v7_cpu_resume(void) {} +static inline void ca7_cpu_resume(void) {} static inline void imx53_suspend(void __iomem *ocram_vbase) {} static const u32 imx53_suspend_sz; static inline void imx6_suspend(void __iomem *ocram_vbase) {} +static inline void imx7_suspend(void __iomem *ocram_vbase) {} +static inline void imx7ulp_cpu_resume(void) {} +static inline void imx7ulp_suspend(void __iomem *ocram_vbase) {} +#endif + +#ifdef CONFIG_HAVE_IMX_DDRC +int imx_ddrc_get_ddr_type(void); +#else +static inline int imx_ddrc_get_ddr_type(void) { return 0; } #endif void v7_cpu_resume(void); @@ -126,6 +201,7 @@ void imx6dl_pm_init(void); void imx6sl_pm_init(void); void imx6sx_pm_init(void); void imx6ul_pm_init(void); +void imx7d_pm_init(void); void imx7ulp_pm_init(void); #ifdef CONFIG_PM @@ -151,4 +227,5 @@ static inline void imx_init_l2cache(void) {} extern const struct smp_operations imx_smp_ops; extern const struct smp_operations ls1021a_smp_ops; +extern bool uart_from_osc; #endif diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 0b137eeffb6162..cd83ca08826eac 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -1,15 +1,20 @@ // SPDX-License-Identifier: GPL-2.0 #include +#include #include #include #include #include +#include #include #include #include "hardware.h" #include "common.h" +#define OCOTP_UID_H 0x420 +#define OCOTP_UID_L 0x410 + unsigned int __mxc_cpu_type; static unsigned int imx_soc_revision; @@ -76,9 +81,13 @@ void __init imx_aips_allow_unprivileged_access( struct device * __init imx_soc_device_init(void) { struct soc_device_attribute *soc_dev_attr; + const char *ocotp_compat = NULL; struct soc_device *soc_dev; struct device_node *root; + struct regmap *ocotp = NULL; const char *soc_id; + u64 soc_uid = 0; + u32 val; int ret; soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); @@ -119,30 +128,42 @@ struct device * __init imx_soc_device_init(void) soc_id = "i.MX53"; break; case MXC_CPU_IMX6SL: + ocotp_compat = "fsl,imx6sl-ocotp"; soc_id = "i.MX6SL"; break; case MXC_CPU_IMX6DL: + ocotp_compat = "fsl,imx6q-ocotp"; soc_id = "i.MX6DL"; break; case MXC_CPU_IMX6SX: + ocotp_compat = "fsl,imx6sx-ocotp"; soc_id = "i.MX6SX"; break; case MXC_CPU_IMX6Q: - soc_id = "i.MX6Q"; + ocotp_compat = "fsl,imx6q-ocotp"; + if (imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) + soc_id = "i.MX6QP"; + else + soc_id = "i.MX6Q"; break; case MXC_CPU_IMX6UL: + ocotp_compat = "fsl,imx6ul-ocotp"; soc_id = "i.MX6UL"; break; case MXC_CPU_IMX6ULL: + ocotp_compat = "fsl,imx6ull-ocotp"; soc_id = "i.MX6ULL"; break; case MXC_CPU_IMX6ULZ: + ocotp_compat = "fsl,imx6ull-ocotp"; soc_id = "i.MX6ULZ"; break; case MXC_CPU_IMX6SLL: + ocotp_compat = "fsl,imx6sll-ocotp"; soc_id = "i.MX6SLL"; break; case MXC_CPU_IMX7D: + ocotp_compat = "fsl,imx7d-ocotp"; soc_id = "i.MX7D"; break; case MXC_CPU_IMX7ULP: @@ -153,18 +174,38 @@ struct device * __init imx_soc_device_init(void) } soc_dev_attr->soc_id = soc_id; + if (ocotp_compat) { + ocotp = syscon_regmap_lookup_by_compatible(ocotp_compat); + if (IS_ERR(ocotp)) + pr_err("%s: failed to find %s regmap!\n", __func__, ocotp_compat); + } + + if (!IS_ERR_OR_NULL(ocotp)) { + regmap_read(ocotp, OCOTP_UID_H, &val); + soc_uid = val; + regmap_read(ocotp, OCOTP_UID_L, &val); + soc_uid <<= 32; + soc_uid |= val; + } + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d", (imx_soc_revision >> 4) & 0xf, imx_soc_revision & 0xf); if (!soc_dev_attr->revision) goto free_soc; + soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid); + if (!soc_dev_attr->serial_number) + goto free_rev; + soc_dev = soc_device_register(soc_dev_attr); if (IS_ERR(soc_dev)) - goto free_rev; + goto free_serial_number; return soc_device_to_device(soc_dev); +free_serial_number: + kfree(soc_dev_attr->serial_number); free_rev: kfree(soc_dev_attr->revision); free_soc: diff --git a/arch/arm/mach-imx/cpuidle-imx6sl.c b/arch/arm/mach-imx/cpuidle-imx6sl.c index 4521e5352bf648..e54acc2ac8a18e 100644 --- a/arch/arm/mach-imx/cpuidle-imx6sl.c +++ b/arch/arm/mach-imx/cpuidle-imx6sl.c @@ -1,26 +1,104 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP. */ +#include #include #include +#include +#include +#include +#include +#include +#include +#include #include +#include +#include + +#include #include "common.h" #include "cpuidle.h" +#include "hardware.h" + +#define MAX_MMDC_IO_NUM 19 + +static void __iomem *wfi_iram_base; +extern unsigned long iram_tlb_base_addr; + +#ifdef CONFIG_CPU_FREQ +extern unsigned long mx6sl_lpm_wfi_start asm("mx6sl_lpm_wfi_start"); +extern unsigned long mx6sl_lpm_wfi_end asm("mx6sl_lpm_wfi_end"); +#endif + +struct imx6_cpuidle_pm_info { + u32 pm_info_size; /* Size of pm_info */ + u32 ttbr; + void __iomem *mmdc_base; + void __iomem *iomuxc_base; + void __iomem *ccm_base; + void __iomem *l2_base; + void __iomem *anatop_base; + u32 mmdc_io_num; /*Number of MMDC IOs which need saved/restored. */ + u32 mmdc_io_val[MAX_MMDC_IO_NUM][2]; /* To save offset and value */ +} __aligned(8); + +static const u32 imx6sl_mmdc_io_offset[] __initconst = { + 0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */ + 0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */ + 0x300, 0x31c, 0x338, 0x5ac, /*CAS, RAS, SDCLK_0, GPR_ADDS */ + 0x33c, 0x340, 0x5b0, 0x5c0, /*SODT0, SODT1, ,MODE_CTL, MODE */ + 0x330, 0x334, 0x320, /*SDCKE0, SDCK1, RESET */ +}; + +static struct regulator *vbus_ldo; +static struct regulator_dev *ldo2p5_dummy_regulator_rdev; +static struct regulator_init_data ldo2p5_dummy_initdata = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, +}; +static int ldo2p5_dummy_enable; + +static void (*imx6sl_wfi_in_iram_fn)(void __iomem *iram_vbase, + int audio_mode, bool vbus_ldo); + +#define MX6SL_POWERDWN_IDLE_PARAM \ + ((1 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \ + (1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \ + (PSCI_POWER_STATE_TYPE_POWER_DOWN << PSCI_0_2_POWER_STATE_TYPE_SHIFT)) static int imx6sl_enter_wait(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { + int mode = get_bus_freq_mode(); + imx6_set_lpm(WAIT_UNCLOCKED); - /* - * Software workaround for ERR005311, see function - * description for details. - */ - imx6sl_set_wait_clk(true); - cpu_do_idle(); - imx6sl_set_wait_clk(false); + + if ((mode == BUS_FREQ_AUDIO) || (mode == BUS_FREQ_ULTRA_LOW)) { + /* + * bit 2 used for low power mode; + * bit 1 used for the ldo2p5_dummmy enable + */ + if (psci_ops.cpu_suspend) { + psci_ops.cpu_suspend((MX6SL_POWERDWN_IDLE_PARAM | ((mode == BUS_FREQ_AUDIO ? 1 : 0) << 2) | + (ldo2p5_dummy_enable ? 1 : 0) << 1), __pa(cpu_resume)); + } else { + imx6sl_wfi_in_iram_fn(wfi_iram_base, (mode == BUS_FREQ_AUDIO) ? 1 : 0, + ldo2p5_dummy_enable); + } + } else { + /* + * Software workaround for ERR005311, see function + * description for details. + */ + imx6sl_set_wait_clk(true); + cpu_do_idle(); + imx6sl_set_wait_clk(false); + } imx6_set_lpm(WAIT_CLOCKED); return index; @@ -48,5 +126,109 @@ static struct cpuidle_driver imx6sl_cpuidle_driver = { int __init imx6sl_cpuidle_init(void) { + +#ifdef CONFIG_CPU_FREQ + struct imx6_cpuidle_pm_info *pm_info; + int i; + const u32 *mmdc_offset_array; + u32 wfi_code_size; + + vbus_ldo = regulator_get(NULL, "ldo2p5-dummy"); + if (IS_ERR(vbus_ldo)) + vbus_ldo = NULL; + + wfi_iram_base = (void *)(iram_tlb_base_addr + MX6_CPUIDLE_IRAM_ADDR_OFFSET); + + /* Make sure wif_iram_base is 8 byte aligned. */ + if ((uintptr_t)(wfi_iram_base) & (FNCPY_ALIGN - 1)) + wfi_iram_base += FNCPY_ALIGN - ((uintptr_t)wfi_iram_base % (FNCPY_ALIGN)); + + pm_info = wfi_iram_base; + pm_info->pm_info_size = sizeof(*pm_info); + pm_info->mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset); + mmdc_offset_array = imx6sl_mmdc_io_offset; + pm_info->mmdc_base = (void __iomem *)IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR); + pm_info->ccm_base = (void __iomem *)IMX_IO_P2V(MX6Q_CCM_BASE_ADDR); + pm_info->anatop_base = (void __iomem *)IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR); + pm_info->iomuxc_base = (void __iomem *)IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR); + pm_info->l2_base = (void __iomem *)IMX_IO_P2V(MX6Q_L2_BASE_ADDR); + + /* Only save mmdc io offset, settings will be saved in asm code */ + for (i = 0; i < pm_info->mmdc_io_num; i++) + pm_info->mmdc_io_val[i][0] = mmdc_offset_array[i]; + + /* calculate the wfi code size */ + wfi_code_size = (&mx6sl_lpm_wfi_end -&mx6sl_lpm_wfi_start) *4; + + imx6sl_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base + sizeof(*pm_info), + &imx6sl_low_power_idle, wfi_code_size); +#endif + return cpuidle_register(&imx6sl_cpuidle_driver, NULL); } + +static int imx_ldo2p5_dummy_enable(struct regulator_dev *rdev) +{ + ldo2p5_dummy_enable = 1; + return 0; +} + +static int imx_ldo2p5_dummy_disable(struct regulator_dev *rdev) +{ + ldo2p5_dummy_enable = 0; + return 0; +} + +static int imx_ldo2p5_dummy_is_enable(struct regulator_dev *rdev) +{ + return ldo2p5_dummy_enable; +} + +static struct regulator_ops ldo2p5_dummy_ops = { + .enable = imx_ldo2p5_dummy_enable, + .disable = imx_ldo2p5_dummy_disable, + .is_enabled = imx_ldo2p5_dummy_is_enable, +}; + +static struct regulator_desc ldo2p5_dummy_desc = { + .name = "ldo2p5-dummy", + .id = -1, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, + .ops = &ldo2p5_dummy_ops, +}; + +static int ldo2p5_dummy_probe(struct platform_device *pdev) +{ + struct regulator_config config = { }; + int ret; + + config.dev = &pdev->dev; + config.init_data = &ldo2p5_dummy_initdata; + config.of_node = pdev->dev.of_node; + + ldo2p5_dummy_regulator_rdev = regulator_register(&ldo2p5_dummy_desc, &config); + if (IS_ERR(ldo2p5_dummy_regulator_rdev)) { + ret = PTR_ERR(ldo2p5_dummy_regulator_rdev); + dev_err(&pdev->dev, "Failed to register dummy ldo2p5 regulator: %d\n", ret); + return ret; + } + return 0; +} + +static const struct of_device_id imx_ldo2p5_dummy_ids[] = { + { .compatible = "fsl,imx6-dummy-ldo2p5", }, + { }, +}; +MODULE_DEVICE_TABLE(ofm, imx_ldo2p5_dummy_ids); + +static struct platform_driver ldo2p5_dummy_driver = { + .probe = ldo2p5_dummy_probe, + .driver = { + .name = "ldo2p5-dummy", + .owner = THIS_MODULE, + .of_match_table = imx_ldo2p5_dummy_ids, + }, +}; + +module_platform_driver(ldo2p5_dummy_driver); diff --git a/arch/arm/mach-imx/cpuidle-imx6sll.c b/arch/arm/mach-imx/cpuidle-imx6sll.c new file mode 100644 index 00000000000000..bb8678ff56f0ee --- /dev/null +++ b/arch/arm/mach-imx/cpuidle-imx6sll.c @@ -0,0 +1,277 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "cpuidle.h" +#include "hardware.h" + +#define MAX_MMDC_IO_NUM 14 + +#define PMU_LOW_PWR_CTRL 0x270 +#define XTALOSC24M_OSC_CONFIG0 0x2a0 +#define XTALOSC24M_OSC_CONFIG1 0x2b0 +#define XTALOSC24M_OSC_CONFIG2 0x2c0 +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT 24 +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK 0xf +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT 16 +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK 0xf +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT 12 +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT 4 +#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT 1 +#define XTALOSC24M_OSC_CONFIG0_START_SHIFT 0 +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT 20 +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT 0 +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK 0xfff +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT 0 + +extern unsigned long iram_tlb_phys_addr; +static void __iomem *wfi_iram_base; + +#ifdef CONFIG_CPU_FREQ +static void __iomem *wfi_iram_base_phys; +extern unsigned long mx6sll_lpm_wfi_start asm("mx6sll_lpm_wfi_start"); +extern unsigned long mx6sll_lpm_wfi_end asm("mx6sll_lpm_wfi_end"); +#endif + +struct imx6_pm_base { + phys_addr_t pbase; + void __iomem *vbase; +}; + +struct imx6_cpuidle_pm_info { + phys_addr_t pbase; /* The physical address of pm_info. */ + phys_addr_t resume_addr; /* The physical resume address for asm code */ + u32 pm_info_size; /* Size of pm_info. */ + u32 ttbr; + struct imx6_pm_base mmdc_base; + struct imx6_pm_base iomuxc_base; + struct imx6_pm_base ccm_base; + struct imx6_pm_base gpc_base; + struct imx6_pm_base anatop_base; + struct imx6_pm_base src_base; + struct imx6_pm_base l2_base; + u32 saved_diagnostic; /* To save disagnostic register */ + u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */ + u32 mmdc_io_val[MAX_MMDC_IO_NUM][2]; /* To save offset and value */ +} __aligned(8); + +static const u32 imx6sll_mmdc_io_offset[] __initconst = { + 0x294, 0x298, 0x29c, 0x2a0, /* DQM0, DQM1, RAS, CAS */ + 0x544, 0x54c, 0x554, 0x558, /* GPR_B0DS ~ GPR_B3DS */ + 0x530, 0x540, 0x2ac, 0x52c, /* MODE_CTL, MODE, SDCLK0, GPR_ADDS */ + 0x2a4, 0x2a8, /* SDCKE0, SDCKE1 */ +}; + +static void (*imx6sll_wfi_in_iram_fn)(void __iomem *iram_vbase); + +#define MX6SLL_POWERDWN_IDLE_PARAM \ + ((1 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \ + (1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \ + (PSCI_POWER_STATE_TYPE_POWER_DOWN << PSCI_0_2_POWER_STATE_TYPE_SHIFT)) + +static int imx6sll_idle_finish(unsigned long val) +{ + if (psci_ops.cpu_suspend) + psci_ops.cpu_suspend(MX6SLL_POWERDWN_IDLE_PARAM, + __pa(cpu_resume)); + else + imx6sll_wfi_in_iram_fn(wfi_iram_base); + + return 0; +} + +static int imx6sll_enter_wait(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) +{ + int mode = get_bus_freq_mode(); + + imx6_set_lpm(WAIT_UNCLOCKED); + if ((index == 1) || ((mode != BUS_FREQ_LOW) && index == 2)) { + index = 1; + cpu_do_idle(); + } else { + imx_gpc_switch_pupscr_clk(true); + /* Need to notify there is a cpu pm operation. */ + cpu_pm_enter(); + cpu_cluster_pm_enter(); + + cpu_suspend(0, imx6sll_idle_finish); + + cpu_cluster_pm_exit(); + cpu_pm_exit(); + imx6_enable_rbc(false); + + imx_gpc_switch_pupscr_clk(false); + } + + imx6_set_lpm(WAIT_CLOCKED); + + return index; +} + +static struct cpuidle_driver imx6sll_cpuidle_driver = { + .name = "imx6sll_cpuidle", + .owner = THIS_MODULE, + .states = { + /* WFI */ + ARM_CPUIDLE_WFI_STATE, + /* WAIT */ + { + .exit_latency = 50, + .target_residency = 75, + .enter = imx6sll_enter_wait, + .name = "WAIT", + .desc = "Clock off", + }, + /* LOW POWER IDLE */ + { + /* + * RBC 130us + ARM gating 43us + RBC clear 65us + * + PLL2 relock 450us and some margin, here set + * it to 700us. + */ + .exit_latency = 700, + .target_residency = 1000, + .enter = imx6sll_enter_wait, + .name = "LOW-POWER-IDLE", + .desc = "ARM power off", + } + }, + .state_count = 3, + .safe_state_index = 0, +}; + +int __init imx6sll_cpuidle_init(void) +{ + void __iomem *anatop_base = (void __iomem *)IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR); + u32 val; +#ifdef CONFIG_CPU_FREQ + struct imx6_cpuidle_pm_info *cpuidle_pm_info; + int i; + const u32 *mmdc_offset_array; + u32 wfi_code_size; + + wfi_iram_base_phys = (void *)(iram_tlb_phys_addr + MX6_CPUIDLE_IRAM_ADDR_OFFSET); + + /* Make sure wfi_iram_base is 8 byte aligned. */ + if ((uintptr_t)(wfi_iram_base_phys) & (FNCPY_ALIGN - 1)) + wfi_iram_base_phys += FNCPY_ALIGN - ((uintptr_t)wfi_iram_base_phys % (FNCPY_ALIGN)); + + wfi_iram_base = (void *)IMX_IO_P2V((unsigned long) wfi_iram_base_phys); + + cpuidle_pm_info = wfi_iram_base; + cpuidle_pm_info->pbase = (phys_addr_t) wfi_iram_base_phys; + cpuidle_pm_info->pm_info_size = sizeof(*cpuidle_pm_info); + cpuidle_pm_info->resume_addr = virt_to_phys(v7_cpu_resume); + cpuidle_pm_info->mmdc_io_num = ARRAY_SIZE(imx6sll_mmdc_io_offset); + mmdc_offset_array = imx6sll_mmdc_io_offset; + + cpuidle_pm_info->mmdc_base.pbase = MX6Q_MMDC_P0_BASE_ADDR; + cpuidle_pm_info->mmdc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR); + + cpuidle_pm_info->ccm_base.pbase = MX6Q_CCM_BASE_ADDR; + cpuidle_pm_info->ccm_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_CCM_BASE_ADDR); + + cpuidle_pm_info->anatop_base.pbase = MX6Q_ANATOP_BASE_ADDR; + cpuidle_pm_info->anatop_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR); + + cpuidle_pm_info->gpc_base.pbase = MX6Q_GPC_BASE_ADDR; + cpuidle_pm_info->gpc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_GPC_BASE_ADDR); + + cpuidle_pm_info->iomuxc_base.pbase = MX6Q_IOMUXC_BASE_ADDR; + cpuidle_pm_info->iomuxc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR); + + cpuidle_pm_info->src_base.pbase = MX6Q_SRC_BASE_ADDR; + cpuidle_pm_info->src_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_SRC_BASE_ADDR); + + cpuidle_pm_info->l2_base.pbase = MX6Q_L2_BASE_ADDR; + cpuidle_pm_info->l2_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_L2_BASE_ADDR); + + /* Only save mmdc io offset, settings will be saved in asm code */ + for (i = 0; i < cpuidle_pm_info->mmdc_io_num; i++) + cpuidle_pm_info->mmdc_io_val[i][0] = mmdc_offset_array[i]; + + wfi_code_size = (&mx6sll_lpm_wfi_end -&mx6sll_lpm_wfi_start) *4; + + imx6sll_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base + sizeof(*cpuidle_pm_info), + &imx6sll_low_power_idle, wfi_code_size); +#endif + + imx6_set_int_mem_clk_lpm(true); + + /* + * enable RC-OSC here, as it needs at least 4ms for RC-OSC to + * be stable, low power idle flow can NOT endure this big + * latency, so we make RC-OSC self-tuning enabled here. + */ + val = readl_relaxed(anatop_base + PMU_LOW_PWR_CTRL); + val |= 0x1; + writel_relaxed(val, anatop_base + PMU_LOW_PWR_CTRL); + /* + * config RC-OSC freq + * tune_enable = 1;tune_start = 1;hyst_plus = 0;hyst_minus = 0; + * osc_prog = 0xa7; + */ + writel_relaxed( + 0x4 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT | + 0xa7 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT | + 0x1 << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT | + 0x1 << XTALOSC24M_OSC_CONFIG0_START_SHIFT, + anatop_base + XTALOSC24M_OSC_CONFIG0); + /* set count_trg = 0x2dc */ + writel_relaxed( + 0x40 << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT | + 0x2dc << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT, + anatop_base + XTALOSC24M_OSC_CONFIG1); + /* wait 4ms according to hardware design */ + msleep(4); + /* + * now add some hysteresis, hyst_plus=3, hyst_minus=3 + * (the minimum hysteresis that looks good is 2) + */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG0); + val &= ~((XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK << + XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) | + (XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK << + XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)); + val |= (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) | + (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT); + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG0); + /* set the count_1m_trg = 0x2d7 */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG2); + val &= ~(XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK << + XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT); + val |= 0x2d7 << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT; + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG2); + /* + * hardware design require to write XTALOSC24M_OSC_CONFIG0 or + * XTALOSC24M_OSC_CONFIG1 to + * make XTALOSC24M_OSC_CONFIG2 write work + */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG1); + + return cpuidle_register(&imx6sll_cpuidle_driver, NULL); +} diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c b/arch/arm/mach-imx/cpuidle-imx6sx.c index 74ea1720e3d836..692775a223a272 100644 --- a/arch/arm/mach-imx/cpuidle-imx6sx.c +++ b/arch/arm/mach-imx/cpuidle-imx6sx.c @@ -1,20 +1,97 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. */ +#include #include #include +#include +#include +#include #include +#include #include #include +#include +#include +#include #include +#include + +#include #include "common.h" #include "cpuidle.h" #include "hardware.h" -static int imx6sx_idle_finish(unsigned long val) +#define MX6_MAX_MMDC_IO_NUM 19 + +#define PMU_LOW_PWR_CTRL 0x270 +#define XTALOSC24M_OSC_CONFIG0 0x2a0 +#define XTALOSC24M_OSC_CONFIG1 0x2b0 +#define XTALOSC24M_OSC_CONFIG2 0x2c0 +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT 24 +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK 0xf +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT 16 +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK 0xf +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT 12 +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT 4 +#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT 1 +#define XTALOSC24M_OSC_CONFIG0_START_SHIFT 0 +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT 20 +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT 0 +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK 0xfff +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT 0 + +extern unsigned long iram_tlb_phys_addr; + +static void __iomem *wfi_iram_base; +#ifdef CONFIG_CPU_FREQ +static void __iomem *wfi_iram_base_phys; +extern unsigned long mx6sx_lpm_wfi_start asm("mx6sx_lpm_wfi_start"); +extern unsigned long mx6sx_lpm_wfi_end asm("mx6sx_lpm_wfi_end"); +#endif + +struct imx6_pm_base { + phys_addr_t pbase; + void __iomem *vbase; +}; + +static const u32 imx6sx_mmdc_io_offset[] __initconst = { + 0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */ + 0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */ + 0x60c, 0x610, 0x61c, 0x620, /* B0DS ~ B3DS */ + 0x5f8, 0x608, 0x310, 0x314, /* CTL, MODE, SODT0, SODT1 */ + 0x300, 0x2fc, 0x32c, /* CAS, RAS, SDCLK_0 */ +}; + +struct imx6_cpuidle_pm_info { + phys_addr_t pbase; /* The physical address of pm_info. */ + phys_addr_t resume_addr; /* The physical resume address for asm code */ + u32 pm_info_size; /* Size of pm_info. */ + u32 ttbr; + struct imx6_pm_base mmdc_base; + struct imx6_pm_base iomuxc_base; + struct imx6_pm_base ccm_base; + struct imx6_pm_base gpc_base; + struct imx6_pm_base l2_base; + struct imx6_pm_base anatop_base; + struct imx6_pm_base src_base; + struct imx6_pm_base sema4_base; + u32 saved_diagnostic; /* To save disagnostic register */ + u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */ + u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */ +} __aligned(8); + +static void (*imx6sx_wfi_in_iram_fn)(void __iomem *iram_vbase); + +#define MX6SX_POWERDWN_IDLE_PARAM \ + ((1 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \ + (1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \ + (PSCI_POWER_STATE_TYPE_POWER_DOWN << PSCI_0_2_POWER_STATE_TYPE_SHIFT)) + +static int imx6_idle_finish(unsigned long val) { /* * for Cortex-A7 which has an internal L2 @@ -25,7 +102,11 @@ static int imx6sx_idle_finish(unsigned long val) * just call flush_cache_all() is fine. */ flush_cache_all(); - cpu_do_idle(); + if (psci_ops.cpu_suspend) + psci_ops.cpu_suspend(MX6SX_POWERDWN_IDLE_PARAM, + __pa(cpu_resume)); + else + imx6sx_wfi_in_iram_fn(wfi_iram_base); return 0; } @@ -33,29 +114,22 @@ static int imx6sx_idle_finish(unsigned long val) static int imx6sx_enter_wait(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - imx6_set_lpm(WAIT_UNCLOCKED); + int mode = get_bus_freq_mode(); - switch (index) { - case 1: + imx6_set_lpm(WAIT_UNCLOCKED); + if ((index == 1) || ((mode != BUS_FREQ_LOW) && index == 2)) { + index = 1; cpu_do_idle(); - break; - case 2: - imx6_enable_rbc(true); - imx_gpc_set_arm_power_in_lpm(true); - imx_set_cpu_jump(0, v7_cpu_resume); - /* Need to notify there is a cpu pm operation. */ - cpu_pm_enter(); - cpu_cluster_pm_enter(); - - cpu_suspend(0, imx6sx_idle_finish); - - cpu_cluster_pm_exit(); - cpu_pm_exit(); - imx_gpc_set_arm_power_in_lpm(false); - imx6_enable_rbc(false); - break; - default: - break; + } else { + /* Need to notify there is a cpu pm operation. */ + cpu_pm_enter(); + cpu_cluster_pm_enter(); + + cpu_suspend(0, imx6_idle_finish); + + cpu_cluster_pm_exit(); + cpu_pm_exit(); + imx6_enable_rbc(false); } imx6_set_lpm(WAIT_CLOCKED); @@ -69,25 +143,23 @@ static struct cpuidle_driver imx6sx_cpuidle_driver = { .states = { /* WFI */ ARM_CPUIDLE_WFI_STATE, - /* WAIT */ + /* WAIT MODE */ { .exit_latency = 50, .target_residency = 75, - .flags = CPUIDLE_FLAG_TIMER_STOP, .enter = imx6sx_enter_wait, .name = "WAIT", .desc = "Clock off", }, - /* WAIT + ARM power off */ + /* LOW POWER IDLE */ { /* - * ARM gating 31us * 5 + RBC clear 65us - * and some margin for SW execution, here set it - * to 300us. + * RBC 130us + ARM gating 93us + RBC clear 65us + * + PLL2 relock 450us and some margin, here set + * it to 800us. */ - .exit_latency = 300, - .target_residency = 500, - .flags = CPUIDLE_FLAG_TIMER_STOP, + .exit_latency = 800, + .target_residency = 1000, .enter = imx6sx_enter_wait, .name = "LOW-POWER-IDLE", .desc = "ARM power off", @@ -99,17 +171,119 @@ static struct cpuidle_driver imx6sx_cpuidle_driver = { int __init imx6sx_cpuidle_init(void) { + void __iomem *anatop_base = (void __iomem *)IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR); + u32 val; +#ifdef CONFIG_CPU_FREQ + struct imx6_cpuidle_pm_info *cpuidle_pm_info; + int i; + const u32 *mmdc_offset_array; + u32 wfi_code_size; + + wfi_iram_base_phys = (void *)(iram_tlb_phys_addr + MX6_CPUIDLE_IRAM_ADDR_OFFSET); + + /* Make sure wfi_iram_base is 8 byte aligned. */ + if ((uintptr_t)(wfi_iram_base_phys) & (FNCPY_ALIGN - 1)) + wfi_iram_base_phys += FNCPY_ALIGN - ((uintptr_t)wfi_iram_base_phys % (FNCPY_ALIGN)); + + wfi_iram_base = (void *)IMX_IO_P2V((unsigned long) wfi_iram_base_phys); + + cpuidle_pm_info = wfi_iram_base; + cpuidle_pm_info->pbase = (phys_addr_t) wfi_iram_base_phys; + cpuidle_pm_info->pm_info_size = sizeof(*cpuidle_pm_info); + cpuidle_pm_info->resume_addr = virt_to_phys(v7_cpu_resume); + cpuidle_pm_info->mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset); + mmdc_offset_array = imx6sx_mmdc_io_offset; + + cpuidle_pm_info->mmdc_base.pbase = MX6Q_MMDC_P0_BASE_ADDR; + cpuidle_pm_info->mmdc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR); + + cpuidle_pm_info->ccm_base.pbase = MX6Q_CCM_BASE_ADDR; + cpuidle_pm_info->ccm_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_CCM_BASE_ADDR); + + cpuidle_pm_info->anatop_base.pbase = MX6Q_ANATOP_BASE_ADDR; + cpuidle_pm_info->anatop_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR); + + cpuidle_pm_info->gpc_base.pbase = MX6Q_GPC_BASE_ADDR; + cpuidle_pm_info->gpc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_GPC_BASE_ADDR); + + cpuidle_pm_info->iomuxc_base.pbase = MX6Q_IOMUXC_BASE_ADDR; + cpuidle_pm_info->iomuxc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR); + + cpuidle_pm_info->l2_base.pbase = MX6Q_L2_BASE_ADDR; + cpuidle_pm_info->l2_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_L2_BASE_ADDR); + + cpuidle_pm_info->src_base.pbase = MX6Q_SRC_BASE_ADDR; + cpuidle_pm_info->src_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_SRC_BASE_ADDR); + + cpuidle_pm_info->sema4_base.pbase = MX6Q_SEMA4_BASE_ADDR; + cpuidle_pm_info->sema4_base.vbase = + (void __iomem *)IMX_IO_P2V(MX6Q_SEMA4_BASE_ADDR); + + /* only save mmdc io offset, settings will be saved in asm code */ + for (i = 0; i < cpuidle_pm_info->mmdc_io_num; i++) + cpuidle_pm_info->mmdc_io_val[i][0] = mmdc_offset_array[i]; + + /* code size should include cpuidle_pm_info size */ + wfi_code_size = (&mx6sx_lpm_wfi_end -&mx6sx_lpm_wfi_start) *4 + sizeof(*cpuidle_pm_info); + imx6sx_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base + sizeof(*cpuidle_pm_info), + &imx6sx_low_power_idle, wfi_code_size); +#endif + imx6_set_int_mem_clk_lpm(true); - imx6_enable_rbc(false); - imx_gpc_set_l2_mem_power_in_lpm(false); - /* - * set ARM power up/down timing to the fastest, - * sw2iso and sw can be set to one 32K cycle = 31us - * except for power up sw2iso which need to be - * larger than LDO ramp up time. - */ - imx_gpc_set_arm_power_up_timing(cpu_is_imx6sx() ? 0xf : 0x2, 1); - imx_gpc_set_arm_power_down_timing(1, 1); + + if (imx_get_soc_revision() >= IMX_CHIP_REVISION_1_2) { + /* + * enable RC-OSC here, as it needs at least 4ms for RC-OSC to + * be stable, low power idle flow can NOT endure this big + * latency, so we make RC-OSC self-tuning enabled here. + */ + val = readl_relaxed(anatop_base + PMU_LOW_PWR_CTRL); + val |= 0x1; + writel_relaxed(val, anatop_base + PMU_LOW_PWR_CTRL); + /* + * config RC-OSC freq + * tune_enable = 1;tune_start = 1;hyst_plus = 0;hyst_minus = 0; + * osc_prog = 0xa7; + */ + writel_relaxed( + 0x4 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT | + 0xa7 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT | + 0x1 << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT | + 0x1 << XTALOSC24M_OSC_CONFIG0_START_SHIFT, + anatop_base + XTALOSC24M_OSC_CONFIG0); + /* set count_trg = 0x2dc */ + writel_relaxed( + 0x40 << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT | + 0x2dc << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT, + anatop_base + XTALOSC24M_OSC_CONFIG1); + /* wait 4ms according to hardware design */ + msleep(4); + /* + * now add some hysteresis, hyst_plus=3, hyst_minus=3 + * (the minimum hysteresis that looks good is 2) + */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG0); + val &= ~((XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK << + XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) | + (XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK << + XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)); + val |= (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) | + (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT); + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG0); + /* set the count_1m_trg = 0x2d7 */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG2); + val &= ~(XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK << + XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT); + val |= 0x2d7 << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT; + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG2); + /* + * hardware design require to write XTALOSC24M_OSC_CONFIG0 or + * XTALOSC24M_OSC_CONFIG1 to + * make XTALOSC24M_OSC_CONFIG2 write work + */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG1); + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG1); + } return cpuidle_register(&imx6sx_cpuidle_driver, NULL); } diff --git a/arch/arm/mach-imx/cpuidle-imx6ul.c b/arch/arm/mach-imx/cpuidle-imx6ul.c new file mode 100644 index 00000000000000..4f22b8f0d02bee --- /dev/null +++ b/arch/arm/mach-imx/cpuidle-imx6ul.c @@ -0,0 +1,327 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "cpuidle.h" +#include "hardware.h" + +#define MAX_MMDC_IO_NUM 14 + +#define PMU_LOW_PWR_CTRL 0x270 +#define XTALOSC24M_OSC_CONFIG0 0x2a0 +#define XTALOSC24M_OSC_CONFIG1 0x2b0 +#define XTALOSC24M_OSC_CONFIG2 0x2c0 +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT 24 +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK 0xf +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT 16 +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK 0xf +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT 12 +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT 4 +#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT 1 +#define XTALOSC24M_OSC_CONFIG0_START_SHIFT 0 +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT 20 +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT 0 +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK 0xfff +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT 0 + +extern unsigned long iram_tlb_phys_addr; +static void __iomem *wfi_iram_base; + +#ifdef CONFIG_CPU_FREQ +static void __iomem *wfi_iram_base_phys; +extern unsigned long mx6ul_lpm_wfi_start asm("mx6ul_lpm_wfi_start"); +extern unsigned long mx6ul_lpm_wfi_end asm("mx6ul_lpm_wfi_end"); +extern unsigned long mx6ull_lpm_wfi_start asm("mx6ull_lpm_wfi_start"); +extern unsigned long mx6ull_lpm_wfi_end asm("mx6ull_lpm_wfi_end"); +#endif + +struct imx6_pm_base { + phys_addr_t pbase; + void __iomem *vbase; +}; + +struct imx6_cpuidle_pm_info { + phys_addr_t pbase; /* The physical address of pm_info. */ + phys_addr_t resume_addr; /* The physical resume address for asm code */ + u32 pm_info_size; /* Size of pm_info. */ + u32 ttbr; + struct imx6_pm_base mmdc_base; + struct imx6_pm_base iomuxc_base; + struct imx6_pm_base ccm_base; + struct imx6_pm_base gpc_base; + struct imx6_pm_base anatop_base; + struct imx6_pm_base src_base; + u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */ + u32 mmdc_io_val[MAX_MMDC_IO_NUM][2]; /* To save offset and value */ +} __aligned(8); + +static const u32 imx6ul_mmdc_io_offset[] __initconst = { + 0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */ + 0x27c, 0x498, 0x4a4, 0x490, /* SDCLK0, GPR_B0DS-B1DS, GPR_ADDS */ + 0x280, 0x284, 0x260, 0x264, /* SDQS0~1, SODT0, SODT1 */ + 0x494, 0x4b0, /* MODE_CTL, MODE, */ +}; + +static void (*imx6ul_wfi_in_iram_fn)(void __iomem *iram_vbase); + +#define MX6UL_POWERDWN_IDLE_PARAM \ + ((1 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \ + (1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \ + (PSCI_POWER_STATE_TYPE_POWER_DOWN << PSCI_0_2_POWER_STATE_TYPE_SHIFT)) + +static int imx6ul_idle_finish(unsigned long val) +{ + if (psci_ops.cpu_suspend) + psci_ops.cpu_suspend(MX6UL_POWERDWN_IDLE_PARAM, + __pa(cpu_resume)); + else + imx6ul_wfi_in_iram_fn(wfi_iram_base); + + return 0; +} + +static int imx6ul_enter_wait(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) +{ + int mode = get_bus_freq_mode(); + + imx6_set_lpm(WAIT_UNCLOCKED); + if ((index == 1) || ((mode != BUS_FREQ_LOW) && index == 2)) { + cpu_do_idle(); + index = 1; + } else { + /* + * i.MX6UL TO1.0 ARM power up uses IPG/2048 as clock source, + * from TO1.1, PGC_CPU_PUPSCR bit [5] is re-defined to switch + * clock to IPG/32, enable this bit to speed up the ARM power + * up process in low power idle case. + */ + if (cpu_is_imx6ul() && imx_get_soc_revision() > + IMX_CHIP_REVISION_1_0) + imx_gpc_switch_pupscr_clk(true); + /* Need to notify there is a cpu pm operation. */ + cpu_pm_enter(); + cpu_cluster_pm_enter(); + + cpu_suspend(0, imx6ul_idle_finish); + + cpu_cluster_pm_exit(); + cpu_pm_exit(); + imx6_enable_rbc(false); + + if (cpu_is_imx6ul() && imx_get_soc_revision() > + IMX_CHIP_REVISION_1_0) + imx_gpc_switch_pupscr_clk(false); + } + + imx6_set_lpm(WAIT_CLOCKED); + + return index; +} + +static struct cpuidle_driver imx6ul_cpuidle_driver_v2 = { + .name = "imx6ul_cpuidle", + .owner = THIS_MODULE, + .states = { + /* WFI */ + ARM_CPUIDLE_WFI_STATE, + /* WAIT */ + { + .exit_latency = 50, + .target_residency = 75, + .enter = imx6ul_enter_wait, + .name = "WAIT", + .desc = "Clock off", + }, + /* LOW POWER IDLE */ + { + /* + * RBC 130us + ARM gating 43us + RBC clear 65us + * + PLL2 relock 450us and some margin, here set + * it to 700us. + */ + .exit_latency = 700, + .target_residency = 1000, + .enter = imx6ul_enter_wait, + .name = "LOW-POWER-IDLE", + .desc = "ARM power off", + } + }, + .state_count = 3, + .safe_state_index = 0, +}; + +static struct cpuidle_driver imx6ul_cpuidle_driver = { + .name = "imx6ul_cpuidle", + .owner = THIS_MODULE, + .states = { + /* WFI */ + ARM_CPUIDLE_WFI_STATE, + /* WAIT */ + { + .exit_latency = 50, + .target_residency = 75, + .enter = imx6ul_enter_wait, + .name = "WAIT", + .desc = "Clock off", + }, + /* LOW POWER IDLE */ + { + /* + * RBC 130us + ARM gating 1370us + RBC clear 65us + * + PLL2 relock 450us and some margin, here set + * it to 2100us. + */ + .exit_latency = 2100, + .target_residency = 2500, + .enter = imx6ul_enter_wait, + .name = "LOW-POWER-IDLE", + .desc = "ARM power off", + } + }, + .state_count = 3, + .safe_state_index = 0, +}; + +int __init imx6ul_cpuidle_init(void) +{ + void __iomem *anatop_base = (void __iomem *)IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR); + u32 val; +#ifdef CONFIG_CPU_FREQ + struct imx6_cpuidle_pm_info *cpuidle_pm_info; + int i; + const u32 *mmdc_offset_array; + u32 wfi_code_size; + + wfi_iram_base_phys = (void *)(iram_tlb_phys_addr + MX6_CPUIDLE_IRAM_ADDR_OFFSET); + + /* Make sure wfi_iram_base is 8 byte aligned. */ + if ((uintptr_t)(wfi_iram_base_phys) & (FNCPY_ALIGN - 1)) + wfi_iram_base_phys += FNCPY_ALIGN - ((uintptr_t)wfi_iram_base_phys % (FNCPY_ALIGN)); + + wfi_iram_base = (void *)IMX_IO_P2V((unsigned long) wfi_iram_base_phys); + + cpuidle_pm_info = wfi_iram_base; + cpuidle_pm_info->pbase = (phys_addr_t) wfi_iram_base_phys; + cpuidle_pm_info->pm_info_size = sizeof(*cpuidle_pm_info); + cpuidle_pm_info->resume_addr = virt_to_phys(v7_cpu_resume); + cpuidle_pm_info->mmdc_io_num = ARRAY_SIZE(imx6ul_mmdc_io_offset); + mmdc_offset_array = imx6ul_mmdc_io_offset; + + cpuidle_pm_info->mmdc_base.pbase = MX6Q_MMDC_P0_BASE_ADDR; + cpuidle_pm_info->mmdc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR); + + cpuidle_pm_info->ccm_base.pbase = MX6Q_CCM_BASE_ADDR; + cpuidle_pm_info->ccm_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_CCM_BASE_ADDR); + + cpuidle_pm_info->anatop_base.pbase = MX6Q_ANATOP_BASE_ADDR; + cpuidle_pm_info->anatop_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR); + + cpuidle_pm_info->gpc_base.pbase = MX6Q_GPC_BASE_ADDR; + cpuidle_pm_info->gpc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_GPC_BASE_ADDR); + + cpuidle_pm_info->iomuxc_base.pbase = MX6Q_IOMUXC_BASE_ADDR; + cpuidle_pm_info->iomuxc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR); + + cpuidle_pm_info->src_base.pbase = MX6Q_SRC_BASE_ADDR; + cpuidle_pm_info->src_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_SRC_BASE_ADDR); + + /* Only save mmdc io offset, settings will be saved in asm code */ + for (i = 0; i < cpuidle_pm_info->mmdc_io_num; i++) + cpuidle_pm_info->mmdc_io_val[i][0] = mmdc_offset_array[i]; + + /* calculate the wfi code size */ + if (cpu_is_imx6ul()) { + wfi_code_size = (&mx6ul_lpm_wfi_end -&mx6ul_lpm_wfi_start) *4; + + imx6ul_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base + sizeof(*cpuidle_pm_info), + &imx6ul_low_power_idle, wfi_code_size); + } else { + wfi_code_size = (&mx6ull_lpm_wfi_end -&mx6ull_lpm_wfi_start) *4; + + imx6ul_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base + sizeof(*cpuidle_pm_info), + &imx6ull_low_power_idle, wfi_code_size); + } +#endif + + imx6_set_int_mem_clk_lpm(true); + + /* + * enable RC-OSC here, as it needs at least 4ms for RC-OSC to + * be stable, low power idle flow can NOT endure this big + * latency, so we make RC-OSC self-tuning enabled here. + */ + val = readl_relaxed(anatop_base + PMU_LOW_PWR_CTRL); + val |= 0x1; + writel_relaxed(val, anatop_base + PMU_LOW_PWR_CTRL); + /* + * config RC-OSC freq + * tune_enable = 1;tune_start = 1;hyst_plus = 0;hyst_minus = 0; + * osc_prog = 0xa7; + */ + writel_relaxed( + 0x4 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT | + 0xa7 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT | + 0x1 << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT | + 0x1 << XTALOSC24M_OSC_CONFIG0_START_SHIFT, + anatop_base + XTALOSC24M_OSC_CONFIG0); + /* set count_trg = 0x2dc */ + writel_relaxed( + 0x40 << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT | + 0x2dc << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT, + anatop_base + XTALOSC24M_OSC_CONFIG1); + /* wait 4ms according to hardware design */ + msleep(4); + /* + * now add some hysteresis, hyst_plus=3, hyst_minus=3 + * (the minimum hysteresis that looks good is 2) + */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG0); + val &= ~((XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK << + XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) | + (XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK << + XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)); + val |= (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) | + (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT); + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG0); + /* set the count_1m_trg = 0x2d7 */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG2); + val &= ~(XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK << + XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT); + val |= 0x2d7 << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT; + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG2); + /* + * hardware design require to write XTALOSC24M_OSC_CONFIG0 or + * XTALOSC24M_OSC_CONFIG1 to + * make XTALOSC24M_OSC_CONFIG2 write work + */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG1); + + /* ARM power up time is reduced since TO1.1 */ + if (imx_get_soc_revision() > IMX_CHIP_REVISION_1_0) + return cpuidle_register(&imx6ul_cpuidle_driver_v2, NULL); + else + return cpuidle_register(&imx6ul_cpuidle_driver, NULL); +} diff --git a/arch/arm/mach-imx/cpuidle-imx7d.c b/arch/arm/mach-imx/cpuidle-imx7d.c new file mode 100644 index 00000000000000..8e1e61c5503b2f --- /dev/null +++ b/arch/arm/mach-imx/cpuidle-imx7d.c @@ -0,0 +1,390 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "cpuidle.h" +#include "hardware.h" + +#define XTALOSC24M_OSC_CONFIG0 0x10 +#define XTALOSC24M_OSC_CONFIG1 0x20 +#define XTALOSC24M_OSC_CONFIG2 0x30 +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT 24 +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK 0xf +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT 16 +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK 0xf +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT 12 +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT 4 +#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT 1 +#define XTALOSC24M_OSC_CONFIG0_START_SHIFT 0 +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT 20 +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT 0 +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK 0xfff +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT 0 + +#define XTALOSC_CTRL_24M 0x0 +#define XTALOSC_CTRL_24M_RC_OSC_EN_SHIFT 13 +#define REG_SET 0x4 + +static void __iomem *wfi_iram_base; +static void __iomem *wfi_iram_base_phys; +extern unsigned long iram_tlb_phys_addr; + +struct imx7_pm_base { + phys_addr_t pbase; + void __iomem *vbase; +}; + +struct imx7_cpuidle_pm_info { + phys_addr_t vbase; /* The virtual address of pm_info. */ + phys_addr_t pbase; /* The physical address of pm_info. */ + phys_addr_t resume_addr; /* The physical resume address for asm code */ + u32 pm_info_size; + u32 ttbr; + u32 num_online_cpus; + u32 num_lpi_cpus; + atomic_t val; + atomic_t flag0; + atomic_t flag1; + struct imx7_pm_base ddrc_base; + struct imx7_pm_base ccm_base; + struct imx7_pm_base anatop_base; + struct imx7_pm_base src_base; + struct imx7_pm_base iomuxc_gpr_base; + struct imx7_pm_base gpc_base; + struct imx7_pm_base gic_dist_base; +} __aligned(8); + +static atomic_t master_lpi = ATOMIC_INIT(0); +static atomic_t master_wait = ATOMIC_INIT(0); + +static void (*imx7d_wfi_in_iram_fn)(void __iomem *iram_vbase); +static struct imx7_cpuidle_pm_info *cpuidle_pm_info; + +#define MX7D_POWERDWN_IDLE_PARAM \ + ((1 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \ + (1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \ + (PSCI_POWER_STATE_TYPE_POWER_DOWN << PSCI_0_2_POWER_STATE_TYPE_SHIFT)) + +#define MX7D_STANDBY_IDLE_PARAM \ + ((1 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \ + (1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \ + (PSCI_POWER_STATE_TYPE_STANDBY << PSCI_0_2_POWER_STATE_TYPE_SHIFT)) + +/* Mapped for the kernel, unlike cpuidle_pm_info->gic_dist_base.vbase */ +static void __iomem *imx7d_cpuidle_gic_base; + +static void imx_pen_lock(int cpu) +{ + if (cpu == 0) { + atomic_set(&cpuidle_pm_info->flag0, 1); + dsb(); + atomic_set(&cpuidle_pm_info->val, cpu); + do { + dsb(); + } while (atomic_read(&cpuidle_pm_info->flag1) == 1 + && atomic_read(&cpuidle_pm_info->val) == cpu) + ; + } else { + atomic_set(&cpuidle_pm_info->flag1, 1); + dsb(); + atomic_set(&cpuidle_pm_info->val, cpu); + do { + dsb(); + } while (atomic_read(&cpuidle_pm_info->flag0) == 1 + && atomic_read(&cpuidle_pm_info->val) == cpu) + ; + } +} + +static void imx_pen_unlock(int cpu) +{ + dsb(); + if (cpu == 0) + atomic_set(&cpuidle_pm_info->flag0, 0); + else + atomic_set(&cpuidle_pm_info->flag1, 0); +} + +static int imx7d_idle_finish(unsigned long val) +{ + if (psci_ops.cpu_suspend) + psci_ops.cpu_suspend(MX7D_POWERDWN_IDLE_PARAM, __pa(cpu_resume)); + else + imx7d_wfi_in_iram_fn(wfi_iram_base); + + return 0; +} + +static bool imx7d_gic_sgis_pending(void) +{ + void __iomem *sgip_base = imx7d_cpuidle_gic_base + 0x1f20; + + return (readl_relaxed(sgip_base + 0x0) | + readl_relaxed(sgip_base + 0x4) | + readl_relaxed(sgip_base + 0x8) | + readl_relaxed(sgip_base + 0xc)); +} + +static DEFINE_SPINLOCK(psci_lock); +static int imx7d_enter_low_power_idle(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) +{ + int mode = get_bus_freq_mode(); + + + if ((index == 1) || ((mode != BUS_FREQ_LOW) && index == 2)) { + index = 1; + if (atomic_inc_return(&master_wait) == num_online_cpus()) + imx_gpcv2_set_lpm_mode(WAIT_UNCLOCKED); + + cpu_do_idle(); + + atomic_dec(&master_wait); + imx_gpcv2_set_lpm_mode(WAIT_CLOCKED); + } else { + if (psci_ops.cpu_suspend) { + cpu_pm_enter(); + spin_lock(&psci_lock); + if (atomic_inc_return(&master_lpi) == num_online_cpus()) { + if (imx7d_gic_sgis_pending()) { + atomic_dec(&master_lpi); + index = -1; + goto psci_skip_lpi_flow; + } + + imx_gpcv2_set_lpm_mode(WAIT_UNCLOCKED); + imx_gpcv2_set_cpu_power_gate_in_idle(true); + + cpu_cluster_pm_enter(); + } + spin_unlock(&psci_lock); + + cpu_suspend(0, imx7d_idle_finish); + + spin_lock(&psci_lock); + if (atomic_read(&master_lpi) == num_online_cpus()) { + cpu_cluster_pm_exit(); + imx_gpcv2_set_cpu_power_gate_in_idle(false); + imx_gpcv2_set_lpm_mode(WAIT_CLOCKED); + } + + atomic_dec(&master_lpi); +psci_skip_lpi_flow: + spin_unlock(&psci_lock); + cpu_pm_exit(); + } else { + imx_pen_lock(dev->cpu); + cpuidle_pm_info->num_online_cpus = num_online_cpus(); + ++cpuidle_pm_info->num_lpi_cpus; + cpu_pm_enter(); + if (cpuidle_pm_info->num_lpi_cpus == + cpuidle_pm_info->num_online_cpus) { + /* + * GPC will not wake on SGIs so check for them + * manually here. At this point we know the other cpu + * is in wfi or waiting for the lock and can't send + * any additional IPIs. + */ + if (imx7d_gic_sgis_pending()) { + index = -1; + goto skip_lpi_flow; + } + imx_gpcv2_set_lpm_mode(WAIT_UNCLOCKED); + imx_gpcv2_set_cpu_power_gate_in_idle(true); + cpu_cluster_pm_enter(); + } else { + imx_set_cpu_jump(dev->cpu, ca7_cpu_resume); + } + + cpu_suspend(0, imx7d_idle_finish); + + if (cpuidle_pm_info->num_lpi_cpus == + cpuidle_pm_info->num_online_cpus) { + cpu_cluster_pm_exit(); + imx_gpcv2_set_cpu_power_gate_in_idle(false); + imx_gpcv2_set_lpm_mode(WAIT_CLOCKED); + } + +skip_lpi_flow: + cpu_pm_exit(); + --cpuidle_pm_info->num_lpi_cpus; + imx_pen_unlock(dev->cpu); + } + } + + return index; +} + +static struct cpuidle_driver imx7d_cpuidle_driver = { + .name = "imx7d_cpuidle", + .owner = THIS_MODULE, + .states = { + /* WFI */ + ARM_CPUIDLE_WFI_STATE, + /* WAIT MODE */ + { + .exit_latency = 50, + .target_residency = 75, + .flags = CPUIDLE_FLAG_TIMER_STOP, + .enter = imx7d_enter_low_power_idle, + .name = "WAIT", + .desc = "Clock off", + }, + /* LOW POWER IDLE */ + { + .exit_latency = 10000, + .target_residency = 20000, + .flags = CPUIDLE_FLAG_TIMER_STOP, + .enter = imx7d_enter_low_power_idle, + .name = "LOW-POWER-IDLE", + .desc = "ARM power off", + }, + }, + .state_count = 3, + .safe_state_index = 0, +}; + +int imx7d_enable_rcosc(void) +{ + void __iomem *anatop_base = + (void __iomem *)IMX_IO_P2V(MX7D_ANATOP_BASE_ADDR); + u32 val; + + imx_gpcv2_set_lpm_mode(WAIT_CLOCKED); + /* set RC-OSC freq and turn it on */ + writel_relaxed(0x1 << XTALOSC_CTRL_24M_RC_OSC_EN_SHIFT, + anatop_base + XTALOSC_CTRL_24M + REG_SET); + /* + * config RC-OSC freq + * tune_enable = 1;tune_start = 1;hyst_plus = 0;hyst_minus = 0; + * osc_prog = 0xa7; + */ + writel_relaxed( + 0x4 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT | + 0xa7 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT | + 0x1 << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT | + 0x1 << XTALOSC24M_OSC_CONFIG0_START_SHIFT, + anatop_base + XTALOSC24M_OSC_CONFIG0); + /* set count_trg = 0x2dc */ + writel_relaxed( + 0x40 << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT | + 0x2dc << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT, + anatop_base + XTALOSC24M_OSC_CONFIG1); + /* wait at least 4ms according to hardware design */ + mdelay(6); + /* + * now add some hysteresis, hyst_plus=3, hyst_minus=3 + * (the minimum hysteresis that looks good is 2) + */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG0); + val &= ~((XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK << + XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) | + (XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK << + XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)); + val |= (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) | + (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT); + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG0); + /* set the count_1m_trg = 0x2d7 */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG2); + val &= ~(XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK << + XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT); + val |= 0x2d7 << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT; + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG2); + /* + * hardware design require to write XTALOSC24M_OSC_CONFIG0 or + * XTALOSC24M_OSC_CONFIG1 to + * make XTALOSC24M_OSC_CONFIG2 write work + */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG1); + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG1); + + return 0; +} + +int __init imx7d_cpuidle_init(void) +{ + wfi_iram_base_phys = (void *)(iram_tlb_phys_addr + + MX7_CPUIDLE_OCRAM_ADDR_OFFSET); + + /* Make sure wfi_iram_base is 8 byte aligned. */ + if ((uintptr_t)(wfi_iram_base_phys) & (FNCPY_ALIGN - 1)) + wfi_iram_base_phys += FNCPY_ALIGN - + ((uintptr_t)wfi_iram_base_phys % (FNCPY_ALIGN)); + + wfi_iram_base = (void *)IMX_IO_P2V((unsigned long) wfi_iram_base_phys); + + cpuidle_pm_info = wfi_iram_base; + cpuidle_pm_info->vbase = (phys_addr_t) wfi_iram_base; + cpuidle_pm_info->pbase = (phys_addr_t) wfi_iram_base_phys; + cpuidle_pm_info->pm_info_size = sizeof(*cpuidle_pm_info); + cpuidle_pm_info->resume_addr = virt_to_phys(ca7_cpu_resume); + cpuidle_pm_info->num_online_cpus = num_online_cpus(); + + cpuidle_pm_info->ddrc_base.pbase = MX7D_DDRC_BASE_ADDR; + cpuidle_pm_info->ddrc_base.vbase = + (void __iomem *)IMX_IO_P2V(MX7D_DDRC_BASE_ADDR); + + cpuidle_pm_info->ccm_base.pbase = MX7D_CCM_BASE_ADDR; + cpuidle_pm_info->ccm_base.vbase = + (void __iomem *)IMX_IO_P2V(MX7D_CCM_BASE_ADDR); + + cpuidle_pm_info->anatop_base.pbase = MX7D_ANATOP_BASE_ADDR; + cpuidle_pm_info->anatop_base.vbase = + (void __iomem *)IMX_IO_P2V(MX7D_ANATOP_BASE_ADDR); + + cpuidle_pm_info->src_base.pbase = MX7D_SRC_BASE_ADDR; + cpuidle_pm_info->src_base.vbase = + (void __iomem *)IMX_IO_P2V(MX7D_SRC_BASE_ADDR); + + cpuidle_pm_info->iomuxc_gpr_base.pbase = MX7D_IOMUXC_GPR_BASE_ADDR; + cpuidle_pm_info->iomuxc_gpr_base.vbase = + (void __iomem *)IMX_IO_P2V(MX7D_IOMUXC_GPR_BASE_ADDR); + + cpuidle_pm_info->gpc_base.pbase = MX7D_GPC_BASE_ADDR; + cpuidle_pm_info->gpc_base.vbase = + (void __iomem *)IMX_IO_P2V(MX7D_GPC_BASE_ADDR); + + cpuidle_pm_info->gic_dist_base.pbase = MX7D_GIC_BASE_ADDR; + cpuidle_pm_info->gic_dist_base.vbase = + (void __iomem *)IMX_IO_P2V(MX7D_GIC_BASE_ADDR); + + imx7d_cpuidle_gic_base = ioremap(MX7D_GIC_BASE_ADDR, MX7D_GIC_SIZE); + + imx7d_enable_rcosc(); + + /* code size should include cpuidle_pm_info size */ + if (!psci_ops.cpu_suspend) { + imx7d_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base + + sizeof(*cpuidle_pm_info), + &imx7d_low_power_idle, + MX7_CPUIDLE_OCRAM_SIZE - sizeof(*cpuidle_pm_info)); + } + + return cpuidle_register(&imx7d_cpuidle_driver, NULL); +} diff --git a/arch/arm/mach-imx/cpuidle.h b/arch/arm/mach-imx/cpuidle.h index ce552c096cae14..340b0e3af05f75 100644 --- a/arch/arm/mach-imx/cpuidle.h +++ b/arch/arm/mach-imx/cpuidle.h @@ -8,7 +8,11 @@ extern int imx5_cpuidle_init(void); extern int imx6q_cpuidle_init(void); extern int imx6sl_cpuidle_init(void); +extern int imx6sll_cpuidle_init(void); extern int imx6sx_cpuidle_init(void); +extern int imx6ul_cpuidle_init(void); +extern int imx7d_cpuidle_init(void); +extern int imx7d_enable_rcosc(void); extern int imx7ulp_cpuidle_init(void); #else static inline int imx5_cpuidle_init(void) @@ -23,10 +27,26 @@ static inline int imx6sl_cpuidle_init(void) { return 0; } +static inline int imx6sll_cpuidle_init(void) +{ + return 0; +} static inline int imx6sx_cpuidle_init(void) { return 0; } +static inline int imx6ul_cpuidle_init(void) +{ + return 0; +} +static inline int imx7d_cpuidle_init(void) +{ + return 0; +} +static inline int imx7d_enable_rcosc(void) +{ + return 0; +} static inline int imx7ulp_cpuidle_init(void) { return 0; diff --git a/arch/arm/mach-imx/ddr3_freq_imx6.S b/arch/arm/mach-imx/ddr3_freq_imx6.S new file mode 100644 index 00000000000000..e6f7f74f7d3220 --- /dev/null +++ b/arch/arm/mach-imx/ddr3_freq_imx6.S @@ -0,0 +1,1103 @@ +/* + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "hardware.h" + +#define MMDC0_MDPDC 0x4 +#define MMDC0_MDCF0 0x0c +#define MMDC0_MDCF1 0x10 +#define MMDC0_MDMISC 0x18 +#define MMDC0_MDSCR 0x1c +#define MMDC0_MAARCR 0x400 +#define MMDC0_MAPSR 0x404 +#define MMDC0_MADPCR0 0x410 +#define MMDC0_MPZQHWCTRL 0x800 +#define MMDC1_MPZQHWCTRL 0x4800 +#define MMDC0_MPODTCTRL 0x818 +#define MMDC1_MPODTCTRL 0x4818 +#define MMDC0_MPDGCTRL0 0x83c +#define MMDC1_MPDGCTRL0 0x483c +#define MMDC0_MPMUR0 0x8b8 +#define MMDC1_MPMUR0 0x48b8 + +#define CCM_CBCDR 0x14 +#define CCM_CBCMR 0x18 +#define CCM_CSCMR1 0x1c +#define CCM_CDHIPR 0x48 + +#define L2_CACHE_SYNC 0x730 +#define PL310_AUX_CTRL 0x104 +#define PL310_DCACHE_LOCKDOWN_BASE 0x900 +#define PL310_AUX_16WAY_BIT 0x10000 +#define PL310_LOCKDOWN_NBREGS 8 +#define PL310_LOCKDOWN_SZREG 4 +#define PL310_8WAYS_MASK 0x00FF +#define PL310_16WAYS_UPPERMASK 0xFF00 + +#define IMX6QP_REVISION_ID 0x630100 +#define ANADIG_DIGPROG 0x260 + +.extern iram_tlb_phys_addr + +.globl mx6_ddr3_freq_change_start +.globl mx6_ddr3_freq_change_end + + .align 3 + + .macro is_mx6qp + + /* check if the SOC is i.MX6QP */ + ldr r0, =IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR) + ldr r1, [r0, #ANADIG_DIGPROG] + ldr r2, =IMX6QP_REVISION_ID + cmp r1, r2 + + .endm + + .macro switch_to_528MHz + + /* check if periph_clk_sel is already set */ + ldr r0, [r6, #CCM_CBCDR] + and r0, r0, #(1 << 25) + cmp r0, #(1 << 25) + beq set_ahb_podf_before_switch + + /* change periph_clk to be sourced from pll3_clk. */ + ldr r0, [r6, #CCM_CBCMR] + bic r0, r0, #(3 << 12) + str r0, [r6, #CCM_CBCMR] + + ldr r0, [r6, #CCM_CBCDR] + bic r0, r0, #(0x38 << 20) + str r0, [r6, #CCM_CBCDR] + + /* + * set the AHB dividers before the switch, + * don't change AXI clock divider, + * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4, + */ + ldr r0, [r6, #CCM_CBCDR] + ldr r2, =0x3f1f00 + bic r0, r0, r2 + orr r0, r0, #0xd00 + orr r0, r0, #(1 << 16) + str r0, [r6, #CCM_CBCDR] + +wait_div_update528: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne wait_div_update528 + + /* now switch periph_clk to pll3_main_clk. */ + ldr r0, [r6, #CCM_CBCDR] + orr r0, r0, #(1 << 25) + str r0, [r6, #CCM_CBCDR] + +periph_clk_switch3: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne periph_clk_switch3 + + b switch_pre_periph_clk_528 + +set_ahb_podf_before_switch: + /* + * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4, + */ + ldr r0, [r6, #CCM_CBCDR] + ldr r2, =0x3f1f00 + bic r0, r0, r2 + orr r0, r0, #0xd00 + orr r0, r0, #(1 << 16) + str r0, [r6, #CCM_CBCDR] + +wait_div_update528_1: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne wait_div_update528_1 + +switch_pre_periph_clk_528: + + /* now switch pre_periph_clk to PLL2_528MHz. */ + ldr r0, [r6, #CCM_CBCMR] + bic r0, r0, #(0xc << 16) + str r0, [r6, #CCM_CBCMR] + + /* now switch periph_clk back. */ + ldr r0, [r6, #CCM_CBCDR] + bic r0, r0, #(1 << 25) + str r0, [r6, #CCM_CBCDR] + +periph_clk_switch4: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne periph_clk_switch4 + + .endm + + .macro switch_to_400MHz + + /* check if periph_clk_sel is already set. */ + ldr r0, [r6, #CCM_CBCDR] + and r0, r0, #(1 << 25) + cmp r0, #(1 << 25) + beq set_ahb_podf_before_switch1 + + /* change periph_clk to be sourced from pll3_clk. */ + ldr r0, [r6, #CCM_CBCMR] + bic r0, r0, #(3 << 12) + str r0, [r6, #CCM_CBCMR] + + ldr r0, [r6, #CCM_CBCDR] + bic r0, r0, #(0x38 << 24) + str r0, [r6, #CCM_CBCDR] + + /* now switch periph_clk to pll3_main_clk. */ + ldr r0, [r6, #CCM_CBCDR] + orr r0, r0, #(1 << 25) + str r0, [r6, #CCM_CBCDR] + +periph_clk_switch5: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne periph_clk_switch5 + + b switch_pre_periph_clk_400 + +set_ahb_podf_before_switch1: + /* + * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4, + */ + ldr r0, [r6, #CCM_CBCDR] + ldr r2, =0x3f1f00 + bic r0, r0, r2 + orr r0, r0, #(0x9 << 8) + orr r0, r0, #(1 << 16) + str r0, [r6, #CCM_CBCDR] + +wait_div_update400_1: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne wait_div_update400_1 + +switch_pre_periph_clk_400: + + /* now switch pre_periph_clk to PFD_400MHz. */ + ldr r0, [r6, #CCM_CBCMR] + bic r0, r0, #(0xc << 16) + orr r0, r0, #(0x4 << 16) + str r0, [r6, #CCM_CBCMR] + + /* now switch periph_clk back. */ + ldr r0, [r6, #CCM_CBCDR] + bic r0, r0, #(1 << 25) + str r0, [r6, #CCM_CBCDR] + +periph_clk_switch6: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne periph_clk_switch6 + + /* + * change AHB divider so that we are at 400/3=133MHz. + * don't change AXI clock divider. + * set the MMDC_DIV=1, AXI_DIV=2, AHB_DIV=3, + */ + ldr r0, [r6, #CCM_CBCDR] + ldr r2, =0x3f1f00 + bic r0, r0, r2 + orr r0, r0, #(0x9 << 8) + orr r0, r0, #(1 << 16) + str r0, [r6, #CCM_CBCDR] + +wait_div_update400_2: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne wait_div_update400_2 + + .endm + + .macro switch_to_50MHz + + /* check if periph_clk_sel is already set. */ + ldr r0, [r6, #CCM_CBCDR] + and r0, r0, #(1 << 25) + cmp r0, #(1 << 25) + beq switch_pre_periph_clk_50 + + /* + * set the periph_clk to be sourced from PLL2_PFD_200M + * change periph_clk to be sourced from pll3_clk. + * ensure PLL3 is the source and set the divider to 1. + */ + ldr r0, [r6, #CCM_CBCMR] + bic r0, r0, #(0x3 << 12) + str r0, [r6, #CCM_CBCMR] + + ldr r0, [r6, #CCM_CBCDR] + bic r0, r0, #(0x38 << 24) + str r0, [r6, #CCM_CBCDR] + + /* now switch periph_clk to pll3_main_clk. */ + ldr r0, [r6, #CCM_CBCDR] + orr r0, r0, #(1 << 25) + str r0, [r6, #CCM_CBCDR] + +periph_clk_switch_50: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne periph_clk_switch_50 + +switch_pre_periph_clk_50: + + /* now switch pre_periph_clk to PFD_200MHz. */ + ldr r0, [r6, #CCM_CBCMR] + orr r0, r0, #(0xc << 16) + str r0, [r6, #CCM_CBCMR] + + /* + * set the MMDC_DIV=4, AXI_DIV = 4, AHB_DIV=8, + */ + ldr r0, [r6, #CCM_CBCDR] + ldr r2, =0x3f1f00 + bic r0, r0, r2 + orr r0, r0, #(0x18 << 16) + orr r0, r0, #(0x3 << 16) + + /* + * if changing AHB divider remember to change + * the IPGPER divider too below. + */ + orr r0, r0, #0x1d00 + str r0, [r6, #CCM_CBCDR] + +wait_div_update_50: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne wait_div_update_50 + + /* now switch periph_clk back. */ + ldr r0, [r6, #CCM_CBCDR] + bic r0, r0, #(1 << 25) + str r0, [r6, #CCM_CBCDR] + +periph_clk_switch2: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne periph_clk_switch2 + + .endm + + .macro switch_to_24MHz + /* + * change the freq now try setting DDR to 24MHz. + * source it from the periph_clk2 ensure the + * periph_clk2 is sourced from 24MHz and the + * divider is 1. + */ + + ldr r0, [r6, #CCM_CBCMR] + bic r0, r0, #(0x3 << 12) + orr r0, r0, #(1 << 12) + str r0, [r6, #CCM_CBCMR] + + ldr r0, [r6, #CCM_CBCDR] + bic r0, r0, #(0x38 << 24) + str r0, [r6, #CCM_CBCDR] + + /* now switch periph_clk to 24MHz. */ + ldr r0, [r6, #CCM_CBCDR] + orr r0, r0, #(1 << 25) + str r0, [r6, #CCM_CBCDR] + +periph_clk_switch1: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne periph_clk_switch1 + + /* change all the dividers to 1. */ + ldr r0, [r6, #CCM_CBCDR] + ldr r2, =0x3f1f00 + bic r0, r0, r2 + orr r0, r0, #(1 << 8) + str r0, [r6, #CCM_CBCDR] + + /* Wait for the divider to change. */ +wait_div_update: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne wait_div_update + + .endm + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r11, lr} + + ldr r7, =v7_flush_kern_cache_all + mov lr, pc + mov pc, r7 + pop {r0 - r11, lr} + + /* disable d-cache */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + dsb + isb + + push {r0 - r11, lr} + + ldr r7, =v7_flush_kern_cache_all + mov lr, pc + mov pc, r7 + pop {r0 - r11, lr} + + .endm + +/* + * mx6_ddr3_freq_change + * + * idle the processor (eg, wait for interrupt). + * make sure DDR is in self-refresh. + * IRQs are already disabled. + */ +ENTRY(mx6_ddr3_freq_change) + +mx6_ddr3_freq_change_start: + stmfd sp!, {r4-r12} + + /* + * r5 -> mmdc_base + * r6 -> ccm_base + * r7 -> iomux_base + * r12 -> l2_base + */ + mov r4, r0 + mov r8, r1 + mov r9, r2 + mov r11, r3 + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* + * Need to flush and disable L1 before + * disabling L2, we need data to + * coherent. Flushing L1 pushes + * everyhting to L2. We sync L2 later, but + * it can still have dirty lines. + * While exiting, we need to enable L2 first + * and then L1. + */ + disable_l1_dcache + +#ifdef CONFIG_CACHE_L2X0 + /* + * Make sure the L2 buffers are drained. + * Sync operation on L2 drains the buffers. + */ + ldr r12, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + + /* Wait for background operations to complete. */ +wait_for_l2_to_idle: + ldr r1, [r12, #L2_CACHE_SYNC] + cmp r1, #0x0 + bne wait_for_l2_to_idle + + mov r1, #0x0 + str r1, [r12, #L2_CACHE_SYNC] + + dsb + isb + + ldr r1, [r12, #PL310_AUX_CTRL] + tst r1, #PL310_AUX_16WAY_BIT + mov r1, #PL310_8WAYS_MASK + orrne r1, #PL310_16WAYS_UPPERMASK + mov r6, #PL310_LOCKDOWN_NBREGS + add r5, r12, #PL310_DCACHE_LOCKDOWN_BASE +1: /* lock Dcache and Icache */ + str r1, [r5], #PL310_LOCKDOWN_SZREG + str r1, [r5], #PL310_LOCKDOWN_SZREG + subs r6, r6, #1 + bne 1b +#endif + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + + /* Now switch the TTBR. */ + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + + ldr r5, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR) + ldr r6, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR) + ldr r7, =IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR) + + /* Read the Original MU delay value */ + ldr r1, [r5, #MMDC0_MPMUR0] + mov r10, r1, lsr #16 + ldr r1, =0x3ff + and r10, r10, r1 + + /* disable automatic power saving. */ + ldr r0, [r5, #MMDC0_MAPSR] + orr r0, r0, #0x01 + str r0, [r5, #MMDC0_MAPSR] + + /* disable MMDC power down timer. */ + ldr r0, [r5, #MMDC0_MDPDC] + bic r0, r0, #(0xff << 8) + str r0, [r5, #MMDC0_MDPDC] + + /* delay for a while */ + ldr r1, =4 +delay1: + ldr r2, =0 +cont1: + ldr r0, [r5, r2] + add r2, r2, #4 + cmp r2, #16 + bne cont1 + sub r1, r1, #1 + cmp r1, #0 + bgt delay1 + + /* set CON_REG */ + ldr r0, =0x8000 + str r0, [r5, #MMDC0_MDSCR] +poll_conreq_set_1: + ldr r0, [r5, #MMDC0_MDSCR] + and r0, r0, #(0x4 << 12) + cmp r0, #(0x4 << 12) + bne poll_conreq_set_1 + + /* + * if requested frequency is great than + * 300MHz, skip setting bypass adopt mode. + */ + ldr r1, =300000000 + cmp r4, r1 + bge 1f + + is_mx6qp + bne 1f + /* Switch to adopt mode, set MMDC0_MAARCR bit25~26 to 2b'01 */ + ldr r0, [r5, #MMDC0_MAARCR] + bic r0, r0, #(0x3 << 25) + orr r0, #(0x01 << 25) + str r0 , [r5, #MMDC0_MAARCR] +1: + ldr r0, =0x00008050 + str r0, [r5, #MMDC0_MDSCR] + ldr r0, =0x00008058 + str r0, [r5, #MMDC0_MDSCR] + + /* + * if requested frequency is greater than + * 300MHz go to DLL on mode. + */ + ldr r1, =300000000 + cmp r4, r1 + bge dll_on_mode + +dll_off_mode: + + /* if DLL is currently on, turn it off. */ + cmp r9, #1 + beq continue_dll_off_1 + + ldr r0, =0x00018031 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x00018039 + str r0, [r5, #MMDC0_MDSCR] + + ldr r1, =10 +delay1a: + ldr r2, =0 +cont1a: + ldr r0, [r5, r2] + add r2, r2, #4 + cmp r2, #16 + bne cont1a + sub r1, r1, #1 + cmp r1, #0 + bgt delay1a + +continue_dll_off_1: + /* set DVFS - enter self refresh mode */ + ldr r0, [r5, #MMDC0_MAPSR] + orr r0, r0, #(1 << 21) + str r0, [r5, #MMDC0_MAPSR] + + /* de-assert con_req */ + mov r0, #0x0 + str r0, [r5, #MMDC0_MDSCR] + +poll_dvfs_set_1: + ldr r0, [r5, #MMDC0_MAPSR] + and r0, r0, #(1 << 25) + cmp r0, #(1 << 25) + bne poll_dvfs_set_1 + + ldr r1, =24000000 + cmp r4, r1 + beq switch_freq_24 + + switch_to_50MHz + b continue_dll_off_2 + +switch_freq_24: + switch_to_24MHz + +continue_dll_off_2: + + /* set SBS - block ddr accesses */ + ldr r0, [r5, #MMDC0_MADPCR0] + orr r0, r0, #(1 << 8) + str r0, [r5, #MMDC0_MADPCR0] + + /* clear DVFS - exit from self refresh mode */ + ldr r0, [r5, #MMDC0_MAPSR] + bic r0, r0, #(1 << 21) + str r0, [r5, #MMDC0_MAPSR] + +poll_dvfs_clear_1: + ldr r0, [r5, #MMDC0_MAPSR] + and r0, r0, #(1 << 25) + cmp r0, #(1 << 25) + beq poll_dvfs_clear_1 + + /* if DLL was previously on, continue DLL off routine. */ + cmp r9, #1 + beq continue_dll_off_3 + + ldr r0, =0x00018031 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x00018039 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x08208030 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x08208038 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x00088032 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x0008803A + str r0, [r5, #MMDC0_MDSCR] + + /* delay for a while. */ + ldr r1, =4 +delay_1: + ldr r2, =0 +cont_1: + ldr r0, [r5, r2] + add r2, r2, #4 + cmp r2, #16 + bne cont_1 + sub r1, r1, #1 + cmp r1, #0 + bgt delay_1 + + ldr r0, [r5, #MMDC0_MDCF0] + bic r0, r0, #0xf + orr r0, r0, #0x3 + str r0, [r5, #MMDC0_MDCF0] + + ldr r0, [r5, #MMDC0_MDCF1] + bic r0, r0, #0x7 + orr r0, r0, #0x4 + str r0, [r5, #MMDC0_MDCF1] + + ldr r0, [r5, #MMDC0_MDMISC] + bic r0, r0, #(0x3 << 16) /* walat = 0x1 */ + orr r0, r0, #(0x1 << 16) + bic r0, r0, #(0x7 << 6) /* ralat = 0x2 */ + orr r0, r0, #(0x2 << 6) + str r0, [r5, #MMDC0_MDMISC] + + /* enable dqs pull down in the IOMUX. */ + ldr r1, [r11] + add r11, r11, #8 + ldr r2, =0x3028 +update_iomux: + ldr r0, [r11, #0x0] + ldr r3, [r7, r0] + bic r3, r3, r2 + orr r3, r3, #(0x3 << 12) + orr r3, r3, #0x28 + str r3, [r7, r0] + add r11, r11, #8 + sub r1, r1, #1 + cmp r1, #0 + bgt update_iomux + + /* ODT disabled. */ + ldr r0, =0x0 + ldr r2, =MMDC0_MPODTCTRL + str r0, [r5, r2] + ldr r2, =MMDC1_MPODTCTRL + str r0, [r5, r2] + + /* DQS gating disabled. */ + ldr r2, =MMDC0_MPDGCTRL0 + ldr r0, [r5, r2] + orr r0, r0, #(1 << 29) + str r0, [r5, r2] + + ldr r2, =MMDC1_MPDGCTRL0 + ldr r0, [r5, r2] + orr r0, r0, #(0x1 << 29) + str r0, [r5, r2] + + /* Add workaround for ERR005778.*/ + /* double the original MU_UNIT_DEL_NUM. */ + lsl r10, r10, #1 + + /* Bypass the automatic MU by setting the mu_byp_en */ + ldr r2, [r5, #MMDC0_MPMUR0] + orr r2, r2, #0x400 + orr r2, r2, r10 + str r2, [r5, #MMDC0_MPMUR0] + ldr r0, =MMDC1_MPMUR0 + str r2, [r5, r0] + + /* Now perform a force measure */ + ldr r0, [r5, #MMDC0_MPMUR0] + orr r0, r0, #0x800 + str r0, [r5, #MMDC0_MPMUR0] + ldr r2, =MMDC1_MPMUR0 + str r0, [r5, r2] + /* Wait for FRC_MSR to clear. */ +1: + ldr r0, [r5, #MMDC0_MPMUR0] + and r0, r0, #0x800 + ldr r1, [r5, r2] + and r1, r1, #0x800 + orr r0, r0, r1 + cmp r0, #0x0 + bne 1b + +continue_dll_off_3: + /* clear SBS - unblock accesses to DDR. */ + ldr r0, [r5, #MMDC0_MADPCR0] + bic r0, r0, #(0x1 << 8) + str r0, [r5, #MMDC0_MADPCR0] + + mov r0, #0x0 + str r0, [r5, #MMDC0_MDSCR] +poll_conreq_clear_1: + ldr r0, [r5, #MMDC0_MDSCR] + and r0, r0, #(0x4 << 12) + cmp r0, #(0x4 << 12) + beq poll_conreq_clear_1 + + b done + +dll_on_mode: + /* assert DVFS - enter self refresh mode. */ + ldr r0, [r5, #MMDC0_MAPSR] + orr r0, r0, #(1 << 21) + str r0, [r5, #MMDC0_MAPSR] + + /* de-assert CON_REQ. */ + mov r0, #0x0 + str r0, [r5, #MMDC0_MDSCR] + + /* poll DVFS ack. */ +poll_dvfs_set_2: + ldr r0, [r5, #MMDC0_MAPSR] + and r0, r0, #(1 << 25) + cmp r0, #(1 << 25) + bne poll_dvfs_set_2 + + ldr r1, =528000000 + cmp r4, r1 + beq switch_freq_528 + + switch_to_400MHz + + b continue_dll_on + +switch_freq_528: + switch_to_528MHz + +continue_dll_on: + + /* set SBS step-by-step mode. */ + ldr r0, [r5, #MMDC0_MADPCR0] + orr r0, r0, #( 1 << 8) + str r0, [r5, #MMDC0_MADPCR0] + + /* clear DVFS - exit self refresh mode. */ + ldr r0, [r5, #MMDC0_MAPSR] + bic r0, r0, #(1 << 21) + str r0, [r5, #MMDC0_MAPSR] + +poll_dvfs_clear_2: + ldr r0, [r5, #MMDC0_MAPSR] + and r0, r0, #(1 << 25) + cmp r0, #(1 << 25) + beq poll_dvfs_clear_2 + + /* if DLL is currently off, turn it back on. */ + cmp r9, #0 + beq update_calibration_only + + /* issue zq calibration command */ + ldr r0, [r5, #MMDC0_MPZQHWCTRL] + orr r0, r0, #0x3 + str r0, [r5, #MMDC0_MPZQHWCTRL] + ldr r2, =MMDC1_MPZQHWCTRL + str r0, [r5, r2] + + /* enable DQS gating. */ + ldr r2, =MMDC0_MPDGCTRL0 + ldr r0, [r5, r2] + bic r0, r0, #(1 << 29) + str r0, [r5, r2] + + ldr r2, =MMDC1_MPDGCTRL0 + ldr r0, [r5, r2] + bic r0, r0, #(1 << 29) + str r0, [r5, r2] + + /* force measure. */ + ldr r0, =0x00000800 + str r0, [r5, #MMDC0_MPMUR0] + ldr r2, =MMDC1_MPMUR0 + str r0, [r5, r2] + + /* Wait for FRC_MSR to clear. */ +1: + ldr r0, [r5, #MMDC0_MPMUR0] + and r0, r0, #0x800 + ldr r1, [r5, r2] + and r1, r1, #0x800 + orr r0, r0, r1 + cmp r0, #0x0 + bne 1b + + /* disable dqs pull down in the IOMUX. */ + ldr r1, [r11] + add r11, r11, #8 +update_iomux1: + ldr r0, [r11, #0x0] + ldr r3, [r11, #0x4] + str r3, [r7, r0] + add r11, r11, #8 + sub r1, r1, #1 + cmp r1, #0 + bgt update_iomux1 + + /* config MMDC timings to 528MHz. */ + ldr r9, [r8] + add r8, r8, #8 + ldr r0, [r8, #0x0] + ldr r3, [r8, #0x4] + str r3, [r5, r0] + add r8, r8, #8 + + ldr r0, [r8, #0x0] + ldr r3, [r8, #0x4] + str r3, [r5, r0] + add r8, r8, #8 + + /* configure ddr devices to dll on, odt. */ + ldr r0, =0x00048031 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x00048039 + str r0, [r5, #MMDC0_MDSCR] + + /* delay for while. */ + ldr r1, =4 +delay7: + ldr r2, =0 +cont7: + ldr r0, [r5, r2] + add r2, r2, #4 + cmp r2, #16 + bne cont7 + sub r1, r1, #1 + cmp r1, #0 + bgt delay7 + + /* reset dll. */ + ldr r0, =0x09408030 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x09408038 + str r0, [r5, #MMDC0_MDSCR] + + /* delay for while. */ + ldr r1, =100 +delay8: + ldr r2, =0 +cont8: + ldr r0, [r5, r2] + add r2, r2, #4 + cmp r2, #16 + bne cont8 + sub r1, r1, #1 + cmp r1, #0 + bgt delay8 + + ldr r0, [r8, #0x0] + ldr r3, [r8, #0x4] + str r3, [r5, r0] + add r8, r8, #8 + + ldr r0, [r8, #0x0] + ldr r3, [r8, #0x4] + str r3, [r5, r0] + add r8, r8, #8 + + ldr r0, =0x00428031 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x00428039 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, [r8, #0x0] + ldr r3, [r8, #0x4] + str r3, [r5, r0] + add r8, r8, #8 + + ldr r0, [r8, #0x0] + ldr r3, [r8, #0x4] + str r3, [r5, r0] + add r8, r8, #8 + + /* issue a zq command. */ + ldr r0, =0x04008040 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x04008048 + str r0, [r5, #MMDC0_MDSCR] + + /* MMDC ODT enable. */ + ldr r0, [r8, #0x0] + ldr r3, [r8, #0x4] + str r3, [r5, r0] + add r8, r8, #8 + + ldr r2, =0x4818 + str r3, [r5, r2] + + /* delay for while. */ + ldr r1, =40 +delay15: + ldr r2, =0 +cont15: + ldr r0, [r5, r2] + add r2, r2, #4 + cmp r2, #16 + bne cont15 + sub r1, r1, #1 + cmp r1, #0 + bgt delay15 + + /* enable MMDC power down timer. */ + ldr r0, [r5, #MMDC0_MDPDC] + orr r0, r0, #(0x55 << 8) + str r0, [r5, #MMDC0_MDPDC] + + b update_calibration + +update_calibration_only: + ldr r1, [r8] + sub r1, r1, #7 + add r8, r8, #64 + b update_calib + +update_calibration: + /* write the new calibration values. */ + mov r1, r9 + sub r1, r1, #7 + +update_calib: + ldr r0, [r8, #0x0] + ldr r3, [r8, #0x4] + str r3, [r5, r0] + add r8, r8, #8 + sub r1, r1, #1 + cmp r1, #0 + bgt update_calib + + /* perform a force measurement. */ + ldr r0, =0x800 + str r0, [r5, #MMDC0_MPMUR0] + ldr r2, =MMDC1_MPMUR0 + str r0, [r5, r2] + + /* Wait for FRC_MSR to clear. */ +1: + ldr r0, [r5, #MMDC0_MPMUR0] + and r0, r0, #0x800 + ldr r1, [r5, r2] + and r1, r1, #0x800 + orr r0, r0, r1 + cmp r0, #0x0 + bne 1b + + /* clear SBS - unblock DDR accesses. */ + ldr r0, [r5, #MMDC0_MADPCR0] + bic r0, r0, #(1 << 8) + str r0, [r5, #MMDC0_MADPCR0] + + is_mx6qp + bne 3f + /* + * Switch back to adopt_bp mode, set MMDC0_MAARCR + * bit25~26 to 2b'10. + */ + ldr r0, [r5, #MMDC0_MAARCR] + bic r0, r0, #(0x3 << 25) + orr r0, r0, #(0x2 << 25) + str r0, [r5, #MMDC0_MAARCR] +3: + mov r0, #0x0 + str r0, [r5, #MMDC0_MDSCR] +poll_conreq_clear_2: + ldr r0, [r5, #MMDC0_MDSCR] + and r0, r0, #(0x4 << 12) + cmp r0, #(0x4 << 12) + beq poll_conreq_clear_2 + +done: + /* MMDC0_MAPSR adopt power down enable. */ + ldr r0, [r5, #MMDC0_MAPSR] + bic r0, r0, #0x01 + str r0, [r5, #MMDC0_MAPSR] + +#ifdef CONFIG_CACHE_L2X0 + ldr r1, [r12, #PL310_AUX_CTRL] + tst r1, #PL310_AUX_16WAY_BIT + mov r6, #PL310_LOCKDOWN_NBREGS + mov r1, #0x00 /* 8 ways mask */ + orrne r1, #0x0000 /* 16 ways mask */ + add r5, r12, #PL310_DCACHE_LOCKDOWN_BASE +1: /* lock Dcache and Icache */ + str r1, [r5], #PL310_LOCKDOWN_SZREG + str r1, [r5], #PL310_LOCKDOWN_SZREG + subs r6, r6, #1 + bne 1b + + isb + dsb +#endif + + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + isb + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + isb + dsb + + /* restore registers */ + ldmfd sp!, {r4-r12} + mov pc, lr + + /* + * Add ltorg here to ensure that all + * literals are stored here and are + * within the text space. + */ + .ltorg +mx6_ddr3_freq_change_end: diff --git a/arch/arm/mach-imx/ddr3_freq_imx6sx.S b/arch/arm/mach-imx/ddr3_freq_imx6sx.S new file mode 100644 index 00000000000000..1ac0d017bdf985 --- /dev/null +++ b/arch/arm/mach-imx/ddr3_freq_imx6sx.S @@ -0,0 +1,764 @@ +/* + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "hardware.h" + +.globl imx6_up_ddr3_freq_change_start +.globl imx6_up_ddr3_freq_change_end + +#define MMDC0_MDPDC 0x4 +#define MMDC0_MDCF0 0xc +#define MMDC0_MDCF1 0x10 +#define MMDC0_MDMISC 0x18 +#define MMDC0_MDSCR 0x1c +#define MMDC0_MAPSR 0x404 +#define MMDC0_MADPCR0 0x410 +#define MMDC0_MPZQHWCTRL 0x800 +#define MMDC0_MPODTCTRL 0x818 +#define MMDC0_MPDGCTRL0 0x83c +#define MMDC0_MPMUR0 0x8b8 + +#define CCM_CBCDR 0x14 +#define CCM_CBCMR 0x18 +#define CCM_CSCMR1 0x1c +#define CCM_CDHIPR 0x48 + +#define L2_CACHE_SYNC 0x730 +#define PL310_AUX_CTRL 0x104 +#define PL310_DCACHE_LOCKDOWN_BASE 0x900 +#define PL310_AUX_16WAY_BIT 0x10000 +#define PL310_LOCKDOWN_NBREGS 8 +#define PL310_LOCKDOWN_SZREG 4 +#define PL310_8WAYS_MASK 0x00FF +#define PL310_16WAYS_UPPERMASK 0xFF00 + +#define BUSFREQ_INFO_FREQ_OFFSET 0x0 +#define BUSFREQ_INFO_DDR_SETTINGS_OFFSET 0x4 +#define BUSFREQ_INFO_DLL_OFF_OFFSET 0x8 +#define BUSFREQ_INFO_IOMUX_OFFSETS_OFFSET 0xc +#define BUSFREQ_INFO_MU_DELAY_OFFSET 0x10 + +.extern iram_tlb_phys_addr + + .align 3 + + /* Check if the cpu is cortex-a7 */ + .macro is_ca7 + + /* Read the primary cpu number is MPIDR */ + mrc p15, 0, r7, c0, c0, 0 + ldr r8, =0xfff0 + and r7, r7, r8 + ldr r8, =0xc070 + cmp r7, r8 + + .endm + + .macro do_delay + +1: + ldr r9, =0 +2: + ldr r10, [r4, r9] + add r9, r9, #4 + cmp r9, #16 + bne 2b + sub r8, r8, #1 + cmp r8, #0 + bgt 1b + + .endm + + .macro wait_for_ccm_handshake + +3: + ldr r8, [r5, #CCM_CDHIPR] + cmp r8, #0 + bne 3b + + .endm + + .macro switch_to_400MHz + + /* check whether periph2_clk is already from top path */ + ldr r8, [r5, #CCM_CBCDR] + ands r8, #(1 << 26) + beq skip_periph2_clk2_switch_400m + + /* now switch periph2_clk back. */ + ldr r8, [r5, #CCM_CBCDR] + bic r8, r8, #(1 << 26) + str r8, [r5, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* + * on i.MX6SX, pre_periph2_clk will be always from + * pll2_pfd2, so no need to set pre_periph2_clk + * parent, just set the mmdc divider directly. + */ +skip_periph2_clk2_switch_400m: + + /* fabric_mmdc_podf to 0 */ + ldr r8, [r5, #CCM_CBCDR] + bic r8, r8, #(0x7 << 3) + str r8, [r5, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro switch_to_50MHz + + /* check whether periph2_clk is already from top path */ + ldr r8, [r5, #CCM_CBCDR] + ands r8, #(1 << 26) + beq skip_periph2_clk2_switch_50m + + /* now switch periph2_clk back. */ + ldr r8, [r5, #CCM_CBCDR] + bic r8, r8, #(1 << 26) + str r8, [r5, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* + * on i.MX6SX, pre_periph2_clk will be always from + * pll2_pfd2, so no need to set pre_periph2_clk + * parent, just set the mmdc divider directly. + */ +skip_periph2_clk2_switch_50m: + + /* fabric_mmdc_podf to 7 so that mmdc is 400 / 8 = 50MHz */ + ldr r8, [r5, #CCM_CBCDR] + orr r8, r8, #(0x7 << 3) + str r8, [r5, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro switch_to_24MHz + + /* periph2_clk2 sel to OSC_CLK */ + ldr r8, [r5, #CCM_CBCMR] + orr r8, r8, #(1 << 20) + str r8, [r5, #CCM_CBCMR] + + /* periph2_clk2_podf to 0 */ + ldr r8, [r5, #CCM_CBCDR] + bic r8, r8, #0x7 + str r8, [r5, #CCM_CBCDR] + + /* periph2_clk sel to periph2_clk2 */ + ldr r8, [r5, #CCM_CBCDR] + orr r8, r8, #(0x1 << 26) + str r8, [r5, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* fabric_mmdc_podf to 0 */ + ldr r8, [r5, #CCM_CBCDR] + bic r8, r8, #(0x7 << 3) + str r8, [r5, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + +/* + * imx6_up_ddr3_freq_change + * Below code can be used by i.MX6SX and i.MX6UL. + * + * idle the processor (eg, wait for interrupt). + * make sure DDR is in self-refresh. + * IRQs are already disabled. + */ +ENTRY(imx6_up_ddr3_freq_change) + +imx6_up_ddr3_freq_change_start: + stmfd sp!, {r4 - r11} + + ldr r1, [r0, #BUSFREQ_INFO_DDR_SETTINGS_OFFSET] + ldr r2, [r0, #BUSFREQ_INFO_DLL_OFF_OFFSET] + ldr r3, [r0, #BUSFREQ_INFO_IOMUX_OFFSETS_OFFSET] + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Disable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + ldr r4, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR) + ldr r5, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR) + ldr r6, =IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR) + + is_ca7 + beq skip_disable_l2 + +#ifdef CONFIG_CACHE_L2X0 + /* + * make sure the L2 buffers are drained, + * sync operation on L2 drains the buffers. + */ + ldr r8, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + + /* Wait for background operations to complete. */ +wait_for_l2_to_idle: + ldr r7, [r8, #0x730] + cmp r7, #0x0 + bne wait_for_l2_to_idle + + mov r7, #0x0 + str r7, [r8, #L2_CACHE_SYNC] + + /* Lock L2. */ + + ldr r9, [r8, #PL310_AUX_CTRL] + tst r9, #PL310_AUX_16WAY_BIT + mov r9, #PL310_8WAYS_MASK + orrne r9, #PL310_16WAYS_UPPERMASK + mov r10, #PL310_LOCKDOWN_NBREGS + add r11, r8, #PL310_DCACHE_LOCKDOWN_BASE +1: /* lock Dcache and Icache */ + str r9, [r11], #PL310_LOCKDOWN_SZREG + str r9, [r11], #PL310_LOCKDOWN_SZREG + subs r10, r10, #1 + bne 1b + + /* + * The second dsb might be needed to keep cache sync (device write) + * ordering with the memory accesses before it. + */ + dsb + isb +#endif + +skip_disable_l2: + /* disable automatic power saving. */ + ldr r8, [r4, #MMDC0_MAPSR] + orr r8, r8, #0x1 + str r8, [r4, #MMDC0_MAPSR] + + /* disable MMDC power down timer. */ + ldr r8, [r4, #MMDC0_MDPDC] + bic r8, r8, #(0xff << 8) + str r8, [r4, #MMDC0_MDPDC] + + /* delay for a while */ + ldr r8, =4 + do_delay + + /* set CON_REG */ + ldr r8, =0x8000 + str r8, [r4, #MMDC0_MDSCR] +poll_conreq_set_1: + ldr r8, [r4, #MMDC0_MDSCR] + and r8, r8, #(0x4 << 12) + cmp r8, #(0x4 << 12) + bne poll_conreq_set_1 + + /* + * if requested frequency is greater than + * 300MHz go to DLL on mode. + */ + ldr r8, [r0, #BUSFREQ_INFO_FREQ_OFFSET] + ldr r9, =300000000 + cmp r8, r9 + bge dll_on_mode + +dll_off_mode: + /* if DLL is currently on, turn it off. */ + cmp r2, #1 + beq continue_dll_off_1 + + ldr r8, =0x00018031 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x00018039 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =10 + do_delay + +continue_dll_off_1: + /* set DVFS - enter self refresh mode */ + ldr r8, [r4, #MMDC0_MAPSR] + orr r8, r8, #(1 << 21) + str r8, [r4, #MMDC0_MAPSR] + + /* de-assert con_req */ + mov r8, #0x0 + str r8, [r4, #MMDC0_MDSCR] + +poll_dvfs_set_1: + ldr r8, [r4, #MMDC0_MAPSR] + and r8, r8, #(1 << 25) + cmp r8, #(1 << 25) + bne poll_dvfs_set_1 + + ldr r8, [r0, #BUSFREQ_INFO_FREQ_OFFSET] + ldr r9, =24000000 + cmp r8, r9 + beq switch_freq_24 + + switch_to_50MHz + b continue_dll_off_2 + +switch_freq_24: + switch_to_24MHz + +continue_dll_off_2: + /* set SBS - block ddr accesses */ + ldr r8, [r4, #MMDC0_MADPCR0] + orr r8, r8, #(1 << 8) + str r8, [r4, #MMDC0_MADPCR0] + + /* clear DVFS - exit from self refresh mode */ + ldr r8, [r4, #MMDC0_MAPSR] + bic r8, r8, #(1 << 21) + str r8, [r4, #MMDC0_MAPSR] + +poll_dvfs_clear_1: + ldr r8, [r4, #MMDC0_MAPSR] + and r8, r8, #(1 << 25) + cmp r8, #(1 << 25) + beq poll_dvfs_clear_1 + + /* if DLL was previously on, continue DLL off routine. */ + cmp r2, #1 + beq continue_dll_off_3 + + ldr r8, =0x00018031 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x00018039 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x04208030 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x04208038 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x00088032 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x0008803A + str r8, [r4, #MMDC0_MDSCR] + + /* delay for a while. */ + ldr r8, =4 + do_delay + + ldr r8, [r4, #MMDC0_MDCF0] + bic r8, r8, #0xf + orr r8, r8, #0x3 + str r8, [r4, #MMDC0_MDCF0] + + ldr r8, [r4, #MMDC0_MDCF1] + bic r8, r8, #0x7 + orr r8, r8, #0x4 + str r8, [r4, #MMDC0_MDCF1] + + ldr r8, [r4, #MMDC0_MDMISC] + bic r8, r8, #(0x3 << 16) /* walat = 0x1 */ + orr r8, r8, #(0x1 << 16) + bic r8, r8, #(0x7 << 6) /* ralat = 0x2 */ + orr r8, r8, #(0x2 << 6) + str r8, [r4, #MMDC0_MDMISC] + + /* enable dqs pull down in the IOMUX. */ + ldr r8, [r3] + add r3, r3, #8 + ldr r9, =0x3028 +update_iomux: + ldr r10, [r3] + ldr r11, [r6, r10] + bic r11, r11, r9 + orr r11, r11, #(0x3 << 12) + orr r11, r11, #0x28 + str r11, [r6, r10] + add r3, r3, #8 + sub r8, r8, #1 + cmp r8, #0 + bgt update_iomux + + /* ODT disabled. */ + ldr r8, =0x0 + str r8, [r4, #MMDC0_MPODTCTRL] + + /* DQS gating disabled. */ + ldr r8, [r4, #MMDC0_MPDGCTRL0] + orr r8, r8, #(1 << 29) + str r8, [r4, #MMDC0_MPDGCTRL0] + + /* Add workaround for ERR005778.*/ + /* double the original MU_UNIT_DEL_NUM. */ + ldr r8, [r0, #BUSFREQ_INFO_MU_DELAY_OFFSET] + lsl r8, r8, #1 + + /* Bypass the automatic MU by setting the mu_byp_en */ + ldr r10, [r4, #MMDC0_MPMUR0] + orr r10, r10, #0x400 + /* Set the MU_BYP_VAL */ + orr r10, r10, r8 + str r10, [r4, #MMDC0_MPMUR0] + + /* Now perform a force measure */ + ldr r8, [r4, #MMDC0_MPMUR0] + orr r8, r8, #0x800 + str r8, [r4, #MMDC0_MPMUR0] + /* Wait for FRC_MSR to clear. */ +1: + ldr r8, [r4, #MMDC0_MPMUR0] + and r8, r8, #0x800 + cmp r8, #0x0 + bne 1b + +continue_dll_off_3: + /* clear SBS - unblock accesses to DDR. */ + ldr r8, [r4, #MMDC0_MADPCR0] + bic r8, r8, #(0x1 << 8) + str r8, [r4, #MMDC0_MADPCR0] + + mov r8, #0x0 + str r8, [r4, #MMDC0_MDSCR] +poll_conreq_clear_1: + ldr r8, [r4, #MMDC0_MDSCR] + and r8, r8, #(0x4 << 12) + cmp r8, #(0x4 << 12) + beq poll_conreq_clear_1 + + b done + +dll_on_mode: + /* assert DVFS - enter self refresh mode. */ + ldr r8, [r4, #MMDC0_MAPSR] + orr r8, r8, #(1 << 21) + str r8, [r4, #MMDC0_MAPSR] + + /* de-assert CON_REQ. */ + mov r8, #0x0 + str r8, [r4, #MMDC0_MDSCR] + + /* poll DVFS ack. */ +poll_dvfs_set_2: + ldr r8, [r4, #MMDC0_MAPSR] + and r8, r8, #(1 << 25) + cmp r8, #(1 << 25) + bne poll_dvfs_set_2 + + switch_to_400MHz + + /* set SBS step-by-step mode. */ + ldr r8, [r4, #MMDC0_MADPCR0] + orr r8, r8, #(1 << 8) + str r8, [r4, #MMDC0_MADPCR0] + + /* clear DVFS - exit self refresh mode. */ + ldr r8, [r4, #MMDC0_MAPSR] + bic r8, r8, #(1 << 21) + str r8, [r4, #MMDC0_MAPSR] + +poll_dvfs_clear_2: + ldr r8, [r4, #MMDC0_MAPSR] + ands r8, r8, #(1 << 25) + bne poll_dvfs_clear_2 + + /* if DLL is currently off, turn it back on. */ + cmp r2, #0 + beq update_calibration_only + + /* issue zq calibration command */ + ldr r8, [r4, #MMDC0_MPZQHWCTRL] + orr r8, r8, #0x3 + str r8, [r4, #MMDC0_MPZQHWCTRL] + + /* enable DQS gating. */ + ldr r10, =MMDC0_MPDGCTRL0 + ldr r8, [r4, r10] + bic r8, r8, #(1 << 29) + str r8, [r4, r10] + + /* Now perform a force measure */ + ldr r8, =0x00000800 + str r8, [r4, #MMDC0_MPMUR0] + /* Wait for FRC_MSR to clear. */ +1: + ldr r8, [r4, #MMDC0_MPMUR0] + and r8, r8, #0x800 + cmp r8, #0x0 + bne 1b + + /* disable dqs pull down in the IOMUX. */ + ldr r8, [r3] + add r3, r3, #8 +update_iomux1: + ldr r10, [r3, #0x0] + ldr r11, [r3, #0x4] + str r11, [r6, r10] + add r3, r3, #8 + sub r8, r8, #1 + cmp r8, #0 + bgt update_iomux1 + + /* config MMDC timings to 400MHz. */ + ldr r1, [r0, #BUSFREQ_INFO_DDR_SETTINGS_OFFSET] + ldr r7, [r1] + add r1, r1, #8 + ldr r10, [r1, #0x0] + ldr r11, [r1, #0x4] + str r11, [r4, r10] + add r1, r1, #8 + + ldr r10, [r1, #0x0] + ldr r11, [r1, #0x4] + str r11, [r4, r10] + add r1, r1, #8 + + /* configure ddr devices to dll on, odt. */ + ldr r8, =0x00028031 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x00028039 + str r8, [r4, #MMDC0_MDSCR] + + /* delay for while. */ + ldr r8, =4 + do_delay + + /* reset dll. */ + ldr r8, =0x09208030 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x09208038 + str r8, [r4, #MMDC0_MDSCR] + + /* delay for while. */ + ldr r8, =100 + do_delay + + ldr r10, [r1, #0x0] + ldr r11, [r1, #0x4] + str r11, [r4, r10] + add r1, r1, #8 + + ldr r10, [r1, #0x0] + ldr r11, [r1, #0x4] + str r11, [r4, r10] + add r1, r1, #8 + + ldr r8, =0x00428031 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x00428039 + str r8, [r4, #MMDC0_MDSCR] + + ldr r10, [r1, #0x0] + ldr r11, [r1, #0x4] + str r11, [r4, r10] + add r1, r1, #8 + + ldr r10, [r1, #0x0] + ldr r11, [r1, #0x4] + str r11, [r4, r10] + add r1, r1, #8 + + /* issue a zq command. */ + ldr r8, =0x04008040 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x04008048 + str r8, [r4, #MMDC0_MDSCR] + + /* MMDC ODT enable. */ + ldr r10, [r1, #0x0] + ldr r11, [r1, #0x4] + str r11, [r4, r10] + add r1, r1, #8 + + /* delay for while. */ + ldr r8, =40 + do_delay + + /* enable MMDC power down timer. */ + ldr r8, [r4, #MMDC0_MDPDC] + orr r8, r8, #(0x55 << 8) + str r8, [r4, #MMDC0_MDPDC] + + b update_calibration + +update_calibration_only: + ldr r8, [r1] + sub r8, r8, #7 + add r1, r1, #64 + b update_calib + +update_calibration: + /* write the new calibration values. */ + mov r8, r7 + sub r8, r8, #7 + +update_calib: + ldr r10, [r1, #0x0] + ldr r11, [r1, #0x4] + str r11, [r4, r10] + add r1, r1, #8 + sub r8, r8, #1 + cmp r8, #0 + bgt update_calib + + /* perform a force measurement. */ + ldr r8, =0x800 + str r8, [r4, #MMDC0_MPMUR0] + /* Wait for FRC_MSR to clear. */ +1: + ldr r8, [r4, #MMDC0_MPMUR0] + and r8, r8, #0x800 + cmp r8, #0x0 + bne 1b + + /* clear SBS - unblock DDR accesses. */ + ldr r8, [r4, #MMDC0_MADPCR0] + bic r8, r8, #(1 << 8) + str r8, [r4, #MMDC0_MADPCR0] + + mov r8, #0x0 + str r8, [r4, #MMDC0_MDSCR] +poll_conreq_clear_2: + ldr r8, [r4, #MMDC0_MDSCR] + and r8, r8, #(0x4 << 12) + cmp r8, #(0x4 << 12) + beq poll_conreq_clear_2 + +done: + + /* MMDC0_MAPSR adopt power down enable. */ + ldr r8, [r4, #MMDC0_MAPSR] + bic r8, r8, #0x01 + str r8, [r4, #MMDC0_MAPSR] + + is_ca7 + beq skip_enable_l2 + +#ifdef CONFIG_CACHE_L2X0 + /* Unlock L2. */ + ldr r8, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + ldr r9, [r8, #PL310_AUX_CTRL] + tst r9, #PL310_AUX_16WAY_BIT + mov r10, #PL310_LOCKDOWN_NBREGS + mov r9, #0x00 /* 8 ways mask */ + orrne r9, #0x0000 /* 16 ways mask */ + add r11, r8, #PL310_DCACHE_LOCKDOWN_BASE +1: /* lock Dcache and Icache */ + str r9, [r11], #PL310_LOCKDOWN_SZREG + str r9, [r11], #PL310_LOCKDOWN_SZREG + subs r10, r10, #1 + bne 1b + +#endif + +skip_enable_l2: + /* Enable L1 data cache. */ + mrc p15, 0, r7, c1, c0, 0 + orr r7, r7, #0x4 + mcr p15, 0, r7, c1, c0, 0 + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r7, c1, c0, 0 + orr r7, r7, #0x800 + mcr p15, 0, r7, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r7, =0x0 + mcr p15, 0, r7, c7, c1, 6 + + /* restore registers */ + ldmfd sp!, {r4 - r11} + mov pc, lr + + /* + * Add ltorg here to ensure that all + * literals are stored here and are + * within the text space. + */ + .ltorg +imx6_up_ddr3_freq_change_end: +ENDPROC(imx6_up_ddr3_freq_change) diff --git a/arch/arm/mach-imx/ddr3_freq_imx7d.S b/arch/arm/mach-imx/ddr3_freq_imx7d.S new file mode 100644 index 00000000000000..9342e0d83f5e88 --- /dev/null +++ b/arch/arm/mach-imx/ddr3_freq_imx7d.S @@ -0,0 +1,586 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "hardware.h" + +#define DDRC_MSTR 0x0 +#define DDRC_STAT 0x4 +#define DDRC_MRCTRL0 0x10 +#define DDRC_MRCTRL1 0x14 +#define DDRC_MRSTAT 0x18 +#define DDRC_PWRCTL 0x30 +#define DDRC_RFSHCTL3 0x60 +#define DDRC_RFSHTMG 0x64 +#define DDRC_DBG1 0x304 +#define DDRC_SWCTL 0x320 +#define DDRC_SWSTAT 0x324 +#define DDRC_PSTAT 0x3fc +#define DDRC_PCTRL_0 0x490 +#define DDRC_ZQCTL0 0x180 +#define DDRC_DFIMISC 0x1b0 +#define DDRC_DBGCAM 0x308 +#define DDRPHY_LP_CON0 0x18 +#define IOMUXC_GPR8 0x20 +#define DDRPHY_MDLL_CON0 0xb0 +#define DDRPHY_MDLL_CON1 0xb4 +#define DDRPHY_OFFSETD_CON0 0x50 +#define DDRPHY_OFFSETR_CON0 0x20 +#define DDRPHY_OFFSETR_CON1 0x24 +#define DDRPHY_OFFSETR_CON2 0x28 +#define DDRPHY_OFFSETW_CON0 0x30 +#define DDRPHY_OFFSETW_CON1 0x34 +#define DDRPHY_OFFSETW_CON2 0x38 +#define DDRPHY_CA_WLDSKEW_CON0 0x6c +#define DDRPHY_CA_DSKEW_CON0 0x7c +#define DDRPHY_CA_DSKEW_CON1 0x80 +#define DDRPHY_CA_DSKEW_CON2 0x84 + +#define ANADIG_DIGPROG 0x800 + + .align 3 + + .macro switch_to_below_100m + + ldr r7, =0x2 + str r7, [r4, #DDRC_DBG1] + + ldr r6, =0x36000000 +1: + ldr r7, [r4, #DDRC_DBGCAM] + and r7, r7, r6 + cmp r7, r6 + bne 1b + + ldr r6, =0x1 +2: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 2b + + ldr r7, =0x10f0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x0 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800010f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r6, =0x1 +3: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 3b + + ldr r7, =0x20f0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x8 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800020f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r6, =0x1 +4: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 4b + + ldr r7, =0x10f0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x1 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800010f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r7, =0x20 + str r7, [r4, #DDRC_PWRCTL] + + ldr r6, =0x23 +5: + ldr r7, [r4, #DDRC_STAT] + and r7, r7, r6 + cmp r7, r6 + bne 5b + + ldr r7, =0x0 + str r7, [r4, #DDRC_SWCTL] + + ldr r7, =0x03048001 + str r7, [r4, #DDRC_MSTR] + + ldr r7, =0x1 + str r7, [r4, #DDRC_SWCTL] + + ldr r6, =0x1 +6: + ldr r7, [r4, #DDRC_SWSTAT] + and r7, r7, r6 + cmp r7, r6 + bne 6b + + ldr r7, =0x10010100 + str r7, [r5, #0x4] + + ldr r6, =24000000 + cmp r0, r6 + beq 25f + + ldr r7, =0x000B000D + str r7,[r4, #DDRC_RFSHTMG] + b 7f + +25: + ldr r7, =0x00030004 + str r7,[r4, #DDRC_RFSHTMG] + + /* dram alt sel set to OSC */ + ldr r7, =0x10000000 + ldr r8, =0xa080 + str r7, [r2, r8] + /* dram root set to from dram alt, div by 1 */ + ldr r7, =0x11000000 + ldr r8, =0x9880 + str r7, [r2, r8] + b 8f +7: + /* dram alt sel set to pfd0_392m */ + ldr r7, =0x15000000 + ldr r8, =0xa080 + str r7, [r2, r8] + /* dram root set to from dram alt, div by 4 */ + ldr r7, =0x11000003 + ldr r8, =0x9880 + str r7, [r2, r8] +8: + ldr r7, =0x202ffd0 + str r7, [r5, #DDRPHY_MDLL_CON0] + + ldr r7, =0x1000007f + str r7, [r5, #DDRPHY_OFFSETD_CON0] + + ldr r7, =0x7f7f7f7f + str r7, [r5, #DDRPHY_OFFSETR_CON0] + str r7, [r5, #DDRPHY_OFFSETR_CON1] + ldr r7, =0x7f + str r7, [r5, #DDRPHY_OFFSETR_CON2] + + ldr r7, =0x7f7f7f7f + str r7, [r5, #DDRPHY_OFFSETW_CON0] + str r7, [r5, #DDRPHY_OFFSETW_CON1] + ldr r7, =0x7f + str r7, [r5, #DDRPHY_OFFSETW_CON2] + + ldr r7, [r9, #ANADIG_DIGPROG] + and r7, r7, #0x11 + cmp r7, #0x11 + bne 20f + + ldr r7, =0x0 + str r7, [r5, #DDRPHY_CA_WLDSKEW_CON0] + ldr r7, =0x60606060 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + ldr r7, =0x00006060 + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] + b 21f +20: + ldr r7, =0x0 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] +21: + ldr r7, =0x1100007f + str r7, [r5, #DDRPHY_OFFSETD_CON0] + ldr r7, =0x1000007f + str r7, [r5, #DDRPHY_OFFSETD_CON0] + + ldr r7, =0x0 + str r7, [r4, #DDRC_PWRCTL] + + ldr r6, =0x1 +9: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 9b + + ldr r7, =0xf0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x820 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800000f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r6, =0x1 +10: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 10b + + ldr r7, =0x800020 + str r7, [r4, #DDRC_ZQCTL0] + + ldr r7, =0x0 + str r7, [r4, #DDRC_DBG1] + + /* enable auto self-refresh */ + ldr r7, [r4, #DDRC_PWRCTL] + orr r7, r7, #(1 << 0) + str r7, [r4, #DDRC_PWRCTL] + + .endm + + .macro switch_to_533m + + ldr r7, =0x2 + str r7, [r4, #DDRC_DBG1] + + ldr r7, =0x78 + str r7, [r3, #IOMUXC_GPR8] + orr r7, r7, #0x100 + str r7, [r3, #IOMUXC_GPR8] + + ldr r6, =0x30000000 +11: + ldr r7, [r4, #DDRC_DBGCAM] + and r7, r7, r6 + cmp r7, r6 + bne 11b + + ldr r6, =0x1 +12: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 12b + + ldr r7, =0x10f0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x1 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800010f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r7, =0x20 + str r7, [r4, #DDRC_PWRCTL] + + ldr r6, =0x23 +13: + ldr r7, [r4, #DDRC_STAT] + and r7, r7, r6 + cmp r7, r6 + bne 13b + + ldr r7, =0x03040001 + str r7, [r4, #DDRC_MSTR] + + ldr r7, =0x40800020 + str r7, [r4, #DDRC_ZQCTL0] + + + ldr r7, =0x10210100 + str r7, [r5, #0x4] + + ldr r7, =0x00040046 + str r7, [r4, #DDRC_RFSHTMG] + + /* dram root set to from dram main, div by 2 */ + ldr r7, =0x10000001 + ldr r8, =0x9880 + str r7, [r2, r8] + + ldr r7, =0x1010007e + str r7, [r5, #DDRPHY_MDLL_CON0] + + ldr r7, =0x10000008 + str r7, [r5, #DDRPHY_OFFSETD_CON0] + + ldr r7, =0x08080808 + str r7, [r5, #DDRPHY_OFFSETR_CON0] + str r7, [r5, #DDRPHY_OFFSETR_CON1] + ldr r7, =0x8 + str r7, [r5, #DDRPHY_OFFSETR_CON2] + + ldr r7, =0x08080808 + str r7, [r5, #DDRPHY_OFFSETW_CON0] + str r7, [r5, #DDRPHY_OFFSETW_CON1] + ldr r7, =0x8 + str r7, [r5, #DDRPHY_OFFSETW_CON2] + + ldr r7, [r9, #ANADIG_DIGPROG] + and r7, r7, #0x11 + cmp r7, #0x11 + bne 22f + + ldr r7, =0x40404040 + str r7, [r5, #DDRPHY_CA_WLDSKEW_CON0] + ldr r7, =0x18181818 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + ldr r7, =0x40401818 + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] + b 23f +22: + ldr r7, =0x0 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] +23: + ldr r7, =0x11000008 + str r7, [r5, #DDRPHY_OFFSETD_CON0] + ldr r7, =0x10000008 + str r7, [r5, #DDRPHY_OFFSETD_CON0] + + ldr r6, =0x4 +14: + ldr r7, [r5, #DDRPHY_MDLL_CON1] + and r7, r7, r6 + cmp r7, r6 + bne 14b + + ldr r7, =0x1 + str r7, [r4, #DDRC_RFSHCTL3] + ldr r7, =0x3 + str r7, [r4, #DDRC_RFSHCTL3] + + ldr r7, =0x0 + str r7, [r4, #DDRC_PWRCTL] + + ldr r6, =0x1 +15: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 15b + + ldr r7, =0x10f0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x0 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800010f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r6, =0x1 +16: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 16b + + ldr r7, =0xf0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x930 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800000f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r7, =0x0 + str r7, [r4, #DDRC_RFSHCTL3] + ldr r7, =0x2 + str r7, [r4, #DDRC_RFSHCTL3] + + ldr r6, =0x1 +17: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 17b + + ldr r7, =0xf0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x930 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800000f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r6, =0x1 +18: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 18b + + ldr r7, =0x20f0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x408 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800020f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r6, =0x1 +19: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 19b + + ldr r7, =0x10f0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x4 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800010f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r7, =0x0 + str r7, [r4, #DDRC_DBG1] + + /* enable auto self-refresh */ + ldr r7, [r4, #DDRC_PWRCTL] + orr r7, r7, #(1 << 0) + str r7, [r4, #DDRC_PWRCTL] + + .endm + +ENTRY(imx7d_ddr3_freq_change) + push {r2 - r9} + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + dsb + isb + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + ldr r2, =IMX_IO_P2V(MX7D_CCM_BASE_ADDR) + ldr r3, =IMX_IO_P2V(MX7D_IOMUXC_GPR_BASE_ADDR) + ldr r4, =IMX_IO_P2V(MX7D_DDRC_BASE_ADDR) + ldr r5, =IMX_IO_P2V(MX7D_DDRC_PHY_BASE_ADDR) + ldr r9, =IMX_IO_P2V(MX7D_ANATOP_BASE_ADDR) + + ldr r6, =100000000 + cmp r0, r6 + bgt set_to_533m + +set_to_below_100m: + switch_to_below_100m + b done + +set_to_533m: + switch_to_533m + b done + +done: + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + dsb + isb + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + /* Restore registers */ + pop {r2 - r9} + mov pc, lr + .ltorg +ENDPROC(imx7d_ddr3_freq_change) diff --git a/arch/arm/mach-imx/ddrc.c b/arch/arm/mach-imx/ddrc.c new file mode 100644 index 00000000000000..9c7f627d465e70 --- /dev/null +++ b/arch/arm/mach-imx/ddrc.c @@ -0,0 +1,86 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include + +#include "hardware.h" + +#define DDRC_MSTR 0x0 +#define BM_DDRC_MSTR_DDR3 0x1 +#define BM_DDRC_MSTR_LPDDR2 0x4 +#define BM_DDRC_MSTR_LPDDR3 0x8 + +static int ddr_type; + +static int imx_ddrc_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + void __iomem *ddrc_base, *reg; + u32 val; + + ddrc_base = of_iomap(np, 0); + WARN_ON(!ddrc_base); + + reg = ddrc_base + DDRC_MSTR; + /* Get ddr type */ + val = readl_relaxed(reg); + val &= (BM_DDRC_MSTR_DDR3 | BM_DDRC_MSTR_LPDDR2 + | BM_DDRC_MSTR_LPDDR3); + + switch (val) { + case BM_DDRC_MSTR_DDR3: + pr_info("DDR type is DDR3!\n"); + ddr_type = IMX_DDR_TYPE_DDR3; + break; + case BM_DDRC_MSTR_LPDDR2: + pr_info("DDR type is LPDDR2!\n"); + ddr_type = IMX_DDR_TYPE_LPDDR2; + break; + case BM_DDRC_MSTR_LPDDR3: + pr_info("DDR type is LPDDR3!\n"); + ddr_type = IMX_DDR_TYPE_LPDDR3; + break; + default: + break; + } + + return 0; +} + +int imx_ddrc_get_ddr_type(void) +{ + return ddr_type; +} + +static struct of_device_id imx_ddrc_dt_ids[] = { + { .compatible = "fsl,imx7-ddrc", }, + { /* sentinel */ } +}; + +static struct platform_driver imx_ddrc_driver = { + .driver = { + .name = "imx-ddrc", + .owner = THIS_MODULE, + .of_match_table = imx_ddrc_dt_ids, + }, + .probe = imx_ddrc_probe, +}; + +static int __init imx_ddrc_init(void) +{ + return platform_driver_register(&imx_ddrc_driver); +} +postcore_initcall(imx_ddrc_init); diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c index b5b557fe2c4995..838d93381c0776 100644 --- a/arch/arm/mach-imx/gpc.c +++ b/arch/arm/mach-imx/gpc.c @@ -14,22 +14,153 @@ #include "common.h" #include "hardware.h" -#define GPC_CNTR 0x0 +#define GPC_CNTR 0x000 +#define GPC_CNTR_L2_PGE 22 + #define GPC_IMR1 0x008 +#define GPC_PGC_MF_PDN 0x220 #define GPC_PGC_CPU_PDN 0x2a0 #define GPC_PGC_CPU_PUPSCR 0x2a4 #define GPC_PGC_CPU_PDNSCR 0x2a8 #define GPC_PGC_SW2ISO_SHIFT 0x8 #define GPC_PGC_SW_SHIFT 0x0 - -#define GPC_CNTR_L2_PGE_SHIFT 22 +#define GPC_M4_LPSR 0x2c +#define GPC_M4_LPSR_M4_SLEEPING_SHIFT 4 +#define GPC_M4_LPSR_M4_SLEEPING_MASK 0x1 +#define GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_MASK 0x1 +#define GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_SHIFT 0 +#define GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_MASK 0x1 +#define GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_SHIFT 1 + +#define GPC_PGC_CPU_SW_SHIFT 0 +#define GPC_PGC_CPU_SW_MASK 0x3f +#define GPC_PGC_CPU_SW2ISO_SHIFT 8 +#define GPC_PGC_CPU_SW2ISO_MASK 0x3f #define IMR_NUM 4 #define GPC_MAX_IRQS (IMR_NUM * 32) +/* for irq #74 and #75 */ +#define GPC_USB_VBUS_WAKEUP_IRQ_MASK 0xc00 + +/* for irq #150 and #151 */ +#define GPC_ENET_WAKEUP_IRQ_MASK 0xC00000 + static void __iomem *gpc_base; static u32 gpc_wake_irqs[IMR_NUM]; static u32 gpc_saved_imrs[IMR_NUM]; +static u32 gpc_mf_irqs[IMR_NUM]; +static u32 gpc_mf_request_on[IMR_NUM]; +static DEFINE_SPINLOCK(gpc_lock); + +void imx_gpc_add_m4_wake_up_irq(u32 hwirq, bool enable) +{ + unsigned int idx = hwirq / 32; + unsigned long flags; + u32 mask; + + /* Sanity check for SPI irq */ + if (hwirq < 32) + return; + + mask = 1 << hwirq % 32; + spin_lock_irqsave(&gpc_lock, flags); + gpc_wake_irqs[idx] = enable ? gpc_wake_irqs[idx] | mask : + gpc_wake_irqs[idx] & ~mask; + spin_unlock_irqrestore(&gpc_lock, flags); +} + +void imx_gpc_hold_m4_in_sleep(void) +{ + int val; + unsigned long timeout = jiffies + msecs_to_jiffies(500); + + /* wait M4 in wfi before asserting hold request */ + while (!imx_gpc_is_m4_sleeping()) + if (time_after(jiffies, timeout)) + pr_err("M4 is NOT in expected sleep!\n"); + + val = readl_relaxed(gpc_base + GPC_M4_LPSR); + val &= ~(GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_MASK << + GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_SHIFT); + writel_relaxed(val, gpc_base + GPC_M4_LPSR); + + timeout = jiffies + msecs_to_jiffies(500); + while (readl_relaxed(gpc_base + GPC_M4_LPSR) + & (GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_MASK << + GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_SHIFT)) + if (time_after(jiffies, timeout)) + pr_err("Wait M4 hold ack timeout!\n"); +} + +void imx_gpc_release_m4_in_sleep(void) +{ + int val; + + val = readl_relaxed(gpc_base + GPC_M4_LPSR); + val |= GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_MASK << + GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_SHIFT; + writel_relaxed(val, gpc_base + GPC_M4_LPSR); +} + +unsigned int imx_gpc_is_m4_sleeping(void) +{ + if (readl_relaxed(gpc_base + GPC_M4_LPSR) & + (GPC_M4_LPSR_M4_SLEEPING_MASK << + GPC_M4_LPSR_M4_SLEEPING_SHIFT)) + return 1; + + return 0; +} + +bool imx_gpc_usb_wakeup_enabled(void) +{ + if (!(cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || + cpu_is_imx6ulz() || cpu_is_imx6sll())) + return false; + + /* + * for SoC later than i.MX6SX, USB vbus wakeup + * only needs weak 2P5 on, stop_mode_config is + * NOT needed, so we check if is USB vbus wakeup + * is enabled(assume irq #74 and #75) to decide + * if to keep weak 2P5 on. + */ + if (gpc_wake_irqs[1] & GPC_USB_VBUS_WAKEUP_IRQ_MASK) + return true; + + return false; +} + +bool imx_gpc_enet_wakeup_enabled(void) +{ + if (!cpu_is_imx6q()) + return false; + + if (gpc_wake_irqs[3] & GPC_ENET_WAKEUP_IRQ_MASK) + return true; + + return false; +} + +unsigned int imx_gpc_is_mf_mix_off(void) +{ + return readl_relaxed(gpc_base + GPC_PGC_MF_PDN); +} + +static void imx_gpc_mf_mix_off(void) +{ + int i; + + for (i = 0; i < IMR_NUM; i++) + if (((gpc_wake_irqs[i] | gpc_mf_request_on[i]) & + gpc_mf_irqs[i]) != 0) + return; + + pr_info("Turn off M/F mix!\n"); + /* turn off mega/fast mix */ + writel_relaxed(0x1, gpc_base + GPC_PGC_MF_PDN); +} void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw) { @@ -53,9 +184,9 @@ void imx_gpc_set_l2_mem_power_in_lpm(bool power_off) u32 val; val = readl_relaxed(gpc_base + GPC_CNTR); - val &= ~(1 << GPC_CNTR_L2_PGE_SHIFT); + val &= ~(1 << GPC_CNTR_L2_PGE); if (power_off) - val |= 1 << GPC_CNTR_L2_PGE_SHIFT; + val |= 1 << GPC_CNTR_L2_PGE; writel_relaxed(val, gpc_base + GPC_CNTR); } @@ -64,6 +195,11 @@ void imx_gpc_pre_suspend(bool arm_power_off) void __iomem *reg_imr1 = gpc_base + GPC_IMR1; int i; + /* power down the mega-fast power domain */ + if ((cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || + cpu_is_imx6ulz() || cpu_is_imx6sll()) && arm_power_off) + imx_gpc_mf_mix_off(); + /* Tell GPC to power off ARM core when suspend */ if (arm_power_off) imx_gpc_set_arm_power_in_lpm(arm_power_off); @@ -81,6 +217,10 @@ void imx_gpc_post_resume(void) /* Keep ARM core powered on for other low-power modes */ imx_gpc_set_arm_power_in_lpm(false); + /* Keep M/F mix powered on for other low-power modes */ + if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || + cpu_is_imx6ulz() || cpu_is_imx6sll()) + writel_relaxed(0x0, gpc_base + GPC_PGC_MF_PDN); for (i = 0; i < IMR_NUM; i++) writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); @@ -89,11 +229,14 @@ void imx_gpc_post_resume(void) static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on) { unsigned int idx = d->hwirq / 32; + unsigned long flags; u32 mask; mask = 1 << d->hwirq % 32; + spin_lock_irqsave(&gpc_lock, flags); gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask : gpc_wake_irqs[idx] & ~mask; + spin_unlock_irqrestore(&gpc_lock, flags); /* * Do *not* call into the parent, as the GIC doesn't have any @@ -225,11 +368,78 @@ static const struct irq_domain_ops imx_gpc_domain_ops = { .free = irq_domain_free_irqs_common, }; +int imx_gpc_mf_power_on(unsigned int irq, unsigned int on) +{ + struct irq_desc *d = irq_to_desc(irq); + unsigned int idx = d->irq_data.hwirq / 32; + unsigned long flags; + u32 mask; + + mask = 1 << (d->irq_data.hwirq % 32); + spin_lock_irqsave(&gpc_lock, flags); + gpc_mf_request_on[idx] = on ? gpc_mf_request_on[idx] | mask : + gpc_mf_request_on[idx] & ~mask; + spin_unlock_irqrestore(&gpc_lock, flags); + + return 0; +} + +int imx_gpc_mf_request_on(unsigned int irq, unsigned int on) +{ + if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || + cpu_is_imx6ulz() || cpu_is_imx6sll()) + return imx_gpc_mf_power_on(irq, on); + else if (cpu_is_imx7d()) + return imx_gpcv2_mf_power_on(irq, on); + else + return 0; +} +EXPORT_SYMBOL_GPL(imx_gpc_mf_request_on); + +void imx_gpc_switch_pupscr_clk(bool flag) +{ + static u32 pupscr_sw2iso, pupscr_sw; + u32 ratio, pupscr = readl_relaxed(gpc_base + GPC_PGC_CPU_PUPSCR); + + if (flag) { + /* save the init clock setting IPG/2048 for IPG@66Mhz */ + pupscr_sw2iso = (pupscr >> GPC_PGC_CPU_SW2ISO_SHIFT) & + GPC_PGC_CPU_SW2ISO_MASK; + pupscr_sw = (pupscr >> GPC_PGC_CPU_SW_SHIFT) & + GPC_PGC_CPU_SW_MASK; + /* + * i.MX6UL TO1.0 ARM power up uses IPG/2048 as clock source, + * from TO1.1, PGC_CPU_PUPSCR bit [5] is re-defined to switch + * clock to IPG/32, enable this bit to speed up the ARM power + * up process in low power idle case(IPG@1.5Mhz). So the sw and + * sw2iso need to be adjusted as below: + * sw_new(sw2iso_new) = (2048 * 1.5 / 66 * 32) * sw(sw2iso) + */ + ratio = 3072 / (66 * 32); + pupscr &= ~(GPC_PGC_CPU_SW_MASK << GPC_PGC_CPU_SW_SHIFT | + GPC_PGC_CPU_SW2ISO_MASK << GPC_PGC_CPU_SW2ISO_SHIFT); + pupscr |= (ratio * pupscr_sw + 1) << GPC_PGC_CPU_SW_SHIFT | + 1 << 5 | (ratio * pupscr_sw2iso + 1) << + GPC_PGC_CPU_SW2ISO_SHIFT; + writel_relaxed(pupscr, gpc_base + GPC_PGC_CPU_PUPSCR); + } else { + /* restore back after exit from low power idle */ + pupscr &= ~(GPC_PGC_CPU_SW_MASK << GPC_PGC_CPU_SW_SHIFT | + GPC_PGC_CPU_SW2ISO_MASK << GPC_PGC_CPU_SW2ISO_SHIFT); + pupscr |= pupscr_sw << GPC_PGC_CPU_SW_SHIFT | + pupscr_sw2iso << GPC_PGC_CPU_SW2ISO_SHIFT; + writel_relaxed(pupscr, gpc_base + GPC_PGC_CPU_PUPSCR); + } +} + static int __init imx_gpc_init(struct device_node *node, struct device_node *parent) { struct irq_domain *parent_domain, *domain; int i; + u32 val; + u32 cpu_pupscr_sw2iso, cpu_pupscr_sw; + u32 cpu_pdnscr_iso2sw, cpu_pdnscr_iso; if (!parent) { pr_err("%pOF: no parent, giving up\n", node); @@ -258,12 +468,70 @@ static int __init imx_gpc_init(struct device_node *node, for (i = 0; i < IMR_NUM; i++) writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4); + /* Read supported wakeup source in M/F domain */ + if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || + cpu_is_imx6ulz() || cpu_is_imx6sll()) { + of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 0, + &gpc_mf_irqs[0]); + of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 1, + &gpc_mf_irqs[1]); + of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 2, + &gpc_mf_irqs[2]); + of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 3, + &gpc_mf_irqs[3]); + if (!(gpc_mf_irqs[0] | gpc_mf_irqs[1] | + gpc_mf_irqs[2] | gpc_mf_irqs[3])) + pr_info("No wakeup source in Mega/Fast domain found!\n"); + } + + /* clear the L2_PGE bit on i.MX6SLL */ + if (cpu_is_imx6sll()) { + val = readl_relaxed(gpc_base + GPC_CNTR); + val &= ~(1 << GPC_CNTR_L2_PGE); + writel_relaxed(val, gpc_base + GPC_CNTR); + } + /* * Clear the OF_POPULATED flag set in of_irq_init so that * later the GPC power domain driver will not be skipped. */ of_node_clear_flag(node, OF_POPULATED); + /* + * If there are CPU isolation timing settings in dts, + * update them according to dts, otherwise, keep them + * with default value in registers. + */ + cpu_pupscr_sw2iso = cpu_pupscr_sw = + cpu_pdnscr_iso2sw = cpu_pdnscr_iso = 0; + + /* Read CPU isolation setting for GPC */ + of_property_read_u32(node, "fsl,cpu_pupscr_sw2iso", &cpu_pupscr_sw2iso); + of_property_read_u32(node, "fsl,cpu_pupscr_sw", &cpu_pupscr_sw); + of_property_read_u32(node, "fsl,cpu_pdnscr_iso2sw", &cpu_pdnscr_iso2sw); + of_property_read_u32(node, "fsl,cpu_pdnscr_iso", &cpu_pdnscr_iso); + + /* Return if no property found in dtb */ + if ((cpu_pupscr_sw2iso | cpu_pupscr_sw + | cpu_pdnscr_iso2sw | cpu_pdnscr_iso) == 0) + return 0; + + /* Update CPU PUPSCR timing if it is defined in dts */ + val = readl_relaxed(gpc_base + GPC_PGC_CPU_PUPSCR); + val &= ~(GPC_PGC_CPU_SW2ISO_MASK << GPC_PGC_CPU_SW2ISO_SHIFT); + val &= ~(GPC_PGC_CPU_SW_MASK << GPC_PGC_CPU_SW_SHIFT); + val |= cpu_pupscr_sw2iso << GPC_PGC_CPU_SW2ISO_SHIFT; + val |= cpu_pupscr_sw << GPC_PGC_CPU_SW_SHIFT; + writel_relaxed(val, gpc_base + GPC_PGC_CPU_PUPSCR); + + /* Update CPU PDNSCR timing if it is defined in dts */ + val = readl_relaxed(gpc_base + GPC_PGC_CPU_PDNSCR); + val &= ~(GPC_PGC_CPU_SW2ISO_MASK << GPC_PGC_CPU_SW2ISO_SHIFT); + val &= ~(GPC_PGC_CPU_SW_MASK << GPC_PGC_CPU_SW_SHIFT); + val |= cpu_pdnscr_iso2sw << GPC_PGC_CPU_SW2ISO_SHIFT; + val |= cpu_pdnscr_iso << GPC_PGC_CPU_SW_SHIFT; + writel_relaxed(val, gpc_base + GPC_PGC_CPU_PDNSCR); + return 0; } IRQCHIP_DECLARE(imx_gpc, "fsl,imx6q-gpc", imx_gpc_init); diff --git a/arch/arm/mach-imx/gpcv2.c b/arch/arm/mach-imx/gpcv2.c new file mode 100644 index 00000000000000..3e8ab91cb97f58 --- /dev/null +++ b/arch/arm/mach-imx/gpcv2.c @@ -0,0 +1,851 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" +#include "hardware.h" + +#define IMR_NUM 4 +#define GPC_MAX_IRQS (IMR_NUM * 32) +#define GPC_LPCR_A7_BSC 0x0 +#define GPC_LPCR_A7_AD 0x4 +#define GPC_LPCR_M4 0x8 +#define GPC_SLPCR 0x14 +#define GPC_MLPCR 0x20 +#define GPC_PGC_ACK_SEL_A7 0x24 +#define GPC_MISC 0x2c +#define GPC_IMR1_CORE0 0x30 +#define GPC_IMR1_CORE1 0x40 +#define GPC_IMR1_M4 0x50 +#define GPC_SLOT0_CFG 0xb0 +#define GPC_PGC_CPU_MAPPING 0xec +#define GPC_CPU_PGC_SW_PUP_REQ 0xf0 +#define GPC_PU_PGC_SW_PUP_REQ 0xf8 +#define GPC_CPU_PGC_SW_PDN_REQ 0xfc +#define GPC_PU_PGC_SW_PDN_REQ 0x104 +#define GPC_GTOR 0x124 +#define GPC_PGC_C0 0x800 +#define GPC_PGC_C0_PUPSCR 0x804 +#define GPC_PGC_SCU_TIMING 0x890 +#define GPC_PGC_C1 0x840 +#define GPC_PGC_C1_PUPSCR 0x844 +#define GPC_PGC_SCU 0x880 +#define GPC_PGC_FM 0xa00 + +#define BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP 0x70000000 +#define BM_LPCR_A7_BSC_CPU_CLK_ON_LPM 0x4000 +#define BM_LPCR_A7_BSC_LPM1 0xc +#define BM_LPCR_A7_BSC_LPM0 0x3 +#define BP_LPCR_A7_BSC_LPM1 2 +#define BP_LPCR_A7_BSC_LPM0 0 +#define BM_LPCR_M4_MASK_DSM_TRIGGER 0x80000000 +#define BM_SLPCR_EN_DSM 0x80000000 +#define BM_SLPCR_RBC_EN 0x40000000 +#define BM_SLPCR_REG_BYPASS_COUNT 0x3f000000 +#define BM_SLPCR_VSTBY 0x4 +#define BM_SLPCR_SBYOS 0x2 +#define BM_SLPCR_BYPASS_PMIC_READY 0x1 +#define BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE 0x10000 +#define BM_LPCR_A7_AD_L2PGE 0x10000 +#define BM_LPCR_A7_AD_EN_C1_PUP 0x800 +#define BM_LPCR_A7_AD_EN_C1_IRQ_PUP 0x400 +#define BM_LPCR_A7_AD_EN_C0_PUP 0x200 +#define BM_LPCR_A7_AD_EN_C0_IRQ_PUP 0x100 +#define BM_LPCR_A7_AD_EN_PLAT_PDN 0x10 +#define BM_LPCR_A7_AD_EN_C1_PDN 0x8 +#define BM_LPCR_A7_AD_EN_C1_WFI_PDN 0x4 +#define BM_LPCR_A7_AD_EN_C0_PDN 0x2 +#define BM_LPCR_A7_AD_EN_C0_WFI_PDN 0x1 + +#define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2 +#define BM_GPC_PGC_PCG 0x1 +#define BM_GPC_PGC_CORE_PUPSCR 0x7fff80 + +#define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK 0x80000000 +#define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK 0x8000 +#define BM_GPC_MLPCR_MEMLP_CTL_DIS 0x1 + +#define BP_LPCR_A7_BSC_IRQ_SRC 28 + +#define MAX_SLOT_NUMBER 10 +#define A7_LPM_WAIT 0x5 +#define A7_LPM_STOP 0xa + +enum imx_gpc_slot { + CORE0_A7, + CORE1_A7, + SCU_A7, + FAST_MEGA_MIX, + MIPI_PHY, + PCIE_PHY, + USB_OTG1_PHY, + USB_OTG2_PHY, + USB_HSIC_PHY, + CORE0_M4, +}; + +static void __iomem *gpc_base; +static u32 gpcv2_wake_irqs[IMR_NUM]; +static u32 gpcv2_saved_imrs[IMR_NUM]; +static u32 gpcv2_saved_imrs_m4[IMR_NUM]; +static u32 gpcv2_mf_irqs[IMR_NUM]; +static u32 gpcv2_mf_request_on[IMR_NUM]; +static DEFINE_SPINLOCK(gpcv2_lock); + +void imx_gpcv2_add_m4_wake_up_irq(u32 hwirq, bool enable) +{ + unsigned int idx = hwirq / 32; + unsigned long flags; + u32 mask; + + /* Sanity check for SPI irq */ + if (hwirq < 32) + return; + + mask = 1 << hwirq % 32; + spin_lock_irqsave(&gpcv2_lock, flags); + gpcv2_wake_irqs[idx] = enable ? gpcv2_wake_irqs[idx] | mask : + gpcv2_wake_irqs[idx] & ~mask; + spin_unlock_irqrestore(&gpcv2_lock, flags); +} + +static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on) +{ + unsigned int idx = d->hwirq / 32; + unsigned long flags; + u32 mask; + + BUG_ON(idx >= IMR_NUM); + + mask = 1 << d->hwirq % 32; + spin_lock_irqsave(&gpcv2_lock, flags); + gpcv2_wake_irqs[idx] = on ? gpcv2_wake_irqs[idx] | mask : + gpcv2_wake_irqs[idx] & ~mask; + spin_unlock_irqrestore(&gpcv2_lock, flags); + + return 0; +} + +void imx_gpcv2_mask_all(void) +{ + void __iomem *reg_imr1 = gpc_base + GPC_IMR1_CORE0; + int i; + + for (i = 0; i < IMR_NUM; i++) { + gpcv2_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); + writel_relaxed(~0, reg_imr1 + i * 4); + } +} + +void imx_gpcv2_restore_all(void) +{ + void __iomem *reg_imr1 = gpc_base + GPC_IMR1_CORE0; + int i; + + for (i = 0; i < IMR_NUM; i++) + writel_relaxed(gpcv2_saved_imrs[i], reg_imr1 + i * 4); +} + +void imx_gpcv2_hwirq_unmask(unsigned int hwirq) +{ + void __iomem *reg; + u32 val; + + reg = gpc_base + GPC_IMR1_CORE0 + (hwirq / 32) * 4; + val = readl_relaxed(reg); + val &= ~(1 << hwirq % 32); + writel_relaxed(val, reg); +} + +void imx_gpcv2_hwirq_mask(unsigned int hwirq) +{ + void __iomem *reg; + u32 val; + + reg = gpc_base + GPC_IMR1_CORE0 + (hwirq / 32) * 4; + val = readl_relaxed(reg); + val |= 1 << (hwirq % 32); + writel_relaxed(val, reg); +} + +static void imx_gpcv2_irq_unmask(struct irq_data *d) +{ + imx_gpcv2_hwirq_unmask(d->hwirq); + irq_chip_unmask_parent(d); +} + +static void imx_gpcv2_irq_mask(struct irq_data *d) +{ + imx_gpcv2_hwirq_mask(d->hwirq); + irq_chip_mask_parent(d); +} + +void imx_gpcv2_set_slot_ack(u32 index, enum imx_gpc_slot m_core, + bool mode, bool ack) +{ + u32 val; + + if (index >= MAX_SLOT_NUMBER) + pr_err("Invalid slot index!\n"); + /* set slot */ + writel_relaxed(readl_relaxed(gpc_base + GPC_SLOT0_CFG + index * 4) | + ((mode + 1) << (m_core * 2)), + gpc_base + GPC_SLOT0_CFG + index * 4); + + if (ack) { + /* set ack */ + val = readl_relaxed(gpc_base + GPC_PGC_ACK_SEL_A7); + /* clear dummy ack */ + val &= ~(1 << (15 + (mode ? 16 : 0))); + val |= 1 << (m_core + (mode ? 16 : 0)); + writel_relaxed(val, gpc_base + GPC_PGC_ACK_SEL_A7); + } +} + +void imx_gpcv2_set_lpm_mode(enum mxc_cpu_pwr_mode mode) +{ + unsigned long flags; + u32 val1, val2; + + spin_lock_irqsave(&gpcv2_lock, flags); + + val1 = readl_relaxed(gpc_base + GPC_LPCR_A7_BSC); + val2 = readl_relaxed(gpc_base + GPC_SLPCR); + + /* all cores' LPM settings must be same */ + val1 &= ~(BM_LPCR_A7_BSC_LPM0 | BM_LPCR_A7_BSC_LPM1); + + val1 |= BM_LPCR_A7_BSC_CPU_CLK_ON_LPM; + + val2 &= ~(BM_SLPCR_EN_DSM | BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN | + BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY); + /* + * GPC: When improper low-power sequence is used, + * the SoC enters low power mode before the ARM core executes WFI. + * + * Software workaround: + * 1) Software should trigger IRQ #32 (IOMUX) to be always pending + * by setting IOMUX_GPR1_IRQ. + * 2) Software should then unmask IRQ #32 in GPC before setting GPC + * Low-Power mode. + * 3) Software should mask IRQ #32 right after GPC Low-Power mode + * is set. + */ + switch (mode) { + case WAIT_CLOCKED: + imx_gpcv2_hwirq_unmask(0); + break; + case WAIT_UNCLOCKED: + val1 |= A7_LPM_WAIT << BP_LPCR_A7_BSC_LPM0; + val1 &= ~BM_LPCR_A7_BSC_CPU_CLK_ON_LPM; + imx_gpcv2_hwirq_mask(0); + break; + case STOP_POWER_ON: + val1 |= A7_LPM_STOP << BP_LPCR_A7_BSC_LPM0; + val1 &= ~BM_LPCR_A7_BSC_CPU_CLK_ON_LPM; + val2 |= BM_SLPCR_EN_DSM; + val2 |= BM_SLPCR_RBC_EN; + val2 |= BM_SLPCR_BYPASS_PMIC_READY; + imx_gpcv2_hwirq_mask(0); + break; + case STOP_POWER_OFF: + val1 |= A7_LPM_STOP << BP_LPCR_A7_BSC_LPM0; + val1 &= ~BM_LPCR_A7_BSC_CPU_CLK_ON_LPM; + val2 |= BM_SLPCR_EN_DSM; + val2 |= BM_SLPCR_RBC_EN; + val2 |= BM_SLPCR_SBYOS; + val2 |= BM_SLPCR_VSTBY; + val2 |= BM_SLPCR_BYPASS_PMIC_READY; + imx_gpcv2_hwirq_mask(0); + break; + default: + return; + } + writel_relaxed(val1, gpc_base + GPC_LPCR_A7_BSC); + writel_relaxed(val2, gpc_base + GPC_SLPCR); + + spin_unlock_irqrestore(&gpcv2_lock, flags); +} + +void imx_gpcv2_set_plat_power_gate_by_lpm(bool pdn) +{ + u32 val = readl_relaxed(gpc_base + GPC_LPCR_A7_AD); + + val &= ~(BM_LPCR_A7_AD_EN_PLAT_PDN | BM_LPCR_A7_AD_L2PGE); + if (pdn) + val |= BM_LPCR_A7_AD_EN_PLAT_PDN | BM_LPCR_A7_AD_L2PGE; + + writel_relaxed(val, gpc_base + GPC_LPCR_A7_AD); +} + +void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset) +{ + u32 val = readl_relaxed(gpc_base + offset) & (~BM_GPC_PGC_PCG); + + if (enable) + val |= BM_GPC_PGC_PCG; + + writel_relaxed(val, gpc_base + offset); +} + +void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn) +{ + u32 val = readl_relaxed(gpc_base + (pdn ? + GPC_CPU_PGC_SW_PDN_REQ : GPC_CPU_PGC_SW_PUP_REQ)); + + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1); + val |= BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7; + writel_relaxed(val, gpc_base + (pdn ? + GPC_CPU_PGC_SW_PDN_REQ : GPC_CPU_PGC_SW_PUP_REQ)); + + while ((readl_relaxed(gpc_base + (pdn ? + GPC_CPU_PGC_SW_PDN_REQ : GPC_CPU_PGC_SW_PUP_REQ)) & + BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7) != 0) + ; + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1); +} + +void imx_gpcv2_set_cpu_power_gate_by_wfi(u32 cpu, bool pdn) +{ + unsigned long flags; + u32 val; + + spin_lock_irqsave(&gpcv2_lock, flags); + val = readl_relaxed(gpc_base + GPC_LPCR_A7_AD); + + if (cpu == 0) { + if (pdn) { + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C0); + val |= BM_LPCR_A7_AD_EN_C0_WFI_PDN | + BM_LPCR_A7_AD_EN_C0_IRQ_PUP; + } else { + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C0); + val &= ~(BM_LPCR_A7_AD_EN_C0_WFI_PDN | + BM_LPCR_A7_AD_EN_C0_IRQ_PUP); + } + } + if (cpu == 1) { + if (pdn) { + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1); + val |= BM_LPCR_A7_AD_EN_C1_WFI_PDN | + BM_LPCR_A7_AD_EN_C1_IRQ_PUP; + } else { + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1); + val &= ~(BM_LPCR_A7_AD_EN_C1_WFI_PDN | + BM_LPCR_A7_AD_EN_C1_IRQ_PUP); + } + } + writel_relaxed(val, gpc_base + GPC_LPCR_A7_AD); + spin_unlock_irqrestore(&gpcv2_lock, flags); +} + +void imx_gpcv2_set_cpu_power_gate_by_lpm(u32 cpu, bool pdn) +{ + unsigned long flags; + u32 val; + + spin_lock_irqsave(&gpcv2_lock, flags); + + val = readl_relaxed(gpc_base + GPC_LPCR_A7_AD); + if (cpu == 0) { + if (pdn) + val |= BM_LPCR_A7_AD_EN_C0_PDN | + BM_LPCR_A7_AD_EN_C0_PUP; + else + val &= ~(BM_LPCR_A7_AD_EN_C0_PDN | + BM_LPCR_A7_AD_EN_C0_PUP); + } + if (cpu == 1) { + if (pdn) + val |= BM_LPCR_A7_AD_EN_C1_PDN | + BM_LPCR_A7_AD_EN_C1_PUP; + else + val &= ~(BM_LPCR_A7_AD_EN_C1_PDN | + BM_LPCR_A7_AD_EN_C1_PUP); + } + + writel_relaxed(val, gpc_base + GPC_LPCR_A7_AD); + spin_unlock_irqrestore(&gpcv2_lock, flags); +} + +void imx_gpcv2_set_cpu_power_gate_in_idle(bool pdn) +{ + unsigned long flags; + u32 cpu; + + for_each_possible_cpu(cpu) + imx_gpcv2_set_cpu_power_gate_by_lpm(cpu, pdn); + + spin_lock_irqsave(&gpcv2_lock, flags); + + imx_gpcv2_set_m_core_pgc(pdn, GPC_PGC_C0); + if (num_online_cpus() > 1) + imx_gpcv2_set_m_core_pgc(pdn, GPC_PGC_C1); + imx_gpcv2_set_m_core_pgc(pdn, GPC_PGC_SCU); + imx_gpcv2_set_plat_power_gate_by_lpm(pdn); + + if (pdn) { + imx_gpcv2_set_slot_ack(0, CORE0_A7, false, false); + if (num_online_cpus() > 1) + imx_gpcv2_set_slot_ack(2, CORE1_A7, false, false); + imx_gpcv2_set_slot_ack(3, SCU_A7, false, true); + imx_gpcv2_set_slot_ack(6, SCU_A7, true, false); + if (num_online_cpus() > 1) + imx_gpcv2_set_slot_ack(6, CORE1_A7, true, false); + imx_gpcv2_set_slot_ack(6, CORE0_A7, true, true); + } else { + writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 0 * 0x4); + writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 2 * 0x4); + writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 3 * 0x4); + writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 6 * 0x4); + writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 7 * 0x4); + writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 8 * 0x4); + writel_relaxed(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK | + BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK, + gpc_base + GPC_PGC_ACK_SEL_A7); + imx_gpcv2_enable_rbc(false); + } + spin_unlock_irqrestore(&gpcv2_lock, flags); +} + +void imx_gpcv2_set_mix_phy_gate_by_lpm(u32 pdn_index, u32 pup_index) +{ + /* set power down slot */ + writel_relaxed(1 << (FAST_MEGA_MIX * 2), + gpc_base + GPC_SLOT0_CFG + pdn_index * 4); + + /* set power up slot */ + writel_relaxed(1 << (FAST_MEGA_MIX * 2 + 1), + gpc_base + GPC_SLOT0_CFG + pup_index * 4); +} + +unsigned int imx_gpcv2_is_mf_mix_off(void) +{ + return readl_relaxed(gpc_base + GPC_PGC_FM); +} + +static void imx_gpcv2_mf_mix_off(void) +{ + int i; + + for (i = 0; i < IMR_NUM; i++) + if (((gpcv2_wake_irqs[i] | gpcv2_mf_request_on[i]) & + gpcv2_mf_irqs[i]) != 0) + return; + + pr_info("Turn off Mega/Fast mix in DSM\n"); + imx_gpcv2_set_slot_ack(1, FAST_MEGA_MIX, false, false); + imx_gpcv2_set_slot_ack(5, FAST_MEGA_MIX, true, false); + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_FM); +} + +int imx_gpcv2_mf_power_on(unsigned int irq, unsigned int on) +{ + struct irq_desc *desc = irq_to_desc(irq); + unsigned long hwirq = desc->irq_data.hwirq; + unsigned int idx = hwirq / 32; + unsigned long flags; + u32 mask = 1 << (hwirq % 32); + + BUG_ON(idx >= IMR_NUM); + + spin_lock_irqsave(&gpcv2_lock, flags); + gpcv2_mf_request_on[idx] = on ? gpcv2_mf_request_on[idx] | mask : + gpcv2_mf_request_on[idx] & ~mask; + spin_unlock_irqrestore(&gpcv2_lock, flags); + + return 0; +} + +void imx_gpcv2_enable_rbc(bool enable) +{ + u32 val; + + /* + * need to mask all interrupts in GPC before + * operating RBC configurations + */ + imx_gpcv2_mask_all(); + + /* configure RBC enable bit */ + val = readl_relaxed(gpc_base + GPC_SLPCR); + val &= ~BM_SLPCR_RBC_EN; + val |= enable ? BM_SLPCR_RBC_EN : 0; + writel_relaxed(val, gpc_base + GPC_SLPCR); + + /* configure RBC count */ + val = readl_relaxed(gpc_base + GPC_SLPCR); + val &= ~BM_SLPCR_REG_BYPASS_COUNT; + val |= enable ? BM_SLPCR_REG_BYPASS_COUNT : 0; + writel(val, gpc_base + GPC_SLPCR); + + /* + * need to delay at least 2 cycles of CKIL(32K) + * due to hardware design requirement, which is + * ~61us, here we use 65us for safe + */ + udelay(65); + + /* restore GPC interrupt mask settings */ + imx_gpcv2_restore_all(); +} + + +void imx_gpcv2_pre_suspend(bool arm_power_off) +{ + void __iomem *reg_imr1 = gpc_base + GPC_IMR1_CORE0; + int i; + + if (arm_power_off) { + imx_gpcv2_set_lpm_mode(STOP_POWER_OFF); + /* enable core0 power down/up with low power mode */ + imx_gpcv2_set_cpu_power_gate_by_lpm(0, true); + /* enable plat power down with low power mode */ + imx_gpcv2_set_plat_power_gate_by_lpm(true); + + /* + * To avoid confuse, we use slot 0~4 for power down, + * slot 5~9 for power up. + * + * Power down slot sequence: + * Slot0 -> CORE0 + * Slot1 -> Mega/Fast MIX + * Slot2 -> SCU + * + * Power up slot sequence: + * Slot5 -> Mega/Fast MIX + * Slot6 -> SCU + * Slot7 -> CORE0 + */ + imx_gpcv2_set_slot_ack(0, CORE0_A7, false, false); + imx_gpcv2_set_slot_ack(2, SCU_A7, false, true); + + if ((!imx_src_is_m4_enabled()) || + (imx_src_is_m4_enabled() && imx_mu_is_m4_in_stop())) + imx_gpcv2_mf_mix_off();; + + imx_gpcv2_set_slot_ack(6, SCU_A7, true, false); + imx_gpcv2_set_slot_ack(6, CORE0_A7, true, true); + + /* enable core0, scu */ + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C0); + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_SCU); + } else { + imx_gpcv2_set_lpm_mode(STOP_POWER_ON); + } + + for (i = 0; i < IMR_NUM; i++) { + gpcv2_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); + writel_relaxed(~gpcv2_wake_irqs[i], reg_imr1 + i * 4); + } +} + +void imx_gpcv2_enable_wakeup_for_m4(void) +{ + void __iomem *reg_imr2 = gpc_base + GPC_IMR1_M4; + u32 i; + + for (i = 0; i < IMR_NUM; i++) { + gpcv2_saved_imrs_m4[i] = readl_relaxed(reg_imr2 + i * 4); + writel_relaxed(~gpcv2_wake_irqs[i], reg_imr2 + i * 4); + } +} + +void imx_gpcv2_disable_wakeup_for_m4(void) +{ + void __iomem *reg_imr2 = gpc_base + GPC_IMR1_M4; + u32 i; + + for (i = 0; i < IMR_NUM; i++) + writel_relaxed(gpcv2_saved_imrs_m4[i], reg_imr2 + i * 4); +} + +void imx_gpcv2_post_resume(void) +{ + void __iomem *reg_imr1 = gpc_base + GPC_IMR1_CORE0; + int i, val; + + /* only external IRQs to wake up LPM and core 0/1 */ + val = readl_relaxed(gpc_base + GPC_LPCR_A7_BSC); + val |= BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP; + writel_relaxed(val, gpc_base + GPC_LPCR_A7_BSC); + /* mask m4 dsm trigger if M4 NOT enabled */ + if (!imx_src_is_m4_enabled()) + writel_relaxed(readl_relaxed(gpc_base + GPC_LPCR_M4) | + BM_LPCR_M4_MASK_DSM_TRIGGER, gpc_base + GPC_LPCR_M4); + /* set mega/fast mix in A7 domain */ + writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_MAPPING); + /* set SCU timing */ + writel_relaxed((0x59 << 10) | 0x5B | (0x2 << 20), + gpc_base + GPC_PGC_SCU_TIMING); + + /* set C0/C1 power up timming per design requirement */ + val = readl_relaxed(gpc_base + GPC_PGC_C0_PUPSCR); + val &= ~BM_GPC_PGC_CORE_PUPSCR; + val |= (0x1A << 7); + writel_relaxed(val, gpc_base + GPC_PGC_C0_PUPSCR); + + val = readl_relaxed(gpc_base + GPC_PGC_C1_PUPSCR); + val &= ~BM_GPC_PGC_CORE_PUPSCR; + val |= (0x1A << 7); + writel_relaxed(val, gpc_base + GPC_PGC_C1_PUPSCR); + + val = readl_relaxed(gpc_base + GPC_SLPCR); + val &= ~(BM_SLPCR_EN_DSM); + if (!imx_src_is_m4_enabled()) + val &= ~(BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN | + BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY); + val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE; + writel_relaxed(val, gpc_base + GPC_SLPCR); + + if (imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) { + /* disable memory low power mode */ + val = readl_relaxed(gpc_base + GPC_MLPCR); + val |= BM_GPC_MLPCR_MEMLP_CTL_DIS; + writel_relaxed(val, gpc_base + GPC_MLPCR); + } + + for (i = 0; i < IMR_NUM; i++) + writel_relaxed(gpcv2_saved_imrs[i], reg_imr1 + i * 4); + + imx_gpcv2_set_lpm_mode(WAIT_CLOCKED); + imx_gpcv2_set_cpu_power_gate_by_lpm(0, false); + imx_gpcv2_set_plat_power_gate_by_lpm(false); + + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C0); + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_SCU); + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_FM); + for (i = 0; i < MAX_SLOT_NUMBER; i++){ + if (i == 1 || i == 5) /* skip slts m4 uses */ + continue; + writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + i * 0x4); + } + writel_relaxed(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK | + BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK, + gpc_base + GPC_PGC_ACK_SEL_A7); + + /* disable RBC */ + imx_gpcv2_enable_rbc(false); +} + +static struct irq_chip imx_gpcv2_chip = { + .name = "GPCV2", + .irq_eoi = irq_chip_eoi_parent, + .irq_mask = imx_gpcv2_irq_mask, + .irq_unmask = imx_gpcv2_irq_unmask, + .irq_retrigger = irq_chip_retrigger_hierarchy, + .irq_set_wake = imx_gpcv2_irq_set_wake, +#ifdef CONFIG_SMP + .irq_set_affinity = irq_chip_set_affinity_parent, +#endif +}; + +static int imx_gpcv2_domain_xlate(struct irq_domain *domain, + struct device_node *controller, + const u32 *intspec, + unsigned int intsize, + unsigned long *out_hwirq, + unsigned int *out_type) +{ + if (irq_domain_get_of_node(domain) != controller) + return -EINVAL; /* Shouldn't happen, really... */ + if (intsize != 3) + return -EINVAL; /* Not GIC compliant */ + if (intspec[0] != 0) + return -EINVAL; /* No PPI should point to this domain */ + + *out_hwirq = intspec[1]; + *out_type = intspec[2]; + return 0; +} + +static int imx_gpcv2_domain_alloc(struct irq_domain *domain, + unsigned int irq, + unsigned int nr_irqs, void *data) +{ + struct irq_fwspec *fwspec = data; + struct irq_fwspec parent_fwspec; + irq_hw_number_t hwirq; + int i; + + if (fwspec->param_count != 3) + return -EINVAL; /* Not GIC compliant */ + if (fwspec->param[0] != 0) + return -EINVAL; /* No PPI should point to this domain */ + + hwirq = fwspec->param[1]; + if (hwirq >= GPC_MAX_IRQS) + return -EINVAL; /* Can't deal with this */ + + for (i = 0; i < nr_irqs; i++) + irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i, + &imx_gpcv2_chip, NULL); + + parent_fwspec.fwnode = domain->parent->fwnode; + parent_fwspec.param_count = 3; + parent_fwspec.param[0] = 0; + parent_fwspec.param[1] = hwirq; + parent_fwspec.param[2] = fwspec->param[2]; + + return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs, + &parent_fwspec); +} + +static struct irq_domain_ops imx_gpcv2_domain_ops = { + .xlate = imx_gpcv2_domain_xlate, + .alloc = imx_gpcv2_domain_alloc, + .free = irq_domain_free_irqs_common, +}; + +static int __init imx_gpcv2_init(struct device_node *node, + struct device_node *parent) +{ + struct irq_domain *parent_domain, *domain; + int i, val; + + if (!parent) { + pr_err("%s: no parent, giving up\n", node->full_name); + return -ENODEV; + } + + parent_domain = irq_find_host(parent); + if (!parent_domain) { + pr_err("%s: unable to obtain parent domain\n", node->full_name); + return -ENXIO; + } + + gpc_base = of_iomap(node, 0); + if (WARN_ON(!gpc_base)) + return -ENOMEM; + + domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS, + node, &imx_gpcv2_domain_ops, + NULL); + if (!domain) { + iounmap(gpc_base); + return -ENOMEM; + } + + /* Initially mask all interrupts */ + for (i = 0; i < IMR_NUM; i++) { + writel_relaxed(~0, gpc_base + GPC_IMR1_CORE0 + i * 4); + writel_relaxed(~0, gpc_base + GPC_IMR1_CORE1 + i * 4); + } + /* + * Due to hardware design requirement, need to make sure GPR + * interrupt(#32) is unmasked during RUN mode to avoid entering + * DSM by mistake. + */ + writel_relaxed(~0x1, gpc_base + GPC_IMR1_CORE0); + + /* Read supported wakeup source in M/F domain */ + if (cpu_is_imx7d()) { + of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 0, + &gpcv2_mf_irqs[0]); + of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 1, + &gpcv2_mf_irqs[1]); + of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 2, + &gpcv2_mf_irqs[2]); + of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 3, + &gpcv2_mf_irqs[3]); + if (!(gpcv2_mf_irqs[0] | gpcv2_mf_irqs[1] | + gpcv2_mf_irqs[2] | gpcv2_mf_irqs[3])) + pr_info("No wakeup source in Mega/Fast domain found!\n"); + } + + /* only external IRQs to wake up LPM and core 0/1 */ + val = readl_relaxed(gpc_base + GPC_LPCR_A7_BSC); + val |= BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP; + writel_relaxed(val, gpc_base + GPC_LPCR_A7_BSC); + /* mask m4 dsm trigger if M4 NOT enabled */ + if (!imx_src_is_m4_enabled()) + writel_relaxed(readl_relaxed(gpc_base + GPC_LPCR_M4) | + BM_LPCR_M4_MASK_DSM_TRIGGER, gpc_base + GPC_LPCR_M4); + /* set mega/fast mix in A7 domain */ + writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_MAPPING); + /* set SCU timing */ + writel_relaxed((0x59 << 10) | 0x5B | (0x2 << 20), + gpc_base + GPC_PGC_SCU_TIMING); + + /* set C0/C1 power up timming per design requirement */ + val = readl_relaxed(gpc_base + GPC_PGC_C0_PUPSCR); + val &= ~BM_GPC_PGC_CORE_PUPSCR; + val |= (0x1A << 7); + writel_relaxed(val, gpc_base + GPC_PGC_C0_PUPSCR); + + val = readl_relaxed(gpc_base + GPC_PGC_C1_PUPSCR); + val &= ~BM_GPC_PGC_CORE_PUPSCR; + val |= (0x1A << 7); + writel_relaxed(val, gpc_base + GPC_PGC_C1_PUPSCR); + + writel_relaxed(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK | + BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK, + gpc_base + GPC_PGC_ACK_SEL_A7); + + val = readl_relaxed(gpc_base + GPC_SLPCR); + val &= ~(BM_SLPCR_EN_DSM); + if (!imx_src_is_m4_enabled()) + val &= ~(BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN | + BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY); + val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE; + writel_relaxed(val, gpc_base + GPC_SLPCR); + + if (imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) { + /* disable memory low power mode */ + val = readl_relaxed(gpc_base + GPC_MLPCR); + val |= BM_GPC_MLPCR_MEMLP_CTL_DIS; + writel_relaxed(val, gpc_base + GPC_MLPCR); + } + + /* disable RBC */ + imx_gpcv2_enable_rbc(false); + + /* + * Clear the OF_POPULATED flag set in of_irq_init so that + * later the GPC power domain driver will not be skipped. + */ + of_node_clear_flag(node, OF_POPULATED); + + return 0; +} + +/* + * We cannot use the IRQCHIP_DECLARE macro that lives in + * drivers/irqchip, so we're forced to roll our own. Not very nice. + */ +OF_DECLARE_2(irqchip, imx_gpcv2, "fsl,imx7d-gpc", imx_gpcv2_init); + +void __init imx_gpcv2_check_dt(void) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-gpc"); + if (WARN_ON(!np)) + return; + + if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) { + pr_warn("Outdated DT detected, suspend/resume will NOT work\n"); + + /* map GPC, so that at least CPUidle and WARs keep working */ + gpc_base = of_iomap(np, 0); + } +} diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h index 92c5a9c9f94bf7..eb05e859272981 100644 --- a/arch/arm/mach-imx/hardware.h +++ b/arch/arm/mach-imx/hardware.h @@ -81,13 +81,16 @@ * CCM 0x020c4000+0x004000 -> 0xf42c4000+0x004000 * ANATOP 0x020c8000+0x004000 -> 0xf42c8000+0x004000 * UART4 0x021f0000+0x004000 -> 0xf42f0000+0x004000 + * mx7d: + * CCM 0x30380000+0x010000 -> 0xf5380000+0x010000 + * ANATOP 0x30360000+0x010000 -> 0xf5360000+0x010000 + * UART1 0x30860000+0x010000 -> 0xf5860000+0x010000 */ #define IMX_IO_P2V(x) ( \ - (((x) & 0x80000000) >> 7) | \ (0xf4000000 + \ - (((x) & 0x50000000) >> 6) + \ - (((x) & 0x0b000000) >> 4) + \ - (((x) & 0x000fffff)))) + (((x) & 0x50000000) >> 4) + \ + (((x) & 0x0a000000) >> 4) + \ + (((x) & 0x00ffffff)))) #define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x)) @@ -99,6 +102,9 @@ #include "mx2x.h" #include "mx21.h" #include "mx27.h" +#include "mx6.h" +#include "mx7.h" +#include "mx7ulp.h" #define imx_map_entry(soc, name, _type) { \ .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S index 766dbdb2ae27b9..c19cfc3166ae57 100644 --- a/arch/arm/mach-imx/headsmp.S +++ b/arch/arm/mach-imx/headsmp.S @@ -21,6 +21,17 @@ diag_reg_offset: ENTRY(v7_secondary_startup) ARM_BE8(setend be) @ go BE8 if entered LE + mrc p15, 0, r0, c0, c0, 0 + ldr r1, =0xf00 + orr r1, r1, #0xff + mov r0, r0, lsr #4 + and r0, r0, r1 + /* 0xc07 is cortex A7's ID */ + ldr r1, =0xc00 + orr r1, r1, #0x7 + cmp r0, r1 + beq secondary_startup + set_diag_reg b secondary_startup ENDPROC(v7_secondary_startup) diff --git a/arch/arm/mach-imx/imx6sl_low_power_idle.S b/arch/arm/mach-imx/imx6sl_low_power_idle.S new file mode 100644 index 00000000000000..978f8d1cc234fa --- /dev/null +++ b/arch/arm/mach-imx/imx6sl_low_power_idle.S @@ -0,0 +1,776 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the license, or + * (at your option) any later version. + * + * This program is distributed in teh hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define PM_INFO_PM_INFO_SIZE_OFFSET 0x0 +#define PM_INFO_TTBR_OFFSET 0x4 +#define PM_INFO_MMDC_V_OFFSET 0x8 +#define PM_INFO_IOMUXC_V_OFFSET 0xc +#define PM_INFO_CCM_V_OFFSET 0x10 +#define PM_INFO_L2_V_OFFSET 0x14 +#define PM_INFO_ANATOP_V_OFFSET 0x18 +#define PM_INFO_IO_NUM_OFFSET 0x1c +#define PM_INFO_IO_VAL_OFFSET 0x20 + +#define MX6Q_MMDC_MAPSR 0x404 +#define MX6Q_MMDC_MPDGCTRL0 0x83c + +.global mx6sl_lpm_wfi_start +.global mx6sl_lpm_wfi_end + + .macro pll_do_wait_lock +1: + ldr r7, [r10, r8] + ands r7, #0x80000000 + beq 1b + + .endm + + .macro ccm_do_wait +2: + ldr r7, [r10, #0x48] + cmp r7, #0x0 + bne 2b + + .endm + + .macro ccm_enter_idle + + ldr r10, [r0, #PM_INFO_CCM_V_OFFSET] + /* + * if in audio_bus_freq_mode, skip to + * audio_mode low power setting. + */ + cmp r1, #0x1 + beq audio_mode + /* + * Now set DDR rate to 1MHz. + * DDR is from bypassed PLL2 on periph2_clk2 path. + * Set the periph2_clk2_podf to divide by 8. + */ + ldr r6, [r10, #0x14] + orr r6, r6, #0x07 + str r6, [r10, #0x14] + + /* Now set MMDC PODF to divide by 3. */ + ldr r6, [r10, #0x14] + bic r6, r6, #0x38 + orr r6, r6, #0x10 + str r6, [r10, #0x14] + + ccm_do_wait + + /* Set the AHB to 3MHz. AXI to 3MHz. */ + ldr r6, [r10, #0x14] + /*r12 stores the origin AHB podf value */ + mov r12, r6 + orr r6, r6, #0x1c00 + orr r6, r6, #0x70000 + str r6, [r10, #0x14] + + ccm_do_wait + + /* Now set ARM to 24MHz. + * Move ARM to be sourced from step_clk + * after setting step_clk to 24MHz. + */ + ldr r6, [r10, #0x0c] + bic r6, r6, #0x100 + str r6, [r10, #0xc] + /*Now pll1_sw_clk to step_clk */ + ldr r6, [r10, #0x0c] + orr r6, r6, #0x4 + str r6, [r10, #0x0c] + + /* Bypass PLL1 and power it down */ + ldr r10, [r0, #PM_INFO_ANATOP_V_OFFSET] + ldr r6, =(1 << 16) + orr r6, r6, #0x1000 + str r6, [r10, #0x04] + + /* + * Set the ARM PODF to divide by 8. + * IPG is at 1.5MHz here, we need ARM to + * run at the 12:5 ratio (WAIT mode issue). + */ + ldr r10, [r0, #PM_INFO_CCM_V_OFFSET] + ldr r11, [r10, #0x10] + ldr r6, =0x07 + str r6, [r10, #0x10] + + ccm_do_wait + + b ccm_idle_done + +audio_mode: + /* + * MMDC is sourced from pll2_200M. + * Set the mmdc_podf to div by 8 + */ + ldr r10, [r0, #PM_INFO_CCM_V_OFFSET] + ldr r6, [r10, #0x14] + orr r6, r6, #0x38 + str r6, [r10, #0x14] + + ccm_do_wait + + /* + * ARM is sourced from pll2_pfd2_400M here. + * switch ARM to bypassed PLL1 + */ + ldr r10, [r0, #PM_INFO_CCM_V_OFFSET] + ldr r6, [r10, #0x0c] + bic r6, r6, #0x4 + str r6, [r10, #0xc] + + /* + * set the arm_podf to divide by 3 + * as IPG is at 4MHz, we cannot run + * arm clk above 9.6MHz when system + * enter WAIT mode + */ + ldr r11, [r10, #0x10] + ldr r6, =0x2 + str r6, [r10, #0x10] + + ccm_do_wait + +ccm_idle_done: + + .endm + + .macro ccm_exit_idle + + /* + * If in audio_bus_freq_mode, skip to + * audio_mode ccm restore. + */ + cmp r1, #0x1 + beq audio_ccm_restore + + ldr r10, [r0, #PM_INFO_ANATOP_V_OFFSET] + /* Power up PLL1 and un-bypass it. */ + ldr r6, =(1 << 12) + str r6, [r10, #0x08] + + /* Wait for PLL1 to relock */ + ldr r8, =0x0 + pll_do_wait_lock + + ldr r6, =(1 << 16) + str r6, [r10, #0x08] + + ldr r10, [r0, #PM_INFO_CCM_V_OFFSET] + /* Set PLL1_sw_clk back to PLL1 */ + ldr r6, [r10, #0x0c] + bic r6, r6, #0x4 + str r6, [r10, #0x0c] + + /* Restore AHB/AXI back */ + str r12, [r10, #0x14] + + ccm_do_wait + + /* restore mmdc back to 24MHz*/ + ldr r6, [r10, #0x14] + bic r6, r6, #0x3f + str r6, [r10, #0x14] + + ccm_do_wait + b ccm_exit_done + +audio_ccm_restore: + /* move arm clk back to pll2_pfd2_400M */ + ldr r6, [r10, #0xc] + orr r6, r6, #0x4 + str r6, [r10, #0xc] + + /* restore mmdc podf */ + ldr r10, [r0, #PM_INFO_CCM_V_OFFSET] + ldr r6, [r10, #0x14] + bic r6, r6, #0x38 + orr r6, #0x8 + str r6, [r10, #0x14] + + ccm_do_wait + +ccm_exit_done: + + .endm + + .macro check_pll_state + + ldr r10, [r0, #PM_INFO_ANATOP_V_OFFSET] + /* + * Check whether any PLL is enabled, as only when + * there is no PLLs enabled, 2p5 can be off and + * only enable the weak one. PLL1 will be powered + * down late, so no need to check PLL1 state. + */ + + /* sys PLL2 */ + ldr r6, [r10, #0x30] + ands r6, r6, #(1 << 31) + bne 1f + + /* usb PLL3 */ + ldr r6, [r10, #0x10] + ands r6, r6, #(1 << 31) + bne 1f + + /* audio PLL4 */ + ldr r6, [r10, #0x70] + ands r6, r6, #(1 << 31) + bne 1f + + /* video PLL5 */ + ldr r6, [r10, #0xa0] + ands r6, r6, #(1 << 31) + bne 1f + + /* enet PLL6 */ + ldr r6, [r10, #0xe0] + ands r6, r6, #(1 << 31) + bne 1f + + /* usb host PLL7 */ + ldr r6, [r10, #0x20] + ands r6, r6, #(1 << 31) + bne 1f + + ldr r4, =0x1 + b check_done +1: + ldr r4, =0x0 + +check_done: + .endm + + .macro anatop_enter_idle + + ldr r10, [r0, #PM_INFO_ANATOP_V_OFFSET] + cmp r4, #0x0 + beq anatop_enter_done + + /* Disable 1p1 brown out. */ + ldr r10, [r0, #PM_INFO_ANATOP_V_OFFSET] + ldr r6, [r10, #0x110] + bic r6, r6, #0x2 + str r6, [r10, #0x110] + /* + * Set the OSC bias current to -37.5% + * to drop the power on VDDHIGH. + */ + ldr r6, [r10, #0x150] + orr r6, r6, #0xc000 + str r6, [r10, #0x150] + + /* + * if the usb VBUS wakeup is enabled, skip + * disable main 2p5. + */ + cmp r2, #0x1 + beq anatop_enter_done + + /* Enable the week 2p5 */ + ldr r6, [r10, #0x130] + orr r6, r6, #0x40000 + str r6, [r10, #0x130] + + /* Disable main 2p5. */ + ldr r6, [r10, #0x130] + bic r6, r6, #0x1 + str r6, [r10, #0x130] + + /* + * Cannot diable regular bandgap + * in LDO-enable mode. The bandgap + * is required for ARM-LDO to regulate + * the voltage. + */ + ldr r6, [r10, #0x140] + and r6, r6, #0x1f + cmp r6, #0x1f + bne anatop_enter_done + + /* Enable low power bandgap */ + ldr r6, [r10, #0x260] + orr r6, r6, #0x20 + str r6, [r10, #0x260] + + /* + * Turn off the bias current + * from the regular bandgap. + */ + ldr r6, [r10, #0x260] + orr r6, r6, #0x80 + str r6, [r10, #0x260] + + /* + * Clear the REFTTOP+SELFBIASOFF, + * self_bais circuit of the band gap. + * Per RM, should be cleared when + * band gap is powered down. + */ + ldr r6, [r10, #0x150] + bic r6, r6, #0x8 + str r6, [r10, #0x150] + + /* Power down the regular bandgap */ + ldr r6, [r10, #0x150] + orr r6, r6, #0x1 + str r6, [r10, #0x150] +anatop_enter_done: + + .endm + + .macro anatop_exit_idle + + ldr r10, [r0, #PM_INFO_ANATOP_V_OFFSET] + cmp r4, #0x0 + beq skip_anatop_restore + + cmp r2, #0x1 + beq ldo2p5_not_disabled + /* + * Regular bandgap will not be disabled + * in LDO-enabled mode as it is required + * for ARM-LDO to reguulate the voltage. + */ + ldr r6, [r10, #0x140] + and r6, r6, #0x1f + cmp r6, #0x1f + bne skip_bandgap_restore + + /* Power up the regular bandgap */ + ldr r6, [r10, #0x150] + bic r6, r6, #0x1 + str r6, [r10, #0x150] + + /* wait for bandgap stable */ +3: + ldr r6, [r10, #0x150] + and r6, r6, #0x80 + cmp r6, #0x80 + bne 3b + + /* now disable bandgap self-bias circuit */ + ldr r6, [r10, #0x150] + orr r6, r6, #0x8 + str r6, [r10, #0x150] + + /* Turn on the bias current + * from the regular bandgap. + */ + ldr r6, [r10, #0x260] + bic r6, r6, #0x80 + str r6, [r10, #0x260] + + /* Disable the low power bandgap */ + ldr r6, [r10, #0x260] + bic r6, r6, #0x20 + str r6, [r10, #0x260] + +skip_bandgap_restore: + /* Enable main 2p5. */ + ldr r6, [r10, #0x130] + orr r6, r6, #0x1 + str r6, [r10, #0x130] + + /* Ensure the 2p5 is up */ +5: + ldr r6, [r10, #0x130] + and r6, r6, #0x20000 + cmp r6, #0x20000 + bne 5b + + /* Disable the weak 2p5 */ + ldr r6, [r10, #0x130] + bic r6, r6, #0x40000 + str r6, [r10, #0x130] + +ldo2p5_not_disabled: + /* + * Set the OSC bias current to max + * value for normal operation. + */ + ldr r6, [r10, #0x150] + bic r6, r6, #0xc000 + str r6, [r10, #0x150] + + /* Enable 1p1 brown out, */ + ldr r6, [r10, #0x110] + orr r6, r6, #0x2 + str r6, [r10, #0x110] + +skip_anatop_restore: + + .endm + + .macro disable_l1_dcache + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + + dsb + isb + + .endm + + .macro mmdc_enter_dvfs_mode + + /* disable automatic power saving. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + /* disable power down timer */ + ldr r7, [r10, #0x04] + bic r7, r7, #0xff00 + str r7, [r10, #0x04] + + /* Make the DDR explicitly enter self-refresh. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] + +poll_dvfs_set: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + beq poll_dvfs_set + + /* set SBS step-by step mode */ + ldr r7, [r10, #0x410] + orr r7, r7, #0x100 + str r7, [r10, #0x410] + + .endm + + .macro resume_mmdc + /* restore MMDC IO */ + ldr r10, [r0, #PM_INFO_IOMUXC_V_OFFSET] + + ldr r6, [r0, #PM_INFO_IO_NUM_OFFSET] + ldr r7, =PM_INFO_IO_VAL_OFFSET + add r7, r7, r0 +6: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r10, r8] + subs r6, r6, #0x1 + bne 6b + + /* + * Need to reset the FIFO to avoid MMDC lockup + * caused because of floating/changing the + * configuration of many DDR IO pads. + */ + ldr r10, [r0, #PM_INFO_MMDC_V_OFFSET] + /* reset read FIFO, RST_RD_FIFO */ + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +7: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 7b + + /* reset FIFO a second time */ + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +8: + ldr r6, [r10, r7] + ands r6, r6, #(1 <<31) + bne 8b + + ldr r10, [r0, #PM_INFO_MMDC_V_OFFSET] + /* Let DDR out of self-refresh */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +9: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + bne 9b + + /* enable power down timer */ + ldr r7, [r10, #0x04] + orr r7, r7, #0x5500 + str r7, [r10, #0x04] + + /* enable DDR auto power saving */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + /* Clear SBS - unblock DDR accesses */ + ldr r7, [r10, #0x410] + bic r7, r7, #0x100 + str r7, [r10, #0x410] + + .endm + + .macro tlb_set_to_ocram + + /* save ttbr */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_TTBR_OFFSET] + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * we need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to the IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is transslated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Disable Branch Prediction, Z bit in SCTLR */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + dsb + isb + + /* store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + /* Read TTBCR and set PD0=1, N=1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* Flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + .endm + + .macro tlb_back_to_ddr + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N=0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + /* Flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0 ,r6, c1, c0, 0 + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + /* Restore ttbr */ + ldr r7, [r0, #PM_INFO_TTBR_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + +.extern iram_tlb_phys_addr + +/* + * imx6sl_low_power_wfi code + * r0: wfi code base address + * r1: audio_bus_freq mode stat + * r2: vbus_ldo status + * r4: used for store the PLLs state + * r11: used for saving the ARM_PODF origin value + * r12: used for saving AHB_PODF origin value + */ + .align 3 +ENTRY(imx6sl_low_power_idle) + +mx6sl_lpm_wfi_start: + push {r4-r12} + + tlb_set_to_ocram + disable_l1_dcache + +#ifdef CONFIG_CACHE_L2X0 + /* sync L2 */ + ldr r10, [r0, #PM_INFO_L2_V_OFFSET] + /* Wait for background operations to complete. */ +wait_for_l2_idle: + ldr r6, [r10, #0x730] + cmp r6, #0x0 + bne wait_for_l2_idle + + mov r6, #0x0 + str r6, [r10, #0x730] + /* disable L2 */ + str r6, [r10, #0x100] + + dsb + isb +#endif + + /* make sure MMDC in self-refresh */ + ldr r10, [r0, #PM_INFO_MMDC_V_OFFSET] + mmdc_enter_dvfs_mode + /* save DDR IO settings and set to LPM mode*/ + ldr r10, [r0, #PM_INFO_IOMUXC_V_OFFSET] + ldr r6, =0x0 + ldr r7, [r0, #PM_INFO_IO_NUM_OFFSET] + ldr r8, =PM_INFO_IO_VAL_OFFSET + add r8, r8, r0 + + /* imx6sl's last 3 IOs need special setting */ + sub r7, r7, #0x3 +save_and_set_mmdc_io_lpm: + ldr r9, [r8], #0x4 + ldr r5, [r10, r9] + str r6, [r10, r9] + str r5, [r8], #0x4 + subs r7, r7, #0x1 + bne save_and_set_mmdc_io_lpm + ldr r6, =0x1000 + ldr r9, [r8], #0x4 + ldr r5, [r10, r9] + str r5, [r8], #0x4 + str r6, [r10, r9] + ldr r9, [r8], #0x4 + ldr r5, [r10, r9] + str r6, [r10, r9] + str r5, [r8], #0x4 + ldr r6, =0x80000 + ldr r9, [r8], #0x4 + ldr r5, [r10, r9] + str r6, [r10, r9] + str r5, [r8], #0x4 + + + /* check the PLLs lock state */ + check_pll_state + + ccm_enter_idle + /* if in audio low power mode, no + * need to do anatop setting. + */ + cmp r1, #0x1 + beq do_wfi + anatop_enter_idle +do_wfi: + wfi + /* + * Add these nops so that the + * prefetcher will not try to get + * any instrutions from DDR. + * The prefetch depth is about 23 + * on A9, so adding 25 nops. + */ + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + /* + * restore the ARM PODF first to speed + * up the restore procedure + */ + ldr r10, [r0, #PM_INFO_CCM_V_OFFSET] + /* Restore arm_clk_podf */ + str r11, [r10, #0x10] + ccm_do_wait + + /* + * if in audio low power mode, skip + * restore the anatop setting. + */ + cmp r1, #0x1 + beq skip_analog_restore + anatop_exit_idle + +skip_analog_restore: + ccm_exit_idle + resume_mmdc + + /* enable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + orr r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + +#ifdef CONFIG_CACHE_L2X0 + ldr r10, [r0, #PM_INFO_L2_V_OFFSET] + mov r7, #0x1 + /* enable L2 */ + str r7, [r10, #0x100] +#endif + tlb_back_to_ddr + + /* Restore register */ + pop {r4 - r12} + mov pc, lr + + /* + * Add ltorg here to ensure that all + * literals are stored here and are + * within the text space. + */ + .ltorg +mx6sl_lpm_wfi_end: diff --git a/arch/arm/mach-imx/imx6sll_low_power_idle.S b/arch/arm/mach-imx/imx6sll_low_power_idle.S new file mode 100644 index 00000000000000..a7e206ecbb42d7 --- /dev/null +++ b/arch/arm/mach-imx/imx6sll_low_power_idle.S @@ -0,0 +1,780 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define PM_INFO_PBASE_OFFSET 0x0 +#define PM_INFO_RESUME_ADDR_OFFSET 0x4 +#define PM_INFO_PM_INFO_SIZE_OFFSET 0x8 +#define PM_INFO_PM_INFO_TTBR_OFFSET 0xc +#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10 +#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14 +#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x18 +#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x1c +#define PM_INFO_MX6Q_CCM_P_OFFSET 0x20 +#define PM_INFO_MX6Q_CCM_V_OFFSET 0x24 +#define PM_INFO_MX6Q_GPC_P_OFFSET 0x28 +#define PM_INFO_MX6Q_GPC_V_OFFSET 0x2c +#define PM_INFO_MX6Q_ANATOP_P_OFFSET 0x30 +#define PM_INFO_MX6Q_ANATOP_V_OFFSET 0x34 +#define PM_INFO_MX6Q_SRC_P_OFFSET 0x38 +#define PM_INFO_MX6Q_SRC_V_OFFSET 0x3c +#define PM_INFO_MX6Q_L2_P_OFFSET 0x40 +#define PM_INFO_MX6Q_L2_V_OFFSET 0x44 +#define PM_INFO_MX6Q_SAVED_DIAGNOSTIC_OFFSET 0x48 + +#define PM_INFO_MMDC_IO_NUM_OFFSET 0x4c +#define PM_INFO_MMDC_IO_VAL_OFFSET 0x50 + +#define MX6Q_MMDC_MAPSR 0x404 +#define MX6Q_MMDC_MPDGCTRL0 0x83c +#define MX6Q_SRC_GPR1 0x20 +#define MX6Q_SRC_GPR2 0x24 +#define MX6Q_GPC_IMR1 0x08 +#define MX6Q_GPC_IMR2 0x0c +#define MX6Q_GPC_IMR3 0x10 +#define MX6Q_GPC_IMR4 0x14 +#define MX6Q_CCM_CCR 0x0 + +.globl mx6sll_lpm_wfi_start +.globl mx6sll_lpm_wfi_end + + .macro pll_do_wait_lock +1: + ldr r7, [r10, r8] + ands r7, #0x80000000 + beq 1b + + .endm + + .macro ccm_do_wait +2: + ldr r7, [r10, #0x48] + cmp r7, #0x0 + bne 2b + + .endm + + .macro ccm_enter_idle + + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + + /* set ahb to 3MHz */ + ldr r7, [r10, #0x14] + orr r7, r7, #0x1c00 + str r7, [r10, #0x14] + + /* set perclk to 6MHz */ + ldr r7, [r10, #0x1c] + bic r7, r7, #0x3f + orr r7, r7, #0x3 + str r7, [r10, #0x1c] + + /* set mmdc to 1MHz, periph2_clk2 need to be @8MHz */ + ldr r7, [r10, #0x14] + orr r7, r7, #0x2 + orr r7, r7, #(0x7 << 3) + str r7, [r10, #0x14] + + ccm_do_wait + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* + * disable pll2, suppose when system enter low + * power idle mode, only 396MHz pfd needs pll2, + * now we switch arm clock to OSC, we can disable + * pll2 now, gate pll2_pfd2 first. + */ + ldr r7, [r10, #0x100] + orr r7, #0x800000 + str r7, [r10, #0x100] + + ldr r7, [r10, #0x30] + orr r7, r7, #0x1000 + bic r7, r7, #0x2000 + str r7, [r10, #0x30] + + .endm + + .macro ccm_exit_idle + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* enable pll2 and pll2_pfd2 */ + ldr r7, [r10, #0x30] + bic r7, r7, #0x1000 + orr r7, r7, #0x2000 + str r7, [r10, #0x30] + + ldr r8, =0x30 + pll_do_wait_lock + + ldr r7, [r10, #0x100] + bic r7, #0x800000 + str r7, [r10, #0x100] + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_CCM_P_OFFSET] + + /* set perclk back to 24MHz */ + ldr r7, [r10, #0x1c] + bic r7, r7, #0x3f + str r7, [r10, #0x1c] + + /* set mmdc back to 24MHz */ + ldr r7, [r10, #0x14] + bic r7, r7, #0x7 + bic r7, r7, #(0x7 << 3) + str r7, [r10, #0x14] + + /* set ahb div back to 24MHz */ + ldr r7, [r10, #0x14] + bic r7, r7, #0x1c00 + str r7, [r10, #0x14] + + ccm_do_wait + + .endm + + .macro anatop_enter_idle + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* + * check whether any PLL is enabled, as only when + * there is no PLLs enabled, 2P5 and 1P1 can be + * off and only enable weak ones. + */ + + /* arm pll1 */ + ldr r7, [r10, #0] + ands r7, r7, #(1 << 31) + bne 10f + + /* sys pll2 */ + ldr r7, [r10, #0x30] + ands r7, r7, #(1 << 31) + bne 10f + + /* usb pll3 */ + ldr r7, [r10, #0x10] + ands r7, r7, #(1 << 31) + bne 10f + + /* audio pll4 */ + ldr r7, [r10, #0x70] + ands r7, r7, #(1 << 31) + bne 10f + + /* vidio pll5 */ + ldr r7, [r10, #0xa0] + ands r7, r7, #(1 << 31) + bne 10f + + /* enet pll6 */ + ldr r7, [r10, #0xe0] + ands r7, r7, #(1 << 31) + bne 10f + + /* usb host pll7 */ + ldr r7, [r10, #0x20] + ands r7, r7, #(1 << 31) + bne 10f + + /* enable weak 2P5 and turn off regular 2P5 */ + ldr r7, [r10, #0x130] + orr r7, r7, #0x40000 + str r7, [r10, #0x130] + bic r7, r7, #0x1 + str r7, [r10, #0x130] + + /* enable weak 1p1 and turn off regular 1P1 */ + ldr r7, [r10, #0x110] + orr r7, r7, #0x40000 + str r7, [r10, #0x110] + bic r7, r7, #0x1 + str r7, [r10, #0x110] + + /* low power band gap enable */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x20 + str r7, [r10, #0x270] + + /* turn off the bias current from the regular bandgap */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x80 + str r7, [r10, #0x270] + + /* + * clear the REFTOP_SELFBIASOFF, + * self-bias circuit of the band gap. + * Per RM, should be cleared when + * band gap is powered down. + */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x8 + str r7, [r10, #0x150] + + /* turn off regular bandgap */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x1 + str r7, [r10, #0x150] + +10: + /* switch to RC-OSC */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x10 + str r7, [r10, #0x270] + + /* turn off XTAL-OSC */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x40000000 + str r7, [r10, #0x150] + + /* lower OSC current by 37.5% */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x6000 + str r7, [r10, #0x150] + + /* disconnect vdd_high_in and vdd_snvs_in */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x1000 + str r7, [r10, #0x150] + + .endm + + .macro anatop_exit_idle + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* increase OSC current to normal */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x6000 + str r7, [r10, #0x150] + + /* turn on XTAL-OSC and detector */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x40000000 + orr r7, r7, #0x10000 + str r7, [r10, #0x150] + + /* wait for XTAL stable */ +14: + ldr r7, [r10, #0x150] + ands r7, r7, #0x8000 + beq 14b + + /* switch to XTAL-OSC */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x10 + str r7, [r10, #0x270] + + /* turn off XTAL-OSC detector */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x10000 + str r7, [r10, #0x150] +15: + /* check whether we need to enable 2P5/1P1 */ + ldr r7, [r10, #0x110] + ands r7, r7, #0x40000 + beq 11f + + /* turn on regular bandgap and wait for stable */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x1 + str r7, [r10, #0x150] +13: + ldr r7, [r10, #0x150] + ands r7, #0x80 + beq 13b + + /* + * set the REFTOP_SELFBIASOFF, + * self-bias circuit of the band gap. + */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x8 + str r7, [r10, #0x150] + + /* turn on the bias current from the regular bandgap */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x80 + str r7, [r10, #0x270] + + /* low power band gap disable */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x20 + str r7, [r10, #0x270] +12: + /* enable regular 2P5 and turn off weak 2P5 */ + ldr r7, [r10, #0x130] + orr r7, r7, #0x1 + str r7, [r10, #0x130] + + /* Ensure the 2P5 is up. */ +3: + ldr r7, [r10, #0x130] + ands r7, r7, #0x20000 + beq 3b + ldr r7, [r10, #0x130] + bic r7, r7, #0x40000 + str r7, [r10, #0x130] + + /* enable regular 1p1 and turn off weak 1P1 */ + ldr r7, [r10, #0x110] + orr r7, r7, #0x1 + str r7, [r10, #0x110] +4: + ldr r7, [r10, #0x110] + ands r7, r7, #0x20000 + beq 4b + ldr r7, [r10, #0x110] + bic r7, r7, #0x40000 + str r7, [r10, #0x110] +11: + .endm + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + .endm + + .macro mmdc_enter_dvfs_mode + + /* disable automatic power savings. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + /* make the DDR explicitly enter self-refresh. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +5: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + beq 5b + + .endm + + .macro resume_mmdc + + /* restore MMDC IO */ + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] + + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +6: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r10, r8] + subs r6, r6, #0x1 + bne 6b + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] + + /* reset read FIFO, RST_RD_FIFO */ + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +7: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 7b + + /* reset FIFO a second time */ + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +8: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 8b + + /* let DDR out of self-refresh */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +9: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + bne 9b + + /* enable DDR auto power saving */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + .endm + + .macro tlb_set_to_ocram + + /* save ttbr */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + .endm + + .macro tlb_back_to_ddr + + /* Restore the TTBCR */ + + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* restore ttbr */ + ldr r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + +.extern iram_tlb_phys_addr + +/* imx6sx_low_power_idle */ + + .align 3 +ENTRY(imx6sll_low_power_idle) +mx6sll_lpm_wfi_start: + push {r4 - r10} + + /* get necessary info from pm_info */ + ldr r1, [r0, #PM_INFO_PBASE_OFFSET] + ldr r2, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET] + + /* + * counting the resume address in iram + * to set it in SRC register. + */ + ldr r5, =imx6sll_low_power_idle + ldr r6, =wakeup + sub r6, r6, r5 + add r8, r1, r2 + add r3, r8, r6 + + /* store physical resume addr and pm_info address. */ + ldr r10, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET] + str r3, [r10, #0x20] + str r1, [r10, #0x24] + + /* save disagnostic register */ + mrc p15, 0, r7, c15, c0, 1 + str r7, [r0, #PM_INFO_MX6Q_SAVED_DIAGNOSTIC_OFFSET] + + /* set ARM power to be gated */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r7, =0x1 + str r7, [r10, #0x2a0] + + disable_l1_dcache + +#ifdef CONFIG_CACHE_L2X0 + /* sync L2 */ + ldr r10, [r0, #PM_INFO_MX6Q_L2_V_OFFSET] + + /* Wait for background operations to complete. */ +wait_for_l2_to_idle: + ldr r7, [r10, #0x730] + cmp r7, #0x0 + bne wait_for_l2_to_idle + + mov r7, #0x0 + str r7, [r10, #0x730] + /* disable L2 */ + str r7, [r10, #0x100] + + dsb + isb +#endif + + tlb_set_to_ocram + + /* make sure MMDC in self-refresh */ + ldr r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + mmdc_enter_dvfs_mode + + /* save DDR IO settings */ + ldr r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldr r6, =0x0 + ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET + add r8, r8, r0 +save_and_set_mmdc_io_lpm: + ldr r9, [r8], #0x4 + ldr r5, [r10, r9] + str r6, [r10, r9] + str r5, [r8], #0x4 + subs r7, r7, #0x1 + bne save_and_set_mmdc_io_lpm + + mov r5, #0x0 + ccm_enter_idle + anatop_enter_idle + + /* + * mask all GPC interrupts before + * enabling the RBC counters to + * avoid the counter starting too + * early if an interupt is already + * pending. + */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r4, [r10, #MX6Q_GPC_IMR1] + ldr r5, [r10, #MX6Q_GPC_IMR2] + ldr r6, [r10, #MX6Q_GPC_IMR3] + ldr r7, [r10, #MX6Q_GPC_IMR4] + + ldr r3, =0xffffffff + str r3, [r10, #MX6Q_GPC_IMR1] + str r3, [r10, #MX6Q_GPC_IMR2] + str r3, [r10, #MX6Q_GPC_IMR3] + str r3, [r10, #MX6Q_GPC_IMR4] + + /* + * enable the RBC bypass counter here + * to hold off the interrupts. RBC counter + * = 4 (120us). With this setting, the latency + * from wakeup interrupt to ARM power up + * is ~130uS. + */ + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldr r3, [r10, #MX6Q_CCM_CCR] + bic r3, r3, #(0x3f << 21) + orr r3, r3, #(0x4 << 21) + str r3, [r10, #MX6Q_CCM_CCR] + + /* enable the counter. */ + ldr r3, [r10, #MX6Q_CCM_CCR] + orr r3, r3, #(0x1 << 27) + str r3, [r10, #MX6Q_CCM_CCR] + + /* unmask all the GPC interrupts. */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + str r4, [r10, #MX6Q_GPC_IMR1] + str r5, [r10, #MX6Q_GPC_IMR2] + str r6, [r10, #MX6Q_GPC_IMR3] + str r7, [r10, #MX6Q_GPC_IMR4] + + /* + * now delay for a short while (3usec) + * ARM is at 24MHz at this point + * so a short loop should be enough. + * this delay is required to ensure that + * the RBC counter can start counting in + * case an interrupt is already pending + * or in case an interrupt arrives just + * as ARM is about to assert DSM_request. + */ + ldr r4, =50 +rbc_loop: + subs r4, r4, #0x1 + bne rbc_loop + + wfi + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + mov r5, #0x0 + anatop_exit_idle + ccm_exit_idle + resume_mmdc + + /* clear ARM power gate setting */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r7, =0x0 + str r7, [r10, #0x2a0] + + /* enable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + orr r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + +#ifdef CONFIG_CACHE_L2X0 + ldr r10, [r0, #PM_INFO_MX6Q_L2_V_OFFSET] + mov r7, #0x1 + /* enable L2 */ + str r7, [r10, #0x100] +#endif + + tlb_back_to_ddr + + /* Restore registers */ + pop {r4 - r10} + mov pc, lr + +wakeup: + + /* invalidate L1 I-cache first */ + mov r1, #0x0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 6 + /* enable the Icache and branch prediction */ + mov r1, #0x1800 + mcr p15, 0, r1, c1, c0, 0 + isb + /* restore disagnostic register */ + ldr r7, [r0, #PM_INFO_MX6Q_SAVED_DIAGNOSTIC_OFFSET] + mcr p15, 0, r7, c15, c0, 1 + + /* get physical resume address from pm_info. */ + ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + /* clear core0's entry and parameter */ + ldr r10, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET] + mov r7, #0x0 + str r7, [r10, #MX6Q_SRC_GPR1] + str r7, [r10, #MX6Q_SRC_GPR2] + + /* clear ARM power gate setting */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_P_OFFSET] + ldr r7, =0x0 + str r7, [r10, #0x2a0] + + mov r5, #0x1 + anatop_exit_idle + ccm_exit_idle + resume_mmdc + + /* Restore registers */ + mov pc, lr + .ltorg +mx6sll_lpm_wfi_end: diff --git a/arch/arm/mach-imx/imx6sx_low_power_idle.S b/arch/arm/mach-imx/imx6sx_low_power_idle.S new file mode 100644 index 00000000000000..7ddda1cd1a8fff --- /dev/null +++ b/arch/arm/mach-imx/imx6sx_low_power_idle.S @@ -0,0 +1,887 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define PM_INFO_PBASE_OFFSET 0x0 +#define PM_INFO_RESUME_ADDR_OFFSET 0x4 +#define PM_INFO_PM_INFO_SIZE_OFFSET 0x8 +#define PM_INFO_PM_INFO_TTBR_OFFSET 0xc +#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10 +#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14 +#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x18 +#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x1c +#define PM_INFO_MX6Q_CCM_P_OFFSET 0x20 +#define PM_INFO_MX6Q_CCM_V_OFFSET 0x24 +#define PM_INFO_MX6Q_GPC_P_OFFSET 0x28 +#define PM_INFO_MX6Q_GPC_V_OFFSET 0x2c +#define PM_INFO_MX6Q_L2_P_OFFSET 0x30 +#define PM_INFO_MX6Q_L2_V_OFFSET 0x34 +#define PM_INFO_MX6Q_ANATOP_P_OFFSET 0x38 +#define PM_INFO_MX6Q_ANATOP_V_OFFSET 0x3c +#define PM_INFO_MX6Q_SRC_P_OFFSET 0x40 +#define PM_INFO_MX6Q_SRC_V_OFFSET 0x44 +#define PM_INFO_MX6Q_SEMA4_P_OFFSET 0x48 +#define PM_INFO_MX6Q_SEMA4_V_OFFSET 0x4c +#define PM_INFO_MX6Q_SAVED_DIAGNOSTIC_OFFSET 0x50 +#define PM_INFO_MMDC_IO_NUM_OFFSET 0x54 +#define PM_INFO_MMDC_IO_VAL_OFFSET 0x58 + +#define MX6Q_MMDC_MAPSR 0x404 +#define MX6Q_MMDC_MPDGCTRL0 0x83c +#define MX6Q_SRC_GPR1 0x20 +#define MX6Q_SRC_GPR2 0x24 +#define MX6Q_GPC_IMR1 0x08 +#define MX6Q_GPC_IMR2 0x0c +#define MX6Q_GPC_IMR3 0x10 +#define MX6Q_GPC_IMR4 0x14 +#define MX6Q_CCM_CCR 0x0 + +.globl mx6sx_lpm_wfi_start +.globl mx6sx_lpm_wfi_end + + .macro pll_do_wait_lock +1: + ldr r7, [r10, r8] + ands r7, #0x80000000 + beq 1b + + .endm + + .macro ccm_do_wait +2: + ldr r7, [r10, #0x48] + cmp r7, #0x0 + bne 2b + + .endm + + .macro ccm_enter_idle + + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + + /* set ahb to 3MHz */ + ldr r7, [r10, #0x14] + orr r7, r7, #0x1c00 + str r7, [r10, #0x14] + + /* set perclk to 6MHz */ + ldr r7, [r10, #0x1c] + bic r7, r7, #0x3f + orr r7, r7, #0x3 + str r7, [r10, #0x1c] + + /* set mmdc to 1MHz, periph2_clk2 need to be @8MHz */ + ldr r7, [r10, #0x14] + orr r7, r7, #0x2 + orr r7, r7, #(0x7 << 3) + str r7, [r10, #0x14] + + ccm_do_wait + + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + + /* set pll1_sw to from pll1 main */ + ldr r7, [r10, #0xc] + bic r7, r7, #0x4 + str r7, [r10, #0xc] + + /* set step from osc */ + ldr r7, [r10, #0xc] + bic r7, r7, #0x100 + str r7, [r10, #0xc] + + /* set pll1_sw to from step */ + ldr r7, [r10, #0xc] + orr r7, r7, #0x4 + str r7, [r10, #0xc] + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* Disable PLL1 bypass output */ + ldr r7, [r10] + bic r7, r7, #0x12000 + str r7, [r10] + + /* + * disable pll2, suppose when system enter low + * power idle mode, only 396MHz pfd needs pll2, + * now we switch arm clock to OSC, we can disable + * pll2 now, gate pll2_pfd2 first. + */ + ldr r7, [r10, #0x100] + orr r7, #0x800000 + str r7, [r10, #0x100] + + ldr r7, [r10, #0x30] + orr r7, r7, #0x1000 + bic r7, r7, #0x2000 + str r7, [r10, #0x30] + + .endm + + .macro ccm_exit_idle + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* enable pll2 and pll2_pfd2 */ + ldr r7, [r10, #0x30] + bic r7, r7, #0x1000 + orr r7, r7, #0x2000 + str r7, [r10, #0x30] + + ldr r8, =0x30 + pll_do_wait_lock + + ldr r7, [r10, #0x100] + bic r7, #0x800000 + str r7, [r10, #0x100] + + /* enable PLL1 bypass output */ + ldr r7, [r10] + orr r7, r7, #0x12000 + str r7, [r10] + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_CCM_P_OFFSET] + + /* set perclk back to 24MHz */ + ldr r7, [r10, #0x1c] + bic r7, r7, #0x3f + str r7, [r10, #0x1c] + + /* set mmdc back to 24MHz */ + ldr r7, [r10, #0x14] + bic r7, r7, #0x7 + bic r7, r7, #(0x7 << 3) + str r7, [r10, #0x14] + + /* set ahb div back to 24MHz */ + ldr r7, [r10, #0x14] + bic r7, r7, #0x1c00 + str r7, [r10, #0x14] + + ccm_do_wait + + /* set pll1_sw to from pll1 main */ + ldr r7, [r10, #0xc] + bic r7, r7, #0x4 + str r7, [r10, #0xc] + + /* set step from pll2_pfd2 */ + ldr r7, [r10, #0xc] + orr r7, r7, #0x100 + str r7, [r10, #0xc] + + /* set pll1_sw to from step */ + ldr r7, [r10, #0xc] + orr r7, r7, #0x4 + str r7, [r10, #0xc] + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + .endm + + .macro anatop_enter_idle + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* + * check whether any PLL is enabled, as only when + * there is no PLLs enabled, 2P5 and 1P1 can be + * off and only enable weak ones. + */ + + /* arm pll1 */ + ldr r7, [r10, #0] + ands r7, r7, #(1 << 31) + bne 10f + + /* sys pll2 */ + ldr r7, [r10, #0x30] + ands r7, r7, #(1 << 31) + bne 10f + + /* usb pll3 */ + ldr r7, [r10, #0x10] + ands r7, r7, #(1 << 31) + bne 10f + + /* audio pll4 */ + ldr r7, [r10, #0x70] + ands r7, r7, #(1 << 31) + bne 10f + + /* vidio pll5 */ + ldr r7, [r10, #0xa0] + ands r7, r7, #(1 << 31) + bne 10f + + /* enet pll6 */ + ldr r7, [r10, #0xe0] + ands r7, r7, #(1 << 31) + bne 10f + + /* usb host pll7 */ + ldr r7, [r10, #0x20] + ands r7, r7, #(1 << 31) + bne 10f + + /* enable weak 2P5 and turn off regular 2P5 */ + ldr r7, [r10, #0x130] + orr r7, r7, #0x40000 + str r7, [r10, #0x130] + bic r7, r7, #0x1 + str r7, [r10, #0x130] + + /* enable weak 1p1 and turn off regular 1P1 */ + ldr r7, [r10, #0x110] + orr r7, r7, #0x40000 + str r7, [r10, #0x110] + bic r7, r7, #0x1 + str r7, [r10, #0x110] + + /* check whether ARM LDO is bypassed */ + ldr r7, [r10, #0x140] + and r7, r7, #0x1f + cmp r7, #0x1f + bne 10f + + /* low power band gap enable */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x20 + str r7, [r10, #0x270] + + /* turn off the bias current from the regular bandgap */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x80 + str r7, [r10, #0x270] + + /* + * clear the REFTOP_SELFBIASOFF, + * self-bias circuit of the band gap. + * Per RM, should be cleared when + * band gap is powered down. + */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x8 + str r7, [r10, #0x150] + + /* turn off regular bandgap */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x1 + str r7, [r10, #0x150] + + /* only switch to RC-OSC clk after TO1.2 */ + ldr r7, [r10, #0x260] + and r7, r7, #0x3 + cmp r7, #0x2 + blt 10f + + /* switch to RC-OSC */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x10 + str r7, [r10, #0x270] + + /* turn off XTAL-OSC */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x40000000 + str r7, [r10, #0x150] +10: + /* lower OSC current by 37.5% */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x6000 + str r7, [r10, #0x150] + + .endm + + .macro anatop_exit_idle + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* increase OSC current to normal */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x6000 + str r7, [r10, #0x150] + + /* only switch to RC-OSC after TO1.2 */ + ldr r7, [r10, #0x260] + and r7, r7, #0x3 + cmp r7, #0x2 + blt 15f + + /* turn on XTAL-OSC and detector */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x40000000 + orr r7, r7, #0x10000 + str r7, [r10, #0x150] + + /* wait for XTAL stable */ +14: + ldr r7, [r10, #0x150] + ands r7, r7, #0x8000 + beq 14b + + /* switch to XTAL-OSC */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x10 + str r7, [r10, #0x270] + + /* turn off XTAL-OSC detector */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x10000 + str r7, [r10, #0x150] +15: + /* check whether we need to enable 2P5/1P1 */ + ldr r7, [r10, #0x110] + ands r7, r7, #0x40000 + beq 11f + + /* check whether ARM LDO is bypassed */ + ldr r7, [r10, #0x140] + and r7, r7, #0x1f + cmp r7, #0x1f + bne 12f + + /* turn on regular bandgap and wait for stable */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x1 + str r7, [r10, #0x150] +13: + ldr r7, [r10, #0x150] + ands r7, #0x80 + beq 13b + + /* + * set the REFTOP_SELFBIASOFF, + * self-bias circuit of the band gap. + */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x8 + str r7, [r10, #0x150] + + /* turn on the bias current from the regular bandgap */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x80 + str r7, [r10, #0x270] + + /* low power band gap disable */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x20 + str r7, [r10, #0x270] +12: + /* enable regular 2P5 and turn off weak 2P5 */ + ldr r7, [r10, #0x130] + orr r7, r7, #0x1 + str r7, [r10, #0x130] + + /* Ensure the 2P5 is up. */ +3: + ldr r7, [r10, #0x130] + ands r7, r7, #0x20000 + beq 3b + ldr r7, [r10, #0x130] + bic r7, r7, #0x40000 + str r7, [r10, #0x130] + + /* enable regular 1p1 and turn off weak 1P1 */ + ldr r7, [r10, #0x110] + orr r7, r7, #0x1 + str r7, [r10, #0x110] +4: + ldr r7, [r10, #0x110] + ands r7, r7, #0x20000 + beq 4b + ldr r7, [r10, #0x110] + bic r7, r7, #0x40000 + str r7, [r10, #0x110] +11: + .endm + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + .endm + + .macro mmdc_enter_dvfs_mode + + /* disable automatic power savings. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + /* disable power down timer */ + ldr r7, [r10, #0x4] + bic r7, r7, #0xff00 + str r7, [r10, #0x4] + + /* make the DDR explicitly enter self-refresh. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +5: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + beq 5b + + .endm + + .macro resume_mmdc + + /* restore MMDC IO */ + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] + + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +6: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r10, r8] + subs r6, r6, #0x1 + bne 6b + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] + + /* reset read FIFO, RST_RD_FIFO */ + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +7: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 7b + + /* reset FIFO a second time */ + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +8: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 8b + + /* let DDR out of self-refresh */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +9: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + bne 9b + + /* enable power down timer */ + ldr r7, [r10, #0x4] + orr r7, r7, #0x5500 + str r7, [r10, #0x4] + + /* enable DDR auto power saving */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + .endm + + .macro sema4_lock + + /* lock share memory sema4 */ + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_SEMA4_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_SEMA4_P_OFFSET] + ldrb r6, =0x1 +16: + ldrb r7, [r10, #0x6] + cmp r7, #0x0 + bne 16b + strb r6, [r10, #0x6] + + .endm + + .macro sema4_unlock + + /* unlock share memory sema4 */ + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_SEMA4_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_SEMA4_P_OFFSET] + ldrb r6, =0x0 + strb r6, [r10, #0x6] + + .endm + + .macro tlb_set_to_ocram + + /* save ttbr */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + .endm + + .macro tlb_back_to_ddr + + /* Restore the TTBCR */ + + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* restore ttbr */ + ldr r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + +.extern iram_tlb_phys_addr + +/* imx6sx_low_power_idle */ + + .align 3 +ENTRY(imx6sx_low_power_idle) +mx6sx_lpm_wfi_start: + push {r4 - r10} + + /* get necessary info from pm_info */ + ldr r1, [r0, #PM_INFO_PBASE_OFFSET] + ldr r2, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET] + + /* + * counting the resume address in iram + * to set it in SRC register. + */ + ldr r5, =imx6sx_low_power_idle + ldr r6, =wakeup + sub r6, r6, r5 + add r8, r1, r2 + add r3, r8, r6 + + /* store physical resume addr and pm_info address. */ + ldr r10, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET] + str r3, [r10, #0x20] + str r1, [r10, #0x24] + + /* save disagnostic register */ + mrc p15, 0, r7, c15, c0, 1 + str r7, [r0, #PM_INFO_MX6Q_SAVED_DIAGNOSTIC_OFFSET] + + /* set ARM power to be gated */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r7, =0x1 + str r7, [r10, #0x2a0] + + disable_l1_dcache + +#ifdef CONFIG_CACHE_L2X0 + /* sync L2 */ + ldr r10, [r0, #PM_INFO_MX6Q_L2_V_OFFSET] + + /* Wait for background operations to complete. */ +wait_for_l2_to_idle: + ldr r7, [r10, #0x730] + cmp r7, #0x0 + bne wait_for_l2_to_idle + + mov r7, #0x0 + str r7, [r10, #0x730] + /* disable L2 */ + str r7, [r10, #0x100] + + dsb + isb +#endif + + tlb_set_to_ocram + + /* make sure MMDC in self-refresh */ + ldr r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + mmdc_enter_dvfs_mode + + /* save DDR IO settings */ + ldr r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldr r6, =0x0 + ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET + add r8, r8, r0 +save_and_set_mmdc_io_lpm: + ldr r9, [r8], #0x4 + ldr r5, [r10, r9] + str r6, [r10, r9] + str r5, [r8], #0x4 + subs r7, r7, #0x1 + bne save_and_set_mmdc_io_lpm + + mov r5, #0x0 + sema4_lock + ccm_enter_idle + anatop_enter_idle + sema4_unlock + + /* + * mask all GPC interrupts before + * enabling the RBC counters to + * avoid the counter starting too + * early if an interupt is already + * pending. + */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r4, [r10, #MX6Q_GPC_IMR1] + ldr r5, [r10, #MX6Q_GPC_IMR2] + ldr r6, [r10, #MX6Q_GPC_IMR3] + ldr r7, [r10, #MX6Q_GPC_IMR4] + + ldr r3, =0xffffffff + str r3, [r10, #MX6Q_GPC_IMR1] + str r3, [r10, #MX6Q_GPC_IMR2] + str r3, [r10, #MX6Q_GPC_IMR3] + str r3, [r10, #MX6Q_GPC_IMR4] + + /* + * enable the RBC bypass counter here + * to hold off the interrupts. RBC counter + * = 4 (120us). With this setting, the latency + * from wakeup interrupt to ARM power up + * is ~130uS. + */ + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldr r3, [r10, #MX6Q_CCM_CCR] + bic r3, r3, #(0x3f << 21) + orr r3, r3, #(0x4 << 21) + str r3, [r10, #MX6Q_CCM_CCR] + + /* enable the counter. */ + ldr r3, [r10, #MX6Q_CCM_CCR] + orr r3, r3, #(0x1 << 27) + str r3, [r10, #MX6Q_CCM_CCR] + + /* unmask all the GPC interrupts. */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + str r4, [r10, #MX6Q_GPC_IMR1] + str r5, [r10, #MX6Q_GPC_IMR2] + str r6, [r10, #MX6Q_GPC_IMR3] + str r7, [r10, #MX6Q_GPC_IMR4] + + /* + * now delay for a short while (3usec) + * ARM is at 24MHz at this point + * so a short loop should be enough. + * this delay is required to ensure that + * the RBC counter can start counting in + * case an interrupt is already pending + * or in case an interrupt arrives just + * as ARM is about to assert DSM_request. + */ + ldr r4, =50 +rbc_loop: + subs r4, r4, #0x1 + bne rbc_loop + + wfi + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + mov r5, #0x0 + sema4_lock + anatop_exit_idle + ccm_exit_idle + sema4_unlock + resume_mmdc + + /* clear ARM power gate setting */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r7, =0x0 + str r7, [r10, #0x2a0] + + /* enable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + orr r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + +#ifdef CONFIG_CACHE_L2X0 + ldr r10, [r0, #PM_INFO_MX6Q_L2_V_OFFSET] + mov r7, #0x1 + /* enable L2 */ + str r7, [r10, #0x100] +#endif + + tlb_back_to_ddr + + /* Restore registers */ + pop {r4 - r10} + mov pc, lr + +wakeup: + + /* invalidate L1 I-cache first */ + mov r1, #0x0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 6 + /* enable the Icache and branch prediction */ + mov r1, #0x1800 + mcr p15, 0, r1, c1, c0, 0 + isb + /* restore disagnostic register */ + ldr r7, [r0, #PM_INFO_MX6Q_SAVED_DIAGNOSTIC_OFFSET] + mcr p15, 0, r7, c15, c0, 1 + + /* get physical resume address from pm_info. */ + ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + /* clear core0's entry and parameter */ + ldr r10, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET] + mov r7, #0x0 + str r7, [r10, #MX6Q_SRC_GPR1] + str r7, [r10, #MX6Q_SRC_GPR2] + + /* clear ARM power gate setting */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_P_OFFSET] + ldr r7, =0x0 + str r7, [r10, #0x2a0] + + mov r5, #0x1 + sema4_lock + anatop_exit_idle + ccm_exit_idle + sema4_unlock + resume_mmdc + + /* Restore registers */ + mov pc, lr + .ltorg +mx6sx_lpm_wfi_end: diff --git a/arch/arm/mach-imx/imx6ul_low_power_idle.S b/arch/arm/mach-imx/imx6ul_low_power_idle.S new file mode 100644 index 00000000000000..26bb83da1a7dd9 --- /dev/null +++ b/arch/arm/mach-imx/imx6ul_low_power_idle.S @@ -0,0 +1,821 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define PM_INFO_PBASE_OFFSET 0x0 +#define PM_INFO_RESUME_ADDR_OFFSET 0x4 +#define PM_INFO_PM_INFO_SIZE_OFFSET 0x8 +#define PM_INFO_PM_INFO_TTBR_OFFSET 0xc +#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10 +#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14 +#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x18 +#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x1c +#define PM_INFO_MX6Q_CCM_P_OFFSET 0x20 +#define PM_INFO_MX6Q_CCM_V_OFFSET 0x24 +#define PM_INFO_MX6Q_GPC_P_OFFSET 0x28 +#define PM_INFO_MX6Q_GPC_V_OFFSET 0x2c +#define PM_INFO_MX6Q_ANATOP_P_OFFSET 0x30 +#define PM_INFO_MX6Q_ANATOP_V_OFFSET 0x34 +#define PM_INFO_MX6Q_SRC_P_OFFSET 0x38 +#define PM_INFO_MX6Q_SRC_V_OFFSET 0x3c +#define PM_INFO_MMDC_IO_NUM_OFFSET 0x40 +#define PM_INFO_MMDC_IO_VAL_OFFSET 0x44 + +#define MX6Q_MMDC_MAPSR 0x404 +#define MX6Q_MMDC_MPDGCTRL0 0x83c +#define MX6Q_SRC_GPR1 0x20 +#define MX6Q_SRC_GPR2 0x24 +#define MX6Q_GPC_IMR1 0x08 +#define MX6Q_GPC_IMR2 0x0c +#define MX6Q_GPC_IMR3 0x10 +#define MX6Q_GPC_IMR4 0x14 +#define MX6Q_CCM_CCR 0x0 + +.globl mx6ul_lpm_wfi_start +.globl mx6ul_lpm_wfi_end + + .macro pll_do_wait_lock +1: + ldr r7, [r10, r8] + ands r7, #0x80000000 + beq 1b + + .endm + + .macro ccm_do_wait +2: + ldr r7, [r10, #0x48] + cmp r7, #0x0 + bne 2b + + .endm + + .macro ccm_enter_idle + + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + + /* set ahb to 3MHz */ + ldr r7, [r10, #0x14] + orr r7, r7, #0x1c00 + str r7, [r10, #0x14] + + /* set perclk to 6MHz */ + ldr r7, [r10, #0x1c] + bic r7, r7, #0x3f + orr r7, r7, #0x3 + str r7, [r10, #0x1c] + + /* set mmdc to 1MHz, periph2_clk2 need to be @8MHz */ + ldr r7, [r10, #0x14] + orr r7, r7, #0x2 + orr r7, r7, #(0x7 << 3) + str r7, [r10, #0x14] + + ccm_do_wait + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* bypass PLL1 output to OSC */ + ldr r7, [r10] + orr r7, r7, #(0x1 << 16) + str r7, [r10] + + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + + /* set pll1_sw to from pll1 main */ + ldr r7, [r10, #0xc] + bic r7, r7, #0x4 + str r7, [r10, #0xc] + + /* set step from osc */ + ldr r7, [r10, #0xc] + bic r7, r7, #0x100 + str r7, [r10, #0xc] + + /* set pll1_sw to from step */ + ldr r7, [r10, #0xc] + orr r7, r7, #0x4 + str r7, [r10, #0xc] + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* Disable PLL1 bypass output */ + ldr r7, [r10] + bic r7, r7, #0x12000 + str r7, [r10] + + /* + * disable pll2, suppose when system enter low + * power idle mode, only 396MHz pfd needs pll2, + * now we switch arm clock to OSC, we can disable + * pll2 now, gate pll2_pfd2 first. + */ + ldr r7, [r10, #0x100] + orr r7, #0x800000 + str r7, [r10, #0x100] + + ldr r7, [r10, #0x30] + orr r7, r7, #0x1000 + bic r7, r7, #0x2000 + str r7, [r10, #0x30] + + .endm + + .macro ccm_exit_idle + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* enable pll2 and pll2_pfd2 */ + ldr r7, [r10, #0x30] + bic r7, r7, #0x1000 + orr r7, r7, #0x2000 + str r7, [r10, #0x30] + + ldr r8, =0x30 + pll_do_wait_lock + + ldr r7, [r10, #0x100] + bic r7, #0x800000 + str r7, [r10, #0x100] + + /* enable PLL1 bypass output */ + ldr r7, [r10] + orr r7, r7, #0x12000 + str r7, [r10] + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_CCM_P_OFFSET] + + /* set perclk back to 24MHz */ + ldr r7, [r10, #0x1c] + bic r7, r7, #0x3f + str r7, [r10, #0x1c] + + /* set mmdc back to 24MHz */ + ldr r7, [r10, #0x14] + bic r7, r7, #0x7 + bic r7, r7, #(0x7 << 3) + str r7, [r10, #0x14] + + /* set ahb div back to 24MHz */ + ldr r7, [r10, #0x14] + bic r7, r7, #0x1c00 + str r7, [r10, #0x14] + + ccm_do_wait + + /* set pll1_sw to from pll1 main */ + ldr r7, [r10, #0xc] + bic r7, r7, #0x4 + str r7, [r10, #0xc] + + /* set step from pll2_pfd2 */ + ldr r7, [r10, #0xc] + orr r7, r7, #0x100 + str r7, [r10, #0xc] + + /* set pll1_sw to from step */ + ldr r7, [r10, #0xc] + orr r7, r7, #0x4 + str r7, [r10, #0xc] + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* Unbypass PLL1 */ + ldr r7, [r10] + bic r7, r7, #(0x1 << 16) + str r7, [r10] + + .endm + + .macro anatop_enter_idle + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* + * check whether any PLL is enabled, as only when + * there is no PLLs enabled, 2P5 and 1P1 can be + * off and only enable weak ones. + */ + + /* arm pll1 */ + ldr r7, [r10, #0] + ands r7, r7, #(1 << 31) + bne 10f + + /* sys pll2 */ + ldr r7, [r10, #0x30] + ands r7, r7, #(1 << 31) + bne 10f + + /* usb pll3 */ + ldr r7, [r10, #0x10] + ands r7, r7, #(1 << 31) + bne 10f + + /* audio pll4 */ + ldr r7, [r10, #0x70] + ands r7, r7, #(1 << 31) + bne 10f + + /* vidio pll5 */ + ldr r7, [r10, #0xa0] + ands r7, r7, #(1 << 31) + bne 10f + + /* enet pll6 */ + ldr r7, [r10, #0xe0] + ands r7, r7, #(1 << 31) + bne 10f + + /* usb host pll7 */ + ldr r7, [r10, #0x20] + ands r7, r7, #(1 << 31) + bne 10f + + /* enable weak 2P5 and turn off regular 2P5 */ + ldr r7, [r10, #0x130] + orr r7, r7, #0x40000 + str r7, [r10, #0x130] + bic r7, r7, #0x1 + str r7, [r10, #0x130] + + /* enable weak 1p1 and turn off regular 1P1 */ + ldr r7, [r10, #0x110] + orr r7, r7, #0x40000 + str r7, [r10, #0x110] + bic r7, r7, #0x1 + str r7, [r10, #0x110] + + /* check whether ARM LDO is bypassed */ + ldr r7, [r10, #0x140] + and r7, r7, #0x1f + cmp r7, #0x1f + bne 10f + + /* low power band gap enable */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x20 + str r7, [r10, #0x270] + + /* turn off the bias current from the regular bandgap */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x80 + str r7, [r10, #0x270] + + /* + * clear the REFTOP_SELFBIASOFF, + * self-bias circuit of the band gap. + * Per RM, should be cleared when + * band gap is powered down. + */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x8 + str r7, [r10, #0x150] + + /* turn off regular bandgap */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x1 + str r7, [r10, #0x150] + + /* switch to RC-OSC */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x10 + str r7, [r10, #0x270] + + /* turn off XTAL-OSC */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x40000000 + str r7, [r10, #0x150] +10: + /* lower OSC current by 37.5% */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x6000 + str r7, [r10, #0x150] + + /* disconnect vdd_high_in and vdd_snvs_in */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x1000 + str r7, [r10, #0x150] + + .endm + + .macro anatop_exit_idle + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* increase OSC current to normal */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x6000 + str r7, [r10, #0x150] + + /* turn on XTAL-OSC and detector */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x40000000 + orr r7, r7, #0x10000 + str r7, [r10, #0x150] + + /* wait for XTAL stable */ +14: + ldr r7, [r10, #0x150] + ands r7, r7, #0x8000 + beq 14b + + /* switch to XTAL-OSC */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x10 + str r7, [r10, #0x270] + + /* turn off XTAL-OSC detector */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x10000 + str r7, [r10, #0x150] +15: + /* check whether we need to enable 2P5/1P1 */ + ldr r7, [r10, #0x110] + ands r7, r7, #0x40000 + beq 11f + + /* check whether ARM LDO is bypassed */ + ldr r7, [r10, #0x140] + and r7, r7, #0x1f + cmp r7, #0x1f + bne 12f + + /* turn on regular bandgap and wait for stable */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x1 + str r7, [r10, #0x150] +13: + ldr r7, [r10, #0x150] + ands r7, #0x80 + beq 13b + + /* + * set the REFTOP_SELFBIASOFF, + * self-bias circuit of the band gap. + */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x8 + str r7, [r10, #0x150] + + /* turn on the bias current from the regular bandgap */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x80 + str r7, [r10, #0x270] + + /* low power band gap disable */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x20 + str r7, [r10, #0x270] +12: + /* enable regular 2P5 and turn off weak 2P5 */ + ldr r7, [r10, #0x130] + orr r7, r7, #0x1 + str r7, [r10, #0x130] + + /* Ensure the 2P5 is up. */ +3: + ldr r7, [r10, #0x130] + ands r7, r7, #0x20000 + beq 3b + ldr r7, [r10, #0x130] + bic r7, r7, #0x40000 + str r7, [r10, #0x130] + + /* enable regular 1p1 and turn off weak 1P1 */ + ldr r7, [r10, #0x110] + orr r7, r7, #0x1 + str r7, [r10, #0x110] +4: + ldr r7, [r10, #0x110] + ands r7, r7, #0x20000 + beq 4b + ldr r7, [r10, #0x110] + bic r7, r7, #0x40000 + str r7, [r10, #0x110] +11: + .endm + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + .endm + + .macro mmdc_enter_dvfs_mode + + /* disable automatic power savings. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + /* disable power down timer */ + ldr r7, [r10, #0x4] + bic r7, r7, #0xff00 + str r7, [r10, #0x4] + + /* make the DDR explicitly enter self-refresh. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +5: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + beq 5b + + .endm + + .macro resume_mmdc + + /* restore MMDC IO */ + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] + + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +6: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r10, r8] + subs r6, r6, #0x1 + bne 6b + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] + + /* reset read FIFO, RST_RD_FIFO */ + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +7: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 7b + + /* reset FIFO a second time */ + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +8: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 8b + + /* let DDR out of self-refresh */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +9: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + bne 9b + + /* enable power down timer */ + ldr r7, [r10, #0x4] + orr r7, r7, #0x5500 + str r7, [r10, #0x4] + + /* enable DDR auto power saving */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + .endm + + .macro tlb_set_to_ocram + + /* save ttbr */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + .endm + + .macro tlb_back_to_ddr + + /* Restore the TTBCR */ + + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* restore ttbr */ + ldr r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + +.extern iram_tlb_phys_addr + +/* imx6ul_low_power_idle */ + + .align 3 +ENTRY(imx6ul_low_power_idle) +mx6ul_lpm_wfi_start: + push {r4 - r10} + + /* get necessary info from pm_info */ + ldr r1, [r0, #PM_INFO_PBASE_OFFSET] + ldr r2, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET] + + /* + * counting the resume address in iram + * to set it in SRC register. + */ + ldr r5, =imx6ul_low_power_idle + ldr r6, =wakeup + sub r6, r6, r5 + add r8, r1, r2 + add r3, r8, r6 + + /* store physical resume addr and pm_info address. */ + ldr r10, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET] + str r3, [r10, #0x20] + str r1, [r10, #0x24] + + /* set ARM power to be gated */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r7, =0x1 + str r7, [r10, #0x2a0] + + disable_l1_dcache + + tlb_set_to_ocram + + /* make sure MMDC in self-refresh */ + ldr r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + mmdc_enter_dvfs_mode + + /* save DDR IO settings */ + ldr r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldr r6, =0x0 + ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET + add r8, r8, r0 +save_and_set_mmdc_io_lpm: + ldr r9, [r8], #0x4 + ldr r5, [r10, r9] + str r6, [r10, r9] + str r5, [r8], #0x4 + subs r7, r7, #0x1 + bne save_and_set_mmdc_io_lpm + + mov r5, #0x0 + ccm_enter_idle + anatop_enter_idle + + /* + * mask all GPC interrupts before + * enabling the RBC counters to + * avoid the counter starting too + * early if an interupt is already + * pending. + */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r4, [r10, #MX6Q_GPC_IMR1] + ldr r5, [r10, #MX6Q_GPC_IMR2] + ldr r6, [r10, #MX6Q_GPC_IMR3] + ldr r7, [r10, #MX6Q_GPC_IMR4] + + ldr r3, =0xffffffff + str r3, [r10, #MX6Q_GPC_IMR1] + str r3, [r10, #MX6Q_GPC_IMR2] + str r3, [r10, #MX6Q_GPC_IMR3] + str r3, [r10, #MX6Q_GPC_IMR4] + + /* + * enable the RBC bypass counter here + * to hold off the interrupts. RBC counter + * = 4 (120us). With this setting, the latency + * from wakeup interrupt to ARM power up + * is ~130uS. + */ + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldr r3, [r10, #MX6Q_CCM_CCR] + bic r3, r3, #(0x3f << 21) + orr r3, r3, #(0x4 << 21) + str r3, [r10, #MX6Q_CCM_CCR] + + /* enable the counter. */ + ldr r3, [r10, #MX6Q_CCM_CCR] + orr r3, r3, #(0x1 << 27) + str r3, [r10, #MX6Q_CCM_CCR] + + /* unmask all the GPC interrupts. */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + str r4, [r10, #MX6Q_GPC_IMR1] + str r5, [r10, #MX6Q_GPC_IMR2] + str r6, [r10, #MX6Q_GPC_IMR3] + str r7, [r10, #MX6Q_GPC_IMR4] + + /* + * now delay for a short while (3usec) + * ARM is at 24MHz at this point + * so a short loop should be enough. + * this delay is required to ensure that + * the RBC counter can start counting in + * case an interrupt is already pending + * or in case an interrupt arrives just + * as ARM is about to assert DSM_request. + */ + ldr r4, =50 +rbc_loop: + subs r4, r4, #0x1 + bne rbc_loop + + wfi + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + mov r5, #0x0 + anatop_exit_idle + ccm_exit_idle + + /* clear ARM power gate setting */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r7, =0x0 + str r7, [r10, #0x2a0] + + resume_mmdc + /* enable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + orr r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + + tlb_back_to_ddr + + /* Restore registers */ + pop {r4 - r10} + mov pc, lr + +wakeup: + /* invalidate L1 I-cache first */ + mov r1, #0x0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 6 + /* enable the Icache and branch prediction */ + mov r1, #0x1800 + mcr p15, 0, r1, c1, c0, 0 + isb + + /* get physical resume address from pm_info. */ + ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + /* clear core0's entry and parameter */ + ldr r10, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET] + mov r7, #0x0 + str r7, [r10, #MX6Q_SRC_GPR1] + str r7, [r10, #MX6Q_SRC_GPR2] + + /* clear ARM power gate setting */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_P_OFFSET] + ldr r7, =0x0 + str r7, [r10, #0x2a0] + + mov r5, #0x1 + anatop_exit_idle + ccm_exit_idle + resume_mmdc + + /* Restore registers */ + mov pc, lr + .ltorg +mx6ul_lpm_wfi_end: diff --git a/arch/arm/mach-imx/imx6ull_low_power_idle.S b/arch/arm/mach-imx/imx6ull_low_power_idle.S new file mode 100644 index 00000000000000..76ceac7fae2649 --- /dev/null +++ b/arch/arm/mach-imx/imx6ull_low_power_idle.S @@ -0,0 +1,764 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define PM_INFO_PBASE_OFFSET 0x0 +#define PM_INFO_RESUME_ADDR_OFFSET 0x4 +#define PM_INFO_PM_INFO_SIZE_OFFSET 0x8 +#define PM_INFO_PM_INFO_TTBR_OFFSET 0xc +#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10 +#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14 +#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x18 +#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x1c +#define PM_INFO_MX6Q_CCM_P_OFFSET 0x20 +#define PM_INFO_MX6Q_CCM_V_OFFSET 0x24 +#define PM_INFO_MX6Q_GPC_P_OFFSET 0x28 +#define PM_INFO_MX6Q_GPC_V_OFFSET 0x2c +#define PM_INFO_MX6Q_ANATOP_P_OFFSET 0x30 +#define PM_INFO_MX6Q_ANATOP_V_OFFSET 0x34 +#define PM_INFO_MX6Q_SRC_P_OFFSET 0x38 +#define PM_INFO_MX6Q_SRC_V_OFFSET 0x3c +#define PM_INFO_MMDC_IO_NUM_OFFSET 0x40 +#define PM_INFO_MMDC_IO_VAL_OFFSET 0x44 + +#define MX6Q_MMDC_MAPSR 0x404 +#define MX6Q_MMDC_MPDGCTRL0 0x83c +#define MX6Q_SRC_GPR1 0x20 +#define MX6Q_SRC_GPR2 0x24 +#define MX6Q_GPC_IMR1 0x08 +#define MX6Q_GPC_IMR2 0x0c +#define MX6Q_GPC_IMR3 0x10 +#define MX6Q_GPC_IMR4 0x14 +#define MX6Q_CCM_CCR 0x0 + +.globl mx6ull_lpm_wfi_start +.globl mx6ull_lpm_wfi_end + + .macro pll_do_wait_lock +1: + ldr r7, [r10, r8] + ands r7, #0x80000000 + beq 1b + + .endm + + .macro ccm_do_wait +2: + ldr r7, [r10, #0x48] + cmp r7, #0x0 + bne 2b + + .endm + + .macro ccm_enter_idle + + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + + /* set ahb to 3MHz */ + ldr r7, [r10, #0x14] + orr r7, r7, #0x1c00 + str r7, [r10, #0x14] + + /* set perclk to 6MHz */ + ldr r7, [r10, #0x1c] + bic r7, r7, #0x3f + orr r7, r7, #0x3 + str r7, [r10, #0x1c] + + /* set mmdc to 1MHz, periph2_clk2 need to be @8MHz */ + ldr r7, [r10, #0x14] + orr r7, r7, #0x2 + orr r7, r7, #(0x7 << 3) + str r7, [r10, #0x14] + + ccm_do_wait + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* + * disable pll2, suppose when system enter low + * power idle mode, only 396MHz pfd needs pll2, + * now we switch arm clock to OSC, we can disable + * pll2 now, gate pll2_pfd2 first. + */ + ldr r7, [r10, #0x100] + orr r7, #0x800000 + str r7, [r10, #0x100] + + ldr r7, [r10, #0x30] + orr r7, r7, #0x1000 + bic r7, r7, #0x2000 + str r7, [r10, #0x30] + + .endm + + .macro ccm_exit_idle + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* enable pll2 and pll2_pfd2 */ + ldr r7, [r10, #0x30] + bic r7, r7, #0x1000 + orr r7, r7, #0x2000 + str r7, [r10, #0x30] + + ldr r8, =0x30 + pll_do_wait_lock + + ldr r7, [r10, #0x100] + bic r7, #0x800000 + str r7, [r10, #0x100] + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_CCM_P_OFFSET] + + /* set perclk back to 24MHz */ + ldr r7, [r10, #0x1c] + bic r7, r7, #0x3f + str r7, [r10, #0x1c] + + /* set mmdc back to 24MHz */ + ldr r7, [r10, #0x14] + bic r7, r7, #0x7 + bic r7, r7, #(0x7 << 3) + str r7, [r10, #0x14] + + /* set ahb div back to 24MHz */ + ldr r7, [r10, #0x14] + bic r7, r7, #0x1c00 + str r7, [r10, #0x14] + + ccm_do_wait + + .endm + + .macro anatop_enter_idle + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* + * check whether any PLL is enabled, as only when + * there is no PLLs enabled, 2P5 and 1P1 can be + * off and only enable weak ones. + */ + + /* arm pll1 */ + ldr r7, [r10, #0] + ands r7, r7, #(1 << 31) + bne 10f + + /* sys pll2 */ + ldr r7, [r10, #0x30] + ands r7, r7, #(1 << 31) + bne 10f + + /* usb pll3 */ + ldr r7, [r10, #0x10] + ands r7, r7, #(1 << 31) + bne 10f + + /* audio pll4 */ + ldr r7, [r10, #0x70] + ands r7, r7, #(1 << 31) + bne 10f + + /* vidio pll5 */ + ldr r7, [r10, #0xa0] + ands r7, r7, #(1 << 31) + bne 10f + + /* enet pll6 */ + ldr r7, [r10, #0xe0] + ands r7, r7, #(1 << 31) + bne 10f + + /* usb host pll7 */ + ldr r7, [r10, #0x20] + ands r7, r7, #(1 << 31) + bne 10f + + /* enable weak 2P5 and turn off regular 2P5 */ + ldr r7, [r10, #0x130] + orr r7, r7, #0x40000 + str r7, [r10, #0x130] + bic r7, r7, #0x1 + str r7, [r10, #0x130] + + /* enable weak 1p1 and turn off regular 1P1 */ + ldr r7, [r10, #0x110] + orr r7, r7, #0x40000 + str r7, [r10, #0x110] + bic r7, r7, #0x1 + str r7, [r10, #0x110] + + /* check whether ARM LDO is bypassed */ + ldr r7, [r10, #0x140] + and r7, r7, #0x1f + cmp r7, #0x1f + bne 10f + + /* low power band gap enable */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x20 + str r7, [r10, #0x270] + + /* turn off the bias current from the regular bandgap */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x80 + str r7, [r10, #0x270] + + /* + * clear the REFTOP_SELFBIASOFF, + * self-bias circuit of the band gap. + * Per RM, should be cleared when + * band gap is powered down. + */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x8 + str r7, [r10, #0x150] + + /* turn off regular bandgap */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x1 + str r7, [r10, #0x150] + +10: + /* switch to RC-OSC */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x10 + str r7, [r10, #0x270] + + /* turn off XTAL-OSC */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x40000000 + str r7, [r10, #0x150] + + /* lower OSC current by 37.5% */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x6000 + str r7, [r10, #0x150] + + /* disconnect vdd_high_in and vdd_snvs_in */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x1000 + str r7, [r10, #0x150] + + .endm + + .macro anatop_exit_idle + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* increase OSC current to normal */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x6000 + str r7, [r10, #0x150] + + /* turn on XTAL-OSC and detector */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x40000000 + orr r7, r7, #0x10000 + str r7, [r10, #0x150] + + /* wait for XTAL stable */ +14: + ldr r7, [r10, #0x150] + ands r7, r7, #0x8000 + beq 14b + + /* switch to XTAL-OSC */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x10 + str r7, [r10, #0x270] + + /* turn off XTAL-OSC detector */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x10000 + str r7, [r10, #0x150] +15: + /* check whether we need to enable 2P5/1P1 */ + ldr r7, [r10, #0x110] + ands r7, r7, #0x40000 + beq 11f + + /* check whether ARM LDO is bypassed */ + ldr r7, [r10, #0x140] + and r7, r7, #0x1f + cmp r7, #0x1f + bne 12f + + /* turn on regular bandgap and wait for stable */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x1 + str r7, [r10, #0x150] +13: + ldr r7, [r10, #0x150] + ands r7, #0x80 + beq 13b + + /* + * set the REFTOP_SELFBIASOFF, + * self-bias circuit of the band gap. + */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x8 + str r7, [r10, #0x150] + + /* turn on the bias current from the regular bandgap */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x80 + str r7, [r10, #0x270] + + /* low power band gap disable */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x20 + str r7, [r10, #0x270] +12: + /* enable regular 2P5 and turn off weak 2P5 */ + ldr r7, [r10, #0x130] + orr r7, r7, #0x1 + str r7, [r10, #0x130] + + /* Ensure the 2P5 is up. */ +3: + ldr r7, [r10, #0x130] + ands r7, r7, #0x20000 + beq 3b + ldr r7, [r10, #0x130] + bic r7, r7, #0x40000 + str r7, [r10, #0x130] + + /* enable regular 1p1 and turn off weak 1P1 */ + ldr r7, [r10, #0x110] + orr r7, r7, #0x1 + str r7, [r10, #0x110] +4: + ldr r7, [r10, #0x110] + ands r7, r7, #0x20000 + beq 4b + ldr r7, [r10, #0x110] + bic r7, r7, #0x40000 + str r7, [r10, #0x110] +11: + .endm + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + .endm + + .macro mmdc_enter_dvfs_mode + + /* disable automatic power savings. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + /* disable power down timer */ + ldr r7, [r10, #0x4] + bic r7, r7, #0xff00 + str r7, [r10, #0x4] + + /* make the DDR explicitly enter self-refresh. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +5: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + beq 5b + + .endm + + .macro resume_mmdc + + /* restore MMDC IO */ + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] + + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +6: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r10, r8] + subs r6, r6, #0x1 + bne 6b + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] + + /* reset read FIFO, RST_RD_FIFO */ + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +7: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 7b + + /* reset FIFO a second time */ + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +8: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 8b + + /* let DDR out of self-refresh */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +9: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + bne 9b + + /* enable power down timer */ + ldr r7, [r10, #0x4] + orr r7, r7, #0x5500 + str r7, [r10, #0x4] + + /* enable DDR auto power saving */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + .endm + + .macro tlb_set_to_ocram + + /* save ttbr */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + .endm + + .macro tlb_back_to_ddr + + /* Restore the TTBCR */ + + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* restore ttbr */ + ldr r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + +.extern iram_tlb_phys_addr + +/* imx6ull_low_power_idle */ + + .align 3 +ENTRY(imx6ull_low_power_idle) +mx6ull_lpm_wfi_start: + push {r4 - r10} + + /* get necessary info from pm_info */ + ldr r1, [r0, #PM_INFO_PBASE_OFFSET] + ldr r2, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET] + + /* + * counting the resume address in iram + * to set it in SRC register. + */ + ldr r5, =imx6ull_low_power_idle + ldr r6, =wakeup + sub r6, r6, r5 + add r8, r1, r2 + add r3, r8, r6 + + /* store physical resume addr and pm_info address. */ + ldr r10, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET] + str r3, [r10, #0x20] + str r1, [r10, #0x24] + + /* set ARM power to be gated */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r7, =0x1 + str r7, [r10, #0x2a0] + + disable_l1_dcache + + tlb_set_to_ocram + + /* make sure MMDC in self-refresh */ + ldr r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + mmdc_enter_dvfs_mode + + /* save DDR IO settings */ + ldr r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldr r6, =0x0 + ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET + add r8, r8, r0 +save_and_set_mmdc_io_lpm: + ldr r9, [r8], #0x4 + ldr r5, [r10, r9] + str r6, [r10, r9] + str r5, [r8], #0x4 + subs r7, r7, #0x1 + bne save_and_set_mmdc_io_lpm + + mov r5, #0x0 + ccm_enter_idle + anatop_enter_idle + + /* + * mask all GPC interrupts before + * enabling the RBC counters to + * avoid the counter starting too + * early if an interupt is already + * pending. + */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r4, [r10, #MX6Q_GPC_IMR1] + ldr r5, [r10, #MX6Q_GPC_IMR2] + ldr r6, [r10, #MX6Q_GPC_IMR3] + ldr r7, [r10, #MX6Q_GPC_IMR4] + + ldr r3, =0xffffffff + str r3, [r10, #MX6Q_GPC_IMR1] + str r3, [r10, #MX6Q_GPC_IMR2] + str r3, [r10, #MX6Q_GPC_IMR3] + str r3, [r10, #MX6Q_GPC_IMR4] + + /* + * enable the RBC bypass counter here + * to hold off the interrupts. RBC counter + * = 4 (120us). With this setting, the latency + * from wakeup interrupt to ARM power up + * is ~130uS. + */ + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldr r3, [r10, #MX6Q_CCM_CCR] + bic r3, r3, #(0x3f << 21) + orr r3, r3, #(0x4 << 21) + str r3, [r10, #MX6Q_CCM_CCR] + + /* enable the counter. */ + ldr r3, [r10, #MX6Q_CCM_CCR] + orr r3, r3, #(0x1 << 27) + str r3, [r10, #MX6Q_CCM_CCR] + + /* unmask all the GPC interrupts. */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + str r4, [r10, #MX6Q_GPC_IMR1] + str r5, [r10, #MX6Q_GPC_IMR2] + str r6, [r10, #MX6Q_GPC_IMR3] + str r7, [r10, #MX6Q_GPC_IMR4] + + /* + * now delay for a short while (3usec) + * ARM is at 24MHz at this point + * so a short loop should be enough. + * this delay is required to ensure that + * the RBC counter can start counting in + * case an interrupt is already pending + * or in case an interrupt arrives just + * as ARM is about to assert DSM_request. + */ + ldr r4, =50 +rbc_loop: + subs r4, r4, #0x1 + bne rbc_loop + + wfi + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + mov r5, #0x0 + anatop_exit_idle + ccm_exit_idle + + /* clear ARM power gate setting */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r7, =0x0 + str r7, [r10, #0x2a0] + + resume_mmdc + /* enable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + orr r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + + tlb_back_to_ddr + + /* Restore registers */ + pop {r4 - r10} + mov pc, lr + +wakeup: + /* invalidate L1 I-cache first */ + mov r1, #0x0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 6 + /* enable the Icache and branch prediction */ + mov r1, #0x1800 + mcr p15, 0, r1, c1, c0, 0 + isb + + /* get physical resume address from pm_info. */ + ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + /* clear core0's entry and parameter */ + ldr r10, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET] + mov r7, #0x0 + str r7, [r10, #MX6Q_SRC_GPR1] + str r7, [r10, #MX6Q_SRC_GPR2] + + /* clear ARM power gate setting */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_P_OFFSET] + ldr r7, =0x0 + str r7, [r10, #0x2a0] + + mov r5, #0x1 + anatop_exit_idle + ccm_exit_idle + resume_mmdc + + /* Restore registers */ + mov pc, lr + .ltorg +mx6ull_lpm_wfi_end: diff --git a/arch/arm/mach-imx/imx7d_low_power_idle.S b/arch/arm/mach-imx/imx7d_low_power_idle.S new file mode 100644 index 00000000000000..85c229700ec43b --- /dev/null +++ b/arch/arm/mach-imx/imx7d_low_power_idle.S @@ -0,0 +1,788 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define PM_INFO_VBASE_OFFSET 0x0 +#define PM_INFO_PBASE_OFFSET 0x4 +#define PM_INFO_RESUME_ADDR_OFFSET 0x8 +#define PM_INFO_PM_INFO_SIZE_OFFSET 0xc +#define PM_INFO_PM_INFO_TTBR_OFFSET 0x10 +#define PM_INFO_PM_INFO_NUM_ONLINE_CPUS_OFFSET 0x14 +#define PM_INFO_PM_INFO_NUM_LPI_CPUS_OFFSET 0x18 +#define PM_INFO_VAL_OFFSET 0x1c +#define PM_INFO_FLAG0_OFFSET 0x20 +#define PM_INFO_FLAG1_OFFSET 0x24 +#define PM_INFO_MX7D_DDRC_P_OFFSET 0x28 +#define PM_INFO_MX7D_DDRC_V_OFFSET 0x2c +#define PM_INFO_MX7D_CCM_P_OFFSET 0x30 +#define PM_INFO_MX7D_CCM_V_OFFSET 0x34 +#define PM_INFO_MX7D_ANATOP_P_OFFSET 0x38 +#define PM_INFO_MX7D_ANATOP_V_OFFSET 0x3c +#define PM_INFO_MX7D_SRC_P_OFFSET 0x40 +#define PM_INFO_MX7D_SRC_V_OFFSET 0x44 +#define PM_INFO_MX7D_IOMUXC_GPR_P_OFFSET 0x48 +#define PM_INFO_MX7D_IOMUXC_GPR_V_OFFSET 0x4c +#define PM_INFO_MX7D_GPC_P_OFFSET 0x50 +#define PM_INFO_MX7D_GPC_V_OFFSET 0x54 +#define PM_INFO_MX7D_GIC_DIST_P_OFFSET 0x58 +#define PM_INFO_MX7D_GIC_DIST_V_OFFSET 0x5c + +#define MX7D_SRC_GPR1 0x74 +#define MX7D_SRC_GPR2 0x78 +#define MX7D_SRC_GPR3 0x7c +#define MX7D_SRC_GPR4 0x80 +#define MX7D_GPC_IMR1 0x30 +#define MX7D_GPC_IMR2 0x34 +#define MX7D_GPC_IMR3 0x38 +#define MX7D_GPC_IMR4 0x3c +#define DDRC_STAT 0x4 +#define DDRC_PWRCTL 0x30 +#define DDRC_DBG1 0x304 +#define DDRC_DBGCAM 0x308 +#define DDRC_PSTAT 0x3fc +#define DDRC_PCTRL_0 0x490 + +/* + * imx_pen_lock + * + * The reference link of Peterson's algorithm: + * http://en.wikipedia.org/wiki/Peterson's_algorithm + * + * val1 = r1 = !turn (inverted from Peterson's algorithm) + * on cpu 0: + * r2 = flag[0] (in flag0) + * r3 = flag[1] (in flag1) + * on cpu1: + * r2 = flag[1] (in flag1) + * r3 = flag[0] (in flag0) + * + */ + .macro imx_pen_lock + + mov r8, r0 + mrc p15, 0, r5, c0, c0, 5 + and r5, r5, #3 + add r6, r8, #PM_INFO_VAL_OFFSET + cmp r5, #0 + addeq r7, r8, #PM_INFO_FLAG0_OFFSET + addeq r8, r8, #PM_INFO_FLAG1_OFFSET + addne r7, r8, #PM_INFO_FLAG1_OFFSET + addne r8, r8, #PM_INFO_FLAG0_OFFSET + + mov r9, #1 + str r9, [r7] + dsb + str r5, [r6] +1: + dsb + ldr r9, [r8] + cmp r9, #1 + ldreq r9, [r6] + cmpeq r9, r5 + beq 1b + + .endm + + .macro imx_pen_unlock + + dsb + mrc p15, 0, r6, c0, c0, 5 + and r6, r6, #3 + cmp r6, #0 + addeq r7, r0, #PM_INFO_FLAG0_OFFSET + addne r7, r0, #PM_INFO_FLAG1_OFFSET + mov r9, #0 + str r9, [r7] + + .endm + + .macro disable_l1_dcache + + push {r0 - r12, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r12, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 - r12, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r12, lr} + +#ifdef CONFIG_SMP + clrex + + /* Turn off SMP bit. */ + mrc p15, 0, r8, c1, c0, 1 + bic r8, r8, #0x40 + mcr p15, 0, r8, c1, c0, 1 + + isb + dsb +#endif + + .endm + + .macro tlb_set_to_ocram + + /* save ttbr */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + .endm + + .macro tlb_back_to_ddr + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* restore ttbr */ + ldr r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + + /* r10 must be DDRC base address */ + .macro ddrc_enter_self_refresh + + ldr r10, [r0, #PM_INFO_MX7D_DDRC_V_OFFSET] + + /* disable port */ + ldr r7, =0x0 + str r7, [r10, #DDRC_PCTRL_0] + + /* let DDR out of self-refresh */ + ldr r7, =0x0 + str r7, [r10, #DDRC_PWRCTL] + + /* wait rw port_busy clear */ + ldr r6, =(0x1 << 16) + orr r6, r6, #0x1 +2: + ldr r7, [r10, #DDRC_PSTAT] + ands r7, r7, r6 + bne 2b + + ldr r7, =0x1 + str r7, [r10, #DDRC_DBG1] + + ldr r6, =0x36000000 +11: + ldr r7, [r10, #DDRC_DBGCAM] + and r7, r7, r6 + cmp r7, r6 + bne 11b + + /* enter self-refresh bit 5 */ + ldr r7, =(0x1 << 5) + str r7, [r10, #DDRC_PWRCTL] + + /* wait until self-refresh mode entered */ +3: + ldr r7, [r10, #DDRC_STAT] + and r7, r7, #0x3 + cmp r7, #0x3 + bne 3b +4: + ldr r7, [r10, #DDRC_STAT] + ands r7, r7, #0x20 + beq 4b + + /* disable dram clk */ + ldr r7, [r10, #DDRC_PWRCTL] + orr r7, r7, #(1 << 3) + str r7, [r10, #DDRC_PWRCTL] + + /* + * TO1.1 adds feature of DDR pads power down, + * although TO1.0 has no such function, but it is + * NOT harmful to program GPR registers for TO1.0, + * it can avoid the logic of version check in idle + * thread. + */ + ldr r10, [r0, #PM_INFO_MX7D_IOMUXC_GPR_V_OFFSET] + ldr r7, =0xf0000 + str r7, [r10] + + /* delay 20us, measured by gpio */ + ldr r7, =20 +12: + subs r7, r7, #0x1 + bne 12b + + .endm + + /* r10 must be DDRC base address */ + .macro ddrc_exit_self_refresh + + cmp r5, #0x1 + ldreq r10, [r0, #PM_INFO_MX7D_IOMUXC_GPR_P_OFFSET] + ldrne r10, [r0, #PM_INFO_MX7D_IOMUXC_GPR_V_OFFSET] + + ldr r7, =0x0 + str r7, [r10] + + ldr r7, =20 +13: + subs r7, r7, #0x1 + bne 13b + + cmp r5, #0x1 + ldreq r10, [r0, #PM_INFO_MX7D_DDRC_P_OFFSET] + ldrne r10, [r0, #PM_INFO_MX7D_DDRC_V_OFFSET] + + ldr r7, =0x0 + str r7, [r10, #DDRC_DBG1] + + ldr r6, =0x30000000 +14: + ldr r7, [r10, #DDRC_DBGCAM] + and r7, r7, r6 + cmp r7, r6 + bne 14b + + /* let DDR out of self-refresh */ + ldr r7, =0x0 + str r7, [r10, #DDRC_PWRCTL] + + /* wait until self-refresh mode exited */ +5: + ldr r7, [r10, #DDRC_STAT] + and r7, r7, #0x3 + cmp r7, #0x3 + beq 5b + + /* enable auto self-refresh */ + ldr r7, [r10, #DDRC_PWRCTL] + orr r7, r7, #(1 << 0) + str r7, [r10, #DDRC_PWRCTL] + + ldr r7, =0x1 + str r7, [r10, #DDRC_PCTRL_0] + + .endm + + .macro pll_do_wait_lock +6: + ldr r7, [r10, r8] + ands r7, #0x80000000 + beq 6b + + .endm + + .macro ccm_enter_idle + + ldr r10, [r0, #PM_INFO_MX7D_ANATOP_V_OFFSET] + + /* ungate pfd1 332m for lower axi */ + ldr r7, =0x8000 + str r7, [r10, #0xc8] + + ldr r10, [r0, #PM_INFO_MX7D_CCM_V_OFFSET] + + /* switch ARM CLK to OSC */ + ldr r8, =0x8000 + ldr r7, [r10, r8] + bic r7, r7, #0x7000000 + str r7, [r10, r8] + + /* lower AXI clk from 24MHz to 3MHz */ + ldr r8, =0x8800 + ldr r7, [r10, r8] + orr r7, r7, #0x7 + str r7, [r10, r8] + + /* lower AHB clk from 24MHz to 3MHz */ + ldr r8, =0x9000 + ldr r7, [r10, r8] + orr r7, r7, #0x7 + str r7, [r10, r8] + + /* gate dram clk */ + ldr r8, =0x9880 + ldr r7, [r10, r8] + bic r7, r7, #0x10000000 + str r7, [r10, r8] + + ldr r10, [r0, #PM_INFO_MX7D_ANATOP_V_OFFSET] + + /* gate pfd1 332m */ + ldr r7, =0x8000 + str r7, [r10, #0xc4] + + /* gate system pll pfd div 1 */ + ldr r7, =0x10 + str r7, [r10, #0xb4] + /* power down ARM, 480 and DRAM PLL */ + ldr r7, =0x1000 + str r7, [r10, #0x64] + str r7, [r10, #0xb4] + ldr r7, =0x100000 + str r7, [r10, #0x74] + + .endm + + .macro ccm_exit_idle + + cmp r5, #0x1 + ldreq r10, [r0, #PM_INFO_MX7D_ANATOP_P_OFFSET] + ldrne r10, [r0, #PM_INFO_MX7D_ANATOP_V_OFFSET] + + /* power up ARM, 480 and DRAM PLL */ + ldr r7, =0x1000 + str r7, [r10, #0x68] + ldr r8, =0x60 + pll_do_wait_lock + + ldr r7, =0x1000 + str r7, [r10, #0xb8] + ldr r8, =0xb0 + pll_do_wait_lock + + ldr r7, =0x100000 + str r7, [r10, #0x78] + ldr r8, =0x70 + pll_do_wait_lock + + /* ungate pfd1 332m for lower axi */ + ldr r7, =0x8000 + str r7, [r10, #0xc8] + + /* ungate system pll pfd div 1 */ + ldr r7, =0x10 + str r7, [r10, #0xb8] + + cmp r5, #0x1 + ldreq r10, [r0, #PM_INFO_MX7D_CCM_P_OFFSET] + ldrne r10, [r0, #PM_INFO_MX7D_CCM_V_OFFSET] + + /* switch ARM CLK to PLL */ + ldr r8, =0x8000 + ldr r7, [r10, r8] + orr r7, r7, #0x1000000 + str r7, [r10, r8] + + /* restore AXI clk from 3MHz to 24MHz */ + ldr r8, =0x8800 + ldr r7, [r10, r8] + bic r7, r7, #0x7 + str r7, [r10, r8] + + /* restore AHB clk from 3MHz to 24MHz */ + ldr r8, =0x9000 + ldr r7, [r10, r8] + bic r7, r7, #0x7 + str r7, [r10, r8] + + /* ungate dram clk */ + ldr r8, =0x9880 + ldr r7, [r10, r8] + orr r7, r7, #0x10000000 + str r7, [r10, r8] + + cmp r5, #0x1 + ldreq r10, [r0, #PM_INFO_MX7D_ANATOP_P_OFFSET] + ldrne r10, [r0, #PM_INFO_MX7D_ANATOP_V_OFFSET] + + /* gate pfd1 332m for lower axi */ + ldr r7, =0x8000 + str r7, [r10, #0xc4] + + .endm + + .macro anatop_enter_idle + + ldr r10, [r0, #PM_INFO_MX7D_ANATOP_V_OFFSET] + + /* XTAL to RC-OSC switch */ + ldr r7, [r10] + orr r7, r7, #0x1000 + str r7, [r10] + /* power down XTAL */ + ldr r7, [r10] + orr r7, r7, #0x1 + str r7, [r10] + + /* enable weak 1P0A */ + ldr r7, [r10, #0x200] + orr r7, r7, #0x40000 + str r7, [r10, #0x200] + + /* disable LDO 1P0A */ + ldr r7, [r10, #0x200] + bic r7, r7, #0x1 + str r7, [r10, #0x200] + + /* disable LDO 1P0D */ + ldr r7, [r10, #0x210] + bic r7, r7, #0x1 + str r7, [r10, #0x210] + + /* disable LDO 1P2 */ + ldr r7, [r10, #0x220] + bic r7, r7, #0x1 + str r7, [r10, #0x220] + + /* switch to low power bandgap */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x400 + str r7, [r10, #0x270] + /* power down normal bandgap */ + orr r7, r7, #0x1 + str r7, [r10, #0x270] + + .endm + + .macro anatop_exit_idle + + cmp r5, #0x1 + ldreq r10, [r0, #PM_INFO_MX7D_ANATOP_P_OFFSET] + ldrne r10, [r0, #PM_INFO_MX7D_ANATOP_V_OFFSET] + + /* power on normal bandgap */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x1 + str r7, [r10, #0x270] + /* switch to normal bandgap */ + bic r7, r7, #0x400 + str r7, [r10, #0x270] + + /* enable LDO 1P2 */ + ldr r7, [r10, #0x220] + orr r7, r7, #0x1 + str r7, [r10, #0x220] +7: + ldr r7, [r10, #0x220] + ands r7, #0x20000 + beq 7b + + /* enable LDO 1P0D */ + ldr r7, [r10, #0x210] + orr r7, r7, #0x1 + str r7, [r10, #0x210] +8: + ldr r7, [r10, #0x210] + ands r7, #0x20000 + beq 8b + + /* enable LDO 1P0A */ + ldr r7, [r10, #0x200] + orr r7, r7, #0x1 + str r7, [r10, #0x200] +9: + ldr r7, [r10, #0x200] + ands r7, #0x20000 + beq 9b + /* disable weak 1P0A */ + ldr r7, [r10, #0x200] + bic r7, r7, #0x40000 + str r7, [r10, #0x200] + + /* power up XTAL and wait */ + ldr r7, [r10] + bic r7, r7, #0x1 + str r7, [r10] +10: + ldr r7, [r10] + ands r7, r7, #0x4 + beq 10b + /* RC-OSC to XTAL switch */ + ldr r7, [r10] + bic r7, r7, #0x1000 + str r7, [r10] + + .endm + +.extern iram_tlb_phys_addr + + .align 3 +ENTRY(imx7d_low_power_idle) + push {r0 - r12} + + /* get necessary info from pm_info */ + ldr r1, [r0, #PM_INFO_PBASE_OFFSET] + ldr r2, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET] + + /* + * counting the resume address in iram + * to set it in SRC register. + */ + ldr r5, =imx7d_low_power_idle + ldr r6, =wakeup + sub r6, r6, r5 + add r8, r1, r2 + add r3, r8, r6 + + /* r11 is cpu id */ + mrc p15, 0, r11, c0, c0, 5 + and r11, r11, #3 + cmp r11, #0x0 + ldreq r6, =MX7D_SRC_GPR1 + ldreq r7, =MX7D_SRC_GPR2 + ldrne r6, =MX7D_SRC_GPR3 + ldrne r7, =MX7D_SRC_GPR4 + /* store physical resume addr and pm_info address. */ + ldr r10, [r0, #PM_INFO_MX7D_SRC_V_OFFSET] + str r3, [r10, r6] + str r1, [r10, r7] + + disable_l1_dcache + + tlb_set_to_ocram + + /* check last to sleep */ + ldr r6, [r0, #PM_INFO_PM_INFO_NUM_ONLINE_CPUS_OFFSET] + ldr r7, [r0, #PM_INFO_PM_INFO_NUM_LPI_CPUS_OFFSET] + cmp r6, r7 + bne lpi_enter_done + + ddrc_enter_self_refresh + ccm_enter_idle + anatop_enter_idle + + ldr r10, [r0, #PM_INFO_MX7D_GIC_DIST_V_OFFSET] + ldr r7, =0x0 + ldr r8, =0x1000 + str r7, [r10, r8] + + ldr r10, [r0, #PM_INFO_MX7D_GPC_V_OFFSET] + ldr r4, [r10, #MX7D_GPC_IMR1] + ldr r5, [r10, #MX7D_GPC_IMR2] + ldr r6, [r10, #MX7D_GPC_IMR3] + ldr r7, [r10, #MX7D_GPC_IMR4] + + ldr r8, =0xffffffff + str r8, [r10, #MX7D_GPC_IMR1] + str r8, [r10, #MX7D_GPC_IMR2] + str r8, [r10, #MX7D_GPC_IMR3] + str r8, [r10, #MX7D_GPC_IMR4] + + /* + * enable the RBC bypass counter here + * to hold off the interrupts. RBC counter + * = 8 (240us). With this setting, the latency + * from wakeup interrupt to ARM power up + * is ~250uS. + */ + ldr r8, [r10, #0x14] + bic r8, r8, #(0x3f << 24) + orr r8, r8, #(0x8 << 24) + str r8, [r10, #0x14] + + /* enable the counter. */ + ldr r8, [r10, #0x14] + orr r8, r8, #(0x1 << 30) + str r8, [r10, #0x14] + + /* unmask all the GPC interrupts. */ + str r4, [r10, #MX7D_GPC_IMR1] + str r5, [r10, #MX7D_GPC_IMR2] + str r6, [r10, #MX7D_GPC_IMR3] + str r7, [r10, #MX7D_GPC_IMR4] + + /* + * now delay for a short while (30usec) + * ARM is at 24MHz at this point + * so a short loop should be enough. + * this delay is required to ensure that + * the RBC counter can start counting in + * case an interrupt is already pending + * or in case an interrupt arrives just + * as ARM is about to assert DSM_request. + */ + ldr r4, =5 +rbc_loop: + subs r4, r4, #0x1 + bne rbc_loop + +lpi_enter_done: + + imx_pen_unlock + + wfi + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + imx_pen_lock + + /* check first to wake */ + ldr r6, [r0, #PM_INFO_PM_INFO_NUM_ONLINE_CPUS_OFFSET] + ldr r7, [r0, #PM_INFO_PM_INFO_NUM_LPI_CPUS_OFFSET] + cmp r6, r7 + bne skip_lpi_flow + + ldr r5, =0x0 + anatop_exit_idle + ccm_exit_idle + ddrc_exit_self_refresh + + ldr r10, [r0, #PM_INFO_MX7D_GIC_DIST_V_OFFSET] + ldr r7, =0x1 + ldr r8, =0x1000 + str r7, [r10, r8] + +skip_lpi_flow: + tlb_back_to_ddr + +#ifdef CONFIG_SMP + /* Turn on SMP bit. */ + mrc p15, 0, r7, c1, c0, 1 + orr r7, r7, #0x40 + mcr p15, 0, r7, c1, c0, 1 + + isb +#endif + + /* enable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + orr r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + /* Restore registers */ + pop {r0 - r12} + mov pc, lr + +wakeup: + + /* invalidate L1 I-cache first */ + mov r1, #0x0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 6 + /* enable the Icache and branch prediction */ + mov r1, #0x1800 + mcr p15, 0, r1, c1, c0, 0 + isb + + imx_pen_lock + + /* check first to wake */ + ldr r6, [r0, #PM_INFO_PM_INFO_NUM_ONLINE_CPUS_OFFSET] + ldr r7, [r0, #PM_INFO_PM_INFO_NUM_LPI_CPUS_OFFSET] + cmp r6, r7 + bne wakeup_skip_lpi_flow + + ldr r5, =0x1 + anatop_exit_idle + ccm_exit_idle + ddrc_exit_self_refresh + +wakeup_skip_lpi_flow: + /* get physical resume address from pm_info. */ + ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + + /* Restore registers */ + mov pc, lr + .ltorg +ENDPROC(imx7d_low_power_idle) diff --git a/arch/arm/mach-imx/lpddr2_freq_imx6.S b/arch/arm/mach-imx/lpddr2_freq_imx6.S new file mode 100644 index 00000000000000..21179fb2cb7270 --- /dev/null +++ b/arch/arm/mach-imx/lpddr2_freq_imx6.S @@ -0,0 +1,618 @@ +/* + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "hardware.h" + +#define PL310_AUX_CTRL 0x104 +#define PL310_DCACHE_LOCKDOWN_BASE 0x900 +#define PL310_AUX_16WAY_BIT 0x10000 +#define PL310_LOCKDOWN_NBREGS 8 +#define PL310_LOCKDOWN_SZREG 4 +#define PL310_8WAYS_MASK 0x00FF +#define PL310_16WAYS_UPPERMASK 0xFF00 + +.globl imx6_lpddr2_freq_change_start +.globl imx6_lpddr2_freq_change_end + + .macro mx6sl_switch_to_24MHz + + /* + * Set MMDC clock to be sourced from PLL3. + * Ensure first periph2_clk2 is sourced from PLL3. + * Set the PERIPH2_CLK2_PODF to divide by 2. + */ + ldr r6, [r2, #0x14] + bic r6, r6, #0x7 + orr r6, r6, #0x1 + str r6, [r2, #0x14] + + /* Select PLL3 to source MMDC. */ + ldr r6, [r2, #0x18] + bic r6, r6, #0x100000 + str r6, [r2, #0x18] + + /* Swtich periph2_clk_sel to run from PLL3. */ + ldr r6, [r2, #0x14] + orr r6, r6, #0x4000000 + str r6, [r2, #0x14] + +periph2_clk_switch1: + ldr r6, [r2, #0x48] + cmp r6, #0 + bne periph2_clk_switch1 + + /* + * Need to clock gate the 528 PFDs before + * powering down PLL2. + * Only the PLL2_PFD2_400M should be ON + * at this time, so only clock gate that one. + */ + ldr r6, [r3, #0x100] + orr r6, r6, #0x800000 + str r6, [r3, #0x100] + + /* + * Set PLL2 to bypass state. We should be here + * only if MMDC is not sourced from PLL2. + */ + ldr r6, [r3, #0x30] + orr r6, r6, #0x10000 + str r6, [r3, #0x30] + + ldr r6, [r3, #0x30] + orr r6, r6, #0x1000 + str r6, [r3, #0x30] + + /* Ensure pre_periph2_clk_mux is set to pll2 */ + ldr r6, [r2, #0x18] + bic r6, r6, #0x600000 + str r6, [r2, #0x18] + + /* Set MMDC clock to be sourced from the bypassed PLL2. */ + ldr r6, [r2, #0x14] + bic r6, r6, #0x4000000 + str r6, [r2, #0x14] + +periph2_clk_switch2: + ldr r6, [r2, #0x48] + cmp r6, #0 + bne periph2_clk_switch2 + + /* + * Now move MMDC back to periph2_clk2 source. + * after selecting PLL2 as the option. + * Select PLL2 as the source. + */ + ldr r6, [r2, #0x18] + orr r6, r6, #0x100000 + str r6, [r2, #0x18] + + /* set periph2_clk2_podf to divide by 1. */ + ldr r6, [r2, #0x14] + bic r6, r6, #0x7 + str r6, [r2, #0x14] + + /* Now move periph2_clk to periph2_clk2 source */ + ldr r6, [r2, #0x14] + orr r6, r6, #0x4000000 + str r6, [r2, #0x14] + +periph2_clk_switch3: + ldr r6, [r2, #0x48] + cmp r6, #0 + bne periph2_clk_switch3 + + /* Now set the MMDC PODF back to 1.*/ + ldr r6, [r2, #0x14] + bic r6, r6, #0x38 + str r6, [r2, #0x14] + +mmdc_podf0: + ldr r6, [r2, #0x48] + cmp r6, #0 + bne mmdc_podf0 + + .endm + + .macro ddr_switch_400MHz + + /* Set MMDC divider first, in case PLL3 is at 480MHz. */ + ldr r6, [r3, #0x10] + and r6, r6, #0x10000 + cmp r6, #0x10000 + beq pll3_in_bypass + + /* Set MMDC divder to divide by 2. */ + ldr r6, [r2, #0x14] + bic r6, r6, #0x38 + orr r6, r6, #0x8 + str r6, [r2, #0x14] + +mmdc_podf: + ldr r6, [r2, #0x48] + cmp r6, #0 + bne mmdc_podf + +pll3_in_bypass: + /* + * Check if we are switching between + * 400Mhz <-> 100MHz.If so, we should + * try to source MMDC from PLL2_200M. + */ + cmp r1, #0 + beq not_low_bus_freq + + /* Ensure that MMDC is sourced from PLL2 mux first. */ + ldr r6, [r2, #0x14] + bic r6, r6, #0x4000000 + str r6, [r2, #0x14] + +periph2_clk_switch4: + ldr r6, [r2, #0x48] + cmp r6, #0 + bne periph2_clk_switch4 + +not_low_bus_freq: + /* Now ensure periph2_clk2_sel mux is set to PLL3 */ + ldr r6, [r2, #0x18] + bic r6, r6, #0x100000 + str r6, [r2, #0x18] + + /* Now switch MMDC to PLL3. */ + ldr r6, [r2, #0x14] + orr r6, r6, #0x4000000 + str r6, [r2, #0x14] + +periph2_clk_switch5: + ldr r6, [r2, #0x48] + cmp r6, #0 + bne periph2_clk_switch5 + + /* + * Check if PLL2 is already unlocked. + * If so do nothing with PLL2. + */ + cmp r1, #0 + beq pll2_already_on + + /* Now power up PLL2 and unbypass it. */ + ldr r6, [r3, #0x30] + bic r6, r6, #0x1000 + str r6, [r3, #0x30] + + /* Make sure PLL2 has locked.*/ +wait_for_pll_lock: + ldr r6, [r3, #0x30] + and r6, r6, #0x80000000 + cmp r6, #0x80000000 + bne wait_for_pll_lock + + ldr r6, [r3, #0x30] + bic r6, r6, #0x10000 + str r6, [r3, #0x30] + + /* + * Need to enable the 528 PFDs after + * powering up PLL2. + * Only the PLL2_PFD2_400M should be ON + * as it feeds the MMDC. Rest should have + * been managed by clock code. + */ + ldr r6, [r3, #0x100] + bic r6, r6, #0x800000 + str r6, [r3, #0x100] + +pll2_already_on: + /* + * Now switch MMDC clk back to pll2_mux option. + * Ensure pre_periph2_clk2 is set to pll2_pfd_400M. + * If switching to audio DDR freq, set the + * pre_periph2_clk2 to PLL2_PFD_200M + */ + ldr r6, =400000000 + cmp r6, r0 + bne use_pll2_pfd_200M + + ldr r6, [r2, #0x18] + bic r6, r6, #0x600000 + orr r6, r6, #0x200000 + str r6, [r2, #0x18] + ldr r6, =400000000 + b cont2 + +use_pll2_pfd_200M: + ldr r6, [r2, #0x18] + orr r6, r6, #0x600000 + str r6, [r2, #0x18] + ldr r6, =200000000 + +cont2: + ldr r4, [r2, #0x14] + bic r4, r4, #0x4000000 + str r4, [r2, #0x14] + +periph2_clk_switch6: + ldr r4, [r2, #0x48] + cmp r4, #0 + bne periph2_clk_switch6 + +change_divider_only: + /* + * Calculate the MMDC divider + * based on the requested freq. + */ + ldr r4, =0 +Loop2: + sub r6, r6, r0 + cmp r6, r0 + blt Div_Found + add r4, r4, #1 + bgt Loop2 + + /* Shift divider into correct offset. */ + lsl r4, r4, #3 +Div_Found: + /* Set the MMDC PODF. */ + ldr r6, [r2, #0x14] + bic r6, r6, #0x38 + orr r6, r6, r4 + str r6, [r2, #0x14] + +mmdc_podf1: + ldr r6, [r2, #0x48] + cmp r6, #0 + bne mmdc_podf1 + + .endm + + .macro mmdc_clk_lower_100MHz + + /* + * Prior to reducing the DDR frequency (at 528/400 MHz), + * read the Measure unit count bits (MU_UNIT_DEL_NUM) + */ + ldr r5, =0x8B8 + ldr r6, [r8, r5] + /* Original MU unit count */ + mov r6, r6, LSR #16 + ldr r4, =0x3FF + and r6, r6, r4 + /* Original MU unit count * 2 */ + mov r7, r6, LSL #1 + /* + * Bypass the automatic measure unit when below 100 MHz + * by setting the Measure unit bypass enable bit (MU_BYP_EN) + */ + ldr r6, [r8, r5] + orr r6, r6, #0x400 + str r6, [r8, r5] + /* + * Double the measure count value read in step 1 and program it in the + * measurement bypass bits (MU_BYP_VAL) of the MMDC PHY Measure Unit + * Register for the reduced frequency operation below 100 MHz + */ + ldr r6, [r8, r5] + ldr r4, =0x3FF + bic r6, r6, r4 + orr r6, r6, r7 + str r6, [r8, r5] + + .endm + + .macro mmdc_clk_above_100MHz + + /* Make sure that the PHY measurement unit is NOT in bypass mode */ + ldr r5, =0x8B8 + ldr r6, [r8, r5] + bic r6, r6, #0x400 + str r6, [r8, r5] + /* Now perform a Force Measurement. */ + ldr r6, [r8, r5] + orr r6, r6, #0x800 + str r6, [r8, r5] + /* Wait for FRC_MSR to clear. */ +force_measure1: + ldr r6, [r8, r5] + and r6, r6, #0x800 + cmp r6, #0x0 + bne force_measure1 + .endm + +/* + * mx6_lpddr2_freq_change + * + * Make sure DDR is in self-refresh. + * IRQs are already disabled. + * r0 : DDR freq. + * r1: low_bus_freq_mode flag + */ + .align 3 +ENTRY(mx6_lpddr2_freq_change) +imx6_lpddr2_freq_change_start: + push {r4-r10} + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + dsb + isb + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Disable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + +#ifdef CONFIG_CACHE_L2X0 + /* + * Need to make sure the buffers in L2 are drained. + * Performing a sync operation does this. + */ + ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + + /* Wait for background operations to complete. */ +wait_for_l2_to_idle: + ldr r6, [r7, #0x730] + cmp r6, #0x0 + bne wait_for_l2_to_idle + + mov r6, #0x0 + str r6, [r7, #0x730] + + /* + * The second dsb might be needed to keep cache sync (device write) + * ordering with the memory accesses before it. + */ + dsb + isb + + ldr r3, [r7, #PL310_AUX_CTRL] + tst r3, #PL310_AUX_16WAY_BIT + mov r3, #PL310_8WAYS_MASK + orrne r3, #PL310_16WAYS_UPPERMASK + mov r6, #PL310_LOCKDOWN_NBREGS + add r5, r7, #PL310_DCACHE_LOCKDOWN_BASE +1: /* lock Dcache and Icache */ + str r3, [r5], #PL310_LOCKDOWN_SZREG + str r3, [r5], #PL310_LOCKDOWN_SZREG + subs r6, r6, #1 + bne 1b +#endif + + ldr r3, =IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR) + ldr r2, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR) + ldr r8, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR) + + /* Disable Automatic power savings. */ + ldr r6, [r8, #0x404] + orr r6, r6, #0x01 + str r6, [r8, #0x404] + + /* MMDC0_MDPDC disable power down timer */ + ldr r6, [r8, #0x4] + bic r6, r6, #0xff00 + str r6, [r8, #0x4] + + /* Delay for a while */ + ldr r10, =10 +delay1: + ldr r7, =0 +cont1: + ldr r6, [r8, r7] + add r7, r7, #4 + cmp r7, #16 + bne cont1 + sub r10, r10, #1 + cmp r10, #0 + bgt delay1 + + /* Make the DDR explicitly enter self-refresh. */ + ldr r6, [r8, #0x404] + orr r6, r6, #0x200000 + str r6, [r8, #0x404] + +poll_dvfs_set_1: + ldr r6, [r8, #0x404] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + bne poll_dvfs_set_1 + + /* set SBS step-by-step mode */ + ldr r6, [r8, #0x410] + orr r6, r6, #0x100 + str r6, [r8, #0x410] + + ldr r10, =100000000 + cmp r0, r10 + bgt set_ddr_mu_above_100 + mmdc_clk_lower_100MHz + +set_ddr_mu_above_100: + ldr r10, =24000000 + cmp r0, r10 + beq set_to_24MHz + + ddr_switch_400MHz + + ldr r10,=100000000 + cmp r0, r10 + blt done + mmdc_clk_above_100MHz + + b done + +set_to_24MHz: + mx6sl_switch_to_24MHz + +done: + /* clear DVFS - exit from self refresh mode */ + ldr r6, [r8, #0x404] + bic r6, r6, #0x200000 + str r6, [r8, #0x404] + +poll_dvfs_clear_1: + ldr r6, [r8, #0x404] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + beq poll_dvfs_clear_1 + + /* Enable Automatic power savings. */ + ldr r6, [r8, #0x404] + bic r6, r6, #0x01 + str r6, [r8, #0x404] + + ldr r10, =24000000 + cmp r0, r10 + beq skip_power_down + + /* Enable MMDC power down timer. */ + ldr r6, [r8, #0x4] + orr r6, r6, #0x5500 + str r6, [r8, #0x4] + +skip_power_down: + /* clear SBS - unblock DDR accesses */ + ldr r6, [r8, #0x410] + bic r6, r6, #0x100 + str r6, [r8, #0x410] + +#ifdef CONFIG_CACHE_L2X0 + ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + ldr r3, [r7, #PL310_AUX_CTRL] + tst r3, #PL310_AUX_16WAY_BIT + mov r6, #PL310_LOCKDOWN_NBREGS + mov r3, #0x00 /* 8 ways mask */ + orrne r3, #0x0000 /* 16 ways mask */ + add r5, r7, #PL310_DCACHE_LOCKDOWN_BASE +1: /* lock Dcache and Icache */ + str r3, [r5], #PL310_LOCKDOWN_SZREG + str r3, [r5], #PL310_LOCKDOWN_SZREG + subs r6, r6, #1 + bne 1b +#endif + + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + pop {r4-r10} + + /* Restore registers */ + mov pc, lr + + /* + * Add ltorg here to ensure that all + * literals are stored here and are + * within the text space. + */ + .ltorg +imx6_lpddr2_freq_change_end: diff --git a/arch/arm/mach-imx/lpddr2_freq_imx6q.S b/arch/arm/mach-imx/lpddr2_freq_imx6q.S new file mode 100644 index 00000000000000..6c9aac07df1619 --- /dev/null +++ b/arch/arm/mach-imx/lpddr2_freq_imx6q.S @@ -0,0 +1,765 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "hardware.h" + +#define CCM_CBCDR 0x14 +#define CCM_CBCMR 0x18 +#define CCM_CSCMR1 0x1c +#define CCM_CDHIPR 0x48 + +.globl mx6q_lpddr2_freq_change_start +.globl mx6q_lpddr2_freq_change_end + + .macro wait_for_ccm_handshake + /* wait for div update */ +1: + ldr r9, [r2, #CCM_CDHIPR] + cmp r9, #0 + bne 1b + + .endm + + .macro set_mmdc_misc_ralat_2_cycles + + /* Set MMDCx_MISC[RALAT] = 2 cycles */ + ldr r6, [r8, #0x18] + bic r6, r6, #(0x7 << 6) + orr r6, r6, #(0x2 << 6) + str r6, [r8, #0x18] + + /* Check if lpddr2 channel 1 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq 1f + + ldr r6, [r4, #0x18] + bic r6, r6, #(0x7 << 6) + orr r6, r6, #(0x2 << 6) + str r6, [r4, #0x18] +1: + .endm + + .macro switch_to_400MHz + /* set the MMDC_DIV=1, AXI_DIV=2, AHB_DIV=3 */ + ldr r9, [r2, #CCM_CBCDR] + ldr r6, =0x3f1f00 + bic r9, r9, r6 + orr r9, r9, #(0x9 << 8) + orr r9, r9, #(1 << 16) + str r9, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* check periph_clk_sel */ + ldr r9, [r2, #CCM_CBCDR] + and r9, r9, #(1 << 25) + cmp r9, #(1 << 25) + bne skip_periph_clk_switch_400m + + /* now switch periph_clk back. */ + ldr r9, [r2, #CCM_CBCDR] + bic r9, r9, #(1 << 25) + str r9, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + +skip_periph_clk_switch_400m: + + .endm + + .macro switch_to_100MHz + /* set the MMDC_DIV=4, AXI_DIV=8, AHB_DIV=8 */ + ldr r9, [r2, #CCM_CBCDR] + ldr r6, =0x3f1f00 + bic r9, r9, r6 + orr r9, r9, #(0x1F << 16) + orr r9, r9, #(0x1D << 8) + str r9, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* check if periph_clk_sel is already set. */ + ldr r9, [r2, #CCM_CBCDR] + and r9, r9, #(1 << 25) + cmp r9, #(1 << 25) + bne skip_periph_clk_switch_100m + + /* now switch periph_clk back. */ + ldr r9, [r2, #CCM_CBCDR] + bic r9, r9, #(1 << 25) + str r9, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + +skip_periph_clk_switch_100m: + + .endm + + .macro switch_to_24MHz + /* + * change the freq now try setting DDR to 24MHz. + * source it from the periph_clk2 ensure the + * periph_clk2 is sourced from 24MHz and the + * divider is 1. + */ + + ldr r9, [r2, #CCM_CBCMR] + bic r9, r9, #(0x3 << 12) + orr r9, r9, #(1 << 12) + str r9, [r2, #CCM_CBCMR] + + ldr r9, [r2, #CCM_CBCDR] + bic r9, r9, #(0x7 << 27) + str r9, [r2, #CCM_CBCDR] + + /* now switch periph_clk to 24MHz. */ + ldr r9, [r2, #CCM_CBCDR] + orr r9, r9, #(1 << 25) + str r9, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* change all the dividers to 1. */ + ldr r9, [r2, #CCM_CBCDR] + ldr r6, =0x3f1f00 + bic r9, r9, r6 + orr r9, r9, #(1 << 8) + str r9, [r2, #CCM_CBCDR] + + /* Wait for the divider to change. */ + wait_for_ccm_handshake + + .endm + + .macro switch_to_24MHZ_from_pll2 + /* Change DDR freq settings from pll2_pfd2 (div 2) */ + + ldr r9, [r2, #CCM_CBCMR] + bic r9, r9, #(0x3 << 18) + orr r9, r9, #(0x3 << 18) + str r9, [r2, #CCM_CBCMR] + + ldr r9, [r2, #CCM_CBCDR] + bic r9, r9, #(1 << 25) + str r9, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + ldr r9, [r2, #CCM_CBCDR] + ldr r6, =0x3f1f00 + bic r9, r9, r6 + orr r9, r9, #(1 << 8) + orr r9, r9, #(0x7 << 19) + str r9, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro set_timings_below_100MHz_operation + set_mmdc_misc_ralat_2_cycles + + /* Adjust LPDDR2 timings for 24Mhz operation */ + ldr r5, =0x03162073 + str r5, [r8, #0xC] /* MMDC0_MDCFG0 */ + ldr r7, =0x00020482 + str r7, [r8, #0x10] /* MMDC0_MDCFG1 */ + ldr r9, =0x00000049 + str r9, [r8, #0x14] /* MMDC0_MDCFG2 */ + ldr r10, =0x00020333 + str r10, [r8, #0x38] /* MMDC0_MDCFG3LP */ + + /* Check if lpddr2 channel 1 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq skip_below_100Mhz_ch1_timings + + str r5, [r4, #0xC] /* MMDC1_MDCFG0 */ + str r7, [r4, #0x10] /* MMDC1_MDCFG1 */ + str r9, [r4, #0x14] /* MMDC1_MDCFG2 */ + str r10, [r4, #0x38] /* MMDC1_MDCFG3LP */ + +skip_below_100Mhz_ch1_timings: + + .endm + + .macro restore_mmdc_settings_info + /* restore timing from mmdc_settings_info */ + ldr r6, [r1, #0x0] + ldr r7, [r1, #0x4] +1: + ldr r9, [r7], #0x4 + ldr r10, [r7], #0x4 + str r10, [r8, r9] + subs r6, r6, #0x1 + bne 1b + + /* Check if lpddr2 channel 1 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq 3f + + ldr r6, [r1, #0x0] + ldr r7, [r1, #0x4] +2: + ldr r9, [r7], #0x4 + ldr r10, [r7], #0x4 + str r10, [r4, r9] + subs r6, r6, #0x1 + bne 2b +3: + + .endm + + .macro mmdc_clk_lower_equal_100MHz + + ldr r10, =100000000 + cmp r0, r10 + beq set_timmings_100MHz + set_timings_below_100MHz_operation + b common_to_lower_equal_100MHz + +set_timmings_100MHz: + restore_mmdc_settings_info + set_mmdc_misc_ralat_2_cycles + +common_to_lower_equal_100MHz: + + /* if MMDC is not in 400MHz mode, skip double mu count */ + ldr r5, [r1, #0x8] + ldr r6, =400000000 + cmp r5, r6 + bne skip_lower_force_measure_ch1 + + /* + * Prior to reducing the DDR frequency (at 528/400 MHz), + * read the Measure unit count bits (MU_UNIT_DEL_NUM) + */ + ldr r5, =0x8B8 + ldr r6, [r8, r5] + /* Original MU unit count */ + mov r6, r6, LSR #16 + ldr r9, =0x3FF + and r6, r6, r9 + /* Original MU unit count * 2 */ + mov r7, r6, LSL #1 + /* + * Bypass the automatic measure unit when below 100 MHz + * by setting the Measure unit bypass enable bit (MU_BYP_EN) + */ + ldr r6, [r8, r5] + orr r6, r6, #0x400 + str r6, [r8, r5] + /* + * Double the measure count value read in step 1 and program it in the + * measurement bypass bits (MU_BYP_VAL) of the MMDC PHY Measure Unit + * Register for the reduced frequency operation below 100 MHz + */ + ldr r6, [r8, r5] + ldr r9, =0x3FF + bic r6, r6, r9 + orr r6, r6, r7 + str r6, [r8, r5] + /* Now perform a Force Measurement. */ + ldr r6, [r8, r5] + orr r6, r6, #0x800 + str r6, [r8, r5] + /* Wait for FRC_MSR to clear. */ +force_measure: + ldr r6, [r8, r5] + and r6, r6, #0x800 + cmp r6, #0x0 + bne force_measure + + /* Check if lpddr2 channel 2 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq skip_lower_force_measure_ch1 + + ldr r5, =0x8B8 + ldr r6, [r4, r5] + /* Original MU unit count */ + mov r6, r6, LSR #16 + ldr r9, =0x3FF + and r6, r6, r9 + /* Original MU unit count * 2 */ + mov r7, r6, LSL #1 + /* + * Bypass the automatic measure unit when below 100 MHz + * by setting the Measure unit bypass enable bit (MU_BYP_EN) + */ + ldr r6, [r4, r5] + orr r6, r6, #0x400 + str r6, [r4, r5] + /* + * Double the measure count value read in step 1 and program it in the + * measurement bypass bits (MU_BYP_VAL) of the MMDC PHY Measure Unit + * Register for the reduced frequency operation below 100 MHz + */ + ldr r6, [r4, r5] + ldr r9, =0x3FF + bic r6, r6, r9 + orr r6, r6, r7 + str r6, [r4, r5] + /* Now perform a Force Measurement. */ + ldr r6, [r4, r5] + orr r6, r6, #0x800 + str r6, [r4, r5] + /* Wait for FRC_MSR to clear. */ +force_measure_ch1: + ldr r6, [r4, r5] + and r6, r6, #0x800 + cmp r6, #0x0 + bne force_measure_ch1 + +skip_lower_force_measure_ch1: + + .endm + + .macro mmdc_clk_above_100MHz + + restore_mmdc_settings_info + + /* Make sure that the PHY measurement unit is NOT in bypass mode */ + ldr r5, =0x8B8 + ldr r6, [r8, r5] + bic r6, r6, #0x400 + str r6, [r8, r5] + /* Now perform a Force Measurement. */ + ldr r6, [r8, r5] + orr r6, r6, #0x800 + str r6, [r8, r5] + /* Wait for FRC_MSR to clear. */ +force_measure1: + ldr r6, [r8, r5] + and r6, r6, #0x800 + cmp r6, #0x0 + bne force_measure1 + + /* Check if lpddr2 channel 2 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq skip_above_force_measure_ch1 + + ldr r5, =0x8B8 + ldr r6, [r4, r5] + bic r6, r6, #0x400 + str r6, [r4, r5] + /* Now perform a Force Measurement. */ + ldr r6, [r4, r5] + orr r6, r6, #0x800 + str r6, [r4, r5] + /* Wait for FRC_MSR to clear. */ +force_measure1_ch1: + ldr r6, [r4, r5] + and r6, r6, #0x800 + cmp r6, #0x0 + bne force_measure1_ch1 + +skip_above_force_measure_ch1: + + .endm + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r11, lr} + + ldr r7, =v7_flush_kern_cache_all + mov lr, pc + mov pc, r7 + pop {r0 - r11, lr} + + /* disable d-cache */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + dsb + isb + + push {r0 - r11, lr} + + ldr r7, =v7_flush_kern_cache_all + mov lr, pc + mov pc, r7 + pop {r0 - r11, lr} + + .endm + +/* + * mx6_lpddr2_freq_change + * + * Make sure DDR is in self-refresh. + * IRQs are already disabled. + * r0 : DDR freq. + * r1 : mmdc_settings_info + */ + .align 3 +ENTRY(mx6q_lpddr2_freq_change) +mx6q_lpddr2_freq_change_start: + push {r2-r10} + + /* + * Need to flush and disable L1 before + * disabling L2, we need data to + * coherent. Flushing L1 pushes + * everyhting to L2. We sync L2 later, but + * it can still have dirty lines. + * While exiting, we need to enable L2 first + * and then L1. + */ + disable_l1_dcache + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + +#ifdef CONFIG_CACHE_L2X0 + /* + * Need to make sure the buffers in L2 are drained. + * Performing a sync operation does this. + */ + ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + + /* Wait for background operations to complete. */ +wait_for_l2_to_idle: + ldr r6, [r7, #0x730] + cmp r6, #0x0 + bne wait_for_l2_to_idle + + mov r6, #0x0 + str r6, [r7, #0x730] + + /* + * The second dsb might be needed to keep cache sync (device write) + * ordering with the memory accesses before it. + */ + dsb + isb + + /* Disable L2. */ + str r6, [r7, #0x100] +#endif + + ldr r3, =IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR) + ldr r2, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR) + ldr r8, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR) + ldr r4, =IMX_IO_P2V(MX6Q_MMDC_P1_BASE_ADDR) + + /* Disable Automatic power savings. */ + ldr r6, [r8, #0x404] + orr r6, r6, #0x01 + str r6, [r8, #0x404] + + /* MMDC0_MDPDC disable power down timer */ + ldr r6, [r8, #0x4] + bic r6, r6, #0xff00 + str r6, [r8, #0x4] + + /* Check if lpddr2 channel 2 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq skip_psd_ch1 + + ldr r6, [r4, #0x404] + orr r6, r6, #0x01 + str r6, [r4, #0x404] + + ldr r6, [r4, #0x4] + bic r6, r6, #0xff00 + str r6, [r4, #0x4] + +skip_psd_ch1: + /* Delay for a while */ + ldr r10, =10 +delay1: + ldr r7, =0 +cont1: + ldr r6, [r8, r7] + add r7, r7, #4 + cmp r7, #16 + bne cont1 + sub r10, r10, #1 + cmp r10, #0 + bgt delay1 + + /* Make the DDR explicitly enter self-refresh. */ + ldr r6, [r8, #0x404] + orr r6, r6, #0x200000 + str r6, [r8, #0x404] + +poll_dvfs_set_1: + ldr r6, [r8, #0x404] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + bne poll_dvfs_set_1 + + /* set SBS step-by-step mode */ + ldr r6, [r8, #0x410] + orr r6, r6, #0x100 + str r6, [r8, #0x410] + + /* Check if lpddr2 channel 2 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq skip_sbs_ch1 + + ldr r6, [r4, #0x404] + orr r6, r6, #0x200000 + str r6, [r4, #0x404] + +poll_dvfs_set_2: + ldr r6, [r4, #0x404] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + bne poll_dvfs_set_2 + + ldr r6, [r4, #0x410] + orr r6, r6, #0x100 + str r6, [r4, #0x410] + +skip_sbs_ch1: + ldr r10, =100000000 + cmp r0, r10 + bgt set_ddr_mu_above_100 + mmdc_clk_lower_equal_100MHz + +set_ddr_mu_above_100: + ldr r10, =24000000 + cmp r0, r10 + beq set_to_24MHz + + ldr r10, =100000000 + cmp r0, r10 + beq set_to_100MHz + + ldr r10, =400000000 + cmp r0, r10 + switch_to_400MHz + b done + +set_to_24MHz: +/* + switch_to_24MHZ_from_pll2 +*/ + switch_to_24MHz + b done + +set_to_100MHz: + switch_to_100MHz + +done: + + ldr r10,=100000000 + cmp r0, r10 + ble skip_mmdc_clk_check + mmdc_clk_above_100MHz + +skip_mmdc_clk_check: + + /* clear DVFS - exit from self refresh mode */ + ldr r6, [r8, #0x404] + bic r6, r6, #0x200000 + str r6, [r8, #0x404] + +poll_dvfs_clear_1: + ldr r6, [r8, #0x404] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + beq poll_dvfs_clear_1 + + /* Enable Automatic power savings. */ + ldr r6, [r8, #0x404] + bic r6, r6, #0x01 + str r6, [r8, #0x404] + + /* Check if lpddr2 channel 2 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq skip_enable_psd_ch1 + + ldr r6, [r4, #0x404] + bic r6, r6, #0x200000 + str r6, [r4, #0x404] + +poll_dvfs_clear_2: + ldr r6, [r4, #0x404] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + beq poll_dvfs_clear_2 + + ldr r6, [r4, #0x404] + bic r6, r6, #0x01 + str r6, [r4, #0x404] + +skip_enable_psd_ch1: + ldr r10, =24000000 + cmp r0, r10 + beq skip_power_down + + /* Enable MMDC power down timer. */ + ldr r6, [r8, #0x4] + orr r6, r6, #0x5500 + str r6, [r8, #0x4] + + /* Check if lpddr2 channel 2 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq skip_power_down + + ldr r6, [r4, #0x4] + orr r6, r6, #0x5500 + str r6, [r4, #0x4] + +skip_power_down: + /* clear SBS - unblock DDR accesses */ + ldr r6, [r8, #0x410] + bic r6, r6, #0x100 + str r6, [r8, #0x410] + + /* Check if lpddr2 channel 2 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq skip_disable_sbs_ch1 + + ldr r6, [r4, #0x410] + bic r6, r6, #0x100 + str r6, [r4, #0x410] + +skip_disable_sbs_ch1: +#ifdef CONFIG_CACHE_L2X0 + /* Enable L2. */ + ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + ldr r6, =0x1 + str r6, [r7, #0x100] +#endif + + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + pop {r2-r10} + + /* Restore registers */ + mov pc, lr + + /* + * Add ltorg here to ensure that all + * literals are stored here and are + * within the text space. + */ + .ltorg +mx6q_lpddr2_freq_change_end: diff --git a/arch/arm/mach-imx/lpddr2_freq_imx6sll.S b/arch/arm/mach-imx/lpddr2_freq_imx6sll.S new file mode 100644 index 00000000000000..c67d9e2b82efe1 --- /dev/null +++ b/arch/arm/mach-imx/lpddr2_freq_imx6sll.S @@ -0,0 +1,460 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "hardware.h" + +#define CCM_CBCDR 0x14 +#define CCM_CBCMR 0x18 +#define CCM_CSCMR1 0x1c +#define CCM_CDHIPR 0x48 + +#define L2_CACHE_SYNC 0x730 +#define PL310_AUX_CTRL 0x104 +#define PL310_DCACHE_LOCKDOWN_BASE 0x900 +#define PL310_AUX_16WAY_BIT 0x10000 +#define PL310_LOCKDOWN_NBREGS 8 +#define PL310_LOCKDOWN_SZREG 4 +#define PL310_8WAYS_MASK 0x00FF +#define PL310_16WAYS_UPPERMASK 0xFF00 + +#define MMDC0_MDPDC 0x4 +#define MMDC0_MAPSR 0x404 +#define MMDC0_MADPCR0 0x410 + +#define HIGH_BUS_MODE 0x0 + + .macro wait_for_ccm_handshake + +1: + ldr r8, [r2, #CCM_CDHIPR] + cmp r8, #0 + bne 1b + + .endm + + .macro switch_to_24MHz + + /* periph2_clk2 sel to OSC_CLK */ + ldr r8, [r2, #CCM_CBCMR] + orr r8, r8, #(1 << 20) + str r8, [r2, #CCM_CBCMR] + + /* periph2_clk2_podf to 0 */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #0x7 + str r8, [r2, #CCM_CBCDR] + + /* periph2_clk sel to periph2_clk2 */ + ldr r8, [r2, #CCM_CBCDR] + orr r8, r8, #(0x1 << 26) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* fabric_mmdc_podf to 0 */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(0x7 << 3) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro switch_to_100MHz + + /* check whether periph2_clk is from top path */ + ldr r8, [r2, #CCM_CBCDR] + ands r8, #(1 << 26) + beq skip_periph2_clk2_switch_100m + + /* now switch periph2_clk back. */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(1 << 26) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* + * on i.MX6SLL, pre_periph2_clk will be always from + * pll2_pfd2, so no need to set pre_periph2_clk + * parent, just set the mmdc divider directly. + */ +skip_periph2_clk2_switch_100m: + + /* fabric_mmdc_podf to 3 so that mmdc is 400 / 4 = 100MHz */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(0x7 << 3) + orr r8, r8, #(0x3 << 3) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro switch_to_400MHz + + /* check whether periph2_clk is from top path */ + ldr r8, [r2, #CCM_CBCDR] + ands r8, #(1 << 26) + beq skip_periph2_clk2_switch_400m + + /* now switch periph2_clk back. */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(1 << 26) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* + * on i.MX6SLL, pre_periph2_clk will be always from + * pll2_pfd2, so no need to set pre_periph2_clk + * parent, just set the mmdc divider directly. + */ +skip_periph2_clk2_switch_400m: + + /* fabric_mmdc_podf to 0 */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(0x7 << 3) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro mmdc_clk_lower_100MHz + /* if MMDC is not in 400MHz mode, skip double mu count */ + cmp r1, #HIGH_BUS_MODE + bne 1f + + /* + * Prior to reducing the DDR frequency (at 528/400 MHz), + * read the Measure unit count bits (MU_UNIT_DEL_NUM) + */ + ldr r8, =0x8B8 + ldr r6, [r5, r8] + /* Original MU unit count */ + mov r6, r6, LSR #16 + ldr r4, =0x3FF + and r6, r6, r4 + /* Original MU unit count * 2 */ + mov r7, r6, LSL #1 + /* + * Bypass the automatic measure unit when below 100 MHz + * by setting the Measure unit bypass enable bit (MU_BYP_EN) + */ + ldr r6, [r5, r8] + orr r6, r6, #0x400 + str r6, [r5, r8] + /* + * Double the measure count value read in step 1 and program it in the + * measurement bypass bits (MU_BYP_VAL) of the MMDC PHY Measure Unit + * Register for the reduced frequency operation below 100 MHz + */ + ldr r6, [r5, r8] + ldr r4, =0x3FF + bic r6, r6, r4 + orr r6, r6, r7 + str r6, [r5, r8] + + /* For freq lower than 100MHz, need to set RALAT to 2 */ + ldr r6, [r5, #0x18] + bic r6, r6, #(0x7 << 6) + orr r6, r6, #(0x2 << 6) + str r6, [r5, #0x18] +1: + .endm + + .macro mmdc_clk_above_100MHz + + /* Make sure that the PHY measurement unit is NOT in bypass mode */ + ldr r8, =0x8B8 + ldr r6, [r5, r8] + bic r6, r6, #0x400 + str r6, [r5, r8] + /* Now perform a Force Measurement. */ + ldr r6, [r5, r8] + orr r6, r6, #0x800 + str r6, [r5, r8] + /* Wait for FRC_MSR to clear. */ +force_measure1: + ldr r6, [r5, r8] + and r6, r6, #0x800 + cmp r6, #0x0 + bne force_measure1 + + /* For freq higher than 100MHz, need to set RALAT to 5 */ + ldr r6, [r5, #0x18] + bic r6, r6, #(0x7 << 6) + orr r6, r6, #(0x5 << 6) + str r6, [r5, #0x18] + + .endm + + .align 3 +/* + * Below code can be used by i.MX6SLL when changing the + * frequency of MMDC. the MMDC is the same on these two SOCs. + */ +ENTRY(imx6sll_lpddr2_freq_change) + push {r2 - r8} + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Disable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + +#ifdef CONFIG_CACHE_L2X0 + /* + * Need to make sure the buffers in L2 are drained. + * Performing a sync operation does this. + */ + ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + mov r6, #0x0 + str r6, [r7, #L2_CACHE_SYNC] + + /* + * The second dsb might be needed to keep cache sync (device write) + * ordering with the memory accesses before it. + */ + dsb + isb + + ldr r3, [r7, #PL310_AUX_CTRL] + tst r3, #PL310_AUX_16WAY_BIT + mov r3, #PL310_8WAYS_MASK + orrne r3, #PL310_16WAYS_UPPERMASK + mov r6, #PL310_LOCKDOWN_NBREGS + add r5, r7, #PL310_DCACHE_LOCKDOWN_BASE +1: /* lock Dcache and Icache */ + str r3, [r5], #PL310_LOCKDOWN_SZREG + str r3, [r5], #PL310_LOCKDOWN_SZREG + subs r6, r6, #1 + bne 1b +#endif + + ldr r2, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR) + ldr r3, =IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR) + ldr r5, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR) + + /* Disable Automatic power savings. */ + ldr r6, [r5, #MMDC0_MAPSR] + orr r6, r6, #0x1 + str r6, [r5, #MMDC0_MAPSR] + + /* Delay for a while */ + ldr r8, =10 +delay: + ldr r7, =0 +cont: + ldr r6, [r5, r7] + add r7, r7, #4 + cmp r7, #16 + bne cont + sub r8, r8, #1 + cmp r8, #0 + bgt delay + + /* Make the DDR explicitly enter self-refresh. */ + ldr r6, [r5, #MMDC0_MAPSR] + orr r6, r6, #0x200000 + str r6, [r5, #MMDC0_MAPSR] + +poll_dvfs_set_1: + ldr r6, [r5, #MMDC0_MAPSR] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + bne poll_dvfs_set_1 + + /* set SBS step-by-step mode */ + ldr r6, [r5, #MMDC0_MADPCR0] + orr r6, r6, #0x100 + str r6, [r5, #MMDC0_MADPCR0] + + ldr r6, =100000000 + cmp r0, r6 + bgt set_ddr_mu_above_100 + mmdc_clk_lower_100MHz + +set_ddr_mu_above_100: + ldr r6, =24000000 + cmp r0, r6 + beq set_to_24MHz + + ldr r6, =100000000 + cmp r0, r6 + beq set_to_100MHz + + switch_to_400MHz + + mmdc_clk_above_100MHz + + b done + +set_to_24MHz: + switch_to_24MHz + b done +set_to_100MHz: + switch_to_100MHz +done: + /* clear DVFS - exit from self refresh mode */ + ldr r6, [r5, #MMDC0_MAPSR] + bic r6, r6, #0x200000 + str r6, [r5, #MMDC0_MAPSR] + +poll_dvfs_clear_1: + ldr r6, [r5, #MMDC0_MAPSR] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + beq poll_dvfs_clear_1 + + /* Enable Automatic power savings. */ + ldr r6, [r5, #MMDC0_MAPSR] + bic r6, r6, #0x1 + str r6, [r5, #MMDC0_MAPSR] + + /* clear SBS - unblock DDR accesses */ + ldr r6, [r5, #MMDC0_MADPCR0] + bic r6, r6, #0x100 + str r6, [r5, #MMDC0_MADPCR0] + + ldr r6, =0xa0000000 + str r6, [r5, #0x83c] + + +#ifdef CONFIG_CACHE_L2X0 + ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + ldr r3, [r7, #PL310_AUX_CTRL] + tst r3, #PL310_AUX_16WAY_BIT + mov r6, #PL310_LOCKDOWN_NBREGS + mov r3, #0x00 /* 8 ways mask */ + orrne r3, #0x0000 /* 16 ways mask */ + add r5, r7, #PL310_DCACHE_LOCKDOWN_BASE +1: /* lock Dcache and Icache */ + str r3, [r5], #PL310_LOCKDOWN_SZREG + str r3, [r5], #PL310_LOCKDOWN_SZREG + subs r6, r6, #1 + bne 1b +#endif + + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + /* Restore registers */ + pop {r2 - r8} + mov pc, lr diff --git a/arch/arm/mach-imx/lpddr2_freq_imx6sx.S b/arch/arm/mach-imx/lpddr2_freq_imx6sx.S new file mode 100644 index 00000000000000..ba3488cad9d4fa --- /dev/null +++ b/arch/arm/mach-imx/lpddr2_freq_imx6sx.S @@ -0,0 +1,492 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "hardware.h" + +#define CCM_CBCDR 0x14 +#define CCM_CBCMR 0x18 +#define CCM_CSCMR1 0x1c +#define CCM_CDHIPR 0x48 + +#define L2_CACHE_SYNC 0x730 +#define PL310_AUX_CTRL 0x104 +#define PL310_DCACHE_LOCKDOWN_BASE 0x900 +#define PL310_AUX_16WAY_BIT 0x10000 +#define PL310_LOCKDOWN_NBREGS 8 +#define PL310_LOCKDOWN_SZREG 4 +#define PL310_8WAYS_MASK 0x00FF +#define PL310_16WAYS_UPPERMASK 0xFF00 + +#define MMDC0_MDPDC 0x4 +#define MMDC0_MAPSR 0x404 +#define MMDC0_MADPCR0 0x410 + +#define HIGH_BUS_MODE 0x0 + + /* Check if the cpu is cortex-a7 */ + .macro is_ca7 + + /* Read the primary cpu number is MPIDR */ + mrc p15, 0, r6, c0, c0, 0 + ldr r7, =0xfff0 + and r6, r6, r7 + ldr r7, =0xc070 + cmp r6, r7 + + .endm + + .macro wait_for_ccm_handshake + +1: + ldr r8, [r2, #CCM_CDHIPR] + cmp r8, #0 + bne 1b + + .endm + + .macro switch_to_24MHz + + /* periph2_clk2 sel to OSC_CLK */ + ldr r8, [r2, #CCM_CBCMR] + orr r8, r8, #(1 << 20) + str r8, [r2, #CCM_CBCMR] + + /* periph2_clk2_podf to 0 */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #0x7 + str r8, [r2, #CCM_CBCDR] + + /* periph2_clk sel to periph2_clk2 */ + ldr r8, [r2, #CCM_CBCDR] + orr r8, r8, #(0x1 << 26) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* fabric_mmdc_podf to 0 */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(0x7 << 3) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro switch_to_100MHz + + /* check whether periph2_clk is from top path */ + ldr r8, [r2, #CCM_CBCDR] + ands r8, #(1 << 26) + beq skip_periph2_clk2_switch_100m + + /* now switch periph2_clk back. */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(1 << 26) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* + * on i.MX6SX, pre_periph2_clk will be always from + * pll2_pfd2, so no need to set pre_periph2_clk + * parent, just set the mmdc divider directly. + */ +skip_periph2_clk2_switch_100m: + + /* fabric_mmdc_podf to 3 so that mmdc is 400 / 4 = 100MHz */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(0x7 << 3) + orr r8, r8, #(0x3 << 3) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro switch_to_400MHz + + /* check whether periph2_clk is from top path */ + ldr r8, [r2, #CCM_CBCDR] + ands r8, #(1 << 26) + beq skip_periph2_clk2_switch_400m + + /* now switch periph2_clk back. */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(1 << 26) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* + * on i.MX6SX, pre_periph2_clk will be always from + * pll2_pfd2, so no need to set pre_periph2_clk + * parent, just set the mmdc divider directly. + */ +skip_periph2_clk2_switch_400m: + + /* fabric_mmdc_podf to 0 */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(0x7 << 3) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro mmdc_clk_lower_100MHz + /* if MMDC is not in 400MHz mode, skip double mu count */ + cmp r1, #HIGH_BUS_MODE + bne 1f + + /* + * Prior to reducing the DDR frequency (at 528/400 MHz), + * read the Measure unit count bits (MU_UNIT_DEL_NUM) + */ + ldr r8, =0x8B8 + ldr r6, [r5, r8] + /* Original MU unit count */ + mov r6, r6, LSR #16 + ldr r4, =0x3FF + and r6, r6, r4 + /* Original MU unit count * 2 */ + mov r7, r6, LSL #1 + /* + * Bypass the automatic measure unit when below 100 MHz + * by setting the Measure unit bypass enable bit (MU_BYP_EN) + */ + ldr r6, [r5, r8] + orr r6, r6, #0x400 + str r6, [r5, r8] + /* + * Double the measure count value read in step 1 and program it in the + * measurement bypass bits (MU_BYP_VAL) of the MMDC PHY Measure Unit + * Register for the reduced frequency operation below 100 MHz + */ + ldr r6, [r5, r8] + ldr r4, =0x3FF + bic r6, r6, r4 + orr r6, r6, r7 + str r6, [r5, r8] + + /* For freq lower than 100MHz, need to set RALAT to 2 */ + ldr r6, [r5, #0x18] + bic r6, r6, #(0x7 << 6) + orr r6, r6, #(0x2 << 6) + str r6, [r5, #0x18] +1: + .endm + + .macro mmdc_clk_above_100MHz + + /* Make sure that the PHY measurement unit is NOT in bypass mode */ + ldr r8, =0x8B8 + ldr r6, [r5, r8] + bic r6, r6, #0x400 + str r6, [r5, r8] + /* Now perform a Force Measurement. */ + ldr r6, [r5, r8] + orr r6, r6, #0x800 + str r6, [r5, r8] + /* Wait for FRC_MSR to clear. */ +force_measure1: + ldr r6, [r5, r8] + and r6, r6, #0x800 + cmp r6, #0x0 + bne force_measure1 + + /* For freq higher than 100MHz, need to set RALAT to 5 */ + ldr r6, [r5, #0x18] + bic r6, r6, #(0x7 << 6) + orr r6, r6, #(0x5 << 6) + str r6, [r5, #0x18] + + .endm + + .align 3 +/* + * Below code can be used by i.MX6SX and i.MX6UL when changing the + * frequency of MMDC. the MMDC is the same on these two SOCs. + */ +ENTRY(imx6_up_lpddr2_freq_change) + + push {r2 - r8} + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Disable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + is_ca7 + beq skip_disable_l2 + +#ifdef CONFIG_CACHE_L2X0 + /* + * Need to make sure the buffers in L2 are drained. + * Performing a sync operation does this. + */ + ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + mov r6, #0x0 + str r6, [r7, #L2_CACHE_SYNC] + + /* + * The second dsb might be needed to keep cache sync (device write) + * ordering with the memory accesses before it. + */ + dsb + isb + + ldr r3, [r7, #PL310_AUX_CTRL] + tst r3, #PL310_AUX_16WAY_BIT + mov r3, #PL310_8WAYS_MASK + orrne r3, #PL310_16WAYS_UPPERMASK + mov r6, #PL310_LOCKDOWN_NBREGS + add r5, r7, #PL310_DCACHE_LOCKDOWN_BASE +1: /* lock Dcache and Icache */ + str r3, [r5], #PL310_LOCKDOWN_SZREG + str r3, [r5], #PL310_LOCKDOWN_SZREG + subs r6, r6, #1 + bne 1b +#endif + +skip_disable_l2: + ldr r2, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR) + ldr r3, =IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR) + ldr r5, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR) + + /* Disable Automatic power savings. */ + ldr r6, [r5, #MMDC0_MAPSR] + orr r6, r6, #0x1 + str r6, [r5, #MMDC0_MAPSR] + + /* MMDC0_MDPDC disable power down timer */ + ldr r6, [r5, #MMDC0_MDPDC] + bic r6, r6, #0xff00 + str r6, [r5, #MMDC0_MDPDC] + + /* Delay for a while */ + ldr r8, =10 +delay: + ldr r7, =0 +cont: + ldr r6, [r5, r7] + add r7, r7, #4 + cmp r7, #16 + bne cont + sub r8, r8, #1 + cmp r8, #0 + bgt delay + + /* Make the DDR explicitly enter self-refresh. */ + ldr r6, [r5, #MMDC0_MAPSR] + orr r6, r6, #0x200000 + str r6, [r5, #MMDC0_MAPSR] + +poll_dvfs_set_1: + ldr r6, [r5, #MMDC0_MAPSR] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + bne poll_dvfs_set_1 + + /* set SBS step-by-step mode */ + ldr r6, [r5, #MMDC0_MADPCR0] + orr r6, r6, #0x100 + str r6, [r5, #MMDC0_MADPCR0] + + ldr r6, =100000000 + cmp r0, r6 + bgt set_ddr_mu_above_100 + mmdc_clk_lower_100MHz + +set_ddr_mu_above_100: + ldr r6, =24000000 + cmp r0, r6 + beq set_to_24MHz + + ldr r6, =100000000 + cmp r0, r6 + beq set_to_100MHz + + switch_to_400MHz + + mmdc_clk_above_100MHz + + b done + +set_to_24MHz: + switch_to_24MHz + b done +set_to_100MHz: + switch_to_100MHz +done: + /* clear DVFS - exit from self refresh mode */ + ldr r6, [r5, #MMDC0_MAPSR] + bic r6, r6, #0x200000 + str r6, [r5, #MMDC0_MAPSR] + +poll_dvfs_clear_1: + ldr r6, [r5, #MMDC0_MAPSR] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + beq poll_dvfs_clear_1 + + /* Enable Automatic power savings. */ + ldr r6, [r5, #MMDC0_MAPSR] + bic r6, r6, #0x1 + str r6, [r5, #MMDC0_MAPSR] + + ldr r6, =24000000 + cmp r0, r6 + beq skip_power_down + + /* Enable MMDC power down timer. */ + ldr r6, [r5, #MMDC0_MDPDC] + orr r6, r6, #0x5500 + str r6, [r5, #MMDC0_MDPDC] + +skip_power_down: + /* clear SBS - unblock DDR accesses */ + ldr r6, [r5, #MMDC0_MADPCR0] + bic r6, r6, #0x100 + str r6, [r5, #MMDC0_MADPCR0] + + is_ca7 + beq skip_enable_l2 + +#ifdef CONFIG_CACHE_L2X0 + ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + ldr r3, [r7, #PL310_AUX_CTRL] + tst r3, #PL310_AUX_16WAY_BIT + mov r6, #PL310_LOCKDOWN_NBREGS + mov r3, #0x00 /* 8 ways mask */ + orrne r3, #0x0000 /* 16 ways mask */ + add r5, r7, #PL310_DCACHE_LOCKDOWN_BASE +1: /* lock Dcache and Icache */ + str r3, [r5], #PL310_LOCKDOWN_SZREG + str r3, [r5], #PL310_LOCKDOWN_SZREG + subs r6, r6, #1 + bne 1b +#endif + +skip_enable_l2: + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + /* Restore registers */ + pop {r2 - r8} + mov pc, lr diff --git a/arch/arm/mach-imx/lpddr3_freq_imx.S b/arch/arm/mach-imx/lpddr3_freq_imx.S new file mode 100644 index 00000000000000..80fb1184fa547a --- /dev/null +++ b/arch/arm/mach-imx/lpddr3_freq_imx.S @@ -0,0 +1,444 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "hardware.h" + +#define DDRC_MSTR 0x0 +#define DDRC_STAT 0x4 +#define DDRC_PWRCTL 0x30 +#define DDRC_RFSHTMG 0x64 +#define DDRC_DBG1 0x304 +#define DDRC_PSTAT 0x3fc +#define DDRC_PCTRL_0 0x490 +#define DDRC_DFIMISC 0x1b0 +#define DDRC_DBGCAM 0x308 +#define DDRC_SWCTL 0x320 +#define DDRC_SWSTAT 0x324 +#define DDRPHY_LP_CON0 0x18 +#define IOMUXC_GPR8 0x20 +#define DDRPHY_PHY_CON1 0x4 +#define DDRPHY_MDLL_CON0 0xb0 +#define DDRPHY_MDLL_CON1 0xb4 +#define DDRPHY_OFFSETD_CON0 0x50 +#define DDRPHY_OFFSETR_CON0 0x20 +#define DDRPHY_OFFSETR_CON1 0x24 +#define DDRPHY_OFFSETR_CON2 0x28 +#define DDRPHY_OFFSETW_CON0 0x30 +#define DDRPHY_OFFSETW_CON1 0x34 +#define DDRPHY_OFFSETW_CON2 0x38 +#define DDRPHY_RFSHTMG 0x64 +#define DDRPHY_CA_WLDSKEW_CON0 0x6c +#define DDRPHY_CA_DSKEW_CON0 0x7c +#define DDRPHY_CA_DSKEW_CON1 0x80 +#define DDRPHY_CA_DSKEW_CON2 0x84 + +#define ANADIG_DIGPROG 0x800 + + .align 3 + + .macro ddrc_prepare + + /* disable port */ + ldr r7, =0x0 + str r7, [r4, #DDRC_PCTRL_0] + + /* wait port busy done */ + ldr r6, =0x10001 +1: + ldr r7, [r4, #DDRC_PSTAT] + and r7, r7, r6 + cmp r7, #0 + bne 1b + + ldr r7, =0x20 + str r7, [r4, #DDRC_PWRCTL] + + ldr r6, =0x23 +2: + ldr r7, [r4, #DDRC_STAT] + and r7, r7, r6 + cmp r7, r6 + bne 2b + + ldr r7, =0x1 + str r7, [r4, #DDRC_DBG1] + + ldr r6, =0x30000000 +3: + ldr r7, [r4, #DDRC_DBGCAM] + and r7, r7, r6 + cmp r7, r6 + bne 3b + + ldr r7, =0x0 + str r7, [r4, #DDRC_SWCTL] + + ldr r7, =0x0 + str r7, [r4, #DDRC_DFIMISC] + + ldr r7, =0x1 + str r7, [r4, #DDRC_SWCTL] + + ldr r6, =0x1 +4: + ldr r7, [r4, #DDRC_SWSTAT] + and r7, r7, r6 + cmp r7, r6 + bne 4b + + .endm + + .macro ddrc_done + + ldr r7, =0x0 + str r7, [r4, #DDRC_PWRCTL] + + ldr r6, =0x3 +5: + ldr r7, [r4, #DDRC_STAT] + and r7, r7, r6 + cmp r7, r6 + beq 5b + + ldr r7, =0x0 + str r7, [r4, #DDRC_DBG1] + + ldr r7, =0x1 + str r7, [r4, #DDRC_PCTRL_0] + + /* enable auto self-refresh */ + ldr r7, [r4, #DDRC_PWRCTL] + orr r7, r7, #(1 << 0) + str r7, [r4, #DDRC_PWRCTL] + + .endm + + .macro switch_to_below_100m + + /* LPDDR2 and LPDDR3 has different setting */ + ldr r8, [r4, #DDRC_MSTR] + ands r8, r8, #0x4 + bne 9f + + /* LPDDR3 */ + ldr r7, =0x00000100 + str r7, [r5, #DDRPHY_PHY_CON1] + b 10f +9: + /* LPDDR2 */ + ldr r7, =0x10010100 + str r7, [r5, #DDRPHY_PHY_CON1] +10: + ldr r6, =24000000 + cmp r0, r6 + beq 16f + + ldr r7, =0x0005000B + str r7, [r4, #DDRC_RFSHTMG] + b 6f +16: + ldr r7, =0x00010003 + str r7, [r4, #DDRC_RFSHTMG] + + /* dram alt sel set to OSC */ + ldr r7, =0x10000000 + ldr r8, =0xa080 + str r7, [r2, r8] + /* dram root set to from dram alt, div by 1 */ + ldr r7, =0x11000000 + ldr r8, =0x9880 + str r7, [r2, r8] + b 7f + +6: + /* dram alt sel set to pfd0_392m */ + ldr r7, =0x15000000 + ldr r8, =0xa080 + str r7, [r2, r8] + /* dram root set to from dram alt, div by 4 */ + ldr r7, =0x11000003 + ldr r8, =0x9880 + str r7, [r2, r8] +7: + ldr r7, =0x202ffd0 + str r7, [r5, #DDRPHY_MDLL_CON0] + + ldr r7, =0x7f + str r7, [r5, #DDRPHY_OFFSETD_CON0] + + ldr r7, =0x7f7f7f7f + str r7, [r5, #DDRPHY_OFFSETR_CON0] + str r7, [r5, #DDRPHY_OFFSETR_CON1] + ldr r7, =0x7f + str r7, [r5, #DDRPHY_OFFSETR_CON2] + + ldr r7, =0x7f7f7f7f + str r7, [r5, #DDRPHY_OFFSETW_CON0] + str r7, [r5, #DDRPHY_OFFSETW_CON1] + ldr r7, =0x7f + str r7, [r5, #DDRPHY_OFFSETW_CON2] + + ldr r7, [r9, #ANADIG_DIGPROG] + and r7, r7, #0x11 + cmp r7, #0x11 + bne 11f + + ldr r7, =0x0 + str r7, [r5, #DDRPHY_CA_WLDSKEW_CON0] + ldr r7, =0x60606060 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + ldr r7, =0x00006060 + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] + b 12f +11: + ldr r7, =0x0 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] +12: + ldr r7, =0x100007f + str r7, [r5, #DDRPHY_OFFSETD_CON0] + ldr r7, =0x7f + str r7, [r5, #DDRPHY_OFFSETD_CON0] + + .endm + + .macro switch_to_533m + + ldr r7, =0x10210100 + str r7, [r5, #DDRPHY_PHY_CON1] + + ldr r7, =0x00200038 + str r7, [r4, #DDRC_RFSHTMG] + + /* dram root set to from dram main, div by 2 */ + ldr r7, =0x10000001 + ldr r8, =0x9880 + str r7, [r2, r8] + + ldr r7, =0x1010007e + str r7, [r5, #DDRPHY_MDLL_CON0] + + ldr r7, =0x10000008 + str r7, [r5, #DDRPHY_OFFSETD_CON0] + + ldr r7, =0x08080808 + str r7, [r5, #DDRPHY_OFFSETR_CON0] + str r7, [r5, #DDRPHY_OFFSETR_CON1] + ldr r7, =0x8 + str r7, [r5, #DDRPHY_OFFSETR_CON2] + + ldr r7, =0x08080808 + str r7, [r5, #DDRPHY_OFFSETW_CON0] + str r7, [r5, #DDRPHY_OFFSETW_CON1] + ldr r7, =0x8 + str r7, [r5, #DDRPHY_OFFSETW_CON2] + + /* LPDDR2 and LPDDR3 has different setting */ + ldr r8, [r4, #DDRC_MSTR] + ands r8, r8, #0x4 + beq 15f + + ldr r7, [r9, #ANADIG_DIGPROG] + and r7, r7, #0x11 + cmp r7, #0x11 + bne 14f + + ldr r7, =0x08080808 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + ldr r7, =0x0a0a0808 + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] + ldr r7, =0x0a0a0a0a + str r7, [r5, #DDRPHY_CA_WLDSKEW_CON0] + b 14f +15: + ldr r7, [r9, #ANADIG_DIGPROG] + and r7, r7, #0x11 + cmp r7, #0x11 + bne 13f + + ldr r7, =0x1c1c1c1c + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + ldr r7, =0x30301c1c + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] + ldr r7, =0x30303030 + str r7, [r5, #DDRPHY_CA_WLDSKEW_CON0] + b 14f +13: + ldr r7, =0x08080808 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + ldr r7, =0x0808 + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] +14: + ldr r7, =0x11000008 + str r7, [r5, #DDRPHY_OFFSETD_CON0] + ldr r7, =0x10000008 + str r7, [r5, #DDRPHY_OFFSETD_CON0] + + ldr r6, =0x4 +8: + ldr r7, [r5, #DDRPHY_MDLL_CON1] + and r7, r7, r6 + cmp r7, r6 + bne 8b + + .endm + +ENTRY(imx_lpddr3_freq_change) + push {r2 - r9} + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Disable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + ldr r2, =IMX_IO_P2V(MX7D_CCM_BASE_ADDR) + ldr r3, =IMX_IO_P2V(MX7D_IOMUXC_GPR_BASE_ADDR) + ldr r4, =IMX_IO_P2V(MX7D_DDRC_BASE_ADDR) + ldr r5, =IMX_IO_P2V(MX7D_DDRC_PHY_BASE_ADDR) + ldr r9, =IMX_IO_P2V(MX7D_ANATOP_BASE_ADDR) + + ddrc_prepare + + ldr r6, =100000000 + cmp r0, r6 + bgt set_to_533m + +set_to_below_100m: + switch_to_below_100m + b done + +set_to_533m: + switch_to_533m + b done + +done: + ddrc_done + + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + /* Restore registers */ + pop {r2 - r9} + mov pc, lr +ENDPROC(imx_lpddr3_freq_change) diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index edd26e0ffeec78..730ce83eee0efc 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -106,6 +106,18 @@ static int ar8031_phy_fixup(struct phy_device *dev) { u16 val; + /* Set RGMII IO voltage to 1.8V */ + phy_write(dev, 0x1d, 0x1f); + phy_write(dev, 0x1e, 0x8); + + /* disable phy AR8031 SmartEEE function. */ + phy_write(dev, 0xd, 0x3); + phy_write(dev, 0xe, 0x805d); + phy_write(dev, 0xd, 0x4003); + val = phy_read(dev, 0xe); + val &= ~(0x1 << 8); + phy_write(dev, 0xe, val); + /* To enable AR8031 output a 125MHz clk from CLK_25M */ phy_write(dev, 0xd, 0x7); phy_write(dev, 0xe, 0x8016); @@ -223,6 +235,58 @@ static void __init imx6q_1588_init(void) of_node_put(np); } +static void __init imx6q_csi_mux_init(void) +{ + /* + * MX6Q SabreSD board: + * IPU1 CSI0 connects to parallel interface. + * Set GPR1 bit 19 to 0x1. + * + * MX6DL SabreSD board: + * IPU1 CSI0 connects to parallel interface. + * Set GPR13 bit 0-2 to 0x4. + * IPU1 CSI1 connects to MIPI CSI2 virtual channel 1. + * Set GPR13 bit 3-5 to 0x1. + */ + struct regmap *gpr; + + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) { + if (of_machine_is_compatible("fsl,imx6q-sabresd") || + of_machine_is_compatible("fsl,imx6q-sabreauto") || + of_machine_is_compatible("fsl,imx6qp-sabresd") || + of_machine_is_compatible("fsl,imx6qp-sabreauto")) + regmap_update_bits(gpr, IOMUXC_GPR1, 1 << 19, 1 << 19); + else if (of_machine_is_compatible("fsl,imx6dl-sabresd") || + of_machine_is_compatible("fsl,imx6dl-sabreauto")) + regmap_update_bits(gpr, IOMUXC_GPR13, 0x3F, 0x0C); + } else { + pr_err("%s(): failed to find fsl,imx6q-iomux-gpr regmap\n", + __func__); + } +} + +static void __init imx6q_enet_clk_sel(void) +{ + struct regmap *gpr; + + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) + regmap_update_bits(gpr, IOMUXC_GPR5, + IMX6Q_GPR5_ENET_TX_CLK_SEL, IMX6Q_GPR5_ENET_TX_CLK_SEL); + else + pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n"); +} + +static inline void imx6q_enet_init(void) +{ + imx6_enet_mac_init("fsl,imx6q-fec", "fsl,imx6q-ocotp"); + imx6q_enet_phy_init(); + imx6q_1588_init(); + if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) + imx6q_enet_clk_sel(); +} + static void __init imx6q_axi_init(void) { struct regmap *gpr; @@ -260,7 +324,7 @@ static void __init imx6q_init_machine(void) { struct device *parent; - if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) + if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0); else imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", @@ -270,13 +334,12 @@ static void __init imx6q_init_machine(void) if (parent == NULL) pr_warn("failed to initialize soc device\n"); - imx6q_enet_phy_init(); - of_platform_default_populate(NULL, NULL, parent); imx_anatop_init(); + imx6q_enet_init(); + imx6q_csi_mux_init(); cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init(); - imx6q_1588_init(); imx6q_axi_init(); } @@ -300,6 +363,8 @@ static void __init imx6q_map_io(void) { debug_ll_io_init(); imx_scu_map_io(); + imx6_pm_map_io(); + imx_busfreq_map_io(); } static void __init imx6q_init_irq(void) diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c index e00818abe54dfd..d1c6a9fa826a98 100644 --- a/arch/arm/mach-imx/mach-imx6sl.c +++ b/arch/arm/mach-imx/mach-imx6sl.c @@ -16,7 +16,7 @@ #include "cpuidle.h" #include "hardware.h" -static void __init imx6sl_fec_init(void) +static void __init imx6sl_fec_clk_init(void) { struct regmap *gpr; @@ -32,6 +32,12 @@ static void __init imx6sl_fec_init(void) } } +static inline void imx6sl_fec_init(void) +{ + imx6sl_fec_clk_init(); + imx6_enet_mac_init("fsl,imx6sl-fec", "fsl,imx6sl-ocotp"); +} + static void __init imx6sl_init_late(void) { /* imx6sl reuses imx6q cpufreq driver */ @@ -41,7 +47,7 @@ static void __init imx6sl_init_late(void) if (IS_ENABLED(CONFIG_SOC_IMX6SL) && cpu_is_imx6sl()) imx6sl_cpuidle_init(); else if (IS_ENABLED(CONFIG_SOC_IMX6SLL)) - imx6sx_cpuidle_init(); + imx6sll_cpuidle_init(); } static void __init imx6sl_init_machine(void) @@ -54,6 +60,7 @@ static void __init imx6sl_init_machine(void) of_platform_default_populate(NULL, NULL, parent); + imx_anatop_init(); if (cpu_is_imx6sl()) imx6sl_fec_init(); imx_anatop_init(); @@ -73,6 +80,14 @@ static void __init imx6sl_init_irq(void) imx6_pm_ccm_init("fsl,imx6sll-ccm"); } +static void __init imx6sl_map_io(void) +{ + imx6_pm_map_io(); +#ifdef CONFIG_CPU_FREQ + imx_busfreq_map_io(); +#endif +} + static const char * const imx6sl_dt_compat[] __initconst = { "fsl,imx6sl", "fsl,imx6sll", @@ -82,6 +97,7 @@ static const char * const imx6sl_dt_compat[] __initconst = { DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)") .l2c_aux_val = 0, .l2c_aux_mask = ~0, + .map_io = imx6sl_map_io, .init_irq = imx6sl_init_irq, .init_machine = imx6sl_init_machine, .init_late = imx6sl_init_late, diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c index d5310bf307ffaa..118e9c9bb5a955 100644 --- a/arch/arm/mach-imx/mach-imx6sx.c +++ b/arch/arm/mach-imx/mach-imx6sx.c @@ -23,6 +23,14 @@ static int ar8031_phy_fixup(struct phy_device *dev) phy_write(dev, 0x1d, 0x1f); phy_write(dev, 0x1e, 0x8); + /* disable phy AR8031 SmartEEE function. */ + phy_write(dev, 0xd, 0x3); + phy_write(dev, 0xe, 0x805d); + phy_write(dev, 0xd, 0x4003); + val = phy_read(dev, 0xe); + val &= ~(0x1 << 8); + phy_write(dev, 0xe, val); + /* introduce tx clock delay */ phy_write(dev, 0x1d, 0x5); val = phy_read(dev, 0x1e); @@ -57,6 +65,7 @@ static void __init imx6sx_enet_clk_sel(void) static inline void imx6sx_enet_init(void) { + imx6_enet_mac_init("fsl,imx6sx-fec", "fsl,imx6sx-ocotp"); imx6sx_enet_phy_init(); imx6sx_enet_clk_sel(); } @@ -71,6 +80,7 @@ static void __init imx6sx_init_machine(void) of_platform_default_populate(NULL, NULL, parent); + imx_anatop_init(); imx6sx_enet_init(); imx_anatop_init(); imx6sx_pm_init(); @@ -86,6 +96,13 @@ static void __init imx6sx_init_irq(void) imx6_pm_ccm_init("fsl,imx6sx-ccm"); } +static void __init imx6sx_map_io(void) +{ + debug_ll_io_init(); + imx6_pm_map_io(); + imx_busfreq_map_io(); +} + static void __init imx6sx_init_late(void) { imx6sx_cpuidle_init(); @@ -102,6 +119,7 @@ static const char * const imx6sx_dt_compat[] __initconst = { DT_MACHINE_START(IMX6SX, "Freescale i.MX6 SoloX (Device Tree)") .l2c_aux_val = 0, .l2c_aux_mask = ~0, + .map_io = imx6sx_map_io, .init_irq = imx6sx_init_irq, .init_machine = imx6sx_init_machine, .dt_compat = imx6sx_dt_compat, diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c index 311f5e4ff723f4..732f9419acd0a0 100644 --- a/arch/arm/mach-imx/mach-imx6ul.c +++ b/arch/arm/mach-imx/mach-imx6ul.c @@ -52,6 +52,7 @@ static inline void imx6ul_enet_init(void) { imx6ul_enet_clk_init(); imx6ul_enet_phy_init(); + imx6_enet_mac_init("fsl,imx6ul-fec", "fsl,imx6ul-ocotp"); } static void __init imx6ul_init_machine(void) @@ -63,6 +64,7 @@ static void __init imx6ul_init_machine(void) pr_warn("failed to initialize soc device\n"); of_platform_default_populate(NULL, NULL, parent); + imx_anatop_init(); imx6ul_enet_init(); imx_anatop_init(); imx6ul_pm_init(); @@ -78,12 +80,18 @@ static void __init imx6ul_init_irq(void) static void __init imx6ul_init_late(void) { - imx6sx_cpuidle_init(); + imx6ul_cpuidle_init(); if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); } +static void __init imx6ul_map_io(void) +{ + imx6_pm_map_io(); + imx_busfreq_map_io(); +} + static const char * const imx6ul_dt_compat[] __initconst = { "fsl,imx6ul", "fsl,imx6ull", @@ -91,6 +99,7 @@ static const char * const imx6ul_dt_compat[] __initconst = { }; DT_MACHINE_START(IMX6UL, "Freescale i.MX6 Ultralite (Device Tree)") + .map_io = imx6ul_map_io, .init_irq = imx6ul_init_irq, .init_machine = imx6ul_init_machine, .init_late = imx6ul_init_late, diff --git a/arch/arm/mach-imx/mach-imx7d.c b/arch/arm/mach-imx/mach-imx7d.c index ebb27592a9f754..7ad5e6f240ddfd 100644 --- a/arch/arm/mach-imx/mach-imx7d.c +++ b/arch/arm/mach-imx/mach-imx7d.c @@ -13,6 +13,13 @@ #include #include "common.h" +#include "cpuidle.h" + +static struct property device_disabled = { + .name = "status", + .length = sizeof("disabled"), + .value = "disabled", +}; static int ar8031_phy_fixup(struct phy_device *dev) { @@ -57,6 +64,23 @@ static void __init imx7d_enet_phy_init(void) } } +static void __init imx7d_enet_mdio_fixup(void) +{ + struct regmap *gpr; + + /* The management data input/output (MDIO) bus where often high-speed, + * open-drain operation is required. i.MX7D TO1.0 ENET MDIO pin has no + * open drain as IC ticket number: TKT252980, i.MX7D TO1.1 fix the issue. + * GPR1[8:7] are reserved bits at TO1.0, there no need to add version check. + */ + gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr"); + if (!IS_ERR(gpr)) + regmap_update_bits(gpr, IOMUXC_GPR0, IMX7D_GPR0_ENET_MDIO_OPEN_DRAIN_MASK, + IMX7D_GPR0_ENET_MDIO_OPEN_DRAIN_MASK); + else + pr_err("failed to find fsl,imx7d-iomux-gpr regmap\n"); +} + static void __init imx7d_enet_clk_sel(void) { struct regmap *gpr; @@ -72,10 +96,23 @@ static void __init imx7d_enet_clk_sel(void) static inline void imx7d_enet_init(void) { + imx6_enet_mac_init("fsl,imx7d-fec", "fsl,imx7d-ocotp"); + imx7d_enet_mdio_fixup(); imx7d_enet_phy_init(); imx7d_enet_clk_sel(); } +static inline void imx7d_disable_arm_arch_timer(void) +{ + struct device_node *node; + + node = of_find_compatible_node(NULL, NULL, "arm,armv7-timer"); + if (node) { + pr_info("disable arm arch timer for nosmp!\n"); + of_add_property(node, &device_disabled); + } +} + static void __init imx7d_init_machine(void) { struct device *parent; @@ -84,21 +121,36 @@ static void __init imx7d_init_machine(void) if (parent == NULL) pr_warn("failed to initialize soc device\n"); + imx_anatop_init(); + of_platform_default_populate(NULL, NULL, parent); + imx7d_pm_init(); imx_anatop_init(); imx7d_enet_init(); } static void __init imx7d_init_late(void) { + imx7d_cpuidle_init(); if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT)) platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0); } static void __init imx7d_init_irq(void) { + imx_gpcv2_check_dt(); imx_init_revision_from_anatop(); imx_src_init(); irqchip_init(); +#ifndef CONFIG_SMP + imx7d_disable_arm_arch_timer(); +#endif +} + +static void __init imx7d_map_io(void) +{ + debug_ll_io_init(); + imx7_pm_map_io(); + imx_busfreq_map_io(); } static const char *const imx7d_dt_compat[] __initconst = { @@ -108,6 +160,8 @@ static const char *const imx7d_dt_compat[] __initconst = { }; DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual (Device Tree)") + .map_io = imx7d_map_io, + .smp = smp_ops(imx_smp_ops), .init_irq = imx7d_init_irq, .init_machine = imx7d_init_machine, .init_late = imx7d_init_late, diff --git a/arch/arm/mach-imx/mach-imx7ulp.c b/arch/arm/mach-imx/mach-imx7ulp.c index 11ac71aaf965a4..419c7905fe0565 100644 --- a/arch/arm/mach-imx/mach-imx7ulp.c +++ b/arch/arm/mach-imx/mach-imx7ulp.c @@ -10,6 +10,7 @@ #include #include #include +#include #include "common.h" #include "cpuidle.h" @@ -17,6 +18,15 @@ #define SIM_JTAG_ID_REG 0x8c +/* static IO mapping, and ioremap() could always share the same mapping. */ +static struct map_desc mx7ulp_io_desc[] __initdata = { + mx7ulp_aips_map_entry(1, MT_DEVICE), + mx7ulp_aips_map_entry(2, MT_DEVICE), + mx7ulp_aips_map_entry(3, MT_DEVICE), + mx7ulp_aips_map_entry(4, MT_DEVICE), + mx7ulp_aips_map_entry(5, MT_DEVICE), +}; + static void __init imx7ulp_set_revision(void) { struct regmap *sim; @@ -65,12 +75,23 @@ static const char *const imx7ulp_dt_compat[] __initconst = { NULL, }; +static void __init imx7ulp_map_io(void) +{ + iotable_init(mx7ulp_io_desc, ARRAY_SIZE(mx7ulp_io_desc)); + imx7ulp_pm_map_io(); +} + static void __init imx7ulp_init_late(void) { + if (IS_ENABLED(CONFIG_ARM_IMX7ULP_CPUFREQ)) + platform_device_register_simple("imx7ulp-cpufreq", -1, NULL, 0); + imx7ulp_cpuidle_init(); + imx7ulp_enable_nmi(); } DT_MACHINE_START(IMX7ulp, "Freescale i.MX7ULP (Device Tree)") + .map_io = imx7ulp_map_io, .init_machine = imx7ulp_init_machine, .dt_compat = imx7ulp_dt_compat, .init_late = imx7ulp_init_late, diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c index 0dfd0ae7a63ddc..8599936fc00103 100644 --- a/arch/arm/mach-imx/mmdc.c +++ b/arch/arm/mach-imx/mmdc.c @@ -59,6 +59,7 @@ #define to_mmdc_pmu(p) container_of(p, struct mmdc_pmu, pmu) static int ddr_type; +static int lpddr2_2ch_mode; struct fsl_mmdc_devtype_data { unsigned int flags; @@ -575,6 +576,11 @@ int imx_mmdc_get_ddr_type(void) return ddr_type; } +int imx_mmdc_get_lpddr2_2ch_mode(void) +{ + return lpddr2_2ch_mode; +} + static struct platform_driver imx_mmdc_driver = { .driver = { .name = "imx-mmdc", diff --git a/arch/arm/mach-imx/mu.c b/arch/arm/mach-imx/mu.c new file mode 100644 index 00000000000000..1a250b07b25666 --- /dev/null +++ b/arch/arm/mach-imx/mu.c @@ -0,0 +1,434 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" +#include "hardware.h" + +#define MU_ATR0_OFFSET 0x0 +#define MU_ARR0_OFFSET 0x10 +#define MU_ARR1_OFFSET 0x14 +#define MU_ASR 0x20 +#define MU_ACR 0x24 +#define MX7ULP_MU_TR0 0x20 +#define MX7ULP_MU_RR0 0x40 +#define MX7ULP_MU_RR1 0x44 +#define MX7ULP_MU_SR 0x60 +#define MX7ULP_MU_CR 0x64 + +#define MU_LPM_HANDSHAKE_INDEX 0 +#define MU_RPMSG_HANDSHAKE_INDEX 1 +#define MU_LPM_BUS_HIGH_READY_FOR_M4 0xFFFF6666 +#define MU_LPM_M4_FREQ_CHANGE_READY 0xFFFF7777 +#define MU_LPM_M4_REQUEST_HIGH_BUS 0x2222CCCC +#define MU_LPM_M4_RELEASE_HIGH_BUS 0x2222BBBB +#define MU_LPM_M4_WAKEUP_SRC_VAL 0x55555000 +#define MU_LPM_M4_WAKEUP_SRC_MASK 0xFFFFF000 +#define MU_LPM_M4_WAKEUP_IRQ_MASK 0xFF0 +#define MU_LPM_M4_WAKEUP_IRQ_SHIFT 0x4 +#define MU_LPM_M4_WAKEUP_ENABLE_MASK 0xF +#define MU_LPM_M4_WAKEUP_ENABLE_SHIFT 0x0 + +#define MU_LPM_M4_RUN_MODE 0x5A5A0001 +#define MU_LPM_M4_WAIT_MODE 0x5A5A0002 +#define MU_LPM_M4_STOP_MODE 0x5A5A0003 + +#define MAX_NUM 10 /* enlarge it if overflow happen */ + +static void __iomem *mu_base; +static u32 m4_message[MAX_NUM]; +static u32 in_idx, out_idx; +static struct delayed_work mu_work; +static u32 m4_wake_irqs[4]; +static bool m4_freq_low; +struct irq_domain *domain; +static bool m4_in_stop; +static struct clk *clk; +static DEFINE_SPINLOCK(mu_lock); + +void imx_mu_set_m4_run_mode(void) +{ + m4_in_stop = false; +} + +bool imx_mu_is_m4_in_stop(void) +{ + return m4_in_stop; +} + +bool imx_mu_is_m4_in_low_freq(void) +{ + return m4_freq_low; +} + +void imx_mu_enable_m4_irqs_in_gic(bool enable) +{ + int i, j; + + for (i = 0; i < 4; i++) { + if (m4_wake_irqs[i] == 0) + continue; + for (j = 0; j < 32; j++) { + if (m4_wake_irqs[i] & (1 << j)) { + if (enable) + enable_irq(irq_find_mapping( + domain, i * 32 + j)); + else + disable_irq(irq_find_mapping( + domain, i * 32 + j)); + } + } + } +} + +static irqreturn_t mcc_m4_dummy_isr(int irq, void *param) +{ + return IRQ_HANDLED; +} + +static int imx_mu_send_message(unsigned int index, unsigned int data) +{ + u32 val, ep; + int i, te_flag = 0; + unsigned long timeout = jiffies + msecs_to_jiffies(500); + + /* wait for transfer buffer empty, and no event pending */ + do { + if (cpu_is_imx7ulp()) + val = readl_relaxed(mu_base + MX7ULP_MU_SR); + else + val = readl_relaxed(mu_base + MU_ASR); + ep = val & BIT(4); + if (time_after(jiffies, timeout)) { + pr_err("Waiting MU transmit buffer empty timeout!\n"); + return -EIO; + } + } while (((val & (1 << (20 + 3 - index))) == 0) || (ep == BIT(4))); + + if (cpu_is_imx7ulp()) + writel_relaxed(data, mu_base + index * 0x4 + MX7ULP_MU_TR0); + else + writel_relaxed(data, mu_base + index * 0x4 + MU_ATR0_OFFSET); + + /* + * make a double check that TEn is not empty after write + */ + if (cpu_is_imx7ulp()) + val = readl_relaxed(mu_base + MX7ULP_MU_SR); + else + val = readl_relaxed(mu_base + MU_ASR); + ep = val & BIT(4); + if (((val & (1 << (20 + (3 - index)))) == 0) || (ep == BIT(4))) + return 0; + else + te_flag = 1; + + /* + * Make sure that TEn flag is changed, after the ATRn is filled up. + */ + for (i = 0; i < 100; i++) { + if (cpu_is_imx7ulp()) + val = readl_relaxed(mu_base + MX7ULP_MU_SR); + else + val = readl_relaxed(mu_base + MU_ASR); + ep = val & BIT(4); + if (((val & (1 << (20 + 3 - index))) == 0) || (ep == BIT(4))) { + /* + * BUG here. TEn flag is changes, after the + * ATRn is filled with MSG for a while. + */ + te_flag = 0; + break; + } else if (time_after(jiffies, timeout)) { + /* Can't see TEn 1->0, maybe already handled! */ + te_flag = 1; + break; + } + } + if (te_flag == 0) + pr_info("BUG: TEn is not changed immediately" + "when ATRn is filled up.\n"); + + return 0; +} + +static void mu_work_handler(struct work_struct *work) +{ + int ret; + u32 irq, enable, idx, mask, virq; + struct of_phandle_args args; + u32 message; + unsigned long flags; + + spin_lock_irqsave(&mu_lock, flags); + message = m4_message[out_idx % MAX_NUM]; + spin_unlock_irqrestore(&mu_lock, flags); + + pr_debug("receive M4 message 0x%x\n", message); + + switch (message) { + case MU_LPM_M4_RUN_MODE: + case MU_LPM_M4_WAIT_MODE: + m4_in_stop = false; + break; + case MU_LPM_M4_STOP_MODE: + m4_in_stop = true; + break; + case MU_LPM_M4_REQUEST_HIGH_BUS: + request_bus_freq(BUS_FREQ_HIGH); +#ifdef CONFIG_SOC_IMX6SX + if (cpu_is_imx6sx()) + imx6sx_set_m4_highfreq(true); +#endif + imx_mu_send_message(MU_LPM_HANDSHAKE_INDEX, + MU_LPM_BUS_HIGH_READY_FOR_M4); + m4_freq_low = false; + break; + case MU_LPM_M4_RELEASE_HIGH_BUS: + release_bus_freq(BUS_FREQ_HIGH); +#ifdef CONFIG_SOC_IMX6SX + if (cpu_is_imx6sx()) { + imx6sx_set_m4_highfreq(false); + imx_mu_send_message(MU_LPM_HANDSHAKE_INDEX, + MU_LPM_M4_FREQ_CHANGE_READY); + } +#endif + m4_freq_low = true; + break; + default: + if ((message & MU_LPM_M4_WAKEUP_SRC_MASK) == + MU_LPM_M4_WAKEUP_SRC_VAL) { + irq = (message & MU_LPM_M4_WAKEUP_IRQ_MASK) >> + MU_LPM_M4_WAKEUP_IRQ_SHIFT; + + enable = (message & MU_LPM_M4_WAKEUP_ENABLE_MASK) >> + MU_LPM_M4_WAKEUP_ENABLE_SHIFT; + + /* to hwirq start from 0 */ + irq -= 32; + + idx = irq / 32; + mask = 1 << irq % 32; + + args.np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-gpc"); + args.args_count = 3; + args.args[0] = 0; + args.args[1] = irq; + args.args[2] = IRQ_TYPE_LEVEL_HIGH; + + virq = irq_create_of_mapping(&args); + + if (enable && can_request_irq(virq, 0)) { + ret = request_irq(virq, mcc_m4_dummy_isr, + IRQF_NO_SUSPEND, "imx-m4-dummy", NULL); + if (ret) { + pr_err("%s: register interrupt %d failed, rc %d\n", + __func__, virq, ret); + break; + } + disable_irq(virq); + m4_wake_irqs[idx] = m4_wake_irqs[idx] | mask; + } + imx_gpc_add_m4_wake_up_irq(irq, enable); + } + break; + } + + spin_lock_irqsave(&mu_lock, flags); + m4_message[out_idx % MAX_NUM] = 0; + out_idx++; + spin_unlock_irqrestore(&mu_lock, flags); + + /* enable RIE3 interrupt */ + if (cpu_is_imx7ulp()) + writel_relaxed(readl_relaxed(mu_base + MX7ULP_MU_CR) | BIT(27), + mu_base + MX7ULP_MU_CR); + else + writel_relaxed(readl_relaxed(mu_base + MU_ACR) | BIT(27), + mu_base + MU_ACR); +} + +int imx_mu_lpm_ready(bool ready) +{ + u32 val; + + if (cpu_is_imx7ulp()) { + val = readl_relaxed(mu_base + MX7ULP_MU_CR); + if (ready) + writel_relaxed(val | BIT(0), mu_base + MX7ULP_MU_CR); + else + writel_relaxed(val & ~BIT(0), mu_base + MX7ULP_MU_CR); + } else { + val = readl_relaxed(mu_base + MU_ACR); + if (ready) + writel_relaxed(val | BIT(0), mu_base + MU_ACR); + else + writel_relaxed(val & ~BIT(0), mu_base + MU_ACR); + } + return 0; +} + +static irqreturn_t imx_mu_isr(int irq, void *param) +{ + u32 irqs; + unsigned long flags; + + if (cpu_is_imx7ulp()) + irqs = readl_relaxed(mu_base + MX7ULP_MU_SR); + else + irqs = readl_relaxed(mu_base + MU_ASR); + + if (irqs & (1 << 27)) { + spin_lock_irqsave(&mu_lock, flags); + /* get message from receive buffer */ + if (cpu_is_imx7ulp()) + m4_message[in_idx % MAX_NUM] = readl_relaxed(mu_base + + MX7ULP_MU_RR0); + else + m4_message[in_idx % MAX_NUM] = readl_relaxed(mu_base + + MU_ARR0_OFFSET); + /* disable RIE3 interrupt */ + if (cpu_is_imx7ulp()) + writel_relaxed(readl_relaxed(mu_base + MX7ULP_MU_CR) + & (~BIT(27)), mu_base + MX7ULP_MU_CR); + else + writel_relaxed(readl_relaxed(mu_base + MU_ACR) + & (~BIT(27)), mu_base + MU_ACR); + in_idx++; + if (in_idx == out_idx) { + spin_unlock_irqrestore(&mu_lock, flags); + pr_err("MU overflow!\n"); + return IRQ_HANDLED; + } + spin_unlock_irqrestore(&mu_lock, flags); + + schedule_delayed_work(&mu_work, 0); + } + + return IRQ_HANDLED; +} + +static int imx_mu_probe(struct platform_device *pdev) +{ + int ret; + u32 irq; + struct device_node *np; + struct device *dev = &pdev->dev; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-mu-lp"); + mu_base = of_iomap(np, 0); + WARN_ON(!mu_base); + + ret = of_device_is_compatible(np, "fsl,imx7ulp-mu-lp"); + if (ret) + irq = platform_get_irq(pdev, 1); + else + irq = platform_get_irq(pdev, 0); + ret = request_irq(irq, imx_mu_isr, + IRQF_NO_SUSPEND | IRQF_SHARED, "imx-mu-lp", dev); + if (ret) { + pr_err("%s: register interrupt %d failed, rc %d\n", + __func__, irq, ret); + return ret; + } + + ret = of_device_is_compatible(np, "fsl,imx7d-mu-lp"); + if (ret) { + clk = devm_clk_get(&pdev->dev, "mu"); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, + "mu clock source missing or invalid\n"); + return PTR_ERR(clk); + } else { + ret = clk_prepare_enable(clk); + if (ret) { + dev_err(&pdev->dev, + "unable to enable mu clock\n"); + return ret; + } + } + + /* MU always as a wakeup source for low power mode */ + imx_gpcv2_add_m4_wake_up_irq(irq_to_desc(irq)->irq_data.hwirq, + true); + } else { + /* MU always as a wakeup source for low power mode */ + imx_gpc_add_m4_wake_up_irq(irq_to_desc(irq)->irq_data.hwirq, true); + } + + INIT_DELAYED_WORK(&mu_work, mu_work_handler); + /* bit0 of MX7ULP_MU_CR used to let m4 to know MU is ready now */ + if (cpu_is_imx7ulp()) + writel_relaxed(readl_relaxed(mu_base + MX7ULP_MU_CR) | + BIT(0) | BIT(26) | BIT(27), mu_base + MX7ULP_MU_CR); + else + writel_relaxed(readl_relaxed(mu_base + MU_ACR) | + BIT(26) | BIT(27), mu_base + MU_ACR); + + pr_info("MU is ready for cross core communication!\n"); + + return 0; +} + +static const struct of_device_id imx_mu_ids[] = { + { .compatible = "fsl,imx6sx-mu-lp" }, + { .compatible = "fsl,imx7d-mu-lp" }, + { .compatible = "fsl,imx7ulp-mu-lp" }, + { } +}; + +#ifdef CONFIG_PM_SLEEP +static int mu_suspend(struct device *dev) +{ + return 0; +} + +static int mu_resume(struct device *dev) +{ + if (!cpu_is_imx7ulp()) + return 0; + + writel_relaxed(readl_relaxed(mu_base + MX7ULP_MU_CR) | + BIT(0) | BIT(26) | BIT(27), mu_base + MX7ULP_MU_CR); + + return 0; +} +#endif +static const struct dev_pm_ops mu_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(mu_suspend, mu_resume) +}; + +static struct platform_driver imx_mu_driver = { + .driver = { + .name = "imx-mu-lp", + .owner = THIS_MODULE, + .pm = &mu_pm_ops, + .of_match_table = imx_mu_ids, + }, + .probe = imx_mu_probe, +}; + +static int __init imx_mu_init(void) +{ + return platform_driver_register(&imx_mu_driver); +} +subsys_initcall(imx_mu_init); diff --git a/arch/arm/mach-imx/mx6.h b/arch/arm/mach-imx/mx6.h new file mode 100644 index 00000000000000..06b8135a995469 --- /dev/null +++ b/arch/arm/mach-imx/mx6.h @@ -0,0 +1,51 @@ +/* + * Copyright 2004-2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * * This program is free software; you can redistribute it and/or modify + * * it under the terms of the GNU General Public License version 2 as + * * published by the Free Software Foundation. + * */ + +#ifndef __ASM_ARCH_MXC_IOMAP_H__ +#define __ASM_ARCH_MXC_IOMAP_H__ + +#define MX6Q_IO_P2V(x) IMX_IO_P2V(x) +#define MX6Q_IO_ADDRESS(x) IOMEM(MX6Q_IO_P2V(x)) + +#define MX6Q_L2_BASE_ADDR 0x00a02000 +#define MX6Q_L2_SIZE 0x1000 +#define MX6Q_IOMUXC_BASE_ADDR 0x020e0000 +#define MX6Q_IOMUXC_SIZE 0x4000 +#define MX6Q_SRC_BASE_ADDR 0x020d8000 +#define MX6Q_SRC_SIZE 0x4000 +#define MX6Q_CCM_BASE_ADDR 0x020c4000 +#define MX6Q_CCM_SIZE 0x4000 +#define MX6Q_ANATOP_BASE_ADDR 0x020c8000 +#define MX6Q_ANATOP_SIZE 0x1000 +#define MX6Q_GPC_BASE_ADDR 0x020dc000 +#define MX6Q_GPC_SIZE 0x4000 +#define MX6Q_SEMA4_BASE_ADDR 0x02290000 +#define MX6Q_SEMA4_SIZE 0x4000 +#define MX6Q_MMDC_P0_BASE_ADDR 0x021b0000 +#define MX6Q_MMDC_P0_SIZE 0x4000 +#define MX6Q_MMDC_P1_BASE_ADDR 0x021b4000 +#define MX6Q_MMDC_P1_SIZE 0x4000 +#define MX6Q_AIPS1_BASE_ADDR 0x02000000 +#define MX6Q_AIPS1_SIZE 0x100000 +#define MX6Q_AIPS2_BASE_ADDR 0x02100000 +#define MX6Q_AIPS2_SIZE 0x100000 +#define MX6Q_AIPS3_BASE_ADDR 0x02200000 +#define MX6Q_AIPS3_SIZE 0x100000 + +#define MX6SX_IRAM_TLB_BASE_ADDR 0x008f8000 +#define MX6Q_IRAM_TLB_BASE_ADDR 0x00900000 +#define MX6Q_IRAM_TLB_SIZE 0x4000 +#define TT_ATTRIB_NON_CACHEABLE_1M 0x802 +#define MX6_SUSPEND_IRAM_DATA_SIZE 256 +#define MX6SL_WFI_IRAM_DATA_SIZE 100 + +#define MX6_SUSPEND_IRAM_ADDR_OFFSET 0 +#define MX6_CPUIDLE_IRAM_ADDR_OFFSET 0x1000 +#endif diff --git a/arch/arm/mach-imx/mx7.h b/arch/arm/mach-imx/mx7.h new file mode 100644 index 00000000000000..afbeaef12d072e --- /dev/null +++ b/arch/arm/mach-imx/mx7.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * * This program is free software; you can redistribute it and/or modify + * * it under the terms of the GNU General Public License version 2 as + * * published by the Free Software Foundation. + * */ + +#ifndef __ASM_ARCH_MX7_IOMAP_H__ +#define __ASM_ARCH_MX7_IOMAP_H__ + +#define MX7D_IO_P2V(x) IMX_IO_P2V(x) +#define MX7D_IO_ADDRESS(x) IOMEM(MX7D_IO_P2V(x)) + +#define MX7D_LPSR_BASE_ADDR 0x30270000 +#define MX7D_LPSR_SIZE 0x10000 +#define MX7D_CCM_BASE_ADDR 0x30380000 +#define MX7D_CCM_SIZE 0x10000 +#define MX7D_IOMUXC_BASE_ADDR 0x30330000 +#define MX7D_IOMUXC_SIZE 0x10000 +#define MX7D_IOMUXC_GPR_BASE_ADDR 0x30340000 +#define MX7D_IOMUXC_GPR_SIZE 0x10000 +#define MX7D_ANATOP_BASE_ADDR 0x30360000 +#define MX7D_ANATOP_SIZE 0x10000 +#define MX7D_SNVS_BASE_ADDR 0x30370000 +#define MX7D_SNVS_SIZE 0x10000 +#define MX7D_GPC_BASE_ADDR 0x303a0000 +#define MX7D_GPC_SIZE 0x10000 +#define MX7D_SRC_BASE_ADDR 0x30390000 +#define MX7D_SRC_SIZE 0x10000 +#define MX7D_DDRC_BASE_ADDR 0x307a0000 +#define MX7D_DDRC_SIZE 0x10000 +#define MX7D_DDRC_PHY_BASE_ADDR 0x30790000 +#define MX7D_DDRC_PHY_SIZE 0x10000 +#define MX7D_AIPS1_BASE_ADDR 0x30000000 +#define MX7D_AIPS1_SIZE 0x400000 +#define MX7D_AIPS2_BASE_ADDR 0x30400000 +#define MX7D_AIPS2_SIZE 0x400000 +#define MX7D_AIPS3_BASE_ADDR 0x30900000 +#define MX7D_AIPS3_SIZE 0x300000 +#define MX7D_GIC_BASE_ADDR 0x31000000 +#define MX7D_GIC_SIZE 0x100000 + +#define TT_ATTRIB_NON_CACHEABLE_1M 0x802 +#define MX7_IRAM_TLB_SIZE 0x4000 +#define MX7_SUSPEND_OCRAM_SIZE 0x1000 +#define MX7_CPUIDLE_OCRAM_ADDR_OFFSET 0x1000 +#define MX7_CPUIDLE_OCRAM_SIZE 0x1000 +#define MX7_BUSFREQ_OCRAM_ADDR_OFFSET 0x2000 +#define MX7_BUSFREQ_OCRAM_SIZE 0x1000 + +#endif diff --git a/arch/arm/mach-imx/mx7ulp.h b/arch/arm/mach-imx/mx7ulp.h new file mode 100644 index 00000000000000..35638dfea68b1c --- /dev/null +++ b/arch/arm/mach-imx/mx7ulp.h @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright NXP 2017. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MX7ULP_IOMAP_H__ +#define __ASM_ARCH_MX7ULP_IOMAP_H__ + +#define MX7ULP_IO_P2V(x) IMX_IO_P2V(x) +#define MX7ULP_IO_ADDRESS(x) IOMEM(MX7ULP_IO_P2V(x)) + +#define MX7ULP_AIPS1_BASE_ADDR 0x40000000 +#define MX7ULP_AIPS1_SIZE 0x100000 +#define MX7ULP_AIPS2_BASE_ADDR 0x40300000 +#define MX7ULP_AIPS2_SIZE 0x100000 +#define MX7ULP_AIPS3_BASE_ADDR 0x40400000 +#define MX7ULP_AIPS3_SIZE 0x100000 +#define MX7ULP_AIPS4_BASE_ADDR 0x40a00000 +#define MX7ULP_AIPS4_SIZE 0x100000 +#define MX7ULP_AIPS5_BASE_ADDR 0x41000000 +#define MX7ULP_AIPS5_SIZE 0x100000 +#define MX7ULP_GPIOC_BASE_ADDR 0x400f0000 +#define MX7ULP_GPIOC_SIZE 0x1000 +#define MX7ULP_PCC3_BASE_ADDR 0x40b30000 +#define MX7ULP_PCC3_SIZE 0x1000 +#define MX7ULP_SCG1_BASE_ADDR 0x403e0000 +#define MX7ULP_SCG1_SIZE 0x1000 +#define MX7ULP_PCC2_BASE_ADDR 0x403f0000 +#define MX7ULP_PCC2_SIZE 0x1000 +#define MX7ULP_SIM_BASE_ADDR 0x410a3000 +#define MX7ULP_SIM_SIZE 0x1000 +#define MX7ULP_PMC1_BASE_ADDR 0x40400000 +#define MX7ULP_PMC1_SIZE 0x1000 +#define MX7ULP_SMC1_BASE_ADDR 0x40410000 +#define MX7ULP_SMC1_SIZE 0x1000 +#define MX7ULP_MMDC_BASE_ADDR 0x40ab0000 +#define MX7ULP_MMDC_SIZE 0x1000 +#define MX7ULP_IOMUXC1_BASE_ADDR 0x40ac0000 +#define MX7ULP_IOMUXC1_BASE__SIZE 0x1000 +#define MX7ULP_MMDC_IO_BASE_ADDR 0x40ad0000 +#define MX7ULP_MMDC_IO_SIZE 0x1000 + +/* below is just used for static mapping of the AIPSx's memory region */ +#define MX7ULP_AIPS_VIRT_BASE(x) (0xf4000000 + ((x) * SZ_1M)) + +#define mx7ulp_aips_map_entry(index, _type) { \ + .virtual = MX7ULP_AIPS_VIRT_BASE(index), \ + .pfn = __phys_to_pfn(MX7ULP_AIPS ## index ## _BASE_ADDR), \ + .length = SZ_1M, \ + .type = _type, \ +} + +#define TT_ATTRIB_NON_CACHEABLE_1M 0x802 +#define MX7ULP_IRAM_TLB_SIZE 0x4000 +#define MX7ULP_SUSPEND_OCRAM_SIZE 0x1000 + +#endif diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h index 2bfd2d59b4a66b..c311f9d48de25f 100644 --- a/arch/arm/mach-imx/mxc.h +++ b/arch/arm/mach-imx/mxc.h @@ -33,7 +33,13 @@ #define MXC_CPU_IMX7D 0x72 #define MXC_CPU_IMX7ULP 0xff +#define IMX_DDR_TYPE_DDR3 0 #define IMX_DDR_TYPE_LPDDR2 1 +#define IMX_DDR_TYPE_LPDDR3 2 +#define IMX_MMDC_DDR_TYPE_LPDDR3 3 + +#define IMX_LPDDR2_1CH_MODE 0 +#define IMX_LPDDR2_2CH_MODE 1 #ifndef __ASSEMBLY__ extern unsigned int __mxc_cpu_type; @@ -85,11 +91,28 @@ static inline bool cpu_is_imx6q(void) return __mxc_cpu_type == MXC_CPU_IMX6Q; } +static inline bool cpu_is_imx6(void) +{ + return __mxc_cpu_type == MXC_CPU_IMX6Q || + __mxc_cpu_type == MXC_CPU_IMX6DL || + __mxc_cpu_type == MXC_CPU_IMX6SL || + __mxc_cpu_type == MXC_CPU_IMX6SX || + __mxc_cpu_type == MXC_CPU_IMX6UL || + __mxc_cpu_type == MXC_CPU_IMX6ULL || + __mxc_cpu_type == MXC_CPU_IMX6SLL || + __mxc_cpu_type == MXC_CPU_IMX6ULZ; +} + static inline bool cpu_is_imx7d(void) { return __mxc_cpu_type == MXC_CPU_IMX7D; } +static inline bool cpu_is_imx7ulp(void) +{ + return __mxc_cpu_type == MXC_CPU_IMX7ULP; +} + struct cpu_op { u32 cpu_rate; }; diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c index 2aa26928221dec..90dccaa66c8998 100644 --- a/arch/arm/mach-imx/platsmp.c +++ b/arch/arm/mach-imx/platsmp.c @@ -18,7 +18,7 @@ #include "hardware.h" u32 g_diag_reg; -static void __iomem *scu_base; +void __iomem *scu_base; static struct map_desc scu_io_desc __initdata = { /* .virtual and .pfn are run-time assigned */ @@ -47,15 +47,39 @@ static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle) return 0; } +#define MXC_ARCH_CA7 0xc07 +static unsigned long __mxc_arch_type; + +static inline bool arm_is_ca7(void) +{ + return __mxc_arch_type == MXC_ARCH_CA7; +} /* * Initialise the CPU possible map early - this describes the CPUs * which may be present or become present in the system. */ static void __init imx_smp_init_cpus(void) { + unsigned long arch_type; int i, ncores; - ncores = scu_get_core_count(scu_base); + asm volatile( + ".align 4\n" + "mrc p15, 0, %0, c0, c0, 0\n" + : "=r" (arch_type) + ); + /* MIDR[15:4] defines ARCH type */ + __mxc_arch_type = (arch_type >> 4) & 0xfff; + + if (arm_is_ca7()) { + unsigned long val; + + /* CA7 core number, [25:24] of CP15 L2CTLR */ + asm volatile("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); + ncores = ((val >> 24) & 0x3) + 1; + } else { + ncores = scu_get_core_count(scu_base); + } for (i = ncores; i < NR_CPUS; i++) set_cpu_possible(i, false); @@ -63,11 +87,15 @@ static void __init imx_smp_init_cpus(void) void imx_smp_prepare(void) { + if (arm_is_ca7()) + return; scu_enable(scu_base); } static void __init imx_smp_prepare_cpus(unsigned int max_cpus) { + if (arm_is_ca7()) + return; imx_smp_prepare(); /* diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c index baf3b47601af03..9f44f0fa121fb5 100644 --- a/arch/arm/mach-imx/pm-imx6.c +++ b/arch/arm/mach-imx/pm-imx6.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * Copyright 2011-2014 Freescale Semiconductor, Inc. + * Copyright 2011-2016 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. */ @@ -13,15 +13,21 @@ #include #include #include +#include #include +#include #include +#include #include #include #include +#include #include #include #include +#include + #include "common.h" #include "hardware.h" @@ -54,13 +60,215 @@ #define CGPR 0x64 #define BM_CGPR_INT_MEM_CLK_LPM (0x1 << 17) +#define CCGR4 0x78 +#define CCGR6 0x80 #define MX6Q_SUSPEND_OCRAM_SIZE 0x1000 -#define MX6_MAX_MMDC_IO_NUM 33 +#define MX6_MAX_MMDC_IO_NUM 36 +#define MX6_MAX_MMDC_NUM 36 + +#define ROMC_ROMPATCH0D 0xf0 +#define ROMC_ROMPATCHCNTL 0xf4 +#define ROMC_ROMPATCHENL 0xfc +#define ROMC_ROMPATCH0A 0x100 +#define BM_ROMPATCHCNTL_0D (0x1 << 0) +#define BM_ROMPATCHCNTL_DIS (0x1 << 29) +#define BM_ROMPATCHENL_0D (0x1 << 0) +#define ROM_ADDR_FOR_INTERNAL_RAM_BASE 0x10d7c + +#define UART_UCR1 0x80 +#define UART_UCR2 0x84 +#define UART_UCR3 0x88 +#define UART_UCR4 0x8c +#define UART_UFCR 0x90 +#define UART_UESC 0x9c +#define UART_UTIM 0xa0 +#define UART_UBIR 0xa4 +#define UART_UBMR 0xa8 +#define UART_UBRC 0xac +#define UART_UTS 0xb4 + +#define IOMUXC_GPR5_CLOCK_AFCG_X_BYPASS_MASK 0xf800 + +extern unsigned long iram_tlb_base_addr; +extern unsigned long iram_tlb_phys_addr; + +/* QSPI register layout */ +#define QSPI_MCR 0x00 +#define QSPI_IPCR 0x08 +#define QSPI_BUF0CR 0x10 +#define QSPI_BUF1CR 0x14 +#define QSPI_BUF2CR 0x18 +#define QSPI_BUF3CR 0x1c +#define QSPI_BFGENCR 0x20 +#define QSPI_BUF0IND 0x30 +#define QSPI_BUF1IND 0x34 +#define QSPI_BUF2IND 0x38 +#define QSPI_SFAR 0x100 +#define QSPI_SMPR 0x108 +#define QSPI_RBSR 0x10c +#define QSPI_RBCT 0x110 +#define QSPI_TBSR 0x150 +#define QSPI_TBDR 0x154 +#define QSPI_SFA1AD 0x180 +#define QSPI_SFA2AD 0x184 +#define QSPI_SFB1AD 0x188 +#define QSPI_SFB2AD 0x18c +#define QSPI_RBDR_BASE 0x200 +#define QSPI_LUTKEY 0x300 +#define QSPI_LCKCR 0x304 +#define QSPI_LUT_BASE 0x310 + +#define QSPI_RBDR_(x) (QSPI_RBDR_BASE + (x) * 4) +#define QSPI_LUT(x) (QSPI_LUT_BASE + (x) * 4) + +#define QSPI_LUTKEY_VALUE 0x5AF05AF0 +#define QSPI_LCKER_LOCK 0x1 +#define QSPI_LCKER_UNLOCK 0x2 + +enum qspi_regs_valuetype { + QSPI_PREDEFINED, + QSPI_RETRIEVED, +}; + +struct qspi_regs { + int offset; + unsigned int value; + enum qspi_regs_valuetype valuetype; +}; +struct qspi_regs qspi_regs_imx6sx[] = { + {QSPI_IPCR, 0, QSPI_RETRIEVED}, + {QSPI_BUF0CR, 0, QSPI_RETRIEVED}, + {QSPI_BUF1CR, 0, QSPI_RETRIEVED}, + {QSPI_BUF2CR, 0, QSPI_RETRIEVED}, + {QSPI_BUF3CR, 0, QSPI_RETRIEVED}, + {QSPI_BFGENCR, 0, QSPI_RETRIEVED}, + {QSPI_BUF0IND, 0, QSPI_RETRIEVED}, + {QSPI_BUF1IND, 0, QSPI_RETRIEVED}, + {QSPI_BUF2IND, 0, QSPI_RETRIEVED}, + {QSPI_SFAR, 0, QSPI_RETRIEVED}, + {QSPI_SMPR, 0, QSPI_RETRIEVED}, + {QSPI_RBSR, 0, QSPI_RETRIEVED}, + {QSPI_RBCT, 0, QSPI_RETRIEVED}, + {QSPI_TBSR, 0, QSPI_RETRIEVED}, + {QSPI_TBDR, 0, QSPI_RETRIEVED}, + {QSPI_SFA1AD, 0, QSPI_RETRIEVED}, + {QSPI_SFA2AD, 0, QSPI_RETRIEVED}, + {QSPI_SFB1AD, 0, QSPI_RETRIEVED}, + {QSPI_SFB2AD, 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(0), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(1), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(2), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(3), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(4), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(5), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(6), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(7), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(8), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(9), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(10), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(11), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(12), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(13), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(14), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(15), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(16), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(17), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(18), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(19), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(20), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(21), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(22), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(23), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(24), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(25), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(26), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(27), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(28), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(29), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(30), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(31), 0, QSPI_RETRIEVED}, + {QSPI_LUTKEY, QSPI_LUTKEY_VALUE, QSPI_PREDEFINED}, + {QSPI_LCKCR, QSPI_LCKER_UNLOCK, QSPI_PREDEFINED}, + {QSPI_LUT(0), 0, QSPI_RETRIEVED}, + {QSPI_LUT(1), 0, QSPI_RETRIEVED}, + {QSPI_LUT(2), 0, QSPI_RETRIEVED}, + {QSPI_LUT(3), 0, QSPI_RETRIEVED}, + {QSPI_LUT(4), 0, QSPI_RETRIEVED}, + {QSPI_LUT(5), 0, QSPI_RETRIEVED}, + {QSPI_LUT(6), 0, QSPI_RETRIEVED}, + {QSPI_LUT(7), 0, QSPI_RETRIEVED}, + {QSPI_LUT(8), 0, QSPI_RETRIEVED}, + {QSPI_LUT(9), 0, QSPI_RETRIEVED}, + {QSPI_LUT(10), 0, QSPI_RETRIEVED}, + {QSPI_LUT(11), 0, QSPI_RETRIEVED}, + {QSPI_LUT(12), 0, QSPI_RETRIEVED}, + {QSPI_LUT(13), 0, QSPI_RETRIEVED}, + {QSPI_LUT(14), 0, QSPI_RETRIEVED}, + {QSPI_LUT(15), 0, QSPI_RETRIEVED}, + {QSPI_LUT(16), 0, QSPI_RETRIEVED}, + {QSPI_LUT(17), 0, QSPI_RETRIEVED}, + {QSPI_LUT(18), 0, QSPI_RETRIEVED}, + {QSPI_LUT(19), 0, QSPI_RETRIEVED}, + {QSPI_LUT(20), 0, QSPI_RETRIEVED}, + {QSPI_LUT(21), 0, QSPI_RETRIEVED}, + {QSPI_LUT(22), 0, QSPI_RETRIEVED}, + {QSPI_LUT(23), 0, QSPI_RETRIEVED}, + {QSPI_LUT(24), 0, QSPI_RETRIEVED}, + {QSPI_LUT(25), 0, QSPI_RETRIEVED}, + {QSPI_LUT(26), 0, QSPI_RETRIEVED}, + {QSPI_LUT(27), 0, QSPI_RETRIEVED}, + {QSPI_LUT(28), 0, QSPI_RETRIEVED}, + {QSPI_LUT(29), 0, QSPI_RETRIEVED}, + {QSPI_LUT(30), 0, QSPI_RETRIEVED}, + {QSPI_LUT(31), 0, QSPI_RETRIEVED}, + {QSPI_LUT(32), 0, QSPI_RETRIEVED}, + {QSPI_LUT(33), 0, QSPI_RETRIEVED}, + {QSPI_LUT(34), 0, QSPI_RETRIEVED}, + {QSPI_LUT(35), 0, QSPI_RETRIEVED}, + {QSPI_LUT(36), 0, QSPI_RETRIEVED}, + {QSPI_LUT(37), 0, QSPI_RETRIEVED}, + {QSPI_LUT(38), 0, QSPI_RETRIEVED}, + {QSPI_LUT(39), 0, QSPI_RETRIEVED}, + {QSPI_LUT(40), 0, QSPI_RETRIEVED}, + {QSPI_LUT(41), 0, QSPI_RETRIEVED}, + {QSPI_LUT(42), 0, QSPI_RETRIEVED}, + {QSPI_LUT(43), 0, QSPI_RETRIEVED}, + {QSPI_LUT(44), 0, QSPI_RETRIEVED}, + {QSPI_LUT(45), 0, QSPI_RETRIEVED}, + {QSPI_LUT(46), 0, QSPI_RETRIEVED}, + {QSPI_LUT(47), 0, QSPI_RETRIEVED}, + {QSPI_LUT(48), 0, QSPI_RETRIEVED}, + {QSPI_LUT(49), 0, QSPI_RETRIEVED}, + {QSPI_LUT(50), 0, QSPI_RETRIEVED}, + {QSPI_LUT(51), 0, QSPI_RETRIEVED}, + {QSPI_LUT(52), 0, QSPI_RETRIEVED}, + {QSPI_LUT(53), 0, QSPI_RETRIEVED}, + {QSPI_LUT(54), 0, QSPI_RETRIEVED}, + {QSPI_LUT(55), 0, QSPI_RETRIEVED}, + {QSPI_LUT(56), 0, QSPI_RETRIEVED}, + {QSPI_LUT(57), 0, QSPI_RETRIEVED}, + {QSPI_LUT(58), 0, QSPI_RETRIEVED}, + {QSPI_LUT(59), 0, QSPI_RETRIEVED}, + {QSPI_LUT(60), 0, QSPI_RETRIEVED}, + {QSPI_LUT(61), 0, QSPI_RETRIEVED}, + {QSPI_LUT(62), 0, QSPI_RETRIEVED}, + {QSPI_LUT(63), 0, QSPI_RETRIEVED}, + {QSPI_LUTKEY, QSPI_LUTKEY_VALUE, QSPI_PREDEFINED}, + {QSPI_LCKCR, QSPI_LCKER_LOCK, QSPI_PREDEFINED}, + {QSPI_MCR, 0, QSPI_RETRIEVED}, +}; + +static unsigned int *ocram_saved_in_ddr; +static void __iomem *ocram_base; +static void __iomem *console_base; +static void __iomem *qspi_base; +static unsigned int ocram_size; static void __iomem *ccm_base; static void __iomem *suspend_ocram_base; static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase); +struct regmap *romcp; /* * suspend ocram space layout: @@ -90,6 +298,8 @@ struct imx6_pm_socdata { const char *pl310_compat; const u32 mmdc_io_num; const u32 *mmdc_io_offset; + const u32 mmdc_num; + const u32 *mmdc_offset; }; static const u32 imx6q_mmdc_io_offset[] __initconst = { @@ -104,6 +314,18 @@ static const u32 imx6q_mmdc_io_offset[] __initconst = { 0x74c, /* GPR_ADDS */ }; +static const u32 imx6q_mmdc_io_lpddr2_offset[] __initconst = { + 0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */ + 0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */ + 0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */ + 0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */ + 0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */ + 0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */ + 0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */ + 0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */ + 0x74c, 0x590, 0x598, 0x57c, /* GRP_ADDS, SDCKE0, SDCKE1, RESET */ +}; + static const u32 imx6dl_mmdc_io_offset[] __initconst = { 0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */ 0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */ @@ -124,11 +346,25 @@ static const u32 imx6sl_mmdc_io_offset[] __initconst = { 0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */ }; -static const u32 imx6sll_mmdc_io_offset[] __initconst = { - 0x294, 0x298, 0x29c, 0x2a0, /* DQM0 ~ DQM3 */ - 0x544, 0x54c, 0x554, 0x558, /* GPR_B0DS ~ GPR_B3DS */ - 0x530, 0x540, 0x2ac, 0x52c, /* MODE_CTL, MODE, SDCLK_0, GPR_ADDDS */ - 0x2a4, 0x2a8, /* SDCKE0, SDCKE1*/ +static const u32 imx6sx_mmdc_io_lpddr2_offset[] __initconst = { + 0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */ + 0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */ + 0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */ + 0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */ + 0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */ + 0x324, 0x328, 0x340, /* DRAM_SDCKE0 ~ 1, DRAM_RESET */ +}; + +static const u32 imx6sx_mmdc_lpddr2_offset[] __initconst = { + 0x01c, 0x85c, 0x800, 0x890, + 0x8b8, 0x81c, 0x820, 0x824, + 0x828, 0x82c, 0x830, 0x834, + 0x838, 0x848, 0x850, 0x8c0, + 0x83c, 0x840, 0x8b8, 0x00c, + 0x004, 0x010, 0x014, 0x018, + 0x02c, 0x030, 0x038, 0x008, + 0x040, 0x000, 0x020, 0x818, + 0x800, 0x004, 0x01c, }; static const u32 imx6sx_mmdc_io_offset[] __initconst = { @@ -139,6 +375,16 @@ static const u32 imx6sx_mmdc_io_offset[] __initconst = { 0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */ }; +static const u32 imx6sx_mmdc_offset[] __initconst = { + 0x800, 0x80c, 0x810, 0x83c, + 0x840, 0x848, 0x850, 0x81c, + 0x820, 0x824, 0x828, 0x8b8, + 0x004, 0x008, 0x00c, 0x010, + 0x014, 0x018, 0x01c, 0x02c, + 0x030, 0x040, 0x000, 0x01c, + 0x020, 0x818, 0x01c, +}; + static const u32 imx6ul_mmdc_io_offset[] __initconst = { 0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */ 0x27c, 0x498, 0x4a4, 0x490, /* SDCLK0, GPR_B0DS-B1DS, GPR_ADDS */ @@ -146,6 +392,53 @@ static const u32 imx6ul_mmdc_io_offset[] __initconst = { 0x494, 0x4b0, /* MODE_CTL, MODE, */ }; +static const u32 imx6ul_mmdc_offset[] __initconst = { + 0x01c, 0x800, 0x80c, 0x83c, + 0x848, 0x850, 0x81c, 0x820, + 0x82c, 0x830, 0x8c0, 0x8b8, + 0x004, 0x008, 0x00c, 0x010, + 0x014, 0x018, 0x01c, 0x02c, + 0x030, 0x040, 0x000, 0x01c, + 0x020, 0x818, 0x01c, +}; + +static const u32 imx6ul_mmdc_io_lpddr2_offset[] __initconst = { + 0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */ + 0x27c, 0x498, 0x4a4, 0x490, /* SDCLK0, GPR_B0DS-B1DS, GPR_ADDS */ + 0x280, 0x284, 0x260, 0x264, /* SDQS0~1, SODT0, SODT1 */ + 0x494, 0x4b0, 0x274, 0x278, /* MODE_CTL, MODE, SDCKE0, SDCKE1 */ + 0x288, /* DRAM_RESET */ +}; + +static const u32 imx6ul_mmdc_lpddr2_offset[] __initconst = { + 0x01c, 0x85c, 0x800, 0x890, + 0x8b8, 0x81c, 0x820, 0x82c, + 0x830, 0x83c, 0x848, 0x850, + 0x8c0, 0x8b8, 0x004, 0x008, + 0x00c, 0x010, 0x038, 0x014, + 0x018, 0x01c, 0x02c, 0x030, + 0x040, 0x000, 0x020, 0x818, + 0x800, 0x004, 0x01c, +}; + +static const u32 imx6sll_mmdc_io_offset[] __initconst = { + 0x294, 0x298, 0x29c, 0x2a0, /* DQM0 ~ DQM3 */ + 0x544, 0x54c, 0x554, 0x558, /* GPR_B0DS ~ GPR_B3DS */ + 0x530, 0x540, 0x2ac, 0x52c, /* MODE_CTL, MODE, SDCLK_0, GPR_ADDDS */ + 0x2a4, 0x2a8, /* SDCKE0, SDCKE1*/ +}; + +static const u32 imx6sll_mmdc_lpddr3_offset[] __initconst = { + 0x01c, 0x85c, 0x800, 0x890, + 0x8b8, 0x81c, 0x820, 0x82c, + 0x830, 0x83c, 0x848, 0x850, + 0x8c0, 0x8b8, 0x004, 0x008, + 0x00c, 0x010, 0x038, 0x014, + 0x018, 0x01c, 0x02c, 0x030, + 0x040, 0x000, 0x020, 0x818, + 0x800, 0x004, 0x01c, +}; + static const struct imx6_pm_socdata imx6q_pm_data __initconst = { .mmdc_compat = "fsl,imx6q-mmdc", .src_compat = "fsl,imx6q-src", @@ -154,6 +447,19 @@ static const struct imx6_pm_socdata imx6q_pm_data __initconst = { .pl310_compat = "arm,pl310-cache", .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset), .mmdc_io_offset = imx6q_mmdc_io_offset, + .mmdc_num = 0, + .mmdc_offset = NULL, +}; + +static const struct imx6_pm_socdata imx6q_lpddr2_pm_data __initconst = { + .mmdc_compat = "fsl,imx6q-mmdc", + .src_compat = "fsl,imx6q-src", + .iomuxc_compat = "fsl,imx6q-iomuxc", + .gpc_compat = "fsl,imx6q-gpc", + .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_lpddr2_offset), + .mmdc_io_offset = imx6q_mmdc_io_lpddr2_offset, + .mmdc_num = 0, + .mmdc_offset = NULL, }; static const struct imx6_pm_socdata imx6dl_pm_data __initconst = { @@ -164,6 +470,8 @@ static const struct imx6_pm_socdata imx6dl_pm_data __initconst = { .pl310_compat = "arm,pl310-cache", .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset), .mmdc_io_offset = imx6dl_mmdc_io_offset, + .mmdc_num = 0, + .mmdc_offset = NULL, }; static const struct imx6_pm_socdata imx6sl_pm_data __initconst = { @@ -174,16 +482,8 @@ static const struct imx6_pm_socdata imx6sl_pm_data __initconst = { .pl310_compat = "arm,pl310-cache", .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset), .mmdc_io_offset = imx6sl_mmdc_io_offset, -}; - -static const struct imx6_pm_socdata imx6sll_pm_data __initconst = { - .mmdc_compat = "fsl,imx6sll-mmdc", - .src_compat = "fsl,imx6sll-src", - .iomuxc_compat = "fsl,imx6sll-iomuxc", - .gpc_compat = "fsl,imx6sll-gpc", - .pl310_compat = "arm,pl310-cache", - .mmdc_io_num = ARRAY_SIZE(imx6sll_mmdc_io_offset), - .mmdc_io_offset = imx6sll_mmdc_io_offset, + .mmdc_num = 0, + .mmdc_offset = NULL, }; static const struct imx6_pm_socdata imx6sx_pm_data __initconst = { @@ -194,6 +494,19 @@ static const struct imx6_pm_socdata imx6sx_pm_data __initconst = { .pl310_compat = "arm,pl310-cache", .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset), .mmdc_io_offset = imx6sx_mmdc_io_offset, + .mmdc_num = ARRAY_SIZE(imx6sx_mmdc_offset), + .mmdc_offset = imx6sx_mmdc_offset, +}; + +static const struct imx6_pm_socdata imx6sx_lpddr2_pm_data __initconst = { + .mmdc_compat = "fsl,imx6sx-mmdc", + .src_compat = "fsl,imx6sx-src", + .iomuxc_compat = "fsl,imx6sx-iomuxc", + .gpc_compat = "fsl,imx6sx-gpc", + .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_lpddr2_offset), + .mmdc_io_offset = imx6sx_mmdc_io_lpddr2_offset, + .mmdc_num = ARRAY_SIZE(imx6sx_mmdc_lpddr2_offset), + .mmdc_offset = imx6sx_mmdc_lpddr2_offset, }; static const struct imx6_pm_socdata imx6ul_pm_data __initconst = { @@ -204,6 +517,61 @@ static const struct imx6_pm_socdata imx6ul_pm_data __initconst = { .pl310_compat = NULL, .mmdc_io_num = ARRAY_SIZE(imx6ul_mmdc_io_offset), .mmdc_io_offset = imx6ul_mmdc_io_offset, + .mmdc_num = ARRAY_SIZE(imx6ul_mmdc_offset), + .mmdc_offset = imx6ul_mmdc_offset, +}; + +static const struct imx6_pm_socdata imx6ul_lpddr2_pm_data __initconst = { + .mmdc_compat = "fsl,imx6ul-mmdc", + .src_compat = "fsl,imx6ul-src", + .iomuxc_compat = "fsl,imx6ul-iomuxc", + .gpc_compat = "fsl,imx6ul-gpc", + .mmdc_io_num = ARRAY_SIZE(imx6ul_mmdc_io_lpddr2_offset), + .mmdc_io_offset = imx6ul_mmdc_io_lpddr2_offset, + .mmdc_num = ARRAY_SIZE(imx6ul_mmdc_lpddr2_offset), + .mmdc_offset = imx6ul_mmdc_lpddr2_offset, +}; + +static const struct imx6_pm_socdata imx6sll_pm_data __initconst = { + .mmdc_compat = "fsl,imx6sll-mmdc", + .src_compat = "fsl,imx6sll-src", + .iomuxc_compat = "fsl,imx6sll-iomuxc", + .gpc_compat = "fsl,imx6sll-gpc", + .mmdc_io_num = ARRAY_SIZE(imx6sll_mmdc_io_offset), + .mmdc_io_offset = imx6sll_mmdc_io_offset, + .mmdc_num = ARRAY_SIZE(imx6sll_mmdc_lpddr3_offset), + .mmdc_offset = imx6sll_mmdc_lpddr3_offset, +}; + +static struct map_desc iram_tlb_io_desc __initdata = { + /* .virtual and .pfn are run-time assigned */ + .length = SZ_1M, + .type = MT_MEMORY_RWX_NONCACHED, +}; + +/* + * AIPS1 and AIPS2 is not used, because it will trigger a BUG_ON if + * lowlevel debug and earlyprintk are configured. + * + * it is because there is a vm conflict because UART1 is mapped early if + * AIPS1 is mapped using 1M size. + * + * Thus no use AIPS1 and AIPS2 to avoid kernel BUG_ON. + */ +static struct map_desc imx6_pm_io_desc[] __initdata = { + imx_map_entry(MX6Q, MMDC_P0, MT_DEVICE), + imx_map_entry(MX6Q, MMDC_P1, MT_DEVICE), + imx_map_entry(MX6Q, SRC, MT_DEVICE), + imx_map_entry(MX6Q, IOMUXC, MT_DEVICE), + imx_map_entry(MX6Q, CCM, MT_DEVICE), + imx_map_entry(MX6Q, ANATOP, MT_DEVICE), + imx_map_entry(MX6Q, GPC, MT_DEVICE), + imx_map_entry(MX6Q, L2, MT_DEVICE), +}; + +static const char * const low_power_ocram_match[] __initconst = { + "fsl,lpm-sram", + NULL }; /* @@ -218,14 +586,19 @@ struct imx6_cpu_pm_info { phys_addr_t resume_addr; /* The physical resume address for asm code */ u32 ddr_type; u32 pm_info_size; /* Size of pm_info. */ - struct imx6_pm_base mmdc_base; + struct imx6_pm_base mmdc0_base; + struct imx6_pm_base mmdc1_base; struct imx6_pm_base src_base; struct imx6_pm_base iomuxc_base; struct imx6_pm_base ccm_base; struct imx6_pm_base gpc_base; struct imx6_pm_base l2_base; + struct imx6_pm_base anatop_base; + u32 ttbr1; /* Store TTBR1 */ u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */ - u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */ + u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][3]; /* To save offset, value, low power settings */ + u32 mmdc_num; /* Number of MMDC registers which need saved/restored. */ + u32 mmdc_val[MX6_MAX_MMDC_NUM][2]; } __aligned(8); void imx6_set_int_mem_clk_lpm(bool enable) @@ -304,11 +677,18 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode) val |= 0x2 << BP_CLPCR_LPM; val &= ~BM_CLPCR_VSTBY; val &= ~BM_CLPCR_SBYOS; - if (cpu_is_imx6sl()) + if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6sll()) val |= BM_CLPCR_BYPASS_PMIC_READY; if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || - cpu_is_imx6ull() || cpu_is_imx6sll() || cpu_is_imx6ulz()) + cpu_is_imx6ull() || cpu_is_imx6ulz() || cpu_is_imx6sll()) val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; + else if (cpu_is_imx6q() && + imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2 && + imx_mmdc_get_lpddr2_2ch_mode() == IMX_LPDDR2_2CH_MODE) { + /* keep handshake enabled for lpddr2 2ch-mode */ + val &= ~BM_CLPCR_BYP_MMDC_CH0_LPM_HS; + val &= ~BM_CLPCR_BYP_MMDC_CH1_LPM_HS; + } else val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; break; @@ -322,11 +702,18 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode) val |= 0x3 << BP_CLPCR_STBY_COUNT; val |= BM_CLPCR_VSTBY; val |= BM_CLPCR_SBYOS; - if (cpu_is_imx6sl() || cpu_is_imx6sx()) + if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6sll()) val |= BM_CLPCR_BYPASS_PMIC_READY; if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || - cpu_is_imx6ull() || cpu_is_imx6sll() || cpu_is_imx6ulz()) + cpu_is_imx6ull() || cpu_is_imx6ulz() || cpu_is_imx6sll()) val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; + else if (cpu_is_imx6q() && + imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2 && + imx_mmdc_get_lpddr2_2ch_mode() == IMX_LPDDR2_2CH_MODE) { + /* keep handshake enabled for lpddr2 2ch-mode */ + val &= ~BM_CLPCR_BYP_MMDC_CH0_LPM_HS; + val &= ~BM_CLPCR_BYP_MMDC_CH1_LPM_HS; + } else val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; break; @@ -357,8 +744,18 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode) return 0; } +#define MX6Q_SUSPEND_PARAM \ + ((0 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \ + (1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \ + (PSCI_POWER_STATE_TYPE_POWER_DOWN << PSCI_0_2_POWER_STATE_TYPE_SHIFT)) + static int imx6q_suspend_finish(unsigned long val) { + if (psci_ops.cpu_suspend) { + return psci_ops.cpu_suspend(MX6Q_SUSPEND_PARAM, + __pa(cpu_resume)); + } + if (!imx6_suspend_in_ocram_fn) { cpu_do_idle(); } else { @@ -377,19 +774,104 @@ static int imx6q_suspend_finish(unsigned long val) return 0; } +static void imx6_console_save(unsigned int *regs) +{ + if (!console_base) + return; + + regs[0] = readl_relaxed(console_base + UART_UCR1); + regs[1] = readl_relaxed(console_base + UART_UCR2); + regs[2] = readl_relaxed(console_base + UART_UCR3); + regs[3] = readl_relaxed(console_base + UART_UCR4); + regs[4] = readl_relaxed(console_base + UART_UFCR); + regs[5] = readl_relaxed(console_base + UART_UESC); + regs[6] = readl_relaxed(console_base + UART_UTIM); + regs[7] = readl_relaxed(console_base + UART_UBIR); + regs[8] = readl_relaxed(console_base + UART_UBMR); + regs[9] = readl_relaxed(console_base + UART_UTS); +} + +static void imx6_console_restore(unsigned int *regs) +{ + if (!console_base) + return; + + writel_relaxed(regs[4], console_base + UART_UFCR); + writel_relaxed(regs[5], console_base + UART_UESC); + writel_relaxed(regs[6], console_base + UART_UTIM); + writel_relaxed(regs[7], console_base + UART_UBIR); + writel_relaxed(regs[8], console_base + UART_UBMR); + writel_relaxed(regs[9], console_base + UART_UTS); + writel_relaxed(regs[0], console_base + UART_UCR1); + writel_relaxed(regs[1] | 0x1, console_base + UART_UCR2); + writel_relaxed(regs[2], console_base + UART_UCR3); + writel_relaxed(regs[3], console_base + UART_UCR4); +} + +static void imx6_qspi_save(struct qspi_regs *pregs, int reg_num) +{ + int i; + + if (!qspi_base) + return; + + for (i = 0; i < reg_num; i++) { + if (QSPI_RETRIEVED == pregs[i].valuetype) + pregs[i].value = readl_relaxed(qspi_base + + pregs[i].offset); + } +} + +static void imx6_qspi_restore(struct qspi_regs *pregs, int reg_num) +{ + int i; + + if (!qspi_base) + return; + + for (i = 0; i < reg_num; i++) + writel_relaxed(pregs[i].value, qspi_base + pregs[i].offset); +} + static int imx6q_pm_enter(suspend_state_t state) { + unsigned int console_saved_reg[10] = {0}; + static unsigned int ccm_ccgr4, ccm_ccgr6; + +#ifdef CONFIG_SOC_IMX6SX + if (imx_src_is_m4_enabled()) { + if (imx_gpc_is_m4_sleeping() && imx_mu_is_m4_in_low_freq()) { + imx_gpc_hold_m4_in_sleep(); + imx_mu_enable_m4_irqs_in_gic(true); + } else { + pr_info("M4 is busy, enter WAIT mode instead of STOP!\n"); + imx6_set_lpm(WAIT_UNCLOCKED); + imx6_set_int_mem_clk_lpm(true); + imx_gpc_pre_suspend(false); + /* Zzz ... */ + cpu_do_idle(); + imx_gpc_post_resume(); + imx6_set_lpm(WAIT_CLOCKED); + + return 0; + } + } +#endif switch (state) { case PM_SUSPEND_STANDBY: imx6_set_lpm(STOP_POWER_ON); imx6_set_int_mem_clk_lpm(true); imx_gpc_pre_suspend(false); +#ifdef CONFIG_SOC_IMX6SL if (cpu_is_imx6sl()) imx6sl_set_wait_clk(true); +#endif /* Zzz ... */ cpu_do_idle(); +#ifdef CONFIG_SOC_IMX6SL if (cpu_is_imx6sl()) imx6sl_set_wait_clk(false); +#endif imx_gpc_post_resume(); imx6_set_lpm(WAIT_CLOCKED); break; @@ -405,8 +887,50 @@ static int imx6q_pm_enter(suspend_state_t state) imx6_enable_rbc(true); imx_gpc_pre_suspend(true); imx_anatop_pre_suspend(); + if ((cpu_is_imx6ull() || cpu_is_imx6ulz() || cpu_is_imx6sll()) && + imx_gpc_is_mf_mix_off()) + imx6_console_save(console_saved_reg); + if (cpu_is_imx6sx() && imx_gpc_is_mf_mix_off()) { + ccm_ccgr4 = readl_relaxed(ccm_base + CCGR4); + ccm_ccgr6 = readl_relaxed(ccm_base + CCGR6); + /* + * i.MX6SX RDC needs PCIe and eim clk to be enabled + * if Mega/Fast off, it is better to check cpu type + * and whether Mega/Fast is off in this suspend flow, + * but we need to add cpu type check for 3 places which + * will increase code size, so here we just do it + * for all cases, as when STOP mode is entered, CCM + * hardware will gate all clocks, so it will NOT impact + * any function or power. + */ + writel_relaxed(ccm_ccgr4 | (0x3 << 0), ccm_base + + CCGR4); + writel_relaxed(ccm_ccgr6 | (0x3 << 10), ccm_base + + CCGR6); + memcpy(ocram_saved_in_ddr, ocram_base, ocram_size); + imx6_console_save(console_saved_reg); + if (imx_src_is_m4_enabled()) + imx6_qspi_save(qspi_regs_imx6sx, + sizeof(qspi_regs_imx6sx) / + sizeof(struct qspi_regs)); + } + /* Zzz ... */ cpu_suspend(0, imx6q_suspend_finish); + + if (cpu_is_imx6sx() && imx_gpc_is_mf_mix_off()) { + writel_relaxed(ccm_ccgr4, ccm_base + CCGR4); + writel_relaxed(ccm_ccgr6, ccm_base + CCGR6); + memcpy(ocram_base, ocram_saved_in_ddr, ocram_size); + imx6_console_restore(console_saved_reg); + if (imx_src_is_m4_enabled()) + imx6_qspi_restore(qspi_regs_imx6sx, + sizeof(qspi_regs_imx6sx) / + sizeof(struct qspi_regs)); + } + if ((cpu_is_imx6ull() || cpu_is_imx6ulz() || cpu_is_imx6sll()) && + imx_gpc_is_mf_mix_off()) + imx6_console_restore(console_saved_reg); if (cpu_is_imx6q() || cpu_is_imx6dl()) imx_smp_prepare(); imx_anatop_post_resume(); @@ -420,6 +944,13 @@ static int imx6q_pm_enter(suspend_state_t state) return -EINVAL; } +#ifdef CONFIG_SOC_IMX6SX + if (imx_src_is_m4_enabled()) { + imx_mu_enable_m4_irqs_in_gic(false); + imx_gpc_release_m4_in_sleep(); + } +#endif + return 0; } @@ -433,41 +964,114 @@ static const struct platform_suspend_ops imx6q_pm_ops = { .valid = imx6q_pm_valid, }; -static int __init imx6_pm_get_base(struct imx6_pm_base *base, - const char *compat) +static int __init imx6_dt_find_lpsram(unsigned long node, const char *uname, + int depth, void *data) { - struct device_node *node; - struct resource res; - int ret = 0; + unsigned long lpram_addr; + const __be32 *prop = of_get_flat_dt_prop(node, "reg", NULL); - node = of_find_compatible_node(NULL, NULL, compat); - if (!node) - return -ENODEV; + if (of_flat_dt_match(node, low_power_ocram_match)) { + if (!prop) + return -EINVAL; - ret = of_address_to_resource(node, 0, &res); - if (ret) - goto put_node; + lpram_addr = be32_to_cpup(prop); - base->pbase = res.start; - base->vbase = ioremap(res.start, resource_size(&res)); - if (!base->vbase) - ret = -ENOMEM; + /* We need to create a 1M page table entry. */ + iram_tlb_io_desc.virtual = IMX_IO_P2V(lpram_addr & 0xFFF00000); + iram_tlb_io_desc.pfn = __phys_to_pfn(lpram_addr & 0xFFF00000); + iram_tlb_phys_addr = lpram_addr; + iram_tlb_base_addr = IMX_IO_P2V(lpram_addr); -put_node: - of_node_put(node); - return ret; + iotable_init(&iram_tlb_io_desc, 1); + } + + return 0; +} + +void __init imx6_pm_map_io(void) +{ + unsigned long i; + + iotable_init(imx6_pm_io_desc, ARRAY_SIZE(imx6_pm_io_desc)); + + /* + * Get the address of IRAM or OCRAM to be used by the low + * power code from the device tree. + */ + WARN_ON(of_scan_flat_dt(imx6_dt_find_lpsram, NULL)); + + /* + * We moved suspend/resume and lowpower idle to TEE, + * But busfreq now still in Linux, this table is still needed + * If we later decide to move busfreq to TEE, we could drop this. + */ + /* Return if no IRAM space is allocated for suspend/resume code. */ + if (!iram_tlb_base_addr) { + pr_warn("No IRAM/OCRAM memory allocated for suspend/resume \ + code. Please ensure device tree has an entry for \ + fsl,lpm-sram.\n"); + return; + } + + /* Set all entries to 0. */ + memset((void *)iram_tlb_base_addr, 0, MX6Q_IRAM_TLB_SIZE); + + /* + * Make sure the IRAM virtual address has a mapping in the IRAM + * page table. + * + * Only use the top 11 bits [31-20] when storing the physical + * address in the page table as only these bits are required + * for 1M mapping. + */ + i = ((iram_tlb_base_addr >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + i) = + (iram_tlb_phys_addr & 0xFFF00000) | TT_ATTRIB_NON_CACHEABLE_1M; + + /* + * Make sure the AIPS1 virtual address has a mapping in the + * IRAM page table. + */ + i = ((IMX_IO_P2V(MX6Q_AIPS1_BASE_ADDR) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + i) = + (MX6Q_AIPS1_BASE_ADDR & 0xFFF00000) | + TT_ATTRIB_NON_CACHEABLE_1M; + + /* + * Make sure the AIPS2 virtual address has a mapping in the + * IRAM page table. + */ + i = ((IMX_IO_P2V(MX6Q_AIPS2_BASE_ADDR) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + i) = + (MX6Q_AIPS2_BASE_ADDR & 0xFFF00000) | + TT_ATTRIB_NON_CACHEABLE_1M; + + /* + * Make sure the AIPS3 virtual address has a mapping + * in the IRAM page table. + */ + i = ((IMX_IO_P2V(MX6Q_AIPS3_BASE_ADDR) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + i) = + (MX6Q_AIPS3_BASE_ADDR & 0xFFF00000) | + TT_ATTRIB_NON_CACHEABLE_1M; + + /* + * Make sure the L2 controller virtual address has a mapping + * in the IRAM page table. + */ + i = ((IMX_IO_P2V(MX6Q_L2_BASE_ADDR) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + i) = + (MX6Q_L2_BASE_ADDR & 0xFFF00000) | TT_ATTRIB_NON_CACHEABLE_1M; } static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) { - phys_addr_t ocram_pbase; struct device_node *node; - struct platform_device *pdev; struct imx6_cpu_pm_info *pm_info; - struct gen_pool *ocram_pool; - unsigned long ocram_base; + unsigned long iram_paddr; int i, ret = 0; const u32 *mmdc_offset_array; + const u32 *mmdc_io_offset_array; suspend_set_ops(&imx6q_pm_ops); @@ -476,41 +1080,30 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) return -EINVAL; } - node = of_find_compatible_node(NULL, NULL, "mmio-sram"); - if (!node) { - pr_warn("%s: failed to find ocram node!\n", __func__); - return -ENODEV; + if (psci_ops.cpu_suspend) { + /* TODO: seems not needed */ + /* of_node_put(node); */ + return ret; } - pdev = of_find_device_by_node(node); - if (!pdev) { - pr_warn("%s: failed to find ocram device!\n", __func__); - ret = -ENODEV; - goto put_node; - } - - ocram_pool = gen_pool_get(&pdev->dev, NULL); - if (!ocram_pool) { - pr_warn("%s: ocram pool unavailable!\n", __func__); - ret = -ENODEV; - goto put_device; - } - - ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE); - if (!ocram_base) { - pr_warn("%s: unable to alloc ocram!\n", __func__); - ret = -ENOMEM; - goto put_device; - } + /* + * 16KB is allocated for IRAM TLB, but only up 8k is for kernel TLB, + * The lower 8K is not used, so use the lower 8K for IRAM code and + * pm_info. + * + */ + iram_paddr = iram_tlb_phys_addr + MX6_SUSPEND_IRAM_ADDR_OFFSET; - ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base); + /* Make sure iram_paddr is 8 byte aligned. */ + if ((uintptr_t)(iram_paddr) & (FNCPY_ALIGN - 1)) + iram_paddr += FNCPY_ALIGN - iram_paddr % (FNCPY_ALIGN); - suspend_ocram_base = __arm_ioremap_exec(ocram_pbase, - MX6Q_SUSPEND_OCRAM_SIZE, false); + /* Get the virtual address of the suspend code. */ + suspend_ocram_base = (void *)IMX_IO_P2V(iram_paddr); memset(suspend_ocram_base, 0, sizeof(*pm_info)); pm_info = suspend_ocram_base; - pm_info->pbase = ocram_pbase; + pm_info->pbase = iram_paddr; pm_info->resume_addr = __pa_symbol(v7_cpu_resume); pm_info->pm_info_size = sizeof(*pm_info); @@ -518,70 +1111,127 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) * ccm physical address is not used by asm code currently, * so get ccm virtual address directly. */ - pm_info->ccm_base.vbase = ccm_base; + pm_info->ccm_base.pbase = MX6Q_CCM_BASE_ADDR; + pm_info->ccm_base.vbase = (void __iomem *) + IMX_IO_P2V(MX6Q_CCM_BASE_ADDR); - ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat); - if (ret) { - pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret); - goto put_device; - } + pm_info->mmdc0_base.pbase = MX6Q_MMDC_P0_BASE_ADDR; + pm_info->mmdc0_base.vbase = (void __iomem *) + IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR); - ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat); - if (ret) { - pr_warn("%s: failed to get src base %d!\n", __func__, ret); - goto src_map_failed; - } + pm_info->mmdc1_base.pbase = MX6Q_MMDC_P1_BASE_ADDR; + pm_info->mmdc1_base.vbase = (void __iomem *) + IMX_IO_P2V(MX6Q_MMDC_P1_BASE_ADDR); - ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat); - if (ret) { - pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret); - goto iomuxc_map_failed; - } + pm_info->src_base.pbase = MX6Q_SRC_BASE_ADDR; + pm_info->src_base.vbase = (void __iomem *) + IMX_IO_P2V(MX6Q_SRC_BASE_ADDR); - ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat); - if (ret) { - pr_warn("%s: failed to get gpc base %d!\n", __func__, ret); - goto gpc_map_failed; - } + pm_info->iomuxc_base.pbase = MX6Q_IOMUXC_BASE_ADDR; + pm_info->iomuxc_base.vbase = (void __iomem *) + IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR); - if (socdata->pl310_compat) { - ret = imx6_pm_get_base(&pm_info->l2_base, socdata->pl310_compat); - if (ret) { - pr_warn("%s: failed to get pl310-cache base %d!\n", - __func__, ret); - goto pl310_cache_map_failed; - } - } + pm_info->gpc_base.pbase = MX6Q_GPC_BASE_ADDR; + pm_info->gpc_base.vbase = (void __iomem *) + IMX_IO_P2V(MX6Q_GPC_BASE_ADDR); + + pm_info->l2_base.pbase = MX6Q_L2_BASE_ADDR; + pm_info->l2_base.vbase = (void __iomem *) + IMX_IO_P2V(MX6Q_L2_BASE_ADDR); + + pm_info->anatop_base.pbase = MX6Q_ANATOP_BASE_ADDR; + pm_info->anatop_base.vbase = (void __iomem *) + IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR); pm_info->ddr_type = imx_mmdc_get_ddr_type(); pm_info->mmdc_io_num = socdata->mmdc_io_num; - mmdc_offset_array = socdata->mmdc_io_offset; + mmdc_io_offset_array = socdata->mmdc_io_offset; + pm_info->mmdc_num = socdata->mmdc_num; + mmdc_offset_array = socdata->mmdc_offset; for (i = 0; i < pm_info->mmdc_io_num; i++) { pm_info->mmdc_io_val[i][0] = - mmdc_offset_array[i]; + mmdc_io_offset_array[i]; pm_info->mmdc_io_val[i][1] = readl_relaxed(pm_info->iomuxc_base.vbase + + mmdc_io_offset_array[i]); + pm_info->mmdc_io_val[i][2] = 0; + } + + /* i.MX6SLL has no DRAM RESET pin */ + if (cpu_is_imx6sll()) { + pm_info->mmdc_io_val[pm_info->mmdc_io_num - 2][2] = 0x1000; + pm_info->mmdc_io_val[pm_info->mmdc_io_num - 1][2] = 0x1000; + } else { + if (pm_info->ddr_type == IMX_DDR_TYPE_LPDDR2) { + /* for LPDDR2, CKE0/1 and RESET pin need special setting */ + pm_info->mmdc_io_val[pm_info->mmdc_io_num - 3][2] = 0x1000; + pm_info->mmdc_io_val[pm_info->mmdc_io_num - 2][2] = 0x1000; + pm_info->mmdc_io_val[pm_info->mmdc_io_num - 1][2] = 0x80000; + } + } + + /* initialize MMDC settings */ + for (i = 0; i < pm_info->mmdc_num; i++) { + pm_info->mmdc_val[i][0] = + mmdc_offset_array[i]; + pm_info->mmdc_val[i][1] = + readl_relaxed(pm_info->mmdc0_base.vbase + mmdc_offset_array[i]); } + if (cpu_is_imx6sll() && pm_info->ddr_type == IMX_MMDC_DDR_TYPE_LPDDR3) { + pm_info->mmdc_val[0][1] = 0x8000; + pm_info->mmdc_val[2][1] = 0xa1390003; + pm_info->mmdc_val[3][1] = 0x400000; + pm_info->mmdc_val[4][1] = 0x800; + pm_info->mmdc_val[13][1] = 0x800; + pm_info->mmdc_val[14][1] = 0x20052; + pm_info->mmdc_val[20][1] = 0x201718; + pm_info->mmdc_val[21][1] = 0x8000; + pm_info->mmdc_val[28][1] = 0xa1310003; + } + + /* need to overwrite the value for some mmdc registers */ + if ((cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx6ulz()) && + pm_info->ddr_type != IMX_DDR_TYPE_LPDDR2) { + pm_info->mmdc_val[20][1] = (pm_info->mmdc_val[20][1] + & 0xffff0000) | 0x0202; + pm_info->mmdc_val[23][1] = 0x8033; + } + + if (cpu_is_imx6sx() && + pm_info->ddr_type == IMX_DDR_TYPE_LPDDR2) { + pm_info->mmdc_val[0][1] = 0x8000; + pm_info->mmdc_val[2][1] = 0xa1390003; + pm_info->mmdc_val[3][1] = 0x380000; + pm_info->mmdc_val[4][1] = 0x800; + pm_info->mmdc_val[18][1] = 0x800; + pm_info->mmdc_val[20][1] = 0x20024; + pm_info->mmdc_val[23][1] = 0x1748; + pm_info->mmdc_val[32][1] = 0xa1310003; + } + + if ((cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx6ulz()) && + pm_info->ddr_type == IMX_DDR_TYPE_LPDDR2) { + pm_info->mmdc_val[0][1] = 0x8000; + pm_info->mmdc_val[2][1] = 0xa1390003; + pm_info->mmdc_val[3][1] = 0x470000; + pm_info->mmdc_val[4][1] = 0x800; + pm_info->mmdc_val[13][1] = 0x800; + pm_info->mmdc_val[14][1] = 0x20012; + pm_info->mmdc_val[20][1] = 0x1748; + pm_info->mmdc_val[21][1] = 0x8000; + pm_info->mmdc_val[28][1] = 0xa1310003; + } + imx6_suspend_in_ocram_fn = fncpy( suspend_ocram_base + sizeof(*pm_info), &imx6_suspend, MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info)); - goto put_device; - -pl310_cache_map_failed: - iounmap(pm_info->gpc_base.vbase); -gpc_map_failed: - iounmap(pm_info->iomuxc_base.vbase); -iomuxc_map_failed: - iounmap(pm_info->src_base.vbase); -src_map_failed: - iounmap(pm_info->mmdc_base.vbase); -put_device: - put_device(&pdev->dev); + goto put_node; + put_node: of_node_put(node); @@ -616,28 +1266,6 @@ static void __init imx6_pm_common_init(const struct imx6_pm_socdata IMX6Q_GPR1_GINT); } -static void imx6_pm_stby_poweroff(void) -{ - imx6_set_lpm(STOP_POWER_OFF); - imx6q_suspend_finish(0); - - mdelay(1000); - - pr_emerg("Unable to poweroff system\n"); -} - -static int imx6_pm_stby_poweroff_probe(void) -{ - if (pm_power_off) { - pr_warn("%s: pm_power_off already claimed %p %ps!\n", - __func__, pm_power_off, pm_power_off); - return -EBUSY; - } - - pm_power_off = imx6_pm_stby_poweroff; - return 0; -} - void __init imx6_pm_ccm_init(const char *ccm_compat) { struct device_node *np; @@ -654,14 +1282,14 @@ void __init imx6_pm_ccm_init(const char *ccm_compat) val = readl_relaxed(ccm_base + CLPCR); val &= ~BM_CLPCR_LPM; writel_relaxed(val, ccm_base + CLPCR); - - if (of_property_read_bool(np, "fsl,pmic-stby-poweroff")) - imx6_pm_stby_poweroff_probe(); } void __init imx6q_pm_init(void) { - imx6_pm_common_init(&imx6q_pm_data); + if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) + imx6_pm_common_init(&imx6q_lpddr2_pm_data); + else + imx6_pm_common_init(&imx6q_pm_data); } void __init imx6dl_pm_init(void) @@ -671,25 +1299,96 @@ void __init imx6dl_pm_init(void) void __init imx6sl_pm_init(void) { + struct device_node *np; struct regmap *gpr; - if (cpu_is_imx6sl()) { - imx6_pm_common_init(&imx6sl_pm_data); - } else { + if (cpu_is_imx6sll()) { imx6_pm_common_init(&imx6sll_pm_data); + np = of_find_node_by_path( + "/soc/aips-bus@02000000/spba-bus@02000000/serial@02020000"); + if (np) + console_base = of_iomap(np, 0); + /* i.MX6SLL has bus auto clock gating function */ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); if (!IS_ERR(gpr)) regmap_update_bits(gpr, IOMUXC_GPR5, - IMX6SLL_GPR5_AFCG_X_BYPASS_MASK, 0); + IOMUXC_GPR5_CLOCK_AFCG_X_BYPASS_MASK, 0); + return; } + + imx6_pm_common_init(&imx6sl_pm_data); } void __init imx6sx_pm_init(void) { - imx6_pm_common_init(&imx6sx_pm_data); + struct device_node *np; + struct resource res; + + if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) + imx6_pm_common_init(&imx6sx_lpddr2_pm_data); + else + imx6_pm_common_init(&imx6sx_pm_data); + if (imx_get_soc_revision() < IMX_CHIP_REVISION_1_2) { + /* + * As there is a 16K OCRAM(start from 0x8f8000) + * dedicated for low power function on i.MX6SX, + * but ROM did NOT do the ocram address change + * accordingly, so we need to add a data patch + * to workaround this issue, otherwise, system + * will fail to resume from DSM mode. TO1.2 fixes + * this issue. + */ + romcp = syscon_regmap_lookup_by_compatible( + "fsl,imx6sx-romcp"); + if (IS_ERR(romcp)) { + pr_err("failed to find fsl,imx6sx-romcp regmap\n"); + return; + } + regmap_write(romcp, ROMC_ROMPATCH0D, iram_tlb_phys_addr); + regmap_update_bits(romcp, ROMC_ROMPATCHCNTL, + BM_ROMPATCHCNTL_0D, BM_ROMPATCHCNTL_0D); + regmap_update_bits(romcp, ROMC_ROMPATCHENL, + BM_ROMPATCHENL_0D, BM_ROMPATCHENL_0D); + regmap_write(romcp, ROMC_ROMPATCH0A, + ROM_ADDR_FOR_INTERNAL_RAM_BASE); + regmap_update_bits(romcp, ROMC_ROMPATCHCNTL, + BM_ROMPATCHCNTL_DIS, ~BM_ROMPATCHCNTL_DIS); + } + + np = of_find_compatible_node(NULL, NULL, "fsl,mega-fast-sram"); + ocram_base = of_iomap(np, 0); + WARN_ON(!ocram_base); + WARN_ON(of_address_to_resource(np, 0, &res)); + ocram_size = resource_size(&res); + ocram_saved_in_ddr = kzalloc(ocram_size, GFP_KERNEL); + WARN_ON(!ocram_saved_in_ddr); + + np = of_find_node_by_path( + "/soc/aips-bus@02000000/spba-bus@02000000/serial@02020000"); + if (np) + console_base = of_iomap(np, 0); + if (imx_src_is_m4_enabled()) { + np = of_find_compatible_node(NULL, NULL, + "fsl,imx6sx-qspi-m4-restore"); + if (np) + qspi_base = of_iomap(np, 0); + WARN_ON(!qspi_base); + } } void __init imx6ul_pm_init(void) { - imx6_pm_common_init(&imx6ul_pm_data); + struct device_node *np; + + if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) + imx6_pm_common_init(&imx6ul_lpddr2_pm_data); + else + imx6_pm_common_init(&imx6ul_pm_data); + + if (cpu_is_imx6ull() || cpu_is_imx6ulz()) { + np = of_find_node_by_path( + "/soc/aips-bus@02000000/spba-bus@02000000/serial@02020000"); + if (np) + console_base = of_iomap(np, 0); + } } diff --git a/arch/arm/mach-imx/pm-imx7.c b/arch/arm/mach-imx/pm-imx7.c new file mode 100644 index 00000000000000..e59cbee6dfc2d5 --- /dev/null +++ b/arch/arm/mach-imx/pm-imx7.c @@ -0,0 +1,1230 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "hardware.h" +#include "cpuidle.h" + +#define MX7_SUSPEND_OCRAM_SIZE 0x1000 +#define MX7_MAX_DDRC_NUM 32 +#define MX7_MAX_DDRC_PHY_NUM 16 + +#define MX7_SUSPEND_IRAM_ADDR_OFFSET 0 +#define READ_DATA_FROM_HARDWARE 0 + +#define UART_UCR1 0x80 +#define UART_UCR2 0x84 +#define UART_UCR3 0x88 +#define UART_UCR4 0x8c +#define UART_UFCR 0x90 +#define UART_UESC 0x9c +#define UART_UTIM 0xa0 +#define UART_UBIR 0xa4 +#define UART_UBMR 0xa8 +#define UART_UBRC 0xac +#define UART_UTS 0xb4 + +#define MAX_IOMUXC_GPR 23 +#define MAX_UART_IO 4 +#define MAX_CCM_LPCG 167 +#define MAX_GPT 3 +#define MAX_GPIO_ROW 7 +#define MAX_GPIO_COL 8 + +#define UART_RX_IO 0x128 +#define UART_RX_PAD 0x398 +#define UART_TX_IO 0x12c +#define UART_TX_PAD 0x39c + +#define GPT_CR 0x0 +#define GPT_PR 0x4 +#define GPT_IR 0xc + +#define CCM_LPCG_START 0x4040 +#define CCM_LPCG_STEP 0x10 +#define CCM_EIM_LPCG 0x4160 +#define CCM_PXP_LPCG 0x44c0 +#define CCM_PCIE_LPCG 0x4600 + +#define BM_CCM_ROOT_POST_PODF 0x3f +#define BM_CCM_ROOT_PRE_PODF 0x70000 +#define BM_CCM_ROOT_MUX 0x7000000 +#define BM_CCM_ROOT_ENABLE 0x10000000 + +#define SYS_COUNTER_CNTSR 0x4 +#define BM_SYS_COUNTER_CNTSR_FCR1 0x200 +#define BM_SYS_COUNTER_CNTSR_FCR0 0x100 +#define BM_SYS_COUNTER_CNTCR_FCR1 0x200 +#define BM_SYS_COUNTER_CNTCR_FCR0 0x100 + +#define PFD_A_OFFSET 0xc0 +#define PFD_B_OFFSET 0xd0 + +#define PLL_ARM_OFFSET 0x60 +#define PLL_DDR_OFFSET 0x70 +#define PLL_DDR_SS_OFFSET 0x80 +#define PLL_DDR_NUM_OFFSET 0x90 +#define PLL_DDR_DENOM_OFFSET 0xa0 +#define PLL_480_OFFSET 0xb0 +#define PLL_ENET_OFFSET 0xe0 +#define PLL_AUDIO_OFFSET 0xf0 +#define PLL_AUDIO_SS_OFFSET 0x100 +#define PLL_AUDIO_NUM_OFFSET 0x110 +#define PLL_AUDIO_DENOM_OFFSET 0x120 +#define PLL_VIDEO_OFFSET 0x130 +#define PLL_VIDEO_SS_OFFSET 0x140 +#define PLL_VIDEO_NUM_OFFSET 0x150 +#define PLL_VIDEO_DENOM_OFFSET 0x160 + +#define REG_SET 0x4 +#define REG_CLR 0x8 + +#define GPIO_DR 0x0 +#define GPIO_GDIR 0x4 +#define GPIO_ICR1 0xc +#define GPIO_ICR2 0x10 +#define GPIO_IMR 0x14 +#define GPIO_EDGE 0x1c + +#define M4RCR 0x0C +#define M4_SP_OFF 0x00 +#define M4_PC_OFF 0x04 +#define M4_RCR_HALT 0xAB +#define M4_RCR_GO 0xAA +#define M4_OCRAMS_RESERVED_SIZE 0xc + +extern unsigned long iram_tlb_base_addr; +extern unsigned long iram_tlb_phys_addr; + +static unsigned int *ocram_saved_in_ddr; +static void __iomem *ocram_base; +static unsigned int ocram_size; +static unsigned int *lpm_ocram_saved_in_ddr; +static void __iomem *lpm_ocram_base; + +static unsigned int *lpm_m4tcm_saved_in_ddr; +static void __iomem *lpm_m4tcm_base; +static void __iomem *m4_bootrom_base; + +static unsigned int lpm_ocram_size; +static void __iomem *ccm_base; +static void __iomem *lpsr_base; +static void __iomem *console_base; +static void __iomem *suspend_ocram_base; +static void __iomem *iomuxc_base; +static void __iomem *gpt1_base; +static void __iomem *system_counter_ctrl_base; +static void __iomem *system_counter_cmp_base; +static void __iomem *gpio1_base; +static void (*imx7_suspend_in_ocram_fn)(void __iomem *ocram_vbase); +struct imx7_cpu_pm_info *pm_info; +static bool lpsr_enabled; +static u32 iomuxc_gpr[MAX_IOMUXC_GPR]; +static u32 uart1_io[MAX_UART_IO]; +static u32 ccm_lpcg[MAX_CCM_LPCG]; +static u32 ccm_root[][2] = { + {0x8000, 0}, {0x8080, 0}, {0x8100, 0}, {0x8800, 0}, + {0x8880, 0}, {0x8900, 0}, {0x8980, 0}, {0x9000, 0}, + {0x9800, 0}, {0x9880, 0}, {0xa000, 0}, {0xa080, 0}, + {0xa100, 0}, {0xa180, 0}, {0xa200, 0}, {0xa280, 0}, + {0xa300, 0}, {0xa380, 0}, {0xa400, 0}, {0xa480, 0}, + {0xa500, 0}, {0xa580, 0}, {0xa600, 0}, {0xa680, 0}, + {0xa700, 0}, {0xa780, 0}, {0xa800, 0}, {0xa880, 0}, + {0xa900, 0}, {0xa980, 0}, {0xaa00, 0}, {0xaa80, 0}, + {0xab00, 0}, {0xab80, 0}, {0xac00, 0}, {0xac80, 0}, + {0xad00, 0}, {0xad80, 0}, {0xae00, 0}, {0xae80, 0}, + {0xaf00, 0}, {0xaf80, 0}, {0xb000, 0}, {0xb080, 0}, + {0xb100, 0}, {0xb180, 0}, {0xb200, 0}, {0xb280, 0}, + {0xb300, 0}, {0xb380, 0}, {0xb400, 0}, {0xb480, 0}, + {0xb500, 0}, {0xb580, 0}, {0xb600, 0}, {0xb680, 0}, + {0xb700, 0}, {0xb780, 0}, {0xb800, 0}, {0xb880, 0}, + {0xb900, 0}, {0xb980, 0}, {0xba00, 0}, {0xba80, 0}, + {0xbb00, 0}, {0xbb80, 0}, {0xbc00, 0}, {0xbc80, 0}, + {0xbd00, 0}, {0xbd80, 0}, {0xbe00, 0}, +}; +static u32 pfd_a, pfd_b; +static u32 pll[15]; +static u32 gpt1_regs[MAX_GPT]; +static u32 sys_ctrl_reg, sys_cmp_reg; +static u32 gpio_reg[MAX_GPIO_ROW][MAX_GPIO_COL]; +/* + * suspend ocram space layout: + * ======================== high address ====================== + * . + * . + * . + * ^ + * ^ + * ^ + * imx7_suspend code + * PM_INFO structure(imx7_cpu_pm_info) + * ======================== low address ======================= + */ + +struct imx7_pm_base { + phys_addr_t pbase; + void __iomem *vbase; +}; + +struct imx7_pm_socdata { + u32 ddr_type; + const char *ddrc_compat; + const char *src_compat; + const char *iomuxc_compat; + const char *gpc_compat; + const u32 ddrc_num; + const u32 (*ddrc_offset)[2]; + const u32 ddrc_phy_num; + const u32 (*ddrc_phy_offset)[2]; +}; + +static const u32 imx7d_ddrc_lpddr3_setting[][2] __initconst = { + { 0x0, READ_DATA_FROM_HARDWARE }, + { 0x1a0, READ_DATA_FROM_HARDWARE }, + { 0x1a4, READ_DATA_FROM_HARDWARE }, + { 0x1a8, READ_DATA_FROM_HARDWARE }, + { 0x64, READ_DATA_FROM_HARDWARE }, + { 0xd0, READ_DATA_FROM_HARDWARE }, + { 0xdc, READ_DATA_FROM_HARDWARE }, + { 0xe0, READ_DATA_FROM_HARDWARE }, + { 0xe4, READ_DATA_FROM_HARDWARE }, + { 0xf4, READ_DATA_FROM_HARDWARE }, + { 0x100, READ_DATA_FROM_HARDWARE }, + { 0x104, READ_DATA_FROM_HARDWARE }, + { 0x108, READ_DATA_FROM_HARDWARE }, + { 0x10c, READ_DATA_FROM_HARDWARE }, + { 0x110, READ_DATA_FROM_HARDWARE }, + { 0x114, READ_DATA_FROM_HARDWARE }, + { 0x118, READ_DATA_FROM_HARDWARE }, + { 0x120, READ_DATA_FROM_HARDWARE }, + { 0x11c, READ_DATA_FROM_HARDWARE }, + { 0x180, READ_DATA_FROM_HARDWARE }, + { 0x184, READ_DATA_FROM_HARDWARE }, + { 0x190, READ_DATA_FROM_HARDWARE }, + { 0x194, READ_DATA_FROM_HARDWARE }, + { 0x200, READ_DATA_FROM_HARDWARE }, + { 0x204, READ_DATA_FROM_HARDWARE }, + { 0x210, READ_DATA_FROM_HARDWARE }, + { 0x214, READ_DATA_FROM_HARDWARE }, + { 0x218, READ_DATA_FROM_HARDWARE }, + { 0x240, READ_DATA_FROM_HARDWARE }, + { 0x244, READ_DATA_FROM_HARDWARE }, +}; + +static const u32 imx7d_ddrc_phy_lpddr3_setting[][2] __initconst = { + { 0x0, READ_DATA_FROM_HARDWARE }, + { 0x4, READ_DATA_FROM_HARDWARE }, + { 0x8, READ_DATA_FROM_HARDWARE }, + { 0x10, READ_DATA_FROM_HARDWARE }, + { 0xb0, READ_DATA_FROM_HARDWARE }, + { 0x1c, READ_DATA_FROM_HARDWARE }, + { 0x9c, READ_DATA_FROM_HARDWARE }, + { 0x7c, READ_DATA_FROM_HARDWARE }, + { 0x80, READ_DATA_FROM_HARDWARE }, + { 0x84, READ_DATA_FROM_HARDWARE }, + { 0x88, READ_DATA_FROM_HARDWARE }, + { 0x6c, READ_DATA_FROM_HARDWARE }, + { 0x20, READ_DATA_FROM_HARDWARE }, + { 0x30, READ_DATA_FROM_HARDWARE }, + { 0x50, 0x01000008 }, + { 0x50, 0x00000008 }, + { 0xc0, 0x0e487304 }, + { 0xc0, 0x0e4c7304 }, + { 0xc0, 0x0e4c7306 }, + { 0xc0, 0x0e487304 }, +}; + +static const u32 imx7d_ddrc_ddr3_setting[][2] __initconst = { + { 0x0, READ_DATA_FROM_HARDWARE }, + { 0x1a0, READ_DATA_FROM_HARDWARE }, + { 0x1a4, READ_DATA_FROM_HARDWARE }, + { 0x1a8, READ_DATA_FROM_HARDWARE }, + { 0x64, READ_DATA_FROM_HARDWARE }, + { 0x490, READ_DATA_FROM_HARDWARE }, + { 0xd0, READ_DATA_FROM_HARDWARE }, + { 0xd4, READ_DATA_FROM_HARDWARE }, + { 0xdc, READ_DATA_FROM_HARDWARE }, + { 0xe0, READ_DATA_FROM_HARDWARE }, + { 0xe4, READ_DATA_FROM_HARDWARE }, + { 0xf4, READ_DATA_FROM_HARDWARE }, + { 0x100, READ_DATA_FROM_HARDWARE }, + { 0x104, READ_DATA_FROM_HARDWARE }, + { 0x108, READ_DATA_FROM_HARDWARE }, + { 0x10c, READ_DATA_FROM_HARDWARE }, + { 0x110, READ_DATA_FROM_HARDWARE }, + { 0x114, READ_DATA_FROM_HARDWARE }, + { 0x120, READ_DATA_FROM_HARDWARE }, + { 0x180, READ_DATA_FROM_HARDWARE }, + { 0x190, READ_DATA_FROM_HARDWARE }, + { 0x194, READ_DATA_FROM_HARDWARE }, + { 0x200, READ_DATA_FROM_HARDWARE }, + { 0x204, READ_DATA_FROM_HARDWARE }, + { 0x210, READ_DATA_FROM_HARDWARE }, + { 0x214, READ_DATA_FROM_HARDWARE }, + { 0x218, READ_DATA_FROM_HARDWARE }, + { 0x240, READ_DATA_FROM_HARDWARE }, + { 0x244, READ_DATA_FROM_HARDWARE }, +}; + +static const u32 imx7d_ddrc_phy_ddr3_setting[][2] __initconst = { + { 0x0, READ_DATA_FROM_HARDWARE }, + { 0x4, READ_DATA_FROM_HARDWARE }, + { 0x10, READ_DATA_FROM_HARDWARE }, + { 0xb0, READ_DATA_FROM_HARDWARE }, + { 0x9c, READ_DATA_FROM_HARDWARE }, + { 0x7c, READ_DATA_FROM_HARDWARE }, + { 0x80, READ_DATA_FROM_HARDWARE }, + { 0x84, READ_DATA_FROM_HARDWARE }, + { 0x88, READ_DATA_FROM_HARDWARE }, + { 0x6c, READ_DATA_FROM_HARDWARE }, + { 0x20, READ_DATA_FROM_HARDWARE }, + { 0x30, READ_DATA_FROM_HARDWARE }, + { 0x50, 0x01000010 }, + { 0x50, 0x00000010 }, + { 0xc0, 0x0e407304 }, + { 0xc0, 0x0e447304 }, + { 0xc0, 0x0e447306 }, + { 0xc0, 0x0e407304 }, +}; + +static const struct imx7_pm_socdata imx7d_pm_data_lpddr3 __initconst = { + .ddrc_compat = "fsl,imx7d-ddrc", + .src_compat = "fsl,imx7d-src", + .iomuxc_compat = "fsl,imx7d-iomuxc", + .gpc_compat = "fsl,imx7d-gpc", + .ddrc_num = ARRAY_SIZE(imx7d_ddrc_lpddr3_setting), + .ddrc_offset = imx7d_ddrc_lpddr3_setting, + .ddrc_phy_num = ARRAY_SIZE(imx7d_ddrc_phy_lpddr3_setting), + .ddrc_phy_offset = imx7d_ddrc_phy_lpddr3_setting, +}; + +static const struct imx7_pm_socdata imx7d_pm_data_ddr3 __initconst = { + .ddrc_compat = "fsl,imx7d-ddrc", + .src_compat = "fsl,imx7d-src", + .iomuxc_compat = "fsl,imx7d-iomuxc", + .gpc_compat = "fsl,imx7d-gpc", + .ddrc_num = ARRAY_SIZE(imx7d_ddrc_ddr3_setting), + .ddrc_offset = imx7d_ddrc_ddr3_setting, + .ddrc_phy_num = ARRAY_SIZE(imx7d_ddrc_phy_ddr3_setting), + .ddrc_phy_offset = imx7d_ddrc_phy_ddr3_setting, +}; + +/* + * This structure is for passing necessary data for low level ocram + * suspend code(arch/arm/mach-imx/suspend-imx7.S), if this struct + * definition is changed, the offset definition in + * arch/arm/mach-imx/suspend-imx7.S must be also changed accordingly, + * otherwise, the suspend to ocram function will be broken! + */ +struct imx7_cpu_pm_info { + u32 m4_reserve0; + u32 m4_reserve1; + u32 m4_reserve2; + phys_addr_t pbase; /* The physical address of pm_info. */ + phys_addr_t resume_addr; /* The physical resume address for asm code */ + u32 ddr_type; + u32 pm_info_size; /* Size of pm_info. */ + struct imx7_pm_base ddrc_base; + struct imx7_pm_base ddrc_phy_base; + struct imx7_pm_base src_base; + struct imx7_pm_base iomuxc_gpr_base; + struct imx7_pm_base ccm_base; + struct imx7_pm_base gpc_base; + struct imx7_pm_base snvs_base; + struct imx7_pm_base anatop_base; + struct imx7_pm_base lpsr_base; + struct imx7_pm_base gic_base; + u32 ttbr1; /* Store TTBR1 */ + u32 ddrc_num; /* Number of DDRC which need saved/restored. */ + u32 ddrc_val[MX7_MAX_DDRC_NUM][2]; /* To save offset and value */ + u32 ddrc_phy_num; /* Number of DDRC which need saved/restored. */ + u32 ddrc_phy_val[MX7_MAX_DDRC_NUM][2]; /* To save offset and value */ +} __aligned(8); + +static struct map_desc imx7_pm_io_desc[] __initdata = { + imx_map_entry(MX7D, AIPS1, MT_DEVICE), + imx_map_entry(MX7D, AIPS2, MT_DEVICE), + imx_map_entry(MX7D, AIPS3, MT_DEVICE), +}; + +static const char * const low_power_ocram_match[] __initconst = { + "fsl,lpm-sram", + NULL +}; + +static void imx7_gpio_save(void) +{ + u32 i; + + for (i = 0; i < 7; i++) { + gpio_reg[i][0] = readl_relaxed(gpio1_base + + (i << 16) + GPIO_DR); + gpio_reg[i][1] = readl_relaxed(gpio1_base + + (i << 16) + GPIO_GDIR); + gpio_reg[i][3] = readl_relaxed(gpio1_base + + (i << 16) + GPIO_ICR1); + gpio_reg[i][4] = readl_relaxed(gpio1_base + + (i << 16) + GPIO_ICR2); + gpio_reg[i][5] = readl_relaxed(gpio1_base + + (i << 16) + GPIO_IMR); + gpio_reg[i][7] = readl_relaxed(gpio1_base + + (i << 16) + GPIO_EDGE); + } +} + +static void imx7_gpio_restore(void) +{ + u32 i, val; + + for (i = 0; i < 7; i++) { + writel_relaxed(gpio_reg[i][1], gpio1_base + + (i << 16) + GPIO_GDIR); + writel_relaxed(gpio_reg[i][3], gpio1_base + + (i << 16) + GPIO_ICR1); + writel_relaxed(gpio_reg[i][4], gpio1_base + + (i << 16) + GPIO_ICR2); + writel_relaxed(gpio_reg[i][5], gpio1_base + + (i << 16) + GPIO_IMR); + writel_relaxed(gpio_reg[i][7], gpio1_base + + (i << 16) + GPIO_EDGE); + /* only restore output gpio value */ + val = readl_relaxed(gpio1_base + (i << 16) + GPIO_DR) | + (gpio_reg[i][0] & gpio_reg[i][1]); + writel_relaxed(val, gpio1_base + (i << 16) + GPIO_DR); + } +} + +static void imx7_ccm_save(void) +{ + u32 i; + + for (i = 0; i < MAX_CCM_LPCG; i++) + ccm_lpcg[i] = readl_relaxed(pm_info->ccm_base.vbase + + i * CCM_LPCG_STEP + CCM_LPCG_START); + pfd_a = readl_relaxed(pm_info->anatop_base.vbase + PFD_A_OFFSET); + pfd_b = readl_relaxed(pm_info->anatop_base.vbase + PFD_B_OFFSET); + + pll[0] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_ARM_OFFSET); + pll[1] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_DDR_OFFSET); + pll[2] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_DDR_SS_OFFSET); + pll[3] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_DDR_NUM_OFFSET); + pll[4] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_DDR_DENOM_OFFSET); + pll[5] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_480_OFFSET); + pll[6] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_ENET_OFFSET); + pll[7] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_AUDIO_OFFSET); + pll[8] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_AUDIO_SS_OFFSET); + pll[9] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_AUDIO_NUM_OFFSET); + pll[10] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_AUDIO_DENOM_OFFSET); + pll[11] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_VIDEO_OFFSET); + pll[12] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_VIDEO_SS_OFFSET); + pll[13] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_VIDEO_NUM_OFFSET); + pll[14] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_VIDEO_DENOM_OFFSET); + + /* enable all PLLs/PFDs for saving CCM root */ + writel_relaxed(0x1c000070, pm_info->anatop_base.vbase + + PLL_480_OFFSET + 0x8); + writel_relaxed(0x80808080, pm_info->anatop_base.vbase + + PFD_A_OFFSET + 0x8); + writel_relaxed(0x80808080, pm_info->anatop_base.vbase + + PFD_B_OFFSET + 0x8); + writel_relaxed(0x1fc0, pm_info->anatop_base.vbase + + PLL_ENET_OFFSET + 0x4); + writel_relaxed(0x12000, pm_info->anatop_base.vbase + + PLL_AUDIO_OFFSET); + writel_relaxed(0x12000, pm_info->anatop_base.vbase + + PLL_VIDEO_OFFSET); + + for (i = 0; i < sizeof(ccm_root) / 8; i++) + ccm_root[i][1] = readl_relaxed( + pm_info->ccm_base.vbase + ccm_root[i][0]); +} + +static void imx7_ccm_restore(void) +{ + u32 i, val; + + /* enable all PLLs/PFDs for restoring CCM root */ + writel_relaxed(0x1c000070, pm_info->anatop_base.vbase + + PLL_480_OFFSET + REG_CLR); + writel_relaxed(0x80808080, pm_info->anatop_base.vbase + + PFD_A_OFFSET + REG_CLR); + writel_relaxed(0x80808080, pm_info->anatop_base.vbase + + PFD_B_OFFSET + REG_CLR); + writel_relaxed(0x1fc0, pm_info->anatop_base.vbase + + PLL_ENET_OFFSET + REG_SET); + writel_relaxed(0x12000, pm_info->anatop_base.vbase + + PLL_AUDIO_OFFSET); + writel_relaxed(0x12000, pm_info->anatop_base.vbase + + PLL_VIDEO_OFFSET); + + for (i = 0; i < sizeof(ccm_root) / 8; i++) { + val = readl_relaxed(pm_info->ccm_base.vbase + ccm_root[i][0]); + /* restore post podf */ + val &= ~BM_CCM_ROOT_POST_PODF; + val |= ccm_root[i][1] & BM_CCM_ROOT_POST_PODF; + writel_relaxed(val, pm_info->ccm_base.vbase + ccm_root[i][0]); + /* resotre pre podf */ + val &= ~BM_CCM_ROOT_PRE_PODF; + val |= ccm_root[i][1] & BM_CCM_ROOT_PRE_PODF; + writel_relaxed(val, pm_info->ccm_base.vbase + ccm_root[i][0]); + /* restore mux */ + val &= ~BM_CCM_ROOT_MUX; + val |= ccm_root[i][1] & BM_CCM_ROOT_MUX; + writel_relaxed(val, pm_info->ccm_base.vbase + ccm_root[i][0]); + /* restore enable */ + val &= ~BM_CCM_ROOT_ENABLE; + val |= ccm_root[i][1] & BM_CCM_ROOT_ENABLE; + writel_relaxed(val, pm_info->ccm_base.vbase + ccm_root[i][0]); + } + + /* restore PLLs */ + writel_relaxed(pll[0], pm_info->anatop_base.vbase + + PLL_ARM_OFFSET); + writel_relaxed(pll[1], pm_info->anatop_base.vbase + + PLL_DDR_OFFSET); + writel_relaxed(pll[2], pm_info->anatop_base.vbase + + PLL_DDR_SS_OFFSET); + writel_relaxed(pll[3], pm_info->anatop_base.vbase + + PLL_DDR_NUM_OFFSET); + writel_relaxed(pll[4], pm_info->anatop_base.vbase + + PLL_DDR_DENOM_OFFSET); + writel_relaxed(pll[5], pm_info->anatop_base.vbase + + PLL_480_OFFSET); + writel_relaxed(pll[6], pm_info->anatop_base.vbase + + PLL_ENET_OFFSET); + writel_relaxed(pll[7], pm_info->anatop_base.vbase + + PLL_AUDIO_OFFSET); + writel_relaxed(pll[8], pm_info->anatop_base.vbase + + PLL_AUDIO_SS_OFFSET); + writel_relaxed(pll[9], pm_info->anatop_base.vbase + + PLL_AUDIO_NUM_OFFSET); + writel_relaxed(pll[10], pm_info->anatop_base.vbase + + PLL_AUDIO_DENOM_OFFSET); + writel_relaxed(pll[11], pm_info->anatop_base.vbase + + PLL_VIDEO_OFFSET); + writel_relaxed(pll[12], pm_info->anatop_base.vbase + + PLL_VIDEO_SS_OFFSET); + writel_relaxed(pll[13], pm_info->anatop_base.vbase + + PLL_VIDEO_NUM_OFFSET); + writel_relaxed(pll[14], pm_info->anatop_base.vbase + + PLL_VIDEO_DENOM_OFFSET); + + for (i = 0; i < MAX_CCM_LPCG; i++) + writel_relaxed(ccm_lpcg[i], pm_info->ccm_base.vbase + + i * CCM_LPCG_STEP + CCM_LPCG_START); + /* restore PFDs */ + writel_relaxed(pfd_a & 0x80808080, + pm_info->anatop_base.vbase + PFD_A_OFFSET + REG_SET); + writel_relaxed(pfd_a, pm_info->anatop_base.vbase + PFD_A_OFFSET); + + writel_relaxed(pfd_b & 0x80808080, + pm_info->anatop_base.vbase + PFD_B_OFFSET + REG_SET); + writel_relaxed(pfd_b, pm_info->anatop_base.vbase + PFD_B_OFFSET); +} + +static void imx7_sys_counter_save(void) +{ + sys_ctrl_reg = readl_relaxed(system_counter_ctrl_base); + sys_cmp_reg = readl_relaxed(system_counter_cmp_base); +} + +static void imx7_sys_counter_restore(void) +{ + writel_relaxed(sys_ctrl_reg, system_counter_ctrl_base); + writel_relaxed(sys_cmp_reg, system_counter_cmp_base); +} + +static void imx7_gpt_save(void) +{ + gpt1_regs[0] = readl_relaxed(gpt1_base + GPT_CR); + gpt1_regs[1] = readl_relaxed(gpt1_base + GPT_PR); + gpt1_regs[2] = readl_relaxed(gpt1_base + GPT_IR); +} + +static void imx7_gpt_restore(void) +{ + writel_relaxed(gpt1_regs[0], gpt1_base + GPT_CR); + writel_relaxed(gpt1_regs[1], gpt1_base + GPT_PR); + writel_relaxed(gpt1_regs[2], gpt1_base + GPT_IR); +} + +static void imx7_iomuxc_gpr_save(void) +{ + u32 i; + + for (i = 0; i < MAX_IOMUXC_GPR; i++) + iomuxc_gpr[i] = readl_relaxed( + pm_info->iomuxc_gpr_base.vbase + i * 4); +} + +static void imx7_iomuxc_gpr_restore(void) +{ + u32 i; + + for (i = 0; i < MAX_IOMUXC_GPR; i++) + writel_relaxed(iomuxc_gpr[i], + pm_info->iomuxc_gpr_base.vbase + i * 4); +} + +static void imx7_console_save(unsigned int *regs) +{ + if (!console_base) + return; + + regs[0] = readl_relaxed(console_base + UART_UCR1); + regs[1] = readl_relaxed(console_base + UART_UCR2); + regs[2] = readl_relaxed(console_base + UART_UCR3); + regs[3] = readl_relaxed(console_base + UART_UCR4); + regs[4] = readl_relaxed(console_base + UART_UFCR); + regs[5] = readl_relaxed(console_base + UART_UESC); + regs[6] = readl_relaxed(console_base + UART_UTIM); + regs[7] = readl_relaxed(console_base + UART_UBIR); + regs[8] = readl_relaxed(console_base + UART_UBMR); + regs[9] = readl_relaxed(console_base + UART_UTS); +} + +static void imx7_console_io_save(void) +{ + /* save uart1 io, driver resume is too late */ + uart1_io[0] = readl_relaxed(iomuxc_base + UART_RX_IO); + uart1_io[1] = readl_relaxed(iomuxc_base + UART_RX_PAD); + uart1_io[2] = readl_relaxed(iomuxc_base + UART_TX_IO); + uart1_io[3] = readl_relaxed(iomuxc_base + UART_TX_PAD); +} + +static void imx7_console_restore(unsigned int *regs) +{ + if (!console_base) + return; + + writel_relaxed(regs[4], console_base + UART_UFCR); + writel_relaxed(regs[5], console_base + UART_UESC); + writel_relaxed(regs[6], console_base + UART_UTIM); + writel_relaxed(regs[7], console_base + UART_UBIR); + writel_relaxed(regs[8], console_base + UART_UBMR); + writel_relaxed(regs[9], console_base + UART_UTS); + writel_relaxed(regs[0], console_base + UART_UCR1); + writel_relaxed(regs[1] | 0x1, console_base + UART_UCR2); + writel_relaxed(regs[2], console_base + UART_UCR3); + writel_relaxed(regs[3], console_base + UART_UCR4); +} + +static void imx7_console_io_restore(void) +{ + /* restore uart1 io */ + writel_relaxed(uart1_io[0], iomuxc_base + UART_RX_IO); + writel_relaxed(uart1_io[1], iomuxc_base + UART_RX_PAD); + writel_relaxed(uart1_io[2], iomuxc_base + UART_TX_IO); + writel_relaxed(uart1_io[3], iomuxc_base + UART_TX_PAD); +} + +#define MX7D_SUSPEND_POWERDWN_PARAM \ + ((0 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \ + (1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \ + (PSCI_POWER_STATE_TYPE_POWER_DOWN << PSCI_0_2_POWER_STATE_TYPE_SHIFT)) + +#define MX7D_SUSPEND_STANDBY_PARAM \ + ((0 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \ + (1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \ + (PSCI_POWER_STATE_TYPE_STANDBY << PSCI_0_2_POWER_STATE_TYPE_SHIFT)) + +static int imx7_suspend_finish(unsigned long val) +{ + u32 state; + + if (val == 0) + state = MX7D_SUSPEND_POWERDWN_PARAM; + else + state = MX7D_SUSPEND_STANDBY_PARAM; + + if (psci_ops.cpu_suspend) { + return psci_ops.cpu_suspend(state, __pa(cpu_resume)); + } + + if (!imx7_suspend_in_ocram_fn) { + cpu_do_idle(); + } else { + /* + * call low level suspend function in ocram, + * as we need to float DDR IO. + */ + local_flush_tlb_all(); + imx7_suspend_in_ocram_fn(suspend_ocram_base); + } + + return 0; +} + +static void imx7_pm_set_lpsr_resume_addr(unsigned long addr) +{ + writel_relaxed(addr, pm_info->lpsr_base.vbase); +} + +static int imx7_pm_is_resume_from_lpsr(void) +{ + return readl_relaxed(lpsr_base); +} + +static int imx7_pm_enter(suspend_state_t state) +{ + unsigned int console_saved_reg[10] = {0}; + u32 val; + + if (!iram_tlb_base_addr) { + pr_warn("No IRAM/OCRAM memory allocated for suspend/resume \ + code. Please ensure device tree has an entry for \ + fsl,lpm-sram.\n"); + return -EINVAL; + } + + /* + * arm_arch_timer driver requires system counter to be + * a clock source with CLOCK_SOURCE_SUSPEND_NONSTOP flag + * set, which means hardware system counter needs to keep + * running during suspend, as the base clock for system + * counter is 24MHz which will be disabled in STOP mode, + * so we need to switch system counter's clock to alternate + * (lower) clock, it is based on 32K, from block guide, there + * is no special flow needs to be followed, system counter + * hardware will handle the clock transition. + */ + val = readl_relaxed(system_counter_ctrl_base); + val &= ~BM_SYS_COUNTER_CNTCR_FCR0; + val |= BM_SYS_COUNTER_CNTCR_FCR1; + writel_relaxed(val, system_counter_ctrl_base); + while (!(readl_relaxed(system_counter_ctrl_base + SYS_COUNTER_CNTSR) + & BM_SYS_COUNTER_CNTSR_FCR1)) + ; + + switch (state) { + case PM_SUSPEND_STANDBY: + imx_anatop_pre_suspend(); + imx_gpcv2_pre_suspend(false); + + /* Zzz ... */ + if (psci_ops.cpu_suspend) + cpu_suspend(1, imx7_suspend_finish); + else + imx7_suspend_in_ocram_fn(suspend_ocram_base); + + imx_anatop_post_resume(); + imx_gpcv2_post_resume(); + break; + case PM_SUSPEND_MEM: + imx_anatop_pre_suspend(); + imx_gpcv2_pre_suspend(true); + if (imx_gpcv2_is_mf_mix_off()) { + /* + * per design requirement, EXSC for PCIe/EIM/PXP + * will need clock to recover RDC setting on + * resume, so enable PCIe/EIM LPCG for RDC + * recovery when M/F mix off + */ + writel_relaxed(0x3, pm_info->ccm_base.vbase + + CCM_EIM_LPCG); + writel_relaxed(0x3, pm_info->ccm_base.vbase + + CCM_PXP_LPCG); + writel_relaxed(0x3, pm_info->ccm_base.vbase + + CCM_PCIE_LPCG); + /* stop m4 if mix will also be shutdown */ + if (imx_src_is_m4_enabled() && imx_mu_is_m4_in_stop()) { + writel(M4_RCR_HALT, + pm_info->src_base.vbase + M4RCR); + imx_gpcv2_enable_wakeup_for_m4(); + } + imx7_console_save(console_saved_reg); + memcpy(ocram_saved_in_ddr, ocram_base, ocram_size); + if (lpsr_enabled) { + imx7_pm_set_lpsr_resume_addr(pm_info->resume_addr); + imx7_console_io_save(); + memcpy(lpm_ocram_saved_in_ddr, lpm_ocram_base, + lpm_ocram_size); + imx7_iomuxc_gpr_save(); + imx7_ccm_save(); + imx7_gpt_save(); + imx7_sys_counter_save(); + imx7_gpio_save(); + } + } + + /* Zzz ... */ + cpu_suspend(0, imx7_suspend_finish); + + if (imx7_pm_is_resume_from_lpsr()) { + imx7_console_io_restore(); + memcpy(lpm_ocram_base, lpm_ocram_saved_in_ddr, + lpm_ocram_size); + imx7_iomuxc_gpr_restore(); + imx7_ccm_restore(); + imx7_gpt_restore(); + imx7_sys_counter_restore(); + imx7_gpio_restore(); + imx7d_enable_rcosc(); + } + if (imx_gpcv2_is_mf_mix_off() || + imx7_pm_is_resume_from_lpsr()) { + writel_relaxed(0x0, pm_info->ccm_base.vbase + + CCM_EIM_LPCG); + writel_relaxed(0x0, pm_info->ccm_base.vbase + + CCM_PXP_LPCG); + writel_relaxed(0x0, pm_info->ccm_base.vbase + + CCM_PCIE_LPCG); + memcpy(ocram_base, ocram_saved_in_ddr, ocram_size); + imx7_console_restore(console_saved_reg); + if (imx_src_is_m4_enabled() && imx_mu_is_m4_in_stop()) { + imx_gpcv2_disable_wakeup_for_m4(); + /* restore M4 image */ + memcpy(lpm_m4tcm_base, + lpm_m4tcm_saved_in_ddr, SZ_32K); + /* kick m4 to enable */ + writel(M4_RCR_GO, + pm_info->src_base.vbase + M4RCR); + /* offset high bus count for m4 image */ + request_bus_freq(BUS_FREQ_HIGH); + /* restore M4 to run mode */ + imx_mu_set_m4_run_mode(); + /* gpc wakeup */ + } + } + /* clear LPSR resume address */ + imx7_pm_set_lpsr_resume_addr(0); + imx_anatop_post_resume(); + imx_gpcv2_post_resume(); + break; + default: + return -EINVAL; + } + + /* restore system counter's clock to base clock */ + val = readl_relaxed(system_counter_ctrl_base); + val &= ~BM_SYS_COUNTER_CNTCR_FCR1; + val |= BM_SYS_COUNTER_CNTCR_FCR0; + writel_relaxed(val, system_counter_ctrl_base); + while (!(readl_relaxed(system_counter_ctrl_base + SYS_COUNTER_CNTSR) + & BM_SYS_COUNTER_CNTSR_FCR0)) + ; + + return 0; +} + +static int imx7_pm_valid(suspend_state_t state) +{ + return state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM; +} + +static const struct platform_suspend_ops imx7_pm_ops = { + .enter = imx7_pm_enter, + .valid = imx7_pm_valid, +}; + +void __init imx7_pm_set_ccm_base(void __iomem *base) +{ + ccm_base = base; +} + +static struct map_desc iram_tlb_io_desc __initdata = { + /* .virtual and .pfn are run-time assigned */ + .length = SZ_1M, + .type = MT_MEMORY_RWX_NONCACHED, +}; + +static int __init imx7_dt_find_lpsram(unsigned long node, const char *uname, + int depth, void *data) +{ + unsigned long lpram_addr; + const __be32 *prop = of_get_flat_dt_prop(node, "reg", NULL); + + if (of_flat_dt_match(node, low_power_ocram_match)) { + if (!prop) + return -EINVAL; + + lpram_addr = be32_to_cpup(prop); + + /* We need to create a 1M page table entry. */ + iram_tlb_io_desc.virtual = IMX_IO_P2V(lpram_addr & 0xFFF00000); + iram_tlb_io_desc.pfn = __phys_to_pfn(lpram_addr & 0xFFF00000); + iram_tlb_phys_addr = lpram_addr; + iram_tlb_base_addr = IMX_IO_P2V(lpram_addr); + iotable_init(&iram_tlb_io_desc, 1); + } + + return 0; +} + +void __init imx7_pm_map_io(void) +{ + unsigned long i, j; + + iotable_init(imx7_pm_io_desc, ARRAY_SIZE(imx7_pm_io_desc)); + /* + * Get the address of IRAM or OCRAM to be used by the low + * power code from the device tree. + */ + WARN_ON(of_scan_flat_dt(imx7_dt_find_lpsram, NULL)); + + /* Return if no IRAM space is allocated for suspend/resume code. */ + if (!iram_tlb_base_addr) { + pr_warn("No valid ocram available for suspend/resume!\n"); + return; + } + + /* TODO: Handle M4 in TEE? */ + /* Set all entries to 0 except first 3 words reserved for M4. */ + memset((void *)(iram_tlb_base_addr + M4_OCRAMS_RESERVED_SIZE), + 0, MX7_IRAM_TLB_SIZE - M4_OCRAMS_RESERVED_SIZE); + + /* + * Make sure the IRAM virtual address has a mapping in the IRAM + * page table. + * + * Only use the top 12 bits [31-20] when storing the physical + * address in the page table as only these bits are required + * for 1M mapping. + */ + j = ((iram_tlb_base_addr >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + (iram_tlb_phys_addr & 0xFFF00000) | TT_ATTRIB_NON_CACHEABLE_1M; + + /* + * Make sure the AIPS1 virtual address has a mapping in the + * IRAM page table. + */ + for (i = 0; i < 4; i++) { + j = ((IMX_IO_P2V(MX7D_AIPS1_BASE_ADDR + i * 0x100000) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + ((MX7D_AIPS1_BASE_ADDR + i * 0x100000) & 0xFFF00000) | + TT_ATTRIB_NON_CACHEABLE_1M; + } + + /* + * Make sure the AIPS2 virtual address has a mapping in the + * IRAM page table. + */ + for (i = 0; i < 4; i++) { + j = ((IMX_IO_P2V(MX7D_AIPS2_BASE_ADDR + i * 0x100000) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + ((MX7D_AIPS2_BASE_ADDR + i * 0x100000) & 0xFFF00000) | + TT_ATTRIB_NON_CACHEABLE_1M; + } + + /* + * Make sure the AIPS3 virtual address has a mapping + * in the IRAM page table. + */ + for (i = 0; i < 4; i++) { + j = ((IMX_IO_P2V(MX7D_AIPS3_BASE_ADDR + i * 0x100000) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + ((MX7D_AIPS3_BASE_ADDR + i * 0x100000) & 0xFFF00000) | + TT_ATTRIB_NON_CACHEABLE_1M; + } + + /* + * Make sure the GIC virtual address has a mapping in the + * IRAM page table. + */ + j = ((IMX_IO_P2V(MX7D_GIC_BASE_ADDR) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + (MX7D_GIC_BASE_ADDR & 0xFFF00000) | TT_ATTRIB_NON_CACHEABLE_1M; +} + +static int __init imx7_suspend_init(const struct imx7_pm_socdata *socdata) +{ + const u32 (*ddrc_offset_array)[2]; + const u32 (*ddrc_phy_offset_array)[2]; + unsigned long iram_paddr; + int i; + + suspend_set_ops(&imx7_pm_ops); + + if (!socdata) { + pr_warn("%s: invalid argument!\n", __func__); + return -EINVAL; + } + + /* + * 16KB is allocated for IRAM TLB, but only up 8k is for kernel TLB, + * The lower 8K is not used, so use the lower 8K for IRAM code and + * pm_info. + * + */ + iram_paddr = iram_tlb_phys_addr + MX7_SUSPEND_IRAM_ADDR_OFFSET; + + /* Make sure iram_paddr is 8 byte aligned. */ + if ((uintptr_t)(iram_paddr) & (FNCPY_ALIGN - 1)) + iram_paddr += FNCPY_ALIGN - iram_paddr % (FNCPY_ALIGN); + + /* Get the virtual address of the suspend code. */ + suspend_ocram_base = (void *)IMX_IO_P2V(iram_paddr); + + if (psci_ops.cpu_suspend) { + pm_info = kmalloc(sizeof(*pm_info), GFP_KERNEL); + if (!pm_info) + return -ENOMEM; + } else { + pm_info = suspend_ocram_base; + } + /* pbase points to iram_paddr. */ + pm_info->pbase = iram_paddr; + pm_info->resume_addr = virt_to_phys(ca7_cpu_resume); + pm_info->pm_info_size = sizeof(*pm_info); + + /* + * ccm physical address is not used by asm code currently, + * so get ccm virtual address directly, as we already have + * it from ccm driver. + */ + pm_info->ccm_base.pbase = MX7D_CCM_BASE_ADDR; + pm_info->ccm_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_CCM_BASE_ADDR); + + pm_info->ddrc_base.pbase = MX7D_DDRC_BASE_ADDR; + pm_info->ddrc_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_DDRC_BASE_ADDR); + + pm_info->ddrc_phy_base.pbase = MX7D_DDRC_PHY_BASE_ADDR; + pm_info->ddrc_phy_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_DDRC_PHY_BASE_ADDR); + + pm_info->src_base.pbase = MX7D_SRC_BASE_ADDR; + pm_info->src_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_SRC_BASE_ADDR); + + pm_info->iomuxc_gpr_base.pbase = MX7D_IOMUXC_GPR_BASE_ADDR; + pm_info->iomuxc_gpr_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_IOMUXC_GPR_BASE_ADDR); + + pm_info->gpc_base.pbase = MX7D_GPC_BASE_ADDR; + pm_info->gpc_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_GPC_BASE_ADDR); + + pm_info->anatop_base.pbase = MX7D_ANATOP_BASE_ADDR; + pm_info->anatop_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_ANATOP_BASE_ADDR); + + pm_info->snvs_base.pbase = MX7D_SNVS_BASE_ADDR; + pm_info->snvs_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_SNVS_BASE_ADDR); + + pm_info->lpsr_base.pbase = MX7D_LPSR_BASE_ADDR; + lpsr_base = pm_info->lpsr_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_LPSR_BASE_ADDR); + + pm_info->gic_base.pbase = MX7D_GIC_BASE_ADDR; + pm_info->gic_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_GIC_BASE_ADDR); + + pm_info->ddrc_num = socdata->ddrc_num; + ddrc_offset_array = socdata->ddrc_offset; + pm_info->ddrc_phy_num = socdata->ddrc_phy_num; + ddrc_phy_offset_array = socdata->ddrc_phy_offset; + + /* initialize DDRC settings */ + for (i = 0; i < pm_info->ddrc_num; i++) { + pm_info->ddrc_val[i][0] = ddrc_offset_array[i][0]; + if (ddrc_offset_array[i][1] == READ_DATA_FROM_HARDWARE) + pm_info->ddrc_val[i][1] = + readl_relaxed(pm_info->ddrc_base.vbase + + ddrc_offset_array[i][0]); + else + pm_info->ddrc_val[i][1] = ddrc_offset_array[i][1]; + + if (pm_info->ddrc_val[i][0] == 0xd0) + pm_info->ddrc_val[i][1] |= 0xc0000000; + } + + /* initialize DDRC PHY settings */ + for (i = 0; i < pm_info->ddrc_phy_num; i++) { + pm_info->ddrc_phy_val[i][0] = + ddrc_phy_offset_array[i][0]; + if (ddrc_phy_offset_array[i][1] == READ_DATA_FROM_HARDWARE) + pm_info->ddrc_phy_val[i][1] = + readl_relaxed(pm_info->ddrc_phy_base.vbase + + ddrc_phy_offset_array[i][0]); + else + pm_info->ddrc_phy_val[i][1] = + ddrc_phy_offset_array[i][1]; + } + + if (psci_ops.cpu_suspend) + return 0; + + imx7_suspend_in_ocram_fn = fncpy( + suspend_ocram_base + sizeof(*pm_info), + &imx7_suspend, + MX7_SUSPEND_OCRAM_SIZE - sizeof(*pm_info)); + + return 0; +} + +static void __init imx7_pm_common_init(const struct imx7_pm_socdata + *socdata) +{ + int ret; + struct regmap *gpr; + + if (IS_ENABLED(CONFIG_SUSPEND)) { + ret = imx7_suspend_init(socdata); + if (ret) + pr_warn("%s: No DDR LPM support with suspend %d!\n", + __func__, ret); + } + + /* + * Force IOMUXC irq pending, so that the interrupt to GPC can be + * used to deassert dsm_request signal when the signal gets + * asserted unexpectedly. + */ + gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr"); + if (!IS_ERR(gpr)) + regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_IRQ_MASK, + IMX7D_GPR1_IRQ_MASK); +} + +void __init imx7d_pm_init(void) +{ + struct device_node *np; + struct resource res; + if (imx_src_is_m4_enabled()) { + /* map the 32K of M4 TCM */ + np = of_find_node_by_path( + "/tcml@007f8000"); + if (np) + lpm_m4tcm_base = of_iomap(np, 0); + WARN_ON(!lpm_m4tcm_base); + + /* map the m4 bootrom from dtb */ + np = of_find_node_by_path( + "/soc/sram@00180000"); + if (np) + m4_bootrom_base = of_iomap(np, 0); + WARN_ON(!m4_bootrom_base); + + lpm_m4tcm_saved_in_ddr = kzalloc(SZ_32K, GFP_KERNEL); + WARN_ON(!lpm_m4tcm_saved_in_ddr); + + /* save M4 Image to DDR */ + memcpy(lpm_m4tcm_saved_in_ddr, lpm_m4tcm_base, SZ_32K); + } + np = of_find_compatible_node(NULL, NULL, "fsl,lpm-sram"); + if (of_get_property(np, "fsl,enable-lpsr", NULL)) + lpsr_enabled = true; + + if (psci_ops.cpu_suspend) + lpsr_enabled = false; + + if (lpsr_enabled) { + pr_info("LPSR mode enabled, DSM will go into LPSR mode!\n"); + lpm_ocram_base = of_iomap(np, 0); + WARN_ON(!lpm_ocram_base); + WARN_ON(of_address_to_resource(np, 0, &res)); + lpm_ocram_size = resource_size(&res); + lpm_ocram_saved_in_ddr = kzalloc(lpm_ocram_size, GFP_KERNEL); + WARN_ON(!lpm_ocram_saved_in_ddr); + + np = of_find_node_by_path( + "/soc/aips-bus@30000000/iomuxc@30330000"); + if (np) + iomuxc_base = of_iomap(np, 0); + WARN_ON(!iomuxc_base); + + np = of_find_node_by_path( + "/soc/aips-bus@30000000/gpt@302d0000"); + if (np) + gpt1_base = of_iomap(np, 0); + WARN_ON(!gpt1_base); + + np = of_find_node_by_path( + "/soc/aips-bus@30400000/system-counter-cmp@306b0000"); + if (np) + system_counter_cmp_base = of_iomap(np, 0); + WARN_ON(!system_counter_cmp_base); + + np = of_find_node_by_path( + "/soc/aips-bus@30000000/gpio@30200000"); + if (np) + gpio1_base = of_iomap(np, 0); + WARN_ON(!gpio1_base); + } + + np = of_find_node_by_path( + "/soc/aips-bus@30400000/system-counter-ctrl@306c0000"); + if (np) + system_counter_ctrl_base = of_iomap(np, 0); + WARN_ON(!system_counter_ctrl_base); + + if (imx_ddrc_get_ddr_type() == IMX_DDR_TYPE_LPDDR3 + || imx_ddrc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) + imx7_pm_common_init(&imx7d_pm_data_lpddr3); + else if (imx_ddrc_get_ddr_type() == IMX_DDR_TYPE_DDR3) + imx7_pm_common_init(&imx7d_pm_data_ddr3); + + np = of_find_compatible_node(NULL, NULL, "fsl,mega-fast-sram"); + ocram_base = of_iomap(np, 0); + WARN_ON(!ocram_base); + WARN_ON(of_address_to_resource(np, 0, &res)); + ocram_size = resource_size(&res); + ocram_saved_in_ddr = kzalloc(ocram_size, GFP_KERNEL); + WARN_ON(!ocram_saved_in_ddr); + + np = of_find_node_by_path( + "/soc/aips-bus@30800000/spba-bus@30800000/serial@30860000"); + if (np) + console_base = of_iomap(np, 0); + + /* clear LPSR resume address first */ + imx7_pm_set_lpsr_resume_addr(0); +} diff --git a/arch/arm/mach-imx/pm-imx7ulp.c b/arch/arm/mach-imx/pm-imx7ulp.c index 7b2f7387e6626e..c821642317ecea 100644 --- a/arch/arm/mach-imx/pm-imx7ulp.c +++ b/arch/arm/mach-imx/pm-imx7ulp.c @@ -5,64 +5,814 @@ * Author: Dong Aisheng */ +#include +#include +#include #include +#include +#include +#include +#include #include #include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include #include "common.h" +#include "hardware.h" + +#define MU_SR 0x60 + +#define PMPROT 0x8 +#define PMCTRL 0x10 +#define PMSTAT 0x18 +#define SRS 0x20 +#define RPC 0x24 +#define SSRS 0x28 +#define SRIE 0x2c +#define SRIF 0x30 +#define CSRE 0x34 +#define MR 0x40 + +#define PMC1_HSRUN 0x4 +#define PMC1_RUN 0x8 +#define PMC1_VLPR 0xc +#define PMC1_STOP 0x10 +#define PMC1_VLPS 0x14 +#define PMC1_LLS 0x18 +#define PMC1_VLLS 0x1c +#define PMC1_STATUS 0x20 +#define PMC1_CTRL 0x24 +#define PMC0_CTRL 0x28 + +#define BM_PMPROT_AHSRUN (1 << 7) +#define BM_PMPROT_AVLP (1 << 5) +#define BM_PMPROT_ALLS (1 << 3) +#define BM_PMPROT_AVLLS (1 << 1) + +#define BM_PMCTRL_STOPA (1 << 24) +#define BM_PMCTRL_PSTOPO (3 << 16) +#define BM_PMCTRL_RUNM (3 << 8) +#define BM_PMCTRL_STOPM (7 << 0) + +#define BM_VLPS_RBBEN (1 << 28) + +#define BM_CTRL_LDOEN (1 << 31) +#define BM_CTRL_LDOOKDIS (1 << 30) + +#define BM_VLLS_MON1P2HVDHP (1 << 5) +#define BM_VLLS_MON1P2LVDHP (1 << 4) -#define SMC_PMCTRL 0x10 -#define BP_PMCTRL_PSTOPO 16 -#define PSTOPO_PSTOP3 0x3 -#define PSTOPO_PSTOP2 0x2 -#define PSTOPO_PSTOP1 0x1 -#define BP_PMCTRL_RUNM 8 -#define RUNM_RUN 0 #define BP_PMCTRL_STOPM 0 -#define STOPM_STOP 0 +#define BP_PMCTRL_PSTOPO 16 + +#define MX7ULP_MAX_MMDC_IO_NUM 64 +#define MX7ULP_MAX_MMDC_NUM 50 +#define MX7ULP_MAX_IOMUX_NUM 116 +#define MX7ULP_MAX_SELECT_INPUT_NUM 78 + +#define IOMUX_START 0x0 +#define SELECT_INPUT_START 0x200 -#define BM_PMCTRL_PSTOPO (3 << BP_PMCTRL_PSTOPO) -#define BM_PMCTRL_RUNM (3 << BP_PMCTRL_RUNM) -#define BM_PMCTRL_STOPM (7 << BP_PMCTRL_STOPM) +#define TPM_SC 0x10 +#define TPM_MOD 0x18 +#define TPM_C0SC 0x20 +#define TPM_C0V 0x24 + +#define PCC2_ENABLE_PCS_FIRC ((1 << 30) | (3 << 24)) +#define PCC2_ENABLE (1 << 30) + +#define LPUART_BAUD 0x10 +#define LPUART_CTRL 0x18 +#define LPUART_FIFO 0x28 +#define LPUART_WATER 0x2c + +#define GPIO_PDOR 0x0 +#define GPIO_PDDR 0x14 + +#define PTC2_LPUART4_TX_OFFSET 0x8 +#define PTC3_LPUART4_RX_OFFSET 0xc +#define PTC2_LPUART4_TX_INPUT_OFFSET 0x248 +#define PTC3_LPUART4_RX_INPUT_OFFSET 0x24c +#define LPUART4_MUX_VALUE (4 << 8) +#define LPUART4_INPUT_VALUE (1) + +#define MU_B_SR_NMIC (1 << 3) + +#define DGO_GPR3 0x60 +#define DGO_GPR4 0x64 + +#define ADDR_1M_MASK 0xFFF00000 static void __iomem *smc1_base; +static void __iomem *pmc0_base; +static void __iomem *pmc1_base; +static void __iomem *tpm5_base; +static void __iomem *lpuart4_base; +static void __iomem *iomuxc1_base; +static void __iomem *pcc2_base; +static void __iomem *pcc3_base; +static void __iomem *mu_base; +static void __iomem *scg1_base; +static void __iomem *gpio_base[4]; +static void __iomem *suspend_ocram_base; +static void (*imx7ulp_suspend_in_ocram_fn)(void __iomem *sram_base); + +static u32 tpm5_regs[4]; +static u32 lpuart4_regs[4]; +static u32 pcc2_regs[24][2] = { + {0x20, 0}, {0x3c, 0}, {0x40, 0}, {0x6c, 0}, + {0x84, 0}, {0x90, 0}, {0x94, 0}, {0x98, 0}, + {0x9c, 0}, {0xa4, 0}, {0xa8, 0}, {0xac, 0}, + {0xb0, 0}, {0xb4, 0}, {0xb8, 0}, {0xc4, 0}, + {0xcc, 0}, {0xd0, 0}, {0xd4, 0}, {0xd8, 0}, + {0xdc, 0}, {0xe0, 0}, {0xf4, 0}, {0x10c, 0}, +}; + +static u32 pcc3_regs[16][2] = { + {0x84, 0}, {0x88, 0}, {0x90, 0}, {0x94, 0}, + {0x98, 0}, {0x9c, 0}, {0xa0, 0}, {0xa4, 0}, + {0xa8, 0}, {0xac, 0}, {0xb8, 0}, {0xbc, 0}, + {0xc0, 0}, {0xc4, 0}, {0x140, 0}, {0x144, 0}, +}; + +static u32 scg1_offset[17] = { + 0x14, 0x30, 0x40, 0x304, + 0x500, 0x504, 0x508, 0x50c, + 0x510, 0x514, 0x600, 0x604, + 0x608, 0x60c, 0x610, 0x614, + 0x104, +}; + +extern unsigned long iram_tlb_base_addr; +extern unsigned long iram_tlb_phys_addr; + +/* + * suspend ocram space layout: + * ======================== high address ====================== + * . + * . + * . + * ^ + * ^ + * ^ + * imx7ulp_suspend code + * PM_INFO structure(imx7ulp_cpu_pm_info) + * ======================== low address ======================= + */ +struct imx7ulp_pm_socdata { + u32 ddr_type; + const char *mmdc_compat; + const u32 mmdc_io_num; + const u32 *mmdc_io_offset; + const u32 mmdc_num; + const u32 *mmdc_offset; +}; + +static const u32 imx7ulp_mmdc_io_lpddr3_offset[] __initconst = { + 0x0, 0x4, 0x8, 0xc, + 0x10, 0x14, 0x18, 0x1c, + 0x20, 0x24, 0x28, 0x2c, + 0x30, 0x34, 0x38, 0x3c, + 0x40, 0x44, 0x48, 0x4c, + 0x50, 0x54, 0x58, 0x5c, + 0x60, 0x64, 0x68, 0x6c, + 0x70, 0x74, 0x78, 0x7c, + 0x80, 0x84, 0x88, 0x8c, + 0x90, 0x94, 0x98, 0x9c, + 0xa0, 0xa4, 0xa8, 0xac, + 0xb0, 0xb4, 0xb8, 0xbc, + 0xc0, 0xc4, 0xc8, 0xcc, + 0xd0, 0xd4, 0xd8, 0xdc, + 0xe8, 0xf8, 0xfc, 0x120, + 0x124, +}; + +static const u32 imx7ulp_mmdc_lpddr3_offset[] __initconst = { + 0x01c, 0x800, 0x85c, 0x890, + 0x848, 0x850, 0x81c, 0x820, + 0x824, 0x828, 0x82c, 0x830, + 0x834, 0x838, 0x8c0, 0x8b8, + 0x004, 0x00c, 0x010, 0x038, + 0x014, 0x018, 0x02c, 0x030, + 0x040, 0x000, 0x01c, 0x01c, + 0x01c, 0x01c, 0x01c, 0x01c, + 0x01c, 0x01c, 0x01c, 0x01c, + 0x01c, 0x01c, 0x83c, 0x020, + 0x800, 0x004, 0x404, 0x01c, +}; + +static const u32 imx7ulp_lpddr3_script[] __initconst = { + 0x00008000, 0xA1390003, 0x0D3900A0, 0x00400000, + 0x40404040, 0x40404040, 0x33333333, 0x33333333, + 0x33333333, 0x33333333, 0xf3333333, 0xf3333333, + 0xf3333333, 0xf3333333, 0x24922492, 0x00000800, + 0x00020052, 0x292C42F3, 0x00100A22, 0x00120556, + 0x00C700DB, 0x00211718, 0x0F9F26D2, 0x009F0E10, + 0x0000003F, 0xC3190000, 0x00008050, 0x00008058, + 0x003F8030, 0x003F8038, 0xFF0A8030, 0xFF0A8038, + 0x04028030, 0x04028038, 0x83018030, 0x83018038, + 0x01038030, 0x01038038, 0x20000000, 0x00001800, + 0xA1310000, 0x00020052, 0x00011006, 0x00000000, +}; + +static const struct imx7ulp_pm_socdata imx7ulp_lpddr3_pm_data __initconst = { + .mmdc_compat = "fsl,imx7ulp-mmdc", + .mmdc_io_num = ARRAY_SIZE(imx7ulp_mmdc_io_lpddr3_offset), + .mmdc_io_offset = imx7ulp_mmdc_io_lpddr3_offset, + .mmdc_num = ARRAY_SIZE(imx7ulp_mmdc_lpddr3_offset), + .mmdc_offset = imx7ulp_mmdc_lpddr3_offset, +}; + +/* + * This structure is for passing necessary data for low level ocram + * suspend code(arch/arm/mach-imx/suspend-imx7ulp.S), if this struct + * definition is changed, the offset definition in + * arch/arm/mach-imx/suspend-imx7ulp.S must be also changed accordingly, + * otherwise, the suspend to sram function will be broken! + */ +struct imx7ulp_cpu_pm_info { + u32 m4_reserve0; + u32 m4_reserve1; + u32 m4_reserve2; + phys_addr_t pbase; /* The physical address of pm_info. */ + phys_addr_t resume_addr; /* The physical resume address for asm code */ + u32 pm_info_size; /* Size of pm_info. */ + void __iomem *sim_base; + void __iomem *scg1_base; + void __iomem *mmdc_base; + void __iomem *mmdc_io_base; + void __iomem *smc1_base; + u32 scg1[17]; + u32 ttbr1; /* Store TTBR1 */ + u32 gpio[4][2]; + u32 iomux_num; /* Number of IOs which need saved/restored. */ + u32 iomux_val[MX7ULP_MAX_IOMUX_NUM]; /* To save value */ + u32 select_input_num; /* Number of select input which need saved/restored. */ + u32 select_input_val[MX7ULP_MAX_SELECT_INPUT_NUM]; /* To save value */ + u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */ + u32 mmdc_io_val[MX7ULP_MAX_MMDC_IO_NUM][2]; /* To save offset and value */ + u32 mmdc_num; /* Number of MMDC registers which need saved/restored. */ + u32 mmdc_val[MX7ULP_MAX_MMDC_NUM][2]; +} __aligned(8); + +static struct imx7ulp_cpu_pm_info *pm_info; +static void __iomem *aips1_base; +static void __iomem *aips2_base; +static void __iomem *aips3_base; +static void __iomem *aips4_base; +static void __iomem *aips5_base; + +static const char * const low_power_ocram_match[] __initconst = { + "fsl,lpm-sram", + NULL +}; + +static void imx7ulp_gpio_save(void) +{ + int i; + + for (i = 0; i < 4; i++) { + pm_info->gpio[i][0] = readl_relaxed(gpio_base[i] + GPIO_PDOR); + pm_info->gpio[i][1] = readl_relaxed(gpio_base[i] + GPIO_PDDR); + } +} + +static void imx7ulp_scg1_save(void) +{ + int i; + + for (i = 0; i < 17; i++) + pm_info->scg1[i] = readl_relaxed(scg1_base + scg1_offset[i]); +} + +static void imx7ulp_pcc3_save(void) +{ + int i; + + for (i = 0; i < 16; i++) + pcc3_regs[i][1] = readl_relaxed(pcc3_base + pcc3_regs[i][0]); +} + +static void imx7ulp_pcc3_restore(void) +{ + int i; + + for (i = 0; i < 16; i++) + writel_relaxed(pcc3_regs[i][1], pcc3_base + pcc3_regs[i][0]); +} + +static void imx7ulp_pcc2_save(void) +{ + int i; + + for (i = 0; i < 24; i++) + pcc2_regs[i][1] = readl_relaxed(pcc2_base + pcc2_regs[i][0]); +} + +static void imx7ulp_pcc2_restore(void) +{ + int i; + + for (i = 0; i < 24; i++) + writel_relaxed(pcc2_regs[i][1], pcc2_base + pcc2_regs[i][0]); +} + +static inline void imx7ulp_iomuxc_save(void) +{ + int i; + + pm_info->iomux_num = MX7ULP_MAX_IOMUX_NUM; + pm_info->select_input_num = MX7ULP_MAX_SELECT_INPUT_NUM; + + for (i = 0; i < pm_info->iomux_num; i++) + pm_info->iomux_val[i] = + readl_relaxed(iomuxc1_base + + IOMUX_START + i * 0x4); + for (i = 0; i < pm_info->select_input_num; i++) + pm_info->select_input_val[i] = + readl_relaxed(iomuxc1_base + + SELECT_INPUT_START + i * 0x4); +} + +static void imx7ulp_lpuart_save(void) +{ + lpuart4_regs[0] = readl_relaxed(lpuart4_base + LPUART_BAUD); + lpuart4_regs[1] = readl_relaxed(lpuart4_base + LPUART_FIFO); + lpuart4_regs[2] = readl_relaxed(lpuart4_base + LPUART_WATER); + lpuart4_regs[3] = readl_relaxed(lpuart4_base + LPUART_CTRL); +} + +static void imx7ulp_lpuart_restore(void) +{ + writel_relaxed(LPUART4_MUX_VALUE, + iomuxc1_base + PTC2_LPUART4_TX_OFFSET); + writel_relaxed(LPUART4_MUX_VALUE, + iomuxc1_base + PTC3_LPUART4_RX_OFFSET); + writel_relaxed(LPUART4_INPUT_VALUE, + iomuxc1_base + PTC2_LPUART4_TX_INPUT_OFFSET); + writel_relaxed(LPUART4_INPUT_VALUE, + iomuxc1_base + PTC3_LPUART4_RX_INPUT_OFFSET); + + writel_relaxed(lpuart4_regs[0], lpuart4_base + LPUART_BAUD); + writel_relaxed(lpuart4_regs[1], lpuart4_base + LPUART_FIFO); + writel_relaxed(lpuart4_regs[2], lpuart4_base + LPUART_WATER); + writel_relaxed(lpuart4_regs[3], lpuart4_base + LPUART_CTRL); +} + +static void imx7ulp_tpm_save(void) +{ + tpm5_regs[0] = readl_relaxed(tpm5_base + TPM_SC); + tpm5_regs[1] = readl_relaxed(tpm5_base + TPM_MOD); + tpm5_regs[2] = readl_relaxed(tpm5_base + TPM_C0SC); + tpm5_regs[3] = readl_relaxed(tpm5_base + TPM_C0V); +} + +static void imx7ulp_tpm_restore(void) +{ + writel_relaxed(tpm5_regs[0], tpm5_base + TPM_SC); + writel_relaxed(tpm5_regs[1], tpm5_base + TPM_MOD); + writel_relaxed(tpm5_regs[2], tpm5_base + TPM_C0SC); + writel_relaxed(tpm5_regs[3], tpm5_base + TPM_C0V); +} + +static void imx7ulp_set_dgo(u32 val) +{ + writel_relaxed(val, pm_info->sim_base + DGO_GPR3); + writel_relaxed(val, pm_info->sim_base + DGO_GPR4); +} int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode) { - u32 val = readl_relaxed(smc1_base + SMC_PMCTRL); + u32 val1 = BM_PMPROT_AHSRUN | BM_PMPROT_AVLP | BM_PMPROT_AVLLS; + u32 val2 = readl_relaxed(smc1_base + PMCTRL); + u32 val3 = readl_relaxed(pmc0_base + PMC0_CTRL); - /* clear all */ - val &= ~(BM_PMCTRL_RUNM | BM_PMCTRL_STOPM | BM_PMCTRL_PSTOPO); + val2 &= ~(BM_PMCTRL_RUNM | + BM_PMCTRL_STOPM | BM_PMCTRL_PSTOPO); + val3 |= BM_CTRL_LDOOKDIS; switch (mode) { case ULP_PM_RUN: /* system/bus clock enabled */ - val |= PSTOPO_PSTOP3 << BP_PMCTRL_PSTOPO; + val2 |= 0x3 << BP_PMCTRL_PSTOPO; break; case ULP_PM_WAIT: /* system clock disabled, bus clock enabled */ - val |= PSTOPO_PSTOP2 << BP_PMCTRL_PSTOPO; + val2 |= 0x2 << BP_PMCTRL_PSTOPO; break; case ULP_PM_STOP: /* system/bus clock disabled */ - val |= PSTOPO_PSTOP1 << BP_PMCTRL_PSTOPO; + val2 |= 0x1 << BP_PMCTRL_PSTOPO; + break; + case ULP_PM_VLPS: + val2 |= 0x2 << BP_PMCTRL_STOPM; + break; + case ULP_PM_VLLS: + val2 |= 0x4 << BP_PMCTRL_STOPM; break; default: return -EINVAL; } - writel_relaxed(val, smc1_base + SMC_PMCTRL); + writel_relaxed(val1, smc1_base + PMPROT); + writel_relaxed(val2, smc1_base + PMCTRL); + writel_relaxed(val3, pmc0_base + PMC0_CTRL); return 0; } -void __init imx7ulp_pm_init(void) +#define MX7ULP_SUSPEND_POWERDWN_PARAM \ + ((0 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \ + (1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \ + (PSCI_POWER_STATE_TYPE_POWER_DOWN << PSCI_0_2_POWER_STATE_TYPE_SHIFT)) + +#define MX7ULP_SUSPEND_STANDBY_PARAM \ + ((0 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \ + (1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \ + (PSCI_POWER_STATE_TYPE_STANDBY << PSCI_0_2_POWER_STATE_TYPE_SHIFT)) + +static int imx7ulp_suspend_finish(unsigned long val) +{ + u32 state; + + if (val == 0) + state = MX7ULP_SUSPEND_POWERDWN_PARAM; + else + state = MX7ULP_SUSPEND_STANDBY_PARAM; + + if (psci_ops.cpu_suspend) + return psci_ops.cpu_suspend(state, __pa(cpu_resume)); + + imx7ulp_suspend_in_ocram_fn(suspend_ocram_base); + + return 0; +} + +static int imx7ulp_pm_enter(suspend_state_t state) +{ + switch (state) { + case PM_SUSPEND_STANDBY: + if (psci_ops.cpu_suspend) + /* Zzz ... */ + cpu_suspend(1, imx7ulp_suspend_finish); + else { + imx7ulp_set_lpm(ULP_PM_VLPS); + writel_relaxed( + readl_relaxed(pmc1_base + PMC1_VLPS) | BM_VLPS_RBBEN, + pmc1_base + PMC1_VLPS); + + /* Zzz ... */ + cpu_suspend(0, imx7ulp_suspend_finish); + + writel_relaxed( + readl_relaxed(pmc1_base + PMC1_VLPS) & ~BM_VLPS_RBBEN, + pmc1_base + PMC1_VLPS); + imx7ulp_set_lpm(ULP_PM_RUN); + } + break; + case PM_SUSPEND_MEM: + if (psci_ops.cpu_suspend) { + /* Zzz ... */ + cpu_suspend(0, imx7ulp_suspend_finish); + } else { + imx7ulp_gpio_save(); + imx7ulp_scg1_save(); + imx7ulp_pcc2_save(); + imx7ulp_pcc3_save(); + imx7ulp_tpm_save(); + if (!console_suspend_enabled) + imx7ulp_lpuart_save(); + imx7ulp_iomuxc_save(); + imx7ulp_set_lpm(ULP_PM_VLLS); + + /* Zzz ... */ + cpu_suspend(0, imx7ulp_suspend_finish); + + imx7ulp_pcc2_restore(); + imx7ulp_pcc3_restore(); + if (!console_suspend_enabled) + imx7ulp_lpuart_restore(); + imx7ulp_set_dgo(0); + imx7ulp_tpm_restore(); + imx7ulp_set_lpm(ULP_PM_RUN); + } + break; + default: + return -EINVAL; + } + + return 0; +} + +/* Put CA7 into VLLS mode before M4 power off CA7 */ +void imx7ulp_poweroff(void) +{ + imx7ulp_set_lpm(ULP_PM_VLLS); + cpu_suspend(0, imx7ulp_suspend_finish); +} + +static int imx7ulp_pm_valid(suspend_state_t state) +{ + return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM); +} + +static const struct platform_suspend_ops imx7ulp_pm_ops = { + .enter = imx7ulp_pm_enter, + .valid = imx7ulp_pm_valid, +}; + +static int __init imx7ulp_suspend_init(void) +{ + int ret = 0; + + suspend_set_ops(&imx7ulp_pm_ops); + + return ret; +} + +static struct map_desc iram_tlb_io_desc __initdata = { + /* .virtual and .pfn are run-time assigned */ + .length = SZ_1M, + .type = MT_MEMORY_RWX_NONCACHED, +}; + +static int __init imx7ulp_dt_find_lpsram(unsigned long node, const char *uname, + int depth, void *data) +{ + unsigned long lpram_addr; + const __be32 *prop = of_get_flat_dt_prop(node, "reg", NULL); + + if (of_flat_dt_match(node, low_power_ocram_match)) { + if (!prop) + return -EINVAL; + + lpram_addr = be32_to_cpup(prop); + + /* We need to create a 1M page table entry. */ + iram_tlb_io_desc.virtual = + IMX_IO_P2V(lpram_addr & ADDR_1M_MASK); + iram_tlb_io_desc.pfn = __phys_to_pfn(lpram_addr & ADDR_1M_MASK); + iram_tlb_phys_addr = lpram_addr; + iram_tlb_base_addr = IMX_IO_P2V(lpram_addr); + iotable_init(&iram_tlb_io_desc, 1); + } + + return 0; +} + +void __init imx7ulp_pm_map_io(void) +{ + /* + * Get the address of IRAM or OCRAM to be used by the low + * power code from the device tree. + */ + WARN_ON(of_scan_flat_dt(imx7ulp_dt_find_lpsram, NULL)); + + /* Return if no IRAM space is allocated for suspend/resume code. */ + if (!iram_tlb_base_addr) { + pr_warn("No valid ocram available for suspend/resume!\n"); + return; + } +} + +void __init imx7ulp_pm_common_init(const struct imx7ulp_pm_socdata + *socdata) { struct device_node *np; + unsigned long sram_paddr = 0; + const u32 *mmdc_offset_array; + const u32 *mmdc_io_offset_array; + unsigned long i, j; + int ret; + + if (psci_ops.cpu_suspend) { + aips1_base = ioremap(MX7ULP_AIPS1_BASE_ADDR, SZ_1M); + aips2_base = ioremap(MX7ULP_AIPS2_BASE_ADDR, SZ_1M); + aips3_base = ioremap(MX7ULP_AIPS3_BASE_ADDR, SZ_1M); + aips4_base = ioremap(MX7ULP_AIPS4_BASE_ADDR, SZ_1M); + aips5_base = ioremap(MX7ULP_AIPS5_BASE_ADDR, SZ_1M); + } else { + /* Set all entries to 0 except first 3 words reserved for M4. */ + memset((void *)iram_tlb_base_addr, 0, MX7ULP_IRAM_TLB_SIZE); + + /* + * Make sure the IRAM virtual address has a mapping in the IRAM + * page table. + * + * Only use the top 12 bits [31-20] when storing the physical + * address in the page table as only these bits are required + * for 1M mapping. + */ + j = ((iram_tlb_base_addr >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + (iram_tlb_phys_addr & ADDR_1M_MASK) | + TT_ATTRIB_NON_CACHEABLE_1M; + /* + * Make sure the AIPS1 virtual address has a mapping in the + * IRAM page table. + */ + aips1_base = ioremap(MX7ULP_AIPS1_BASE_ADDR, SZ_1M); + j = (((u32)aips1_base >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + ((MX7ULP_AIPS1_BASE_ADDR) & ADDR_1M_MASK) | + TT_ATTRIB_NON_CACHEABLE_1M; + /* + * Make sure the AIPS2 virtual address has a mapping in the + * IRAM page table. + */ + aips2_base = ioremap(MX7ULP_AIPS2_BASE_ADDR, SZ_1M); + j = (((u32)aips2_base >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + ((MX7ULP_AIPS2_BASE_ADDR) & ADDR_1M_MASK) | + TT_ATTRIB_NON_CACHEABLE_1M; + /* + * Make sure the AIPS3 virtual address has a mapping in the + * IRAM page table. + */ + aips3_base = ioremap(MX7ULP_AIPS3_BASE_ADDR, SZ_1M); + j = (((u32)aips3_base >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + ((MX7ULP_AIPS3_BASE_ADDR) & ADDR_1M_MASK) | + TT_ATTRIB_NON_CACHEABLE_1M; + /* + * Make sure the AIPS4 virtual address has a mapping in the + * IRAM page table. + */ + aips4_base = ioremap(MX7ULP_AIPS4_BASE_ADDR, SZ_1M); + j = (((u32)aips4_base >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + ((MX7ULP_AIPS4_BASE_ADDR) & ADDR_1M_MASK) | + TT_ATTRIB_NON_CACHEABLE_1M; + /* + * Make sure the AIPS5 virtual address has a mapping in the + * IRAM page table. + */ + aips5_base = ioremap(MX7ULP_AIPS5_BASE_ADDR, SZ_1M); + j = (((u32)aips5_base >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + ((MX7ULP_AIPS5_BASE_ADDR) & ADDR_1M_MASK) | + TT_ATTRIB_NON_CACHEABLE_1M; + } np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1"); smc1_base = of_iomap(np, 0); WARN_ON(!smc1_base); + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pmc0"); + pmc0_base = of_iomap(np, 0); + WARN_ON(!pmc0_base); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pmc1"); + pmc1_base = of_iomap(np, 0); + WARN_ON(!pmc1_base); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-tpm"); + tpm5_base = of_iomap(np, 0); + WARN_ON(!tpm5_base); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-lpuart"); + lpuart4_base = of_iomap(np, 0); + WARN_ON(!lpuart4_base); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pcc2"); + pcc2_base = of_iomap(np, 0); + WARN_ON(!pcc2_base); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pcc3"); + pcc3_base = of_iomap(np, 0); + WARN_ON(!pcc3_base); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-iomuxc1"); + iomuxc1_base = of_iomap(np, 0); + WARN_ON(!iomuxc1_base); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-scg1"); + scg1_base = of_iomap(np, 0); + WARN_ON(!scg1_base); + + np = NULL; + for (i = 0; i < 4; i++) { + np = of_find_compatible_node(np, NULL, "fsl,vf610-gpio"); + gpio_base[i] = of_iomap(np, 1); + WARN_ON(!gpio_base[i]); + } + + if (psci_ops.cpu_suspend) { + pm_info = kzalloc(SZ_16K, GFP_KERNEL); + if (!pm_info) + panic("pm info allocation failed\n"); + } else { + /* + * 16KB is allocated for IRAM TLB, but only up 8k is for kernel TLB, + * The lower 8K is not used, so use the lower 8K for IRAM code and + * pm_info. + * + */ + sram_paddr = iram_tlb_phys_addr; + + /* Make sure sram_paddr is 8 byte aligned. */ + if ((uintptr_t)(sram_paddr) & (FNCPY_ALIGN - 1)) + sram_paddr += FNCPY_ALIGN - sram_paddr % (FNCPY_ALIGN); + + /* Get the virtual address of the suspend code. */ + suspend_ocram_base = (void *)IMX_IO_P2V(sram_paddr); + + pm_info = suspend_ocram_base; + } + pm_info->pbase = sram_paddr; + pm_info->resume_addr = virt_to_phys(imx7ulp_cpu_resume); + pm_info->pm_info_size = sizeof(*pm_info); + + pm_info->scg1_base = aips2_base + + (MX7ULP_SCG1_BASE_ADDR & ~ADDR_1M_MASK); + pm_info->smc1_base = aips3_base + + (MX7ULP_SMC1_BASE_ADDR & ~ADDR_1M_MASK); + pm_info->mmdc_base = aips4_base + + (MX7ULP_MMDC_BASE_ADDR & ~ADDR_1M_MASK); + pm_info->mmdc_io_base = aips4_base + + (MX7ULP_MMDC_IO_BASE_ADDR & ~ADDR_1M_MASK); + pm_info->sim_base = aips5_base + + (MX7ULP_SIM_BASE_ADDR & ~ADDR_1M_MASK); + + pm_info->mmdc_io_num = socdata->mmdc_io_num; + mmdc_io_offset_array = socdata->mmdc_io_offset; + pm_info->mmdc_num = socdata->mmdc_num; + mmdc_offset_array = socdata->mmdc_offset; + + for (i = 0; i < pm_info->mmdc_io_num; i++) { + pm_info->mmdc_io_val[i][0] = + mmdc_io_offset_array[i]; + pm_info->mmdc_io_val[i][1] = + readl_relaxed(pm_info->mmdc_io_base + + mmdc_io_offset_array[i]); + } + + /* initialize MMDC settings */ + for (i = 0; i < pm_info->mmdc_num; i++) + pm_info->mmdc_val[i][0] = + mmdc_offset_array[i]; + + for (i = 0; i < pm_info->mmdc_num; i++) + pm_info->mmdc_val[i][1] = imx7ulp_lpddr3_script[i]; + + if (!psci_ops.cpu_suspend) { + imx7ulp_suspend_in_ocram_fn = fncpy( + suspend_ocram_base + sizeof(*pm_info), + &imx7ulp_suspend, + MX7ULP_SUSPEND_OCRAM_SIZE - sizeof(*pm_info)); + } + + if (IS_ENABLED(CONFIG_SUSPEND)) { + ret = imx7ulp_suspend_init(); + if (ret) + pr_warn("%s: No DDR LPM support with suspend %d!\n", + __func__, ret); + } +} + +void __init imx7ulp_pm_init(void) +{ + imx7ulp_pm_common_init(&imx7ulp_lpddr3_pm_data); imx7ulp_set_lpm(ULP_PM_RUN); } + +static irqreturn_t imx7ulp_nmi_isr(int irq, void *param) +{ + writel_relaxed(readl_relaxed(mu_base + MU_SR) | MU_B_SR_NMIC, + mu_base + MU_SR); + pm_system_wakeup(); + + return IRQ_HANDLED; +} + +void imx7ulp_enable_nmi(void) +{ + struct device_node *np; + int irq, ret; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-nmi"); + mu_base = of_iomap(np, 0); + WARN_ON(!mu_base); + irq = of_irq_get(np, 0); + ret = request_irq(irq, imx7ulp_nmi_isr, + IRQF_NO_SUSPEND, "imx7ulp-nmi", NULL); + if (ret) { + pr_err("%s: register interrupt %d failed, rc %d\n", + __func__, irq, ret); + return; + } +} diff --git a/arch/arm/mach-imx/pm-rpmsg.c b/arch/arm/mach-imx/pm-rpmsg.c new file mode 100644 index 00000000000000..4dfe489f5d38ed --- /dev/null +++ b/arch/arm/mach-imx/pm-rpmsg.c @@ -0,0 +1,353 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +#define RPMSG_TIMEOUT 1000 + +#define PM_RPMSG_TYPE 0 +#define HEATBEAT_RPMSG_TYPE 2 + +enum pm_rpmsg_cmd { + PM_RPMSG_MODE, + PM_RPMSG_HEART_BEAT, + PM_RPMSG_HEART_BEAT_OFF, +}; + +enum pm_rpmsg_power_mode { + PM_RPMSG_HSRUN, + PM_RPMSG_RUN, + PM_RPMSG_VLPR, + PM_RPMSG_WAIT, + PM_RPMSG_VLPS, + PM_RPMSG_VLLS, + PM_RPMSG_REBOOT, + PM_RPMSG_SHUTDOWN, +}; + +struct pm_rpmsg_info { + struct rpmsg_device *rpdev; + struct device *dev; + struct pm_rpmsg_data *msg; + struct pm_qos_request pm_qos_req; + struct notifier_block restart_handler; + struct completion cmd_complete; + bool first_flag; + struct mutex lock; +}; + +static struct pm_rpmsg_info pm_rpmsg; + +static struct delayed_work heart_beat_work; + +static bool heartbeat_off; + +struct pm_rpmsg_data { + struct imx_rpmsg_head header; + u8 data; +} __attribute__ ((packed)); + +static int pm_send_message(struct pm_rpmsg_data *msg, + struct pm_rpmsg_info *info, bool ack) +{ + int err; + + if (!info->rpdev) { + dev_dbg(info->dev, + "rpmsg channel not ready, m4 image ready?\n"); + return -EINVAL; + } + + mutex_lock(&info->lock); + pm_qos_add_request(&info->pm_qos_req, + PM_QOS_CPU_DMA_LATENCY, 0); + + reinit_completion(&info->cmd_complete); + + err = rpmsg_send(info->rpdev->ept, (void *)msg, + sizeof(struct pm_rpmsg_data)); + + if (err) { + dev_err(&info->rpdev->dev, "rpmsg_send failed: %d\n", err); + goto err_out; + } + + if (ack) { + err = wait_for_completion_timeout(&info->cmd_complete, + msecs_to_jiffies(RPMSG_TIMEOUT)); + if (!err) { + dev_err(&info->rpdev->dev, "rpmsg_send timeout!\n"); + err = -ETIMEDOUT; + goto err_out; + } + + if (info->msg->data != 0) { + dev_err(&info->rpdev->dev, "rpmsg not ack %d!\n", + info->msg->data); + err = -EINVAL; + goto err_out; + } + + err = 0; + } + +err_out: + pm_qos_remove_request(&info->pm_qos_req); + mutex_unlock(&info->lock); + + return err; +} + +static int pm_vlls_notify_m4(bool enter) +{ + struct pm_rpmsg_data msg; + + msg.header.cate = IMX_RMPSG_LIFECYCLE; + msg.header.major = IMX_RMPSG_MAJOR; + msg.header.minor = IMX_RMPSG_MINOR; + msg.header.type = PM_RPMSG_TYPE; + msg.header.cmd = PM_RPMSG_MODE; + msg.data = enter ? PM_RPMSG_VLLS : PM_RPMSG_RUN; + + return pm_send_message(&msg, &pm_rpmsg, true); +} + +void pm_shutdown_notify_m4(void) +{ + struct pm_rpmsg_data msg; + + msg.header.cate = IMX_RMPSG_LIFECYCLE; + msg.header.major = IMX_RMPSG_MAJOR; + msg.header.minor = IMX_RMPSG_MINOR; + msg.header.type = PM_RPMSG_TYPE; + msg.header.cmd = PM_RPMSG_MODE; + msg.data = PM_RPMSG_SHUTDOWN; + /* No ACK from M4 */ + pm_send_message(&msg, &pm_rpmsg, false); + imx7ulp_poweroff(); +} + +void pm_reboot_notify_m4(void) +{ + struct pm_rpmsg_data msg; + + msg.header.cate = IMX_RMPSG_LIFECYCLE; + msg.header.major = IMX_RMPSG_MAJOR; + msg.header.minor = IMX_RMPSG_MINOR; + msg.header.type = PM_RPMSG_TYPE; + msg.header.cmd = PM_RPMSG_MODE; + msg.data = PM_RPMSG_REBOOT; + + pm_send_message(&msg, &pm_rpmsg, true); + +} + +void pm_heartbeat_off_notify_m4(bool enter) +{ + struct pm_rpmsg_data msg; + + msg.header.cate = IMX_RMPSG_LIFECYCLE; + msg.header.major = IMX_RMPSG_MAJOR; + msg.header.minor = IMX_RMPSG_MINOR; + msg.header.type = PM_RPMSG_TYPE; + msg.header.cmd = PM_RPMSG_HEART_BEAT_OFF; + msg.data = enter ? 0 : 1; + + pm_send_message(&msg, &pm_rpmsg, true); +} + +static void pm_heart_beat_work_handler(struct work_struct *work) +{ + struct pm_rpmsg_data msg; + + /* Notify M4 side A7 in RUN mode at boot time */ + if (pm_rpmsg.first_flag) { + pm_vlls_notify_m4(false); + + pm_heartbeat_off_notify_m4(heartbeat_off); + + pm_rpmsg.first_flag = false; + } + + if (!heartbeat_off) { + msg.header.cate = IMX_RMPSG_LIFECYCLE; + msg.header.major = IMX_RMPSG_MAJOR; + msg.header.minor = IMX_RMPSG_MINOR; + msg.header.type = HEATBEAT_RPMSG_TYPE; + msg.header.cmd = PM_RPMSG_HEART_BEAT; + msg.data = 0; + pm_send_message(&msg, &pm_rpmsg, false); + + schedule_delayed_work(&heart_beat_work, + msecs_to_jiffies(30000)); + } +} + +static void pm_poweroff_rpmsg(void) +{ + pm_shutdown_notify_m4(); + pr_emerg("Unable to poweroff system\n"); +} + +static int pm_restart_handler(struct notifier_block *this, unsigned long mode, + void *cmd) +{ + pm_reboot_notify_m4(); + + return NOTIFY_DONE; +} + +static int pm_rpmsg_probe(struct rpmsg_device *rpdev) +{ + int ret; + + pm_rpmsg.rpdev = rpdev; + + dev_info(&rpdev->dev, "new channel: 0x%x -> 0x%x!\n", + rpdev->src, rpdev->dst); + + init_completion(&pm_rpmsg.cmd_complete); + mutex_init(&pm_rpmsg.lock); + + INIT_DELAYED_WORK(&heart_beat_work, + pm_heart_beat_work_handler); + + pm_rpmsg.first_flag = true; + schedule_delayed_work(&heart_beat_work, 0); + + pm_rpmsg.restart_handler.notifier_call = pm_restart_handler; + pm_rpmsg.restart_handler.priority = 128; + ret = register_restart_handler(&pm_rpmsg.restart_handler); + if (ret) + dev_err(&rpdev->dev, "cannot register restart handler\n"); + + pm_power_off = pm_poweroff_rpmsg; + + return 0; +} + +static int pm_rpmsg_cb(struct rpmsg_device *rpdev, void *data, int len, + void *priv, u32 src) +{ + struct pm_rpmsg_data *msg = (struct pm_rpmsg_data *)data; + + pm_rpmsg.msg = msg; + + complete(&pm_rpmsg.cmd_complete); + + return 0; +} + +static void pm_rpmsg_remove(struct rpmsg_device *rpdev) +{ + dev_info(&rpdev->dev, "pm rpmsg driver is removed\n"); +} + +static struct rpmsg_device_id pm_rpmsg_id_table[] = { + { .name = "rpmsg-life-cycle-channel" }, + { }, +}; + +static struct rpmsg_driver pm_rpmsg_driver = { + .drv.name = "pm_rpmsg", + .drv.owner = THIS_MODULE, + .id_table = pm_rpmsg_id_table, + .probe = pm_rpmsg_probe, + .callback = pm_rpmsg_cb, + .remove = pm_rpmsg_remove, +}; + +#ifdef CONFIG_PM_SLEEP +static int pm_heartbeat_suspend(struct device *dev) +{ + int err; + + err = pm_vlls_notify_m4(true); + if (err) + return err; + + cancel_delayed_work_sync(&heart_beat_work); + + return 0; +} + +static int pm_heartbeat_resume(struct device *dev) +{ + int err; + + err = pm_vlls_notify_m4(false); + if (err) + return err; + + schedule_delayed_work(&heart_beat_work, + msecs_to_jiffies(10000)); + + return 0; +} +#endif + +static int pm_heartbeat_probe(struct platform_device *pdev) +{ + platform_set_drvdata(pdev, &pm_rpmsg); + + return register_rpmsg_driver(&pm_rpmsg_driver); +} + +static const struct of_device_id pm_heartbeat_id[] = { + {"fsl,heartbeat-rpmsg",}, + {}, +}; +MODULE_DEVICE_TABLE(of, pm_heartbeat_id); + +static const struct dev_pm_ops pm_heartbeat_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_heartbeat_suspend, + pm_heartbeat_resume) +}; + +static struct platform_driver pm_heartbeat_driver = { + .driver = { + .name = "heartbeat-rpmsg", + .owner = THIS_MODULE, + .of_match_table = pm_heartbeat_id, + .pm = &pm_heartbeat_ops, + }, + .probe = pm_heartbeat_probe, +}; + +static int __init setup_heartbeat(char *str) +{ + heartbeat_off = true; + + return 1; +}; +__setup("heartbeat_off", setup_heartbeat); + +module_platform_driver(pm_heartbeat_driver); + +MODULE_DESCRIPTION("Freescale PM rpmsg driver"); +MODULE_AUTHOR("Anson Huang "); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-imx/smp_wfe.S b/arch/arm/mach-imx/smp_wfe.S new file mode 100644 index 00000000000000..08894bb39c4df9 --- /dev/null +++ b/arch/arm/mach-imx/smp_wfe.S @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "hardware.h" + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + .endm + +#ifdef CONFIG_SMP + .align 3 + +ENTRY(imx7_smp_wfe) + push {r4 - r11, lr} + + dsb + isb + + disable_l1_dcache + + isb + + /* Turn off SMP bit. */ + mrc p15, 0, r8, c1, c0, 1 + bic r8, r8, #0x40 + mcr p15, 0, r8, c1, c0, 1 + + isb + /* Set flag of entering WFE. */ + mov r7, #0xff + lsl r7, r7, r0 + mov r6, #SCU_PM_DORMANT + lsl r6, r6, r0 + ldr r8, [r1, #0x4] + bic r8, r8, r7 + orr r6, r6, r8 + str r6, [r1, #0x4] + +go_back_wfe: + wfe + + /* Offset 0x0 stores busfeq done flag */ + ldr r6, [r1] + cmp r6, #1 + beq go_back_wfe + + /* Turn ON SMP bit. */ + mrc p15, 0, r8, c1, c0, 1 + orr r8, r8, #0x40 + mcr p15, 0, r8, c1, c0, 1 + + isb + /* Enable L1 data cache. */ + mrc p15, 0, r8, c1, c0, 0 + orr r8, r8, #0x4 + mcr p15, 0, r8, c1, c0, 0 + isb + + /* Set flag of exiting WFE. */ + mov r7, #0xff + lsl r7, r7, r0 + mov r6, #SCU_PM_NORMAL + lsl r6, r6, r0 + ldr r8, [r1, #0x4] + bic r8, r8, r7 + orr r6, r6, r8 + str r6, [r1, #0x4] + + /* Pop all saved registers. */ + pop {r4 - r11, lr} + mov pc, lr + .ltorg +ENDPROC(imx7_smp_wfe) +#endif diff --git a/arch/arm/mach-imx/smp_wfe_imx6.S b/arch/arm/mach-imx/smp_wfe_imx6.S new file mode 100644 index 00000000000000..791e93ce98da37 --- /dev/null +++ b/arch/arm/mach-imx/smp_wfe_imx6.S @@ -0,0 +1,186 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include "hardware.h" + +#ifdef CONFIG_SMP +.extern scu_base +#endif + +.globl wfe_smp_freq_change_start +.globl wfe_smp_freq_change_end + +#ifdef CONFIG_SMP + + .align 3 + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r11, lr} + + ldr r7, =v7_flush_kern_cache_all + mov lr, pc + mov pc, r7 + pop {r0 - r11, lr} + + /* disable d-cache */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + dsb + isb + + push {r0 - r11, lr} + + ldr r7, =v7_flush_kern_cache_all + mov lr, pc + mov pc, r7 + pop {r0 - r11, lr} + + .endm + +ENTRY(wfe_smp_freq_change) +wfe_smp_freq_change_start: + push {r4 - r11, lr} + + mov r6, r0 + mov r7, r1 + + dsb + isb + + disable_l1_dcache + + isb + + /* Turn off SMP bit. */ + mrc p15, 0, r8, c1, c0, 1 + bic r8, r8, #0x40 + mcr p15, 0, r8, c1, c0, 1 + + isb + + /* Inform the SCU we are going to enter WFE. */ + push {r0 - r11, lr} + + ldr r0,=scu_base + ldr r0, [r0] + mov r1, #SCU_PM_DORMANT + ldr r3, =scu_power_mode + mov lr, pc + mov pc, r3 + + pop {r0 - r11, lr} + +go_back_wfe: + wfe + + ldr r3, [r7] + cmp r3, #1 + beq go_back_wfe + + /* Turn ON SMP bit. */ + mrc p15, 0, r8, c1, c0, 1 + orr r8, r8, #0x40 + mcr p15, 0, r8, c1, c0, 1 + + isb + /* Enable L1 data cache. */ + mrc p15, 0, r8, c1, c0, 0 + orr r8, r8, #0x4 + mcr p15, 0, r8, c1, c0, 0 + isb + + /* Inform the SCU we have exited WFE. */ + push {r0 - r11, lr} + + ldr r0,=scu_base + ldr r0, [r0] + mov r1, #SCU_PM_NORMAL + ldr r3, =scu_power_mode + mov lr, pc + mov pc, r3 + + pop {r0 - r11, lr} + + /* Pop all saved registers. */ + pop {r4 - r11, lr} + mov pc, lr + .ltorg +wfe_smp_freq_change_end: +ENDPROC(wfe_smp_freq_change) + +#ifdef CONFIG_OPTEE +/** + * @brief Switch CPU in WFE mode while bus frequency change + * on-going + * + * @param[in] r0 CPU in WFE Status + * @param[in] r1 Bus frequency change status + */ + +.globl imx_smp_wfe_optee_end + +ENTRY(imx_smp_wfe_optee) + push {r4-r11, lr} + + dsb + isb + + disable_l1_dcache + isb + + /* Set flag CPU entering WFE. */ + mov r4, #1 + str r4, [r0] + + dsb + isb + +1: + wfe + + /* Check if busfreq is done, else loop */ + ldr r4, [r1] + cmp r4, #1 + beq 1b + + /* Enable L1 data cache. */ + mrc p15, 0, r4, c1, c0, 0 + orr r4, r4, #0x4 + mcr p15, 0, r4, c1, c0, 0 + isb + + /* Set flag CPU exiting WFE. */ + mov r4, #0 + str r4, [r0] + + /* Pop all saved registers. */ + pop {r4-r11, lr} + mov pc, lr + .ltorg +imx_smp_wfe_optee_end: +ENDPROC(imx_smp_wfe_optee) +#endif +#endif diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c index 0beea6d0217f2a..399771e2912e8e 100644 --- a/arch/arm/mach-imx/src.c +++ b/arch/arm/mach-imx/src.c @@ -12,6 +12,7 @@ #include #include #include "common.h" +#include "hardware.h" #define SRC_SCR 0x000 #define SRC_GPR1 0x020 @@ -23,9 +24,18 @@ #define BP_SRC_SCR_SW_IPU2_RST 12 #define BP_SRC_SCR_CORE1_RST 14 #define BP_SRC_SCR_CORE1_ENABLE 22 +/* below is for i.MX7D */ +#define SRC_GPR1_V2 0x074 +#define SRC_A7RCR0 0x004 +#define SRC_A7RCR1 0x008 +#define SRC_M4RCR 0x00C + +#define BP_SRC_A7RCR0_A7_CORE_RESET0 0 +#define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1 static void __iomem *src_base; -static DEFINE_SPINLOCK(scr_lock); +static DEFINE_SPINLOCK(src_lock); +static bool m4_is_enabled; static const int sw_reset_bits[5] = { BP_SRC_SCR_SW_GPU_RST, @@ -35,6 +45,11 @@ static const int sw_reset_bits[5] = { BP_SRC_SCR_SW_IPU2_RST }; +bool imx_src_is_m4_enabled(void) +{ + return m4_is_enabled; +} + static int imx_src_reset_module(struct reset_controller_dev *rcdev, unsigned long sw_reset_idx) { @@ -51,11 +66,11 @@ static int imx_src_reset_module(struct reset_controller_dev *rcdev, bit = 1 << sw_reset_bits[sw_reset_idx]; - spin_lock_irqsave(&scr_lock, flags); + spin_lock_irqsave(&src_lock, flags); val = readl_relaxed(src_base + SRC_SCR); val |= bit; writel_relaxed(val, src_base + SRC_SCR); - spin_unlock_irqrestore(&scr_lock, flags); + spin_unlock_irqrestore(&src_lock, flags); timeout = jiffies + msecs_to_jiffies(1000); while (readl(src_base + SRC_SCR) & bit) { @@ -81,32 +96,59 @@ void imx_enable_cpu(int cpu, bool enable) u32 mask, val; cpu = cpu_logical_map(cpu); - mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1); - spin_lock(&scr_lock); - val = readl_relaxed(src_base + SRC_SCR); - val = enable ? val | mask : val & ~mask; - val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1); - writel_relaxed(val, src_base + SRC_SCR); - spin_unlock(&scr_lock); + spin_lock(&src_lock); + if (cpu_is_imx7d()) { + /* enable core */ + if (enable) + imx_gpcv2_set_core1_pdn_pup_by_software(false); + + mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1); + val = readl_relaxed(src_base + SRC_A7RCR1); + val = enable ? val | mask : val & ~mask; + writel_relaxed(val, src_base + SRC_A7RCR1); + } else { + mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1); + val = readl_relaxed(src_base + SRC_SCR); + val = enable ? val | mask : val & ~mask; + val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1); + writel_relaxed(val, src_base + SRC_SCR); + } + spin_unlock(&src_lock); } void imx_set_cpu_jump(int cpu, void *jump_addr) { + spin_lock(&src_lock); cpu = cpu_logical_map(cpu); - writel_relaxed(__pa_symbol(jump_addr), - src_base + SRC_GPR1 + cpu * 8); + if (cpu_is_imx7d()) + writel_relaxed(__pa_symbol(jump_addr), + src_base + SRC_GPR1_V2 + cpu * 8); + else + writel_relaxed(__pa_symbol(jump_addr), + src_base + SRC_GPR1 + cpu * 8); + spin_unlock(&src_lock); } u32 imx_get_cpu_arg(int cpu) { cpu = cpu_logical_map(cpu); - return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4); + if (cpu_is_imx7d()) + return readl_relaxed(src_base + SRC_GPR1_V2 + + cpu * 8 + 4); + else + return readl_relaxed(src_base + SRC_GPR1 + + cpu * 8 + 4); } void imx_set_cpu_arg(int cpu, u32 arg) { cpu = cpu_logical_map(cpu); - writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4); + if (cpu_is_imx7d()) + writel_relaxed(arg, src_base + SRC_GPR1_V2 + + cpu * 8 + 4); + else + writel_relaxed(arg, src_base + SRC_GPR1 + + cpu * 8 + 4); } void __init imx_src_init(void) @@ -120,6 +162,15 @@ void __init imx_src_init(void) src_base = of_iomap(np, 0); WARN_ON(!src_base); + if (cpu_is_imx7d()) { + val = readl_relaxed(src_base + SRC_M4RCR); + if (((val & BIT(3)) == BIT(3)) && !(val & BIT(0))) + m4_is_enabled = true; + else + m4_is_enabled = false; + return; + } + imx_reset_controller.of_node = np; if (IS_ENABLED(CONFIG_RESET_CONTROLLER)) reset_controller_register(&imx_reset_controller); @@ -128,9 +179,17 @@ void __init imx_src_init(void) * force warm reset sources to generate cold reset * for a more reliable restart */ - spin_lock(&scr_lock); + spin_lock(&src_lock); val = readl_relaxed(src_base + SRC_SCR); + + /* bit 4 is m4c_non_sclr_rst on i.MX6SX */ + if (cpu_is_imx6sx() && ((val & + (1 << BP_SRC_SCR_SW_OPEN_VG_RST)) == 0)) + m4_is_enabled = true; + else + m4_is_enabled = false; + val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE); writel_relaxed(val, src_base + SRC_SCR); - spin_unlock(&scr_lock); + spin_unlock(&src_lock); } diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S index 1eabf2d2834be7..a7e349e583e740 100644 --- a/arch/arm/mach-imx/suspend-imx6.S +++ b/arch/arm/mach-imx/suspend-imx6.S @@ -41,23 +41,32 @@ #define PM_INFO_RESUME_ADDR_OFFSET 0x4 #define PM_INFO_DDR_TYPE_OFFSET 0x8 #define PM_INFO_PM_INFO_SIZE_OFFSET 0xC -#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10 -#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14 -#define PM_INFO_MX6Q_SRC_P_OFFSET 0x18 -#define PM_INFO_MX6Q_SRC_V_OFFSET 0x1C -#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x20 -#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x24 -#define PM_INFO_MX6Q_CCM_P_OFFSET 0x28 -#define PM_INFO_MX6Q_CCM_V_OFFSET 0x2C -#define PM_INFO_MX6Q_GPC_P_OFFSET 0x30 -#define PM_INFO_MX6Q_GPC_V_OFFSET 0x34 -#define PM_INFO_MX6Q_L2_P_OFFSET 0x38 -#define PM_INFO_MX6Q_L2_V_OFFSET 0x3C -#define PM_INFO_MMDC_IO_NUM_OFFSET 0x40 -#define PM_INFO_MMDC_IO_VAL_OFFSET 0x44 +#define PM_INFO_MX6Q_MMDC0_P_OFFSET 0x10 +#define PM_INFO_MX6Q_MMDC0_V_OFFSET 0x14 +#define PM_INFO_MX6Q_MMDC1_P_OFFSET 0x18 +#define PM_INFO_MX6Q_MMDC1_V_OFFSET 0x1C +#define PM_INFO_MX6Q_SRC_P_OFFSET 0x20 +#define PM_INFO_MX6Q_SRC_V_OFFSET 0x24 +#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x28 +#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x2C +#define PM_INFO_MX6Q_CCM_P_OFFSET 0x30 +#define PM_INFO_MX6Q_CCM_V_OFFSET 0x34 +#define PM_INFO_MX6Q_GPC_P_OFFSET 0x38 +#define PM_INFO_MX6Q_GPC_V_OFFSET 0x3C +#define PM_INFO_MX6Q_L2_P_OFFSET 0x40 +#define PM_INFO_MX6Q_L2_V_OFFSET 0x44 +#define PM_INFO_MX6Q_ANATOP_P_OFFSET 0x48 +#define PM_INFO_MX6Q_ANATOP_V_OFFSET 0x4C +#define PM_INFO_MX6Q_TTBR1_V_OFFSET 0x50 +#define PM_INFO_MMDC_IO_NUM_OFFSET 0x54 +#define PM_INFO_MMDC_IO_VAL_OFFSET 0x58 +/* below offsets depends on MX6_MAX_MMDC_IO_NUM(36) definition */ +#define PM_INFO_MMDC_NUM_OFFSET 0x208 +#define PM_INFO_MMDC_VAL_OFFSET 0x20C #define MX6Q_SRC_GPR1 0x20 #define MX6Q_SRC_GPR2 0x24 +#define MX6Q_MMDC_MISC 0x18 #define MX6Q_MMDC_MAPSR 0x404 #define MX6Q_MMDC_MPDGCTRL0 0x83c #define MX6Q_GPC_IMR1 0x08 @@ -65,9 +74,49 @@ #define MX6Q_GPC_IMR3 0x10 #define MX6Q_GPC_IMR4 0x14 #define MX6Q_CCM_CCR 0x0 +#define MX6Q_ANATOP_CORE 0x140 .align 3 + /* Check if the cpu is cortex-a7 */ + .macro is_cortex_a7 + + /* Read the primary cpu number is MPIDR */ + mrc p15, 0, r5, c0, c0, 0 + ldr r6, =0xfff0 + and r5, r5, r6 + ldr r6, =0xc070 + cmp r5, r6 + + .endm + + .macro disable_l1_cache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 -r10, lr} + ldr r7, = v7_flush_dcache_all + mov lr, pc + mov pc , r7 + pop {r0 -r10, lr} + + .endm + .macro sync_l2_cache /* sync L2 cache to drain L2's buffers to DRAM. */ @@ -86,29 +135,8 @@ .endm - .macro resume_mmdc - - /* restore MMDC IO */ - cmp r5, #0x0 - ldreq r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] - ldrne r11, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] - - ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] - ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET - add r7, r7, r0 -1: - ldr r8, [r7], #0x4 - ldr r9, [r7], #0x4 - str r9, [r11, r8] - subs r6, r6, #0x1 - bne 1b - - cmp r5, #0x0 - ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] - ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] - - cmp r3, #IMX_DDR_TYPE_LPDDR2 - bne 4f + /* r11 must be MMDC base address */ + .macro reset_read_fifo /* reset read FIFO, RST_RD_FIFO */ ldr r7, =MX6Q_MMDC_MPDGCTRL0 @@ -128,23 +156,294 @@ ldr r6, [r11, r7] ands r6, r6, #(1 << 31) bne 3b + + /* check if lppdr2 2 channel mode is enabled */ + ldr r7, =MX6Q_MMDC_MISC + ldr r6, [r11, r7] + ands r6, r6, #(1 << 2) + beq 6f + + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r12, r7] + orr r6, r6, #(1 << 31) + str r6, [r12, r7] 4: + ldr r6, [r12, r7] + ands r6, r6, #(1 << 31) + bne 4b + + ldr r6, [r12, r7] + orr r6, r6, #(1 << 31) + str r6, [r12, r7] +5: + ldr r6, [r12, r7] + ands r6, r6, #(1 << 31) + bne 5b + +6: + .endm + + /* r11 must be MMDC base address */ + .macro mmdc_out_and_auto_self_refresh + /* let DDR out of self-refresh */ ldr r7, [r11, #MX6Q_MMDC_MAPSR] bic r7, r7, #(1 << 21) str r7, [r11, #MX6Q_MMDC_MAPSR] -5: +7: ldr r7, [r11, #MX6Q_MMDC_MAPSR] ands r7, r7, #(1 << 25) - bne 5b + bne 7b /* enable DDR auto power saving */ ldr r7, [r11, #MX6Q_MMDC_MAPSR] bic r7, r7, #0x1 str r7, [r11, #MX6Q_MMDC_MAPSR] + /* check if lppdr2 2 channel mode is enabled */ + ldr r7, =MX6Q_MMDC_MISC + ldr r6, [r11, r7] + ands r6, r6, #(1 << 2) + beq 9f + + ldr r7, [r12, #MX6Q_MMDC_MAPSR] + bic r7, r7, #(1 << 21) + str r7, [r12, #MX6Q_MMDC_MAPSR] +8: + ldr r7, [r12, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + bne 8b + + ldr r7, [r12, #MX6Q_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r12, #MX6Q_MMDC_MAPSR] +9: + .endm + + /* r10 must be iomuxc base address */ + .macro resume_iomuxc_gpr + + add r10, r10, #0x4000 + /* IOMUXC GPR DRAM_RESET_BYPASS */ + ldr r4, [r10, #0x8] + bic r4, r4, #(0x1 << 27) + str r4, [r10, #0x8] + /* IOMUXC GPR DRAM_CKE_BYPASS */ + ldr r4, [r10, #0x8] + bic r4, r4, #(0x1 << 31) + str r4, [r10, #0x8] + + .endm + + .macro resume_io + + /* restore MMDC IO */ + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] + + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +10: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x8 + str r9, [r10, r8] + subs r6, r6, #0x1 + bne 10b + + cmp r5, #0x0 + /* Here only MMDC0 is set */ + ldreq r11, [r0, #PM_INFO_MX6Q_MMDC0_V_OFFSET] + ldrne r11, [r0, #PM_INFO_MX6Q_MMDC0_P_OFFSET] + ldreq r12, [r0, #PM_INFO_MX6Q_MMDC1_V_OFFSET] + ldrne r12, [r0, #PM_INFO_MX6Q_MMDC1_P_OFFSET] + + reset_read_fifo + mmdc_out_and_auto_self_refresh + + .endm + + .macro resume_mmdc_io + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] + ldreq r11, [r0, #PM_INFO_MX6Q_MMDC0_V_OFFSET] + ldrne r11, [r0, #PM_INFO_MX6Q_MMDC0_P_OFFSET] + + /* resume mmdc iomuxc settings */ + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +11: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x8 + str r9, [r10, r8] + subs r6, r6, #0x1 + bne 11b + + /* check whether we need to restore MMDC */ + cmp r5, #0x0 + beq 12f + + /* check whether last suspend is with M/F mix off */ + ldr r9, [r0, #PM_INFO_MX6Q_GPC_P_OFFSET] + ldr r6, [r9, #0x220] + cmp r6, #0x0 + bne 13f +12: + resume_iomuxc_gpr + reset_read_fifo + + b 17f +13: + /* restore MMDC settings */ + ldr r6, [r0, #PM_INFO_MMDC_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_VAL_OFFSET + add r7, r7, r0 +14: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r11, r8] + subs r6, r6, #0x1 + bne 14b + + /* let DDR enter self-refresh */ + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + orr r7, r7, #(1 << 20) + str r7, [r11, #MX6Q_MMDC_MAPSR] +15: + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 24) + beq 15b + + resume_iomuxc_gpr + reset_read_fifo + + /* let DDR out of self-refresh */ + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + bic r7, r7, #(1 << 20) + str r7, [r11, #MX6Q_MMDC_MAPSR] +16: + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 24) + bne 16b + + /* kick off MMDC */ + ldr r4, =0x0 + str r4, [r11, #0x1c] + +17: + mmdc_out_and_auto_self_refresh + + .endm + + .macro store_ttbr1 + + /* Store TTBR1 to pm_info->ttbr1 */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_MX6Q_TTBR1_V_OFFSET] + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + ldr r6, =iram_tlb_phys_addr + ldr r6, [r6] + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r6, c2, c0, 1 + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Disable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + is_cortex_a7 + beq 17f + +#ifdef CONFIG_CACHE_L2X0 + ldr r8, [r0, #PM_INFO_MX6Q_L2_V_OFFSET] + mov r6, #0x0 + str r6, [r8, #0x100] + + dsb + isb +#endif +17: .endm + .macro restore_ttbr1 + + is_cortex_a7 + beq 18f + +#ifdef CONFIG_CACHE_L2X0 + /* Enable L2. */ + ldr r8, [r0, #PM_INFO_MX6Q_L2_V_OFFSET] + ldr r7, =0x1 + str r7, [r8, #0x100] +#endif + +18: + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + /* Restore TTBCR */ + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Restore TTBR1, get the origin ttbr1 from pm info */ + ldr r7, [r0, #PM_INFO_MX6Q_TTBR1_V_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + + ENTRY(imx6_suspend) ldr r1, [r0, #PM_INFO_PBASE_OFFSET] ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET] @@ -179,10 +478,25 @@ ENTRY(imx6_suspend) str r9, [r11, #MX6Q_SRC_GPR1] str r1, [r11, #MX6Q_SRC_GPR2] + /* + * Check if the cpu is Cortex-A7, for Cortex-A7 + * the cache implementation is not the same as + * Cortex-A9, so the cache maintenance operation + * is different. + */ + is_cortex_a7 + beq a7_dache_flush + /* need to sync L2 cache before DSM. */ sync_l2_cache - - ldr r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + b ttbr_store +a7_dache_flush: + disable_l1_cache +ttbr_store: + store_ttbr1 + + ldr r11, [r0, #PM_INFO_MX6Q_MMDC0_V_OFFSET] + ldr r12, [r0, #PM_INFO_MX6Q_MMDC1_V_OFFSET] /* * put DDR explicitly into self-refresh and * disable automatic power savings. @@ -201,31 +515,59 @@ poll_dvfs_set: ands r7, r7, #(1 << 25) beq poll_dvfs_set + /* check if lppdr2 2 channel mode is enabled */ + ldr r7, =MX6Q_MMDC_MISC + ldr r6, [r11, r7] + ands r6, r6, #(1 << 2) + beq skip_self_refresh_ch1 + + ldr r7, [r12, #MX6Q_MMDC_MAPSR] + orr r7, r7, #0x1 + str r7, [r12, #MX6Q_MMDC_MAPSR] + + ldr r7, [r12, #MX6Q_MMDC_MAPSR] + orr r7, r7, #(1 << 21) + str r7, [r12, #MX6Q_MMDC_MAPSR] + +poll_dvfs_set_ch1: + ldr r7, [r12, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + beq poll_dvfs_set_ch1 + +skip_self_refresh_ch1: + /* use r11 to store the IO address */ ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] - ldr r6, =0x0 - ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET add r8, r8, r0 - /* LPDDR2's last 3 IOs need special setting */ - cmp r3, #IMX_DDR_TYPE_LPDDR2 - subeq r7, r7, #0x3 set_mmdc_io_lpm: - ldr r9, [r8], #0x8 - str r6, [r11, r9] - subs r7, r7, #0x1 + ldr r7, [r8], #0x8 + ldr r9, [r8], #0x4 + str r9, [r11, r7] + subs r6, r6, #0x1 bne set_mmdc_io_lpm - cmp r3, #IMX_DDR_TYPE_LPDDR2 - bne set_mmdc_io_lpm_done - ldr r6, =0x1000 - ldr r9, [r8], #0x8 - str r6, [r11, r9] - ldr r9, [r8], #0x8 - str r6, [r11, r9] - ldr r6, =0x80000 - ldr r9, [r8] - str r6, [r11, r9] -set_mmdc_io_lpm_done: + /* check whether it supports Mega/Fast off */ + ldr r6, [r0, #PM_INFO_MMDC_NUM_OFFSET] + cmp r6, #0x0 + beq set_mmdc_lpm_done + + /* IOMUXC GPR DRAM_RESET */ + add r11, r11, #0x4000 + ldr r6, [r11, #0x8] + orr r6, r6, #(0x1 << 28) + str r6, [r11, #0x8] + + /* IOMUXC GPR DRAM_RESET_BYPASS */ + ldr r6, [r11, #0x8] + orr r6, r6, #(0x1 << 27) + str r6, [r11, #0x8] + + /* IOMUXC GPR DRAM_CKE_BYPASS */ + ldr r6, [r11, #0x8] + orr r6, r6, #(0x1 << 31) + str r6, [r11, #0x8] +set_mmdc_lpm_done: /* * mask all GPC interrupts before @@ -285,6 +627,27 @@ rbc_loop: subs r6, r6, #0x1 bne rbc_loop + /* + * ERR005852 Analog: Transition from Deep Sleep Mode to + * LDO Bypass Mode may cause the slow response of the + * VDDARM_CAP output. + * + * Software workaround: + * if internal ldo(VDDARM) bypassed, switch to analog bypass + * mode (0x1E), prio to entering DSM, and then, revert to the + * normal bypass mode, when exiting from DSM. + */ + ldr r11, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldr r10, [r11, #MX6Q_ANATOP_CORE] + and r10, r10, #0x1f + cmp r10, #0x1f + bne ldo_check_done1 +ldo_analog_bypass: + ldr r10, [r11, #MX6Q_ANATOP_CORE] + bic r10, r10, #0x1f + orr r10, r10, #0x1e + str r10, [r11, #MX6Q_ANATOP_CORE] +ldo_check_done1: /* Zzz, enter stop mode */ wfi nop @@ -297,8 +660,28 @@ rbc_loop: * wakeup source, system should auto * resume, we need to restore MMDC IO first */ + /* restore it with 0x1f if use ldo bypass mode.*/ + ldr r10, [r11, #MX6Q_ANATOP_CORE] + and r10, r10, #0x1f + cmp r10, #0x1e + bne ldo_check_done2 +ldo_bypass_restore: + ldr r10, [r11, #MX6Q_ANATOP_CORE] + orr r10, r10, #0x1f + str r10, [r11, #MX6Q_ANATOP_CORE] +ldo_check_done2: mov r5, #0x0 - resume_mmdc + /* check whether it supports Mega/Fast off */ + ldr r6, [r0, #PM_INFO_MMDC_NUM_OFFSET] + cmp r6, #0x0 + beq only_resume_io + resume_mmdc_io + b resume_mmdc_done +only_resume_io: + resume_io +resume_mmdc_done: + + restore_ttbr1 /* return to suspend finish */ ret lr @@ -313,6 +696,16 @@ resume: mcr p15, 0, r6, c1, c0, 0 isb + /* restore it with 0x1f if use ldo bypass mode.*/ + ldr r11, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + ldr r7, [r11, #MX6Q_ANATOP_CORE] + and r7, r7, #0x1f + cmp r7, #0x1e + bne ldo_check_done3 + ldr r7, [r11, #MX6Q_ANATOP_CORE] + orr r7, r7, #0x1f + str r7, [r11, #MX6Q_ANATOP_CORE] +ldo_check_done3: /* get physical resume address from pm_info. */ ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] /* clear core0's entry and parameter */ @@ -323,7 +716,16 @@ resume: ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET] mov r5, #0x1 - resume_mmdc + /* check whether it supports Mega/Fast off */ + ldr r6, [r0, #PM_INFO_MMDC_NUM_OFFSET] + cmp r6, #0x0 + beq dsm_only_resume_io + resume_mmdc_io + b dsm_resume_mmdc_done +dsm_only_resume_io: + ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET] + resume_io +dsm_resume_mmdc_done: ret lr ENDPROC(imx6_suspend) diff --git a/arch/arm/mach-imx/suspend-imx7.S b/arch/arm/mach-imx/suspend-imx7.S new file mode 100644 index 00000000000000..5f4e31152a69a9 --- /dev/null +++ b/arch/arm/mach-imx/suspend-imx7.S @@ -0,0 +1,714 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include "hardware.h" + +/* + * ==================== low level suspend ==================== + * + * Better to follow below rules to use ARM registers: + * r0: pm_info structure address; + * r1 ~ r4: for saving pm_info members; + * r5 ~ r10: free registers; + * r11: io base address. + * + * suspend ocram space layout: + * ======================== high address ====================== + * . + * . + * . + * ^ + * ^ + * ^ + * imx7_suspend code + * PM_INFO structure(imx7_cpu_pm_info) + * ======================== low address ======================= + */ + +/* + * Below offsets are based on struct imx7_cpu_pm_info + * which defined in arch/arm/mach-imx/pm-imx7.c, this + * structure contains necessary pm info for low level + * suspend related code. + */ +#define PM_INFO_M4_RESERVE0_OFFSET 0x0 +#define PM_INFO_M4_RESERVE1_OFFSET 0x4 +#define PM_INFO_M4_RESERVE2_OFFSET 0x8 +#define PM_INFO_PBASE_OFFSET 0xc +#define PM_INFO_RESUME_ADDR_OFFSET 0x10 +#define PM_INFO_DDR_TYPE_OFFSET 0x14 +#define PM_INFO_PM_INFO_SIZE_OFFSET 0x18 +#define PM_INFO_MX7_DDRC_P_OFFSET 0x1c +#define PM_INFO_MX7_DDRC_V_OFFSET 0x20 +#define PM_INFO_MX7_DDRC_PHY_P_OFFSET 0x24 +#define PM_INFO_MX7_DDRC_PHY_V_OFFSET 0x28 +#define PM_INFO_MX7_SRC_P_OFFSET 0x2c +#define PM_INFO_MX7_SRC_V_OFFSET 0x30 +#define PM_INFO_MX7_IOMUXC_GPR_P_OFFSET 0x34 +#define PM_INFO_MX7_IOMUXC_GPR_V_OFFSET 0x38 +#define PM_INFO_MX7_CCM_P_OFFSET 0x3c +#define PM_INFO_MX7_CCM_V_OFFSET 0x40 +#define PM_INFO_MX7_GPC_P_OFFSET 0x44 +#define PM_INFO_MX7_GPC_V_OFFSET 0x48 +#define PM_INFO_MX7_SNVS_P_OFFSET 0x4c +#define PM_INFO_MX7_SNVS_V_OFFSET 0x50 +#define PM_INFO_MX7_ANATOP_P_OFFSET 0x54 +#define PM_INFO_MX7_ANATOP_V_OFFSET 0x58 +#define PM_INFO_MX7_LPSR_P_OFFSET 0x5c +#define PM_INFO_MX7_LPSR_V_OFFSET 0x60 +#define PM_INFO_MX7_GIC_DIST_P_OFFSET 0x64 +#define PM_INFO_MX7_GIC_DIST_V_OFFSET 0x68 +#define PM_INFO_MX7_TTBR1_V_OFFSET 0x6c +#define PM_INFO_DDRC_REG_NUM_OFFSET 0x70 +#define PM_INFO_DDRC_REG_OFFSET 0x74 +#define PM_INFO_DDRC_VALUE_OFFSET 0x78 +#define PM_INFO_DDRC_PHY_REG_NUM_OFFSET 0x174 +#define PM_INFO_DDRC_PHY_REG_OFFSET 0x178 +#define PM_INFO_DDRC_PHY_VALUE_OFFSET 0x17c + +#define MX7_SRC_GPR1 0x74 +#define MX7_SRC_GPR2 0x78 +#define GPC_PGC_C0 0x800 +#define GPC_PGC_FM 0xa00 +#define ANADIG_SNVS_MISC_CTRL 0x380 +#define ANADIG_SNVS_MISC_CTRL_SET 0x384 +#define ANADIG_SNVS_MISC_CTRL_CLR 0x388 +#define ANADIG_DIGPROG 0x800 +#define DDRC_STAT 0x4 +#define DDRC_PWRCTL 0x30 +#define DDRC_PSTAT 0x3fc +#define DDRC_PCTRL_0 0x490 +#define DDRC_DFIMISC 0x1b0 +#define DDRC_SWCTL 0x320 +#define DDRC_SWSTAT 0x324 +#define DDRPHY_LP_CON0 0x18 + +#define CCM_SNVS_LPCG 0x250 +#define MX7D_GPC_IMR1 0x30 +#define MX7D_GPC_IMR2 0x34 +#define MX7D_GPC_IMR3 0x38 +#define MX7D_GPC_IMR4 0x3c + + .align 3 + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + .endm + + .macro store_ttbr1 + + /* Store TTBR1 to pm_info->ttbr1 */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_MX7_TTBR1_V_OFFSET] + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + ldr r6, =iram_tlb_phys_addr + ldr r6, [r6] + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r6, c2, c0, 1 + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + .endm + + .macro restore_ttbr1 + + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + /* Restore TTBCR */ + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Restore TTBR1, get the origin ttbr1 from pm info */ + ldr r7, [r0, #PM_INFO_MX7_TTBR1_V_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + + .macro ddrc_enter_self_refresh + + ldr r11, [r0, #PM_INFO_MX7_DDRC_V_OFFSET] + + /* let DDR out of self-refresh */ + ldr r7, =0x0 + str r7, [r11, #DDRC_PWRCTL] + + /* wait rw port_busy clear */ + ldr r6, =(0x1 << 16) + orr r6, r6, #0x1 +1: + ldr r7, [r11, #DDRC_PSTAT] + ands r7, r7, r6 + bne 1b + + /* enter self-refresh bit 5 */ + ldr r7, =(0x1 << 5) + str r7, [r11, #DDRC_PWRCTL] + + /* wait until self-refresh mode entered */ +2: + ldr r7, [r11, #DDRC_STAT] + and r7, r7, #0x3 + cmp r7, #0x3 + bne 2b +3: + ldr r7, [r11, #DDRC_STAT] + ands r7, r7, #0x20 + beq 3b + + /* disable dram clk */ + ldr r7, [r11, #DDRC_PWRCTL] + orr r7, r7, #(1 << 3) + str r7, [r11, #DDRC_PWRCTL] + + .endm + + .macro ddrc_exit_self_refresh + + cmp r5, #0x0 + ldreq r11, [r0, #PM_INFO_MX7_DDRC_V_OFFSET] + ldrne r11, [r0, #PM_INFO_MX7_DDRC_P_OFFSET] + + /* let DDR out of self-refresh */ + ldr r7, =0x0 + str r7, [r11, #DDRC_PWRCTL] + + /* wait until self-refresh mode entered */ +4: + ldr r7, [r11, #DDRC_STAT] + and r7, r7, #0x3 + cmp r7, #0x3 + beq 4b + + /* enable auto self-refresh */ + ldr r7, [r11, #DDRC_PWRCTL] + orr r7, r7, #(1 << 0) + str r7, [r11, #DDRC_PWRCTL] + + .endm + + .macro wait_delay +5: + subs r6, r6, #0x1 + bne 5b + + .endm + + .macro ddr_enter_retention + + ldr r11, [r0, #PM_INFO_MX7_DDRC_V_OFFSET] + + /* let DDR out of self-refresh */ + ldr r7, =0x0 + str r7, [r11, #DDRC_PCTRL_0] + + /* wait rw port_busy clear */ + ldr r6, =(0x1 << 16) + orr r6, r6, #0x1 +6: + ldr r7, [r11, #DDRC_PSTAT] + ands r7, r7, r6 + bne 6b + + ldr r11, [r0, #PM_INFO_MX7_DDRC_V_OFFSET] + /* enter self-refresh bit 5 */ + ldr r7, =(0x1 << 5) + str r7, [r11, #DDRC_PWRCTL] + + /* wait until self-refresh mode entered */ +7: + ldr r7, [r11, #DDRC_STAT] + and r7, r7, #0x3 + cmp r7, #0x3 + bne 7b +8: + ldr r7, [r11, #DDRC_STAT] + ands r7, r7, #0x20 + beq 8b + + /* disable dram clk */ + ldr r7, =(0x1 << 5) + orr r7, r7, #(1 << 3) + str r7, [r11, #DDRC_PWRCTL] + + ldr r11, [r0, #PM_INFO_MX7_ANATOP_V_OFFSET] + ldr r7, [r11, #ANADIG_DIGPROG] + and r7, r7, #0xff + cmp r7, #0x11 + bne 10f + + /* TO 1.1 */ + ldr r11, [r0, #PM_INFO_MX7_IOMUXC_GPR_V_OFFSET] + ldr r7, =0x38000000 + str r7, [r11] + + /* LPSR mode need to use TO1.0 flow as IOMUX lost power */ + ldr r10, [r0, #PM_INFO_MX7_LPSR_V_OFFSET] + ldr r7, [r10] + cmp r7, #0x0 + beq 11f +10: + /* reset ddr_phy */ + ldr r11, [r0, #PM_INFO_MX7_ANATOP_V_OFFSET] + ldr r7, =0x0 + str r7, [r11, #ANADIG_SNVS_MISC_CTRL] + + /* delay 7 us */ + ldr r6, =6000 + wait_delay + + ldr r11, [r0, #PM_INFO_MX7_SRC_V_OFFSET] + ldr r6, =0x1000 + ldr r7, [r11, r6] + orr r7, r7, #0x1 + str r7, [r11, r6] +11: + /* turn off ddr power */ + ldr r11, [r0, #PM_INFO_MX7_ANATOP_V_OFFSET] + ldr r7, =(0x1 << 29) + str r7, [r11, #ANADIG_SNVS_MISC_CTRL_SET] + + ldr r11, [r0, #PM_INFO_MX7_SRC_V_OFFSET] + ldr r6, =0x1000 + ldr r7, [r11, r6] + orr r7, r7, #0x1 + str r7, [r11, r6] + + .endm + + .macro ddr_exit_retention + + cmp r5, #0x0 + ldreq r1, [r0, #PM_INFO_MX7_ANATOP_V_OFFSET] + ldrne r1, [r0, #PM_INFO_MX7_ANATOP_P_OFFSET] + ldreq r2, [r0, #PM_INFO_MX7_SRC_V_OFFSET] + ldrne r2, [r0, #PM_INFO_MX7_SRC_P_OFFSET] + ldreq r3, [r0, #PM_INFO_MX7_DDRC_V_OFFSET] + ldrne r3, [r0, #PM_INFO_MX7_DDRC_P_OFFSET] + ldreq r4, [r0, #PM_INFO_MX7_DDRC_PHY_V_OFFSET] + ldrne r4, [r0, #PM_INFO_MX7_DDRC_PHY_P_OFFSET] + ldreq r10, [r0, #PM_INFO_MX7_CCM_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX7_CCM_P_OFFSET] + ldreq r11, [r0, #PM_INFO_MX7_IOMUXC_GPR_V_OFFSET] + ldrne r11, [r0, #PM_INFO_MX7_IOMUXC_GPR_P_OFFSET] + + /* turn on ddr power */ + ldr r7, =(0x1 << 29) + str r7, [r1, #ANADIG_SNVS_MISC_CTRL_CLR] + + ldr r6, =50 + wait_delay + + /* clear ddr_phy reset */ + ldr r6, =0x1000 + ldr r7, [r2, r6] + orr r7, r7, #0x3 + str r7, [r2, r6] + ldr r7, [r2, r6] + bic r7, r7, #0x1 + str r7, [r2, r6] +13: + ldr r6, [r0, #PM_INFO_DDRC_REG_NUM_OFFSET] + ldr r7, =PM_INFO_DDRC_REG_OFFSET + add r7, r7, r0 +14: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r3, r8] + subs r6, r6, #0x1 + bne 14b + ldr r7, =0x20 + str r7, [r3, #DDRC_PWRCTL] + ldr r7, =0x0 + str r7, [r3, #DDRC_DFIMISC] + + /* do PHY, clear ddr_phy reset */ + ldr r6, =0x1000 + ldr r7, [r2, r6] + bic r7, r7, #0x2 + str r7, [r2, r6] + + ldr r7, [r1, #ANADIG_DIGPROG] + and r7, r7, #0xff + cmp r7, #0x11 + bne 12f + + /* + * TKT262940: + * System hang when press RST for DDR PAD is + * in retention mode, fixed on TO1.1 + */ + ldr r7, [r11] + bic r7, r7, #(1 << 27) + str r7, [r11] + ldr r7, [r11] + bic r7, r7, #(1 << 29) + str r7, [r11] +12: + ldr r7, =(0x1 << 30) + str r7, [r1, #ANADIG_SNVS_MISC_CTRL_SET] + + /* need to delay ~5mS */ + ldr r6, =0x100000 + wait_delay + + ldr r6, [r0, #PM_INFO_DDRC_PHY_REG_NUM_OFFSET] + ldr r7, =PM_INFO_DDRC_PHY_REG_OFFSET + add r7, r7, r0 + +15: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r4, r8] + subs r6, r6, #0x1 + bne 15b + + ldr r7, =0x0 + add r9, r10, #0x4000 + str r7, [r9, #0x130] + + ldr r7, =0x170 + orr r7, r7, #0x8 + str r7, [r11, #0x20] + + ldr r7, =0x2 + add r9, r10, #0x4000 + str r7, [r9, #0x130] + + ldr r7, =0xf + str r7, [r4, #DDRPHY_LP_CON0] + + /* wait until self-refresh mode entered */ +16: + ldr r7, [r3, #DDRC_STAT] + and r7, r7, #0x3 + cmp r7, #0x3 + bne 16b + ldr r7, =0x0 + str r7, [r3, #DDRC_SWCTL] + ldr r7, =0x1 + str r7, [r3, #DDRC_DFIMISC] + ldr r7, =0x1 + str r7, [r3, #DDRC_SWCTL] +17: + ldr r7, [r3, #DDRC_SWSTAT] + and r7, r7, #0x1 + cmp r7, #0x1 + bne 17b +18: + ldr r7, [r3, #DDRC_STAT] + and r7, r7, #0x20 + cmp r7, #0x20 + bne 18b + + /* let DDR out of self-refresh */ + ldr r7, =0x0 + str r7, [r3, #DDRC_PWRCTL] +19: + ldr r7, [r3, #DDRC_STAT] + and r7, r7, #0x30 + cmp r7, #0x0 + bne 19b + +20: + ldr r7, [r3, #DDRC_STAT] + and r7, r7, #0x3 + cmp r7, #0x1 + bne 20b + + /* enable port */ + ldr r7, =0x1 + str r7, [r3, #DDRC_PCTRL_0] + + /* enable auto self-refresh */ + ldr r7, [r3, #DDRC_PWRCTL] + orr r7, r7, #(1 << 0) + str r7, [r3, #DDRC_PWRCTL] + + .endm + +ENTRY(imx7_suspend) + push {r4-r12} + + /* make sure SNVS clk is enabled */ + ldr r11, [r0, #PM_INFO_MX7_CCM_V_OFFSET] + add r11, r11, #0x4000 + ldr r7, =0x3 + str r7, [r11, #CCM_SNVS_LPCG] + + /* check whether it is a standby mode */ + ldr r11, [r0, #PM_INFO_MX7_GPC_V_OFFSET] + ldr r7, [r11, #GPC_PGC_C0] + cmp r7, #0 + beq ddr_only_self_refresh + + /* + * The value of r0 is mapped the same in origin table and IRAM table, + * thus no need to care r0 here. + */ + ldr r1, [r0, #PM_INFO_PBASE_OFFSET] + ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET] + ldr r4, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET] + + /* + * counting the resume address in iram + * to set it in SRC register. + */ + ldr r6, =imx7_suspend + ldr r7, =resume + sub r7, r7, r6 + add r8, r1, r4 + add r9, r8, r7 + + ldr r11, [r0, #PM_INFO_MX7_SRC_V_OFFSET] + /* store physical resume addr and pm_info address. */ + str r9, [r11, #MX7_SRC_GPR1] + str r1, [r11, #MX7_SRC_GPR2] + + disable_l1_dcache + + store_ttbr1 + + ldr r11, [r0, #PM_INFO_MX7_GPC_V_OFFSET] + ldr r7, [r11, #GPC_PGC_FM] + cmp r7, #0 + beq ddr_only_self_refresh + + ddr_enter_retention + /* enter LPSR mode if resume addr is valid */ + ldr r11, [r0, #PM_INFO_MX7_LPSR_V_OFFSET] + ldr r7, [r11] + cmp r7, #0x0 + beq ddr_retention_enter_out + + /* disable STOP mode before entering LPSR */ + ldr r11, [r0, #PM_INFO_MX7_GPC_V_OFFSET] + ldr r7, [r11] + bic r7, #0xf + str r7, [r11] + + /* shut down vddsoc to enter lpsr mode */ + ldr r11, [r0, #PM_INFO_MX7_SNVS_V_OFFSET] + ldr r7, [r11, #0x38] + orr r7, r7, #0x60 + str r7, [r11, #0x38] +wait_shutdown: + wfi + nop + nop + nop + nop + b wait_shutdown + +ddr_only_self_refresh: + ddrc_enter_self_refresh + b wfi +ddr_retention_enter_out: + + ldr r11, [r0, #PM_INFO_MX7_GIC_DIST_V_OFFSET] + ldr r7, =0x0 + ldr r8, =0x1000 + str r7, [r11, r8] + + ldr r11, [r0, #PM_INFO_MX7_GPC_V_OFFSET] + ldr r4, [r11, #MX7D_GPC_IMR1] + ldr r5, [r11, #MX7D_GPC_IMR2] + ldr r6, [r11, #MX7D_GPC_IMR3] + ldr r7, [r11, #MX7D_GPC_IMR4] + + ldr r8, =0xffffffff + str r8, [r11, #MX7D_GPC_IMR1] + str r8, [r11, #MX7D_GPC_IMR2] + str r8, [r11, #MX7D_GPC_IMR3] + str r8, [r11, #MX7D_GPC_IMR4] + + /* + * enable the RBC bypass counter here + * to hold off the interrupts. RBC counter + * = 8 (240us). With this setting, the latency + * from wakeup interrupt to ARM power up + * is ~250uS. + */ + ldr r8, [r11, #0x14] + bic r8, r8, #(0x3f << 24) + orr r8, r8, #(0x8 << 24) + str r8, [r11, #0x14] + + /* enable the counter. */ + ldr r8, [r11, #0x14] + orr r8, r8, #(0x1 << 30) + str r8, [r11, #0x14] + + /* unmask all the GPC interrupts. */ + str r4, [r11, #MX7D_GPC_IMR1] + str r5, [r11, #MX7D_GPC_IMR2] + str r6, [r11, #MX7D_GPC_IMR3] + str r7, [r11, #MX7D_GPC_IMR4] + + /* + * now delay for a short while (3usec) + * ARM is at 1GHz at this point + * so a short loop should be enough. + * this delay is required to ensure that + * the RBC counter can start counting in + * case an interrupt is already pending + * or in case an interrupt arrives just + * as ARM is about to assert DSM_request. + */ + ldr r7, =2000 +rbc_loop: + subs r7, r7, #0x1 + bne rbc_loop +wfi: + /* Zzz, enter stop mode */ + wfi + nop + nop + nop + nop + + mov r5, #0x0 + + ldr r11, [r0, #PM_INFO_MX7_GPC_V_OFFSET] + ldr r7, [r11, #GPC_PGC_FM] + cmp r7, #0 + beq wfi_ddr_self_refresh_out + + ddr_exit_retention + b wfi_ddr_retention_out +wfi_ddr_self_refresh_out: + ddrc_exit_self_refresh +wfi_ddr_retention_out: + + /* check whether it is a standby mode */ + ldr r11, [r0, #PM_INFO_MX7_GPC_V_OFFSET] + ldr r7, [r11, #GPC_PGC_C0] + cmp r7, #0 + beq standby_out + + ldr r11, [r0, #PM_INFO_MX7_GIC_DIST_V_OFFSET] + ldr r7, =0x1 + ldr r8, =0x1000 + str r7, [r11, r8] + + restore_ttbr1 +standby_out: + pop {r4-r12} + /* return to suspend finish */ + mov pc, lr + +resume: + /* invalidate L1 I-cache first */ + mov r6, #0x0 + mcr p15, 0, r6, c7, c5, 0 + mcr p15, 0, r6, c7, c5, 6 + /* enable the Icache and branch prediction */ + mov r6, #0x1800 + mcr p15, 0, r6, c1, c0, 0 + isb + + /* get physical resume address from pm_info. */ + ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + /* clear core0's entry and parameter */ + ldr r11, [r0, #PM_INFO_MX7_SRC_P_OFFSET] + mov r7, #0x0 + str r7, [r11, #MX7_SRC_GPR1] + str r7, [r11, #MX7_SRC_GPR2] + + mov r5, #0x1 + + ldr r11, [r0, #PM_INFO_MX7_GPC_P_OFFSET] + ldr r7, [r11, #GPC_PGC_FM] + cmp r7, #0 + beq dsm_ddr_self_refresh_out + + ddr_exit_retention + b dsm_ddr_retention_out +dsm_ddr_self_refresh_out: + ddrc_exit_self_refresh +dsm_ddr_retention_out: + + mov pc, lr +ENDPROC(imx7_suspend) + +ENTRY(ca7_cpu_resume) + bl v7_invalidate_l1 + b cpu_resume +ENDPROC(ca7_cpu_resume) diff --git a/arch/arm/mach-imx/suspend-imx7ulp.S b/arch/arm/mach-imx/suspend-imx7ulp.S new file mode 100644 index 00000000000000..bd45e460f75f26 --- /dev/null +++ b/arch/arm/mach-imx/suspend-imx7ulp.S @@ -0,0 +1,625 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include "hardware.h" + +/* + * ==================== low level suspend ==================== + * + * Better to follow below rules to use ARM registers: + * r0: pm_info structure address; + * + * suspend ocram space layout: + * ======================== high address ====================== + * . + * . + * . + * ^ + * ^ + * ^ + * imx7ulp_suspend code + * PM_INFO structure(imx7ulp_cpu_pm_info) + * ======================== low address ======================= + */ + +/* + * Below offsets are based on struct imx7ulp_cpu_pm_info + * which defined in arch/arm/mach-imx/pm-imx7ulp.c, this + * structure contains necessary pm info for low level + * suspend related code. + */ +#define PM_INFO_M4_RESERVE0_OFFSET 0x0 +#define PM_INFO_M4_RESERVE1_OFFSET 0x4 +#define PM_INFO_M4_RESERVE2_OFFSET 0x8 +#define PM_INFO_PBASE_OFFSET 0xc +#define PM_INFO_RESUME_ADDR_OFFSET 0x10 +#define PM_INFO_PM_INFO_SIZE_OFFSET 0x14 +#define PM_INFO_PM_INFO_SIM_VBASE_OFFSET 0x18 +#define PM_INFO_PM_INFO_SCG1_VBASE_OFFSET 0x1c +#define PM_INFO_PM_INFO_MMDC_VBASE_OFFSET 0x20 +#define PM_INFO_PM_INFO_MMDC_IO_VBASE_OFFSET 0x24 +#define PM_INFO_PM_INFO_SMC1_VBASE_OFFSET 0x28 +#define PM_INFO_PM_INFO_SCG1_VAL_OFFSET 0x2c +#define PM_INFO_MX7ULP_TTBR1_V_OFFSET 0x70 +#define PM_INFO_MX7ULP_GPIO_REG_OFFSET 0x74 +#define PM_INFO_IOMUX_NUM_OFFSET 0x94 +#define PM_INFO_IOMUX_VAL_OFFSET 0x98 +#define PM_INFO_SELECT_INPUT_NUM_OFFSET 0x268 +#define PM_INFO_SELECT_INPUT_VAL_OFFSET 0x26c +#define PM_INFO_MMDC_IO_NUM_OFFSET 0x3a4 +#define PM_INFO_MMDC_IO_VAL_OFFSET 0x3a8 +/* below offsets depends on MX7ULP_MAX_MMDC_IO_NUM(36) definition */ +#define PM_INFO_MMDC_NUM_OFFSET 0x5a8 +#define PM_INFO_MMDC_VAL_OFFSET 0x5ac + +#define DGO_CTRL0 0x50 +#define DGO_GPR3 0x60 +#define DGO_GPR4 0x64 + +#define MX7ULP_MMDC_MISC 0x18 +#define MX7ULP_MMDC_MAPSR 0x404 +#define MX7ULP_MMDC_MPDGCTRL0 0x83c + +#define SCG_RCCR 0x14 +#define SCG_DDRCCR 0x30 +#define SCG_NICCCR 0x40 +#define SCG_FIRCDIV 0x304 +#define SCG_APLLCSR 0x500 +#define SCG_APLLDIV 0x504 +#define SCG_APLLCFG 0x508 +#define SCG_APLLPFD 0x50c +#define SCG_APLLNUM 0x510 +#define SCG_APLLDENOM 0x514 +#define SCG_SPLLCSR 0x600 +#define SCG_SPLLDIV 0x604 +#define SCG_SPLLCFG 0x608 +#define SCG_SPLLPFD 0x60c +#define SCG_SPLLNUM 0x610 +#define SCG_SPLLDENOM 0x614 +#define SCG_SOSCDIV 0x104 + +#define PMC1_CTRL 0x24 + +#define GPIO_PDOR 0x0 +#define GPIO_PDDR 0x14 +#define GPIO_PORT_NUM 0x4 +#define GPIO_PORT_OFFSET 0x40 + +#define PMCTRL 0x10 + +#define IOMUX_OFFSET 0x0 +#define SELECT_INPUT_OFFSET 0x200 + + .align 3 + + .macro store_ttbr1 + + /* Store TTBR1 to pm_info->ttbr1 */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_MX7ULP_TTBR1_V_OFFSET] + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + ldr r6, =iram_tlb_phys_addr + ldr r6, [r6] + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r6, c2, c0, 1 + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + .endm + + .macro restore_ttbr1 + + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + /* Restore TTBCR */ + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Restore TTBR1, get the origin ttbr1 from pm info */ + ldr r7, [r0, #PM_INFO_MX7ULP_TTBR1_V_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + .endm + + .macro restore_mmdc_settings + + ldr r10, =MX7ULP_MMDC_IO_BASE_ADDR + ldr r11, =MX7ULP_MMDC_BASE_ADDR + + /* resume mmdc iomuxc settings */ + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +11: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r10, r8] + subs r6, r6, #0x1 + bne 11b + + /* restore MMDC settings */ + ldr r6, [r0, #PM_INFO_MMDC_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_VAL_OFFSET + add r7, r7, r0 +1: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r11, r8] + subs r6, r6, #0x1 + bne 1b + + /* let DDR enter self-refresh */ + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + orr r7, r7, #(1 << 20) + str r7, [r11, #MX7ULP_MMDC_MAPSR] +2: + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + ands r7, r7, #(1 << 24) + beq 2b + + /* let DDR out of self-refresh */ + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + bic r7, r7, #(1 << 20) + str r7, [r11, #MX7ULP_MMDC_MAPSR] +3: + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + ands r7, r7, #(1 << 24) + bne 3b + + /* kick off MMDC */ + ldr r4, =0x0 + str r4, [r11, #0x1c] + + /* let DDR out of self-refresh */ + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + bic r7, r7, #(1 << 20) + str r7, [r11, #MX7ULP_MMDC_MAPSR] +4: + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + ands r7, r7, #(1 << 24) + bne 4b + + /* enable DDR auto power saving */ + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r11, #MX7ULP_MMDC_MAPSR] + + .endm + +ENTRY(imx7ulp_suspend) + push {r4-r12} + + /* + * The value of r0 is mapped the same in origin table and IRAM table, + * thus no need to care r0 here. + */ + ldr r1, [r0, #PM_INFO_PBASE_OFFSET] + ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + ldr r3, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET] + + /* + * counting the resume address in iram + * to set it in SRC register. + */ + ldr r6, =imx7ulp_suspend + ldr r7, =resume + sub r7, r7, r6 + add r8, r1, r3 + add r9, r8, r7 + + ldr r11, [r0, #PM_INFO_PM_INFO_SIM_VBASE_OFFSET] + /* store physical resume addr and pm_info address. */ + str r9, [r11, #DGO_GPR3] + str r1, [r11, #DGO_GPR4] + ldr r7, [r11, #DGO_CTRL0] + orr r7, r7, #0xc + str r7, [r11, #DGO_CTRL0] +wait_dgo: + ldr r7, [r11, #DGO_CTRL0] + and r7, r7, #0x18000 + cmp r7, #0x18000 + bne wait_dgo + + ldr r7, [r11, #DGO_CTRL0] + orr r7, r7, #0x18000 + bic r7, r7, #0xc + str r7, [r11, #DGO_CTRL0] + + disable_l1_dcache + + store_ttbr1 + + ldr r11, [r0, #PM_INFO_PM_INFO_MMDC_VBASE_OFFSET] + + /* + * put DDR explicitly into self-refresh and + * disable automatic power savings. + */ + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + orr r7, r7, #0x1 + str r7, [r11, #MX7ULP_MMDC_MAPSR] + + /* make the DDR explicitly enter self-refresh. */ + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + orr r7, r7, #(1 << 20) + str r7, [r11, #MX7ULP_MMDC_MAPSR] + +poll_dvfs_set: + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + ands r7, r7, #(1 << 24) + beq poll_dvfs_set + + /* put mmdc io into lpm */ + ldr r11, [r0, #PM_INFO_PM_INFO_MMDC_IO_VBASE_OFFSET] + ldr r10, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +mmdc_io_lpm: + ldr r8, [r7], #0x8 + mov r9, #0x0 + str r9, [r11, r8] + subs r10, r10, #0x1 + bne mmdc_io_lpm + + /* switch NIC clock to FIRC */ + ldr r10, [r0, #PM_INFO_PM_INFO_SCG1_VBASE_OFFSET] + ldr r7, [r10, #SCG_NICCCR] + bic r7, #(1 << 28) + str r7, [r10, #SCG_NICCCR] + + /* switch RUN clock to FIRC */ + ldr r7, [r10, #SCG_RCCR] + bic r7, #(0xf << 24) + orr r7, #(0x3 << 24) + str r7, [r10, #SCG_RCCR] + + /* turn off SPLL and SPFD */ + ldr r7, [r10, #SCG_SPLLPFD] + mov r8, r7 + orr r7, r7, #(0x1 << 31) + orr r7, r7, #(0x1 << 23) + orr r7, r7, #(0x1 << 15) + orr r7, r7, #(0x1 << 7) + str r7, [r10, #SCG_SPLLPFD] + + ldr r7, [r10, #SCG_SPLLCSR] + bic r7, r7, #0x1 + str r7, [r10, #SCG_SPLLCSR] + + /* turn off APLL and APFD */ + ldr r7, [r10, #SCG_APLLPFD] + mov r9, r7 + orr r7, r7, #(0x1 << 31) + orr r7, r7, #(0x1 << 23) + orr r7, r7, #(0x1 << 15) + orr r7, r7, #(0x1 << 7) + str r7, [r10, #SCG_APLLPFD] + + ldr r7, [r10, #SCG_APLLCSR] + bic r7, r7, #0x1 + str r7, [r10, #SCG_APLLCSR] + + /* Zzz, enter stop mode */ + wfi + nop + nop + nop + nop + + /* clear core0's entry and parameter */ + ldr r10, [r0, #PM_INFO_PM_INFO_SIM_VBASE_OFFSET] + mov r7, #0x0 + str r7, [r10, #DGO_GPR3] + str r7, [r10, #DGO_GPR4] + + /* enable SPLL and SPFD */ + ldr r10, [r0, #PM_INFO_PM_INFO_SCG1_VBASE_OFFSET] + ldr r7, [r10, #SCG_SPLLCSR] + orr r7, r7, #1 + str r7, [r10, #SCG_SPLLCSR] +wait_spll: + ldr r7, [r10, #SCG_SPLLCSR] + ands r7, r7, #(1 << 24) + beq wait_spll + + str r8, [r10, #SCG_SPLLPFD] + /* switch RUN clock to SPLL */ + ldr r7, [r10, #SCG_RCCR] + bic r7, #(0xf << 24) + orr r7, #(0x6 << 24) + str r7, [r10, #SCG_RCCR] + + /* enable APLL and APFD */ + ldr r7, [r10, #SCG_APLLCSR] + orr r7, r7, #1 + str r7, [r10, #SCG_APLLCSR] +wait_apll: + ldr r7, [r10, #SCG_APLLCSR] + ands r7, r7, #(1 << 24) + beq wait_apll + + str r9, [r10, #SCG_APLLPFD] + + /* switch NIC clock to DDR */ + ldr r7, [r10, #SCG_NICCCR] + orr r7, #(1 << 28) + str r7, [r10, #SCG_NICCCR] + + /* let mmdc io out of lpm */ + ldr r11, [r0, #PM_INFO_PM_INFO_MMDC_IO_VBASE_OFFSET] + ldr r10, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +mmdc_io_exit_lpm: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r11, r8] + subs r10, r10, #0x1 + bne mmdc_io_exit_lpm + + /* let DDR out of self-refresh */ + ldr r11, [r0, #PM_INFO_PM_INFO_MMDC_VBASE_OFFSET] + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + bic r7, r7, #(1 << 20) + str r7, [r11, #MX7ULP_MMDC_MAPSR] +poll_dvfs_clear: + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + ands r7, r7, #(1 << 24) + bne poll_dvfs_clear + + /* enable DDR auto power saving */ + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r11, #MX7ULP_MMDC_MAPSR] + + restore_ttbr1 + pop {r4-r12} + /* return to suspend finish */ + mov pc, lr + +resume: + /* invalidate L1 I-cache first */ + mov r6, #0x0 + mcr p15, 0, r6, c7, c5, 0 + mcr p15, 0, r6, c7, c5, 6 + /* enable the Icache and branch prediction */ + mov r6, #0x1800 + mcr p15, 0, r6, c1, c0, 0 + isb + + ldr r6, =MX7ULP_SIM_BASE_ADDR + ldr r0, [r6, #DGO_GPR4] + /* get physical resume address from pm_info. */ + ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + + ldr r11, =MX7ULP_SCG1_BASE_ADDR + /* enable spll and pfd0 */ + ldr r5, =PM_INFO_PM_INFO_SCG1_VAL_OFFSET + add r6, r5, #48 + ldr r7, [r0, r6] + str r7, [r11, #SCG_SPLLCFG] + + add r6, r5, #56 + ldr r7, [r0, r6] + str r7, [r11, #SCG_SPLLNUM] + + add r6, r5, #60 + ldr r7, [r0, r6] + str r7, [r11, #SCG_SPLLDENOM] + + add r6, r5, #40 + ldr r7, [r0, r6] + str r7, [r11, #SCG_SPLLCSR] +5: + ldr r7, [r11, #SCG_SPLLCSR] + ands r7, r7, #0x1000000 + beq 5b + + add r6, r5, #44 + ldr r7, [r0, r6] + str r7, [r11, #SCG_SPLLDIV] + + add r6, r5, #52 + ldr r7, [r0, r6] + str r7, [r11, #SCG_SPLLPFD] + + add r6, r5, #0 + ldr r7, [r0, r6] + str r7, [r11, #SCG_RCCR] + + /* enable apll and pfd0 */ + add r6, r5, #24 + ldr r7, [r0, r6] + str r7, [r11, #SCG_APLLCFG] + + add r6, r5, #32 + ldr r7, [r0, r6] + str r7, [r11, #SCG_APLLNUM] + + add r6, r5, #36 + ldr r7, [r0, r6] + str r7, [r11, #SCG_APLLDENOM] + + add r6, r5, #16 + ldr r7, [r0, r6] + str r7, [r11, #SCG_APLLCSR] +6: + ldr r7, [r11, #SCG_APLLCSR] + ands r7, r7, #0x1000000 + beq 6b + + add r6, r5, #20 + ldr r7, [r0, r6] + str r7, [r11, #SCG_APLLDIV] + + add r6, r5, #28 + ldr r7, [r0, r6] + str r7, [r11, #SCG_APLLPFD] + + /* set ddr ccr */ + add r6, r5, #4 + ldr r7, [r0, r6] + str r7, [r11, #SCG_DDRCCR] + + /* set nic sel */ + add r6, r5, #8 + ldr r7, [r0, r6] + str r7, [r11, #SCG_NICCCR] + + /* set firc div2 to get 48MHz */ + add r6, r5, #12 + ldr r7, [r0, r6] + str r7, [r11, #SCG_FIRCDIV] + + /* restore system OSC div */ + add r6, r5, #64 + ldr r7, [r0, r6] + str r7, [r11, #SCG_SOSCDIV] + + /* enable mmdc clock in pcc3 */ + ldr r11, =MX7ULP_PCC3_BASE_ADDR + ldr r7, [r11, #0xac] + orr r7, r7, #(1 << 30) + str r7, [r11, #0xac] + + /* enable GPIO clock in pcc2 */ + ldr r11, =MX7ULP_PCC2_BASE_ADDR + ldr r7, [r11, #0x3c] + orr r7, r7, #(1 << 30) + str r7, [r11, #0x3c] + + /* restore gpio settings */ + ldr r10, =MX7ULP_GPIOC_BASE_ADDR + ldr r7, =PM_INFO_MX7ULP_GPIO_REG_OFFSET + add r7, r7, r0 + ldr r6, =GPIO_PORT_NUM +12: + ldr r9, [r7], #0x4 + str r9, [r10, #GPIO_PDOR] + ldr r9, [r7], #0x4 + str r9, [r10, #GPIO_PDDR] + add r10, r10, #GPIO_PORT_OFFSET + subs r6, r6, #0x1 + bne 12b + + /* restore iomuxc settings */ + ldr r10, =MX7ULP_IOMUXC1_BASE_ADDR + add r10, r10, #IOMUX_OFFSET + ldr r6, [r0, #PM_INFO_IOMUX_NUM_OFFSET] + ldr r7, =PM_INFO_IOMUX_VAL_OFFSET + add r7, r7, r0 +13: + ldr r9, [r7], #0x4 + str r9, [r10], #0x4 + subs r6, r6, #0x1 + bne 13b + + /* restore select input settings */ + ldr r10, =MX7ULP_IOMUXC1_BASE_ADDR + add r10, r10, #SELECT_INPUT_OFFSET + ldr r6, [r0, #PM_INFO_SELECT_INPUT_NUM_OFFSET] + ldr r7, =PM_INFO_SELECT_INPUT_VAL_OFFSET + add r7, r7, r0 +14: + ldr r9, [r7], #0x4 + str r9, [r10], #0x4 + subs r6, r6, #0x1 + bne 14b + + /* isoack */ + ldr r6, =MX7ULP_PMC1_BASE_ADDR + ldr r7, [r6, #PMC1_CTRL] + orr r7, r7, #(1 << 14) + str r7, [r6, #PMC1_CTRL] + + restore_mmdc_settings + + mov pc, lr +ENDPROC(imx7ulp_suspend) + +ENTRY(imx7ulp_cpu_resume) + bl v7_invalidate_l1 + b cpu_resume +ENDPROC(imx7ulp_cpu_resume) diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 27576c7b836ee6..15c8733ce44aa0 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -2320,6 +2320,7 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, #endif dev->archdata.dma_ops_setup = true; } +EXPORT_SYMBOL(arch_setup_dma_ops); void arch_teardown_dma_ops(struct device *dev) { diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index d42b9331618325..5606c0e7fde4cc 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -399,6 +399,13 @@ void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size) } EXPORT_SYMBOL(ioremap_wc); +void __iomem *ioremap_cache_ns(resource_size_t res_cookie, size_t size) +{ + return arch_ioremap_caller(res_cookie, size, MT_MEMORY_RW_NS, + __builtin_return_address(0)); +} +EXPORT_SYMBOL(ioremap_cache_ns); + /* * Remap an arbitrary physical address space into the kernel virtual * address space as memory. Needed when the kernel wants to execute diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 48c2888297dd93..5cf31b4913825a 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -312,6 +312,13 @@ static struct mem_type mem_types[] __ro_after_init = { .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, .domain = DOMAIN_KERNEL, }, + [MT_MEMORY_RW_NS] = { + .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | + L_PTE_XN, + .prot_l1 = PMD_TYPE_TABLE, + .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_XN, + .domain = DOMAIN_KERNEL, + }, [MT_ROM] = { .prot_sect = PMD_TYPE_SECT, .domain = DOMAIN_KERNEL, @@ -648,6 +655,7 @@ static void __init build_mem_type_table(void) } kern_pgprot |= PTE_EXT_AF; vecs_pgprot |= PTE_EXT_AF; + mem_types[MT_MEMORY_RW_NS].prot_pte |= PTE_EXT_AF | cp->pte; /* * Set PXN for user mappings @@ -676,6 +684,7 @@ static void __init build_mem_type_table(void) mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot; mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd; mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot; + mem_types[MT_MEMORY_RW_NS].prot_sect |= ecc_mask | cp->pmd; mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot; mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask; mem_types[MT_ROM].prot_sect |= cp->pmd; diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index a0bc9bbb92f341..d806f5d05cef7b 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1063,7 +1063,7 @@ config XEN Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. config FORCE_MAX_ZONEORDER - int + int "Maximum zone order" default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) default "11" diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 16d761475a8600..5785677c9b31a9 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -171,6 +171,9 @@ config ARCH_MXC select ARM64_ERRATUM_845719 if COMPAT select IMX_GPCV2 select IMX_GPCV2_PM_DOMAINS + select HAVE_IMX_BUSFREQ + select IMX8M_BUSFREQ + select IMX8M_PM_DOMAINS select PM select PM_GENERIC_DOMAINS select SOC_BUS @@ -179,6 +182,9 @@ config ARCH_MXC This enables support for the ARMv8 based SoCs in the NXP i.MX family. +config HAVE_IMX_BUSFREQ + bool "i.MX8M busfreq" + config ARCH_QCOM bool "Qualcomm Platforms" select GPIOLIB @@ -212,6 +218,20 @@ config ARCH_ROCKCHIP This enables support for the ARMv8 based Rockchip chipsets, like the RK3368. +config ARCH_S32 + bool "NXP S32 SoC Family" + select ARCH_S32_CLK + select PINCTRL + help + This enables support for the NXP S32 family of processors. + +if ARCH_S32 +menu "S32 SOC selection" + config SOC_S32V234 + bool "S32V234 SOC" +endmenu +endif + config ARCH_SEATTLE bool "AMD Seattle SoC Family" help diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 93fce8f0c66d83..d5eb439fe4a63d 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -1,34 +1,145 @@ # SPDX-License-Identifier: GPL-2.0 + +# required for overlay support +DTC_FLAGS_fsl-ls1028a-qds := -@ +DTC_FLAGS_fsl-ls1028a-qds-13bb := -@ +DTC_FLAGS_fsl-ls1028a-qds-65bb := -@ +DTC_FLAGS_fsl-ls1028a-qds-7777 := -@ +DTC_FLAGS_fsl-ls1028a-qds-85bb := -@ +DTC_FLAGS_fsl-ls1028a-qds-899b := -@ +DTC_FLAGS_fsl-ls1028a-qds-9999 := -@ + +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-2g5rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-13bb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-65bb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-7777.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-85bb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb-dpdk.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds-sdk.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-sdk.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-usdpaa.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy-sdk.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy-usdpaa.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds-sdk.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-sdk.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-usdpaa.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb imx8mm-evk-rpmsg.dtb imx8mm-evk-rm67191.dtb \ + imx8mm-ddr4-evk.dtb imx8mm-evk-root.dtb imx8mm-evk-inmate.dtb \ + imx8mm-ddr4-evk-rm67191.dtb imx8mm-evk-revb.dtb imx8mm-ddr4-evk-revb.dtb \ + imx8mm-ddr4-evk-revb-rm67191.dtb imx8mm-ddr3l-val.dtb \ + imx8mm-evk-usd-wifi.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-ak4497.dtb imx8mm-evk-ak5558.dtb imx8mm-evk-audio-tdm.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-8mic-revE.dtb imx8mm-evk-8mic-swpdm.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-ab2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb imx8mn-evk-rm67191.dtb imx8mn-ddr4-evk.dtb imx8mn-ddr4-evk-ak5558.dtb \ + imx8mn-ddr4-evk-rm67191.dtb imx8mn-ddr4-evk-rpmsg.dtb imx8mn-ddr4-evk-usd-wifi.dtb \ + imx8mn-evk-ak5558.dtb imx8mn-evk-rpmsg.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk-root.dtb imx8mn-ddr4-evk-inmate.dtb imx8mn-evk-root.dtb imx8mn-evk-inmate.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-ab2.dtb imx8mn-ddr4-ab2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb imx8mp-evk-root.dtb imx8mp-evk-inmate.dtb imx8mp-evk-rpmsg.dtb \ + imx8mp-evk-rm67191.dtb imx8mp-evk-flexcan2.dtb imx8mp-evk-it6263-lvds-dual-channel.dtb \ + imx8mp-evk-jdi-wuxga-lvds-panel.dtb imx8mp-ab2.dtb imx8mp-evk-sof-wm8960.dtb \ + imx8mp-evk-dsp.dtb imx8mp-evk-ov2775.dtb imx8mp-evk-basler.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb imx8mq-evk-rpmsg.dtb imx8mq-evk-pcie1-m2.dtb imx8mq-evk-usd-wifi.dtb \ + imx8mq-evk-usdhc2-m2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-ak4497.dtb imx8mq-evk-audio-tdm.dtb imx8mq-evk-pdm.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-root.dtb imx8mq-evk-inmate.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-lcdif-rm67191.dtb imx8mq-evk-lcdif-adv7535.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-dcss-rm67191.dtb imx8mq-evk-dcss-adv7535.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-dual-display.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-dp.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-ddr3l-val.dtb imx8mq-ddr4-val.dtb imx8mq-ddr4-val-gpmi-nand.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb imx8qm-mek-ov5640.dtb \ + imx8qm-mek-enet2-tja1100.dtb imx8qm-mek-rpmsg.dtb \ + imx8qm-mek-hdmi.dtb imx8qm-mek-dsp.dtb \ + imx8qm-mek-jdi-wuxga-lvds1-panel.dtb \ + imx8qm-mek-jdi-wuxga-lvds1-panel-rpmsg.dtb \ + imx8qm-lpddr4-val.dtb imx8qm-lpddr4-val-mqs.dtb \ + imx8qm-lpddr4-val-spdif.dtb imx8qm-mek-ca53.dtb \ + imx8qm-mek-ca72.dtb imx8qm-lpddr4-val-ca53.dtb \ + imx8qm-lpddr4-val-ca72.dtb imx8qm-ddr4-val.dtb \ + imx8qm-lpddr4-val-lpspi.dtb imx8qm-lpddr4-val-lpspi-slave.dtb \ + imx8qm-mek-dsi-rm67191.dtb imx8qm-lpddr4-val-dp.dtb\ + imx8qp-lpddr4-val.dtb imx8dm-lpddr4-val.dtb imx8qm-pcieax2pciebx1.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-dom0.dtb imx8qm-mek-domu.dtb \ + imx8qm-mek-root.dtb imx8qm-mek-inmate.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8dxl-phantom-mek.dtb \ + imx8dxl-phantom-mek-rpmsg.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb imx8qxp-mek-dsp.dtb imx8qxp-mek-ov5640.dtb \ + imx8qxp-mek-enet2.dtb imx8qxp-mek-enet2-tja1100.dtb \ + imx8qxp-mek-sof-cs42888.dtb imx8qxp-mek-sof-wm8960.dtb \ + imx8qm-mek-sof-cs42888.dtb imx8qm-mek-sof-wm8960.dtb \ + imx8qxp-mek-rpmsg.dtb imx8qxp-mek-a0.dtb \ + imx8qxp-mek-it6263-lvds0-dual-channel.dtb \ + imx8qxp-mek-it6263-lvds1-dual-channel.dtb \ + imx8qxp-mek-it6263-lvds0-dual-channel-rpmsg.dtb \ + imx8qxp-mek-it6263-lvds1-dual-channel-rpmsg.dtb \ + imx8qxp-mek-jdi-wuxga-lvds0-panel.dtb \ + imx8qxp-mek-jdi-wuxga-lvds1-panel.dtb \ + imx8qxp-mek-jdi-wuxga-lvds0-panel-rpmsg.dtb \ + imx8qxp-mek-jdi-wuxga-lvds1-panel-rpmsg.dtb \ + imx8qxp-mek-dsi-rm67191.dtb \ + imx8qxp-mek-dsi-rm67191-rpmsg.dtb \ + imx8qxp-mek-dpu-lcdif.dtb \ + imx8qxp-mek-dpu-lcdif-rpmsg.dtb \ + imx8qxp-mek-ov5640-rpmsg.dtb \ + imx8dx-mek.dtb imx8dx-mek-dsp.dtb imx8dx-mek-rpmsg.dtb \ + imx8dx-mek-enet2-tja1100.dtb \ + imx8dx-mek-ov5640.dtb \ + imx8dx-mek-ov5640-rpmsg.dtb \ + imx8dx-mek-it6263-lvds0-dual-channel.dtb \ + imx8dx-mek-it6263-lvds1-dual-channel.dtb \ + imx8dx-mek-it6263-lvds0-dual-channel-rpmsg.dtb \ + imx8dx-mek-it6263-lvds1-dual-channel-rpmsg.dtb \ + imx8dx-mek-jdi-wuxga-lvds0-panel.dtb \ + imx8dx-mek-jdi-wuxga-lvds1-panel.dtb \ + imx8dx-mek-jdi-wuxga-lvds0-panel-rpmsg.dtb \ + imx8dx-mek-jdi-wuxga-lvds1-panel-rpmsg.dtb \ + imx8dx-mek-dsi-rm67191.dtb \ + imx8dx-mek-dsi-rm67191-rpmsg.dtb \ + imx8qxp-lpddr4-val-a0.dtb \ + imx8qxp-lpddr4-val.dtb imx8qxp-lpddr4-val-mqs.dtb imx8qxp-ddr3l-val.dtb \ + imx8qxp-lpddr4-val-lpspi.dtb imx8qxp-lpddr4-val-lpspi-slave.dtb \ + imx8qxp-lpddr4-val-spdif.dtb imx8qxp-lpddr4-val-gpmi-nand.dtb imx8dxp-lpddr4-val.dtb \ + imx8qxp-17x17-val.dtb imx8dx-lpddr4-val.dtb imx8dx-17x17-val.dtb \ + imx8qxp-lpddr4-val-mlb.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-dom0.dtb imx8qxp-mek-root.dtb \ + imx8qxp-mek-inmate.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb imx8dxl-evk-rpmsg.dtb \ + imx8dxl-evk-enet0.dtb imx8dxl-evk-enet0-tja1100.dtb imx8dxl-evk-pcie.dtb \ + imx8dxl-evk-lpspi-slave.dtb \ + imx8dxl-ddr3-evk.dtb +dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb \ + s32v234-sbc.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts new file mode 100644 index 00000000000000..119bf4b388c6fb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for NXP LS1012A 2G5RDB Board. + * + * Copyright 2017 NXP + * + * Bhaskar Upadhaya + */ +/dts-v1/; + +#include "fsl-ls1012a.dtsi" + +/ { + model = "LS1012A 2G5RDB Board"; + compatible = "fsl,ls1012a-rdb", "fsl,ls1012a"; + + aliases { + ethernet0 = &pfe_mac0; + ethernet1 = &pfe_mac1; + }; +}; + +&duart0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&qspi { + num-cs = <2>; + bus-num = <0>; + status = "okay"; + + qflash0: s25fs512s@0 { + compatible = "spansion,m25p80"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + m25p,fast-read; + reg = <0>; + }; +}; + +&sata { + status = "okay"; +}; + +&pfe { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pfe_mac0: ethernet@0 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* GEM_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii-2500"; + phy-handle = <&sgmii_phy1>; + }; + + pfe_mac1: ethernet@1 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* GEM_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii-2500"; + phy-handle = <&sgmii_phy2>; + }; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; + + sgmii_phy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts index f90c040fd5e8e1..fcc3c271a4d247 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts @@ -13,6 +13,11 @@ model = "LS1012A Freedom Board"; compatible = "fsl,ls1012a-frdm", "fsl,ls1012a"; + aliases { + ethernet0 = &pfe_mac0; + ethernet1 = &pfe_mac1; + }; + sys_mclk: clock-mclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -74,6 +79,45 @@ }; }; +&pfe { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pfe_mac0: ethernet@0 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* GEM_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy1>; + }; + + pfe_mac1: ethernet@1 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* GEM_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy2>; + }; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy1: ethernet-phy@2 { + reg = <0x2>; + }; + + sgmii_phy2: ethernet-phy@1 { + reg = <0x1>; + }; + }; +}; + &sai2 { status = "okay"; }; @@ -81,3 +125,18 @@ &sata { status = "okay"; }; + +&qspi { + status = "okay"; + qflash0: s25fs512s@0 { + compatible = "spansion,m25p80"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + m25p,fast-read; + reg = <0>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; + +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts index 8749634c55ee89..55806119a8a3ca 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts @@ -14,6 +14,58 @@ / { model = "LS1012A FRWY Board"; compatible = "fsl,ls1012a-frwy", "fsl,ls1012a"; + + aliases { + ethernet0 = &pfe_mac0; + ethernet1 = &pfe_mac1; + }; + + sys_mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Speaker", "Speaker Ext", + "Line", "Line In Jack"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "Microphone Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "Speaker Ext", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + frame-master; + bitclock-master; + }; + + simple-audio-card,codec { + sound-dai = <&codec>; + frame-master; + bitclock-master; + system-clock-frequency = <25000000>; + }; + }; +}; + +&pcie { + status = "okay"; }; &duart0 { @@ -22,4 +74,72 @@ &i2c0 { status = "okay"; + + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + reg = <0xa>; + VDDA-supply = <®_1p8v>; + VDDIO-supply = <®_1p8v>; + clocks = <&sys_mclk>; + }; +}; + +&qspi { + num-cs = <1>; + bus-num = <0>; + status = "okay"; + + qflash0: w25q16dw@0 { + compatible = "spansion,m25p80"; + #address-cells = <1>; + #size-cells = <1>; + m25p,fast-read; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&pfe { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pfe_mac0: ethernet@0 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* GEM_ID */ + fsl,gemac-bus-id = <0x0>; /* BUS_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy1>; + }; + + pfe_mac1: ethernet@1 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* GEM_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy2>; + }; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy1: ethernet-phy@2 { + reg = <0x2>; + }; + + sgmii_phy2: ethernet-phy@1 { + reg = <0x1>; + }; + }; +}; + +&sai2 { + status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts index 2fb1cb1f7d8f82..a4fed83900ea73 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts @@ -13,6 +13,11 @@ model = "LS1012A QDS Board"; compatible = "fsl,ls1012a-qds", "fsl,ls1012a"; + aliases { + ethernet0 = &pfe_mac0; + ethernet1 = &pfe_mac1; + }; + sys_mclk: clock-mclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -57,6 +62,10 @@ }; }; +&pcie { + status = "okay"; +}; + &dspi { bus-num = <0>; status = "okay"; @@ -128,6 +137,47 @@ }; }; +&pfe { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pfe_mac0: ethernet@0 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* GEM_ID */ + fsl,mdio-mux-val = <0x2>; + phy-mode = "sgmii-2500"; + phy-handle = <&sgmii_phy1>; + }; + + pfe_mac1: ethernet@1 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* GEM_ID */ + fsl,mdio-mux-val = <0x3>; + phy-mode = "sgmii-2500"; + phy-handle = <&sgmii_phy2>; + }; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; + + sgmii_phy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x2>; + }; + }; +}; + &sai2 { status = "okay"; }; @@ -135,3 +185,18 @@ &sata { status = "okay"; }; + +&qspi { + status = "okay"; + qflash0: s25fs512s@0 { + compatible = "spansion,m25p80"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + m25p,fast-read; + reg = <0>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; + +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts index 5edb1e137a52cf..57a1e0d9b5e801 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts @@ -12,6 +12,15 @@ / { model = "LS1012A RDB Board"; compatible = "fsl,ls1012a-rdb", "fsl,ls1012a"; + + aliases { + ethernet0 = &pfe_mac0; + ethernet1 = &pfe_mac1; + }; +}; + +&pcie { + status = "okay"; }; &duart0 { @@ -38,3 +47,57 @@ &sata { status = "okay"; }; + +&pfe { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pfe_mac0: ethernet@0 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* GEM_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy>; + }; + + pfe_mac1: ethernet@1 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* GEM_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "rgmii-txid"; + phy-handle = <&rgmii_phy>; + }; + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy: ethernet-phy@2 { + reg = <0x2>; + }; + + rgmii_phy: ethernet-phy@1 { + reg = <0x1>; + }; + }; +}; + +&qspi { + status = "okay"; + + s25fs512s0: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + m25p,fast-read; + reg = <0>; + spi-rx-bus-width = <1>; + spi-tx-bus-width = <1>; + }; + +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index 337919366dc85f..df48daea83a2e3 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -3,6 +3,7 @@ * Device Tree Include file for Freescale Layerscape-1012A family SoC. * * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2019 NXP * */ @@ -22,13 +23,14 @@ rtic-c = &rtic_c; rtic-d = &rtic_d; sec-mon = &sec_mon; + rtc1 = &ftm_alarm0; }; cpus { #address-cells = <1>; #size-cells = <0>; - cpu0: cpu@0 { + cooling_map0: cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; @@ -100,36 +102,7 @@ mask = <0x02>; }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 0>; - - trips { - cpu_alert: cpu-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - }; - }; - }; + #include "fsl-tmu.dtsi" soc { compatible = "simple-bus"; @@ -260,7 +233,7 @@ dcfg: dcfg@1ee0000 { compatible = "fsl,ls1012a-dcfg", "syscon"; - reg = <0x0 0x1ee0000 0x0 0x10000>; + reg = <0x0 0x1ee0000 0x0 0x1000>; big-endian; }; @@ -317,13 +290,29 @@ #thermal-sensor-cells = <1>; }; + rcpm: rcpm@1ee2140 { + compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1+"; + reg = <0x0 0x1ee2140 0x0 0x4>; + #fsl,rcpm-wakeup-cells = <1>; + }; + + ftm_alarm0: timer@29d0000 { + compatible = "fsl,ls1012a-ftm-alarm"; + reg = <0x0 0x29d0000 0x0 0x10000>; + fsl,rcpm-wakeup = <&rcpm 0x20000>; + interrupts = <0 86 0x4>; + big-endian; + }; + + i2c0: i2c@2180000 { - compatible = "fsl,vf610-i2c"; + compatible = "fsl,vf610-i2c", "fsl,ls1012a-vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2180000 0x0 0x10000>; interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen 4 3>; + scl-gpios = <&gpio0 13 0>; status = "disabled"; }; @@ -395,14 +384,28 @@ big-endian; }; + qspi: spi@1550000 { + compatible = "fsl,ls1021a-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x1550000 0x0 0x10000>, + <0x0 0x40000000 0x0 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = ; + clock-names = "qspi_en", "qspi"; + clocks = <&clockgen 4 0>, <&clockgen 4 0>; + status = "disabled"; + }; + sai1: sai@2b50000 { #sound-dai-cells = <0>; compatible = "fsl,vf610-sai"; reg = <0x0 0x2b50000 0x0 0x10000>; interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen 4 3>, <&clockgen 4 3>, - <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + <&clockgen 4 3>, <&clockgen 4 3>, + <&clockgen 4 3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 47>, <&edma0 1 46>; @@ -415,8 +418,9 @@ reg = <0x0 0x2b60000 0x0 0x10000>; interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen 4 3>, <&clockgen 4 3>, - <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + <&clockgen 4 3>, <&clockgen 4 3>, + <&clockgen 4 3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 45>, <&edma0 1 44>; @@ -440,13 +444,15 @@ }; usb0: usb3@2f00000 { - compatible = "snps,dwc3"; + compatible = "fsl,ls1012a-dwc3", "snps,dwc3"; reg = <0x0 0x2f00000 0x0 0x10000>; interrupts = <0 60 0x4>; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; + dma-coherent; }; sata: sata@3200000 { @@ -501,6 +507,35 @@ }; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + pfe_reserved: packetbuffer@83400000 { + reg = <0 0x83400000 0 0xc00000>; + }; + }; + + pfe: pfe@4000000 { + compatible = "fsl,pfe"; + reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */ + <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */ + reg-names = "pfe", "pfe-ddr"; + fsl,pfe-num-interfaces = <0x2>; + interrupts = <0 172 0x4>, /* HIF interrupt */ + <0 173 0x4>, /*HIF_NOCPY interrupt */ + <0 174 0x4>; /* WoL interrupt */ + interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol"; + memory-region = <&pfe_reserved>; + fsl,pfe-scfg = <&scfg 0>; + fsl,rcpm-wakeup = <&rcpm 0xf0000020>; + clocks = <&clockgen 4 0>; + clock-names = "pfe"; + + status = "okay"; + }; + firmware { optee { compatible = "linaro,optee-tz"; @@ -508,3 +543,9 @@ }; }; }; + +&thermal_zones { + thermal-zone0 { + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts new file mode 100644 index 00000000000000..2755ff204e8b1f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 13bb + * + * Copyright 2019 NXP + * + * Requires a LS1028A QDS board with lane B rework. + * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C. + * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + slot1_sgmii: ethernet-phy@2 { + /* AQR112 */ + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + }; + }; + + fragment@1 { + target = <&enetc_port0>; + __overlay__ { + phy-handle = <&slot1_sgmii>; + phy-mode = "usxgmii"; + }; + }; + + fragment@2 { + target = <&mdio_slot2>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on AQR412 */ + slot2_qxgmii0: ethernet-phy@0 { + reg = <0x0>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot2_qxgmii1: ethernet-phy@1 { + reg = <0x1>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot2_qxgmii2: ethernet-phy@2 { + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot2_qxgmii3: ethernet-phy@3 { + reg = <0x3>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + }; + }; + + fragment@3 { + target = <&mscc_felix_ports>; + __overlay__ { + port@0 { + status = "okay"; + phy-handle = <&slot2_qxgmii0>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot2_qxgmii1>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot2_qxgmii2>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot2_qxgmii3>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts new file mode 100644 index 00000000000000..fb718a57b520f3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 69xx + * + * Copyright 2019 NXP + * + * Requires a LS1028A QDS board with lane B rework. + * Requires a SCH-30842 card in slot 1 and a SCH-28021 card in slot 2. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + slot1_sgmii: ethernet-phy@2 { + /* AQR112 */ + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + }; + }; + + fragment@1 { + target = <&enetc_port0>; + __overlay__ { + phy-handle = <&slot1_sgmii>; + phy-mode = "2500base-x"; + }; + }; + + fragment@2 { + target = <&mdio_slot2>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on VSC8514 */ + slot2_qsgmii0: ethernet-phy@8 { + reg = <0x8>; + }; + + slot2_qsgmii1: ethernet-phy@9 { + reg = <0x9>; + }; + + slot2_qsgmii2: ethernet-phy@a { + reg = <0xa>; + }; + + slot2_qsgmii3: ethernet-phy@b { + reg = <0xb>; + }; + }; + }; + + fragment@3 { + target = <&mscc_felix_ports>; + __overlay__ { + port@0 { + status = "okay"; + phy-handle = <&slot2_qsgmii0>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot2_qsgmii1>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot2_qsgmii2>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot2_qsgmii3>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts new file mode 100644 index 00000000000000..fa47f5466a814e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 7777 + * + * Copyright 2019 NXP + * + * Requires a LS1028A QDS board without lane B rework. + * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing + * disabled, plugged in slot 1. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on AQR412 */ + slot1_sxgmii0: ethernet-phy@0 { + reg = <0x0>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot1_sxgmii1: ethernet-phy@1 { + reg = <0x1>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot1_sxgmii2: ethernet-phy@2 { + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot1_sxgmii3: ethernet-phy@3 { + reg = <0x3>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + }; + }; + + fragment@1 { + target = <&mscc_felix_ports>; + __overlay__ { + port@0 { + status = "okay"; + phy-handle = <&slot1_sxgmii0>; + phy-mode = "2500base-x"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot1_sxgmii1>; + phy-mode = "2500base-x"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot1_sxgmii2>; + phy-mode = "2500base-x"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot1_sxgmii3>; + phy-mode = "2500base-x"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts new file mode 100644 index 00000000000000..88c415644b29f2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 85bb + * + * Copyright 2019 NXP + * + * Requires a LS1028A QDS board with lane B rework. + * Requires a SCH-24801 card in slot 1 and a SCH-28021 card in slot 2. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + slot1_sgmii: ethernet-phy@1c { + /* 1st port on VSC8234 */ + reg = <0x1c>; + }; + }; + }; + + fragment@1 { + target = <&enetc_port0>; + __overlay__ { + phy-handle = <&slot1_sgmii>; + phy-mode = "sgmii"; + }; + }; + + fragment@2 { + target = <&mdio_slot2>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on VSC8514 */ + slot2_qsgmii0: ethernet-phy@8 { + reg = <0x8>; + }; + + slot2_qsgmii1: ethernet-phy@9 { + reg = <0x9>; + }; + + slot2_qsgmii2: ethernet-phy@a { + reg = <0xa>; + }; + + slot2_qsgmii3: ethernet-phy@b { + reg = <0xb>; + }; + }; + }; + + fragment@3 { + target = <&mscc_felix_ports>; + __overlay__ { + port@0 { + status = "okay"; + phy-handle = <&slot2_qsgmii0>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot2_qsgmii1>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot2_qsgmii2>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot2_qsgmii3>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts new file mode 100644 index 00000000000000..578e913c4bfe9d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 85xx + * + * Copyright 2019 NXP + * + * Requires a LS1028A QDS board without lane B rework. + * Requires a SCH-24801 card in slot 1. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* VSC8234 */ + slot1_sgmii0: ethernet-phy@1c { + reg = <0x1c>; + }; + + slot1_sgmii1: ethernet-phy@1d { + reg = <0x1d>; + }; + + slot1_sgmii2: ethernet-phy@1e { + reg = <0x1e>; + }; + + slot1_sgmii3: ethernet-phy@1f { + reg = <0x1f>; + }; + }; + }; + + fragment@1 { + target = <&enetc_port0>; + __overlay__ { + phy-handle = <&slot1_sgmii0>; + phy-mode = "sgmii"; + }; + }; + + fragment@2 { + target = <&mscc_felix_ports>; + __overlay__ { + port@1 { + status = "okay"; + phy-handle = <&slot1_sgmii1>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot1_sgmii2>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts new file mode 100644 index 00000000000000..5c8b3c6b43ab30 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 85xx + * + * Copyright 2019 NXP + * + * Requires a LS1028A QDS board without lane B rework. + * Requires a SCH-24801 card in slot 1. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* VSC8234 */ + slot1_sgmii0: ethernet-phy@1c { + reg = <0x1c>; + }; + + slot1_sgmii1: ethernet-phy@1d { + reg = <0x1d>; + }; + + slot1_sgmii2: ethernet-phy@1e { + reg = <0x1e>; + }; + + slot1_sgmii3: ethernet-phy@1f { + reg = <0x1f>; + }; + }; + }; + fragment@1 { + target = <&mscc_felix_ports>; + __overlay__ { + port@0 { + status = "okay"; + phy-handle = <&slot1_sgmii0>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot1_sgmii1>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot1_sgmii2>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot1_sgmii3>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts index 078a5010228cd7..c893dcc16c51cb 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts @@ -2,7 +2,7 @@ /* * Device Tree file for NXP LS1028A QDS Board. * - * Copyright 2018 NXP + * Copyright 2018-2019 NXP * * Harninder Rai * @@ -104,9 +104,41 @@ reg = <5>; }; }; + + mdio_slot1: mdio@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + mdio_slot2: mdio@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + mdio_slot3: mdio@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + mdio_slot4: mdio@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; }; }; +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + &duart0 { status = "okay"; }; @@ -161,11 +193,6 @@ vcc-supply = <&sb_3v3>; }; - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; - }; - eeprom@56 { compatible = "atmel,24c512"; reg = <0x56>; @@ -209,11 +236,34 @@ }; +&i2c1 { + status = "okay"; + rtc@51 { + compatible = "nxp,pcf2129"; + reg = <0x51>; + }; +}; + &enetc_port1 { phy-handle = <&qds_phy1>; phy-connection-type = "rgmii-id"; }; +&fspi { + status = "okay"; + mt35xu02g: flash@0 { + compatible = "spansion,m25p80"; + #address-cells = <1>; + #size-cells = <1>; + m25p,fast-read; + spi-max-frequency = <20000000>; + reg = <0>; + /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */ + spi-rx-bus-width = <8>; /* 8 SPI Rx lines */ + spi-tx-bus-width = <1>; /* 1 SPI Tx line */ + }; +}; + &sai1 { status = "okay"; }; @@ -221,3 +271,8 @@ &sata { status = "okay"; }; + +&hdptx0 { + lane-mapping = <0x4e>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb-dpdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb-dpdk.dts new file mode 100644 index 00000000000000..4767d0dd0a77a6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb-dpdk.dts @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * NXP LS1028A RDB Board device tree file for DPDK + * + * Copyright 2018-2020 NXP + */ + +/dts-v1/; +#include "fsl-ls1028a-rdb.dts" + +&enetc_port0 { + status = "okay"; + /delete-property/ phy-handle; + /delete-property/ phy-connection-type; + /delete-node/ mdio; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +/delete-node/ &enetc_mdio_pf3; + +/* l2switch ports */ +&mscc_felix_ports { + port@0 { + status = "okay"; + phy-mode = "qsgmii"; + /delete-property/ managed; + /delete-property/ phy-handle; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + status = "okay"; + phy-mode = "qsgmii"; + /delete-property/ managed; + /delete-property/ phy-handle; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@2 { + status = "okay"; + phy-mode = "qsgmii"; + /delete-property/ managed; + /delete-property/ phy-handle; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@3 { + status = "okay"; + phy-mode = "qsgmii"; + /delete-property/ managed; + /delete-property/ phy-handle; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@5 { + status = "okay"; + /delete-property/ managed; + /delete-property/ phy-handle; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; +}; + +&enetc_port3 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index 1a69221d9a1b0d..d4e6ef40a14963 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -2,7 +2,7 @@ /* * Device Tree file for NXP LS1028A RDB Board. * - * Copyright 2018 NXP + * Copyright 2018-2019 NXP * * Harninder Rai * @@ -93,9 +93,15 @@ &esdhc1 { mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; status = "okay"; }; +&usb1 { + dr_mode = "otg"; +}; + &i2c0 { status = "okay"; @@ -152,6 +158,37 @@ }; }; +&can0 { + status = "okay"; + + can-transceiver { + max-bitrate = <5000000>; + }; +}; + +&can1 { + status = "okay"; + + can-transceiver { + max-bitrate = <5000000>; + }; +}; + +&fspi { + status = "okay"; + mt35xu02g: flash@0 { + compatible = "spansion,m25p80"; + #address-cells = <1>; + #size-cells = <1>; + m25p,fast-read; + spi-max-frequency = <20000000>; + reg = <0>; + /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */ + spi-rx-bus-width = <8>; /* 8 SPI Rx lines */ + spi-tx-bus-width = <1>; /* 1 SPI Tx line */ + }; +}; + &duart0 { status = "okay"; }; @@ -177,6 +214,55 @@ status = "disabled"; }; +&enetc_mdio_pf3 { + qsgmii_phy1: ethernet-phy@10 { + reg = <0x10>; + }; + + qsgmii_phy2: ethernet-phy@11 { + reg = <0x11>; + }; + + qsgmii_phy3: ethernet-phy@12 { + reg = <0x12>; + }; + + qsgmii_phy4: ethernet-phy@13 { + reg = <0x13>; + }; +}; + +/* l2switch ports */ +&mscc_felix_ports { + port@0 { + status = "okay"; + phy-handle = <&qsgmii_phy1>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&qsgmii_phy2>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&qsgmii_phy3>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&qsgmii_phy4>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; +}; + &sai4 { status = "okay"; }; @@ -184,3 +270,8 @@ &sata { status = "okay"; }; + +&hdptx0 { + lane-mapping = <0x4e>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 9589b15693d6e9..2c7ea5867e5104 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Include file for NXP Layerscape-1028A family SoC. * - * Copyright 2018 NXP + * Copyright 2018-2019 NXP * * Harninder Rai * @@ -17,6 +17,10 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + rtc1 = &ftm_alarm0; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -82,22 +86,8 @@ dpclk: clock-controller@f1f0000 { compatible = "fsl,ls1028a-plldig"; reg = <0x0 0xf1f0000 0x0 0xffff>; - #clock-cells = <1>; - clocks = <&osc_27m>; - }; - - aclk: clock-axi { - compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <650000000>; - clock-output-names= "aclk"; - }; - - pclk: clock-apb { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <650000000>; - clock-output-names= "pclk"; + clocks = <&osc_27m>; }; reboot { @@ -180,6 +170,18 @@ clocks = <&sysclk>; }; + fspi: spi@20c0000 { + compatible = "nxp,lx2160a-fspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20c0000 0x0 0x10000>, + <0x0 0x20000000 0x0 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = <0 25 0x4>; /* Level high type */ + clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clock-names = "fspi_en", "fspi"; + }; + i2c0: i2c@2000000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; @@ -287,6 +289,26 @@ status = "disabled"; }; + can0: can@2180000 { + compatible = "fsl,ls1028ar1-flexcan", + "fsl,lx2160ar1-flexcan"; + reg = <0x0 0x2180000 0x0 0x10000>; + interrupts = ; + clocks = <&sysclk>, <&clockgen 4 1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can1: can@2190000 { + compatible = "fsl,ls1028ar1-flexcan", + "fsl,lx2160ar1-flexcan"; + reg = <0x0 0x2190000 0x0 0x10000>; + interrupts = ; + clocks = <&sysclk>, <&clockgen 4 1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + duart0: serial@21c0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x00 0x21c0500 0x0 0x100>; @@ -305,7 +327,7 @@ edma0: dma-controller@22c0000 { #dma-cells = <2>; - compatible = "fsl,vf610-edma"; + compatible = "fsl,ls1028a-edma"; reg = <0x0 0x22c0000 0x0 0x10000>, <0x0 0x22d0000 0x0 0x10000>, <0x0 0x22e0000 0x0 0x10000>; @@ -359,6 +381,7 @@ snps,dis_rxdet_inp3_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + dma-coherent; }; usb1: usb@3110000 { @@ -369,6 +392,7 @@ snps,dis_rxdet_inp3_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + dma-coherent; }; sata: sata@3200000 { @@ -506,14 +530,25 @@ clock-names = "apb_pclk", "wdog_clk"; }; + gpu@f0c0000 { + compatible = "fsl,ls1028a-gpu"; + reg = <0x0 0x0f0c0000 0x0 0x10000>, + <0x0 0x80000000 0x0 0x80000000>, + <0x0 0x0 0x0 0x3000000>; + reg-names = "base", "phys_baseaddr", + "contiguous_mem"; + interrupts = ; + }; + sai1: audio-controller@f100000 { #sound-dai-cells = <0>; compatible = "fsl,vf610-sai"; reg = <0x0 0xf100000 0x0 0x10000>; interrupts = ; clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 4>, <&edma0 1 3>; @@ -526,8 +561,9 @@ reg = <0x0 0xf110000 0x0 0x10000>; interrupts = ; clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 6>, <&edma0 1 5>; @@ -540,8 +576,9 @@ reg = <0x0 0xf130000 0x0 0x10000>; interrupts = ; clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 10>, <&edma0 1 9>; @@ -631,12 +668,63 @@ }; }; + pcie@3400000 { + compatible = "fsl,ls1028a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = , /* PME interrupt */ + ; /* aer interrupt */ + interrupt-names = "pme", "aer"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie@3500000 { + compatible = "fsl,ls1028a-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ + 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = , + ; + interrupt-names = "pme", "aer"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + pcie@1f0000000 { /* Integrated Endpoint Root Complex */ compatible = "pci-host-ecam-generic"; reg = <0x01 0xf0000000 0x0 0x100000>; #address-cells = <3>; #size-cells = <2>; - #interrupt-cells = <1>; msi-parent = <&its>; device_type = "pci"; bus-range = <0x0 0x0>; @@ -654,7 +742,9 @@ /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 /* PF1: VF0-1 BAR2 - prefetchable memory */ - 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>; + 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000 + /* BAR4 (PF5) - non-prefetchable memory */ + 0x82000000 0x0 0x00000000 0x1 0xfc000000 0x0 0x400000>; enetc_port0: ethernet@0,0 { compatible = "fsl,enetc"; @@ -670,12 +760,111 @@ #address-cells = <1>; #size-cells = <0>; }; + enetc_port2: ethernet@0,2 { + compatible = "fsl,enetc"; + reg = <0x000200 0 0 0 0>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; ethernet@0,4 { compatible = "fsl,enetc-ptp"; reg = <0x000400 0 0 0 0>; clocks = <&clockgen 4 0>; little-endian; }; + + ethernet-switch@0,5 { + reg = <0x000500 0 0 0 0>; + /* IEP INT_B */ + interrupts = ; + + mscc_felix_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* external ports */ + mscc_felix_port0: port@0 { + reg = <0>; + status = "disabled"; + label = "swp0"; + }; + + mscc_felix_port1: port@1 { + reg = <1>; + status = "disabled"; + label = "swp1"; + }; + + mscc_felix_port2: port@2 { + reg = <2>; + status = "disabled"; + label = "swp2"; + }; + + mscc_felix_port3: port@3 { + reg = <3>; + status = "disabled"; + label = "swp3"; + }; + + /* internal to-cpu ports */ + mscc_felix_port4: port@4 { + reg = <4>; + ethernet = <&enetc_port2>; + phy-mode = "gmii"; + + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + mscc_felix_port5: port@5 { + reg = <5>; + phy-mode = "gmii"; + status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + enetc_port3: ethernet@0,6 { + compatible = "fsl,enetc"; + reg = <0x000600 0 0 0 0>; + status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + rcpm: rcpm@1e34040 { + compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; + reg = <0x0 0x1e34040 0x0 0x1c>; + #fsl,rcpm-wakeup-cells = <7>; + little-endian; + }; + + ftm_alarm0: timer@2800000 { + compatible = "fsl,ls1028a-ftm-alarm"; + reg = <0x0 0x2800000 0x0 0x10000>; + fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; + interrupts = ; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; }; }; @@ -685,14 +874,31 @@ interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, <0 223 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "DE", "SE"; - clocks = <&dpclk 0>, <&aclk>, <&aclk>, <&pclk>; + clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>, + <&clockgen 2 2>; clock-names = "pxlclk", "mclk", "aclk", "pclk"; arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; arm,malidp-arqos-value = <0xd000d000>; port { dp0_out: endpoint { + remote-endpoint = <&dp1_out>; + }; + }; + }; + hdptx0: display@f200000 { + compatible = "cdn,ls1028a-dp"; + reg = <0x0 0xf200000 0x0 0xfffff>; + interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen 2 2>, <&clockgen 2 2>, <&clockgen 2 2>, + <&clockgen 2 2>, <&clockgen 2 2>, <&dpclk>; + clock-names = "clk_core", "pclk", "sclk", + "cclk", "clk_vif", "clk_pxl"; + + port { + dp1_out: endpoint { + remote-endpoint = <&dp0_out>; }; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts new file mode 100644 index 00000000000000..43bafb51515eb2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts @@ -0,0 +1,263 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * + * Mingkai Hu + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "fsl-ls1043a-qds.dts" +#include "qoriq-qman-portals-sdk.dtsi" +#include "qoriq-bman-portals-sdk.dtsi" + +&bman_fbpr { + compatible = "fsl,bman-fbpr"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&soc { +/delete-property/ dma-coherent; + +#include "qoriq-dpaa-eth.dtsi" +#include "qoriq-fman3-0-6oh.dtsi" + +pcie@3400000 { + /delete-property/ iommu-map; + dma-coherent; +}; + +pcie@3500000 { + /delete-property/ iommu-map; + dma-coherent; +}; + +pcie@3600000 { + /delete-property/ iommu-map; + dma-coherent; +}; + +/delete-node/ iommu@9000000; +}; + +&fman0 { + compatible = "fsl,fman", "simple-bus"; + dma-coherent; +}; + +&clockgen { + dma-coherent; +}; + +&scfg { + dma-coherent; +}; + +&crypto { + dma-coherent; +}; + +&dcfg { + dma-coherent; +}; + +&ifc { + dma-coherent; +}; + +&qspi { + dma-coherent; +}; + +&esdhc { + dma-coherent; +}; + +&ddr { + dma-coherent; +}; + +&tmu { + dma-coherent; +}; + +&qman { + dma-coherent; +}; + +&bman { + dma-coherent; +}; + +&bportals { + dma-coherent; +}; + +&qportals { + dma-coherent; +}; + +&dspi0 { + dma-coherent; +}; + +&dspi1 { + dma-coherent; +}; + +&i2c0 { + dma-coherent; +}; + +&i2c1 { + dma-coherent; +}; + +&i2c2 { + dma-coherent; +}; + +&i2c3 { + dma-coherent; +}; + +&duart0 { + dma-coherent; +}; + +&duart1 { + dma-coherent; +}; + +&duart2 { + dma-coherent; +}; + +&duart3 { + dma-coherent; +}; + +&gpio1 { + dma-coherent; +}; + +&gpio2 { + dma-coherent; +}; + +&gpio3 { + dma-coherent; +}; + +&gpio4 { + dma-coherent; +}; + +&uqe { + dma-coherent; +}; + +&lpuart0 { + dma-coherent; +}; + +&lpuart1 { + dma-coherent; +}; + +&lpuart2 { + dma-coherent; +}; + +&lpuart3 { + dma-coherent; +}; + +&lpuart4 { + dma-coherent; +}; + +&lpuart5 { + dma-coherent; +}; + +&ftm_alarm0 { + dma-coherent; +}; + +&wdog0 { + dma-coherent; +}; + +&edma0 { + dma-coherent; +}; + +&qdma { + dma-coherent; +}; + +&msi1 { + dma-coherent; +}; + +&msi2 { + dma-coherent; +}; + +&msi3 { + dma-coherent; +}; + +&ptp_timer0 { + dma-coherent; +}; + +&fsldpaa { + dma-coherent; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts index 1aac81da7e37f6..219a987800fbc0 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts @@ -3,7 +3,7 @@ * Device Tree Include file for Freescale Layerscape-1043A family SoC. * * Copyright 2014-2015 Freescale Semiconductor, Inc. - * Copyright 2018 NXP + * Copyright 2018-2019 NXP * * Mingkai Hu */ @@ -24,6 +24,22 @@ serial1 = &duart1; serial2 = &duart2; serial3 = &duart3; + sgmii-riser-s1-p1 = &sgmii_phy_s1_p1; + sgmii-riser-s2-p1 = &sgmii_phy_s2_p1; + sgmii-riser-s3-p1 = &sgmii_phy_s3_p1; + sgmii-riser-s4-p1 = &sgmii_phy_s4_p1; + qsgmii-s1-p1 = &qsgmii_phy_s1_p1; + qsgmii-s1-p2 = &qsgmii_phy_s1_p2; + qsgmii-s1-p3 = &qsgmii_phy_s1_p3; + qsgmii-s1-p4 = &qsgmii_phy_s1_p4; + qsgmii-s2-p1 = &qsgmii_phy_s2_p1; + qsgmii-s2-p2 = &qsgmii_phy_s2_p2; + qsgmii-s2-p3 = &qsgmii_phy_s2_p3; + qsgmii-s2-p4 = &qsgmii_phy_s2_p4; + emi1-slot1 = &ls1043mdio_s1; + emi1-slot2 = &ls1043mdio_s2; + emi1-slot3 = &ls1043mdio_s3; + emi1-slot4 = &ls1043mdio_s4; }; chosen { @@ -62,8 +78,11 @@ }; fpga: board-control@2,0 { - compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis"; + compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis", "simple-bus"; reg = <0x2 0x0 0x0000100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 2 0 0x100>; }; }; @@ -149,3 +168,147 @@ }; #include "fsl-ls1043-post.dtsi" + +&fman0 { + ethernet@e0000 { + phy-handle = <&qsgmii_phy_s2_p1>; + phy-connection-type = "sgmii"; + }; + + ethernet@e2000 { + phy-handle = <&qsgmii_phy_s2_p2>; + phy-connection-type = "sgmii"; + }; + + ethernet@e4000 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii"; + }; + + ethernet@e6000 { + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii"; + }; + + ethernet@e8000 { + phy-handle = <&qsgmii_phy_s2_p3>; + phy-connection-type = "sgmii"; + }; + + ethernet@ea000 { + phy-handle = <&qsgmii_phy_s2_p4>; + phy-connection-type = "sgmii"; + }; + + ethernet@f0000 { /* DTSEC9/10GEC1 */ + fixed-link = <1 1 10000 0 0>; + phy-connection-type = "xgmii"; + }; +}; + +&fpga { + mdio-mux-emi1 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + mdio-parent-bus = <&mdio0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x54 1>; /* BRDCFG4 */ + mux-mask = <0xe0>; /* EMI1 */ + + /* On-board RGMII1 PHY */ + ls1043mdio0: mdio@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + rgmii_phy1: ethernet-phy@1 { /* MAC3 */ + reg = <0x1>; + }; + }; + + /* On-board RGMII2 PHY */ + ls1043mdio1: mdio@1 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + rgmii_phy2: ethernet-phy@2 { /* MAC4 */ + reg = <0x2>; + }; + }; + + /* Slot 1 */ + ls1043mdio_s1: mdio@2 { + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + qsgmii_phy_s1_p1: ethernet-phy@4 { + reg = <0x4>; + }; + qsgmii_phy_s1_p2: ethernet-phy@5 { + reg = <0x5>; + }; + qsgmii_phy_s1_p3: ethernet-phy@6 { + reg = <0x6>; + }; + qsgmii_phy_s1_p4: ethernet-phy@7 { + reg = <0x7>; + }; + + sgmii_phy_s1_p1: ethernet-phy@1c { + reg = <0x1c>; + }; + }; + + /* Slot 2 */ + ls1043mdio_s2: mdio@3 { + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + qsgmii_phy_s2_p1: ethernet-phy@8 { + reg = <0x8>; + }; + qsgmii_phy_s2_p2: ethernet-phy@9 { + reg = <0x9>; + }; + qsgmii_phy_s2_p3: ethernet-phy@a { + reg = <0xa>; + }; + qsgmii_phy_s2_p4: ethernet-phy@b { + reg = <0xb>; + }; + + sgmii_phy_s2_p1: ethernet-phy@1c { + reg = <0x1c>; + }; + }; + + /* Slot 3 */ + ls1043mdio_s3: mdio@4 { + reg = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sgmii_phy_s3_p1: ethernet-phy@1c { + reg = <0x1c>; + }; + }; + + /* Slot 4 */ + ls1043mdio_s4: mdio@5 { + reg = <0xa0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sgmii_phy_s4_p1: ethernet-phy@1c { + reg = <0x1c>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts new file mode 100644 index 00000000000000..210bc9f25c47bb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts @@ -0,0 +1,262 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * + * Mingkai Hu + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "fsl-ls1043a-rdb.dts" +#include "qoriq-qman-portals-sdk.dtsi" +#include "qoriq-bman-portals-sdk.dtsi" + +&bman_fbpr { + compatible = "fsl,bman-fbpr"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&soc { +/delete-property/ dma-coherent; + +#include "qoriq-dpaa-eth.dtsi" +#include "qoriq-fman3-0-6oh.dtsi" + +pcie@3400000 { + /delete-property/ iommu-map; + dma-coherent; +}; + +pcie@3500000 { + /delete-property/ iommu-map; + dma-coherent; +}; + +pcie@3600000 { + /delete-property/ iommu-map; + dma-coherent; +}; + +/delete-node/ iommu@9000000; +}; + +&fman0 { + compatible = "fsl,fman", "simple-bus"; +}; + +&clockgen { + dma-coherent; +}; + +&scfg { + dma-coherent; +}; + +&crypto { + dma-coherent; +}; + +&dcfg { + dma-coherent; +}; + +&ifc { + dma-coherent; +}; + +&qspi { + dma-coherent; +}; + +&esdhc { + dma-coherent; +}; + +&ddr { + dma-coherent; +}; + +&tmu { + dma-coherent; +}; + +&qman { + dma-coherent; +}; + +&bman { + dma-coherent; +}; + +&bportals { + dma-coherent; +}; + +&qportals { + dma-coherent; +}; + +&dspi0 { + dma-coherent; +}; + +&dspi1 { + dma-coherent; +}; + +&i2c0 { + dma-coherent; +}; + +&i2c1 { + dma-coherent; +}; + +&i2c2 { + dma-coherent; +}; + +&i2c3 { + dma-coherent; +}; + +&duart0 { + dma-coherent; +}; + +&duart1 { + dma-coherent; +}; + +&duart2 { + dma-coherent; +}; + +&duart3 { + dma-coherent; +}; + +&gpio1 { + dma-coherent; +}; + +&gpio2 { + dma-coherent; +}; + +&gpio3 { + dma-coherent; +}; + +&gpio4 { + dma-coherent; +}; + +&lpuart0 { + dma-coherent; +}; + +&lpuart1 { + dma-coherent; +}; + +&lpuart2 { + dma-coherent; +}; + +&lpuart3 { + dma-coherent; +}; + +&lpuart4 { + dma-coherent; +}; + +&lpuart5 { + dma-coherent; +}; + +&ftm_alarm0 { + dma-coherent; +}; + +&wdog0 { + dma-coherent; +}; + +&edma0 { + dma-coherent; +}; + +&qdma { + dma-coherent; +}; + +&msi1 { + dma-coherent; +}; + +&msi2 { + dma-coherent; +}; + +&msi3 { + dma-coherent; +}; + +&fman0 { + dma-coherent; +}; + +&ptp_timer0 { + dma-coherent; +}; + +&fsldpaa { + dma-coherent; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts new file mode 100644 index 00000000000000..7beb9985add260 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts @@ -0,0 +1,140 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * + * Copyright (C) 2014-2015, Freescale Semiconductor + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include "fsl-ls1043a-rdb-sdk.dts" + +&soc { + bp7: buffer-pool@7 { + compatible = "fsl,p4080-bpool", "fsl,bpool"; + fsl,bpid = <7>; + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>; + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>; + dma-coherent; + }; + + bp8: buffer-pool@8 { + compatible = "fsl,p4080-bpool", "fsl,bpool"; + fsl,bpid = <8>; + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>; + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; + dma-coherent; + }; + + bp9: buffer-pool@9 { + compatible = "fsl,p4080-bpool", "fsl,bpool"; + fsl,bpid = <9>; + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>; + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; + dma-coherent; + }; + + fsl,dpaa { + compatible = "fsl,ls1043a", "fsl,dpaa", "simple-bus"; + dma-coherent; + + ethernet@0 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x50 1 0x51 1>; + fsl,qman-frame-queues-tx = <0x70 1 0x71 1>; + }; + + ethernet@1 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x52 1 0x53 1>; + fsl,qman-frame-queues-tx = <0x72 1 0x73 1>; + }; + + ethernet@2 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>; + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>; + }; + + ethernet@3 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>; + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>; + }; + + ethernet@4 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x58 1 0x59 1>; + fsl,qman-frame-queues-tx = <0x78 1 0x79 1>; + }; + + ethernet@5 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x60 1 0x61 1>; + fsl,qman-frame-queues-tx = <0x80 1 0x81 1>; + }; + + ethernet@8 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>; + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>; + + }; + dpa-fman0-oh@2 { + compatible = "fsl,dpa-oh"; + /* Define frame queues for the OH port*/ + /* */ + fsl,qman-frame-queues-oh = <0x5a 1 0x5b 1>; + fsl,fman-oh-port = <&fman0_oh2>; + }; + }; + + pcie@3400000 { + /delete-property/ iommu-map; + }; + + pcie@3500000 { + /delete-property/ iommu-map; + }; + + pcie@3600000 { + /delete-property/ iommu-map; + }; + + /delete-node/ iommu@9000000; +}; +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* For legacy usdpaa based use-cases, update the size and + alignment parameters. e.g. to allocate 256 MB memory: + size = <0 0x10000000>; + alignment = <0 0x10000000>; + */ + usdpaa_mem: usdpaa_mem { + compatible = "fsl,usdpaa-mem"; + alloc-ranges = <0 0 0x10000 0>; + size = <0 0x1000>; + alignment = <0 0x1000>; + }; + }; +}; + +&fman0 { + fman0_oh2: port@83000 { + cell-index = <1>; + compatible = "fsl,fman-port-oh"; + reg = <0x83000 0x1000>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts index dde50c88f5e35c..06d12ba8ac0f35 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts @@ -49,6 +49,10 @@ compatible = "pericom,pt7c4338"; reg = <0x68>; }; + rtc@51 { + compatible = "nxp,pcf85263"; + reg = <0x51>; + }; }; &ifc { @@ -94,6 +98,38 @@ reg = <0>; spi-max-frequency = <1000000>; /* input clock */ }; + + slic@2 { + compatible = "maxim,ds26522"; + reg = <2>; + spi-max-frequency = <2000000>; + fsl,spi-cs-sck-delay = <100>; + fsl,spi-sck-cs-delay = <50>; + }; + + slic@3 { + compatible = "maxim,ds26522"; + reg = <3>; + spi-max-frequency = <2000000>; + fsl,spi-cs-sck-delay = <100>; + fsl,spi-sck-cs-delay = <50>; + }; +}; + +&uqe { + ucc_hdlc: ucc@2000 { + compatible = "fsl,ucc-hdlc"; + rx-clock-name = "clk8"; + tx-clock-name = "clk9"; + fsl,rx-sync-clock = "rsync_pin"; + fsl,tx-sync-clock = "tsync_pin"; + fsl,tx-timeslot-mask = <0xfffffffe>; + fsl,rx-timeslot-mask = <0xfffffffe>; + fsl,tdm-framer-type = "e1"; + fsl,tdm-id = <0>; + fsl,siram-entry-id = <0>; + fsl,tdm-interface; + }; }; &duart0 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index c084c7a4b6a6f7..e19e05ddae0835 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -27,6 +27,7 @@ ethernet4 = &enet4; ethernet5 = &enet5; ethernet6 = &enet6; + rtc1 = &ftm_alarm0; }; cpus { @@ -39,7 +40,7 @@ * * Currently supported enable-method is psci v0.2 */ - cpu0: cpu@0 { + cooling_map0: cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; @@ -148,38 +149,7 @@ mask = <0x02>; }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <5000>; - - thermal-sensors = <&tmu 3>; - - trips { - cpu_alert: cpu-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit: cpu-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; + #include "fsl-tmu.dtsi" timer { compatible = "arm,armv8-timer"; @@ -218,6 +188,8 @@ #address-cells = <2>; #size-cells = <2>; ranges; + dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; + dma-coherent; clockgen: clocking@1ee1000 { compatible = "fsl,ls1043a-clockgen"; @@ -226,6 +198,49 @@ clocks = <&sysclk>; }; + smmu: iommu@9000000 { + compatible = "arm,mmu-500"; + reg = <0 0x9000000 0 0x400000>; + dma-coherent; + stream-match-mask = <0x7f00>; + #global-interrupts = <2>; + #iommu-cells = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + scfg: scfg@1570000 { compatible = "fsl,ls1043a-scfg", "syscon"; reg = <0x0 0x1570000 0x0 0x10000>; @@ -277,7 +292,7 @@ dcfg: dcfg@1ee0000 { compatible = "fsl,ls1043a-dcfg", "syscon"; - reg = <0x0 0x1ee0000 0x0 0x10000>; + reg = <0x0 0x1ee0000 0x0 0x1000>; big-endian; }; @@ -411,7 +426,7 @@ }; i2c0: i2c@2180000 { - compatible = "fsl,vf610-i2c"; + compatible = "fsl,vf610-i2c", "fsl,ls1043a-vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2180000 0x0 0x10000>; @@ -421,6 +436,7 @@ dmas = <&edma0 1 39>, <&edma0 1 38>; dma-names = "tx", "rx"; + scl-gpios = <&gpio4 12 0>; status = "disabled"; }; @@ -525,6 +541,72 @@ #interrupt-cells = <2>; }; + uqe: uqe@2400000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "qe"; + compatible = "fsl,qe", "simple-bus"; + ranges = <0x0 0x0 0x2400000 0x40000>; + reg = <0x0 0x2400000 0x0 0x480>; + brg-frequency = <100000000>; + bus-frequency = <200000000>; + + fsl,qe-num-riscs = <1>; + fsl,qe-num-snums = <28>; + + qeic: qeic@80 { + compatible = "fsl,qe-ic"; + reg = <0x80 0x80>; + #address-cells = <0>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = <0 77 0x04 0 77 0x04>; + }; + + si1: si@700 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,ls1043-qe-si", + "fsl,t1040-qe-si"; + reg = <0x700 0x80>; + }; + + siram1: siram@1000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,ls1043-qe-siram", + "fsl,t1040-qe-siram"; + reg = <0x1000 0x800>; + }; + + ucc@2000 { + cell-index = <1>; + reg = <0x2000 0x200>; + interrupts = <32>; + interrupt-parent = <&qeic>; + }; + + ucc@2200 { + cell-index = <3>; + reg = <0x2200 0x200>; + interrupts = <34>; + interrupt-parent = <&qeic>; + }; + + muram@10000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0x0 0x10000 0x6000>; + + data-only@0 { + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0x0 0x6000>; + }; + }; + }; + lpuart0: serial@2950000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2950000 0x0 0x1000>; @@ -604,44 +686,66 @@ <&clockgen 4 0>; }; - usb0: usb3@2f00000 { - compatible = "snps,dwc3"; - reg = <0x0 0x2f00000 0x0 0x10000>; - interrupts = <0 60 0x4>; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - usb1: usb3@3000000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3000000 0x0 0x10000>; - interrupts = <0 61 0x4>; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - usb2: usb3@3100000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = <0 63 0x4>; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - sata: sata@3200000 { - compatible = "fsl,ls1043a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>, - <0x0 0x20140520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = <0 69 0x4>; - clocks = <&clockgen 4 0>; - dma-coherent; + aux_bus: aux_bus { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>; + + usb0: usb3@2f00000 { + compatible = "fsl,ls1043a-dwc3", "snps,dwc3"; + reg = <0x0 0x2f00000 0x0 0x10000>; + interrupts = <0 60 0x4>; + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + usb3-lpm-capable; + snps,dis-u1u2-when-u3-quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; + configure-gfladj; + dma-coherent; + }; + + usb1: usb3@3000000 { + compatible = "fsl,ls1043a-dwc3", "snps,dwc3"; + reg = <0x0 0x3000000 0x0 0x10000>; + interrupts = <0 61 0x4>; + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + usb3-lpm-capable; + snps,dis-u1u2-when-u3-quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; + configure-gfladj; + dma-coherent; + }; + + usb2: usb3@3100000 { + compatible = "fsl,ls1043a-dwc3", "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 63 0x4>; + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + usb3-lpm-capable; + snps,dis-u1u2-when-u3-quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; + configure-gfladj; + dma-coherent; + }; + + sata: sata@3200000 { + compatible = "fsl,ls1043a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>, + <0x0 0x20140520 0x0 0x4>; + reg-names = "ahci", "sata-ecc"; + interrupts = <0 69 0x4>; + clocks = <&clockgen 4 0>; + }; }; msi1: msi-controller1@1571000 { @@ -670,13 +774,13 @@ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 118 0x4>, /* controller interrupt */ - <0 117 0x4>; /* PME interrupt */ - interrupt-names = "intr", "pme"; + interrupts = <0 117 0x4>, /* PME interrupt */ + <0 118 0x4>; /* aer interrupt */ + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - dma-coherent; + iommu-map = <0 &smmu 0 1>; /* update by bootloader */ num-viewport = <6>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -696,13 +800,13 @@ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 128 0x4>, - <0 127 0x4>; - interrupt-names = "intr", "pme"; + interrupts = <0 127 0x4>, + <0 128 0x4>; + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - dma-coherent; + iommu-map = <0 &smmu 0 1>; /* update by bootloader */ num-viewport = <6>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -722,13 +826,13 @@ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 162 0x4>, - <0 161 0x4>; - interrupt-names = "intr", "pme"; + interrupts = <0 161 0x4>, + <0 162 0x4>; + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - dma-coherent; + iommu-map = <0 &smmu 0 1>; /* update by bootloader */ num-viewport = <6>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -764,6 +868,19 @@ big-endian; }; + rcpm: rcpm@1ee2140 { + compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+"; + reg = <0x0 0x1ee2140 0x0 0x4>; + #fsl,rcpm-wakeup-cells = <1>; + }; + + ftm_alarm0: timer@29d0000 { + compatible = "fsl,ls1043a-ftm-alarm"; + reg = <0x0 0x29d0000 0x0 0x10000>; + fsl,rcpm-wakeup = <&rcpm 0x20000>; + interrupts = <0 86 0x4>; + big-endian; + }; }; firmware { @@ -777,3 +894,29 @@ #include "qoriq-qman-portals.dtsi" #include "qoriq-bman-portals.dtsi" + +&thermal_zones { + thermal-zone0 { + status = "okay"; + }; + + thermal-zone1 { + status = "okay"; + }; + + thermal-zone2 { + status = "okay"; + }; + + thermal-zone3 { + status = "okay"; + }; + + thermal-zone4 { + status = "okay"; + }; + + thermal-zone5 { + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts new file mode 100644 index 00000000000000..8c0e8aaddc2fd9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Freescale Layerscape-1046A family SoC. + * + * Copyright 2019 NXP. + * + */ + +#include "fsl-ls1046a-frwy.dts" +#include "qoriq-qman-portals-sdk.dtsi" +#include "qoriq-bman-portals-sdk.dtsi" + +&bman_fbpr { + compatible = "fsl,bman-fbpr"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&soc { +/delete-property/ dma-coherent; + +#include "qoriq-dpaa-eth.dtsi" +#include "qoriq-fman3-0-6oh.dtsi" + + pcie@3400000 { + /delete-property/ iommu-map; + }; + + pcie@3500000 { + /delete-property/ iommu-map; + }; + + pcie@3600000 { + /delete-property/ iommu-map; + }; + + /delete-node/ iommu@9000000; +}; + +&fsldpaa { + ethernet@1 { + status = "disabled"; + }; + ethernet@2 { + status = "disabled"; + }; + ethernet@3 { + status = "disabled"; + }; + ethernet@6 { + status = "disabled"; + }; + ethernet@9 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet7>; + dma-coherent; + }; +}; + +&fman0 { + compatible = "fsl,fman", "simple-bus"; +}; + +&clockgen { + dma-coherent; +}; + +&scfg { + dma-coherent; +}; + +&crypto { + dma-coherent; +}; + +&dcfg { + dma-coherent; +}; + +&ifc { + dma-coherent; +}; + +&qspi { + dma-coherent; +}; + +&esdhc { + dma-coherent; +}; + +&ddr { + dma-coherent; +}; + +&tmu { + dma-coherent; +}; + +&qman { + dma-coherent; +}; + +&bman { + dma-coherent; +}; + +&bportals { + dma-coherent; +}; + +&qportals { + dma-coherent; +}; + +&dspi { + dma-coherent; +}; + +&i2c0 { + dma-coherent; +}; + +&i2c1 { + dma-coherent; +}; + +&i2c2 { + dma-coherent; +}; + +&i2c3 { + dma-coherent; +}; + +&duart0 { + dma-coherent; +}; + +&duart1 { + dma-coherent; +}; + +&duart2 { + dma-coherent; +}; + +&duart3 { + dma-coherent; +}; + +&gpio0 { + dma-coherent; +}; + +&gpio1 { + dma-coherent; +}; + +&gpio2 { + dma-coherent; +}; + +&gpio3 { + dma-coherent; +}; + +&lpuart0 { + dma-coherent; +}; + +&lpuart1 { + dma-coherent; +}; + +&lpuart2 { + dma-coherent; +}; + +&lpuart3 { + dma-coherent; +}; + +&lpuart4 { + dma-coherent; +}; + +&lpuart5 { + dma-coherent; +}; + +&ftm_alarm0 { + dma-coherent; +}; + +&wdog0 { + dma-coherent; +}; + +&edma0 { + dma-coherent; +}; + +&sata { + dma-coherent; +}; + +&qdma { + dma-coherent; +}; + +&msi1 { + dma-coherent; +}; + +&msi2 { + dma-coherent; +}; + +&msi3 { + dma-coherent; +}; + +&fman0 { + dma-coherent; +}; + +&ptp_timer0 { + dma-coherent; +}; + +&fsldpaa { + dma-coherent; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-usdpaa.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-usdpaa.dts new file mode 100644 index 00000000000000..bd4f884eb945a7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-usdpaa.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Freescale Layerscape-1046A family SoC. + * + * Copyright 2019 NXP. + * + */ + +#include "fsl-ls1046a-frwy-sdk.dts" + +&soc { + bp7: buffer-pool@7 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <7>; + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>; + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>; + dma-coherent; + }; + + bp8: buffer-pool@8 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <8>; + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>; + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; + dma-coherent; + }; + + bp9: buffer-pool@9 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <9>; + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>; + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; + dma-coherent; + }; + + fsl,dpaa { + compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus"; + dma-coherent; + + ethernet@0 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x50 1 0x51 1>; + fsl,qman-frame-queues-tx = <0x70 1 0x71 1>; + }; + + ethernet@4 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x52 1 0x53 1>; + fsl,qman-frame-queues-tx = <0x72 1 0x73 1>; + }; + + ethernet@5 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>; + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>; + }; + + ethernet@9 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>; + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>; + }; + + dpa-fman0-oh@2 { + compatible = "fsl,dpa-oh"; + /* Define frame queues for the OH port*/ + /* */ + fsl,qman-frame-queues-oh = <0x60 1 0x61 1>; + fsl,fman-oh-port = <&fman0_oh2>; + }; + }; + + pcie@3400000 { + /delete-property/ iommu-map; + }; + + pcie@3500000 { + /delete-property/ iommu-map; + }; + + pcie@3600000 { + /delete-property/ iommu-map; + }; + + /delete-node/ iommu@9000000; +}; +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + /* For legacy usdpaa based use-cases, update the size and + alignment parameters. e.g. to allocate 256 MB memory: + size = <0 0x10000000>; + alignment = <0 0x10000000>; + */ + + usdpaa_mem: usdpaa_mem { + compatible = "fsl,usdpaa-mem"; + alloc-ranges = <0 0 0x10000 0>; + size = <0 0x1000>; + alignment = <0 0x1000>; + }; + }; +}; + +&fman0 { + fman0_oh2: port@83000 { + cell-index = <1>; + compatible = "fsl,fman-port-oh"; + reg = <0x83000 0x1000>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts index 3595be0f252773..1f434e693c8168 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts @@ -112,6 +112,23 @@ }; + +&qspi { + num-cs = <1>; + bus-num = <0>; + status = "okay"; + + qflash0: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + #include "fsl-ls1046-post.dtsi" &fman0 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts new file mode 100644 index 00000000000000..d5de7ea92c5bb3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts @@ -0,0 +1,264 @@ +/* + * Device Tree Include file for Freescale Layerscape-1046A family SoC. + * + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * + * Mingkai Hu + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "fsl-ls1046a-qds.dts" +#include "qoriq-qman-portals-sdk.dtsi" +#include "qoriq-bman-portals-sdk.dtsi" + +&bman_fbpr { + compatible = "fsl,bman-fbpr"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&soc { +/delete-property/ dma-coherent; + +#include "qoriq-dpaa-eth.dtsi" +#include "qoriq-fman3-0-6oh.dtsi" + +pcie@3400000 { + /delete-property/ iommu-map; +}; + +pcie@3500000 { + /delete-property/ iommu-map; +}; + +pcie@3600000 { + /delete-property/ iommu-map; +}; + +/delete-node/ iommu@9000000; +}; + +&fsldpaa { + ethernet@9 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet7>; + dma-coherent; + }; +}; + +&fman0 { + compatible = "fsl,fman", "simple-bus"; + dma-coherent; +}; + +&clockgen { + dma-coherent; +}; + +&scfg { + dma-coherent; +}; + +&crypto { + dma-coherent; +}; + +&dcfg { + dma-coherent; +}; + +&ifc { + dma-coherent; +}; + +&qspi { + dma-coherent; +}; + +&esdhc { + dma-coherent; +}; + +&ddr { + dma-coherent; +}; + +&tmu { + dma-coherent; +}; + +&qman { + dma-coherent; +}; + +&bman { + dma-coherent; +}; + +&bportals { + dma-coherent; +}; + +&qportals { + dma-coherent; +}; + +&dspi { + dma-coherent; +}; + +&i2c0 { + dma-coherent; +}; + +&i2c1 { + dma-coherent; +}; + +&i2c2 { + dma-coherent; +}; + +&i2c3 { + dma-coherent; +}; + +&duart0 { + dma-coherent; +}; + +&duart1 { + dma-coherent; +}; + +&duart2 { + dma-coherent; +}; + +&duart3 { + dma-coherent; +}; + +&gpio0 { + dma-coherent; +}; + +&gpio1 { + dma-coherent; +}; + +&gpio2 { + dma-coherent; +}; + +&gpio3 { + dma-coherent; +}; + +&lpuart0 { + dma-coherent; +}; + +&lpuart1 { + dma-coherent; +}; + +&lpuart2 { + dma-coherent; +}; + +&lpuart3 { + dma-coherent; +}; + +&lpuart4 { + dma-coherent; +}; + +&lpuart5 { + dma-coherent; +}; + +&ftm_alarm0 { + dma-coherent; +}; + +&wdog0 { + dma-coherent; +}; + +&edma0 { + dma-coherent; +}; + +&sata { + dma-coherent; +}; + +&qdma { + dma-coherent; +}; + +&msi1 { + dma-coherent; +}; + +&msi2 { + dma-coherent; +}; + +&msi3 { + dma-coherent; +}; + +&ptp_timer0 { + dma-coherent; +}; + +&fsldpaa { + dma-coherent; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts index eec62c63dafe24..35fa10a5d594e0 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts @@ -3,7 +3,7 @@ * Device Tree Include file for Freescale Layerscape-1046A family SoC. * * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2018 NXP + * Copyright 2018-2019 NXP * * Shaohui Xie */ @@ -25,6 +25,20 @@ serial1 = &duart1; serial2 = &duart2; serial3 = &duart3; + + emi1-slot1 = &ls1046mdio_s1; + emi1-slot2 = &ls1046mdio_s2; + emi1-slot4 = &ls1046mdio_s4; + + sgmii-s1-p1 = &sgmii_phy_s1_p1; + sgmii-s1-p2 = &sgmii_phy_s1_p2; + sgmii-s1-p3 = &sgmii_phy_s1_p3; + sgmii-s1-p4 = &sgmii_phy_s1_p4; + sgmii-s4-p1 = &sgmii_phy_s4_p1; + qsgmii-s2-p1 = &qsgmii_phy_s2_p1; + qsgmii-s2-p2 = &qsgmii_phy_s2_p2; + qsgmii-s2-p3 = &qsgmii_phy_s2_p3; + qsgmii-s2-p4 = &qsgmii_phy_s2_p4; }; chosen { @@ -153,8 +167,9 @@ }; fpga: board-control@2,0 { - compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis"; + compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-bus"; reg = <0x2 0x0 0x0000100>; + ranges = <0 2 0 0x100>; }; }; @@ -169,7 +184,7 @@ compatible = "spansion,m25p80"; #address-cells = <1>; #size-cells = <1>; - spi-max-frequency = <20000000>; + spi-max-frequency = <50000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; reg = <0>; @@ -177,3 +192,137 @@ }; #include "fsl-ls1046-post.dtsi" + +&fman0 { + ethernet@e0000 { + phy-handle = <&qsgmii_phy_s2_p1>; + phy-connection-type = "sgmii"; + }; + + ethernet@e2000 { + phy-handle = <&sgmii_phy_s4_p1>; + phy-connection-type = "sgmii"; + }; + + ethernet@e4000 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii"; + }; + + ethernet@e6000 { + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii"; + }; + + ethernet@e8000 { + phy-handle = <&sgmii_phy_s1_p3>; + phy-connection-type = "sgmii"; + }; + + ethernet@ea000 { + phy-handle = <&sgmii_phy_s1_p4>; + phy-connection-type = "sgmii"; + }; + + ethernet@f0000 { /* DTSEC9/10GEC1 */ + phy-handle = <&sgmii_phy_s1_p1>; + phy-connection-type = "xgmii"; + }; + + ethernet@f2000 { /* DTSEC10/10GEC2 */ + phy-handle = <&sgmii_phy_s1_p2>; + phy-connection-type = "xgmii"; + }; +}; + +&fpga { + #address-cells = <1>; + #size-cells = <1>; + mdio-mux-emi1 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + mdio-parent-bus = <&mdio0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x54 1>; /* BRDCFG4 */ + mux-mask = <0xe0>; /* EMI1 */ + + /* On-board RGMII1 PHY */ + ls1046mdio0: mdio@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + rgmii_phy1: ethernet-phy@1 { /* MAC3 */ + reg = <0x1>; + }; + }; + + /* On-board RGMII2 PHY */ + ls1046mdio1: mdio@1 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + rgmii_phy2: ethernet-phy@2 { /* MAC4 */ + reg = <0x2>; + }; + }; + + /* Slot 1 */ + ls1046mdio_s1: mdio@2 { + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sgmii_phy_s1_p1: ethernet-phy@1c { + reg = <0x1c>; + }; + + sgmii_phy_s1_p2: ethernet-phy@1d { + reg = <0x1d>; + }; + + sgmii_phy_s1_p3: ethernet-phy@1e { + reg = <0x1e>; + }; + + sgmii_phy_s1_p4: ethernet-phy@1f { + reg = <0x1f>; + }; + }; + + /* Slot 2 */ + ls1046mdio_s2: mdio@3 { + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + qsgmii_phy_s2_p1: ethernet-phy@8 { + reg = <0x8>; + }; + qsgmii_phy_s2_p2: ethernet-phy@9 { + reg = <0x9>; + }; + qsgmii_phy_s2_p3: ethernet-phy@a { + reg = <0xa>; + }; + qsgmii_phy_s2_p4: ethernet-phy@b { + reg = <0xb>; + }; + }; + + /* Slot 4 */ + ls1046mdio_s4: mdio@5 { + reg = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sgmii_phy_s4_p1: ethernet-phy@1c { + reg = <0x1c>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts new file mode 100644 index 00000000000000..d9ae081b4f3bc6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts @@ -0,0 +1,273 @@ +/* + * Device Tree Include file for Freescale Layerscape-1046A family SoC. + * + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * + * Mingkai Hu + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "fsl-ls1046a-rdb.dts" +#include "qoriq-qman-portals-sdk.dtsi" +#include "qoriq-bman-portals-sdk.dtsi" + +&bman_fbpr { + compatible = "fsl,bman-fbpr"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&soc { +/delete-property/ dma-coherent; + +#include "qoriq-dpaa-eth.dtsi" +#include "qoriq-fman3-0-6oh.dtsi" + +pcie@3400000 { + /delete-property/ iommu-map; +}; + +pcie@3500000 { + /delete-property/ iommu-map; +}; + +pcie@3600000 { + /delete-property/ iommu-map; +}; + +/delete-node/ iommu@9000000; +}; + +&fsldpaa { + ethernet@0 { + status = "disabled"; + }; + ethernet@1 { + status = "disabled"; + }; + ethernet@9 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet7>; + dma-coherent; + }; +}; + +&fman0 { + compatible = "fsl,fman", "simple-bus"; +}; + +&clockgen { + dma-coherent; +}; + +&scfg { + dma-coherent; +}; + +&crypto { + dma-coherent; +}; + +&dcfg { + dma-coherent; +}; + +&ifc { + dma-coherent; +}; + +&qspi { + dma-coherent; +}; + +&esdhc { + dma-coherent; +}; + +&ddr { + dma-coherent; +}; + +&tmu { + dma-coherent; +}; + +&qman { + dma-coherent; +}; + +&bman { + dma-coherent; +}; + +&bportals { + dma-coherent; +}; + +&qportals { + dma-coherent; +}; + +&dspi { + dma-coherent; +}; + +&i2c0 { + dma-coherent; +}; + +&i2c1 { + dma-coherent; +}; + +&i2c2 { + dma-coherent; +}; + +&i2c3 { + dma-coherent; +}; + +&duart0 { + dma-coherent; +}; + +&duart1 { + dma-coherent; +}; + +&duart2 { + dma-coherent; +}; + +&duart3 { + dma-coherent; +}; + +&gpio0 { + dma-coherent; +}; + +&gpio1 { + dma-coherent; +}; + +&gpio2 { + dma-coherent; +}; + +&gpio3 { + dma-coherent; +}; + +&lpuart0 { + dma-coherent; +}; + +&lpuart1 { + dma-coherent; +}; + +&lpuart2 { + dma-coherent; +}; + +&lpuart3 { + dma-coherent; +}; + +&lpuart4 { + dma-coherent; +}; + +&lpuart5 { + dma-coherent; +}; + +&ftm_alarm0 { + dma-coherent; +}; + +&wdog0 { + dma-coherent; +}; + +&edma0 { + dma-coherent; +}; + +&sata { + dma-coherent; +}; + +&qdma { + dma-coherent; +}; + +&msi1 { + dma-coherent; +}; + +&msi2 { + dma-coherent; +}; + +&msi3 { + dma-coherent; +}; + +&fman0 { + dma-coherent; +}; + +&ptp_timer0 { + dma-coherent; +}; + +&fsldpaa { + dma-coherent; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts new file mode 100644 index 00000000000000..343c9d81a83f94 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts @@ -0,0 +1,133 @@ +/* + * Device Tree Include file for Freescale Layerscape-1046A family SoC. + * + * Copyright (C) 2016, Freescale Semiconductor + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include "fsl-ls1046a-rdb-sdk.dts" + +&soc { + bp7: buffer-pool@7 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <7>; + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>; + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>; + dma-coherent; + }; + + bp8: buffer-pool@8 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <8>; + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>; + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; + dma-coherent; + }; + + bp9: buffer-pool@9 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <9>; + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>; + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; + dma-coherent; + }; + + fsl,dpaa { + compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus"; + dma-coherent; + + ethernet@2 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>; + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>; + }; + + ethernet@3 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>; + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>; + }; + + ethernet@4 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x58 1 0x59 1>; + fsl,qman-frame-queues-tx = <0x78 1 0x79 1>; + }; + + ethernet@5 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1>; + fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1>; + }; + + ethernet@8 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>; + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>; + }; + + ethernet@9 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1>; + fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1>; + }; + + dpa-fman0-oh@2 { + compatible = "fsl,dpa-oh"; + /* Define frame queues for the OH port*/ + /* */ + fsl,qman-frame-queues-oh = <0x60 1 0x61 1>; + fsl,fman-oh-port = <&fman0_oh2>; + }; + }; + + pcie@3400000 { + /delete-property/ iommu-map; + }; + + pcie@3500000 { + /delete-property/ iommu-map; + }; + + pcie@3600000 { + /delete-property/ iommu-map; + }; + + /delete-node/ iommu@9000000; +}; +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* For legacy usdpaa based use-cases, update the size and + alignment parameters. e.g. to allocate 256 MB memory: + size = <0 0x10000000>; + alignment = <0 0x10000000>; + */ + usdpaa_mem: usdpaa_mem { + compatible = "fsl,usdpaa-mem"; + alloc-ranges = <0 0 0x10000 0>; + size = <0 0x1000>; + alignment = <0 0x1000>; + }; + }; +}; + +&fman0 { + fman0_oh2: port@83000 { + cell-index = <1>; + compatible = "fsl,fman-port-oh"; + reg = <0x83000 0x1000>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts index 2743397591141f..3fc9b35fac9cc2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts @@ -3,6 +3,7 @@ * Device Tree Include file for Freescale Layerscape-1046A family SoC. * * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2019 NXP * * Mingkai Hu */ @@ -43,6 +44,10 @@ sd-uhs-sdr12; }; +&usb1 { + dr_mode = "otg"; +}; + &i2c0 { status = "okay"; @@ -101,23 +106,23 @@ &qspi { status = "okay"; - qflash0: flash@0 { - compatible = "spansion,m25p80"; + s25fs512s0: flash@0 { + compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; - spi-max-frequency = <20000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <1>; + spi-tx-bus-width = <1>; reg = <0>; }; - qflash1: flash@1 { - compatible = "spansion,m25p80"; + s25fs512s: flash@1 { + compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; - spi-max-frequency = <20000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <1>; + spi-tx-bus-width = <1>; reg = <1>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index d4c1da3d4bde28..91b1eb8a2917fa 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -28,13 +28,14 @@ ethernet5 = &enet5; ethernet6 = &enet6; ethernet7 = &enet7; + rtc1 = &ftm_alarm0; }; cpus { #address-cells = <1>; #size-cells = <0>; - cpu0: cpu@0 { + cooling_map0: cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x0>; @@ -116,38 +117,7 @@ mask = <0x02>; }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 3>; - - trips { - cpu_alert: cpu-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; + #include "fsl-tmu.dtsi" timer { compatible = "arm,armv8-timer"; @@ -190,6 +160,8 @@ #address-cells = <2>; #size-cells = <2>; ranges; + dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; + dma-coherent; ddr: memory-controller@1080000 { compatible = "fsl,qoriq-memory-controller"; @@ -229,6 +201,49 @@ bus-width = <4>; }; + smmu: iommu@9000000 { + compatible = "arm,mmu-500"; + reg = <0 0x9000000 0 0x400000>; + dma-coherent; + stream-match-mask = <0x7f00>; + #global-interrupts = <2>; + #iommu-cells = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + scfg: scfg@1570000 { compatible = "fsl,ls1046a-scfg", "syscon"; reg = <0x0 0x1570000 0x0 0x10000>; @@ -304,7 +319,7 @@ dcfg: dcfg@1ee0000 { compatible = "fsl,ls1046a-dcfg", "syscon"; - reg = <0x0 0x1ee0000 0x0 0x10000>; + reg = <0x0 0x1ee0000 0x0 0x1000>; big-endian; }; @@ -376,7 +391,7 @@ }; i2c0: i2c@2180000 { - compatible = "fsl,vf610-i2c"; + compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2180000 0x0 0x10000>; @@ -385,6 +400,7 @@ dmas = <&edma0 1 39>, <&edma0 1 38>; dma-names = "tx", "rx"; + scl-gpios = <&gpio3 12 0>; status = "disabled"; }; @@ -409,12 +425,13 @@ }; i2c3: i2c@21b0000 { - compatible = "fsl,vf610-i2c"; + compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x21b0000 0x0 0x10000>; interrupts = ; clocks = <&clockgen 4 1>; + scl-gpios = <&gpio3 12 0>; status = "disabled"; }; @@ -568,43 +585,63 @@ <&clockgen 4 1>; }; - usb0: usb@2f00000 { - compatible = "snps,dwc3"; - reg = <0x0 0x2f00000 0x0 0x10000>; - interrupts = ; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - usb1: usb@3000000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3000000 0x0 0x10000>; - interrupts = ; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - usb2: usb@3100000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = ; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - sata: sata@3200000 { - compatible = "fsl,ls1046a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>, - <0x0 0x20140520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = ; - clocks = <&clockgen 4 1>; + aux_bus: aux_bus { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>; + + usb0: usb@2f00000 { + compatible = "fsl,ls1046a-dwc3", "snps,dwc3"; + reg = <0x0 0x2f00000 0x0 0x10000>; + interrupts = ; + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + usb3-lpm-capable; + snps,dis-u1u2-when-u3-quirk; + snps,host-vbus-glitches; + dma-coherent; + }; + + usb1: usb@3000000 { + compatible = "fsl,ls1046a-dwc3", "snps,dwc3"; + reg = <0x0 0x3000000 0x0 0x10000>; + interrupts = ; + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + usb3-lpm-capable; + snps,dis-u1u2-when-u3-quirk; + snps,host-vbus-glitches; + dma-coherent; + }; + + usb2: usb@3100000 { + compatible = "fsl,ls1046a-dwc3", "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = ; + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + usb3-lpm-capable; + snps,dis-u1u2-when-u3-quirk; + snps,host-vbus-glitches; + dma-coherent; + }; + + sata: sata@3200000 { + compatible = "fsl,ls1046a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>, + <0x0 0x20140520 0x0 0x4>; + reg-names = "ahci", "sata-ecc"; + interrupts = ; + clocks = <&clockgen 4 1>; + }; }; msi1: msi-controller@1580000 { @@ -649,6 +686,7 @@ #size-cells = <2>; device_type = "pci"; dma-coherent; + iommu-map = <0 &smmu 0 1>; /* update by bootloader */ num-viewport = <8>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -685,6 +723,7 @@ #size-cells = <2>; device_type = "pci"; dma-coherent; + iommu-map = <0 &smmu 0 1>; /* update by bootloader */ num-viewport = <8>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -721,6 +760,7 @@ #size-cells = <2>; device_type = "pci"; dma-coherent; + iommu-map = <0 &smmu 0 1>; /* update by bootloader */ num-viewport = <8>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -765,6 +805,20 @@ queue-sizes = <64 64>; big-endian; }; + + rcpm: rcpm@1ee208c { + compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+"; + reg = <0x0 0x1ee208c 0x0 0x4>; + #fsl,rcpm-wakeup-cells = <1>; + }; + + ftm_alarm0: timer@29d0000 { + compatible = "fsl,ls1046a-ftm-alarm"; + reg = <0x0 0x29d0000 0x0 0x10000>; + fsl,rcpm-wakeup = <&rcpm 0x20000>; + interrupts = ; + big-endian; + }; }; reserved-memory { @@ -804,3 +858,25 @@ #include "qoriq-qman-portals.dtsi" #include "qoriq-bman-portals.dtsi" + +&thermal_zones { + thermal-zone0 { + status = "okay"; + }; + + thermal-zone1 { + status = "okay"; + }; + + thermal-zone2 { + status = "okay"; + }; + + thermal-zone3 { + status = "okay"; + }; + + thermal-zone4 { + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts index 120e62dad1542d..38e3bed550470d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts @@ -131,6 +131,30 @@ }; }; +&qspi { + status = "okay"; + fsl,qspi-has-second-chip; + qflash0: s25fs512s@0 { + compatible = "spansion,m25p80"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; + + qflash1: s25fs512s@1 { + compatible = "spansion,m25p80"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <1>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + &duart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts index 8e925df6c01c04..c8c73e29ca0dec 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts @@ -74,6 +74,31 @@ }; }; +&qspi { + status = "okay"; + + s25fs512s0: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + spi-rx-bus-width = <1>; + spi-tx-bus-width = <1>; + }; + + s25fs512s1: flash@1 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <1>; + spi-rx-bus-width = <1>; + spi-tx-bus-width = <1>; + }; + +}; + &duart0 { status = "okay"; }; @@ -95,5 +120,85 @@ }; &usb1 { + dr_mode = "otg"; status = "okay"; }; + +&emdio1 { + /* Freescale F104 PHY1 */ + mdio1_phy1: emdio1_phy@1 { + reg = <0x1c>; + phy-connection-type = "qsgmii"; + }; + mdio1_phy2: emdio1_phy@2 { + reg = <0x1d>; + phy-connection-type = "qsgmii"; + }; + mdio1_phy3: emdio1_phy@3 { + reg = <0x1e>; + phy-connection-type = "qsgmii"; + }; + mdio1_phy4: emdio1_phy@4 { + reg = <0x1f>; + phy-connection-type = "qsgmii"; + }; + /* F104 PHY2 */ + mdio1_phy5: emdio1_phy@5 { + reg = <0x0c>; + phy-connection-type = "qsgmii"; + }; + mdio1_phy6: emdio1_phy@6 { + reg = <0x0d>; + phy-connection-type = "qsgmii"; + }; + mdio1_phy7: emdio1_phy@7 { + reg = <0x0e>; + phy-connection-type = "qsgmii"; + }; + mdio1_phy8: emdio1_phy@8 { + reg = <0x0f>; + phy-connection-type = "qsgmii"; + }; +}; + +&emdio2 { + /* Aquantia AQR105 10G PHY */ + mdio2_phy1: emdio2_phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 2 0x4>; + reg = <0x0>; + phy-connection-type = "xfi"; + }; +}; + +/* DPMAC connections to external PHYs + * based on LS1088A RM RevC - $24.1.2 SerDes Options + */ +/* DPMAC1 is 10G SFP+, fixed link */ +&dpmac2 { + phy-handle = <&mdio2_phy1>; +}; +&dpmac3 { + phy-handle = <&mdio1_phy5>; +}; +&dpmac4 { + phy-handle = <&mdio1_phy6>; +}; +&dpmac5 { + phy-handle = <&mdio1_phy7>; +}; +&dpmac6 { + phy-handle = <&mdio1_phy8>; +}; +&dpmac7 { + phy-handle = <&mdio1_phy1>; +}; +&dpmac8 { + phy-handle = <&mdio1_phy2>; +}; +&dpmac9 { + phy-handle = <&mdio1_phy3>; +}; +&dpmac10 { + phy-handle = <&mdio1_phy4>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index c676d0771762fc..217d98ba1c411c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Include file for NXP Layerscape-1088A family SoC. * - * Copyright 2017 NXP + * Copyright 2017-2019 NXP * * Harninder Rai * @@ -18,6 +18,7 @@ aliases { crypto = &crypto; + rtc1 = &ftm_alarm0; }; cpus { @@ -25,7 +26,7 @@ #size-cells = <0>; /* We have 2 clusters having 4 Cortex-A53 cores each */ - cpu0: cpu@0 { + cooling_map0: cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; @@ -61,7 +62,7 @@ #cooling-cells = <2>; }; - cpu4: cpu@100 { + cooling_map1: cpu4: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x100>; @@ -128,42 +129,7 @@ }; }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 0>; - - trips { - cpu_alert: cpu-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; + #include "fsl-tmu.dtsi" timer { compatible = "arm,armv8-timer"; @@ -185,6 +151,19 @@ clock-output-names = "sysclk"; }; + rstcr: syscon@1e60000 { + compatible = "fsl,ls1088a-rstcr", "syscon"; + reg = <0x0 0x1e60000 0x0 0x4>; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&rstcr>; + offset = <0x0>; + mask = <0x02>; + }; + + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -325,6 +304,32 @@ #interrupt-cells = <2>; }; + /* TODO: WRIOP (CCSR?) */ + emdio1: mdio@8B96000 { /* WRIOP0: 0x8B8_0000, + * E-MDIO1: 0x1_6000 + */ + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8B96000 0x0 0x1000>; + device_type = "mdio"; + little-endian; /* force the driver in LE mode */ + + /* Not necessary on the QDS, but needed on the RDB */ + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio2: mdio@8B97000 { /* WRIOP0: 0x8B8_0000, + * E-MDIO2: 0x1_7000 + */ + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8B97000 0x0 0x1000>; + device_type = "mdio"; + little-endian; /* force the driver in LE mode */ + + #address-cells = <1>; + #size-cells = <0>; + }; + ifc: ifc@2240000 { compatible = "fsl,ifc", "simple-bus"; reg = <0x0 0x2240000 0x0 0x20000>; @@ -336,12 +341,13 @@ }; i2c0: i2c@2000000 { - compatible = "fsl,vf610-i2c"; + compatible = "fsl,vf610-i2c", "fsl,ls1088a-vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2000000 0x0 0x10000>; interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen 4 7>; + scl-gpios = <&gpio3 30 0>; status = "disabled"; }; @@ -388,23 +394,28 @@ }; usb0: usb3@3100000 { - compatible = "snps,dwc3"; + compatible = "fsl,ls1088a-dwc3", "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; + dma-coherent; status = "disabled"; }; usb1: usb3@3110000 { - compatible = "snps,dwc3"; + compatible = "fsl,ls1088a-dwc3", "snps,dwc3"; reg = <0x0 0x3110000 0x0 0x10000>; interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; + dma-coherent; status = "disabled"; }; @@ -418,6 +429,17 @@ dma-coherent; status = "disabled"; }; + qspi: spi@20c0000 { + compatible = "fsl,ls2080a-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20c0000 0x0 0x10000>, + <0x0 0x20000000 0x0 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <0 25 0x4>; /* Level high type */ + clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clock-names = "qspi_en", "qspi"; + }; crypto: crypto@8000000 { compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; @@ -474,6 +496,7 @@ ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, @@ -499,6 +522,7 @@ ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>, @@ -524,6 +548,7 @@ ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>, @@ -764,6 +789,20 @@ }; }; }; + + rcpm: rcpm@1e34040 { + compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+"; + reg = <0x0 0x1e34040 0x0 0x18>; + #fsl,rcpm-wakeup-cells = <6>; + little-endian; + }; + + ftm_alarm0: timer@2800000 { + compatible = "fsl,ls1088a-ftm-alarm"; + reg = <0x0 0x2800000 0x0 0x10000>; + fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; + interrupts = <0 44 4>; + }; }; firmware { @@ -773,3 +812,15 @@ }; }; }; + +#include "fsl-tmu-map1.dtsi" + +&thermal_zones { + thermal-zone0 { + status = "okay"; + }; + + thermal-zone1 { + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts index f6c3ee78ace06c..20157fd69530a4 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts @@ -23,3 +23,65 @@ stdout-path = "serial0:115200n8"; }; }; + +&ifc { + boardctrl: board-control@3,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus"; + reg = <3 0 0x300>; /* TODO check address */ + ranges = <0 3 0 0x300>; + + mdio_mux_emi1 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + mdio-parent-bus = <&emdio1>; + reg = <0x54 1>; /* BRDCFG4 */ + mux-mask = <0xe0>; /* EMI1_MDIO */ + + #address-cells=<1>; + #size-cells = <0>; + + /* Child MDIO buses, one for each riser card: + * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0. + * VSC8234 PHYs on the riser cards. + */ + + mdio_mux3: mdio@60 { + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + mdio0_phy12: mdio_phy0@1c { + reg = <0x1c>; + phy-connection-type = "sgmii"; + }; + mdio0_phy13: mdio_phy1@1d { + reg = <0x1d>; + phy-connection-type = "sgmii"; + }; + mdio0_phy14: mdio_phy2@1e { + reg = <0x1e>; + phy-connection-type = "sgmii"; + }; + mdio0_phy15: mdio_phy3@1f { + reg = <0x1f>; + phy-connection-type = "sgmii"; + }; + }; + }; + }; +}; + +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */ +&dpmac9 { + phy-handle = <&mdio0_phy12>; +}; +&dpmac10 { + phy-handle = <&mdio0_phy13>; +}; +&dpmac11 { + phy-handle = <&mdio0_phy14>; +}; +&dpmac12 { + phy-handle = <&mdio0_phy15>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts index 44894356059ce0..2ed99e98f59dc5 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts @@ -23,3 +23,83 @@ stdout-path = "serial1:115200n8"; }; }; + +&emdio1 { + status = "disabled"; + /* CS4340 PHYs */ + mdio1_phy1: emdio1_phy@1 { + reg = <0x10>; + phy-connection-type = "xfi"; + }; + mdio1_phy2: emdio1_phy@2 { + reg = <0x11>; + phy-connection-type = "xfi"; + }; + mdio1_phy3: emdio1_phy@3 { + reg = <0x12>; + phy-connection-type = "xfi"; + }; + mdio1_phy4: emdio1_phy@4 { + reg = <0x13>; + phy-connection-type = "xfi"; + }; +}; + +&emdio2 { + /* AQR405 PHYs */ + mdio2_phy1: emdio2_phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 1 0x4>; /* Level high type */ + reg = <0x0>; + phy-connection-type = "xfi"; + }; + mdio2_phy2: emdio2_phy@2 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 2 0x4>; /* Level high type */ + reg = <0x1>; + phy-connection-type = "xfi"; + }; + mdio2_phy3: emdio2_phy@3 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 4 0x4>; /* Level high type */ + reg = <0x2>; + phy-connection-type = "xfi"; + }; + mdio2_phy4: emdio2_phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 5 0x4>; /* Level high type */ + reg = <0x3>; + phy-connection-type = "xfi"; + }; +}; + +/* Update DPMAC connections to external PHYs, under the assumption of + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board. + */ +/* Leave Cortina nodes commented out until driver is integrated + *&dpmac1 { + * phy-handle = <&mdio1_phy1>; + *}; + *&dpmac2 { + * phy-handle = <&mdio1_phy2>; + *}; + *&dpmac3 { + * phy-handle = <&mdio1_phy3>; + *}; + *&dpmac4 { + * phy-handle = <&mdio1_phy4>; + *}; + */ + +&dpmac5 { + phy-handle = <&mdio2_phy1>; +}; +&dpmac6 { + phy-handle = <&mdio2_phy2>; +}; +&dpmac7 { + phy-handle = <&mdio2_phy3>; +}; +&dpmac8 { + phy-handle = <&mdio2_phy4>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index f9c1d30cf4a7df..3b00e6f1b24350 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -12,7 +12,7 @@ #include "fsl-ls208xa.dtsi" &cpu { - cpu0: cpu@0 { + cooling_map0: cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0>; @@ -32,7 +32,7 @@ #cooling-cells = <2>; }; - cpu2: cpu@100 { + cooling_map1: cpu2: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x100>; @@ -52,7 +52,7 @@ #cooling-cells = <2>; }; - cpu4: cpu@200 { + cooling_map2: cpu4: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x200>; @@ -72,7 +72,7 @@ #cooling-cells = <2>; }; - cpu6: cpu@300 { + cooling_map3: cpu6: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x300>; @@ -118,6 +118,18 @@ }; }; +&timer { + fsl,erratum-a008585; +}; + +&usb0 { + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; +}; + +&usb1 { + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; +}; + &pcie1 { reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 0x10 0x00000000 0x0 0x00002000>; /* configuration space */ diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts new file mode 100644 index 00000000000000..0e240a97f589b4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for NXP LS2081A RDB Board. + * + * Copyright 2017 NXP + * + * Priyanka Jain + * + */ + +/dts-v1/; + +#include "fsl-ls2088a.dtsi" + +/ { + model = "NXP Layerscape 2081A RDB Board"; + compatible = "fsl,ls2081a-rdb", "fsl,ls2081a"; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; +}; + +&esdhc { + status = "okay"; +}; + +&ifc { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + pca9547@75 { + compatible = "nxp,pca9547"; + reg = <0x75>; + #address-cells = <1>; + #size-cells = <0>; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x01>; + rtc@51 { + compatible = "nxp,pcf2129"; + reg = <0x51>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x02>; + + ina220@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <500>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + adt7481@4c { + compatible = "adi,adt7461"; + reg = <0x4c>; + }; + }; + }; +}; + +&dspi { + status = "okay"; + dflash0: n25q512a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p80"; + spi-max-frequency = <3000000>; + reg = <0>; + }; +}; + +&qspi { + status = "okay"; + fsl,qspi-has-second-chip; + flash0: s25fs512s@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,m25p80"; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + spi-max-frequency = <20000000>; + reg = <0>; + }; + flash1: s25fs512s@1 { + #address-cells = <1>; + #size-cells = <1>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + compatible = "spansion,m25p80"; + spi-max-frequency = <20000000>; + reg = <1>; + }; +}; + +&sata0 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts index 7c17b1bd4529a0..01a3775528dd17 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts @@ -22,3 +22,65 @@ stdout-path = "serial0:115200n8"; }; }; + +&ifc { + boardctrl: board-control@3,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus"; + reg = <3 0 0x300>; /* TODO check address */ + ranges = <0 3 0 0x300>; + + mdio_mux_emi1 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + mdio-parent-bus = <&emdio1>; + reg = <0x54 1>; /* BRDCFG4 */ + mux-mask = <0xe0>; /* EMI1_MDIO */ + + #address-cells=<1>; + #size-cells = <0>; + + /* Child MDIO buses, one for each riser card: + * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0. + * VSC8234 PHYs on the riser cards. + */ + + mdio_mux3: mdio@60 { + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + mdio0_phy12: mdio_phy0@1c { + reg = <0x1c>; + phy-connection-type = "sgmii"; + }; + mdio0_phy13: mdio_phy1@1d { + reg = <0x1d>; + phy-connection-type = "sgmii"; + }; + mdio0_phy14: mdio_phy2@1e { + reg = <0x1e>; + phy-connection-type = "sgmii"; + }; + mdio0_phy15: mdio_phy3@1f { + reg = <0x1f>; + phy-connection-type = "sgmii"; + }; + }; + }; + }; +}; + +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */ +&dpmac9 { + phy-handle = <&mdio0_phy12>; +}; +&dpmac10 { + phy-handle = <&mdio0_phy13>; +}; +&dpmac11 { + phy-handle = <&mdio0_phy14>; +}; +&dpmac12 { + phy-handle = <&mdio0_phy15>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts index f6b4d75a258bed..a32b0f6e9238e9 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts @@ -22,3 +22,83 @@ stdout-path = "serial1:115200n8"; }; }; + +&emdio1 { + status = "disabled"; + /* CS4340 PHYs */ + mdio1_phy1: emdio1_phy@1 { + reg = <0x10>; + phy-connection-type = "xfi"; + }; + mdio1_phy2: emdio1_phy@2 { + reg = <0x11>; + phy-connection-type = "xfi"; + }; + mdio1_phy3: emdio1_phy@3 { + reg = <0x12>; + phy-connection-type = "xfi"; + }; + mdio1_phy4: emdio1_phy@4 { + reg = <0x13>; + phy-connection-type = "xfi"; + }; +}; + +&emdio2 { + /* AQR405 PHYs */ + mdio2_phy1: emdio2_phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 1 0x4>; /* Level high type */ + reg = <0x0>; + phy-connection-type = "xfi"; + }; + mdio2_phy2: emdio2_phy@2 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 2 0x4>; /* Level high type */ + reg = <0x1>; + phy-connection-type = "xfi"; + }; + mdio2_phy3: emdio2_phy@3 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 4 0x4>; /* Level high type */ + reg = <0x2>; + phy-connection-type = "xfi"; + }; + mdio2_phy4: emdio2_phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 5 0x4>; /* Level high type */ + reg = <0x3>; + phy-connection-type = "xfi"; + }; +}; + +/* Update DPMAC connections to external PHYs, under the assumption of + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board. + */ +/* Leave Cortina PHYs commented out until proper driver is integrated + *&dpmac1 { + * phy-handle = <&mdio1_phy1>; + *}; + *&dpmac2 { + * phy-handle = <&mdio1_phy2>; + *}; + *&dpmac3 { + * phy-handle = <&mdio1_phy3>; + *}; + *&dpmac4 { + * phy-handle = <&mdio1_phy4>; + *}; + */ + +&dpmac5 { + phy-handle = <&mdio2_phy1>; +}; +&dpmac6 { + phy-handle = <&mdio2_phy2>; +}; +&dpmac7 { + phy-handle = <&mdio2_phy3>; +}; +&dpmac8 { + phy-handle = <&mdio2_phy4>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi index a5f668d786b81d..c699b65dbfe385 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi @@ -12,7 +12,7 @@ #include "fsl-ls208xa.dtsi" &cpu { - cpu0: cpu@0 { + cooling_map0: cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x0>; @@ -32,7 +32,7 @@ #cooling-cells = <2>; }; - cpu2: cpu@100 { + cooling_map1: cpu2: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x100>; @@ -52,7 +52,7 @@ #cooling-cells = <2>; }; - cpu4: cpu@200 { + cooling_map2: cpu4: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x200>; @@ -72,7 +72,7 @@ #cooling-cells = <2>; }; - cpu6: cpu@300 { + cooling_map3: cpu6: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x300>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi index 10d2fe0919651a..2d05e840fd243b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi @@ -129,6 +129,7 @@ &qspi { status = "okay"; + fsl,qspi-has-second-chip; flash0: s25fl256s1@0 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi index 6fd7f63085c9be..4c4fde6b6d3143 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi @@ -49,6 +49,7 @@ reg = <0x75>; #address-cells = <1>; #size-cells = <0>; + i2c-mux-never-disable; i2c@1 { #address-cells = <1>; #size-cells = <0>; @@ -108,7 +109,15 @@ }; &qspi { - status = "disabled"; + status = "okay"; + + s25fs512s0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + }; }; &sata0 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 7a0be8eaa84a25..30929586970fd5 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -3,7 +3,7 @@ * Device Tree Include file for Freescale Layerscape-2080A family SoC. * * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017-2019 NXP * * Abhimanyu Saini * @@ -24,6 +24,7 @@ serial1 = &serial1; serial2 = &serial2; serial3 = &serial3; + rtc1 = &ftm_alarm0; }; cpu: cpus { @@ -77,50 +78,14 @@ mask = <0x2>; }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <5000>; + #include "fsl-tmu.dtsi" - thermal-sensors = <&tmu 4>; - - trips { - cpu_alert: cpu-alert { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit: cpu-crit { - temperature = <85000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - timer { + timer: timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, /* Physical Secure PPI, active-low */ <1 14 4>, /* Physical Non-Secure PPI, active-low */ <1 11 4>, /* Virtual PPI, active-low */ <1 10 4>; /* Hypervisor PPI, active-low */ - fsl,erratum-a008585; }; pmu { @@ -560,15 +525,42 @@ #interrupt-cells = <2>; }; + /* TODO: WRIOP (CCSR?) */ + emdio1: mdio@8B96000 { /* WRIOP0: 0x8B8_0000, + * E-MDIO1: 0x1_6000 + */ + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8B96000 0x0 0x1000>; + device_type = "mdio"; /* TODO: is this necessary? */ + little-endian; /* force the driver in LE mode */ + + /* Not necessary on the QDS, but needed on the RDB */ + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio2: mdio@8B97000 { /* WRIOP0: 0x8B8_0000, + * E-MDIO2: 0x1_7000 + */ + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8B97000 0x0 0x1000>; + device_type = "mdio"; /* TODO: is this necessary? */ + little-endian; /* force the driver in LE mode */ + + #address-cells = <1>; + #size-cells = <0>; + }; + i2c0: i2c@2000000 { status = "disabled"; - compatible = "fsl,vf610-i2c"; + compatible = "fsl,vf610-i2c", "fsl,ls208xa-vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2000000 0x0 0x10000>; interrupts = <0 34 0x4>; /* Level high type */ clock-names = "i2c"; - clocks = <&clockgen 4 3>; + clocks = <&clockgen 4 1>; + scl-gpios = <&gpio3 10 0>; }; i2c1: i2c@2010000 { @@ -579,7 +571,7 @@ reg = <0x0 0x2010000 0x0 0x10000>; interrupts = <0 34 0x4>; /* Level high type */ clock-names = "i2c"; - clocks = <&clockgen 4 3>; + clocks = <&clockgen 4 1>; }; i2c2: i2c@2020000 { @@ -590,7 +582,7 @@ reg = <0x0 0x2020000 0x0 0x10000>; interrupts = <0 35 0x4>; /* Level high type */ clock-names = "i2c"; - clocks = <&clockgen 4 3>; + clocks = <&clockgen 4 1>; }; i2c3: i2c@2030000 { @@ -601,7 +593,7 @@ reg = <0x0 0x2030000 0x0 0x10000>; interrupts = <0 35 0x4>; /* Level high type */ clock-names = "i2c"; - clocks = <&clockgen 4 3>; + clocks = <&clockgen 4 1>; }; ifc: ifc@2240000 { @@ -618,23 +610,23 @@ }; qspi: spi@20c0000 { - status = "disabled"; - compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi"; + compatible = "fsl,ls2080a-qspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x20c0000 0x0 0x10000>, <0x0 0x20000000 0x0 0x10000000>; reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = <0 25 0x4>; /* Level high type */ + interrupts = ; clocks = <&clockgen 4 3>, <&clockgen 4 3>; clock-names = "qspi_en", "qspi"; + status = "disabled"; }; pcie1: pcie@3400000 { compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; reg-names = "regs", "config"; - interrupts = <0 108 0x4>; /* Level high type */ - interrupt-names = "intr"; + interrupts = <0 108 0x4>; /* aer interrupt */ + interrupt-names = "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -642,6 +634,7 @@ num-viewport = <6>; bus-range = <0x0 0xff>; msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, @@ -654,8 +647,8 @@ pcie2: pcie@3500000 { compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; reg-names = "regs", "config"; - interrupts = <0 113 0x4>; /* Level high type */ - interrupt-names = "intr"; + interrupts = <0 113 0x4>; /* aer interrupt */ + interrupt-names = "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -663,6 +656,7 @@ num-viewport = <6>; bus-range = <0x0 0xff>; msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, @@ -675,8 +669,8 @@ pcie3: pcie@3600000 { compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; reg-names = "regs", "config"; - interrupts = <0 118 0x4>; /* Level high type */ - interrupt-names = "intr"; + interrupts = <0 118 0x4>; /* aer interrupt */ + interrupt-names = "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -684,6 +678,7 @@ num-viewport = <256>; bus-range = <0x0 0xff>; msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, @@ -696,8 +691,8 @@ pcie4: pcie@3700000 { compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; reg-names = "regs", "config"; - interrupts = <0 123 0x4>; /* Level high type */ - interrupt-names = "intr"; + interrupts = <0 123 0x4>; /* aer interrupt */ + interrupt-names = "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -705,6 +700,7 @@ num-viewport = <6>; bus-range = <0x0 0xff>; msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>, @@ -734,24 +730,26 @@ usb0: usb3@3100000 { status = "disabled"; - compatible = "snps,dwc3"; + compatible = "fsl,ls2088a-dwc3", "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = <0 80 0x4>; /* Level high type */ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; }; usb1: usb3@3110000 { status = "disabled"; - compatible = "snps,dwc3"; + compatible = "fsl,ls2088a-dwc3", "snps,dwc3"; reg = <0x0 0x3110000 0x0 0x10000>; interrupts = <0 81 0x4>; /* Level high type */ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; }; ccn@4000000 { @@ -759,6 +757,20 @@ reg = <0x0 0x04000000 0x0 0x01000000>; interrupts = <0 12 4>; }; + + rcpm: rcpm@1e34040 { + compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+"; + reg = <0x0 0x1e34040 0x0 0x18>; + #fsl,rcpm-wakeup-cells = <6>; + little-endian; + }; + + ftm_alarm0: timer@2800000 { + compatible = "fsl,ls208xa-ftm-alarm"; + reg = <0x0 0x2800000 0x0 0x10000>; + fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; + interrupts = <0 44 4>; + }; }; ddr1: memory-controller@1080000 { @@ -782,3 +794,36 @@ }; }; }; + +#include "fsl-tmu-map1.dtsi" +#include "fsl-tmu-map2.dtsi" +#include "fsl-tmu-map3.dtsi" +&thermal_zones { + thermal-zone1 { + status = "okay"; + }; + + thermal-zone2{ + status = "okay"; + }; + + thermal-zone3{ + status = "okay"; + }; + + thermal-zone4{ + status = "okay"; + }; + + thermal-zone5{ + status = "okay"; + }; + + thermal-zone6{ + status = "okay"; + }; + + thermal-zone7 { + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts index 1a5acf62f23c65..a0c27b5bac0d8f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts @@ -2,7 +2,7 @@ // // Device Tree file for LX2160AQDS // -// Copyright 2018 NXP +// Copyright 2018-2019 NXP /dts-v1/; @@ -29,12 +29,188 @@ regulator-boot-on; regulator-always-on; }; + + mdio-mux-1 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mux 0>; + mdio-parent-bus = <&emdio1>; + #address-cells=<1>; + #size-cells = <0>; + + mdio@0 { /* On-board PHY #1 RGMI1*/ + reg = <0x00>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@8 { /* On-board PHY #2 RGMI2*/ + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@18 { /* Slot #1 */ + reg = <0x18>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@19 { /* Slot #2 */ + reg = <0x19>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1a { /* Slot #3 */ + reg = <0x1a>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1b { /* Slot #4 */ + reg = <0x1b>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1c { /* Slot #5 */ + reg = <0x1c>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1d { /* Slot #6 */ + reg = <0x1d>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1e { /* Slot #7 */ + reg = <0x1e>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1f { /* Slot #8 */ + reg = <0x1f>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + mdio-mux-2 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mux 1>; + mdio-parent-bus = <&emdio2>; + #address-cells=<1>; + #size-cells = <0>; + + mdio@0 { /* Slot #1 (secondary EMI) */ + reg = <0x00>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1 { /* Slot #2 (secondary EMI) */ + reg = <0x01>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@2 { /* Slot #3 (secondary EMI) */ + reg = <0x02>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@3 { /* Slot #4 (secondary EMI) */ + reg = <0x03>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@4 { /* Slot #5 (secondary EMI) */ + reg = <0x04>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@5 { /* Slot #6 (secondary EMI) */ + reg = <0x05>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@6 { /* Slot #7 (secondary EMI) */ + reg = <0x06>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@7 { /* Slot #8 (secondary EMI) */ + reg = <0x07>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; }; &crypto { status = "okay"; }; +&dspi0 { + status = "okay"; + + dflash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <1000000>; + }; +}; + +&dspi1 { + status = "okay"; + + dflash1: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <1000000>; + }; +}; + +&dspi2 { + status = "okay"; + + dflash2: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <1000000>; + }; +}; + +&emdio1 { + status = "okay"; +}; + +&emdio2 { + status = "okay"; +}; + &esdhc0 { status = "okay"; }; @@ -46,6 +222,19 @@ &i2c0 { status = "okay"; + fpga@66 { + compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c", + "simple-mfd"; + reg = <0x66>; + + mux: mux-controller { + compatible = "reg-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */ + <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */ + }; + }; + i2c-mux@77 { compatible = "nxp,pca9547"; reg = <0x77>; @@ -126,3 +315,19 @@ &usb1 { status = "okay"; }; + +&sata0 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +&sata3 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts index c2817b784232dc..2ec43c6fbc9883 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts @@ -2,7 +2,7 @@ // // Device Tree file for LX2160ARDB // -// Copyright 2018 NXP +// Copyright 2018-2019 NXP /dts-v1/; @@ -31,10 +31,34 @@ }; }; +&can0 { + status = "okay"; + + can-transceiver { + max-bitrate = <5000000>; + }; +}; + +&can1 { + status = "okay"; + + can-transceiver { + max-bitrate = <5000000>; + }; +}; + &crypto { status = "okay"; }; +&emdio1 { + status = "okay"; +}; + +&emdio2 { + status = "okay"; +}; + &esdhc0 { sd-uhs-sdr104; sd-uhs-sdr50; @@ -159,3 +183,65 @@ &usb1 { status = "okay"; }; + +&emdio1 { + rgmii_phy1: ethernet-phy@1 { + /* AR8035 PHY - "compatible" property not strictly needed */ + compatible = "ethernet-phy-id004d.d072"; + reg = <0x1>; + /* Poll mode - no "interrupts" property defined */ + }; + rgmii_phy2: ethernet-phy@2 { + /* AR8035 PHY - "compatible" property not strictly needed */ + compatible = "ethernet-phy-id004d.d072"; + reg = <0x2>; + /* Poll mode - no "interrupts" property defined */ + }; + aquantia_phy1: ethernet-phy@4 { + /* AQR107 PHY - "compatible" property not strictly needed */ + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = ; + reg = <0x4>; + }; + aquantia_phy2: ethernet-phy@5 { + /* AQR107 PHY - "compatible" property not strictly needed */ + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = ; + reg = <0x5>; + }; +}; + +&emdio2 { + inphi_phy: ethernet-phy@0 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x0>; + }; +}; + +&dpmac3 { + phy-handle = <&aquantia_phy1>; + phy-connection-type = "usxgmii"; +}; + +&dpmac4 { + phy-handle = <&aquantia_phy2>; + phy-connection-type = "usxgmii"; +}; + +&dpmac5 { + phy-handle = <&inphi_phy>; +}; + +&dpmac6 { + phy-handle = <&inphi_phy>; +}; + +&dpmac17 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-id"; +}; + +&dpmac18 { + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii-id"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index b032f3890c8c61..cab7468c3df0ef 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -2,10 +2,11 @@ // // Device Tree Include file for Layerscape-LX2160A family SoC. // -// Copyright 2018 NXP +// Copyright 2018-2019 NXP #include #include +#include /memreserve/ 0x80000000 0x00010000; @@ -15,12 +16,16 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + rtc1 = &ftm_alarm0; + }; + cpus { #address-cells = <1>; #size-cells = <0>; // 8 clusters having 2 Cortex-A72 cores each - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -34,9 +39,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster0_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -50,9 +56,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster0_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@100 { + cpu100: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -66,9 +73,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster1_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@101 { + cpu101: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -82,9 +90,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster1_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@200 { + cpu200: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -98,9 +107,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster2_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@201 { + cpu201: cpu@201 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -114,9 +124,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster2_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@300 { + cpu300: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -130,9 +141,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster3_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@301 { + cpu301: cpu@301 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -146,9 +158,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster3_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@400 { + cpu400: cpu@400 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -162,9 +175,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster4_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@401 { + cpu401: cpu@401 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -178,9 +192,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster4_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@500 { + cpu500: cpu@500 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -194,9 +209,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster5_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@501 { + cpu501: cpu@501 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -210,9 +226,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster5_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@600 { + cpu600: cpu@600 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -226,9 +243,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster6_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@601 { + cpu601: cpu@601 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -242,9 +260,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster6_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@700 { + cpu700: cpu@700 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -258,9 +277,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster7_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@701 { + cpu701: cpu@701 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -274,6 +294,7 @@ i-cache-sets = <192>; next-level-cache = <&cluster7_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; cluster0_l2: l2-cache0 { @@ -418,6 +439,51 @@ clock-output-names = "sysclk"; }; + thermal-zones { + core_thermal1: core-thermal1 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 0>; + + trips { + core_cluster_alert: core-cluster-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + core_cluster_crit: core-cluster-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&core_cluster_alert>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -478,6 +544,28 @@ little-endian; }; + /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */ + emdio1: mdio@8b96000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8b96000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + little-endian; /* force the driver in LE mode */ + status = "disabled"; + }; + + /* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */ + emdio2: mdio@8b97000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8b97000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + little-endian; /* force the driver in LE mode */ + status = "disabled"; + }; + i2c0: i2c@2000000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; @@ -486,7 +574,7 @@ interrupts = ; clock-names = "i2c"; clocks = <&clockgen 4 15>; - scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; status = "disabled"; }; @@ -531,7 +619,7 @@ interrupts = ; clock-names = "i2c"; clocks = <&clockgen 4 15>; - scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; status = "disabled"; }; @@ -581,6 +669,45 @@ status = "disabled"; }; + dspi0: spi@2100000 { + compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen 4 7>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <0>; + status = "disabled"; + }; + + dspi1: spi@2110000 { + compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2110000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen 4 7>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <1>; + status = "disabled"; + }; + + dspi2: spi@2120000 { + compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2120000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen 4 7>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <2>; + status = "disabled"; + }; + esdhc0: esdhc@2140000 { compatible = "fsl,esdhc"; reg = <0x0 0x2140000 0x0 0x10000>; @@ -606,6 +733,38 @@ status = "disabled"; }; + can0: can@2180000 { + compatible = "fsl,lx2160ar1-flexcan"; + reg = <0x0 0x2180000 0x0 0x10000>; + interrupts = ; + clocks = <&sysclk>, <&clockgen 4 7>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can1: can@2190000 { + compatible = "fsl,lx2160ar1-flexcan"; + reg = <0x0 0x2190000 0x0 0x10000>; + interrupts = ; + clocks = <&sysclk>, <&clockgen 4 7>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + tmu: tmu@1f80000 { + compatible = "fsl,qoriq-tmu"; + reg = <0x0 0x1f80000 0x0 0x10000>; + interrupts = <0 23 0x4>; + fsl,tmu-range = <0x800000E6 0x8001017D>; + fsl,tmu-calibration = + /* Calibration data group 1 */ + <0x00000000 0x00000035 + /* Calibration data group 2 */ + 0x00010001 0x00000154>; + little-endian; + #thermal-sensor-cells = <1>; + }; + uart0: serial@21c0000 { compatible = "arm,sbsa-uart","arm,pl011"; reg = <0x0 0x21c0000 0x0 0x1000>; @@ -690,25 +849,46 @@ timeout-sec = <30>; }; + rcpm: rcpm@1e34040 { + compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+"; + reg = <0x0 0x1e34040 0x0 0x1c>; + #fsl,rcpm-wakeup-cells = <7>; + little-endian; + }; + + ftm_alarm0: timer@2800000 { + compatible = "fsl,lx2160a-ftm-alarm"; + reg = <0x0 0x2800000 0x0 0x10000>; + fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; + interrupts = <0 44 4>; + }; + usb0: usb@3100000 { - compatible = "snps,dwc3"; + compatible = "fsl,lx2160a-dwc3", "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = ; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; + usb3-lpm-capable; + snps,dis-u1u2-when-u3-quirk; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; + dma-coherent; status = "disabled"; }; usb1: usb@3110000 { - compatible = "snps,dwc3"; + compatible = "fsl,lx2160a-dwc3", "snps,dwc3"; reg = <0x0 0x3110000 0x0 0x10000>; interrupts = ; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; + usb3-lpm-capable; + snps,dis-u1u2-when-u3-quirk; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; status = "disabled"; }; @@ -756,6 +936,230 @@ status = "disabled"; }; + pcie@3400000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x80 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie_ep@3400000 { + compatible = "fsl,lx2160a-pcie-ep"; + reg = <0x00 0x03400000 0x0 0x00100000 + 0x80 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <256>; + status = "disabled"; + }; + + pcie@3500000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ + 0x88 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie_ep@3500000 { + compatible = "fsl,lx2160a-pcie-ep"; + reg = <0x00 0x03500000 0x0 0x00100000 + 0x88 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <256>; + status = "disabled"; + }; + + pcie@3600000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ + 0x90 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie_ep@3600000 { + compatible = "fsl,lx2160a-pcie-ep"; + reg = <0x00 0x03600000 0x0 0x00100000 + 0x90 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <256>; + max-functions = <2>; + status = "disabled"; + }; + + pcie@3700000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ + 0x98 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie_ep@3700000 { + compatible = "fsl,lx2160a-pcie-ep"; + reg = <0x00 0x03700000 0x0 0x00100000 + 0x98 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <256>; + status = "disabled"; + }; + + pcie@3800000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ + 0xa0 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie_ep@3800000 { + compatible = "fsl,lx2160a-pcie-ep"; + reg = <0x00 0x03800000 0x0 0x00100000 + 0xa0 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <256>; + max-functions = <2>; + status = "disabled"; + }; + + pcie@3900000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ + 0xa8 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie_ep@3900000 { + compatible = "fsl,lx2160a-pcie-ep"; + reg = <0x00 0x03900000 0x0 0x00100000 + 0xa8 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <256>; + status = "disabled"; + }; + smmu: iommu@5000000 { compatible = "arm,mmu-500"; reg = <0 0x5000000 0 0x800000>; @@ -978,4 +1382,11 @@ }; }; }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-tmu-map1.dtsi b/arch/arm64/boot/dts/freescale/fsl-tmu-map1.dtsi new file mode 100644 index 00000000000000..87e0d2ea587969 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-tmu-map1.dtsi @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Thermal Monitor Unit. + * + * Copyright 2018 NXP + * + * Tang Yuantian + * + */ + +&thermal_zones { + thermal-zone0 { + cooling-maps { + map1 { + trip = <&alert0>; + cooling-device = + <&cooling_map1 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone1 { + cooling-maps { + map1 { + trip = <&alert1>; + cooling-device = + <&cooling_map1 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone2 { + cooling-maps { + map1 { + trip = <&alert2>; + cooling-device = + <&cooling_map1 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone3 { + cooling-maps { + map1 { + trip = <&alert3>; + cooling-device = + <&cooling_map1 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone4 { + cooling-maps { + map1 { + trip = <&alert4>; + cooling-device = + <&cooling_map1 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone5 { + cooling-maps { + map1 { + trip = <&alert5>; + cooling-device = + <&cooling_map1 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone6 { + cooling-maps { + map1 { + trip = <&alert6>; + cooling-device = + <&cooling_map1 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone7 { + cooling-maps { + map1 { + trip = <&alert7>; + cooling-device = + <&cooling_map1 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-tmu-map2.dtsi b/arch/arm64/boot/dts/freescale/fsl-tmu-map2.dtsi new file mode 100644 index 00000000000000..7e350736821c2d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-tmu-map2.dtsi @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Thermal Monitor Unit. + * + * Copyright 2018 NXP + * + * Tang Yuantian + * + */ + +&thermal_zones { + thermal-zone0 { + cooling-maps { + map2 { + trip = <&alert0>; + cooling-device = + <&cooling_map2 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone1 { + cooling-maps { + map2 { + trip = <&alert1>; + cooling-device = + <&cooling_map2 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone2 { + cooling-maps { + map2 { + trip = <&alert2>; + cooling-device = + <&cooling_map2 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone3 { + cooling-maps { + map2 { + trip = <&alert3>; + cooling-device = + <&cooling_map2 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone4 { + cooling-maps { + map2 { + trip = <&alert4>; + cooling-device = + <&cooling_map2 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone5 { + cooling-maps { + map2 { + trip = <&alert5>; + cooling-device = + <&cooling_map2 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone6 { + cooling-maps { + map2 { + trip = <&alert6>; + cooling-device = + <&cooling_map2 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone7 { + cooling-maps { + map2 { + trip = <&alert7>; + cooling-device = + <&cooling_map2 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-tmu-map3.dtsi b/arch/arm64/boot/dts/freescale/fsl-tmu-map3.dtsi new file mode 100644 index 00000000000000..dcde9432fd2a4a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-tmu-map3.dtsi @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Thermal Monitor Unit. + * + * Copyright 2018 NXP + * + * Tang Yuantian + * + */ + +&thermal_zones { + thermal-zone0 { + cooling-maps { + map3 { + trip = <&alert0>; + cooling-device = + <&cooling_map3 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone1 { + cooling-maps { + map3 { + trip = <&alert1>; + cooling-device = + <&cooling_map3 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone2 { + cooling-maps { + map3 { + trip = <&alert2>; + cooling-device = + <&cooling_map3 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone3 { + cooling-maps { + map3 { + trip = <&alert3>; + cooling-device = + <&cooling_map3 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone4 { + cooling-maps { + map3 { + trip = <&alert4>; + cooling-device = + <&cooling_map3 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone5 { + cooling-maps { + map3 { + trip = <&alert5>; + cooling-device = + <&cooling_map3 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone6 { + cooling-maps { + map3 { + trip = <&alert6>; + cooling-device = + <&cooling_map3 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone7 { + cooling-maps { + map3 { + trip = <&alert7>; + cooling-device = + <&cooling_map3 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-tmu.dtsi b/arch/arm64/boot/dts/freescale/fsl-tmu.dtsi new file mode 100644 index 00000000000000..133d2dc8e61bb3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-tmu.dtsi @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Thermal Monitor Unit. + * + * Copyright 2018 NXP + * + * Tang Yuantian + * + */ + +thermal_zones: thermal-zones { + thermal_zone0: thermal-zone0 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 0>; + status = "disabled"; + + trips { + alert0: alert0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + crit0: crit0 { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&alert0>; + cooling-device = + <&cooling_map0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone1 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 1>; + status = "disabled"; + + trips { + alert1: alert1 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + crit1: crit1 { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&alert1>; + cooling-device = + <&cooling_map0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone2 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 2>; + status = "disabled"; + + trips { + alert2: alert2 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + crit2: crit2 { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&alert2>; + cooling-device = + <&cooling_map0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone3 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 3>; + status = "disabled"; + + trips { + alert3: alert3 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + crit3: crit3 { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&alert3>; + cooling-device = + <&cooling_map0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone4 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 4>; + status = "disabled"; + + trips { + alert4: alert4 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + crit4: crit4 { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&alert4>; + cooling-device = + <&cooling_map0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone5 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 5>; + status = "disabled"; + + trips { + alert5: alert5 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + crit5: crit5 { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&alert5>; + cooling-device = + <&cooling_map0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone6 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 6>; + status = "disabled"; + + trips { + alert6: alert6 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + crit6: crit6 { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&alert6>; + cooling-device = + <&cooling_map0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone7 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 7>; + status = "disabled"; + + trips { + alert7: alert7 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + crit7: crit7 { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&alert7>; + cooling-device = + <&cooling_map0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi new file mode 100644 index 00000000000000..841758bd2c8cd1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng + */ + +#include "imx8-ss-audio.dtsi" +#include "imx8-ss-dma.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi new file mode 100644 index 00000000000000..8698c5566e9308 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi @@ -0,0 +1,668 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + * Dong Aisheng + */ + +#include + +audio_subsys: bus@59000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x59000000 0x0 0x59000000 0x1000000>; + + audio_ipg_clk: clock-audio-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <175000000>; + clock-output-names = "audio_ipg_clk"; + }; + + edma0: dma-controller@591F0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x59200000 0x10000>, /* asrc0 */ + <0x59210000 0x10000>, + <0x59220000 0x10000>, + <0x59230000 0x10000>, + <0x59240000 0x10000>, + <0x59250000 0x10000>, + <0x59260000 0x10000>, /* esai0 rx */ + <0x59270000 0x10000>, /* esai0 tx */ + <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x592e0000 0x10000>, /* sai1 rx */ + <0x592f0000 0x10000>, /* sai1 tx */ + <0x59300000 0x10000>, /* sai2 rx */ + <0x59310000 0x10000>, /* sai3 rx */ + <0x59350000 0x10000>, + <0x59370000 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <18>; + interrupts = , /* asrc 0 */ + , + , + , + , + , + , /* esai0 */ + , + , /* spdif0 */ + , + , /* sai0 */ + , + , /* sai1 */ + , + , /* sai2 */ + , /* sai3 */ + , + ; + interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* asrc0 */ + "edma0-chan2-rx", "edma0-chan3-tx", + "edma0-chan4-tx", "edma0-chan5-tx", + "edma0-chan6-rx", "edma0-chan7-tx", /* esai0 */ + "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ + "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ + "edma0-chan16-rx", "edma0-chan17-rx", /* sai2, sai3 */ + "edma0-chan21-tx", /* gpt5 */ + "edma0-chan23-rx"; /* gpt7 */ + power-domains = <&pd IMX_SC_R_DMA_0_CH0>, + <&pd IMX_SC_R_DMA_0_CH1>, + <&pd IMX_SC_R_DMA_0_CH2>, + <&pd IMX_SC_R_DMA_0_CH3>, + <&pd IMX_SC_R_DMA_0_CH4>, + <&pd IMX_SC_R_DMA_0_CH5>, + <&pd IMX_SC_R_DMA_0_CH6>, + <&pd IMX_SC_R_DMA_0_CH7>, + <&pd IMX_SC_R_DMA_0_CH8>, + <&pd IMX_SC_R_DMA_0_CH9>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>, + <&pd IMX_SC_R_DMA_0_CH16>, + <&pd IMX_SC_R_DMA_0_CH17>, + <&pd IMX_SC_R_DMA_0_CH21>, + <&pd IMX_SC_R_DMA_0_CH23>; + power-domain-names = "edma0-chan0", "edma0-chan1", + "edma0-chan2", "edma0-chan3", + "edma0-chan4", "edma0-chan5", + "edma0-chan6", "edma0-chan7", + "edma0-chan8", "edma0-chan9", + "edma0-chan12", "edma0-chan13", + "edma0-chan14", "edma0-chan15", + "edma0-chan16", "edma0-chan17", + "edma0-chan21", "edma0-chan23"; + status = "okay"; + }; + + edma1: dma-controller@599F0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x59A00000 0x10000>, /* asrc1 */ + <0x59A10000 0x10000>, + <0x59A20000 0x10000>, + <0x59A30000 0x10000>, + <0x59A40000 0x10000>, + <0x59A50000 0x10000>, + <0x59A80000 0x10000>, /* sai4 rx */ + <0x59A90000 0x10000>, /* sai4 tx */ + <0x59AA0000 0x10000>; /* sai5 tx */ + #dma-cells = <3>; + shared-interrupt; + dma-channels = <9>; + interrupts = , /* asrc 1 */ + , + , + , + , + , + , /* sai4 */ + , + ; /* sai5 */ + interrupt-names = "edma1-chan0-rx", "edma1-chan1-rx", /* asrc1 */ + "edma1-chan2-rx", "edma1-chan3-tx", + "edma1-chan4-tx", "edma1-chan5-tx", + "edma1-chan8-rx", "edma1-chan9-tx", /* sai4 */ + "edma1-chan10-tx"; /* sai5 */ + power-domains = <&pd IMX_SC_R_DMA_1_CH0>, + <&pd IMX_SC_R_DMA_1_CH1>, + <&pd IMX_SC_R_DMA_1_CH2>, + <&pd IMX_SC_R_DMA_1_CH3>, + <&pd IMX_SC_R_DMA_1_CH4>, + <&pd IMX_SC_R_DMA_1_CH5>, + <&pd IMX_SC_R_DMA_1_CH8>, + <&pd IMX_SC_R_DMA_1_CH9>, + <&pd IMX_SC_R_DMA_1_CH10>; + power-domain-names = "edma1-chan0", "edma1-chan1", + "edma1-chan2", "edma1-chan3", + "edma1-chan4", "edma1-chan5", + "edma1-chan8", "edma1-chan9", + "edma1-chan10"; + status = "okay"; + }; + + acm: acm@59e00000 { + compatible = "nxp,imx8qxp-acm"; + reg = <0x59e00000 0x1D0000>; + #clock-cells = <1>; + power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_MCLK_OUT_0>, + <&pd IMX_SC_R_MCLK_OUT_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_ASRC_1>, + <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_SAI_0>, + <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_SAI_2>, + <&pd IMX_SC_R_SAI_3>, + <&pd IMX_SC_R_SAI_4>, + <&pd IMX_SC_R_SAI_5>, + <&pd IMX_SC_R_SPDIF_0>, + <&pd IMX_SC_R_MQS_0>; + }; + + asrc0: asrc@59000000 { + compatible = "fsl,imx8qm-asrc0"; + reg = <0x59000000 0x10000>; + interrupts = , + ; + clocks = <&asrc0_lpcg 0>, + <&asrc0_lpcg 0>, + <&aud_pll_div0_lpcg 0>, + <&aud_pll_div1_lpcg 0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "ipg", "mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma0 0 0 0>, <&edma0 1 0 0>, <&edma0 2 0 0>, + <&edma0 3 0 1>, <&edma0 4 0 1>, <&edma0 5 0 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + power-domains = <&pd IMX_SC_R_ASRC_0>; + status = "disabled"; + }; + + esai0: esai@59010000 { + compatible = "fsl,imx8qm-esai", "fsl,imx6ull-esai"; + reg = <0x59010000 0x10000>; + interrupts = ; + clocks = <&esai0_lpcg 1>, + <&esai0_lpcg 0>, + <&esai0_lpcg 1>, + <&clk_dummy>; + clock-names = "core", "extal", "fsys", "spba"; + dmas = <&edma0 6 0 1>, <&edma0 7 0 0>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_ESAI_0>; + status = "disabled"; + }; + + spdif0: spdif@59020000 { + compatible = "fsl,imx8qm-spdif"; + reg = <0x59020000 0x10000>; + interrupts = , /* rx */ + ; /* tx */ + clocks = <&spdif0_lpcg 1>, /* core */ + <&clk_dummy>, /* rxtx0 */ + <&spdif0_lpcg 0>, /* rxtx1 */ + <&clk_dummy>, /* rxtx2 */ + <&clk_dummy>, /* rxtx3 */ + <&clk_dummy>, /* rxtx4 */ + <&audio_ipg_clk>, /* rxtx5 */ + <&clk_dummy>, /* rxtx6 */ + <&clk_dummy>, /* rxtx7 */ + <&clk_dummy>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&edma0 8 0 5>, <&edma0 9 0 4>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_SPDIF_0>; + status = "disabled"; + }; + + spdif1: spdif@59030000 { + compatible = "fsl,imx8qm-spdif"; + reg = <0x59030000 0x10000>; + interrupts = , /* rx */ + ; /* tx */ + clocks = <&spdif1_lpcg 1>, /* core */ + <&clk_dummy>, /* rxtx0 */ + <&spdif1_lpcg 0>, /* rxtx1 */ + <&clk_dummy>, /* rxtx2 */ + <&clk_dummy>, /* rxtx3 */ + <&clk_dummy>, /* rxtx4 */ + <&audio_ipg_clk>, /* rxtx5 */ + <&clk_dummy>, /* rxtx6 */ + <&clk_dummy>, /* rxtx7 */ + <&clk_dummy>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&edma0 10 0 5>, <&edma0 11 0 4>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_SPDIF_1>; + status = "disabled"; + }; + + sai0: sai@59040000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59040000 0x10000>; + interrupts = ; + clocks = <&sai0_lpcg 1>, + <&clk_dummy>, + <&sai0_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma0 12 0 1>, <&edma0 13 0 0>; + power-domains = <&pd IMX_SC_R_SAI_0>; + status = "disabled"; + }; + + sai1: sai@59050000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59050000 0x10000>; + interrupts = ; + clocks = <&sai1_lpcg 1>, + <&clk_dummy>, + <&sai1_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma0 14 0 1>, <&edma0 15 0 0>; + power-domains = <&pd IMX_SC_R_SAI_1>; + status = "disabled"; + }; + + sai2: sai@59060000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59060000 0x10000>; + interrupts = ; + clocks = <&sai2_lpcg 1>, + <&clk_dummy>, + <&sai2_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma0 16 0 1>; + power-domains = <&pd IMX_SC_R_SAI_2>; + status = "disabled"; + }; + + sai3: sai@59070000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59070000 0x10000>; + interrupts = ; + clocks = <&sai3_lpcg 1>, + <&clk_dummy>, + <&sai3_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma0 17 0 1>; + power-domains = <&pd IMX_SC_R_SAI_3>; + status = "disabled"; + }; + + asrc1: asrc@59800000 { + compatible = "fsl,imx8qm-asrc1"; + reg = <0x59800000 0x10000>; + interrupts = , + ; + clocks = <&asrc1_lpcg 0>, + <&asrc1_lpcg 0>, + <&aud_pll_div0_lpcg 0>, + <&aud_pll_div1_lpcg 0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "ipg", "mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma1 0 0 0>, <&edma1 1 0 0>, <&edma1 2 0 0>, + <&edma1 3 0 1>, <&edma1 4 0 1>, <&edma1 5 0 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + power-domains = <&pd IMX_SC_R_ASRC_1>; + status = "disabled"; + }; + + sai4: sai@59820000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59820000 0x10000>; + interrupts = ; + clocks = <&sai4_lpcg 1>, + <&clk_dummy>, + <&sai4_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma1 8 0 1>, <&edma1 9 0 0>; + power-domains = <&pd IMX_SC_R_SAI_4>; + status = "disabled"; + }; + + sai5: sai@59830000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59830000 0x10000>; + interrupts = ; + clocks = <&sai5_lpcg 1>, + <&clk_dummy>, + <&sai5_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "tx"; + dmas = <&edma1 10 0 0>; + power-domains = <&pd IMX_SC_R_SAI_5>; + status = "disabled"; + }; + + amix: amix@59840000 { + compatible = "fsl,imx8qm-audmix"; + reg = <0x59840000 0x10000>; + clocks = <&amix_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_AMIX>; + dais = <&sai4>, <&sai5>; + status = "disabled"; + }; + + mqs: mqs@59850000 { + compatible = "fsl,imx8qm-mqs"; + reg = <0x59850000 0x10000>; + clocks = <&mqs0_lpcg 1>, + <&mqs0_lpcg 0>; + clock-names = "core", "mclk"; + power-domains = <&pd IMX_SC_R_MQS_0>; + status = "disabled"; + }; + + asrc0_lpcg: clock-controller@59400000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59400000 0x10000>; + #clock-cells = <1>; + clocks = <&audio_ipg_clk>; + bit-offset = <16>; + clock-output-names = "asrc0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ASRC_0>; + }; + + esai0_lpcg: clock-controller@59410000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59410000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "esai0_lpcg_extal_clk", + "esai0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ESAI_0>; + }; + + spdif0_lpcg: clock-controller@59420000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59420000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "spdif0_lpcg_tx_clk", + "spdif0_lpcg_gclkw"; + power-domains = <&pd IMX_SC_R_SPDIF_0>; + }; + + spdif1_lpcg: clock-controller@59430000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59430000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "spdif1_lpcg_tx_clk", + "spdif1_lpcg_gclkw"; + power-domains = <&pd IMX_SC_R_SPDIF_1>; + status = "disabled"; + }; + + sai0_lpcg: clock-controller@59440000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59440000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI0_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "sai0_lpcg_mclk", + "sai0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_0>; + }; + + sai1_lpcg: clock-controller@59450000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59450000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI1_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "sai1_lpcg_mclk", + "sai1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_1>; + }; + + sai2_lpcg: clock-controller@59460000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59460000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI2_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "sai2_lpcg_mclk", + "sai2_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_2>; + }; + + sai3_lpcg: clock-controller@59470000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59470000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI3_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "sai3_lpcg_mclk", + "sai3_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_3>; + }; + + dsp_lpcg: clock-controller@59580000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59580000 0x10000>; + #clock-cells = <1>; + clocks = <&audio_ipg_clk>, + <&audio_ipg_clk>, + <&audio_ipg_clk>; + bit-offset = <16 20 28>; + clock-output-names = "dsp_lpcg_adb_aclk", + "dsp_lpcg_ipg_clk", + "dsp_lpcg_core_clk"; + power-domains = <&pd IMX_SC_R_DSP>; + }; + + dsp_ram_lpcg: clock-controller@59590000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59590000 0x10000>; + #clock-cells = <1>; + clocks = <&audio_ipg_clk>; + bit-offset = <16>; + clock-output-names = "dsp_ram_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_DSP_RAM>; + }; + + asrc1_lpcg: clock-controller@59c00000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c00000 0x10000>; + #clock-cells = <1>; + clocks = <&audio_ipg_clk>; + bit-offset = <16>; + clock-output-names = "asrc1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ASRC_1>; + }; + + sai4_lpcg: clock-controller@59c20000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c20000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "sai4_lpcg_mclk", + "sai4_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_4>; + }; + + sai5_lpcg: clock-controller@59c30000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c30000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "sai5_lpcg_mclk", + "sai5_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_5>; + }; + + amix_lpcg: clock-controller@59c40000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c40000 0x10000>; + #clock-cells = <1>; + clocks = <&audio_ipg_clk>; + bit-offset = <0>; + clock-output-names = "amix_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_AMIX>; + }; + + mqs0_lpcg: clock-controller@59c50000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c50000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_MQS_TX_CLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "mqs0_lpcg_mclk", + "mqs0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MQS_0>; + }; + + aud_rec0_lpcg: clock-controller@59d00000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d00000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; + bit-offset = <0>; + clock-output-names = "aud_rec_clk0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>; + }; + + aud_rec1_lpcg: clock-controller@59d10000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d10000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>; + bit-offset = <0>; + clock-output-names = "aud_rec_clk1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>; + }; + + aud_pll_div0_lpcg: clock-controller@59d20000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d20000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>; + bit-offset = <0>; + clock-output-names = "aud_pll_div_clk0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>; + }; + + aud_pll_div1_lpcg: clock-controller@59d30000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d30000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>; + bit-offset = <0>; + clock-output-names = "aud_pll_div_clk1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>; + }; + + mclkout0_lpcg: clock-controller@59d50000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d50000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_MCLKOUT0_SEL>; + bit-offset = <0>; + clock-output-names = "mclkout0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_MCLK_OUT_0>; + }; + + mclkout1_lpcg: clock-controller@59d60000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d60000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_MCLKOUT1_SEL>; + bit-offset = <0>; + clock-output-names = "mclkout1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_MCLK_OUT_1>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi new file mode 100644 index 00000000000000..850ba6115f047a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +#include + +cm40_subsys: bus@34000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x34000000 0x0 0x34000000 0x4000000>; + + cm40_ipg_clk: clock-cm40-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <132000000>; + clock-output-names = "cm40_ipg_clk"; + }; + + cm40_i2c: i2c@37230000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x37230000 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&cm40_intmux>; + clocks = <&cm40_i2c_lpcg 0>, + <&cm40_i2c_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_M4_0_I2C>; + status = "disabled"; + }; + + cm40_i2c_lpcg: clock-controller@37630000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x37630000 0x1000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>, + <&cm40_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "cm40_lpcg_i2c_clk", + "cm40_lpcg_i2c_ipg_clk"; + power-domains = <&pd IMX_SC_R_M4_0_I2C>; + }; + + cm40_intmux: intmux@37400000 { + compatible = "nxp,imx8qxp-intmux", "nxp,imx-intmux"; + reg = <0x37400000 0x1000>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&cm40_ipg_clk>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_M4_0_INTMUX>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi new file mode 100644 index 00000000000000..19c38af5563c27 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +#include + +cm41_subsys: bus@38000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x38000000 0x0 0x38000000 0x4000000>; + + cm41_ipg_clk: clock-cm41-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <132000000>; + clock-output-names = "cm41_ipg_clk"; + }; + + cm41_i2c: i2c@3b230000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x3b230000 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&cm41_intmux>; + clocks = <&cm41_i2c_lpcg 0>, + <&cm41_i2c_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_M4_1_I2C>; + status = "disabled"; + }; + + cm41_i2c_lpcg: clock-controller@3b630000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x3b630000 0x1000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>, + <&cm41_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "cm41_lpcg_i2c_clk", + "cm41_lpcg_i2c_ipg_clk"; + power-domains = <&pd IMX_SC_R_M4_1_I2C>; + }; + + cm41_intmux: intmux@3b400000 { + compatible = "nxp,imx8qxp-intmux", "nxp,imx-intmux"; + reg = <0x3b400000 0x1000>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&cm41_ipg_clk>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_M4_1_INTMUX>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi new file mode 100644 index 00000000000000..4eb51cad186d94 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -0,0 +1,398 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng + */ + +#include + +conn_subsys: bus@5b000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; + + conn_axi_clk: clock-conn-axi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <333333333>; + clock-output-names = "conn_axi_clk"; + }; + + conn_ahb_clk: clock-conn-ahb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <166666666>; + clock-output-names = "conn_ahb_clk"; + }; + + conn_ipg_clk: clock-conn-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <83333333>; + clock-output-names = "conn_ipg_clk"; + }; + + conn_bch_clk: clock-conn-bch { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "conn_bch_clk"; + }; + + usbotg1: usb@5b0d0000 { + compatible = "fsl,imx8qm-usb", "fsl,imx7ulp-usb", + "fsl,imx27-usb"; + reg = <0x5b0d0000 0x200>; + interrupt-parent = <&gic>; + interrupts = ; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc1 0>; + clocks = <&usb2_lpcg 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + power-domains = <&pd IMX_SC_R_USB_0>; + status = "disabled"; + }; + + usbmisc1: usbmisc@5b0d0200 { + #index-cells = <1>; + compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x5b0d0200 0x200>; + }; + + usbphy1: usbphy@0x5b100000 { + compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", + "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x5b100000 0x1000>; + clocks = <&usb2_lpcg 1>; + power-domains = <&pd IMX_SC_R_USB_0_PHY>; + status = "disabled"; + }; + + usdhc1: mmc@5b010000 { + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x5b010000 0x10000>; + clocks = <&sdhc0_lpcg 1>, + <&sdhc0_lpcg 0>, + <&sdhc0_lpcg 2>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <400000000>; + power-domains = <&pd IMX_SC_R_SDHC_0>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc2: mmc@5b020000 { + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x5b020000 0x10000>; + clocks = <&sdhc1_lpcg 1>, + <&sdhc1_lpcg 0>, + <&sdhc1_lpcg 2>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <200000000>; + power-domains = <&pd IMX_SC_R_SDHC_1>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc3: mmc@5b030000 { + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x5b030000 0x10000>; + clocks = <&sdhc2_lpcg 1>, + <&sdhc2_lpcg 0>, + <&sdhc2_lpcg 2>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <200000000>; + power-domains = <&pd IMX_SC_R_SDHC_2>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + fec1: ethernet@5b040000 { + reg = <0x5b040000 0x10000>; + interrupts = , + , + , + ; + clocks = <&enet0_lpcg 4>, + <&enet0_lpcg 2>, + <&enet0_lpcg 3>, + <&enet0_lpcg 0>, + <&enet0_lpcg 1>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; + assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; + assigned-clock-rates = <250000000>, <125000000>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + power-domains = <&pd IMX_SC_R_ENET_0>; + status = "disabled"; + }; + + fec2: ethernet@5b050000 { + reg = <0x5b050000 0x10000>; + interrupts = , + , + , + ; + clocks = <&enet1_lpcg 4>, + <&enet1_lpcg 2>, + <&enet1_lpcg 3>, + <&enet1_lpcg 0>, + <&enet1_lpcg 1>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; + assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>; + assigned-clock-rates = <250000000>, <125000000>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + power-domains = <&pd IMX_SC_R_ENET_1>; + status = "disabled"; + }; + + mlb: mlb@5b060000 { + compatible = "fsl,imx8qxp-mlb150"; + reg = <0x5B060000 0x10000>; + interrupt-parent = <&gic>; + interrupts = , + ; + clocks = <&mlb_lpcg 0>, + <&mlb_lpcg 1>, + <&mlb_lpcg 2>; + clock-names = "mlb", "hclk", "ipg"; + power-domains = <&pd IMX_SC_R_MLB_0>; + status = "disabled"; + }; + + usb3phynop1: usb3-phy { + compatible = "usb-nop-xceiv"; + clocks = <&usb3_lpcg 4>; + clock-names = "main_clk"; + power-domains = <&pd IMX_SC_R_USB_2_PHY>; + status = "disabled"; + }; + + usbotg3: usb3@5b110000 { + compatible = "Cadence,usb3"; + reg = <0x5B110000 0x10000>, + <0x5B130000 0x10000>, + <0x5B140000 0x10000>, + <0x5B160000 0x40000>, + <0x5B120000 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&usb3_lpcg 1>, + <&usb3_lpcg 0>, + <&usb3_lpcg 5>, + <&usb3_lpcg 2>, + <&usb3_lpcg 3>; + clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk", + "usb3_ipg_clk", "usb3_core_pclk"; + assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>, + <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <125000000>, <12000000>, <250000000>; + power-domains = <&pd IMX_SC_R_USB_2>; + cdns3,usbphy = <&usb3phynop1>; + status = "disabled"; + }; + + /* LPCG clocks */ + sdhc0_lpcg: clock-controller@5b200000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b200000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>, + <&conn_ipg_clk>, <&conn_axi_clk>; + bit-offset = <0 16 20>; + clock-output-names = "sdhc0_lpcg_per_clk", + "sdhc0_lpcg_ipg_clk", + "sdhc0_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_0>; + }; + + sdhc1_lpcg: clock-controller@5b210000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b210000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>, + <&conn_ipg_clk>, <&conn_axi_clk>; + bit-offset = <0 16 20>; + clock-output-names = "sdhc1_lpcg_per_clk", + "sdhc1_lpcg_ipg_clk", + "sdhc1_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_1>; + }; + + sdhc2_lpcg: clock-controller@5b220000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b220000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>, + <&conn_ipg_clk>, <&conn_axi_clk>; + bit-offset = <0 16 20>; + clock-output-names = "sdhc2_lpcg_per_clk", + "sdhc2_lpcg_ipg_clk", + "sdhc2_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_2>; + }; + + enet0_lpcg: clock-controller@5b230000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b230000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, + <&conn_axi_clk>, + <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>, + <&conn_ipg_clk>, + <&conn_ipg_clk>; + bit-offset = <0 4 8 12 16 20>; + clock-output-names = "enet0_lpcg_timer_clk", + "enet0_lpcg_txc_sampling_clk", + "enet0_lpcg_ahb_clk", + "enet0_lpcg_rgmii_txc_clk", + "enet0_lpcg_ipg_clk", + "enet0_lpcg_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_ENET_0>; + }; + + enet1_lpcg: clock-controller@5b240000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b240000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, + <&conn_axi_clk>, + <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>, + <&conn_ipg_clk>, + <&conn_ipg_clk>; + bit-offset = <0 4 8 12 16 20>; + clock-output-names = "enet1_lpcg_timer_clk", + "enet1_lpcg_txc_sampling_clk", + "enet1_lpcg_ahb_clk", + "enet1_lpcg_rgmii_txc_clk", + "enet1_lpcg_ipg_clk", + "enet1_lpcg_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_ENET_1>; + }; + + mlb_lpcg: clock-controller@5b260000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b260000 0x10000>; + #clock-cells = <1>; + clocks = <&conn_axi_clk>, + <&conn_axi_clk>, + <&conn_ipg_clk>; + bit-offset = <0 20 16>; + clock-output-names = "mlb_lpcg_clk", + "mlb_lpcg_hclk", + "mlb_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MLB_0>; + }; + + usb2_lpcg: clock-controller@5b270000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b270000 0x10000>; + #clock-cells = <1>; + clocks = <&conn_ahb_clk>, <&conn_ipg_clk>; + bit-offset = <24 28>; + clock-output-names = "usboh3_ahb_clk", + "usboh3_phy_ipg_clk"; + power-domains = <&pd IMX_SC_R_USB_0_PHY>; + }; + + usb3_lpcg: clock-controller@5b280000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b280000 0x10000>; + #clock-cells = <1>; + bit-offset = <0 4 16 20 24 28>; + clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>, + <&conn_ipg_clk>, + <&conn_ipg_clk>, + <&conn_ipg_clk>, + <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>; + clock-output-names = "usb3_app_clk", + "usb3_lpm_clk", + "usb3_ipg_clk", + "usb3_core_pclk", + "usb3_phy_clk", + "usb3_aclk"; + power-domains = <&pd IMX_SC_R_USB_2_PHY>; + }; + + rawnand_0_lpcg: clock-controller@5b290000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b290000 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>, + <&conn_axi_clk>, + <&conn_axi_clk>; + bit-offset = <0 4 16 20>; + clock-output-names = "bch_clk", + "gpmi_clk", + "gpmi_apb_clk", + "bch_apb_clk"; + power-domains = <&pd IMX_SC_R_NAND>; + }; + + rawnand_4_lpcg: clock-controller@5b290004 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b290004 0x10000>; + #clock-cells = <1>; + clocks = <&conn_axi_clk>; + bit-offset = <16>; + clock-output-names = "apbhdma_hclk"; + power-domains = <&pd IMX_SC_R_NAND>; + }; + + dma_apbh: dma-apbh@5b810000 { + compatible = "fsl,imx28-dma-apbh"; + reg = <0x5b810000 0x2000>; + interrupts = , + , + , + ; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&rawnand_4_lpcg 0>; + clock-names = "apbhdma_hclk"; + power-domains = <&pd IMX_SC_R_NAND>; + }; + + gpmi: gpmi-nand@5b812000{ + compatible = "fsl,imx8qxp-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x5b812000 0x2000>, <0x5b814000 0x2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = ; + interrupt-names = "bch"; + clocks = <&rawnand_0_lpcg 1>, + <&rawnand_0_lpcg 2>, + <&rawnand_0_lpcg 0>, + <&rawnand_0_lpcg 3>; + clock-names = "gpmi_clk", "gpmi_apb_clk", + "bch_clk", "bch_apb_clk"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + power-domains = <&pd IMX_SC_R_NAND>; + assigned-clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <50000000>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi new file mode 100644 index 00000000000000..eef051915fcc27 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi @@ -0,0 +1,487 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019,2020 NXP + */ + +dc0_subsys: bus@56000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x56000000 0x0 0x56000000 0x300000>; + + dc0_cfg_clk: clock-dc-cfg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "dc0_cfg_clk"; + }; + + dc0_axi_int_clk: clock-dc-axi-int { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "dc0_axi_int_clk"; + }; + + dc0_axi_ext_clk: clock-dc-axi-ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "dc0_axi_ext_clk"; + }; + + dc0_disp_lpcg: clock-controller@56010000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010000 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>; + bit-offset = <0 4>; + clock-output-names = "dc0_disp0_lpcg_clk", "dc0_disp1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_dpr0_lpcg: clock-controller@56010018 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010018 0x4>; + #clock-cells = <1>; + clocks = <&dc0_cfg_clk>, + <&dc0_axi_ext_clk>; + bit-offset = <16 20>; + clock-output-names = "dc0_dpr0_lpcg_apb_clk", + "dc0_dpr0_lpcg_b_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_rtram0_lpcg: clock-controller@5601001c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5601001c 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>; + bit-offset = <0>; + clock-output-names = "dc0_rtram0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + + dc0_prg0_lpcg: clock-controller@56010020 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010020 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg0_lpcg_rtram_clk", + "dc0_prg0_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_prg1_lpcg: clock-controller@56010024 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010024 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg1_lpcg_rtram_clk", + "dc0_prg1_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_prg2_lpcg: clock-controller@56010028 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010028 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg2_lpcg_rtram_clk", + "dc0_prg2_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_dpr1_lpcg: clock-controller@5601002c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5601002c 0x4>; + #clock-cells = <1>; + clocks = <&dc0_cfg_clk>, + <&dc0_axi_ext_clk>; + bit-offset = <16 20>; + clock-output-names = "dc0_dpr1_lpcg_apb_clk", + "dc0_dpr1_lpcg_b_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_rtram1_lpcg: clock-controller@56010030 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010030 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>; + bit-offset = <0>; + clock-output-names = "dc0_rtram1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_prg3_lpcg: clock-controller@56010034 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010034 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg3_lpcg_rtram_clk", + "dc0_prg3_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_prg4_lpcg: clock-controller@56010038 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010038 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg4_lpcg_rtram_clk", + "dc0_prg4_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_prg5_lpcg: clock-controller@5601003c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5601003c 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg5_lpcg_rtram_clk", + "dc0_prg5_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_prg6_lpcg: clock-controller@56010040 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010040 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg6_lpcg_rtram_clk", + "dc0_prg6_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_prg7_lpcg: clock-controller@56010044 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010044 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg7_lpcg_rtram_clk", + "dc0_prg7_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_prg8_lpcg: clock-controller@56010048 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010048 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg8_lpcg_rtram_clk", + "dc0_prg8_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_irqsteer: irqsteer@56000000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x56000000 0x10000>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&dc0_cfg_clk>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <512>; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_pc: pixel-combiner@56020000 { + compatible = "fsl,imx8qxp-pixel-combiner", + "fsl,imx8qm-pixel-combiner"; + reg = <0x56020000 0x10000>; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg1: prg@56040000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x56040000 0x10000>; + clocks = <&dc0_prg0_lpcg 0>, + <&dc0_prg0_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg2: prg@56050000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x56050000 0x10000>; + clocks = <&dc0_prg1_lpcg 0>, + <&dc0_prg1_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg3: prg@56060000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x56060000 0x10000>; + clocks = <&dc0_prg2_lpcg 0>, + <&dc0_prg2_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg4: prg@56070000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x56070000 0x10000>; + clocks = <&dc0_prg3_lpcg 0>, + <&dc0_prg3_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg5: prg@56080000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x56080000 0x10000>; + clocks = <&dc0_prg4_lpcg 0>, + <&dc0_prg4_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg6: prg@56090000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x56090000 0x10000>; + clocks = <&dc0_prg5_lpcg 0>, + <&dc0_prg5_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg7: prg@560a0000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x560a0000 0x10000>; + clocks = <&dc0_prg6_lpcg 0>, + <&dc0_prg6_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg8: prg@560b0000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x560b0000 0x10000>; + clocks = <&dc0_prg7_lpcg 0>, + <&dc0_prg7_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg9: prg@560c0000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x560c0000 0x10000>; + clocks = <&dc0_prg8_lpcg 0>, + <&dc0_prg8_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_dpr1_channel1: dpr-channel@560d0000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x560d0000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc0_prg1>; + clocks = <&dc0_dpr0_lpcg 0>, + <&dc0_dpr0_lpcg 1>, + <&dc0_rtram0_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_dpr1_channel2: dpr-channel@560e0000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x560e0000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc0_prg2>, <&dc0_prg1>; + clocks = <&dc0_dpr0_lpcg 0>, + <&dc0_dpr0_lpcg 1>, + <&dc0_rtram0_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_dpr1_channel3: dpr-channel@560f0000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x560f0000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc0_prg3>; + clocks = <&dc0_dpr0_lpcg 0>, + <&dc0_dpr0_lpcg 1>, + <&dc0_rtram0_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_dpr2_channel1: dpr-channel@56100000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x56100000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc0_prg4>, <&dc0_prg5>; + clocks = <&dc0_dpr1_lpcg 0>, + <&dc0_dpr1_lpcg 1>, + <&dc0_rtram1_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_dpr2_channel2: dpr-channel@56110000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x56110000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc0_prg6>, <&dc0_prg7>; + clocks = <&dc0_dpr1_lpcg 0>, + <&dc0_dpr1_lpcg 1>, + <&dc0_rtram1_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_dpr2_channel3: dpr-channel@56120000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x56120000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc0_prg8>, <&dc0_prg9>; + clocks = <&dc0_dpr1_lpcg 0>, + <&dc0_dpr1_lpcg 1>, + <&dc0_rtram1_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dpu1: dpu@56180000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x56180000 0x40000>; + interrupt-parent = <&dc0_irqsteer>; + interrupts = <448>, <449>, <450>, <64>, + <65>, <66>, <67>, <68>, + <69>, <70>, <193>, <194>, + <195>, <196>, <197>, <72>, + <73>, <74>, <75>, <76>, + <77>, <78>, <79>, <80>, + <81>, <199>, <200>, <201>, + <202>, <203>, <204>, <205>, + <206>, <207>, <208>, <5>, + <0>, <1>, <2>, <3>, + <4>, <82>, <83>, <84>, + <85>, <209>, <210>, <211>, + <212>; + interrupt-names = "store9_shdload", + "store9_framecomplete", + "store9_seqcomplete", + "extdst0_shdload", + "extdst0_framecomplete", + "extdst0_seqcomplete", + "extdst4_shdload", + "extdst4_framecomplete", + "extdst4_seqcomplete", + "extdst1_shdload", + "extdst1_framecomplete", + "extdst1_seqcomplete", + "extdst5_shdload", + "extdst5_framecomplete", + "extdst5_seqcomplete", + "disengcfg_shdload0", + "disengcfg_framecomplete0", + "disengcfg_seqcomplete0", + "framegen0_int0", + "framegen0_int1", + "framegen0_int2", + "framegen0_int3", + "sig0_shdload", + "sig0_valid", + "sig0_error", + "disengcfg_shdload1", + "disengcfg_framecomplete1", + "disengcfg_seqcomplete1", + "framegen1_int0", + "framegen1_int1", + "framegen1_int2", + "framegen1_int3", + "sig1_shdload", + "sig1_valid", + "sig1_error", + "reserved", + "cmdseq_error", + "comctrl_sw0", + "comctrl_sw1", + "comctrl_sw2", + "comctrl_sw3", + "framegen0_primsync_on", + "framegen0_primsync_off", + "framegen0_secsync_on", + "framegen0_secsync_off", + "framegen1_primsync_on", + "framegen1_primsync_off", + "framegen1_secsync_on", + "framegen1_secsync_off"; + clocks = <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_0_VIDEO0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>, + <&dc0_disp_lpcg 0>, <&dc0_disp_lpcg 1>; + clock-names = "pll0", "pll1", "bypass0", "disp0", "disp1", "disp0_lpcg", "disp1_lpcg"; + power-domains = <&pd IMX_SC_R_DC_0>, + <&pd IMX_SC_R_DC_0_PLL_0>, + <&pd IMX_SC_R_DC_0_PLL_1>; + power-domain-names = "dc", "pll0", "pll1"; + fsl,dpr-channels = <&dc0_dpr1_channel1>, + <&dc0_dpr1_channel2>, + <&dc0_dpr1_channel3>, + <&dc0_dpr2_channel1>, + <&dc0_dpr2_channel2>, + <&dc0_dpr2_channel3>; + fsl,pixel-combiner = <&dc0_pc>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi new file mode 100644 index 00000000000000..c05a3eb7f9e575 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi @@ -0,0 +1,488 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019,2020 NXP + */ + +dc1_subsys: bus@57000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x57000000 0x0 0x57000000 0x300000>; + + dc1_cfg_clk: clock-dc-cfg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "dc1_cfg_clk"; + }; + + dc1_axi_int_clk: clock-dc-axi-int { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "dc1_axi_int_clk"; + }; + + dc1_axi_ext_clk: clock-dc-axi-ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "dc1_axi_ext_clk"; + }; + + dc1_disp_lpcg: clock-controller@57010000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010000 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC1>; + bit-offset = <0 4>; + clock-output-names = "dc1_disp0_lpcg_clk", "dc1_disp1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_dpr0_lpcg: clock-controller@57010018 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010018 0x4>; + #clock-cells = <1>; + clocks = <&dc1_cfg_clk>, + <&dc1_axi_ext_clk>; + bit-offset = <16 20>; + clock-output-names = "dc1_dpr0_lpcg_apb_clk", + "dc1_dpr0_lpcg_b_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_rtram0_lpcg: clock-controller@5701001c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5701001c 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>; + bit-offset = <0>; + clock-output-names = "dc1_rtram0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + + dc1_prg0_lpcg: clock-controller@57010020 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010020 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg0_lpcg_rtram_clk", + "dc1_prg0_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_prg1_lpcg: clock-controller@57010024 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010024 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg1_lpcg_rtram_clk", + "dc1_prg1_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_prg2_lpcg: clock-controller@57010028 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010028 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg2_lpcg_rtram_clk", + "dc1_prg2_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_dpr1_lpcg: clock-controller@5701002c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5701002c 0x4>; + #clock-cells = <1>; + clocks = <&dc1_cfg_clk>, + <&dc1_axi_ext_clk>; + bit-offset = <16 20>; + clock-output-names = "dc1_dpr1_lpcg_apb_clk", + "dc1_dpr1_lpcg_b_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_rtram1_lpcg: clock-controller@57010030 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010030 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>; + bit-offset = <0>; + clock-output-names = "dc1_rtram1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_prg3_lpcg: clock-controller@57010034 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010034 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg3_lpcg_rtram_clk", + "dc1_prg3_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_prg4_lpcg: clock-controller@57010038 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010038 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg4_lpcg_rtram_clk", + "dc1_prg4_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_prg5_lpcg: clock-controller@5701003c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5701003c 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg5_lpcg_rtram_clk", + "dc1_prg5_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_prg6_lpcg: clock-controller@57010040 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010040 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg6_lpcg_rtram_clk", + "dc1_prg6_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_prg7_lpcg: clock-controller@57010044 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010044 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg7_lpcg_rtram_clk", + "dc1_prg7_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_prg8_lpcg: clock-controller@57010048 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010048 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg8_lpcg_rtram_clk", + "dc1_prg8_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_irqsteer: irqsteer@57000000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x57000000 0x10000>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&dc1_cfg_clk>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <512>; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_pc: pixel-combiner@57020000 { + compatible = "fsl,imx8qxp-pixel-combiner", + "fsl,imx8qm-pixel-combiner"; + reg = <0x57020000 0x10000>; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg1: prg@57040000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x57040000 0x10000>; + clocks = <&dc1_prg0_lpcg 0>, + <&dc1_prg0_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg2: prg@57050000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x57050000 0x10000>; + clocks = <&dc1_prg1_lpcg 0>, + <&dc1_prg1_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg3: prg@57060000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x57060000 0x10000>; + clocks = <&dc1_prg2_lpcg 0>, + <&dc1_prg2_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg4: prg@57070000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x57070000 0x10000>; + clocks = <&dc1_prg3_lpcg 0>, + <&dc1_prg3_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg5: prg@57080000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x57080000 0x10000>; + clocks = <&dc1_prg4_lpcg 0>, + <&dc1_prg4_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg6: prg@57090000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x57090000 0x10000>; + clocks = <&dc1_prg5_lpcg 0>, + <&dc1_prg5_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg7: prg@570a0000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x570a0000 0x10000>; + clocks = <&dc1_prg6_lpcg 0>, + <&dc1_prg6_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg8: prg@570b0000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x570b0000 0x10000>; + clocks = <&dc1_prg7_lpcg 0>, + <&dc1_prg7_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg9: prg@570c0000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x570c0000 0x10000>; + clocks = <&dc1_prg8_lpcg 0>, + <&dc1_prg8_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_dpr1_channel1: dpr-channel@570d0000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x570d0000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc1_prg1>; + clocks = <&dc1_dpr0_lpcg 0>, + <&dc1_dpr0_lpcg 1>, + <&dc1_rtram0_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_dpr1_channel2: dpr-channel@570e0000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x570e0000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc1_prg2>, <&dc1_prg1>; + clocks = <&dc1_dpr0_lpcg 0>, + <&dc1_dpr0_lpcg 1>, + <&dc1_rtram0_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_dpr1_channel3: dpr-channel@570f0000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x570f0000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc1_prg3>; + clocks = <&dc1_dpr0_lpcg 0>, + <&dc1_dpr0_lpcg 1>, + <&dc1_rtram0_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_dpr2_channel1: dpr-channel@57100000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x57100000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc1_prg4>, <&dc1_prg5>; + clocks = <&dc1_dpr1_lpcg 0>, + <&dc1_dpr1_lpcg 1>, + <&dc1_rtram1_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_dpr2_channel2: dpr-channel@57110000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x57110000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc1_prg6>, <&dc1_prg7>; + clocks = <&dc1_dpr1_lpcg 0>, + <&dc1_dpr1_lpcg 1>, + <&dc1_rtram1_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_dpr2_channel3: dpr-channel@57120000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x57120000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc1_prg8>, <&dc1_prg9>; + clocks = <&dc1_dpr1_lpcg 0>, + <&dc1_dpr1_lpcg 1>, + <&dc1_rtram1_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dpu2: dpu@57180000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x57180000 0x40000>; + interrupt-parent = <&dc1_irqsteer>; + interrupts = <448>, <449>, <450>, <64>, + <65>, <66>, <67>, <68>, + <69>, <70>, <193>, <194>, + <195>, <196>, <197>, <72>, + <73>, <74>, <75>, <76>, + <77>, <78>, <79>, <80>, + <81>, <199>, <200>, <201>, + <202>, <203>, <204>, <205>, + <206>, <207>, <208>, <5>, + <0>, <1>, <2>, <3>, + <4>, <82>, <83>, <84>, + <85>, <209>, <210>, <211>, + <212>; + interrupt-names = "store9_shdload", + "store9_framecomplete", + "store9_seqcomplete", + "extdst0_shdload", + "extdst0_framecomplete", + "extdst0_seqcomplete", + "extdst4_shdload", + "extdst4_framecomplete", + "extdst4_seqcomplete", + "extdst1_shdload", + "extdst1_framecomplete", + "extdst1_seqcomplete", + "extdst5_shdload", + "extdst5_framecomplete", + "extdst5_seqcomplete", + "disengcfg_shdload0", + "disengcfg_framecomplete0", + "disengcfg_seqcomplete0", + "framegen0_int0", + "framegen0_int1", + "framegen0_int2", + "framegen0_int3", + "sig0_shdload", + "sig0_valid", + "sig0_error", + "disengcfg_shdload1", + "disengcfg_framecomplete1", + "disengcfg_seqcomplete1", + "framegen1_int0", + "framegen1_int1", + "framegen1_int2", + "framegen1_int3", + "sig1_shdload", + "sig1_valid", + "sig1_error", + "reserved", + "cmdseq_error", + "comctrl_sw0", + "comctrl_sw1", + "comctrl_sw2", + "comctrl_sw3", + "framegen0_primsync_on", + "framegen0_primsync_off", + "framegen0_secsync_on", + "framegen0_secsync_off", + "framegen1_primsync_on", + "framegen1_primsync_off", + "framegen1_secsync_on", + "framegen1_secsync_off"; + clocks = <&clk IMX_SC_R_DC_1_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_1_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_1_VIDEO0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC1>, + <&dc1_disp_lpcg 0>, <&dc1_disp_lpcg 1>; + clock-names = "pll0", "pll1", "bypass0", "disp0", "disp1", "disp0_lpcg", "disp1_lpcg"; + power-domains = <&pd IMX_SC_R_DC_1>, + <&pd IMX_SC_R_DC_1_PLL_0>, + <&pd IMX_SC_R_DC_1_PLL_1>; + power-domain-names = "dc", "pll0", "pll1"; + fsl,dpr-channels = <&dc1_dpr1_channel1>, + <&dc1_dpr1_channel2>, + <&dc1_dpr1_channel3>, + <&dc1_dpr2_channel1>, + <&dc1_dpr2_channel2>, + <&dc1_dpr2_channel3>; + fsl,pixel-combiner = <&dc1_pc>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi new file mode 100644 index 00000000000000..89dd105b2c440b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +ddr_subsys: bus@5c000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; + + ddr_pmu0: ddr-pmu@5c020000 { + compatible = "fsl,imx8-ddr-pmu"; + reg = <0x5c020000 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi new file mode 100644 index 00000000000000..5e2cc27877168d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi @@ -0,0 +1,586 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + * Dong Aisheng + */ + +#include + +dma_subsys: bus@5a000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5a000000 0x0 0x5a000000 0x1000000>; + + dma_ipg_clk: clock-dma-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "dma_ipg_clk"; + }; + + lpspi0: spi@5a000000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x5a000000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&spi0_lpcg 0>, + <&spi0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <20000000>; + power-domains = <&pd IMX_SC_R_SPI_0>; + dma-names = "tx","rx"; + dmas = <&edma2 1 0 0>, <&edma2 0 0 1>; + status = "disabled"; + }; + + lpspi2: spi@5a020000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x5a020000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&spi2_lpcg 0>, + <&spi2_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <60000000>; + power-domains = <&pd IMX_SC_R_SPI_2>; + dma-names = "tx","rx"; + dmas = <&edma2 5 0 0>, <&edma2 4 0 1>; + status = "disabled"; + }; + + lpspi3: spi@5a030000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x5a030000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&spi3_lpcg 0>, + <&spi3_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <60000000>; + power-domains = <&pd IMX_SC_R_SPI_3>; + dma-names = "tx","rx"; + dmas = <&edma2 7 0 0>, <&edma2 6 0 1>; + status = "disabled"; + }; + + lpuart0: serial@5a060000 { + reg = <0x5a060000 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&uart0_lpcg 1>, <&uart0_lpcg 0>; + clock-names = "ipg", "baud"; + assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <80000000>; + power-domains = <&pd IMX_SC_R_UART_0>; + status = "disabled"; + }; + + lpuart1: serial@5a070000 { + reg = <0x5a070000 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&uart1_lpcg 1>, <&uart1_lpcg 0>; + clock-names = "ipg", "baud"; + assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <80000000>; + power-domains = <&pd IMX_SC_R_UART_1>; + power-domain-names = "uart"; + dma-names = "tx","rx"; + dmas = <&edma2 11 0 0>, + <&edma2 10 0 1>; + status = "disabled"; + }; + + lpuart2: serial@5a080000 { + reg = <0x5a080000 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&uart2_lpcg 1>, <&uart2_lpcg 0>; + clock-names = "ipg", "baud"; + assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <80000000>; + power-domains = <&pd IMX_SC_R_UART_2>; + power-domain-names = "uart"; + dma-names = "tx","rx"; + dmas = <&edma2 13 0 0>, + <&edma2 12 0 1>; + status = "disabled"; + }; + + lpuart3: serial@5a090000 { + reg = <0x5a090000 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&uart3_lpcg 1>, <&uart3_lpcg 0>; + clock-names = "ipg", "baud"; + assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <80000000>; + power-domains = <&pd IMX_SC_R_UART_3>; + power-domain-names = "uart"; + dma-names = "tx","rx"; + dmas = <&edma2 15 0 0>, + <&edma2 14 0 1>; + status = "disabled"; + }; + + emvsim0: sim0@5a0d0000 { + compatible = "fsl,imx8-emvsim"; + reg = <0x5a0d0000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&emvsim0_lpcg 0>, + <&emvsim0_lpcg 1>; + clock-names = "sim", "ipg"; + assigned-clocks = <&clk IMX_SC_R_EMVSIM_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_EMVSIM_0>, <&pd IMX_SC_R_BOARD_R2>; + power-domain-names = "sim_pd", "sim_aux_pd"; + status = "disabled"; + }; + + edma2: dma-controller@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x5a200000 0x10000>, /* channel0 LPSPI0 rx */ + <0x5a210000 0x10000>, /* channel1 LPSPI0 tx */ + <0x5a220000 0x10000>, /* channel2 LPSPI1 rx */ + <0x5a230000 0x10000>, /* channel3 LPSPI1 tx */ + <0x5a240000 0x10000>, /* channel4 LPSPI2 rx */ + <0x5a250000 0x10000>, /* channel5 LPSPI2 tx */ + <0x5a260000 0x10000>, /* channel6 LPSPI3 rx */ + <0x5a270000 0x10000>, /* channel7 LPSPI3 tx */ + <0x5a280000 0x10000>, /* channel8 UART0 rx */ + <0x5a290000 0x10000>, /* channel9 UART0 tx */ + <0x5a2a0000 0x10000>, /* channel10 UART1 rx */ + <0x5a2b0000 0x10000>, /* channel11 UART1 tx */ + <0x5a2c0000 0x10000>, /* channel12 UART2 rx */ + <0x5a2d0000 0x10000>, /* channel13 UART2 tx */ + <0x5a2e0000 0x10000>, /* channel14 UART3 rx */ + <0x5a2f0000 0x10000>; /* channel15 UART3 tx */ + #dma-cells = <3>; + dma-channels = <16>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "edma2-chan0-rx", "edma2-chan1-tx", + "edma2-chan2-rx", "edma2-chan3-tx", + "edma2-chan4-rx", "edma2-chan5-tx", + "edma2-chan6-rx", "edma2-chan7-tx", + "edma2-chan8-rx", "edma2-chan9-tx", + "edma2-chan10-rx", "edma2-chan11-tx", + "edma2-chan12-rx", "edma2-chan13-tx", + "edma2-chan14-rx", "edma2-chan15-tx"; + power-domains = <&pd IMX_SC_R_DMA_2_CH0>, + <&pd IMX_SC_R_DMA_2_CH1>, + <&pd IMX_SC_R_DMA_2_CH2>, + <&pd IMX_SC_R_DMA_2_CH3>, + <&pd IMX_SC_R_DMA_2_CH4>, + <&pd IMX_SC_R_DMA_2_CH5>, + <&pd IMX_SC_R_DMA_2_CH6>, + <&pd IMX_SC_R_DMA_2_CH7>, + <&pd IMX_SC_R_DMA_2_CH8>, + <&pd IMX_SC_R_DMA_2_CH9>, + <&pd IMX_SC_R_DMA_2_CH10>, + <&pd IMX_SC_R_DMA_2_CH11>, + <&pd IMX_SC_R_DMA_2_CH12>, + <&pd IMX_SC_R_DMA_2_CH13>, + <&pd IMX_SC_R_DMA_2_CH14>, + <&pd IMX_SC_R_DMA_2_CH15>; + power-domain-names = "edma2-chan0", "edma2-chan1", + "edma2-chan2", "edma2-chan3", + "edma2-chan4", "edma2-chan5", + "edma2-chan6", "edma2-chan7", + "edma2-chan8", "edma2-chan9", + "edma2-chan10", "edma2-chan11", + "edma2-chan12", "edma2-chan13", + "edma2-chan14", "edma2-chan15"; + status = "disabled"; + }; + + spi0_lpcg: clock-controller@5a400000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a400000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "spi0_lpcg_clk", + "spi0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_0>; + }; + + spi1_lpcg: clock-controller@5a410000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a410000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "spi1_lpcg_clk", + "spi1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_1>; + }; + + spi2_lpcg: clock-controller@5a420000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a420000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "spi2_lpcg_clk", + "spi2_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_2>; + }; + + spi3_lpcg: clock-controller@5a430000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a430000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "spi3_lpcg_clk", + "spi3_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_3>; + }; + + uart0_lpcg: clock-controller@5a460000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a460000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart0_lpcg_baud_clk", + "uart0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_UART_0>; + }; + + uart1_lpcg: clock-controller@5a470000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a470000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart1_lpcg_baud_clk", + "uart1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_UART_1>; + }; + + uart2_lpcg: clock-controller@5a480000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a480000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart2_lpcg_baud_clk", + "uart2_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_UART_2>; + }; + + uart3_lpcg: clock-controller@5a490000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a490000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart3_lpcg_baud_clk", + "uart3_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_UART_3>; + }; + + emvsim0_lpcg: clock-controller@5a4d0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a4d0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_EMVSIM_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "emvsim0_lpcg_clk", + "emvsim0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_EMVSIM_0>; + }; + + adc0: adc@5a880000 { + compatible = "fsl,imx8qxp-adc"; + reg = <0x5a880000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&adc0_lpcg 0>, + <&adc0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_ADC_0>; + status = "disabled"; + }; + + adc1: adc@5a890000 { + compatible = "fsl,imx8qxp-adc"; + reg = <0x5a890000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&adc1_lpcg 0>, + <&adc1_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_ADC_1>; + status = "disabled"; + }; + + + i2c0: i2c@5a800000 { + reg = <0x5a800000 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&i2c0_lpcg 0>, + <&i2c0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_0>; + status = "disabled"; + }; + + i2c1: i2c@5a810000 { + reg = <0x5a810000 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&i2c1_lpcg 0>, + <&i2c1_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_1>; + status = "disabled"; + }; + + i2c2: i2c@5a820000 { + reg = <0x5a820000 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&i2c2_lpcg 0>, + <&i2c2_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_2>; + status = "disabled"; + }; + + i2c3: i2c@5a830000 { + reg = <0x5a830000 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&i2c3_lpcg 0>, + <&i2c3_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_3>; + status = "disabled"; + }; + + flexcan1: can@5a8d0000 { + compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + reg = <0x5a8d0000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_0>; + /* SLSlice[4] */ + fsl,clk-source= <0>; + status = "disabled"; + }; + + flexcan2: can@5a8e0000 { + compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + reg = <0x5a8e0000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + /* CAN0 clock and PD is shared among all CAN instances as + * CAN1 shares CAN0's clock and to enable CAN0's clock it + * has to be powered on. + */ + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_1>; + /* SLSlice[4] */ + fsl,clk-source = <0>; + status = "disabled"; + }; + + flexcan3: can@5a8f0000 { + compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + reg = <0x5a8f0000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + /* CAN0 clock and PD is shared among all CAN instances as + * CAN2 shares CAN0's clock and to enable CAN0's clock it + * has to be powered on. + */ + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_2>; + /* SLSlice[4] */ + fsl,clk-source = <0>; + status = "disabled"; + }; + + adc0_lpcg: clock-controller@5ac80000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ac80000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "adc0_lpcg_clk", + "adc0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ADC_0>; + }; + + adc1_lpcg: clock-controller@5ac90000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ac90000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "adc1_lpcg_clk", + "adc1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ADC_1>; + }; + + i2c0_lpcg: clock-controller@5ac00000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ac00000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c0_lpcg_clk", + "i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_I2C_0>; + }; + + i2c1_lpcg: clock-controller@5ac10000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ac10000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c1_lpcg_clk", + "i2c1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_I2C_1>; + }; + + i2c2_lpcg: clock-controller@5ac20000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ac20000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c2_lpcg_clk", + "i2c2_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_I2C_2>; + }; + + i2c3_lpcg: clock-controller@5ac30000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ac30000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c3_lpcg_clk", + "i2c3_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_I2C_3>; + }; + + can0_lpcg: clock-controller@5acd0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5acd0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>, <&dma_ipg_clk>; + bit-offset = <0 16 20>; + clock-output-names = "can0_lpcg_pe_clk", + "can0_lpcg_ipg_clk", + "can0_lpcg_chi_clk"; + power-domains = <&pd IMX_SC_R_CAN_0>; + }; + + i2c_rpbus_0: i2c-rpbus-0 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_1: i2c-rpbus-1 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_5: i2c-rpbus-5 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_12: i2c-rpbus-12 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_13: i2c-rpbus-13 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_14: i2c-rpbus-14 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_15: i2c-rpbus-15 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi new file mode 100644 index 00000000000000..28aeeecb183239 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +#include + +gpu0_subsys: bus@53100000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x53100000 0x0 0x53100000 0x40000>, + <0x80000000 0x0 0x80000000 0x80000000>, + <0x0 0x0 0x0 0x10000000>; + + gpu_3d0: gpu@53100000 { + compatible = "fsl,imx8-gpu"; + reg = <0x53100000 0x40000>; + interrupts = ; + clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; + clock-names = "core", "shader"; + assigned-clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; + assigned-clock-rates = <700000000>, <850000000>; + power-domains = <&pd IMX_SC_R_GPU_0_PID0>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-gpu1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-gpu1.dtsi new file mode 100644 index 00000000000000..0e84e5199a8f44 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-gpu1.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +#include + +gpu1_subsys: bus@54100000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x54100000 0x0 0x54100000 0x40000>, + <0x80000000 0x0 0x80000000 0x80000000>, + <0x0 0x0 0x0 0x10000000>; + + gpu_3d1: gpu@54100000 { + compatible = "fsl,imx8-gpu"; + reg = <0x54100000 0x40000>; + interrupts = ; + clocks = <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_MISC>; + clock-names = "core", "shader"; + assigned-clocks = <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_MISC>; + assigned-clock-rates = <800000000>, <1000000000>; + fsl,sc_gpu_pid = ; + power-domains = <&pd IMX_SC_R_GPU_1_PID0>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi new file mode 100644 index 00000000000000..916b18bb925fd4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Richard Zhu + */ +#include + +hsio_subsys: bus@5f000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + /* Only supports up to 32bits DMA, map all possible DDR as inbound ranges */ + dma-ranges = <0x80000000 0 0x80000000 0x80000000>; + ranges = <0x5f000000 0x0 0x5f000000 0x21000000>; + + xtal100m: clock-xtal100m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "xtal_100MHz"; + }; + + hsio_refa_clk: clock-hsio-refa { + compatible = "gpio-gate-clock"; + clocks = <&xtal100m>; + #clock-cells = <0>; + enable-gpios = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>; + }; + + hsio_refb_clk: clock-hsio-refb { + compatible = "gpio-gate-clock"; + clocks = <&xtal100m>; + #clock-cells = <0>; + enable-gpios = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + }; + + hsio_axi_clk: clock-hsio-axi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "hsio_axi_clk"; + }; + + hsio_per_clk: clock-hsio-per { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133333333>; + clock-output-names = "hsio_per_clk"; + }; + + pcieb_lpcg: clock-controller@5f060000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f060000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_axi_clk>, <&hsio_axi_clk>, <&hsio_axi_clk>; + bit-offset = <16 20 24>; + clock-output-names = "hsio_pcieb_mstr_axi_clk", + "hsio_pcieb_slv_axi_clk", + "hsio_pcieb_dbi_axi_clk"; + power-domains = <&pd IMX_SC_R_PCIE_B>; + }; + + phyx1_crr1_lpcg: clock-controller@5f0b0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f0b0000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_per_clk>; + bit-offset = <16>; + clock-output-names = "hsio_phyx1_per_clk"; + power-domains = <&pd IMX_SC_R_SERDES_1>; + }; + + pcieb_crr3_lpcg: clock-controller@5f0d0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f0d0000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_per_clk>; + bit-offset = <16>; + clock-output-names = "hsio_pcieb_per_clk"; + power-domains = <&pd IMX_SC_R_PCIE_B>; + }; + + misc_crr5_lpcg: clock-controller@5f0f0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f0f0000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_per_clk>; + bit-offset = <16>; + clock-output-names = "hsio_misc_per_clk"; + power-domains = <&pd IMX_SC_R_HSIO_GPIO>; + }; + + pcieb: pcie@0x5f010000 { + compatible = "fsl,imx8qm-pcie","snps,dw-pcie"; + reg = <0x5f010000 0x10000>, /* Controller reg */ + <0x7ff00000 0x80000>, /* PCI cfg space */ + <0x5f080000 0xf0000>; /* lpcg, csr, msic, gpio */ + reg-names = "dbi", "config", "hsio"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x00000000 0x7ff80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x70000000 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + num-viewport = <4>; + interrupts = , + ; /* eDMA */ + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 105 4>, + <0 0 0 2 &gic 0 106 4>, + <0 0 0 3 &gic 0 107 4>, + <0 0 0 4 &gic 0 108 4>; + clocks = <&pcieb_lpcg 0>, + <&pcieb_lpcg 1>, + <&pcieb_lpcg 2>, + <&phyx1_lpcg 0>, + <&phyx1_crr1_lpcg 0>, + <&pcieb_crr3_lpcg 0>, + <&misc_crr5_lpcg 0>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", + "pcie_phy", "phy_per", "pcie_per", "misc_per"; + power-domains = <&pd IMX_SC_R_PCIE_B>, + <&pd IMX_SC_R_SERDES_1>, + <&pd IMX_SC_R_HSIO_GPIO>; + power-domain-names = "pcie", "pcie_phy", "hsio_gpio"; + fsl,max-link-speed = <3>; + hsio-cfg = ; + local-addr = <0x80000000>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi new file mode 100644 index 00000000000000..c7be9fdc4df090 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi @@ -0,0 +1,594 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019-2020 NXP + * Zhou Guoniu + */ +img_subsys: bus@58000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x58000000 0x0 0x58000000 0x1000000>; + + img_ipg_clk: clock-img-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "img_ipg_clk"; + }; + + img_axi_clk: clock-img-axi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "img_axi_clk"; + }; + + img_pxl_clk: clock-img-pxl { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + clock-output-names = "img_pxl_clk"; + }; + + csi0_core_lpcg: clock-controller@58223018 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58223018 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_PER>; + bit-offset = <16>; + clock-output-names = "csi0_lpcg_core_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + }; + + csi0_esc_lpcg: clock-controller@5822301c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5822301c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_MISC>; + bit-offset = <16>; + clock-output-names = "csi0_lpcg_esc_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + }; + + csi1_core_lpcg: clock-controller@58243018 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58243018 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_PER>; + bit-offset = <16>; + clock-output-names = "csi1_lpcg_core_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + }; + + csi1_esc_lpcg: clock-controller@5824301c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5824301c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_MISC>; + bit-offset = <16>; + clock-output-names = "csi1_lpcg_esc_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + }; + + pi0_pxl_lpcg: clock-controller@58263018 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58263018 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>; + bit-offset = <0>; + clock-output-names = "pi0_lpcg_pxl_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + }; + + pi0_ipg_lpcg: clock-controller@58263004 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58263004 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>; + bit-offset = <16>; + clock-output-names = "pi0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + }; + + pi0_misc_lpcg: clock-controller@5826301c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5826301c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_MISC0>; + bit-offset = <0>; + clock-output-names = "pi0_lpcg_misc_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + }; + + pdma0_lpcg: clock-controller@58500000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58500000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "pdma0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + }; + + pdma1_lpcg: clock-controller@58510000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58510000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "pdma1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH1>; + }; + + pdma2_lpcg: clock-controller@58520000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58520000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "pdma2_lpcg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH2>; + }; + + pdma3_lpcg: clock-controller@58530000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58530000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "pdma3_lpcg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH3>; + }; + + pdma4_lpcg: clock-controller@58540000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58540000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "pdma4_lpcg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH4>; + }; + + pdma5_lpcg: clock-controller@58550000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58550000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "pdma5_lpcg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH5>; + }; + + pdma6_lpcg: clock-controller@58560000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58560000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "pdma6_lpcg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH6>; + }; + + pdma7_lpcg: clock-controller@58570000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58570000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "pdma7_lpcg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH7>; + }; + + csi0_pxl_lpcg: clock-controller@58580000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58580000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "csi0_lpcg_pxl_clk"; + power-domains = <&pd IMX_SC_R_CSI_0>; + }; + + csi1_pxl_lpcg: clock-controller@58590000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58590000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "csi1_lpcg_pxl_clk"; + power-domains = <&pd IMX_SC_R_CSI_1>; + }; + + img_jpeg_dec_clk: clock-controller@585d0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x585d0000 0x10000>; + #clock-cells = <1>; + clocks = <&img_ipg_clk>, <&img_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "img_jpeg_dec_clk", + "img_jpeg_dec_ipg_clk"; + power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>; + }; + + img_jpeg_enc_clk: clock-controller@585f0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x585f0000 0x10000>; + #clock-cells = <1>; + clocks = <&img_ipg_clk>, <&img_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "img_jpeg_enc_clk", + "img_jpeg_enc_ipg_clk"; + power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>; + }; + + irqsteer_csi0: irqsteer@58220000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x58220000 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + clocks = <&img_ipg_clk>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <32>; + power-domains = <&pd IMX_SC_R_CSI_0>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_csi", "pd_isi_ch0"; + status = "disabled"; + }; + + irqsteer_csi1: irqsteer@58240000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x58240000 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + clocks = <&img_ipg_clk>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <32>; + power-domains = <&pd IMX_SC_R_CSI_1>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_csi", "pd_isi_ch0"; + status = "disabled"; + }; + + irqsteer_parallel: irqsteer@58260000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x58260000 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + clocks = <&clk_dummy>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <32>; + power-domains = <&pd IMX_SC_R_PI_0>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_pi", "pd_isi_ch0"; + status = "disabled"; + }; + + gpio0_mipi_csi0: gpio@58222000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x58222000 0x1000>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_csi0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_CSI_0>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_csi", "pd_isi_ch0"; + }; + + i2c_mipi_csi0: i2c@58226000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x58226000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_csi0>; + clocks = <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&img_ipg_clk>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_CSI_0_I2C_0>; + status = "disabled"; + }; + + i2c0_parallel: i2c@58266000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x58266000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_parallel>; + clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&img_ipg_clk>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_PI_0_I2C_0>; + status = "disabled"; + }; + + gpio0_mipi_csi1: gpio@58242000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x58242000 0x1000>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_csi1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_CSI_1>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_csi", "pd_isi_ch0"; + }; + + i2c_mipi_csi1: i2c@58246000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x58246000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_csi1>; + clocks = <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>, + <&img_ipg_clk>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_CSI_1_I2C_0>; + status = "disabled"; + }; + + cameradev: camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + isi_0: isi@58100000 { + compatible = "fsl,imx8-isi"; + reg = <0x58100000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&pdma0_lpcg 0>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + interface = <2 0 2>; + no-reset-control; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + + m2m_device{ + compatible = "imx-isi-m2m"; + status = "disabled"; + }; + }; + + isi_1: isi@58110000 { + compatible = "fsl,imx8-isi"; + reg = <0x58110000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&pdma1_lpcg 0>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH1>; + interface = <2 1 2>; + no-reset-control; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + isi_2: isi@58120000 { + compatible = "fsl,imx8-isi"; + reg = <0x58120000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&pdma2_lpcg 0>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH2>; + interface = <2 2 2>; + no-reset-control; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + isi_3: isi@58130000 { + compatible = "fsl,imx8-isi"; + reg = <0x58130000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&pdma3_lpcg 0>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH3>; + interface = <2 3 2>; + no-reset-control; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + isi_4: isi@58140000 { + compatible = "fsl,imx8-isi"; + reg = <0x58140000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&pdma4_lpcg 0>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH4>; + interface = <3 0 2>; + no-reset-control; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + isi_5: isi@58150000 { + compatible = "fsl,imx8-isi"; + reg = <0x58150000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&pdma5_lpcg 0>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH5>; + interface = <3 1 2>; + no-reset-control; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + isi_6: isi@58160000 { + compatible = "fsl,imx8-isi"; + reg = <0x58160000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&pdma6_lpcg 0>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH6>; + interface = <3 2 2>; + no-reset-control; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + isi_7: isi@58170000 { + compatible = "fsl,imx8-isi"; + reg = <0x58170000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&pdma7_lpcg 0>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH7>; + interface = <3 3 2>; + no-reset-control; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + mipi_csi_0: csi@58227000 { + compatible = "fsl,mxc-mipi-csi2"; + reg = <0x58227000 0x1000>, + <0x58221000 0x1000>; + clocks = <&csi0_core_lpcg 0>, + <&csi0_esc_lpcg 0>, + <&csi0_pxl_lpcg 0>; + clock-names = "clk_core", "clk_esc", "clk_pxl"; + assigned-clocks = <&csi0_core_lpcg 0>, + <&csi0_esc_lpcg 0>; + assigned-clock-rates = <360000000>, <72000000>; + power-domains = <&pd IMX_SC_R_CSI_0>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_csi", "pd_isi_ch0"; + status = "disabled"; + }; + + mipi_csi_1: csi@58247000{ + compatible = "fsl,mxc-mipi-csi2"; + reg = <0x58247000 0x1000>, + <0x58241000 0x1000>; + clocks = <&csi1_core_lpcg 0>, + <&csi1_esc_lpcg 0>, + <&csi1_pxl_lpcg 0>; + clock-names = "clk_core", "clk_esc", "clk_pxl"; + assigned-clocks = <&csi1_core_lpcg 0>, + <&csi1_esc_lpcg 0>; + assigned-clock-rates = <360000000>, <72000000>; + power-domains = <&pd IMX_SC_R_CSI_1>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_csi", "pd_isi_ch0"; + status = "disabled"; + }; + + parallel_csi: pcsi@58261000 { + compatible = "fsl,mxc-parallel-csi"; + reg = <0x58261000 0x1000>; + clocks = <&pi0_pxl_lpcg 0>, + <&pi0_ipg_lpcg 0>, + <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PI_0_PLL IMX_SC_PM_CLK_PLL>; + clock-names = "pixel", "ipg", "div", "dpll"; + assigned-clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>; + assigned-clock-parents = <&clk IMX_SC_R_PI_0_PLL IMX_SC_PM_CLK_PLL>; + assigned-clock-rates = <160000000>; /* 160MHz */ + power-domains = <&pd IMX_SC_R_PI_0>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_pi", "pd_isi_ch0"; + status = "disabled"; + }; + + jpegdec: jpegdec@58400000 { + compatible = "fsl,imx8-jpgdec"; + reg = <0x58400000 0x00050000 >; + interrupts = , + , + , + ; + clocks = <&img_jpeg_dec_clk 0>, + <&img_jpeg_dec_clk 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&img_jpeg_dec_clk 0>, + <&img_jpeg_dec_clk 1>; + assigned-clock-rates = <200000000>; + power-domains = <&pd IMX_SC_R_ISI_CH0>, + <&pd IMX_SC_R_MJPEG_DEC_MP>, + <&pd IMX_SC_R_MJPEG_DEC_S0>, + <&pd IMX_SC_R_MJPEG_DEC_S1>, + <&pd IMX_SC_R_MJPEG_DEC_S2>, + <&pd IMX_SC_R_MJPEG_DEC_S3>; + power-domain-names = "pd_isi_ch0", "pd_dec_mp", + "pd_dec_s0", "pd_dec_s1", + "pd_dec_s2", "pd_dec_s3"; + status = "disabled"; + }; + + jpegenc: jpegenc@58450000 { + compatible = "fsl,imx8-jpgenc"; + reg = <0x58450000 0x00050000 >; + interrupts = , + , + , + ; + clocks = <&img_jpeg_enc_clk 0>, + <&img_jpeg_enc_clk 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&img_jpeg_enc_clk 0>, + <&img_jpeg_enc_clk 1>; + assigned-clock-rates = <200000000>; + power-domains = <&pd IMX_SC_R_ISI_CH0>, + <&pd IMX_SC_R_MJPEG_ENC_MP>, + <&pd IMX_SC_R_MJPEG_ENC_S0>, + <&pd IMX_SC_R_MJPEG_ENC_S1>, + <&pd IMX_SC_R_MJPEG_ENC_S2>, + <&pd IMX_SC_R_MJPEG_ENC_S3>; + power-domain-names = "pd_isi_ch0", "pd_enc_mp", + "pd_enc_s0", "pd_enc_s1", + "pd_enc_s2", "pd_enc_s3"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi new file mode 100644 index 00000000000000..f406f6adce31ba --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi @@ -0,0 +1,319 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng + */ + +#include + +lsio_subsys: bus@5d000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5d000000 0x0 0x5d000000 0x1000000>, + <0x08000000 0x0 0x08000000 0x10000000>; + + lsio_mem_clk: clock-lsio-mem { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "lsio_mem_clk"; + }; + + lsio_bus_clk: clock-lsio-bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "lsio_bus_clk"; + }; + + lsio_gpio0: gpio@5d080000 { + reg = <0x5d080000 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_0>; + }; + + lsio_gpio1: gpio@5d090000 { + reg = <0x5d090000 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_1>; + }; + + lsio_gpio2: gpio@5d0a0000 { + reg = <0x5d0a0000 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_2>; + }; + + lsio_gpio3: gpio@5d0b0000 { + reg = <0x5d0b0000 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_3>; + }; + + lsio_gpio4: gpio@5d0c0000 { + reg = <0x5d0c0000 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_4>; + }; + + lsio_gpio5: gpio@5d0d0000 { + reg = <0x5d0d0000 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_5>; + }; + + lsio_gpio6: gpio@5d0e0000 { + reg = <0x5d0e0000 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_6>; + }; + + lsio_gpio7: gpio@5d0f0000 { + reg = <0x5d0f0000 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_7>; + }; + + flexspi0: spi@5d120000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8qxp-fspi"; + reg = <0x5d120000 0x10000>, <0x08000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = ; + clocks = <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>; + clock-names = "fspi", "fspi_en"; + power-domains = <&pd IMX_SC_R_FSPI_0>; + status = "disabled"; + }; + + lsio_mu0: mailbox@5d1b0000 { + reg = <0x5d1b0000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + lsio_mu1: mailbox@5d1c0000 { + reg = <0x5d1c0000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + lsio_mu2: mailbox@5d1d0000 { + reg = <0x5d1d0000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + lsio_mu3: mailbox@5d1e0000 { + reg = <0x5d1e0000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + lsio_mu4: mailbox@5d1f0000 { + reg = <0x5d1f0000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + lsio_mu5: mailbox@5d200000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x5d200000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_MU_5A>; + }; + + lsio_mu13: mailbox@5d280000 { + compatible = "fsl,imx8-mu-dsp", "fsl,imx6sx-mu"; + reg = <0x5d280000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_MU_13A>; + fsl,dsp_ap_mu_id = <13>; + }; + + /* LPCG clocks */ + pwm0_lpcg: clock-controller@5d400000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5d400000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, + <&lsio_bus_clk>, + <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm0_lpcg_ipg_clk", + "pwm0_lpcg_ipg_hf_clk", + "pwm0_lpcg_ipg_s_clk", + "pwm0_lpcg_ipg_slv_clk", + "pwm0_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_0>; + }; + + pwm1_lpcg: clock-controller@5d410000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5d410000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, + <&lsio_bus_clk>, + <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm1_lpcg_ipg_clk", + "pwm1_lpcg_ipg_hf_clk", + "pwm1_lpcg_ipg_s_clk", + "pwm1_lpcg_ipg_slv_clk", + "pwm1_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_1>; + }; + + pwm2_lpcg: clock-controller@5d420000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5d420000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, + <&lsio_bus_clk>, + <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm2_lpcg_ipg_clk", + "pwm2_lpcg_ipg_hf_clk", + "pwm2_lpcg_ipg_s_clk", + "pwm2_lpcg_ipg_slv_clk", + "pwm2_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_2>; + }; + + pwm3_lpcg: clock-controller@5d430000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5d430000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, + <&lsio_bus_clk>, + <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm3_lpcg_ipg_clk", + "pwm3_lpcg_ipg_hf_clk", + "pwm3_lpcg_ipg_s_clk", + "pwm3_lpcg_ipg_slv_clk", + "pwm3_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_3>; + }; + + pwm4_lpcg: clock-controller@5d440000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5d440000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, + <&lsio_bus_clk>, + <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm4_lpcg_ipg_clk", + "pwm4_lpcg_ipg_hf_clk", + "pwm4_lpcg_ipg_s_clk", + "pwm4_lpcg_ipg_slv_clk", + "pwm4_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_4>; + }; + + pwm5_lpcg: clock-controller@5d450000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5d450000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, + <&lsio_bus_clk>, + <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm5_lpcg_ipg_clk", + "pwm5_lpcg_ipg_hf_clk", + "pwm5_lpcg_ipg_s_clk", + "pwm5_lpcg_ipg_slv_clk", + "pwm5_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_5>; + }; + + pwm6_lpcg: clock-controller@5d460000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5d460000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, + <&lsio_bus_clk>, + <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm6_lpcg_ipg_clk", + "pwm6_lpcg_ipg_hf_clk", + "pwm6_lpcg_ipg_s_clk", + "pwm6_lpcg_ipg_slv_clk", + "pwm6_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_6>; + }; + + pwm7_lpcg: clock-controller@5d470000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5d470000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, + <&lsio_bus_clk>, + <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm7_lpcg_ipg_clk", + "pwm7_lpcg_ipg_hf_clk", + "pwm7_lpcg_ipg_s_clk", + "pwm7_lpcg_ipg_slv_clk", + "pwm7_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_7>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi new file mode 100644 index 00000000000000..57734ed8a9226a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include + +security_subsys: bus@31400000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x31400000 0x0 0x31400000 0x410000>; + + crypto: crypto@31400000 { + compatible = "fsl,sec-v4.0"; + reg = <0x31400000 0x90000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x31400000 0x90000>; + fsl,sec-era = <9>; + power-domains = <&pd IMX_SC_R_CAAM_JR2>; + power-domain-names = "jr"; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = ; + power-domains = <&pd IMX_SC_R_CAAM_JR2>; + power-domain-names = "jr"; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = ; + power-domains = <&pd IMX_SC_R_CAAM_JR3>; + power-domain-names = "jr"; + }; + }; + + caam_sm: caam-sm@31800000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x31800000 0x10000>; + }; + + sec_mu2: mu@31560000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x31560000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_SECO_MU_2>; + status = "okay"; + }; + + sec_mu3: mu@31570000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x31570000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_SECO_MU_3>; + status = "okay"; + }; + + sec_mu4: mu@31580000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x31580000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_SECO_MU_4>; + status = "okay"; + }; +}; + +seco_mu1: seco_mu1 { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&sec_mu2 2 0 + &sec_mu2 3 0>; + + fsl,seco_mu_id = <1>; + fsl,seco_max_users = <4>; + status = "okay"; +}; + +seco_mu2: seco_mu2 { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&sec_mu3 2 0 + &sec_mu3 3 0>; + + fsl,seco_mu_id = <2>; + fsl,seco_max_users = <4>; + status = "okay"; +}; + +seco_mu3: seco_mu3 { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&sec_mu4 2 0 + &sec_mu4 3 0>; + + fsl,seco_mu_id = <3>; + fsl,seco_max_users = <4>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-v2x.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-v2x.dtsi new file mode 100644 index 00000000000000..78a6aeb49921ba --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-v2x.dtsi @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include + +v2x_subsys: bus@2C000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x2c000000 0x0 0x2c000000 0x50000>; + + v2x_sv0: mu@2C000000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x2c000000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_V2X_MU_0>; + status = "okay"; + }; + v2x_sv1: mu@2c010000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x2c010000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_V2X_MU_1>; + status = "okay"; + }; + v2x_she: mu@2c020000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x2c020000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_V2X_MU_2>; + status = "okay"; + }; + v2x_sg0: mu@2c030000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x2c030000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_V2X_MU_3>; + status = "okay"; + }; + v2x_sg1: mu@2c040000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x2c040000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_V2X_MU_4>; + status = "okay"; + }; +}; + +v2x_mu_sv0: v2x_mu_sv0 { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&v2x_sv0 2 0 + &v2x_sv0 3 0>; + + fsl,seco_mu_id = <4>; + fsl,seco_max_users = <2>; + fsl,cmd_tag = /bits/ 8 <0x18>; + fsl,rsp_tag = /bits/ 8 <0xe2>; + status = "okay"; +}; +v2x_mu_sv1: v2x_mu_sv1 { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&v2x_sv1 2 0 + &v2x_sv1 3 0>; + + fsl,seco_mu_id = <5>; + fsl,seco_max_users = <2>; + fsl,cmd_tag = /bits/ 8 <0x19>; + fsl,rsp_tag = /bits/ 8 <0xe3>; + status = "okay"; +}; +v2x_mu_she: v2x_mu_she { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&v2x_she 2 0 + &v2x_she 3 0>; + + fsl,seco_mu_id = <6>; + fsl,seco_max_users = <2>; + fsl,cmd_tag = /bits/ 8 <0x1a>; + fsl,rsp_tag = /bits/ 8 <0xe4>; + status = "okay"; +}; +v2x_mu_sg0: v2x_mu_sg0 { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&v2x_sg0 2 0 + &v2x_sg0 3 0>; + + fsl,seco_mu_id = <7>; + fsl,seco_max_users = <2>; + fsl,cmd_tag = /bits/ 8 <0x1d>; + fsl,rsp_tag = /bits/ 8 <0xe7>; + status = "okay"; +}; +v2x_mu_sg1: v2x_mu_sg1 { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&v2x_sg1 2 0 + &v2x_sg1 3 0>; + + fsl,seco_mu_id = <8>; + fsl,seco_max_users = <2>; + fsl,cmd_tag = /bits/ 8 <0x1e>; + fsl,rsp_tag = /bits/ 8 <0xe8>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi new file mode 100755 index 00000000000000..dd7df81743490e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng + */ + +vpu_subsys: bus@2c000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x2c000000 0x0 0x2c000000 0x2000000>; + + vpu_lpcg: clock-controller@2d000000 { + compatible = "fsl,imx8qxp-lpcg-vpu"; + reg = <0x2c000000 0x2000000>; + #clock-cells = <1>; + status = "disabled"; + }; + + vpu_decoder: vpu_decoder@2c000000 { + compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec"; + reg = <0x2c000000 0x1000000>; + reg-names = "vpu_regs"; + power-domains = <&pd IMX_SC_R_VPU_DEC_0>, + <&pd IMX_SC_R_VPU>; + power-domain-names = "vpudec", "vpu"; + + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu_m0 0 0 + &mu_m0 0 1 + &mu_m0 1 0>; + + status = "disabled"; + }; + + vpu_encoder: vpu_encoder@2d000000 { + compatible = "nxp,imx8qxp-b0-vpuenc"; + reg = <0x2d000000 0x1000000>, /*VPU Encoder*/ + <0x2c000000 0x2000000>; /*VPU*/ + reg-names = "vpu_regs"; + power-domains = <&pd IMX_SC_R_VPU_ENC_0>, + <&pd IMX_SC_R_VPU>; + power-domain-names = "vpuenc1", "vpu"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; + + vpu_ts: vpu_ts@2c000000 { + compatible = "nxp,imx8qm-b0-vpu-ts"; + reg = <0x2c000000 0x1000000>; + reg-names = "vpu_ts"; + power-domains = <&pd IMX_SC_R_VPU_TS_0>, + <&pd IMX_SC_R_VPU>; + power-domain-names = "vputs", "vpu"; + mbox-names = "ts_tx0", "ts_tx1", "ts_tx2", "ts_tx3", + "ts_rx0", "ts_rx1", "ts_rx2", "ts_rx3"; + mboxes = <&mu3_m0 0 0 + &mu3_m0 0 1 + &mu3_m0 0 2 + &mu3_m0 0 3 + &mu3_m0 1 0 + &mu3_m0 1 1 + &mu3_m0 1 2 + &mu3_m0 1 3>; + status = "disabled"; + }; + + mu_m0: mailbox@2d000000 { + compatible = "fsl,imx8-mu0-vpu-m0", "fsl,imx6sx-mu"; + reg = <0x2d000000 0x20000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_0>; + power-domain-names = "vpumu0"; + fsl,vpu_ap_mu_id = <16>; + status = "okay"; + }; + + mu1_m0: mailbox@2d020000 { + compatible = "fsl,imx8-mu1-vpu-m0", "fsl,imx6sx-mu"; + reg = <0x2d020000 0x20000>; + interrupts = ; + fsl,vpu_ap_mu_id = <17>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_1>; + power-domain-names = "vpumu1"; + status = "okay"; + }; + + mu2_m0: mailbox@2d040000 { + compatible = "fsl,imx8-mu2-vpu-m0", "fsl,imx6sx-mu"; + reg = <0x2d040000 0x20000>; + interrupts = ; + fsl,vpu_ap_mu_id = <18>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_2>; + power-domain-names = "vpumu2"; + status = "disabled"; + }; + + mu3_m0: mailbox@2d060000 { + compatible = "fsl,imx8-mu3-vpu-m0", "fsl,imx6sx-mu"; + reg = <0x2d060000 0x20000>; + interrupts = ; + fsl,vpu_ap_mu_id = <19>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_3>; + power-domain-names = "vpumu3"; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dm-lpddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8dm-lpddr4-val.dts new file mode 100644 index 00000000000000..ad663b2706ab0c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dm-lpddr4-val.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8dm.dtsi" +#include "imx8q-val.dtsi" + +/ { + model = "Freescale i.MX8DM Validation Board"; + compatible = "fsl,imx8dm-val", "fsl,imx8dm", "fsl,imx8qm"; +}; + +&gpu_3d1 { + status = "disabled"; +}; + +&dc1_prg1 { + status = "disabled"; +}; + +&dc1_prg2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dm.dtsi b/arch/arm64/boot/dts/freescale/imx8dm.dtsi new file mode 100644 index 00000000000000..23cbfb330acfe9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dm.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include "imx8qm.dtsi" + +/ { + model = "Freescale i.MX8DM"; + compatible = "fsl, imx8dm", "fsl,imx8qm"; + +}; + +&thermal_zones { + /delete-node/ cpu-thermal0; + + pmic-thermal0 { + cooling-maps { + map0 { + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@0; + /delete-node/ cpu@1; + /delete-node/ cpu@2; + /delete-node/ cpu@3; + /delete-node/ l2-cache0; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dx-17x17-val.dts b/arch/arm64/boot/dts/freescale/imx8dx-17x17-val.dts new file mode 100644 index 00000000000000..8fff0b531b09f6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-17x17-val.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8dx.dtsi" +#include "imx8x-17x17-val.dtsi" + +/ { + model = "Freescale i.MX8DX 17x17 Validation Board"; + compatible = "fsl,imx8dx-17x17-val", "fsl,imx8dx", "fsl,imx8qxp"; +}; + diff --git a/arch/arm64/boot/dts/freescale/imx8dx-lpddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8dx-lpddr4-val.dts new file mode 100644 index 00000000000000..0556fd01b2a771 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-lpddr4-val.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8dx.dtsi" +#include "imx8x-val.dtsi" + +/ { + model = "Freescale i.MX8DX VALIDATION"; + compatible = "fsl,imx8dx-val", "fsl,imx8dx", "fsl,imx8qxp"; +}; + diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191-rpmsg.dts new file mode 100644 index 00000000000000..7696e3dc78b65f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191-rpmsg.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek-dsi-rm67191.dts" +#include "imx8x-mek-rpmsg.dtsi" + diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191.dts new file mode 100644 index 00000000000000..3157b4720fff35 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191.dts @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8dx-mek.dts" + +/delete-node/ &adv_bridge0; +/delete-node/ &adv_bridge1; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&ldb2_phy { + status = "disabled"; +}; + +&ldb2 { + status = "disabled"; +}; + +&lvds_bridge0 { + status = "disabled"; +}; + +&lvds_bridge1 { + status = "disabled"; +}; + +&mipi0_dphy { + status = "okay"; +}; + +&mipi0_dsi_host { + status = "okay"; + fsl,clock-drop-level = <2>; + + panel@0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "raydium,rm67191"; + reg = <0>; + reset-gpios = <&pca9557_a 6 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; + width-mm = <68>; + height-mm = <121>; + + port@0 { + reg = <0>; + panel0_in: endpoint { + remote-endpoint = <&mipi0_panel_out>; + }; + }; + }; + + ports { + /delete-node/ port@1; + + port@1 { + reg = <1>; + mipi0_panel_out: endpoint { + remote-endpoint = <&panel0_in>; + }; + }; + }; +}; + +&mipi1_dphy { + status = "okay"; +}; + +&mipi1_dsi_host { + status = "okay"; + fsl,clock-drop-level = <2>; + + panel@0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "raydium,rm67191"; + reg = <0>; + reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; + width-mm = <68>; + height-mm = <121>; + + port@0 { + reg = <0>; + panel1_in: endpoint { + remote-endpoint = <&mipi1_panel_out>; + }; + }; + }; + + ports { + /delete-node/ port@1; + + port@1 { + reg = <1>; + mipi1_panel_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-dsp.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-dsp.dts new file mode 100644 index 00000000000000..953b510f89351c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-dsp.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2018 + +#include "imx8dx-mek-rpmsg.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-wm8960 { + status = "disabled"; + }; + + dspaudio: dspaudio { + compatible = "fsl,dsp-audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + status = "okay"; + }; + + sound-dsp { + compatible = "fsl,imx-dsp-audio"; + model = "dsp-audio"; + cpu-dai = <&dspaudio>; + audio-codec = <&cs42888>; + audio-platform = <&dsp>; + }; +}; + +&edma0 { + compatible = "fsl,imx8qm-edma"; + reg = <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x592e0000 0x10000>, /* sai1 rx */ + <0x592f0000 0x10000>, /* sai1 tx */ + <0x59350000 0x10000>, + <0x59370000 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <8>; + interrupts = , /* spdif0 */ + , + , /* sai0 */ + , + , /* sai1 */ + , + , + ; + interrupt-names = "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ + "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ + "edma0-chan21-tx", /* gpt5 */ + "edma0-chan23-rx"; /* gpt7 */ + power-domains = <&pd IMX_SC_R_DMA_0_CH8>, + <&pd IMX_SC_R_DMA_0_CH9>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>, + <&pd IMX_SC_R_DMA_0_CH21>, + <&pd IMX_SC_R_DMA_0_CH23>; + power-domain-names = "edma0-chan8", "edma0-chan9", + "edma0-chan12", "edma0-chan13", + "edma0-chan14", "edma0-chan15", + "edma0-chan21", "edma0-chan23"; + status = "okay"; +}; + +&dsp { + compatible = "fsl,imx8qxp-dsp-v1"; + reserved-region = <&dsp_reserved>; + reg = <0x596e8000 0x88000>; + clocks = <&esai0_lpcg 1>, + <&esai0_lpcg 0>, + <&asrc0_lpcg 0>, + <&clk_dummy>, + <&aud_pll_div0_lpcg 0>, + <&aud_pll_div1_lpcg 0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>; + clock-names = "esai_ipg", "esai_mclk", "asrc_ipg", "asrc_mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3"; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + fsl,dsp-firmware = "imx/dsp/hifi4.bin"; + power-domains = <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_IRQSTR_DSP>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>, + <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_DMA_0_CH6>, + <&pd IMX_SC_R_DMA_0_CH7>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_DMA_0_CH0>, + <&pd IMX_SC_R_DMA_0_CH1>, + <&pd IMX_SC_R_DMA_0_CH2>, + <&pd IMX_SC_R_DMA_0_CH3>, + <&pd IMX_SC_R_DMA_0_CH4>, + <&pd IMX_SC_R_DMA_0_CH5>; +}; + +&esai0 { + status = "disabled"; +}; + +&asrc0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&wm8960 { + status = "disabled"; +}; + +&cs42888 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-enet2-tja1100.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-enet2-tja1100.dts new file mode 100644 index 00000000000000..67e9ba641c8c43 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-enet2-tja1100.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek.dts" +#include "imx8qxp-enet2-tja1100.dtsi" + +&esai0 { + status = "disabled"; +}; + +&fec2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel-rpmsg.dts new file mode 100644 index 00000000000000..6dde34436e386c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel-rpmsg.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek-rpmsg.dts" +#include "imx8x-mek-it6263-lvds0-dual-channel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel.dts new file mode 100644 index 00000000000000..511d327845c1da --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek.dts" +#include "imx8x-mek-it6263-lvds0-dual-channel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel-rpmsg.dts new file mode 100644 index 00000000000000..e81c9510ca820f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel-rpmsg.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek-rpmsg.dts" +#include "imx8x-mek-it6263-lvds1-dual-channel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel.dts new file mode 100644 index 00000000000000..b05ee54a35cca1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek.dts" +#include "imx8x-mek-it6263-lvds1-dual-channel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel-rpmsg.dts new file mode 100644 index 00000000000000..88d31032b0bce2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel-rpmsg.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek-rpmsg.dts" +#include "imx8x-mek-jdi-wuxga-lvds0-panel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel.dts new file mode 100644 index 00000000000000..9ad1f1ed3fa198 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek.dts" +#include "imx8x-mek-jdi-wuxga-lvds0-panel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel-rpmsg.dts new file mode 100644 index 00000000000000..631ab37190cf0c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel-rpmsg.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek-rpmsg.dts" +#include "imx8x-mek-jdi-wuxga-lvds1-panel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel.dts new file mode 100644 index 00000000000000..4349fc034e6848 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek.dts" +#include "imx8x-mek-jdi-wuxga-lvds1-panel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640-rpmsg.dts new file mode 100644 index 00000000000000..e0271bc7cba9e2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640-rpmsg.dts @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2020 +#include "imx8dx-mek-ov5640.dts" +#include "imx8x-mek-rpmsg.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640.dts new file mode 100644 index 00000000000000..62fa5eae3acce3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640.dts @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2020 + +#include "imx8dx-mek.dts" + +&isi_1 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_2 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_3 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + /delete-property/virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <1 2>; + }; + }; +}; + +&i2c_mipi_csi0 { + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&xtal24m>; + clock-names = "xclk"; + csi_id = <0>; + powerdown-gpios = <&lsio_gpio3 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&lsio_gpio3 8 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_mipi_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2>; + clocks-lanes = <0>; + }; + }; + }; + + /delete-node/max9286_mipi@6a; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-rpmsg.dts new file mode 100644 index 00000000000000..a219f16323bb19 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-rpmsg.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek.dts" +#include "imx8x-mek-rpmsg.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek.dts new file mode 100644 index 00000000000000..807d8cdc9a41bb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; +#include "imx8dx.dtsi" +#include "imx8x-mek.dtsi" + +/ { + model = "Freescale i.MX8DX MEK"; + compatible = "fsl,imx8dx-mek", "fsl,imx8dx", "fsl,imx8qxp"; + + reserved-memory { +/* + * Memory reserved for optee usage. Please do not use. + * This will be automaticky added to dtb if OP-TEE is installed. + * optee@96000000 { + * reg = <0 0x96000000 0 0x2000000>; + * no-map; + * }; + */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x14000000>; + alloc-ranges = <0 0x98000000 0 0x14000000>; + linux,cma-default; + }; + }; +}; + +&thermal_zones { + pmic-thermal0 { + cooling-maps { + map0 { + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&imx8_gpu_ss { + reg = <0x80000000 0x40000000>, <0x0 0x08000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dx.dtsi b/arch/arm64/boot/dts/freescale/imx8dx.dtsi new file mode 100644 index 00000000000000..05a7f593e717f4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2020 NXP + */ + +/dts-v1/; + +#include "imx8dxp.dtsi" + +&gpu_3d0 { + assigned-clock-rates = <372000000>, <372000000>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-evk.dts new file mode 100644 index 00000000000000..d4b80f4a49c747 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-evk.dts @@ -0,0 +1,697 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020 NXP + */ + +/dts-v1/; + +#include "imx8dxl.dtsi" + +/ { + model = "Freescale i.MX8DXL DDR3 EVK"; + compatible = "fsl,imx8dxl-mek", "fsl,imx8dxl"; + + chosen { + stdout-path = &lpuart0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x20000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + + rpmsg_dma_reserved:rpmsg_dma@0x90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x100000>; + }; + +/* + * Memory reserved for optee usage. Please do not use. + * This will be automaticky added to dtb if OP-TEE is installed. + * optee@96000000 { + * reg = <0 0x96000000 0 0x2000000>; + * no-map; + * }; + */ + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x8000000>; + alloc-ranges = <0 0x98000000 0 0x8000000>; + linux,cma-default; + }; + }; + + reg_can0_stby: regulator-can0-stby { + compatible = "regulator-fixed"; + regulator-name = "can0-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_3 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + regulator-name = "can1-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_3 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <3480>; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc>; + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + interrupts = ; + status = "okay"; + + mt35xu512aba0: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&lpspi3 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi3>; + pinctrl-assert-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <30000000>; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pca6416_1: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca6416_2: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9548_1: pca9548@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + }; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pca6416_3: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&lsio_gpio2>; + interrupts = <5 IRQ_TYPE_EDGE_RISING>; + }; + + pca9548_2: pca9548@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-1 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can0_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&lsio_gpio4 { + status = "okay"; +}; + +&lsio_gpio5 { + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; + max-cs = <1>; +}; + +&pcieb{ + compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + status = "disabled"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 497>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>; + max-frequency = <100000000>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + snps,reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>; + snps,reset-delays-us = <10 20 200000>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + eee-broken-1000t; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + phy-reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&usbphy1 { + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 0x0600004c + IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN 0x0600004c + >; + }; + + pinctrl_usbotg1: otg1 { + fsl,pins = < + IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_usbotg2: otg2 { + fsl,pins = < + IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR 0x00000021 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020 + IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020 + IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020 + IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020 + IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020 + IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020 + IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020 + IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020 + IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020 + IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020 + IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020 + IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020 + IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020 + IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + IMX8DXL_EMMC0_DATA0_CONN_NAND_DATA00 0x0e00004c + IMX8DXL_EMMC0_DATA1_CONN_NAND_DATA01 0x0e00004c + IMX8DXL_EMMC0_DATA2_CONN_NAND_DATA02 0x0e00004c + IMX8DXL_EMMC0_DATA3_CONN_NAND_DATA03 0x0e00004c + IMX8DXL_EMMC0_DATA4_CONN_NAND_DATA04 0x0e00004c + IMX8DXL_EMMC0_DATA5_CONN_NAND_DATA05 0x0e00004c + IMX8DXL_EMMC0_DATA6_CONN_NAND_DATA06 0x0e00004c + IMX8DXL_EMMC0_DATA7_CONN_NAND_DATA07 0x0e00004c + IMX8DXL_EMMC0_CLK_CONN_NAND_READY_B 0x0e00004c + IMX8DXL_EMMC0_STROBE_CONN_NAND_CLE 0x0e00004c + IMX8DXL_EMMC0_RESET_B_CONN_NAND_WP_B 0x0e00004c + IMX8DXL_EMMC0_CMD_CONN_NAND_DQS 0x0e00004c + + IMX8DXL_USDHC1_RESET_B_CONN_NAND_WE_B 0x0e00004c + IMX8DXL_USDHC1_WP_CONN_NAND_ALE 0x0e00004c + IMX8DXL_USDHC1_VSELECT_CONN_NAND_RE_B 0x0e00004c + >; + }; + + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x600004c + IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x600004c + IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x600004c + IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x600004c + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021 + IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021 + IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8DXL_UART0_RX_ADMA_UART0_RX 0x0600004c + IMX8DXL_UART0_TX_ADMA_UART0_TX 0x0600004c + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8DXL_UART1_TX_ADMA_UART1_TX 0x0600004c + IMX8DXL_UART1_RX_ADMA_UART1_RX 0x0600004c + IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x0600004c + IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x0600004c + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021 + IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021 + >; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins = < + IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x00000021 + IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x00000021 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX8DXL_FLEXCAN0_RX_ADMA_SAI1_TXC 0x06000040 + IMX8DXL_FLEXCAN0_TX_ADMA_SAI1_TXFS 0x06000040 + IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000040 + IMX8DXL_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000060 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + IMX8DXL_SNVS_TAMPER_OUT3_ADMA_SAI2_RXC 0x06000040 + IMX8DXL_SNVS_TAMPER_IN0_ADMA_SAI2_RXFS 0x06000040 + IMX8DXL_SNVS_TAMPER_OUT4_ADMA_SAI2_RXD 0x06000060 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + IMX8DXL_SNVS_TAMPER_IN1_ADMA_SAI3_RXC 0x06000040 + IMX8DXL_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS 0x06000040 + IMX8DXL_SNVS_TAMPER_IN2_ADMA_SAI3_RXD 0x06000060 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000040 /* RESET_B */ + IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000021 /* WP */ + IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000021 /* CD */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_pcieb: pcieagrp{ + fsl,pins = < + IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 + IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + >; + }; + + pinctrl_adc: adcgrp{ + fsl,pins = < + IMX8DXL_ADC_IN0_ADMA_ADC_IN0 0x06000021 + IMX8DXL_ADC_IN1_ADMA_ADC_IN1 0x06000021 + IMX8DXL_ADC_IN4_ADMA_ADC_IN4 0x06000021 + IMX8DXL_ADC_IN5_ADMA_ADC_IN5 0x06000021 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0-tja1100.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0-tja1100.dts new file mode 100644 index 00000000000000..b1de12136d6868 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0-tja1100.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8dxl-evk-enet0.dts" + +ðphy1 { + status = "disabled"; +}; + +&fec1 { + pinctrl-0 = <&pinctrl_fec1_rmii>; + clocks = <&enet0_lpcg 4>, + <&enet0_lpcg 2>, + <&clk IMX_SC_R_ENET_0 IMX_SC_C_DISABLE_50>, + <&enet0_lpcg 0>, + <&enet0_lpcg 1>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + tja110x,refclk_in; + }; + }; +}; + +&iomuxc { + pinctrl_fec1_rmii: fec1rmiigrp { + fsl,pins = < + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000060 + IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x00000060 + >; + }; +}; + +&max7322 { + status = "disabled"; +}; + +®_fec1_io { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0.dts new file mode 100644 index 00000000000000..394cdc8864e637 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8dxl-evk.dts" + +®_fec1_sel { + status = "okay"; +}; + +®_fec1_io { + status = "okay"; +}; + +&eqos { + status = "disabled"; +}; + +&fec1 { + status = "okay"; +}; + +&max7322 { + status = "okay"; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-lpspi-slave.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-lpspi-slave.dts new file mode 100644 index 00000000000000..d5689b1726835e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk-lpspi-slave.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8dxl-evk.dts" + +/delete-node/&spidev0; + +&pinctrl_lpspi3 { + fsl,pins = < + IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x600004c + IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x600004c + IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x600004c + IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x600004c + >; +}; + +&lpspi3 { + #address-cells = <0>; + pinctrl-0 = <&pinctrl_lpspi3>; + /delete-property/ cs-gpios; + spi-slave; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-pcie.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-pcie.dts new file mode 100644 index 00000000000000..9be6c12161da99 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk-pcie.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8dxl-evk.dts" + +&pcieb { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-rpmsg.dts new file mode 100644 index 00000000000000..914cdd30247656 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk-rpmsg.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8dxl-evk.dts" + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + memory-region = <&vdevbuffer>; + status = "disabled"; +}; + +&imx8dxl_cm4 { + /* Assume you have partitioned M4, so M4 is ont controled by Linux */ + /delete-property/ power-domains; + status = "okay"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&flexcan3 { + status = "disabled"; +}; + +&flexspi0 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts new file mode 100644 index 00000000000000..71102ad7969269 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -0,0 +1,994 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020 NXP + */ + +/dts-v1/; + +#include "imx8dxl.dtsi" + +/ { + model = "Freescale i.MX8DXL EVK"; + compatible = "fsl,imx8dxl-mek", "fsl,imx8dxl"; + + chosen { + stdout-path = &lpuart0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + + rpmsg_reserved: rpmsg@0x90200000 { + no-map; + reg = <0 0x90200000 0 0x200000>; + }; + +/* + * Memory reserved for optee usage. Please do not use. + * This will be automaticky added to dtb if OP-TEE is installed. + * optee@96000000 { + * reg = <0 0x96000000 0 0x2000000>; + * no-map; + * }; + */ + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x14000000>; + alloc-ranges = <0 0x98000000 0 0x14000000>; + linux,cma-default; + }; + + vdev0vring0: vdev0vring0@90000000 { + compatible = "shared-dma-pool"; + reg = <0 0x90000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@90008000 { + compatible = "shared-dma-pool"; + reg = <0 0x90008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@90010000 { + compatible = "shared-dma-pool"; + reg = <0 0x90010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@90018000 { + compatible = "shared-dma-pool"; + reg = <0 0x90018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer { + compatible = "shared-dma-pool"; + reg = <0 0x90400000 0 0x100000>; + no-map; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&pca6416_2 0 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + reg_can0_stby: regulator-can0-stby { + compatible = "regulator-fixed"; + regulator-name = "can0-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_3 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + regulator-name = "can1-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_3 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_fec1_sel: regfec1_sel { + compatible = "regulator-fixed"; + regulator-name = "fec1_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_1 11 GPIO_ACTIVE_LOW>; + regulator-always-on; + status = "disabled"; + }; + + reg_fec1_io: regfec1_io { + compatible = "regulator-fixed"; + regulator-name = "fec1_io_supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + status = "disabled"; + }; + + reg_usdhc2_vmmc: usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <3480>; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&pca6416_1 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + m2_uart1_sel: fixedregulator@101 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "m2_uart1_sel"; + gpio = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + mux3_en: fixedregulator@102 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "mux3_en"; + gpio = <&pca6416_2 8 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + pcie_clk_sel_ext: fixedregulator@103 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "clk_ext_sel"; + gpio = <&pca6416_1 10 GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; + + clock_mclk_out1: clock_mclk_out1 { + compatible = "gpio-gate-clock"; + clocks = <&mclkout1_lpcg 0>; + #clock-cells = <0>; + enable-gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; + }; + + sound-wm8960 { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai1>; + audio-codec = <&wm8960_1>; + asrc-controller = <&asrc0>; + codec-master; + /* + * hp-det = ; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <2 0>; + hp-det-gpios = <&pca6416_3 2 GPIO_ACTIVE_HIGH>; + mic-det-gpios = <&pca6416_3 2 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + }; + + sound-wm8960-2 { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio-2"; + cpu-dai = <&sai2>; + audio-codec = <&wm8960_2>; + codec-master; + capture-only; + /* + * hp-det = ; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <2 0>; + hp-det-gpios = <&pca6416_3 3 GPIO_ACTIVE_HIGH>; + mic-det-gpios = <&pca6416_3 3 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB", + "Playback", "CPU-Playback", + "CPU-Capture", "Capture"; + }; + + sound-wm8960-3 { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio-3"; + cpu-dai = <&sai3>; + audio-codec = <&wm8960_3>; + codec-master; + capture-only; + /* + * hp-det = ; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <2 0>; + hp-det-gpios = <&pca6416_3 4 GPIO_ACTIVE_HIGH>; + mic-det-gpios = <&pca6416_3 4 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB", + "Playback", "CPU-Playback", + "CPU-Capture", "Capture"; + }; +}; + +&adc0 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + interrupts = ; + status = "okay"; + + mt35xu512aba0: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&imx8dxl_cm4 { + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>, + <&vdev1vring0>, <&vdev1vring1>; + status = "disabled"; +}; + +&lpspi3 { + fsl,spi-num-chipselects = <1>; + fsl,spi-only-use-cs1-sel; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi3>; + pinctrl-assert-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <30000000>; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pca6416_1: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca6416_2: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9548_1: pca9548@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + + wm8960_1: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clock_mclk_out1>; + clock-names = "mclk"; + wlf,shared-lrclk; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout1_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + wm8960_2: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clock_mclk_out1>; + clock-names = "mclk"; + wlf,shared-lrclk; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout1_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + wm8960_3: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clock_mclk_out1>; + clock-names = "mclk"; + wlf,shared-lrclk; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout1_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + }; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pca6416_3: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&lsio_gpio2>; + interrupts = <5 IRQ_TYPE_EDGE_RISING>; + }; + + pca9548_2: pca9548@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can0_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&lsio_gpio4 { + status = "okay"; +}; + +&lsio_gpio5 { + status = "okay"; +}; + +&pcieb{ + compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + ext_osc = <0>; + epdev_on-supply = <&epdev_on>; + reserved-region = <&rpmsg_reserved>; + status = "disabled"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&sai2 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai2_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&sai3 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai3_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 497>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>; + max-frequency = <100000000>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + nvmem-cells = <&fec_mac1>; + nvmem-cell-names = "mac-address"; + snps,reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>; + snps,reset-delays-us = <10 20 200000>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + eee-broken-1000t; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + nvmem-cells = <&fec_mac0>; + nvmem-cell-names = "mac-address"; + phy-reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&usbphy1 { + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0 + IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 0x0600004c + IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN 0x0600004c + >; + }; + + pinctrl_usbotg1: otg1 { + fsl,pins = < + IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_usbotg2: otg2 { + fsl,pins = < + IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR 0x00000021 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020 + IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020 + IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020 + IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020 + IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020 + IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020 + IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020 + IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020 + IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020 + IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020 + IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020 + IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020 + IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020 + IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + >; + }; + + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x600004c + IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x600004c + IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x600004c + IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x600004c + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021 + IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021 + IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020 + IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020 + IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020 + IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 + IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021 + IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021 + >; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins = < + IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x00000021 + IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x00000021 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX8DXL_FLEXCAN0_RX_ADMA_SAI1_TXC 0x06000040 + IMX8DXL_FLEXCAN0_TX_ADMA_SAI1_TXFS 0x06000040 + IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000040 + IMX8DXL_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000060 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + IMX8DXL_SNVS_TAMPER_OUT3_ADMA_SAI2_RXC 0x06000040 + IMX8DXL_SNVS_TAMPER_IN0_ADMA_SAI2_RXFS 0x06000040 + IMX8DXL_SNVS_TAMPER_OUT4_ADMA_SAI2_RXD 0x06000060 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + IMX8DXL_SNVS_TAMPER_IN1_ADMA_SAI3_RXC 0x06000040 + IMX8DXL_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS 0x06000040 + IMX8DXL_SNVS_TAMPER_IN2_ADMA_SAI3_RXD 0x06000060 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000040 /* RESET_B */ + IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000021 /* WP */ + IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000021 /* CD */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_pcieb: pcieagrp{ + fsl,pins = < + IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 + IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek-rpmsg.dts new file mode 100755 index 00000000000000..d336ff759b289a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek-rpmsg.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8dxl-phantom-mek.dtsi" + +/delete-node/ &cm40_i2c; + +&i2c_rpbus_5 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&cm40_i2c_lpcg { + status = "disabled"; +}; + +&can0_lpcg { + status = "disabled"; +}; + +®_can0_en { + status = "disabled"; +}; + +®_can0_stby { + status = "disabled"; +}; + +®_can1_en { + status = "disabled"; +}; + +®_can1_stby { + status = "disabled"; +}; + +&cm40_intmux { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&flexspi0 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dts b/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dts new file mode 100755 index 00000000000000..d7702a2a87f851 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8dxl-phantom-mek.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dtsi new file mode 100755 index 00000000000000..5a28a7ca7463eb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dtsi @@ -0,0 +1,734 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include +#include "imx8qxp.dtsi" + +/ { + model = "Freescale i.MX8DXL Phantom MEK"; + compatible = "fsl,imx8dxl-phantom-mek", "fsl,imx8dxl-phantom", "fsl,imx8qxp"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + + rpmsg_dma_reserved:rpmsg_dma@0x90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x100000>; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_modem_reset>; + pinctrl-1 = <&pinctrl_modem_reset_sleep>; + reset-gpios = <&lsio_gpio3 1 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + + rpmsg_dma_reserved:rpmsg_dma@0x90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x100000>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_can0_en: regulator-can0-gen { + compatible = "regulator-fixed"; + regulator-name = "can0-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can1_en: regulator-can1-gen { + compatible = "regulator-fixed"; + regulator-name = "can1-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can0_stby: regulator-can0-stby { + compatible = "regulator-fixed"; + regulator-name = "can0-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can0_en>; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + regulator-name = "can1-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can1_en>; + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /*gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; removing as i2c bus is changing in new board */ + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <3480>; + enable-active-high; + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_wlreg_on>; + pinctrl-1 = <&pinctrl_wlreg_on_sleep>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&lsio_gpio3 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb_vbus>; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&lsio_gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_audio: fixedregulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + sound: sound { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai1>; + audio-codec = <&wm8960>; + asrc-controller = <&asrc0>; + codec-master; + /* + * hp-det = ; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <2 0>; + hp-det-gpios = <&lsio_gpio0 13 0>; + mic-det-gpios = <&lsio_gpio0 13 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Main MIC", + "RINPUT2", "Main MIC", + "Mic Jack", "MICB", + "Main MIC", "MICB", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + }; +}; + +&lvds_subsys { + status = "disabled"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + memory-region = <&rpmsg_dma_reserved>; + status = "okay"; +}; + +&acm { + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx8dxl-phantom-mek { + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 + IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 + IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 + IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 + IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 + IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 + IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 + IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 + IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 + IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 + IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QXP_UART1_TX_ADMA_UART1_TX 0x06000020 + IMX8QXP_UART1_RX_ADMA_UART1_RX 0x06000020 + IMX8QXP_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 + IMX8QXP_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 + >; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 + IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000021 + IMX8QXP_ENET0_MDC_CONN_ENET1_MDC 0x06000020 + IMX8QXP_ENET0_MDIO_CONN_ENET1_MDIO 0x06000020 + IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 + IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060 + IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060 + IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060 + IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060 + IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060 + IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 + IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QXP_UART2_TX_ADMA_FLEXCAN1_TX 0x21 + IMX8QXP_UART2_RX_ADMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + >; + }; + + pinctrl_cm40_i2c: cm40i2cgrp { + fsl,pins = < + IMX8QXP_ADC_IN1_M40_I2C0_SDA 0x0600004c + IMX8QXP_ADC_IN0_M40_I2C0_SCL 0x0600004c + >; + }; + + pinctrl_ioexp_rst_sleep: ioexp_rst_sleep_grp { + fsl,pins = < + IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x07800021 + >; + }; + + pinctrl_modem_reset: modemresetgrp { + fsl,pins = < + IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x06000021 + >; + }; + + pinctrl_modem_reset_sleep: modemreset_sleepgrp { + fsl,pins = < + IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x07800021 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX8QXP_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000040 + IMX8QXP_FLEXCAN2_TX_ADMA_SAI1_RXC 0x06000040 + IMX8QXP_FLEXCAN2_RX_ADMA_SAI1_RXFS 0x06000040 + IMX8QXP_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000060 + IMX8QXP_SPI3_SCK_LSIO_GPIO0_IO13 0x06000040 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + pinctrl_reg_usb_vbus: regusbvbusgrp { + fsl,pins = < + IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 + IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 + IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QXP_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8QXP_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8QXP_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8QXP_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8QXP_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8QXP_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + IMX8QXP_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8QXP_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8QXP_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8QXP_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8QXP_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8QXP_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + IMX8QXP_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8QXP_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8QXP_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8QXP_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8QXP_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8QXP_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_pcieb: pcieagrp{ + fsl,pins = < + IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 + IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x06000021 + IMX8QXP_EMMC0_RESET_B_LSIO_GPIO4_IO18 0x06000021 + >; + }; + + pinctrl_gpio3: gpio3grp{ + fsl,pins = < + IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xC0000041 + IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xC0000041 + >; + }; + + pinctrl_wlreg_on: wlregongrp{ + fsl,pins = < + IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x06000000 + >; + }; + + pinctrl_wlreg_on_sleep: wlregon_sleepgrp{ + fsl,pins = < + IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x07800000 + >; + }; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "okay"; +}; + + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + phy-reset-gpio=<&lsio_gpio5 9 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + nvmem-cells = <&fec_mac1>; + nvmem-cell-names = "mac-address"; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can0_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt35xu512aba"; + spi-max-frequency = <133000000>; + spi-nor,ddr-quad-read-dummy = <4>; + }; +}; + +&cm40_intmux { + status = "okay"; +}; + +&cm40_i2c { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cm40_i2c>; + status = "okay"; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + fsl,sai-synchronous-rx; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <114>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&lsio_gpio3 { + pinctrl-name = "default"; + pinctrl-0 = <&pinctrl_gpio3>; +}; + +&tsens { + tsens-num = <3>; +}; + +&thermal_zones { + cpu-thermal0 { + cooling-maps { + map0 { + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 497>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&a35_opp_table { + /delete-node/ opp-900000000; +}; + +&cpus { + /delete-node/ cpu@2; + /delete-node/ cpu@3; +}; + +&pcieb{ + compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + epdev_on-supply = <&epdev_on>; + ext_osc = <1>; + status = "okay"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + memory-region = <&rpmsg_dma_reserved>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi new file mode 100644 index 00000000000000..ae90a2e139e7d3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020 NXP + */ + +/delete-node/ &sai4; +/delete-node/ &sai5; +/delete-node/ &esai0; +/delete-node/ &asrc1; +/delete-node/ &spdif1; +/delete-node/ &amix; +/delete-node/ &adc1; +/delete-node/ &emvsim0; +/delete-node/ &edma1; +/delete-node/ &sai4_lpcg; +/delete-node/ &sai5_lpcg; +/delete-node/ &esai0_lpcg; +/delete-node/ &asrc1_lpcg; +/delete-node/ &spdif1_lpcg; +/delete-node/ &amix_lpcg; +/delete-node/ &emvsim0_lpcg; +/delete-node/ &adc1_lpcg; +/delete-node/ &dsp_lpcg; +/delete-node/ &dsp_ram_lpcg; + +&dma_ipg_clk { + clock-frequency = <160000000>; +}; + +&audio_ipg_clk { + clock-frequency = <160000000>; +}; + +&edma0 { + reg = <0x59200000 0x10000>, /* asrc0 */ + <0x59210000 0x10000>, + <0x59220000 0x10000>, + <0x59230000 0x10000>, + <0x59240000 0x10000>, + <0x59250000 0x10000>, + <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x592e0000 0x10000>, /* sai1 rx */ + <0x592f0000 0x10000>, /* sai1 tx */ + <0x59300000 0x10000>, /* sai2 rx */ + <0x59310000 0x10000>, /* sai3 rx */ + <0x59350000 0x10000>, /* gpt0 */ + <0x59360000 0x10000>, /* gpt1 */ + <0x59370000 0x10000>, /* gpt2 */ + <0x59380000 0x10000>; /* gpt3 */ + interrupts = , /* asrc 0 */ + , + , + , + , + , + , /* spdif0 */ + , + , /* sai0 */ + , + , /* sai1 */ + , + , /* sai2 */ + , /* sai3 */ + , /* gpt0 */ + , /* gpt1 */ + , /* gpt2 */ + ; /* gpt3 */ + interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* asrc0 */ + "edma0-chan2-rx", "edma0-chan3-tx", + "edma0-chan4-tx", "edma0-chan5-tx", + "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ + "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ + "edma0-chan16-rx", "edma0-chan17-rx", /* sai2, sai3 */ + "edma0-chan21-tx", /* gpt0 */ + "edma0-chan22-tx", /* gpt1 */ + "edma0-chan23-tx", /* gpt2 */ + "edma0-chan24-rx"; /* gpt3 */ + power-domains = <&pd IMX_SC_R_DMA_0_CH0>, + <&pd IMX_SC_R_DMA_0_CH1>, + <&pd IMX_SC_R_DMA_0_CH2>, + <&pd IMX_SC_R_DMA_0_CH3>, + <&pd IMX_SC_R_DMA_0_CH4>, + <&pd IMX_SC_R_DMA_0_CH5>, + <&pd IMX_SC_R_DMA_0_CH8>, + <&pd IMX_SC_R_DMA_0_CH9>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>, + <&pd IMX_SC_R_DMA_0_CH16>, + <&pd IMX_SC_R_DMA_0_CH17>, + <&pd IMX_SC_R_DMA_0_CH21>, + <&pd IMX_SC_R_DMA_0_CH22>, + <&pd IMX_SC_R_DMA_0_CH23>, + <&pd IMX_SC_R_DMA_0_CH24>; + power-domain-names = "edma0-chan0", "edma0-chan1", + "edma0-chan2", "edma0-chan3", + "edma0-chan4", "edma0-chan5", + "edma0-chan8", "edma0-chan9", + "edma0-chan12", "edma0-chan13", + "edma0-chan14", "edma0-chan15", + "edma0-chan16", "edma0-chan17", + "edma0-chan21", "edma0-chan22", + "edma0-chan23", "edma0-chan24"; +}; + +&acm { + compatible = "nxp,imx8dxl-acm"; + power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_MCLK_OUT_0>, + <&pd IMX_SC_R_MCLK_OUT_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_SAI_0>, + <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_SAI_2>, + <&pd IMX_SC_R_SAI_3>, + <&pd IMX_SC_R_SPDIF_0>, + <&pd IMX_SC_R_MQS_0>; +}; + +&edma2 { + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + +&lpuart0 { + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + interrupts = ; +}; + +&lpuart1 { + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + interrupts = ; +}; + +&lpuart2 { + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + interrupts = ; +}; + +&lpuart3 { + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + interrupts = ; +}; + +&i2c0 { + compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + interrupts = ; +}; + +&i2c1 { + compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + interrupts = ; +}; + +&i2c2 { + compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + interrupts = ; +}; + +&i2c3 { + compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + interrupts = ; +}; + +&lpspi3 { + compatible = "fsl,imx8dxl-spi", "fsl,imx8qxp-spi", "fsl,imx7ulp-spi"; + interrupts = ; +}; + +&flexcan1 { + compatible = "fsl,imx8dxl-flexcan", "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + interrupts = ; +}; + +&flexcan2 { + compatible = "fsl,imx8dxl-flexcan", "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + interrupts = ; +}; + +&flexcan3 { + compatible = "fsl,imx8dxl-flexcan", "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + interrupts = ; +}; + +&adc0 { + interrupts = ; +}; + +&sai0 { + interrupts = ; +}; + +&sai1 { + interrupts = ; +}; + +&sai2 { + interrupts = ; +}; + +&sai3 { + interrupts = ; +}; + +&spdif0 { + interrupts = , /* rx */ + ; /* tx */ +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi new file mode 100644 index 00000000000000..9fd0757b2c3b8a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020 NXP + */ + +/delete-node/ &enet1_lpcg; +/delete-node/ &fec2; +/delete-node/ &mlb; +/delete-node/ &mlb_lpcg; + +&usdhc1 { + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + interrupts = ; +}; + +&usdhc2 { + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + interrupts = ; +}; + +&usdhc3 { + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + interrupts = ; +}; + +&enet0_lpcg { + clocks = <&conn_enet0_root_clk>, + <&conn_enet0_root_clk>, + <&conn_axi_clk>, + <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>, + <&conn_ipg_clk>, + <&conn_ipg_clk>; +}; + +&usbotg1 { + interrupts = ; + /* + * usbotg1 and usbotg2 share one clcok + * scfw disable clock access and keep it always on + * in case other core (M4) use one of these. + */ + clocks = <&clk_dummy>; +}; + +&fec1 { + compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec"; + interrupts = , + , + , + ; + assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; + assigned-clock-rates = <125000000>; +}; + +&dma_apbh { + compatible = "fsl,imx28-dma-apbh"; + interrupts = , + , + , + ; +}; + +&gpmi { + compatible = "fsl,imx8qxp-gpmi-nand"; + interrupts = ; +}; + +&conn_subsys { + + usb2_2_lpcg: clock-controller@5b280000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b280000 0x10000>; + #clock-cells = <1>; + + bit-offset = <28>; + clocks = <&conn_ipg_clk>; + clock-output-names = "usboh3_2_phy_ipg_clk"; + power-domains = <&pd IMX_SC_R_USB_1_PHY>; + }; + + conn_enet0_root_clk: clock-conn-enet0-root { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + clock-output-names = "conn_enet0_root_clk"; + }; + + eqos_lpcg: clock-controller@5b240000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b240000 0x10000>; + #clock-cells = <1>; + clocks = <&conn_enet0_root_clk>, + <&conn_axi_clk>, + <&conn_axi_clk>, + <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, + <&conn_ipg_clk>; + bit-offset = <0 8 16 20 24>; + clock-output-names = "eqos_ptp", + "eqos_mem_clk", + "eqos_aclk", + "eqos_clk", + "eqos_csr_clk"; + power-domains = <&pd IMX_SC_R_ENET_1>; + }; + + eqos: ethernet@5b050000 { + compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a"; + reg = <0x5b050000 0x10000>; + interrupt-parent = <&gic>; + interrupts = , + ; + interrupt-names = "eth_wake_irq", "macirq"; + clocks = <&eqos_lpcg 2>, + <&eqos_lpcg 4>, + <&eqos_lpcg 0>, + <&eqos_lpcg 3>, + <&eqos_lpcg 1>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; + assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <125000000>; + power-domains = <&pd IMX_SC_R_ENET_1>; + clk_csr = <0>; + status = "disabled"; + }; + + usbphy2: usbphy@0x5b110000 { + compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x5b110000 0x1000>; + clocks = <&usb2_2_lpcg 0>; + power-domains = <&pd IMX_SC_R_USB_1_PHY>; + status = "disabled"; + }; + + usbotg2: usb@5b0e0000 { + compatible = "fsl,imx8qm-usb", "fsl,imx7ulp-usb"; + reg = <0x5b0e0000 0x200>; + interrupt-parent = <&gic>; + interrupts = ; + fsl,usbphy = <&usbphy2>; + fsl,usbmisc = <&usbmisc2 0>; + /* + * usbotg1 and usbotg2 share one clcok + * scfw disable clock access and keep it always on + * in case other core (M4) use one of these. + */ + clocks = <&clk_dummy>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + #stream-id-cells = <1>; + power-domains = <&pd IMX_SC_R_USB_1>; + status = "disabled"; + }; + + usbmisc2: usbmisc@5b0e0200 { + #index-cells = <1>; + compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x5b0e0200 0x200>; + }; + +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi new file mode 100644 index 00000000000000..b2be8fa51ba8af --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + * Dong Aisheng + */ + +&ddr_pmu0 { + compatible = "fsl,imx8dxl-ddr-pmu", "fsl,imx8-ddr-pmu"; + interrupts = ; +}; + +&ddr_subsys { + db_ipg_clk: clock-db-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <456000000>; + clock-output-names = "db_ipg_clk"; + }; + + db_pmu0: db-pmu@5ca40000 { + compatible = "fsl,imx8dxl-db-pmu"; + reg = <0x5ca40000 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&db_pmu0_lpcg 1>, <&db_pmu0_lpcg 0>; + clock-names = "ipg", "cnt"; + power-domains = <&pd IMX_SC_R_PERF>; + }; + + db_pmu0_lpcg: clock-controller@5cae0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5cae0000 0x10000>; + #clock-cells = <1>; + clocks = <&db_ipg_clk>, <&db_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "perf_lpcg_cnt_clk", + "perf_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_PERF>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi new file mode 100644 index 00000000000000..e748a794325d63 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020 NXP + */ + +&hsio_subsys { + phyx1_lpcg: clock-controller@5f090000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f090000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_refb_clk>, <&hsio_per_clk>, + <&hsio_per_clk>, <&hsio_per_clk>; + bit-offset = <0 4 8 16>; + clock-output-names = "hsio_phyx1_pclk", + "hsio_phyx1_epcs_tx_clk", + "hsio_phyx1_epcs_rx_clk", + "hsio_phyx1_apb_clk"; + power-domains = <&pd IMX_SC_R_SERDES_1>; + }; +}; + +&pcieb { + compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; + interrupts = , + ; + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 47 4>, + <0 0 0 2 &gic 0 48 4>, + <0 0 0 3 &gic 0 49 4>, + <0 0 0 4 &gic 0 50 4>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi new file mode 100644 index 00000000000000..877aa1fe89d500 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020 NXP + */ + +&lsio_gpio0 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + interrupts = ; +}; + +&lsio_gpio1 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + interrupts = ; +}; + +&lsio_gpio2 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + interrupts = ; +}; + +&lsio_gpio3 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + interrupts = ; +}; + +&lsio_gpio4 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + interrupts = ; +}; + +&lsio_gpio5 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + interrupts = ; +}; + +&lsio_gpio6 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + interrupts = ; +}; + +&lsio_gpio7 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + interrupts = ; +}; + +&lsio_mu0 { + compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = ; +}; + +&lsio_mu1 { + compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = ; +}; + +&lsio_mu2 { + compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = ; +}; + +&lsio_mu3 { + compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = ; +}; + +&lsio_mu4 { + compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = ; +}; + +&lsio_mu5 { + compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = ; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-security.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-security.dtsi new file mode 100644 index 00000000000000..c6dfc52ac49ce2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-security.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +&sec_mu2 { + interrupts = ; +}; + +&sec_mu3 { + interrupts = ; +}; + +&sec_mu4 { + interrupts = ; +}; + +&sec_jr2 { + interrupts = ; +}; + +&sec_jr3 { + interrupts = ; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi new file mode 100644 index 00000000000000..983ffae5c2e9b8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020 NXP + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &fec1; + ethernet1 = &eqos; + gpio0 = &lsio_gpio0; + gpio1 = &lsio_gpio1; + gpio2 = &lsio_gpio2; + gpio3 = &lsio_gpio3; + gpio4 = &lsio_gpio4; + gpio5 = &lsio_gpio5; + gpio6 = &lsio_gpio6; + gpio7 = &lsio_gpio7; + i2c2 = &i2c2; + i2c3 = &i2c3; + mu1 = &lsio_mu1; + serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + can0 = &flexcan1; + can1 = &flexcan2; + can2 = &flexcan3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + }; + + cpus: cpus { + #address-cells = <2>; + #size-cells = <0>; + + /* We have 1 clusters with 4 Cortex-A35 cores */ + A35_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + #cooling-cells = <2>; + operating-points-v2 = <&a35_opp_table>; + }; + + A35_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + #cooling-cells = <2>; + operating-points-v2 = <&a35_opp_table>; + }; + + A35_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + a35_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dsp_reserved: dsp@92400000 { + reg = <0 0x92400000 0 0x2000000>; + no-map; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx8qxp-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu5 0 1 + &lsio_mu5 1 1 + &lsio_mu5 3 1>; + mub-partition = <3>; + status = "disabled"; + }; + + imx8dxl_cm4: imx8dxl_cm4@0 { + compatible = "fsl,imx8qxp-cm4"; + rsc-da = <0x90000000>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu5 0 1 + &lsio_mu5 1 1 + &lsio_mu5 3 1>; + mub-partition = <3>; + core-index = <0>; + core-id = ; + status = "disabled"; + power-domains = <&pd IMX_SC_R_M4_0_PID0>, + <&pd IMX_SC_R_M4_0_MU_1A>; + }; + + + scu { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", "tx1", "tx2", "tx3", + "rx0", "rx1", "rx2", "rx3", + "gip3"; + mboxes = <&lsio_mu1 0 0 + &lsio_mu1 0 1 + &lsio_mu1 0 2 + &lsio_mu1 0 3 + &lsio_mu1 1 0 + &lsio_mu1 1 1 + &lsio_mu1 1 2 + &lsio_mu1 1 3 + &lsio_mu1 3 3>; + + pd: imx8dxl-pd { + compatible = "fsl,imx8dxl-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + wakeup-irq = <160 163 235 236 237 228 229 230 231 238 + 239 240 166 169>; + }; + + clk: clock-controller { + compatible = "fsl,imx8dxl-clk", "fsl,scu-clk"; + #clock-cells = <2>; + clocks = <&xtal32k &xtal24m>; + clock-names = "xtal_32KHz", "xtal_24Mhz"; + }; + + iomuxc: pinctrl { + compatible = "fsl,imx8dxl-iomuxc"; + }; + + ocotp: imx8qx-ocotp { + compatible = "fsl,imx8qxp-scu-ocotp"; + #address-cells = <1>; + #size-cells = <1>; + + fec_mac0: mac@2c4 { + reg = <0x2c4 6>; + }; + + fec_mac1: mac@2c6 { + reg = <0x2c6 6>; + }; + }; + + rtc: rtc { + compatible = "fsl,imx8qxp-sc-rtc"; + }; + + watchdog { + compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; + timeout-sec = <60>; + }; + + tsens: thermal-sensor { + compatible = "fsl,imx8qxp-sc-thermal"; + tsens-num = <2>; + #thermal-sensor-cells = <1>; + }; + }; + + soc { + compatible = "fsl,imx8qxp-soc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + }; + + thermal_zones: thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 355>; + trips { + cpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + xtal32k: clock-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xtal_24MHz"; + }; + + imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; + }; + + sc_pwrkey: sc-powerkey { + compatible = "fsl,imx8-pwrkey"; + linux,keycode = ; + wakeup-source; + }; + + /* sorted in register address */ + #include "imx8-ss-v2x.dtsi" + #include "imx8-ss-security.dtsi" + #include "imx8-ss-cm40.dtsi" + #include "imx8-ss-adma.dtsi" + #include "imx8-ss-conn.dtsi" + #include "imx8-ss-ddr.dtsi" + #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-hsio.dtsi" +}; + +#include "imx8dxl-ss-adma.dtsi" +#include "imx8dxl-ss-conn.dtsi" +#include "imx8dxl-ss-lsio.dtsi" +#include "imx8dxl-ss-hsio.dtsi" +#include "imx8dxl-ss-ddr.dtsi" +#include "imx8dxl-ss-security.dtsi" + +&edma2 { + status = "okay"; +}; + + diff --git a/arch/arm64/boot/dts/freescale/imx8dxp-lpddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8dxp-lpddr4-val.dts new file mode 100644 index 00000000000000..15b28e1514012d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxp-lpddr4-val.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8dxp.dtsi" +#include "imx8x-val.dtsi" + +/ { + model = "Freescale i.MX8DXP VALIDATION"; + compatible = "fsl,imx8dxp-val", "fsl,imx8dxp", "fsl,imx8qxp"; +}; + +&usbotg3 { + dr_mode = "otg"; + extcon = <&typec_ptn5150>; + status = "okay"; +}; + +&vpu_decoder { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxp.dtsi b/arch/arm64/boot/dts/freescale/imx8dxp.dtsi new file mode 100644 index 00000000000000..fba74a31184d28 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxp.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + */ + +/dts-v1/; + +#include "imx8qxp.dtsi" + +&thermal_zones { + cpu-thermal0 { + cooling-maps { + map0 { + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&cpus { + /delete-node/ cpu@2; + /delete-node/ cpu@3; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mm-ab2.dts new file mode 100755 index 00000000000000..29f63b4eb407f3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ab2.dts @@ -0,0 +1,869 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include +#include "imx8mm.dtsi" + +/ { + model = "FSL i.MX8MM Audio board 2.0"; + compatible = "fsl,imx8mm-ab2", "fsl,imx8mm"; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rpmsg_reserved: rpmsg@0xb8000000 { + no-map; + reg = <0 0xb8000000 0 0x400000>; + }; + }; + + chosen { + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status { + label = "status"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + panel { + label = "panel"; + gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + reg_sd1_vmmc: sd1_regulator { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + startup-delay-us = <100>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + enable-active-high; + }; + + reg_ab2_ana_pwr: regulator-ab2-ana-pwr { + compatible = "regulator-fixed"; + regulator-name = "ab2_ana_pwr"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_ana_pwr>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { + compatible = "regulator-fixed"; + regulator-name = "ab2_vdd_pwr_5v0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <0>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai2>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec>; + }; + }; + + sound-ak4458 { + compatible = "fsl,imx-audio-ak4458"; + model = "ak4458-audio"; + audio-cpu = <&sai1>; + audio-codec = <&ak4458_1>, <&ak4458_2>; + ak4458,pdn-gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; + }; + + sound-ak5552 { + compatible = "fsl,imx-audio-ak5552"; + model = "ak5552-audio"; + audio-cpu = <&sai3>; + audio-codec = <&ak5552>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + phy-reset-post-delay = <150>; + phy-reset-duration = <10>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + eee-broken-1000t; + }; + }; +}; + +&sai1 { + pinctrl-names = "default", "dsd"; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-1 = <&pinctrl_sai1_dsd>; + assigned-clocks = <&clk IMX8MM_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-multi-lane; + fsl,dataline,dsd = <0 0xff 0xff 2 0xff 0x11>; + dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>; + status = "okay"; +}; + +&sai2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MM_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MM_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI3_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + status = "okay"; +}; + +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, + <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", + "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MM_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + bus-width = <4>; + vmmc-supply = <®_sd1_vmmc>; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 GPIO_ACTIVE_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck3_reg: BUCK3 { + // BUCK5 in datasheet + regulator-name = "BUCK3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "BUCK5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "BUCK6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + adv_bridge: adv7535@3d { + compatible = "adi,adv7533"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + adv7535_from_dsim: endpoint { + remote-endpoint = <&dsim_to_adv7535>; + }; + }; + }; + + pca6408_2: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&buck4_reg>; + }; + + pca6416_2: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&buck5_reg>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&buck5_reg>; + }; + + ak4458_1: ak4458@10 { + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_vdd_pwr_5v0>; + }; + + ak4458_2: ak4458@11 { + compatible = "asahi-kasei,ak4458"; + reg = <0x11>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_vdd_pwr_5v0>; + }; + + ak4458_3: ak4458@12 { + compatible = "asahi-kasei,ak4458"; + reg = <0x12>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_vdd_pwr_5v0>; + status = "disabled"; + }; + + ak5552: ak5552@13 { + compatible = "asahi-kasei,ak5552"; + reg = <0x13>; + reset-gpios = <&pca6416 2 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_vdd_pwr_5v0>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 + >; + }; + + pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 /* Touch interrupt */ + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_ab2_ana_pwr: ab2anapwrgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 + >; + }; + + pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_dsd: sai1grp_dsd { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6 + MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; + }; + + pinctrl_spdif1: spdif1grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 + MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 + MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grpgpio { + fsl,pins = < + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + attach-bridge; + }; + }; +}; + +&vpu_g1 { + status = "okay"; +}; + +&vpu_g2 { + status = "okay"; +}; + +&vpu_h1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr3l-val.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr3l-val.dts new file mode 100644 index 00000000000000..37432b208554ec --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr3l-val.dts @@ -0,0 +1,417 @@ +// SPDX-License-Identifier: GPL-2.0+ + /* + * Copyright 2018-2020 NXP + */ + +/dts-v1/; + +#include "imx8mm.dtsi" + +/ { + model = "FSL i.MX8MM DDR3L Validation board"; + compatible = "fsl,imx8mm-ddr3l-val", "fsl,imx8mm"; + + chosen { + stdout-path = &uart2; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + busfreq { + status = "okay"; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mm-val { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 + >; + }; + + pinctrl_ecspi1_cs: ecspi1cs { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56 + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56 + MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 + MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 + MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 + MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 + MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 + MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 + MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 + MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 + MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 + MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 + MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 + MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 + MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 + MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 + MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 + >; + }; + }; +}; + +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "gd25q16", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: bd71837@4b { + reg = <0x4b>; + compatible = "rohm,bd71837"; + + gpo { + rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ + }; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + bd71837,pmic-buck2-uses-i2c-dvs; + bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck7_reg: regulator@6 { + reg = <6>; + regulator-compatible = "buck7"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck8_reg: regulator@7 { + reg = <7>; + regulator-compatible = "buck8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@11 { + reg = <11>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@12 { + reg = <12>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6_reg: regulator@13 { + reg = <13>; + regulator-compatible = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo7_reg: regulator@14 { + reg = <14>; + regulator-compatible = "ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&mu { + status = "okay"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + * --0xb8000000~0xb800ffff: pingpong + */ + vdev-nums = <1>; + reg = <0x0 0xb8000000 0x0 0x10000>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "host"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; + nand-on-flash-bbt; +}; + +&A53_0 { + arm-supply = <&buck2_reg>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67191.dts new file mode 100644 index 00000000000000..2373442639af9a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67191.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include "imx8mm-ddr4-evk-revb.dts" + +&adv_bridge { + status = "disabled"; +}; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + panel-width-mm = <68>; + panel-height-mm = <121>; + status = "okay"; + }; +}; + +&i2c2 { + synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb.dts new file mode 100644 index 00000000000000..d442c9e8918e3c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8mm-ddr4-evk.dts" + +/ { + model = "FSL i.MX8MM DDR4 EVK RevB board"; +}; + +/* + * External OSC is used as PCIe REFCLK on RevC board. + * Use the -revb.dts file to distiguish the different + * HW design. + */ +&pcie0{ + ext_osc = <0>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67191.dts new file mode 100644 index 00000000000000..9df67a9b26676b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67191.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mm-ddr4-evk.dts" + +&adv_bridge { + status = "disabled"; +}; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + panel-width-mm = <68>; + panel-height-mm = <121>; + status = "okay"; + }; +}; + +&i2c2 { + synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts new file mode 100644 index 00000000000000..53e6397b4a78c4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +/dts-v1/; + +#include "imx8mm-evk.dts" + +/ { + model = "FSL i.MX8MM DDR4 EVK with CYW43455 WIFI/BT board"; + + leds { + pinctrl-0 = <&pinctrl_gpio_led_2>; + + status { + gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; + }; + }; + + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_gpio>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + }; +}; + +&iomuxc { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 + MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 + MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x00000096 + MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 + MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 + MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 + MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 + MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 + MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 + MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 + MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 + MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 + MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 + MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 + MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 + MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 + >; + }; + + pinctrl_gpio_led_2: gpioled2grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 + >; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +®_sd1_vmmc { + status = "disabled"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>; + cap-power-off-card; + /delete-property/ vmmc-supply; + mmc-pwrseq = <&usdhc1_pwrseq>; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&usdhc3 { + status = "disabled"; +}; + +&flexspi { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-revE.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-revE.dts new file mode 100644 index 00000000000000..ec4108c4c21788 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-revE.dts @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mm-evk.dts" + +/ { + mic_leds { + compatible = "gpio-leds"; + mic0 { + label = "mic0"; + gpios = <&pca9555 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic1 { + label = "mic1"; + gpios = <&pca9555 7 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic2 { + label = "mic2"; + gpios = <&pca9555 6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic3 { + label = "mic3"; + gpios = <&pca9555 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic4 { + label = "mic4"; + gpios = <&pca9555 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic5 { + label = "mic5"; + gpios = <&pca9555 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic6 { + label = "mic6"; + gpios = <&pca9555 4 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic7 { + label = "mic7"; + gpios = <&pca9555 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + sw_keys { + compatible = "gpio-keys"; + + sw4: volume_down { + label = "Volume Down"; + gpios = <&pca9555 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + sw3: volume_up { + label = "Volume Up"; + gpios = <&pca9555 15 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + sw2: volume_mute { + label = "Volume Mute"; + gpios = <&pca9555 16 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + sw1: key_act { + label = "Key Act"; + gpios = <&pca9555 17 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + reg_vddext_3v3: regulator-vddext { + compatible = "regulator-fixed"; + regulator-name = "VDDEXT_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&iomuxc { + pinctrl_swpdm_mute_irq: swpdm_mute_grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x19 + >; + }; + + pinctrl_pushbutton_irq: pushbutton_grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 + >; + }; +}; + +&i2c3 { + pca9555: gpio@21 { + compatible = "nxp,pca9555"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pushbutton_irq>; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio5>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_vddext_3v3>; + status = "okay"; + }; +}; + +&uart3 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-swpdm.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-swpdm.dts new file mode 100644 index 00000000000000..3c0ca3e5a28dcb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-swpdm.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mm-evk-8mic-revE.dts" + +/ { + sound-micfil { + status = "disabled"; + }; + + sound-swpdm { + compatible = "fsl,imx-pdm-mic"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_swpdm_mute_irq>; + mute-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + model = "imx-swpdm-audio"; + audio-cpu = <&sai5>; + decimation = <128>; + status = "okay"; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-ak4497.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-ak4497.dts new file mode 100644 index 00000000000000..18aacba546f639 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-ak4497.dts @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mm-evk.dts" + +/ { + sound-ak4458 { + status = "disabled"; + }; + + sound-ak4497 { + status = "okay"; + }; +}; + +&iomuxc { + pinctrl_sai1_pcm: sai1grp_pcm { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_dsd: sai1grp_dsd { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; +}; + +&sai1 { + pinctrl-names = "default", "dsd"; + pinctrl-0 = <&pinctrl_sai1_pcm>; + pinctrl-1 = <&pinctrl_sai1_dsd>; + assigned-clocks = <&clk IMX8MM_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>; + assigned-clock-rates = <22579200>; + fsl,sai-multi-lane; + fsl,dataline,dsd = <0 0xff 0x11>; + dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>; + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-ak5558.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-ak5558.dts new file mode 100644 index 00000000000000..4d3da8e33688c3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-ak5558.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + + +#include "imx8mm-evk.dts" + +/ { + sound-ak5558 { + status = "okay"; + }; + sound-micfil { + status = "disabled"; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-audio-tdm.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-audio-tdm.dts new file mode 100644 index 00000000000000..7e34cd63f83b22 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-audio-tdm.dts @@ -0,0 +1,25 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mm-evk-ak5558.dts" + +/ { + sound-ak4458 { + fsl,tdm; + }; + + sound-ak5558 { + fsl,tdm; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-inmate.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-inmate.dts new file mode 100644 index 00000000000000..fe9d9613104558 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-inmate.dts @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include + +/ { + model = "Freescale i.MX8MM EVK"; + compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial3 = &uart4; + mmc2 = &usdhc3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + clk_dummy: clock@7 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + /* The clocks are configured by 1st OS */ + clk_200m: clock@8 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "200m"; + }; + clk_266m: clock@9 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <266000000>; + clock-output-names = "266m"; + }; + clk_80m: clock@10 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <80000000>; + clock-output-names = "80m"; + }; + + osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + pci@bb800000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, + <0 0 0 3 &gic GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, + <0 0 0 4 &gic GIC_SPI 77 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xbb800000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x3e000000>; + + aips3: bus@30800000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x30800000 0x30800000 0x400000>, + <0x8000000 0x8000000 0x10000000>; + + uart4: serial@30a60000 { + compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = ; + status = "disabled"; + }; + + usdhc3: mmc@30b60000 { + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = ; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + }; + }; +}; + +&uart4 { + clocks = <&osc_24m>, + <&osc_24m>; + clock-names = "ipg", "per"; + /delete-property/ dmas; + /delete-property/ dmas-names; + status = "okay"; +}; + +&usdhc3 { + clocks = <&clk_dummy>, + <&clk_266m>, + <&clk_200m>; + /delete-property/assigned-clocks; + /delete-property/assigned-clock-rates; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-revb.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-revb.dts new file mode 100644 index 00000000000000..1f5ad5f07dc206 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-revb.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8mm-evk.dts" + +/ { + model = "FSL i.MX8MM LPDDR4 EVK RevB board"; +}; + +/* + * External OSC is used as PCIe REFCLK on RevC board. + * Use the -revb.dts file to distiguish the different + * HW design. + */ +&pcie0{ + ext_osc = <0>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67191.dts new file mode 100644 index 00000000000000..d7a2cedf7fc27c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67191.dts @@ -0,0 +1,35 @@ +#include "imx8mm-evk.dts" + +&adv_bridge { + status = "disabled"; +}; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + panel-width-mm = <68>; + panel-height-mm = <121>; + status = "okay"; + }; +}; + +&i2c2 { + synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-root.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-root.dts new file mode 100644 index 00000000000000..c414dd91c95e15 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-root.dts @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mm-evk.dts" + +/ { + interrupt-parent = <&gic>; +}; + +&cpu_pd_wait { + /delete-property/ compatible; + /*arm,psci-suspend-param = <0x0>;*/ +}; + +&clk { + init-on-array = ; +}; + +&iomuxc { + /* + * Used for the 2nd Linux. + * TODO: M4 may use these pins. + */ + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; +}; + +&{/busfreq} { + /* Disable busfreq, to avoid 1st Linux busfreq crash other inmates */ + status = "disabled"; +}; + +&{/reserved-memory} { + + ivshmem_reserved: ivshmem@bbb00000 { + no-map; + reg = <0 0xbbb00000 0x0 0x00100000>; + }; + + ivshmem2_reserved: ivshmem2@bba00000 { + no-map; + reg = <0 0xbba00000 0x0 0x00100000>; + }; + + pci_reserved: pci@bb800000 { + no-map; + reg = <0 0xbb800000 0x0 0x00200000>; + }; + + loader_reserved: loader@bb700000 { + no-map; + reg = <0 0xbb700000 0x0 0x00100000>; + }; + + jh_reserved: jh@b7c00000 { + no-map; + reg = <0 0xb7c00000 0x0 0x00400000>; + }; + + /* 512MB */ + inmate_reserved: inmate@93c00000 { + no-map; + reg = <0 0x93c00000 0x0 0x24000000>; + }; +}; + +&uart2 { + /* uart2 is used by the 2nd OS, so configure pin and clk */ + pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MM_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MM_CLK_24M>; +}; + +&usdhc3 { + status = "disabled"; +}; + +&usdhc2 { + /* sdhc3 is used by 2nd linux, configure the pin */ + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-rpmsg.dts new file mode 100644 index 00000000000000..23cc2d5a39a887 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-rpmsg.dts @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8mm-evk.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m4_reserved: m4@0x80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + vdev0vring0: vdev0vring0@b8000000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@b8008000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8008000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@b8400000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8400000 0 0x100000>; + no-map; + }; + }; + + bt_sco_codec: bt_sco_codec { + status = "disabled"; + }; + + sound-bt-sco { + status = "disabled"; + }; + + sound-wm8524 { + status = "disabled"; + }; + + wm8524: audio-codec { + status = "disabled"; + }; + + rpmsg_i2s: rpmsg-i2s { + compatible = "fsl,imx8mq-rpmsg-i2s"; + /* the audio device index in m4 domain */ + fsl,audioindex = <0> ; + fsl,dma-buffer-size = <0x6000000>; + fsl,enable-lpa; + status = "okay"; + }; + + sound-rpmsg { + compatible = "fsl,imx-audio-rpmsg"; + model = "ak4497-audio"; + cpu-dai = <&rpmsg_i2s>; + rpmsg-out; + }; + + imx8mm-cm4 { + compatible = "fsl,imx8mm-cm4"; + rsc-da = <0xb8000000>; + clocks = <&clk IMX8MM_CLK_M4_DIV>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>; + syscon = <&src>; + }; +}; + +&clk { + init-on-array = ; +}; + +/* + * ATTENTION: M4 may use IPs like below + * ECSPI0/ECSPI2, GPIO1/GPIO5, GPT1, I2C3, I2S3, WDOG1, UART4, PWM3, SDMA1 + */ + +&i2c3 { + status = "disabled"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + * --0xb8000000~0xb800ffff: pingpong + */ + vdev-nums = <1>; + reg = <0x0 0xb8000000 0x0 0x10000>; + memory-region = <&vdevbuffer>; + status = "disabled"; +}; + +&sdma1{ + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; + +&sai3 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&sai2 { + status = "disabled"; +}; + +&flexspi { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-usd-wifi.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-usd-wifi.dts new file mode 100644 index 00000000000000..175020b7c9a5c8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-usd-wifi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-evk.dts" + +&usdhc2 { + /delete-property/ cd-gpios; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts old mode 100644 new mode 100755 index b9f8b7aac8ff17..50487c7f49cdda --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts @@ -12,6 +12,17 @@ model = "FSL i.MX8MM EVK board"; compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rpmsg_reserved: rpmsg@0xb8000000 { + no-map; + reg = <0 0xb8000000 0 0x400000>; + }; + }; + chosen { stdout-path = &uart2; }; @@ -28,6 +39,31 @@ }; }; + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + reg_sd1_vmmc: sd1_regulator { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + startup-delay-us = <100>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -36,7 +72,18 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + enable-active-high; + }; + + reg_audio_board: regulator-audio-board { + compatible = "regulator-fixed"; + regulator-name = "EXT_PWREN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; enable-active-high; + startup-delay-us = <300000>; + gpio = <&pca6416 1 GPIO_ACTIVE_HIGH>; }; wm8524: audio-codec { @@ -47,6 +94,30 @@ wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; }; + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <0>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai2>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec>; + }; + }; + sound-wm8524 { compatible = "simple-audio-card"; simple-audio-card,name = "wm8524-audio"; @@ -71,12 +142,60 @@ clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; }; }; + + sound-ak4458 { + compatible = "fsl,imx-audio-ak4458"; + model = "ak4458-audio"; + audio-cpu = <&sai1>; + audio-codec = <&ak4458_1>, <&ak4458_2>; + ak4458,pdn-gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; + }; + + sound-ak5558 { + compatible = "fsl,imx-audio-ak5558"; + model = "ak5558-audio"; + audio-cpu = <&sai5>; + audio-codec = <&ak5558>; + status = "disabled"; + }; + + sound-ak4497 { + compatible = "fsl,imx-audio-ak4497"; + model = "ak4497-audio"; + audio-cpu = <&sai1>; + audio-codec = <&ak4497>; + status = "disabled"; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; + }; + + sound-micfil { + compatible = "fsl,imx-audio-micfil"; + model = "imx-audio-micfil"; + cpu-dai = <&micfil>; + }; }; &A53_0 { cpu-supply = <&buck2_reg>; }; +&csi1_bridge { + fsl,mipi-mode; + status = "okay"; + port { + csi1_ep: endpoint { + remote-endpoint = <&csi1_mipi_ep>; + }; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; @@ -92,10 +211,27 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; }; }; }; +&pcie0{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + disable-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + ext_osc = <1>; + reserved-region = <&rpmsg_reserved>; + status = "okay"; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -105,22 +241,118 @@ status = "okay"; }; +&sai2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MM_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default", "dsd"; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-1 = <&pinctrl_sai1_dsd>; + assigned-clocks = <&clk IMX8MM_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-multi-lane; + fsl,dataline,dsd = <0 0xff 0xff 2 0xff 0x11>; + dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>; + status = "okay"; +}; + +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MM_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-asynchronous; + status = "disabled"; +}; + +&sai6 { + fsl,sai-monitor-spdif; + fsl,sai-asynchronous; + status = "okay"; +}; + +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, + <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", + "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; + status = "okay"; +}; + +&micfil { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MM_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + &uart2 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; status = "okay"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MM_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + &usbotg1 { dr_mode = "otg"; hnp-disable; srp-disable; adp-disable; usb-role-switch; + picophy,pre-emp-curr-control = <3>; + picophy,dc-vol-level-adjust = <7>; status = "okay"; port { @@ -130,6 +362,19 @@ }; }; +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + bus-width = <4>; + vmmc-supply = <®_sd1_vmmc>; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + status = "okay"; +}; + &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; @@ -158,6 +403,22 @@ status = "okay"; }; +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -232,7 +493,7 @@ ldo1_reg: LDO1 { regulator-name = "LDO1"; regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; + regulator-max-microvolt = <1900000>; regulator-boot-on; regulator-always-on; }; @@ -278,6 +539,24 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + adv_bridge: adv7535@3d { + compatible = "adi,adv7533"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + adv7535_from_dsim: endpoint { + remote-endpoint = <&dsim_to_adv7535>; + }; + }; + }; + ptn5110: tcpc@50 { compatible = "nxp,ptn5110"; pinctrl-names = "default"; @@ -308,9 +587,89 @@ }; }; +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&buck4_reg>; + }; + + ak4458_1: ak4458@10 { + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + }; + + ak4458_2: ak4458@12 { + compatible = "asahi-kasei,ak4458"; + reg = <0x12>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + }; + + ak5558: ak5558@13 { + compatible = "asahi-kasei,ak5558"; + reg = <0x13>; + ak5558,pdn-gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + }; + + ak4497: ak4497@11 { + compatible = "asahi-kasei,ak4497"; + reg = <0x11>; + ak4497,pdn-gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + }; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>; + clocks = <&clk IMX8MM_CLK_CLKO1>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; + assigned-clock-parents = <&clk IMX8MM_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + pwn-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5640_mipi1_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; + }; + }; + }; +}; + &iomuxc { pinctrl-names = "default"; + pinctrl_csi_pwn: csi_pwn_grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + >; + }; + + pinctrl_csi_rst: csi_rst_grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 @@ -331,6 +690,17 @@ >; }; + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + pinctrl_gpio_led: gpioledgrp { fsl,pins = < MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 @@ -357,6 +727,33 @@ >; }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 + >; + }; + + pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 /* Touch int */ + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 /* open drain, pull up */ + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 + MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 + >; + }; + pinctrl_pmic: pmicirq { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 @@ -369,6 +766,15 @@ >; }; + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 + >; + }; + pinctrl_sai3: sai3grp { fsl,pins = < MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 @@ -378,12 +784,87 @@ >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_dsd: sai1grp_dsd { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6 + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 + MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6 + >; + }; + + pinctrl_spdif1: spdif1grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + pinctrl_typec1: typec1grp { fsl,pins = < MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 >; }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 @@ -391,6 +872,54 @@ >; }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 + MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 + MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grpgpio { + fsl,pins = < + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + pinctrl_usdhc2_gpio: usdhc2grpgpio { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 @@ -487,3 +1016,53 @@ >; }; }; + +&lcdif { + status = "okay"; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port { + mipi1_sensor_ep: endpoint@1 { + remote-endpoint = <&ov5640_mipi1_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + }; + + csi1_mipi_ep: endpoint@2 { + remote-endpoint = <&csi1_ep>; + }; + }; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + attach-bridge; + }; + }; +}; + +&vpu_g1 { + status = "okay"; +}; + +&vpu_g2 { + status = "okay"; +}; + +&vpu_h1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi old mode 100644 new mode 100755 index fde1849d36ca5f..f22417f4abbf0d --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -4,9 +4,11 @@ */ #include +#include #include #include #include +#include #include #include "imx8mm-pinfunc.h" @@ -38,6 +40,11 @@ gpio2 = &gpio3; gpio3 = &gpio4; gpio4 = &gpio5; + sai1 = &sai1; + sai2 = &sai2; + sai3 = &sai3; + sai5 = &sai5; + sai6 = &sai6; }; cpus { @@ -69,6 +76,7 @@ nvmem-cells = <&cpu_speed_grade>; nvmem-cell-names = "speed_grade"; cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_1: cpu@1 { @@ -81,6 +89,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_2: cpu@2 { @@ -93,6 +102,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_3: cpu@3 { @@ -105,6 +115,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_L2: l2-cache0 { @@ -126,7 +137,7 @@ opp-1600000000 { opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <900000>; + opp-microvolt = <950000>; opp-supported-hw = <0xc>, <0x7>; clock-latency-ns = <150000>; opp-suspend; @@ -146,6 +157,22 @@ reg = <0x0 0x40000000 0 0x80000000>; }; + resmem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x40000000 0 0x60000000>; + linux,cma-default; + }; + }; + + osc_32k: clock-osc-32k { compatible = "fixed-clock"; #clock-cells = <0>; @@ -200,6 +227,110 @@ interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; }; + power-domains { + compatible = "simple-bus"; + /* HSIO SS */ + hsiomix_pd: hsiomix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <0>; + domain-name = "hsiomix"; + clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; + }; + + pcie_pd: pcie-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <1>; + domain-name = "pcie"; + parent-domains = <&hsiomix_pd>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>; + }; + + usb_otg1_pd: usbotg1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <2>; + domain-name = "usb_otg1"; + parent-domains = <&hsiomix_pd>; + }; + + usb_otg2_pd: usbotg2-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <3>; + domain-name = "usb_otg2"; + parent-domains = <&hsiomix_pd>; + }; + + /* GPU SS */ + gpumix_pd: gpumix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <4>; + domain-name = "gpumix"; + clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU_AHB>, + <&clk IMX8MM_CLK_GPU2D_ROOT>, + <&clk IMX8MM_CLK_GPU3D_ROOT>; + }; + + /* VPU SS */ + vpumix_pd: vpumix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <5>; + domain-name = "vpumix"; + clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + }; + + vpu_g1_pd: vpug1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <6>; + domain-name = "vpu_g1"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>; + }; + + vpu_g2_pd: vpug2-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <7>; + domain-name = "vpu_g2"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>; + }; + + vpu_h1_pd: vpuh1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <8>; + domain-name = "vpu_h1"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MM_CLK_VPU_H1_ROOT>; + }; + + /* DISP SS */ + dispmix_pd: dispmix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <9>; + domain-name = "dispmix"; + clocks = <&clk IMX8MM_CLK_DISP_ROOT>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>; + }; + + mipi_pd: mipi-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <10>; + domain-name = "mipi"; + parent-domains = <&dispmix_pd>; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , /* Physical Secure */ @@ -210,6 +341,38 @@ arm,no-tick-in-suspend; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu>; + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + usbphynop1: usbphynop1 { compatible = "usb-nop-xceiv"; clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; @@ -226,12 +389,36 @@ clock-names = "main_clk"; }; + busfreq { /* BUSFREQ */ + compatible = "fsl,imx_busfreq"; + clocks = <&clk IMX8MM_DRAM_PLL_OUT>, <&clk IMX8MM_CLK_DRAM_ALT>, + <&clk IMX8MM_CLK_DRAM_APB>, <&clk IMX8MM_CLK_DRAM_APB>, + <&clk IMX8MM_CLK_DRAM_CORE>, <&clk IMX8MM_CLK_DRAM_ALT_ROOT>, + <&clk IMX8MM_SYS_PLL1_40M>, <&clk IMX8MM_SYS_PLL1_100M>, + <&clk IMX8MM_SYS_PLL2_333M>, <&clk IMX8MM_CLK_NOC>, + <&clk IMX8MM_CLK_AHB>, <&clk IMX8MM_CLK_MAIN_AXI>, + <&clk IMX8MM_CLK_24M>, <&clk IMX8MM_SYS_PLL1_800M>, + <&clk IMX8MM_DRAM_PLL>; + clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", + "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m", + "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m", + "sys_pll1_800m", "dram_pll_div"; + interrupts = , , + , ; + interrupt-name = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3"; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + caam_sm: caam-sm@100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; @@ -242,12 +429,13 @@ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30010000 0x10000>; interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI1_IPG>, + clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; dma-names = "rx", "tx"; + fsl,dataline = <0 0xff 0xff>; status = "disabled"; }; @@ -255,10 +443,10 @@ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30020000 0x10000>; interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI2_IPG>, + clocks = <&clk IMX8MM_CLK_SAI2_IPG>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_SAI2_ROOT>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; dma-names = "rx", "tx"; status = "disabled"; @@ -269,10 +457,10 @@ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30030000 0x10000>; interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI3_IPG>, + clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_SAI3_ROOT>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; dma-names = "rx", "tx"; status = "disabled"; @@ -282,12 +470,13 @@ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30050000 0x10000>; interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI5_IPG>, + clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; dma-names = "rx", "tx"; + fsl,dataline = <0 0xf 0xf>; status = "disabled"; }; @@ -295,15 +484,58 @@ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30060000 0x10000>; interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI6_IPG>, + clocks = <&clk IMX8MM_CLK_SAI6_IPG>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_SAI6_ROOT>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; dma-names = "rx", "tx"; status = "disabled"; }; + micfil: micfil@30080000 { + compatible = "fsl,imx8mm-micfil"; + reg = <0x30080000 0x10000>; + interrupts = , + , + , + ; + clocks = <&clk IMX8MM_CLK_PDM_IPG>, + <&clk IMX8MM_CLK_PDM_ROOT>, + <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>, + <&clk IMX8MM_CLK_EXT3>; + clock-names = "ipg_clk", "ipg_clk_app", + "pll8k", "pll11k", "clkext3"; + dmas = <&sdma2 24 25 0x80000000>; + dma-names = "rx"; + status = "disabled"; + }; + + spdif1: spdif@30090000 { + compatible = "fsl,imx8mm-spdif"; + reg = <0x30090000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */ + <&clk IMX8MM_CLK_24M>, /* rxtx0 */ + <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8MM_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + gpio1: gpio@30200000 { compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; reg = <0x30200000 0x10000>; @@ -369,6 +601,13 @@ gpio-ranges = <&iomuxc 0 119 30>; }; + tmu: tmu@30260000 { + compatible = "fsl,imx8mm-tmu"; + reg = <0x30260000 0x10000>; + clocks = <&clk IMX8MM_CLK_TMU_ROOT>; + #thermal-sensor-cells = <0>; + }; + wdog1: watchdog@30280000 { compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; reg = <0x30280000 0x10000>; @@ -421,12 +660,12 @@ }; gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; + compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; }; - ocotp: ocotp-ctrl@30350000 { - compatible = "fsl,imx8mm-ocotp", "fsl,imx7d-ocotp", "syscon"; + ocotp: efuse@30350000 { + compatible = "fsl,imx8mm-ocotp", "syscon"; reg = <0x30350000 0x10000>; clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; /* For nvmem subnodes */ @@ -436,6 +675,10 @@ cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; + + fec_mac_address: mac-address@640 { + reg = <0x90 6>; + }; }; anatop: anatop@30360000 { @@ -443,6 +686,20 @@ reg = <0x30360000 0x10000>; }; + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + }; + snvs: snvs@30370000 { compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; reg = <0x30370000 0x10000>; @@ -461,6 +718,8 @@ compatible = "fsl,sec-v4.0-pwrkey"; regmap = <&snvs>; interrupts = ; + clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; + clock-names = "snvs"; linux,keycode = ; wakeup-source; status = "disabled"; @@ -564,10 +823,24 @@ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x30800000 0x30800000 0x400000>; + ranges = <0x30800000 0x30800000 0x400000>, + <0x8000000 0x8000000 0x10000000>; + + flexspi: spi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mm-fspi"; + reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = ; + clocks = <&clk IMX8MM_CLK_QSPI_ROOT>, + <&clk IMX8MM_CLK_QSPI_ROOT>; + clock-names = "fspi", "fspi_en"; + status = "disabled"; + }; ecspi1: spi@30820000 { - compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; + compatible = "fsl,imx8mm-ecspi", "fsl,imx6ul-ecspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x30820000 0x10000>; @@ -581,7 +854,7 @@ }; ecspi2: spi@30830000 { - compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; + compatible = "fsl,imx8mm-ecspi", "fsl,imx6ul-ecspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x30830000 0x10000>; @@ -595,7 +868,7 @@ }; ecspi3: spi@30840000 { - compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; + compatible = "fsl,imx8mm-ecspi", "fsl,imx6ul-ecspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x30840000 0x10000>; @@ -642,6 +915,36 @@ status = "disabled"; }; + crypto: crypto@30900000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0x30900000 0x40000>; + ranges = <0 0x30900000 0x40000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_AHB>, + <&clk IMX8MM_CLK_IPG_ROOT>; + clock-names = "aclk", "ipg"; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + + sec_jr2: jr@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = ; + }; + }; + i2c1: i2c@30a20000 { compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; #address-cells = <1>; @@ -694,6 +997,15 @@ status = "disabled"; }; + mu: mu@30aa0000 { + compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_MU_ROOT>; + clock-names = "mu"; + #mbox-cells = <2>; + }; + usdhc1: mmc@30b40000 { compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b40000 0x10000>; @@ -752,7 +1064,7 @@ }; fec1: ethernet@30be0000 { - compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec"; + compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; reg = <0x30be0000 0x10000>; interrupts = , , @@ -774,6 +1086,11 @@ assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; + nvmem-cells = <&fec_mac_address>; + nvmem-cell-names = "mac-address"; + nvmem_macaddr_swap; + stop-mode = <&gpr 0x10 3>; + fsl,wakeup_irq = <2>; status = "disabled"; }; @@ -785,6 +1102,100 @@ #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; + lcdif: lcdif@32e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-lcdif"; + reg = <0x32e00000 0x10000>; + clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "pix", "disp-axi", "disp-apb"; + assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, + <&clk IMX8MM_CLK_DISP_AXI>, + <&clk IMX8MM_CLK_DISP_APB>; + assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>, + <&clk IMX8MM_SYS_PLL2_1000M>, + <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rate = <594000000>, <500000000>, <200000000>; + interrupts = ; + lcdif-gpr = <&dispmix_gpr>; + resets = <&lcdif_resets>; + power-domains = <&dispmix_pd>; + status = "disabled"; + + lcdif_disp0: port@0 { + reg = <0>; + + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + mipi_dsi: mipi_dsi@32e10000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-mipi-dsim"; + reg = <0x32e10000 0x400>; + clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + clock-names = "cfg", "pll-ref"; + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_VIDEO_PLL1_OUT>; + assigned-clock-rates = <266000000>, <594000000>; + interrupts = ; + dsi-gpr = <&dispmix_gpr>; + resets = <&mipi_dsi_resets>; + power-domains = <&mipi_pd>; + status = "disabled"; + + port@0 { + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + + csi1_bridge: csi1_bridge@32e20000 { + compatible = "fsl,imx8mm-csi", "fsl,imx8mq-csi", "fsl,imx6s-csi"; + reg = <0x32e20000 0x1000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_CSI1_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + power-domains = <&dispmix_pd>; + status = "disabled"; + }; + + mipi_csi_1: mipi_csi@32e30000 { + compatible = "fsl,imx8mm-mipi-csi"; + reg = <0x32e30000 0x1000>; + interrupts = ; + clock-frequency = <333000000>; + clocks = <&clk IMX8MM_CLK_CSI1_CORE>, + <&clk IMX8MM_CLK_CSI1_PHY_REF>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "mipi_clk", "phy_clk", "disp_axi", "disp_apb"; + bus-width = <4>; + power-domains = <&mipi_pd>; + status = "disabled"; + }; + + dispmix_gpr: display-gpr@32e28000 { + compatible = "fsl, imx8mm-iomuxc-gpr", "syscon"; + reg = <0x32e28000 0x100>; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&lcdif_disp0>; + }; + usbotg1: usb@32e40000 { compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; reg = <0x32e40000 0x200>; @@ -795,6 +1206,7 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; fsl,usbphy = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; + power-domains = <&usb_otg1_pd>; status = "disabled"; }; @@ -814,6 +1226,7 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; fsl,usbphy = <&usbphynop2>; fsl,usbmisc = <&usbmisc2 0>; + power-domains = <&usb_otg2_pd>; status = "disabled"; }; @@ -823,6 +1236,10 @@ reg = <0x32e50200 0x200>; }; + pcie_phy: pcie-phy@32f00000 { + compatible = "fsl,imx7d-pcie-phy"; + reg = <0x32f00000 0x10000>; + }; }; dma_apbh: dma-controller@33000000 { @@ -854,6 +1271,39 @@ status = "disabled"; }; + pcie0: pcie@33800000 { + compatible = "fsl,imx8mm-pcie", "snps,dw-pcie"; + reg = <0x33800000 0x400000>, + <0x1ff00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + num-viewport = <4>; + interrupts = , + ; /* eDMA */ + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + fsl,max-link-speed = <2>; + power-domains = <&pcie_pd>; + resets = <&src IMX8MQ_RESET_PCIEPHY>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "clkreq", "turnoff"; + fsl,imx7d-pcie-phy = <&pcie_phy>; + status = "disabled"; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */ @@ -870,4 +1320,169 @@ interrupts = ; }; }; + + dispmix-reset { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dispmix_sft_rstn: dispmix-sft-rstn@32e28000 { + compatible = "fsl,imx8mm-dispmix-sft-rstn"; + reg = <0x0 0x32e28000 0x0 0x4>; + clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "disp_apb_root_clk"; + active_low; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + + dispmix_clk_en: dispmix-clk-en@32e28004 { + compatible = "fsl,imx8mm-dispmix-clk-en"; + reg = <0x0 0x32e28004 0x0 0x4>; + clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "disp_apb_root_clk"; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + + dispmix_mipi_rst: dispmix-mipi-rst@32e28008 { + compatible = "fsl,imx8mm-dispmix-mipi-rst"; + reg = <0x0 0x32e28008 0x0 0x4>; + clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "disp_apb_root_clk"; + active_low; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + }; + + lcdif_resets: lcdif-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + lcdif-clk-enable { + compatible = "lcdif,clk-enable"; + resets = <&dispmix_clk_en IMX8MM_LCDIF_APB_CLK_EN>, + <&dispmix_clk_en IMX8MM_LCDIF_PIXEL_CLK_EN>; + }; + }; + + mipi_dsi_resets: mipi-dsi-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + dsi-soft-resetn { + compatible = "dsi,soft-resetn"; + resets = <&dispmix_sft_rstn IMX8MM_MIPI_DSI_I_PRESET>; + }; + + dsi-clk-enable { + compatible = "dsi,clk-enable"; + resets = <&dispmix_clk_en IMX8MM_MIPI_DSI_CLKREF_EN>, + <&dispmix_clk_en IMX8MM_MIPI_DSI_PCLK_EN>; + }; + + dsi-mipi-reset { + compatible = "dsi,mipi-reset"; + resets = <&dispmix_mipi_rst IMX8MM_MIPI_M_RESET>; + }; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx8mq-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + status = "disabled"; + }; + + vpu_h1: vpu_h1@38320000 { + compatible = "nxp,imx8mm-hantro-h1"; + reg = <0x0 0x38320000 0x0 0x10000>; + reg-names = "regs_hantro_h1"; + interrupts = ; + interrupt-names = "irq_hantro_h1"; + clocks = <&clk IMX8MM_CLK_VPU_H1_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + clock-names = "clk_hantro_h1", "clk_hantro_h1_bus"; + assigned-clocks = <&clk IMX8MM_CLK_VPU_H1>,<&clk IMX8MM_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <600000000>, <800000000>; + power-domains = <&vpu_h1_pd>; + status = "disabled"; + }; + + vpu_g1: vpu_g1@38300000 { + compatible = "nxp,imx8mm-hantro"; + reg = <0x0 0x38300000 0x0 0x100000>; + reg-names = "regs_hantro"; + interrupts = ; + interrupt-names = "irq_hantro"; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + clock-names = "clk_hantro", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>, <&clk IMX8MM_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <600000000>, <800000000>; + power-domains = <&vpu_g1_pd>; + status = "disabled"; + }; + + vpu_g2: vpu_g2@38310000 { + compatible = "nxp,imx8mm-hantro"; + reg = <0x0 0x38310000 0x0 0x100000>; + reg-names = "regs_hantro"; + interrupts = ; + interrupt-names = "irq_hantro"; + clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + clock-names = "clk_hantro", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MM_CLK_VPU_G2>, <&clk IMX8MM_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <600000000>, <800000000>; + power-domains = <&vpu_g2_pd>; + status = "disabled"; + }; + + gpu: gpu@38000000 { + compatible ="fsl,imx8mm-gpu", "fsl,imx6q-gpu"; + reg = <0x0 0x38000000 0x0 0x8000>, <0x0 0x38008000 0x0 0x8000>, + <0x0 0x40000000 0x0 0x80000000>, <0x0 0x0 0x0 0x8000000>; + reg-names = "iobase_3d", "iobase_2d", + "phys_baseaddr", "contiguous_mem"; + interrupts = , + ; + interrupt-names = "irq_3d", "irq_2d"; + clocks = <&clk IMX8MM_CLK_GPU3D_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU_AHB>, + <&clk IMX8MM_CLK_GPU2D_ROOT>, + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU_AHB>; + clock-names = "gpu3d_clk", "gpu3d_shader_clk", + "gpu3d_axi_clk", "gpu3d_ahb_clk", + "gpu2d_clk", "gpu2d_axi_clk", + "gpu2d_ahb_clk"; + assigned-clocks = <&clk IMX8MM_CLK_GPU3D_SRC>, + <&clk IMX8MM_CLK_GPU2D_SRC>, + <&clk IMX8MM_CLK_GPU_AXI>, + <&clk IMX8MM_CLK_GPU_AHB>, + <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>, + <&clk IMX8MM_GPU_PLL_OUT>, + <&clk IMX8MM_SYS_PLL1_800M>, + <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <0>, <0>,<400000000>,<1000000000>; + + power-domains = <&gpumix_pd>; + + status = "disabled"; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mn-ab2.dts new file mode 100644 index 00000000000000..ac7c0402953302 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-ab2.dts @@ -0,0 +1,834 @@ +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include +#include "imx8mn.dtsi" + +/ { + model = "NXP i.MX8MNano Audio board 2.0"; + compatible = "fsl,imx8mn-ab2", "fsl,imx8mn"; + + chosen { + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status { + label = "status"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + panel { + label = "panel"; + gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_gpio>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + reg_ab2_ana_pwr: regulator-ab2-ana-pwr { + compatible = "regulator-fixed"; + regulator-name = "ab2_ana_pwr"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_ana_pwr>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { + compatible = "regulator-fixed"; + regulator-name = "ab2_vdd_pwr_5v0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + }; + + sound-ak5552 { + compatible = "fsl,imx-audio-ak5552"; + model = "ak5552-audio"; + audio-cpu = <&sai3>; + audio-codec = <&ak5552>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&clk { + assigned-clocks = <&clk IMX8MN_AUDIO_PLL1>, <&clk IMX8MN_AUDIO_PLL2>; + assigned-clock-rates = <393216000>, <361267200>; +}; + +&easrc { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx8mn-ab2 { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 + + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 + MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 + MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 + >; + }; + + pinctrl_ecspi2_cs: ecspi2cs { + fsl,pins = < + MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 + MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_ab2_ana_pwr: ab2anapwrgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 + >; + }; + + pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { + fsl,pins = < + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MN_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6 + MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0xd6 + MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; + }; + + pinctrl_spdif1: spdif1grp { + fsl,pins = < + MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 + MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 + MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 + MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grpgpio { + fsl,pins = < + MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 + MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 + >; + }; + + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 + >; + }; + + pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <500000>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + pca9450,pmic-buck2-uses-i2c-dvs; + /* Run/Standby voltage */ + pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; + + adv_bridge: adv7535@3d { + compatible = "adi,adv7533"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_from_dsim: endpoint { + remote-endpoint = <&dsim_to_adv7535>; + }; + }; + }; + + pca6408_2: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&buck5_reg>; + }; + + pca6416_2: gpio@21 { + compatible = "ti,tca6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&buck5_reg>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&buck5_reg>; + }; + + ak5552: ak5552@13 { + compatible = "asahi-kasei,ak5552"; + reg = <0x13>; + reset-gpios = <&pca6416 2 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_vdd_pwr_5v0>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + phy-reset-post-delay = <150>; + phy-reset-duration = <10>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + eee-broken-1000t; + }; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + attach-bridge; + }; + }; +}; + +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MN_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MN_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MN_CLK_SAI3_IPG>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI3_ROOT>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>, + <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + status = "okay"; +}; + +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_24M>, + <&clk IMX8MN_CLK_SPDIF1>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_AUDIO_PLL1_OUT>, <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", + "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; + status = "okay"; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MN_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>; + bus-width = <4>; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; + /delete-property/ vmmc-supply; + mmc-pwrseq = <&usdhc1_pwrseq>; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&gpu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-ab2.dts new file mode 100644 index 00000000000000..463319e93f8f22 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-ab2.dts @@ -0,0 +1,757 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include +#include "imx8mn.dtsi" + +/ { + model = "NXP i.MX8MNano DDR4 Audio board 2.0"; + compatible = "fsl,imx8mn-ddr4-ab2", "fsl,imx8mn"; + + chosen { + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status { + label = "status"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + panel { + label = "panel"; + gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_gpio>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <12000>; + enable-active-high; + }; + + reg_ab2_ana_pwr: regulator-ab2-ana-pwr { + compatible = "regulator-fixed"; + regulator-name = "ab2_ana_pwr"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_ana_pwr>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { + compatible = "regulator-fixed"; + regulator-name = "ab2_vdd_pwr_5v0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound-ak5552 { + compatible = "fsl,imx-audio-ak5552"; + model = "ak5552-audio"; + audio-cpu = <&sai3>; + audio-codec = <&ak5552>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; + }; +}; + +&clk { + assigned-clocks = <&clk IMX8MN_AUDIO_PLL1>, <&clk IMX8MN_AUDIO_PLL2>; + assigned-clock-rates = <393216000>, <361267200>; +}; + +&easrc { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 + >; + }; + + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_ab2_ana_pwr: ab2anapwrgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 + >; + }; + + pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { + fsl,pins = < + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + + pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MN_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6 + MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0xd6 + MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; + }; + + pinctrl_spdif1: spdif1grp { + fsl,pins = < + MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 + MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 + MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 + MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grpgpio { + fsl,pins = < + MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 + MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 + >; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; + + adv_bridge: adv7535@3d { + compatible = "adi,adv7533"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_from_dsim: endpoint { + remote-endpoint = <&dsim_to_adv7535>; + }; + }; + }; + + pca6408_2: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&buck4_reg>; + }; + + pca6416_2: gpio@21 { + compatible = "ti,tca6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&buck5_reg>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&buck5_reg>; + }; + + ak5552: ak5552@13 { + compatible = "asahi-kasei,ak5552"; + reg = <0x13>; + reset-gpios = <&pca6416 2 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_vdd_pwr_5v0>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + phy-reset-post-delay = <150>; + phy-reset-duration = <10>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + eee-broken-1000t; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 GPIO_ACTIVE_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "BUCK5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "BUCK6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + attach-bridge; + }; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MN_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MN_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>; + bus-width = <4>; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; + /delete-property/ vmmc-supply; + mmc-pwrseq = <&usdhc1_pwrseq>; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&gpu { + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>, + <&clk IMX8MN_CLK_GPU_SHADER_SRC>, + <&clk IMX8MN_CLK_GPU_AXI>, + <&clk IMX8MN_CLK_GPU_AHB>, + <&clk IMX8MN_GPU_PLL>, + <&clk IMX8MN_CLK_GPU_CORE_DIV>, + <&clk IMX8MN_CLK_GPU_SHADER_DIV>; + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>, + <400000000>, <400000000>; + status= "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MN_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MN_CLK_SAI3_IPG>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI3_ROOT>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>, + <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + status = "okay"; +}; + +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_24M>, + <&clk IMX8MN_CLK_SPDIF1>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_AUDIO_PLL1_OUT>, <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", + "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-ak5558.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-ak5558.dts new file mode 100644 index 00000000000000..d628182a4f7ba4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-ak5558.dts @@ -0,0 +1,36 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mn-ddr4-evk.dts" + +/ { + sound-wm8524 { + asrc-controller = <0>; + }; + sound-ak5558 { + asrc-controller = <&easrc>; + status = "okay"; + }; + sound-micfil { + status = "disabled"; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-inmate.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-inmate.dts new file mode 100644 index 00000000000000..96a7616bb3e487 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-inmate.dts @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include + +/ { + model = "Freescale i.MX8MN EVK"; + compatible = "fsl,imx8mn-evk", "fsl,imx8mm"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial3 = &uart4; + mmc2 = &usdhc3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clock-latency = <61036>; + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clock-latency = <61036>; + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + clk_dummy: clock@7 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + /* The clocks are configured by 1st OS */ + clk_200m: clock@8 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "200m"; + }; + clk_266m: clock@9 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <266000000>; + clock-output-names = "266m"; + }; + clk_80m: clock@10 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <80000000>; + clock-output-names = "80m"; + }; + + pci@bb800000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, + <0 0 0 3 &gic GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, + <0 0 0 4 &gic GIC_SPI 77 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xbb800000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x3e000000>; + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; + + aips3: bus@30800000 { + compatible = "fsl,imx8mq-aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x30800000 0x30800000 0x400000>, + <0x08000000 0x08000000 0x10000000>; + + uart4: serial@30a60000 { + compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = ; + status = "disabled"; + }; + + usdhc3: mmc@30b60000 { + compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = ; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + }; + }; +}; + +&uart4 { + clocks = <&osc_24m>, + <&osc_24m>; + clock-names = "ipg", "per"; + /delete-property/ dmas; + /delete-property/ dmas-names; + status = "okay"; +}; + +&usdhc3 { + clocks = <&clk_dummy>, + <&clk_266m>, + <&clk_200m>; + /delete-property/assigned-clocks; + /delete-property/assigned-clock-rates; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67191.dts new file mode 100644 index 00000000000000..46f344ab67bf81 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67191.dts @@ -0,0 +1,49 @@ +/* + * Copyright 2018-2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mn-ddr4-evk.dts" + +&adv_bridge { + status = "disabled"; +}; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + panel-width-mm = <68>; + panel-height-mm = <121>; + status = "okay"; + }; +}; + +&i2c2 { + synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-root.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-root.dts new file mode 100644 index 00000000000000..9e71421e4f4b28 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-root.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mn-ddr4-evk.dts" + +/* +TODO: need uncomment when linux ready +&cpu_pd_wait { + /delete-property/ compatible; +}; +*/ + +&{/} { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x40000000 0 0x93c00000>; + linux,cma-default; + }; + + ivshmem_reserved: ivshmem@0xbbb00000 { + no-map; + reg = <0 0xbbb00000 0x0 0x00100000>; + }; + + ivshmem2_reserved: ivshmem2@0xbba00000 { + no-map; + reg = <0 0xbba00000 0x0 0x00100000>; + }; + + pci_reserved: pci@0xbb800000 { + no-map; + reg = <0 0xbb800000 0x0 0x00200000>; + }; + + loader_reserved: loader@0xbb700000 { + no-map; + reg = <0 0xbb700000 0x0 0x00100000>; + }; + + jh_reserved: jh@0xb7c00000 { + no-map; + reg = <0 0xb7c00000 0x0 0x00400000>; + }; + + /* 512MB */ + inmate_reserved: inmate@0x93c00000 { + no-map; + reg = <0 0x93c00000 0x0 0x24000000>; + }; + }; +}; + +&iomuxc { + /* + * Used for the 2nd Linux. + * TODO: M4 may use these pins. + */ + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; +}; + +&clk { + init-on-array = ; +}; + +&uart2 { + pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MN_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MN_CLK_24M>; +}; + +&usdhc3 { + status = "disabled"; +}; + +&usdhc2 { + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rpmsg.dts new file mode 100644 index 00000000000000..784931192dc0e2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rpmsg.dts @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mn-ddr4-evk.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m_core_reserved: m_core@0x80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + rpmsg_reserved: rpmsg@0xb8200000 { + no-map; + reg = <0 0xb8200000 0 0x200000>; + }; + + vdev0vring0: vdev0vring0@b8000000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@b8008000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8008000 0 0x8000>; + no-map; + }; + vdevbuffer: vdevbuffer@b8400000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8400000 0 0x100000>; + no-map; + }; + }; + + sound-wm8524 { + status = "disabled"; + }; + + wm8524: audio-codec { + status = "disabled"; + }; + + rpmsg_i2s: rpmsg-i2s { + compatible = "fsl,imx8mn-rpmsg-i2s"; + /* the audio device index in m4 domain */ + fsl,audioindex = <0> ; + fsl,dma-buffer-size = <0x6000000>; + fsl,enable-lpa; + status = "okay"; + }; + + sound-rpmsg { + compatible = "fsl,imx-audio-rpmsg"; + model = "wm8524-audio"; + cpu-dai = <&rpmsg_i2s>; + rpmsg-out; + }; + + imx8mn-cm7 { + compatible = "fsl,imx8mn-cm7"; + rsc-da = <0xb8000000>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>; + status = "okay"; + }; +}; + +&clk { + init-on-array = < + IMX8MN_CLK_UART4_ROOT + >; +}; + +/* + * ATTENTION: M core may use IPs like below + * ECSPI2, GPIO1/GPIO5, GPT1, I2C3, I2S3, UART4, PWM3, SDMA1/3 and PDM + */ + +&ecspi2 { + status = "disabled"; +}; + +&flexspi { + status = "disabled"; +}; + +&i2c3 { + status = "disabled"; +}; + +&pwm3 { + status = "disabled"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + * --0xb8000000~0xb800ffff: pingpong + */ + vdev-nums = <1>; + reg = <0x0 0xb8000000 0x0 0x10000>; + memory-region = <&vdevbuffer>; + status = "disabled"; +}; + +&sai3 { + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; + +&sdma1{ + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-usd-wifi.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-usd-wifi.dts new file mode 100644 index 00000000000000..846f384dca0685 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-usd-wifi.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-ddr4-evk.dts" + +&usdhc2 { + /delete-property/ cd-gpios; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts index 9ad1d43b8ce756..3c5df779c1d848 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include "imx8mn.dtsi" / { @@ -15,6 +16,33 @@ stdout-path = &uart2; }; + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status { + label = "status"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_gpio>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -23,10 +51,74 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <12000>; + enable-active-high; + }; + + reg_audio_board: regulator-audio-board { + compatible = "regulator-fixed"; + regulator-name = "EXT_PWREN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; enable-active-high; + startup-delay-us = <300000>; + gpio = <&pca6416 1 GPIO_ACTIVE_HIGH>; + }; + + wm8524: audio-codec { + #sound-dai-cells = <0>; + compatible = "wlf,wm8524"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_wlf>; + wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; + clock-names = "mclk"; + }; + + sound-wm8524 { + compatible = "fsl,imx-audio-wm8524"; + model = "wm8524-audio"; + audio-cpu = <&sai3>; + audio-codec = <&wm8524>; + audio-routing = + "Line Out Jack", "LINEVOUTL", + "Line Out Jack", "LINEVOUTR"; + asrc-controller = <&easrc>; + }; + + sound-micfil { + compatible = "fsl,imx-audio-micfil"; + model = "imx-audio-micfil"; + cpu-dai = <&micfil>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; + }; + + sound-ak5558 { + compatible = "fsl,imx-audio-ak5558"; + model = "ak5558-audio"; + audio-cpu = <&sai5>; + audio-codec = <&ak5558>; + status = "disabled"; }; }; +&clk { + assigned-clocks = <&clk IMX8MN_AUDIO_PLL1>, <&clk IMX8MN_AUDIO_PLL2>; + assigned-clock-rates = <393216000>, <361267200>; +}; + +&easrc { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + &A53_0 { cpu-supply = <&buck2_reg>; }; @@ -54,6 +146,23 @@ >; }; + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 + >; + }; + + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 @@ -67,12 +176,114 @@ >; }; + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + >; + }; + + pinctrl_gpio_wlf: gpiowlfgrp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + + pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 + MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0xd6 + MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0xd6 + MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0xd6 + MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0xd6 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MN_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6 + MX8MN_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6 + MX8MN_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6 + >; + }; + + pinctrl_spdif1: spdif1grp { + fsl,pins = < + MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + + pinctrl_typec1: typec1grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { fsl,pins = < MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 >; }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 @@ -80,6 +291,54 @@ >; }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 + MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 + MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 + MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grpgpio { + fsl,pins = < + MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + pinctrl_usdhc2_gpio: usdhc2grpgpio { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 @@ -175,6 +434,152 @@ MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 >; }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 + MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 + >; + }; + + pinctrl_csi_pwn: csi_pwn_grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + >; + }; + + pinctrl_csi_rst: csi_rst_grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 + >; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; + + adv_bridge: adv7535@3d { + compatible = "adi,adv7533"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_from_dsim: endpoint { + remote-endpoint = <&dsim_to_adv7535>; + }; + }; + }; + + ptn5110_1: tcpc@50 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec1>; + reg = <0x50>; + interrupt-parent = <&gpio2>; + interrupts = <11 8>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + ak4458_1: ak4458@10 { + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + }; + + ak4458_2: ak4458@12 { + compatible = "asahi-kasei,ak4458"; + reg = <0x12>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + }; + + ak5558: ak5558@13 { + compatible = "asahi-kasei,ak5558"; + reg = <0x13>; + ak5558,pdn-gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + }; + + ak4497: ak4497@11 { + compatible = "asahi-kasei,ak4497"; + reg = <0x11>; + ak4497,pdn-gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + }; + + ov5640_mipi_0: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>; + clocks = <&clk IMX8MN_CLK_CLKO1>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MN_CLK_CLKO1>; + assigned-clock-parents = <&clk IMX8MN_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; + data-lanes = <1 2>; + clocks-lanes = <0>; + }; + }; + }; }; &fec1 { @@ -199,6 +604,20 @@ }; }; +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -230,13 +649,8 @@ regulator-boot-on; regulator-always-on; regulator-ramp-delay = <1250>; - }; - - buck3_reg: BUCK3 { - // BUCK5 in datasheet - regulator-name = "BUCK3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; }; buck4_reg: BUCK4 { @@ -269,7 +683,7 @@ ldo1_reg: LDO1 { regulator-name = "LDO1"; regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; + regulator-max-microvolt = <1900000>; regulator-boot-on; regulator-always-on; }; @@ -290,14 +704,6 @@ regulator-always-on; }; - ldo4_reg: LDO4 { - regulator-name = "LDO4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - ldo6_reg: LDO6 { regulator-name = "LDO6"; regulator-min-microvolt = <900000>; @@ -309,16 +715,92 @@ }; }; +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + attach-bridge; + }; + }; +}; + &snvs_pwrkey { status = "okay"; }; +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MN_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + &uart2 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; status = "okay"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MN_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + picophy,pre-emp-curr-control = <3>; + picophy,dc-vol-level-adjust = <7>; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>; + bus-width = <4>; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; + /delete-property/ vmmc-supply; + mmc-pwrseq = <&usdhc1_pwrseq>; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; @@ -346,3 +828,98 @@ fsl,ext-reset-output; status = "okay"; }; + +&gpu { + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>, + <&clk IMX8MN_CLK_GPU_SHADER_SRC>, + <&clk IMX8MN_CLK_GPU_AXI>, + <&clk IMX8MN_CLK_GPU_AHB>, + <&clk IMX8MN_GPU_PLL>, + <&clk IMX8MN_CLK_GPU_CORE_DIV>, + <&clk IMX8MN_CLK_GPU_SHADER_DIV>; + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>, + <400000000>, <400000000>; + status= "okay"; +}; + +&micfil { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MN_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MN_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MN_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MN_CLK_SAI5_IPG>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI5_ROOT>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>, + <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-asynchronous; + status = "disabled"; +}; + +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_24M>, + <&clk IMX8MN_CLK_SPDIF1>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_AUDIO_PLL1_OUT>, <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", + "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; + status = "okay"; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port@0 { + reg = <0>; + mipi1_sensor_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + }; + }; +}; + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&cameradev { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk-ak5558.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk-ak5558.dts new file mode 100644 index 00000000000000..d7fcf032c9a270 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk-ak5558.dts @@ -0,0 +1,40 @@ +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mn-evk.dts" + +/ { + sound-wm8524 { + asrc-controller = <0>; + }; + sound-ak5558 { + asrc-controller = <&easrc>; + status = "okay"; + }; + sound-micfil { + status = "disabled"; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + status = "okay"; +}; + +&ak5558 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk-inmate.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk-inmate.dts new file mode 100644 index 00000000000000..584c1fa19f56f6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk-inmate.dts @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include + +/ { + model = "Freescale i.MX8MN EVK"; + compatible = "fsl,imx8mn-evk", "fsl,imx8mm"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial3 = &uart4; + mmc2 = &usdhc3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clock-latency = <61036>; + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clock-latency = <61036>; + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + clk_dummy: clock@7 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + /* The clocks are configured by 1st OS */ + clk_200m: clock@8 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "200m"; + }; + clk_266m: clock@9 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <266000000>; + clock-output-names = "266m"; + }; + clk_80m: clock@10 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <80000000>; + clock-output-names = "80m"; + }; + + pci@bb800000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, + <0 0 0 3 &gic GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, + <0 0 0 4 &gic GIC_SPI 77 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xbb800000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x3e000000>; + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; + + aips3: bus@30800000 { + compatible = "fsl,imx8mq-aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x30800000 0x30800000 0x400000>, + <0x08000000 0x08000000 0x10000000>; + + uart4: serial@30a60000 { + compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = ; + status = "disabled"; + }; + + usdhc3: mmc@30b60000 { + compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = ; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + }; + }; +}; + +&uart4 { + clocks = <&osc_24m>, + <&osc_24m>; + clock-names = "ipg", "per"; + /delete-property/ dmas; + /delete-property/ dmas-names; + status = "okay"; +}; + +&usdhc3 { + clocks = <&clk_dummy>, + <&clk_266m>, + <&clk_200m>; + /delete-property/assigned-clocks; + /delete-property/assigned-clock-rates; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67191.dts new file mode 100644 index 00000000000000..5e8d16c93c4881 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67191.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mn-evk.dts" + +&adv_bridge { + status = "disabled"; +}; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + panel-width-mm = <68>; + panel-height-mm = <121>; + status = "okay"; + }; +}; + +&i2c2 { + synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk-root.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk-root.dts new file mode 100644 index 00000000000000..d0f8eaf92f3421 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk-root.dts @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-evk.dts" + +&{/} { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x40000000 0 0x93c00000>; + linux,cma-default; + }; + + ivshmem_reserved: ivshmem@0xbbb00000 { + no-map; + reg = <0 0xbbb00000 0x0 0x00100000>; + }; + + ivshmem2_reserved: ivshmem2@0xbba00000 { + no-map; + reg = <0 0xbba00000 0x0 0x00100000>; + }; + + pci_reserved: pci@0xbb800000 { + no-map; + reg = <0 0xbb800000 0x0 0x00200000>; + }; + + loader_reserved: loader@0xbb700000 { + no-map; + reg = <0 0xbb700000 0x0 0x00100000>; + }; + + jh_reserved: jh@0xb7c00000 { + no-map; + reg = <0 0xb7c00000 0x0 0x00400000>; + }; + + /* 512MB */ + inmate_reserved: inmate@0x93c00000 { + no-map; + reg = <0 0x93c00000 0x0 0x24000000>; + }; + }; +}; + +&iomuxc { + /* + * Used for the 2nd Linux. + * TODO: M4 may use these pins. + */ + imx8mn-evk { + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; + }; +}; + +&clk { + init-on-array = ; +}; + +&uart2 { + pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MN_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MN_CLK_24M>; +}; + +&usdhc3 { + status = "disabled"; +}; + +&usdhc2 { + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk-rpmsg.dts new file mode 100644 index 00000000000000..dbd8d024131ad4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk-rpmsg.dts @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-evk.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m_core_reserved: m_core@0x80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + vdev0vring0: vdev0vring0@b8000000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@b8008000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8008000 0 0x8000>; + no-map; + }; + vdevbuffer: vdevbuffer@b8400000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8400000 0 0x100000>; + no-map; + }; + }; + + sound-wm8524 { + status = "disabled"; + }; + + wm8524: wm8524{ + status = "disabled"; + }; + + rpmsg_i2s: rpmsg-i2s { + compatible = "fsl,imx8mn-rpmsg-i2s"; + /* the audio device index in m4 domain */ + fsl,audioindex = <0> ; + fsl,dma-buffer-size = <0x6000000>; + fsl,enable-lpa; + status = "okay"; + }; + + sound-rpmsg { + compatible = "fsl,imx-audio-rpmsg"; + model = "wm8524-audio"; + cpu-dai = <&rpmsg_i2s>; + rpmsg-out; + }; + + imx8mn-cm7 { + compatible = "fsl,imx8mn-cm7"; + rsc-da = <0xb8000000>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>; + status = "okay"; + }; +}; + +&clk { + init-on-array = < + IMX8MN_CLK_UART4_ROOT + >; +}; + +/* + * ATTENTION: M core may use IPs like below + * ECSPI2, GPIO1/GPIO5, GPT1, I2C3, I2S3, UART4, PWM3, SDMA1/3 and PDM + */ + +&ecspi2 { + status = "disabled"; +}; + +&flexspi { + status = "disabled"; +}; + +&i2c3 { + status = "disabled"; +}; + +&pwm3 { + status = "disabled"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + * --0xb8000000~0xb800ffff: pingpong + */ + vdev-nums = <1>; + reg = <0x0 0xb8000000 0x0 0x10000>; + memory-region = <&vdevbuffer>; + status = "disabled"; +}; + +&sai3 { + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; + +&sdma1{ + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts new file mode 100644 index 00000000000000..c1fa4702a48f8a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts @@ -0,0 +1,996 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include +#include "imx8mn.dtsi" + +/ { + model = "NXP i.MX8MNano EVK board"; + compatible = "fsl,imx8mn-evk", "fsl,imx8mn"; + + chosen { + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status { + label = "status"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_gpio>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + reg_audio_board: regulator-audio-board { + compatible = "regulator-fixed"; + regulator-name = "EXT_PWREN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + startup-delay-us = <300000>; + gpio = <&pca6416 1 GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; + }; + + wm8524: wm8524 { + compatible = "wlf,wm8524"; + clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; + clock-names = "mclk"; + wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; + }; + + sound-wm8524 { + compatible = "fsl,imx-audio-wm8524"; + model = "wm8524-audio"; + audio-cpu = <&sai3>; + audio-codec = <&wm8524>; + audio-routing = + "Line Out Jack", "LINEVOUTL", + "Line Out Jack", "LINEVOUTR"; + asrc-controller = <&easrc>; + }; + + sound-micfil { + compatible = "fsl,imx-audio-micfil"; + model = "imx-audio-micfil"; + cpu-dai = <&micfil>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; + }; + + sound-ak5558 { + compatible = "fsl,imx-audio-ak5558"; + model = "ak5558-audio"; + audio-cpu = <&sai5>; + audio-codec = <&ak5558>; + status = "disabled"; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&clk { + assigned-clocks = <&clk IMX8MN_AUDIO_PLL1>, <&clk IMX8MN_AUDIO_PLL2>; + assigned-clock-rates = <393216000>, <361267200>; +}; + +&easrc { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx8mn-evk { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 + + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 + MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 + MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 + >; + }; + + pinctrl_ecspi2_cs: ecspi2cs { + fsl,pins = < + MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 + MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 + MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0xd6 + MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0xd6 + MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0xd6 + MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0xd6 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MN_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6 + MX8MN_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6 + MX8MN_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6 + >; + }; + + pinctrl_spdif1: spdif1grp { + fsl,pins = < + MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 + MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 + MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 + MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 + >; + }; + + pinctrl_typec1: typec1grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grpgpio { + fsl,pins = < + MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 + MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 + >; + }; + + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 + >; + }; + + pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_csi_pwn: csi_pwn_grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + >; + }; + + pinctrl_csi_rst: csi_rst_grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 + >; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <500000>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + pca9450,pmic-buck2-uses-i2c-dvs; + /* Run/Standby voltage */ + pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; + + adv_bridge: adv7535@3d { + compatible = "adi,adv7533"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_from_dsim: endpoint { + remote-endpoint = <&dsim_to_adv7535>; + }; + }; + }; + + ptn5110_1: tcpc@50 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec1>; + reg = <0x50>; + interrupt-parent = <&gpio2>; + interrupts = <11 8>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + ak4458_1: ak4458@10 { + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + status = "disabled"; + }; + + ak4458_2: ak4458@12 { + compatible = "asahi-kasei,ak4458"; + reg = <0x12>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + status = "disabled"; + }; + + ak5558: ak5558@13 { + compatible = "asahi-kasei,ak5558"; + reg = <0x13>; + ak5558,pdn-gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + status = "disabled"; + }; + + ak4497: ak4497@11 { + compatible = "asahi-kasei,ak4497"; + reg = <0x11>; + ak4497,pdn-gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + status = "disabled"; + }; + + ov5640: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>; + clocks = <&clk IMX8MN_CLK_CLKO1>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MN_CLK_CLKO1>; + assigned-clock-parents = <&clk IMX8MN_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; + data-lanes = <1 2>; + clocks-lanes = <0>; + }; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,led-act-blind-workaround; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + attach-bridge; + }; + }; +}; + +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MN_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + +&micfil { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MN_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MN_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MN_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MN_CLK_SAI5_IPG>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI5_ROOT>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>, + <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-asynchronous; + status = "disabled"; +}; + +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_24M>, + <&clk IMX8MN_CLK_SPDIF1>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_AUDIO_PLL1_OUT>, <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", + "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MN_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>; + bus-width = <4>; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; + /delete-property/ vmmc-supply; + mmc-pwrseq = <&usdhc1_pwrseq>; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&usbotg1 { + picophy,pre-emp-curr-control = <3>; + picophy,dc-vol-level-adjust = <7>; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port@0 { + reg = <0>; + mipi1_sensor_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + }; + }; +}; + +&isi_0 { + status = "okay"; + cap_device { + status = "okay"; + }; +}; + +&cameradev { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index ac3a3b333efa62..f41df0e8d97f0c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -6,7 +6,9 @@ #include #include #include +#include #include +#include #include "imx8mn-pinfunc.h" @@ -37,12 +39,28 @@ spi0 = &ecspi1; spi1 = &ecspi2; spi2 = &ecspi3; + isi0 = &isi_0; + csi0 = &mipi_csi_1; }; cpus { #address-cells = <1>; #size-cells = <0>; + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + A53_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; @@ -54,6 +72,8 @@ operating-points-v2 = <&a53_opp_table>; nvmem-cells = <&cpu_speed_grade>; nvmem-cell-names = "speed_grade"; + cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; A53_1: cpu@1 { @@ -65,6 +85,8 @@ enable-method = "psci"; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; A53_2: cpu@2 { @@ -76,6 +98,8 @@ enable-method = "psci"; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; A53_3: cpu@3 { @@ -87,6 +111,8 @@ enable-method = "psci"; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; A53_L2: l2-cache0 { @@ -128,6 +154,21 @@ reg = <0x0 0x40000000 0 0x80000000>; }; + resmem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x40000000 0 0x60000000>; + linux,cma-default; + }; + }; + osc_32k: clock-osc-32k { compatible = "fixed-clock"; #clock-cells = <0>; @@ -170,11 +211,84 @@ clock-output-names = "clk_ext4"; }; + busfreq { /* BUSFREQ */ + compatible = "fsl,imx_busfreq"; + clocks = <&clk IMX8MN_DRAM_PLL_OUT>, <&clk IMX8MN_CLK_DRAM_ALT>, + <&clk IMX8MN_CLK_DRAM_APB>, <&clk IMX8MN_CLK_DRAM_APB>, + <&clk IMX8MN_CLK_DRAM_CORE>, <&clk IMX8MN_CLK_DRAM_ALT_ROOT>, + <&clk IMX8MN_SYS_PLL1_40M>, <&clk IMX8MN_SYS_PLL1_100M>, + <&clk IMX8MN_SYS_PLL2_333M>, <&clk IMX8MN_CLK_NOC>, + <&clk IMX8MN_CLK_AHB>, <&clk IMX8MN_CLK_MAIN_AXI>, + <&clk IMX8MN_CLK_24M>, <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_DRAM_PLL>; + clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", + "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m", + "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m", + "sys_pll1_800m", "dram_pll_div"; + }; + + power-domains { + compatible = "simple-bus"; + + /* HSIOMIX */ + hsiomix_pd: hsiomix-pd { + compatible = "fsl,imx8m-pm-domain"; + domain-index = <0>; + #power-domain-cells = <0>; + domain-name = "hsiomix"; + clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; + }; + + usb_otg1_pd: usbotg1-pd{ + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <2>; + domain-name = "usb_otg1"; + parent-domains = <&hsiomix_pd>; + }; + + /* GPU2D&3D */ + gpumix_pd: gpumix-pd { + compatible = "fsl,imx8m-pm-domain"; + domain-index = <4>; + #power-domain-cells = <0>; + domain-name = "gpumix"; + clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, + <&clk IMX8MN_CLK_GPU_SHADER_DIV>, + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, + <&clk IMX8MN_CLK_GPU_AHB>; + }; + + dispmix_pd: dispmix-pd { + compatible = "fsl,imx8m-pm-domain"; + domain-index = <9>; + #power-domain-cells = <0>; + domain-name = "dispmix"; + clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + }; + + mipi_pd: mipi-pd { + compatible = "fsl,imx8m-pm-domain"; + domain-index = <10>; + #power-domain-cells = <0>; + domain-name = "mipi"; + parent-domains = <&dispmix_pd>; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; }; + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , @@ -185,12 +299,49 @@ arm,no-tick-in-suspend; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu>; + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + caam_sm: caam-sm@00100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30000000 0x400000>; @@ -198,6 +349,152 @@ #size-cells = <1>; ranges; + spba-bus@30000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30000000 0x100000>; + ranges; + + easrc: easrc@300C0000 { + compatible = "fsl,imx8mn-easrc"; + reg = <0x300C0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_ASRC_ROOT>; + clock-names = "mem"; + dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, + <&sdma2 18 23 0> , <&sdma2 19 23 0>, + <&sdma2 20 23 0> , <&sdma2 21 23 0>, + <&sdma2 22 23 0> , <&sdma2 23 23 0>; + dma-names = "ctx0_rx", "ctx0_tx", + "ctx1_rx", "ctx1_tx", + "ctx2_rx", "ctx2_tx", + "ctx3_rx", "ctx3_tx"; + fsl,easrc-ram-script-name = "imx/easrc/easrc-imx8mn.bin"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + status = "disabled"; + }; + + sai2: sai@30020000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x30020000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_SAI2_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI2_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai3: sai@30030000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x30030000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_SAI3_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI3_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai5: sai@30050000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x30050000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_SAI5_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI5_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0 0xf 0xf>; + status = "disabled"; + }; + + sai6: sai@30060000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x30060000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_SAI6_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI6_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai7: sai@300b0000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x300b0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_SAI7_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI7_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + micfil: micfil@30080000 { + compatible = "fsl,imx8mm-micfil"; + reg = <0x30080000 0x10000>; + interrupts = , + , + , + ; + clocks = <&clk IMX8MN_CLK_PDM_IPG>, + <&clk IMX8MN_CLK_PDM_ROOT>, + <&clk IMX8MN_AUDIO_PLL1_OUT>, + <&clk IMX8MN_AUDIO_PLL2_OUT>, + <&clk IMX8MN_CLK_EXT3>; + clock-names = "ipg_clk", "ipg_clk_app", + "pll8k", "pll11k", "clkext3"; + dmas = <&sdma2 24 25 0x80000000>; + dma-names = "rx"; + status = "disabled"; + }; + + spdif1: spdif@30090000 { + compatible = "fsl,imx8mm-spdif"; + reg = <0x30090000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */ + <&clk IMX8MN_CLK_24M>, /* rxtx0 */ + <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8MN_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + }; + gpio1: gpio@30200000 { compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; reg = <0x30200000 0x10000>; @@ -263,6 +560,13 @@ gpio-ranges = <&iomuxc 0 119 30>; }; + tmu: tmu@30260000 { + compatible = "fsl,imx8mm-tmu"; + reg = <0x30260000 0x10000>; + clocks = <&clk IMX8MN_CLK_TMU_ROOT>; + #thermal-sensor-cells = <0>; + }; + wdog1: watchdog@30280000 { compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; reg = <0x30280000 0x10000>; @@ -288,7 +592,7 @@ }; sdma3: dma-controller@302b0000 { - compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; + compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; reg = <0x302b0000 0x10000>; interrupts = ; clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, @@ -299,7 +603,7 @@ }; sdma2: dma-controller@302c0000 { - compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; + compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; reg = <0x302c0000 0x10000>; interrupts = ; clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, @@ -319,8 +623,8 @@ reg = <0x30340000 0x10000>; }; - ocotp: ocotp-ctrl@30350000 { - compatible = "fsl,imx8mn-ocotp", "fsl,imx7d-ocotp", "syscon"; + ocotp: efuse@30350000 { + compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon"; reg = <0x30350000 0x10000>; clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>; #address-cells = <1>; @@ -337,6 +641,20 @@ reg = <0x30360000 0x10000>; }; + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + }; + snvs: snvs@30370000 { compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; reg = <0x30370000 0x10000>; @@ -347,6 +665,7 @@ offset = <0x34>; interrupts = , ; + clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; clock-names = "snvs-rtc"; }; @@ -354,6 +673,8 @@ compatible = "fsl,sec-v4.0-pwrkey"; regmap = <&snvs>; interrupts = ; + clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; + clock-names = "snvs"; linux,keycode = ; wakeup-source; status = "disabled"; @@ -428,6 +749,14 @@ #pwm-cells = <2>; status = "disabled"; }; + + system_counter: timer@306a0000 { + compatible = "nxp,sysctr-timer"; + reg = <0x306a0000 0x20000>; + interrupts = ; + clocks = <&osc_24m>; + clock-names = "per"; + }; }; aips3: bus@30800000 { @@ -513,6 +842,36 @@ status = "disabled"; }; + crypto: crypto@30900000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0x30900000 0x40000>; + ranges = <0 0x30900000 0x40000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_AHB>, + <&clk IMX8MN_CLK_IPG_ROOT>; + clock-names = "aclk", "ipg"; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + + sec_jr2: jr@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = ; + }; + }; + i2c1: i2c@30a20000 { compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; #address-cells = <1>; @@ -565,8 +924,17 @@ status = "disabled"; }; + mu: mu@30aa0000 { + compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_MU_ROOT>; + clock-names = "mu"; + #mbox-cells = <2>; + }; + usdhc1: mmc@30b40000 { - compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc"; reg = <0x30b40000 0x10000>; interrupts = ; clocks = <&clk IMX8MN_CLK_IPG_ROOT>, @@ -582,7 +950,7 @@ }; usdhc2: mmc@30b50000 { - compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc"; reg = <0x30b50000 0x10000>; interrupts = ; clocks = <&clk IMX8MN_CLK_IPG_ROOT>, @@ -596,7 +964,7 @@ }; usdhc3: mmc@30b60000 { - compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc"; reg = <0x30b60000 0x10000>; interrupts = ; clocks = <&clk IMX8MN_CLK_IPG_ROOT>, @@ -611,8 +979,24 @@ status = "disabled"; }; + flexspi: spi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mm-fspi"; + reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = ; + clocks = <&clk IMX8MN_CLK_QSPI_ROOT>, + <&clk IMX8MN_CLK_QSPI_ROOT>; + clock-names = "fspi", "fspi_en"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MN_CLK_QSPI>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>; + status = "disabled"; + }; + sdma1: dma-controller@30bd0000 { - compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; + compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; reg = <0x30bd0000 0x10000>; interrupts = ; clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, @@ -623,7 +1007,7 @@ }; fec1: ethernet@30be0000 { - compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec"; + compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; reg = <0x30be0000 0x10000>; interrupts = , , @@ -645,6 +1029,8 @@ assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; + stop-mode = <&gpr 0x10 3>; + fsl,wakeup_irq = <2>; status = "disabled"; }; @@ -657,18 +1043,80 @@ #size-cells = <1>; ranges; + lcdif: lcd-controller@32e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mn-lcdif"; + reg = <0x32e00000 0x10000>; + clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "pix", "disp-axi", "disp-apb"; + assigned-clocks = <&clk IMX8MN_CLK_DISP_PIXEL>, + <&clk IMX8MN_CLK_DISP_AXI>, + <&clk IMX8MN_CLK_DISP_APB>; + assigned-clock-parents = <&clk IMX8MN_VIDEO_PLL1_OUT>, + <&clk IMX8MN_SYS_PLL2_1000M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rate = <594000000>, + <500000000>, + <200000000>; + interrupts = ; + resets = <&lcdif_resets>; + power-domains = <&dispmix_pd>; + status = "disabled"; + + lcdif_disp0: port@0 { + reg = <0>; + + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + mipi_dsi: dsi_controller@32e10000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mn-mipi-dsim"; + reg = <0x32e10000 0x400>; + clocks = <&clk IMX8MN_CLK_DSI_CORE>, + <&clk IMX8MN_CLK_DSI_PHY_REF>; + clock-names = "cfg", "pll-ref"; + assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>, + <&clk IMX8MN_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, + <&clk IMX8MN_VIDEO_PLL1_OUT>; + assigned-clock-rates = <266000000>, + <594000000>; + interrupts = ; + resets = <&mipi_dsi_resets>; + power-domains = <&mipi_pd>; + status = "disabled"; + + port@0 { + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&lcdif_disp0>; + }; + usbotg1: usb@32e40000 { compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; reg = <0x32e40000 0x200>; interrupts = ; clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; clock-names = "usb1_ctrl_root_clk"; - assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>, - <&clk IMX8MN_CLK_USB_CORE_REF>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>, - <&clk IMX8MN_SYS_PLL1_100M>; + assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; fsl,usbphy = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; + power-domains = <&usb_otg1_pd>; status = "disabled"; }; @@ -677,28 +1125,6 @@ #index-cells = <1>; reg = <0x32e40200 0x200>; }; - - usbotg2: usb@32e50000 { - compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; - reg = <0x32e50000 0x200>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; - clock-names = "usb1_ctrl_root_clk"; - assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>, - <&clk IMX8MN_CLK_USB_CORE_REF>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>, - <&clk IMX8MN_SYS_PLL1_100M>; - fsl,usbphy = <&usbphynop2>; - fsl,usbmisc = <&usbmisc2 0>; - status = "disabled"; - }; - - usbmisc2: usbmisc@32e50200 { - compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc"; - #index-cells = <1>; - reg = <0x32e50200 0x200>; - }; - }; dma_apbh: dma-controller@33000000 { @@ -740,6 +1166,48 @@ }; }; + gpu: gpu@38000000 { + compatible = "fsl,imx8mn-gpu", "fsl,imx6q-gpu"; + reg = <0x0 0x38000000 0x0 0x40000>, <0x0 0x40000000 0x0 0x80000000>, <0x0 0x0 0x0 0x8000000>; + reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem"; + interrupts = ; + interrupt-names = "irq_3d"; + clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, + <&clk IMX8MN_CLK_GPU_SHADER_DIV>, + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, + <&clk IMX8MN_CLK_GPU_AHB>; + clock-names = "gpu3d_clk", "gpu3d_shader_clk", "gpu3d_axi_clk", "gpu3d_ahb_clk"; + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>, + <&clk IMX8MN_CLK_GPU_SHADER_SRC>, + <&clk IMX8MN_CLK_GPU_AXI>, + <&clk IMX8MN_CLK_GPU_AHB>, + <&clk IMX8MN_GPU_PLL>, + <&clk IMX8MN_CLK_GPU_CORE_DIV>, + <&clk IMX8MN_CLK_GPU_SHADER_DIV>; + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>, + <600000000>, <600000000>; + power-domains = <&gpumix_pd>; + status = "disabled"; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx8mq-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + status = "disabled"; + }; + usbphynop1: usbphynop1 { compatible = "usb-nop-xceiv"; clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; @@ -748,11 +1216,177 @@ clock-names = "main_clk"; }; - usbphynop2: usbphynop2 { - compatible = "usb-nop-xceiv"; - clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; - assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; - clock-names = "main_clk"; + dispmix-reset { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dispmix_sft_rstn: dispmix-sft-rstn@32e28000 { + compatible = "fsl,imx8mn-dispmix-sft-rstn"; + reg = <0x0 0x32e28000 0x0 0x4>; + clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "disp_apb_root_clk"; + active_low; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + + dispmix_clk_en: dispmix-clk-en@32e28004 { + compatible = "fsl,imx8mn-dispmix-clk-en"; + reg = <0x0 0x32e28004 0x0 0x4>; + clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "disp_apb_root_clk"; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + + dispmix_mipi_rst: dispmix-mipi-rst@32e28008 { + compatible = "fsl,imx8mn-dispmix-mipi-rst"; + reg = <0x0 0x32e28008 0x0 0x4>; + clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "disp_apb_root_clk"; + active_low; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + }; + + lcdif_resets: lcdif-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + lcdif-soft-resetn { + compatible = "lcdif,soft-resetn"; + resets = <&dispmix_sft_rstn IMX8MN_LCDIF_APB_CLK_RESET>, + <&dispmix_sft_rstn IMX8MN_LCDIF_PIXEL_CLK_RESET>; + }; + + lcdif-clk-enable { + compatible = "lcdif,clk-enable"; + resets = <&dispmix_clk_en IMX8MN_LCDIF_APB_CLK_EN>, + <&dispmix_clk_en IMX8MN_LCDIF_PIXEL_CLK_EN>; + }; + }; + + mipi_dsi_resets: mipi-dsi-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + dsi-soft-resetn { + compatible = "dsi,soft-resetn"; + resets = <&dispmix_sft_rstn IMX8MN_MIPI_DSI_CLKREF_RESET>, + <&dispmix_sft_rstn IMX8MN_MIPI_DSI_PCLK_RESET>; + }; + + dsi-clk-enable { + compatible = "dsi,clk-enable"; + resets = <&dispmix_clk_en IMX8MN_MIPI_DSI_CLKREF_EN>, + <&dispmix_clk_en IMX8MN_MIPI_DSI_PCLK_EN>; + }; + + dsi-mipi-reset { + compatible = "dsi,mipi-reset"; + resets = <&dispmix_mipi_rst IMX8MN_MIPI_M_RESET>; + }; + }; + + isi_resets: isi-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + isi-soft-resetn { + compatible = "isi,soft-resetn"; + resets = <&dispmix_sft_rstn IMX8MN_ISI_PROC_CLK_RESET>, + <&dispmix_sft_rstn IMX8MN_ISI_APB_CLK_RESET>; + }; + + isi-clk-enable { + compatible = "isi,clk-enable"; + resets = <&dispmix_clk_en IMX8MN_ISI_PROC_CLK_EN>, + <&dispmix_clk_en IMX8MN_ISI_APB_CLK_EN>; + }; + + }; + + mipi_csi_resets: mipi-csi-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + csi-soft-resetn { + compatible = "csi,soft-resetn"; + resets = <&dispmix_sft_rstn IMX8MN_MIPI_CSI_PCLK_RESET>, + <&dispmix_sft_rstn IMX8MN_MIPI_CSI_ACLK_RESET>; + }; + + csi-clk-enable { + compatible = "csi,clk-enable"; + resets = <&dispmix_clk_en IMX8MN_MIPI_CSI_PCLK_EN>, + <&dispmix_clk_en IMX8MN_MIPI_CSI_ACLK_EN>; + }; + + csi-mipi-reset { + compatible = "csi,mipi-reset"; + resets = <&dispmix_mipi_rst IMX8MN_MIPI_S_RESET>; + }; + }; + + mipi2csi_gasket: gasket@32e28060 { + compatible = "syscon"; + reg = <0x0 0x32e28060 0x0 0x28>; + }; + + cameradev: camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + isi_0: isi@0x32e20000 { + compatible = "fsl,imx8mn-isi"; + reg = <0x0 0x32e20000 0x0 0x2000>; + power-domains = <&dispmix_pd>; + interrupts = ; + interface = <2 0 2>; + clocks = <&clk IMX8MN_CLK_DISP_AXI>, + <&clk IMX8MN_CLK_DISP_APB>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root"; + assigned-clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + assigned-clock-rates = <500000000>, <200000000>; + resets = <&isi_resets>; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + mipi_csi_1: csi@32e30000 { + compatible = "fsl,imx8mn-mipi-csi"; + reg = <0x0 0x32e30000 0x0 0x10000>; + interrupts = ; + clock-frequency = <333000000>; + clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "mipi_clk", "disp_axi", "disp_apb"; + assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>; + assigned-clock-rates = <333000000>; + bus-width = <4>; + csi-gpr = <&mipi2csi_gasket>; + power-domains = <&mipi_pd>; + resets = <&mipi_csi_resets>; + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts new file mode 100755 index 00000000000000..909ec078af0888 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts @@ -0,0 +1,870 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include +#include "imx8mp.dtsi" + +/ { + model = "NXP i.MX8MP SOM on AB2"; + compatible = "fsl,imx8mp-ab2", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status { + label = "status"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; /* LED GREEN */ + }; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + reg_ab2_ana_pwr: regulator-ab2-ana-pwr { + compatible = "regulator-fixed"; + regulator-name = "ab2_ana_pwr"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_ana_pwr>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { + compatible = "regulator-fixed"; + regulator-name = "ab2_vdd_pwr_5v0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound-micfil { + compatible = "fsl,imx-audio-micfil"; + model = "imx-audio-micfil"; + cpu-dai = <&micfil>; + }; + + sound-xcvr { + compatible = "fsl,imx-audio-xcvr"; + model = "imx-audio-xcvr"; + cpu-dai = <&xcvr>; + }; + + sound-ak4458 { + compatible = "fsl,imx-audio-ak4458"; + model = "ak4458-audio"; + audio-cpu = <&sai1>; + audio-codec = <&ak4458_1>, <&ak4458_2>; + ak4458,pdn-gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; + }; + + sound-ak5552 { + compatible = "fsl,imx-audio-ak5558"; + model = "ak5552-audio"; + audio-cpu = <&sai3>; + audio-codec = <&ak5552>; + }; + + sound-hdmi { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + constraint-rate = <44100>, + <88200>, + <176400>, + <32000>, + <48000>, + <96000>, + <192000>; + status = "okay"; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&lcdif3_disp>; + }; +}; + +&{/busfreq} { + status = "disabled"; +}; + +&clk { + init-on-array = ; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev1: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <500000>; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + pca9450,pmic-buck2-uses-i2c-dvs; + /* Run/Standby voltage */ + pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pca6408_2: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca6416_2: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + ak4458_1: ak4458@10 { + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_ana_pwr>; + }; + + ak4458_2: ak4458@11 { + compatible = "asahi-kasei,ak4458"; + reg = <0x11>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_ana_pwr>; + }; + + ak4458_3: ak4458@12 { + compatible = "asahi-kasei,ak4458"; + reg = <0x12>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_ana_pwr>; + }; + + ak5552: ak5552@13 { + compatible = "asahi-kasei,ak5552"; + reg = <0x13>; + reset-gpios = <&pca6416 2 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_ana_pwr>; + }; +}; + +&easrc { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&micfil { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MP_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clk IMX8MP_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI1_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-multi-lane; + fsl,dataline,dsd = <0 0xff 0xff>; + dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + status = "okay"; +}; + +&xcvr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_xcvr>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&sdma2 { + status = "okay"; +}; + +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MP_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&vpu_g1 { + status = "okay"; +}; + +&vpu_g2 { + status = "okay"; +}; + +&vpu_vc8000e { + status = "okay"; +}; + +&gpu_3d { + status = "okay"; +}; + +&gpu_2d { + status = "okay"; +}; + +&ml_vipsi { + status = "okay"; +}; + +&mix_gpu_ml { + status = "okay"; +}; + +&lcdif3 { + status = "okay"; +}; + +&irqsteer_hdmi { + status = "okay"; +}; + +&hdmimix_clk { + status = "okay"; +}; + +&hdmimix_reset { + status = "okay"; +}; + +&hdmi_pavi { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + +&aud2htx { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_EARC_SCL 0x400001c3 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_EARC_SDA 0x400001c3 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_EARC_DC_HPD 0x40000019 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_EARC_CEC 0x40000019 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 + >; + }; + + pinctrl_ecspi2_cs: ecspi2cs { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x19 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + pinctrl_ab2_ana_pwr: ab2anapwrgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0xd6 + >; + }; + + pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0xd6 + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_CLK 0xd6 + MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_BIT_STREAM00 0xd6 + MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_BIT_STREAM01 0xd6 + MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_BIT_STREAM02 0xd6 + MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_BIT_STREAM03 0xd6 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0xd6 + MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 0xd6 + MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 0xd6 + MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03 0xd6 + MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04 0xd6 + MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI1_TX_DATA05 0xd6 + MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI1_TX_DATA06 0xd6 + MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07 0xd6 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + >; + }; + + pinctrl_xcvr: xcvrgrp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_SPDIF_EXT_CLK 0xd6 + MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF_IN 0xd6 + MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF_OUT 0xd6 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-basler.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-basler.dts new file mode 100644 index 00000000000000..6843601e0c84f6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-basler.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Basler AG + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mp-evk-ov2775.dts" + +&ov2775_0 { + status = "disabled"; +}; + +&i2c2 { + basler_camera@36 { + compatible = "basler,basler-camera-vvcam", "basler-camera-vvcam"; + reg = <0x36>; + csi_id = <0x00>; + status = "okay"; + + port { + endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <248000000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-dsp.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-dsp.dts new file mode 100644 index 00000000000000..93b4f7e6421e5b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-dsp.dts @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ +/dts-v1/; + +#include "imx8mp-evk.dts" + +/ { + sound-wm8960 { + status = "disable"; + }; + + dspaudio: dspaudio { + compatible = "fsl,dsp-audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + status = "okay"; + }; + + sound-dsp { + compatible = "fsl,imx-dsp-audio"; + model = "wm8960-audio"; + cpu-dai = <&dspaudio>; + audio-codec = <&codec>; + audio-platform = <&dsp>; + }; +}; + +&sai3 { + status = "disable"; +}; + +&easrc { + status = "disable"; +}; + +&uart4 { + /* console for debug dsp*/ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&iomuxc { + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 + >; + }; +}; + +&dsp { + compatible = "fsl,imx8mp-dsp-v1"; + memory-region = <&dsp_reserved>; + reg = <0x0 0x3B6E8000 0x0 0x88000>; + pinctrl-0 = <&pinctrl_uart4>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_DSP_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_MU2_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, + <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_ASRC_IPG>, + <&clk IMX8MP_CLK_UART4_ROOT>, + <&clk IMX8MP_CLK_UART4_ROOT>; + clock-names = "ocram", "core", "debug", "mu2", "sdma_root", "sai_ipg", "sai_mclk", "pll8k", "pll11k", + "asrc_ipg", "uart_ipg", "uart_per"; + + power-domains = <&audiomix_pd>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + + audio-interface = "sai"; + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + mboxes = <&mu2 2 0>, + <&mu2 2 1>, + <&mu2 3 0>, + <&mu2 3 1>; + fsl,dsp-firmware = "imx/dsp/hifi4.bin"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dts new file mode 100644 index 00000000000000..0b778945b334a7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mp-evk.dts" + +&flexcan2 { + status = "okay";/* can2 pin conflict with pdm */ +}; + +&micfil { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-inmate.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-inmate.dts new file mode 100644 index 00000000000000..277ef70f290358 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-inmate.dts @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include + +/ { + model = "Freescale i.MX8MP EVK"; + compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial3 = &uart4; + mmc2 = &usdhc3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + clk_dummy: clock@7 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + /* The clocks are configured by 1st OS */ + clk_400m: clock@8 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "200m"; + }; + + clk_266m: clock@9 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <266000000>; + clock-output-names = "266m"; + }; + + osc_24m: clock@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + pci@fd700000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 155 IRQ_TYPE_EDGE_RISING>, + <0 0 0 3 &gic GIC_SPI 156 IRQ_TYPE_EDGE_RISING>, + <0 0 0 4 &gic GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xfd700000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x3e000000>; + + aips3: bus@30800000 { + compatible = "simple-bus"; + reg = <0x30800000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + uart4: serial@30a60000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = ; + status = "disabled"; + }; + + usdhc3: mmc@30b60000 { + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = ; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + }; + }; +}; + +&uart4 { + clocks = <&osc_24m>, + <&osc_24m>; + clock-names = "ipg", "per"; + status = "okay"; +}; + +&usdhc3 { + clocks = <&clk_dummy>, + <&clk_266m>, + <&clk_400m>; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-it6263-lvds-dual-channel.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-it6263-lvds-dual-channel.dts new file mode 100644 index 00000000000000..69fe4aefd9531e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-it6263-lvds-dual-channel.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8mp-evk.dts" + +&lvds_bridge { + split-mode; +}; + +&ldb { + fsl,dual-channel; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-jdi-wuxga-lvds-panel.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-jdi-wuxga-lvds-panel.dts new file mode 100644 index 00000000000000..904229c988dd14 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-jdi-wuxga-lvds-panel.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8mp-evk.dts" + +/ { + lvds0_panel { + compatible = "jdi,tx26d202vm0bwa"; + backlight = <&lvds_backlight>; + + port { + panel_lvds_in: endpoint { + remote-endpoint = <&lvds_out>; + }; + }; + }; +}; + +/delete-node/ &lvds_bridge; + +&ldb { + fsl,dual-channel; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + + /delete-node/ port@1; + + port@1 { + reg = <1>; + + lvds_out: endpoint { + remote-endpoint = <&panel_lvds_in>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts new file mode 100644 index 00000000000000..eef0da685ab248 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "imx8mp-evk.dts" + +&i2c2 { + ov5640_0: ov5640_mipi@3c { + status = "disabled"; + }; + + ov2775_0: ov2775_mipi@36 { + compatible = "ovti,ov2775"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + pwn-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + ov5640_1: ov5640_mipi@3c { + status = "disabled"; + }; + + ov2775_1: ov2775_mipi@36 { + compatible = "ovti,ov2775"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <1>; + pwn-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + status = "disabled"; + }; +}; + +&cameradev { + status = "okay"; +}; + +&isi_0 { + status = "disabled"; +}; + +&isi_1 { + status = "disabled"; +}; + +&isp_0 { + status = "okay"; +}; + +&mipi_csi_0 { + clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "mipi_clk", "axi_root", "apb_root"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <500000000>, <500000000>, <200000000>; +}; + +&mipi_csi_1 { + clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "mipi_clk", "axi_root", "apb_root"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <500000000>, <500000000>, <200000000>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-rm67191.dts new file mode 100644 index 00000000000000..bf23e8a378f908 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-rm67191.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include "imx8mp-evk.dts" + +&adv_bridge { + status = "disabled"; +}; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + panel-width-mm = <68>; + panel-height-mm = <121>; + status = "okay"; + }; +}; + +&i2c2 { + synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-root.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-root.dts new file mode 100644 index 00000000000000..898dc706cf7400 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-root.dts @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mp-evk.dts" + +/ { + interrupt-parent = <&gic>; + + resmem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + }; +}; + +&cpu_pd_wait { + /delete-property/ compatible; +}; + +/delete-node/ &gpc; + +&clk { + init-on-array = ; +}; + +&{/busfreq} { + status = "disabled"; +}; + +&{/reserved-memory} { + jh_reserved: jh@fdc00000 { + no-map; + reg = <0 0xfdc00000 0x0 0x400000>; + }; + + loader_reserved: loader@fdb00000 { + no-map; + reg = <0 0xfdb00000 0x0 0x00100000>; + }; + + ivshmem_reserved: ivshmem@fda00000 { + no-map; + reg = <0 0xfda00000 0x0 0x00100000>; + }; + + ivshmem2_reserved: ivshmem2@fd900000 { + no-map; + reg = <0 0xfd900000 0x0 0x00100000>; + }; + + pci_reserved: pci@fd700000 { + no-map; + reg = <0 0xfd700000 0x0 0x00200000>; + }; + + inmate_reserved: inmate@c0000000 { + no-map; + reg = <0 0xc0000000 0x0 0x3d700000>; + }; +}; + +&iomuxc { + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 + >; + }; +}; + +&usdhc3 { + status = "disabled"; +}; + +&uart4 { + /delete-property/ dmas; + /delete-property/ dma-names; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "disabled"; +}; + +&uart2 { + /* uart4 is used by the 2nd OS, so configure pin and clk */ + pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MP_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; +}; + +&usdhc2 { + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-rpmsg.dts new file mode 100644 index 00000000000000..e84b1a5b2296da --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-rpmsg.dts @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mp-evk.dts" + +/ { + aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c_rpbus_3; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m4_reserved: m4@0x80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + vdev0vring0: vdev0vring0@55000000 { + compatible = "shared-dma-pool"; + reg = <0 0x55000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@55008000 { + compatible = "shared-dma-pool"; + reg = <0 0x55008000 0 0x8000>; + no-map; + }; + vdevbuffer: vdevbuffer@55400000 { + compatible = "shared-dma-pool"; + reg = <0 0x55400000 0 0x100000>; + no-map; + }; + + audio_reserved: audio@0x81000000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x81000000 0 0x10000000>; + }; + }; + + sound-wm8960 { + status = "disabled"; + }; + + rpmsg_i2s: rpmsg-i2s { + compatible = "fsl,imx8mp-rpmsg-i2s"; + /* the audio device index in m4 domain */ + fsl,audioindex = <0> ; + fsl,dma-buffer-size = <0x6000000>; + fsl,enable-lpa; + power-domains = <&audiomix_pd>; + status = "okay"; + }; + + sound-rpmsg { + compatible = "fsl,imx-audio-rpmsg"; + model = "wm8960-audio"; + cpu-dai = <&rpmsg_i2s>; + audio-codec = <&codec>; + memory-region = <&audio_reserved>; + rpmsg-out; + audio-routing = + "LINPUT1", "MICB", + "LINPUT3", "MICB"; + }; + + imx8mp-cm7 { + compatible = "fsl,imx8mn-cm7"; + rsc-da = <0x55000000>; + clocks = <&clk IMX8MP_CLK_M7_DIV>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>; + status = "okay"; + }; +}; + +/* + * ATTENTION: M7 may use IPs like below + * ECSPI0/ECSPI2, FLEXCAN, GPIO1/GPIO5, GPT1, I2C3, I2S3, UART4, + * PWM4, SDMA1/SDMA2 + */ +&ecspi2 { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexspi { + status = "disabled"; +}; + +/delete-node/ &i2c3; + +&i2c_rpbus_3 { + compatible = "fsl,i2c-rpbus"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + ov5640_1: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + powerdown-gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "disabled"; + + port { + ov5640_mipi_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2>; + clock-lanes = <0>; + }; + }; + }; + + codec: wm8960@1a { + compatible = "wlf,wm8960,lpa"; + reg = <0x1a>; + wlf,shared-lrclk; + SPKVDD1-supply = <®_audio_pwr>; + }; +}; + +&pwm4{ + status = "disabled"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + * --0x55000000~0x5500ffff: pingpong + */ + vdev-nums = <1>; + reg = <0x0 0x55000000 0x0 0x10000>; + memory-region = <&vdevbuffer>; + status = "disabled"; +}; + +&sdma1{ + status = "disabled"; +}; + +&sdma3{ + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; + +&sai3 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-sof-wm8960.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-sof-wm8960.dts new file mode 100644 index 00000000000000..a0607ca2a69e9b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-sof-wm8960.dts @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2020 + +#include "imx8mp-evk.dts" + +/ { + sound-wm8960 { + status = "disabled"; + }; + + sound-micfil { + status = "disabled"; + }; + + sai3_port: sai-port { + #sound-dai-cells = <0>; + compatible = "fsl,sai-dai"; + + dai-index = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + + power-domains = <&audiomix_pd>; + + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + + status="okay"; + }; + + sof-sound-wm8960 { + compatible = "simple-audio-card"; + label = "wm8960-audio"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + simple-audio-card,hp-det-gpio = <&gpio4 0 0>; + simple-audio-card,mic-det-gpio = <&gpio4 0 0>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Speaker", "Ext Spk", + "Microphone", "Mic Jack"; + simple-audio-card,audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Mic Jack", + "RINPUT2", "Mic Jack", + "Playback", "SAI3.OUT", + "SAI3.IN", "Capture"; + simple-audio-card,dai-link { + format = "i2s"; + cpu { + sound-dai = <&sai3_port>; + }; + plat { + sound-dai = <&dsp>; + }; + sndcodec: codec { + sound-dai = <&codec>; + }; + }; + }; +}; + +&dsp { + #sound-dai-cells = <0>; + compatible = "fsl,imx8mp-dsp"; + reg = <0x0 0x3B6E8000 0x0 0x88000>; + tplg-name = "sof-imx8mp-wm8960.tplg"; + + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_DSP_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_MU2_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_IPG>; + clock-names = "ocram", "core", "debug", "mu2", "sdma3", "sai3_ipg"; + machine-drv-name = "asoc-simple-card"; + status = "okay"; +}; + +&codec { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&sai3 { + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts new file mode 100644 index 00000000000000..062d7ca9f35854 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -0,0 +1,1272 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include +#include "imx8mp.dtsi" + +/ { + model = "NXP i.MX8MPlus EVK board"; + compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rpmsg_reserved: rpmsg@0x55800000 { + no-map; + reg = <0 0x55800000 0 0x800000>; + }; + }; + + chosen { + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status { + label = "status"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; /* LED GREEN */ + }; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + regulator-name = "can1-stby"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + regulator-name = "can2-stby"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb1_host_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_host_vbus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + cbtl04gp { + compatible = "nxp,cbtl04gp"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec_mux>; + switch-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; + orientation-switch; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; + + sound-hdmi { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + constraint-rate = <44100>, + <88200>, + <176400>, + <32000>, + <48000>, + <96000>, + <192000>; + status = "okay"; + }; + + sound-wm8960 { + compatible = "fsl,imx7d-evk-wm8960", "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai3>; + audio-codec = <&codec>; + asrc-controller = <&easrc>; + codec-master; + /* JD2: hp detect high for headphone*/ + hp-det = <3 0>; + hp-det-gpios = <&gpio4 28 0>; + mic-det-gpios = <&gpio4 28 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "LINPUT3", "Mic Jack", + "Mic Jack", "MICB", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + }; + + sound-micfil { + compatible = "fsl,imx-audio-micfil"; + model = "imx-audio-micfil"; + cpu-dai = <&micfil>; + }; + + sound-xcvr { + compatible = "fsl,imx-audio-xcvr"; + model = "imx-audio-xcvr"; + cpu-dai = <&xcvr>; + }; + + lvds_backlight: lvds_backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 100000>; + status = "okay"; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; +}; + +&aud2htx { + status = "okay"; +}; + +&clk { + init-on-array = ; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev1: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <500000>; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + pca9450,pmic-buck2-uses-i2c-dvs; + /* Run/Standby voltage */ + pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + adv_bridge: adv7535@3d { + compatible = "adi,adv7533"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_from_dsim: endpoint { + remote-endpoint = <&dsim_to_adv7535>; + }; + }; + }; + + lvds_bridge: lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + + port { + it6263_in: endpoint { + remote-endpoint = <&lvds_out>; + }; + }; + }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x50>; + interrupt-parent = <&gpio4>; + interrupts = <19 8>; + + port { + typec_dr_sw: endpoint { + remote-endpoint = <&usb3_drd_sw>; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; + + ov5640_0: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + powerdown-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + + port { + ov5640_mipi_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2>; + clock-lanes = <0>; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + ov5640_1: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + powerdown-gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "disabled"; + + port { + ov5640_mipi_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2>; + clock-lanes = <0>; + }; + }; + }; + + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; + clock-names = "mclk"; + wlf,shared-lrclk; + SPKVDD1-supply = <®_audio_pwr>; + }; +}; + +&irqsteer_hdmi { + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_stby>; + pinctrl-assert-gpios = <&pca6416 3 GPIO_ACTIVE_HIGH>; + status = "disabled";/* can2 pin conflict with pdm: gpio low select pdm, gpio high select can2 */ +}; + +&hdmimix_clk { + status = "okay"; +}; + +&hdmimix_reset { + status = "okay"; +}; + +&hdmi_pavi { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + +&lcdif1 { + status = "okay"; +}; + +&lcdif2 { + status = "okay"; +}; + +&lcdif3 { + status = "okay"; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds_out: endpoint { + remote-endpoint = <&it6263_in>; + }; + }; + }; +}; + +&ldb_phy { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + attach-bridge; + }; + }; +}; + +&easrc { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&micfil { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MP_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + +&pcie{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + disable-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; + ext_osc = <0>; + clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>, + <&clk IMX8MP_CLK_PCIE_AUX>, + <&clk IMX8MP_CLK_PCIE_PHY>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>, + <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL2_50M>; + reserved-region = <&rpmsg_reserved>; + status = "okay"; +}; + +&pcie_phy{ + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&xcvr { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&sdma2 { + status = "okay"; +}; + +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MP_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usb3_phy0 { + fsl,phy-tx-vref-tune = <6>; + fsl,phy-tx-rise-tune = <0>; + fsl,phy-tx-preemp-amp-tune = <3>; + fsl,phy-comp-dis-tune = <7>; + fsl,pcs-tx-deemph-3p5db = <0x21>; + fsl,phy-pcs-tx-swing-full = <0x7f>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + status = "okay"; + + port { + usb3_drd_sw: endpoint { + remote-endpoint = <&typec_dr_sw>; + }; + }; +}; + +&usb3_phy1 { + fsl,phy-tx-preemp-amp-tune = <2>; + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_EARC_SCL 0x400001c3 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_EARC_SDA 0x400001c3 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_EARC_DC_HPD 0x40000019 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_EARC_CEC 0x40000019 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 + >; + }; + + pinctrl_ecspi2_cs: ecspi2cs { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + >; + }; + + pinctrl_flexcan1_reg: flexcan1reggrp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ + >; + }; + + pinctrl_flexcan2_reg: flexcan2reggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x16 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__HSIOMIX_PCIE_CLKREQ_B 0x61 /* open drain, pull up */ + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41 + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + pinctrl_typec: typec1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4 + >; + }; + + pinctrl_typec_mux: typec1muxgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16 + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_CLK 0xd6 + MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_BIT_STREAM00 0xd6 + MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_BIT_STREAM01 0xd6 + MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_BIT_STREAM02 0xd6 + MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_BIT_STREAM03 0xd6 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0xd6 + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6 + >; + }; + + pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x16 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 + >; + }; + + pinctrl_usb1_vbus: usb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_csi0_pwn: csi0_pwn_grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x19 + >; + }; + + pinctrl_csi0_rst: csi0_rst_grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x19 + MX8MP_IOMUXC_GPIO1_IO15__CCMSRCGPCMIX_CLKO2 0x59 + >; + }; +}; + +&vpu_g1 { + status = "okay"; +}; + +&vpu_g2 { + status = "okay"; +}; + +&vpu_vc8000e { + status = "okay"; +}; + +&gpu_3d { + status = "okay"; +}; + +&gpu_2d { + status = "okay"; +}; + +&ml_vipsi { + status = "okay"; +}; + +&mix_gpu_ml { + status = "okay"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_0_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + }; + }; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&ov5640_mipi_1_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + }; + }; +}; + +&cameradev { + status = "okay"; +}; + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; + + m2m_device { + status = "okay"; + }; +}; + +&isi_1 { + status = "disabled"; + + cap_device { + status = "okay"; + }; +}; + +&dsp { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h new file mode 100644 index 00000000000000..319ab34cab3e5e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h @@ -0,0 +1,931 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __DTS_IMX8MP_PINFUNC_H +#define __DTS_IMX8MP_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO00__CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO00__MEDIAMIX_ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO00__ANAMIX_REF_CLK_32K 0x014 0x274 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO00__CCMSRCGPCMIX_EXT_CLK1 0x014 0x274 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO00__SJC_FAIL 0x014 0x274 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO01__MEDIAMIX_ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO01__ANAMIX_REF_CLK_24M 0x018 0x278 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO01__CCMSRCGPCMIX_EXT_CLK2 0x018 0x278 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO01__SJC_ACTIVE 0x018 0x278 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO02__MEDIAMIX_ISP_FLASH_TRIG_0 0x01C 0x27C 0x000 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_ANY 0x01C 0x27C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO02__SJC_DE_B 0x01C 0x27C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x020 0x280 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT 0x020 0x280 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO03__MEDIAMIX_ISP_PRELIGHT_TRIG_0 0x020 0x280 0x000 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO03__SDMA1_EXT_EVENT00 0x020 0x280 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO03__ANAMIX_XTAL_OK 0x020 0x280 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO03__SJC_DONE 0x020 0x280 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x024 0x284 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x024 0x284 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO04__MEDIAMIX_ISP_SHUTTER_OPEN_0 0x024 0x284 0x000 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO04__SDMA1_EXT_EVENT01 0x024 0x284 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO04__ANAMIX_XTAL_OK_LV 0x024 0x284 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO04__USDHC1_TEST_TRIG 0x024 0x284 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x028 0x288 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO05__M7_NMI 0x028 0x288 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO05__MEDIAMIX_ISP_FL_TRIG_1 0x028 0x288 0x5D8 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO05__CCMSRCGPCMIX_PMIC_READY 0x028 0x288 0x554 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO05__CCMSRCGPCMIX_INT_BOOT 0x028 0x288 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO05__USDHC2_TEST_TRIG 0x028 0x288 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x02C 0x28C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO06__ENET_QOS_MDC 0x02C 0x28C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO06__MEDIAMIX_ISP_SHUTTER_TRIG_1 0x02C 0x28C 0x5E0 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO06__USDHC1_CD_B 0x02C 0x28C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO06__CCMSRCGPCMIX_EXT_CLK3 0x02C 0x28C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO06__ECSPI1_TEST_TRIG 0x02C 0x28C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x030 0x290 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO07__ENET_QOS_MDIO 0x030 0x290 0x590 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO07__MEDIAMIX_ISP_FLASH_TRIG_1 0x030 0x290 0x000 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO07__USDHC1_WP 0x030 0x290 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO07__CCMSRCGPCMIX_EXT_CLK4 0x030 0x290 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO07__ECSPI2_TEST_TRIG 0x030 0x290 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x034 0x294 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_IN 0x034 0x294 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO08__PWM1_OUT 0x034 0x294 0x000 0x2 0x0 +#define MX8MP_IOMUXC_GPIO1_IO08__MEDIAMIX_ISP_PRELIGHT_TRIG_1 0x034 0x294 0x000 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_AUX_IN 0x034 0x294 0x000 0x4 0x0 +#define MX8MP_IOMUXC_GPIO1_IO08__USDHC2_RESET_B 0x034 0x294 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO08__CCMSRCGPCMIX_WAIT 0x034 0x294 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO08__FLEXSPI_TEST_TRIG 0x034 0x294 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x038 0x298 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT 0x038 0x298 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x038 0x298 0x000 0x2 0x0 +#define MX8MP_IOMUXC_GPIO1_IO09__MEDIAMIX_ISP_SHUTTER_OPEN_1 0x038 0x298 0x000 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x038 0x298 0x000 0x4 0x0 +#define MX8MP_IOMUXC_GPIO1_IO09__AUDIOMIX_EXT_EVENT00 0x038 0x298 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO09__CCMSRCGPCMIX_STOP 0x038 0x298 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO09__RAWNAND_TEST_TRIG 0x038 0x298 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x03C 0x29C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO10__HSIOMIX_usb1_OTG_ID 0x03C 0x29C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x03C 0x29C 0x000 0x2 0x0 +#define MX8MP_IOMUXC_GPIO1_IO10__OCOTP_FUSE_LATCHED 0x03C 0x29C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x040 0x2A0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO11__HSIOMIX_usb2_OTG_ID 0x040 0x2A0 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x040 0x2A0 0x000 0x2 0x0 +#define MX8MP_IOMUXC_GPIO1_IO11__USDHC3_VSELECT 0x040 0x2A0 0x000 0x4 0x0 +#define MX8MP_IOMUXC_GPIO1_IO11__CCMSRCGPCMIX_PMIC_READY 0x040 0x2A0 0x554 0x5 0x1 +#define MX8MP_IOMUXC_GPIO1_IO11__CCMSRCGPCMIX_OUT0 0x040 0x2A0 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO11__CAAM_RNG_OSC_OBS 0x040 0x2A0 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x044 0x2A4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO12__HSIOMIX_usb1_OTG_PWR 0x044 0x2A4 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO12__AUDIOMIX_EXT_EVENT01 0x044 0x2A4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO12__CCMSRCGPCMIX_OUT1 0x044 0x2A4 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO12__CSU_CSU_ALARM_AUT00 0x044 0x2A4 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x048 0x2A8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO13__HSIOMIX_usb1_OTG_OC 0x048 0x2A8 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO13__PWM2_OUT 0x048 0x2A8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO13__CCMSRCGPCMIX_OUT2 0x048 0x2A8 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO13__CSU_CSU_ALARM_AUT01 0x048 0x2A8 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x04C 0x2AC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO14__HSIOMIX_usb2_OTG_PWR 0x04C 0x2AC 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO14__USDHC3_CD_B 0x04C 0x2AC 0x608 0x4 0x0 +#define MX8MP_IOMUXC_GPIO1_IO14__PWM3_OUT 0x04C 0x2AC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO14__CCMSRCGPCMIX_CLKO1 0x04C 0x2AC 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO14__CSU_CSU_ALARM_AUT02 0x04C 0x2AC 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x050 0x2B0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO15__HSIOMIX_usb2_OTG_OC 0x050 0x2B0 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO15__USDHC3_WP 0x050 0x2B0 0x634 0x4 0x0 +#define MX8MP_IOMUXC_GPIO1_IO15__PWM4_OUT 0x050 0x2B0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO15__CCMSRCGPCMIX_CLKO2 0x050 0x2B0 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO15__CSU_CSU_INT_DEB 0x050 0x2B0 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x054 0x2B4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_MDC__AUDIOMIX_SAI6_TX_DATA00 0x054 0x2B4 0x000 0x2 0x0 +#define MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16 0x054 0x2B4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_MDC__USDHC3_STROBE 0x054 0x2B4 0x630 0x6 0x0 +#define MX8MP_IOMUXC_ENET_MDC__SIM_M_HADDR15 0x054 0x2B4 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x058 0x2B8 0x590 0x0 0x1 +#define MX8MP_IOMUXC_ENET_MDIO__AUDIOMIX_SAI6_TX_SYNC 0x058 0x2B8 0x528 0x2 0x0 +#define MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17 0x058 0x2B8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_MDIO__USDHC3_DATA5 0x058 0x2B8 0x624 0x6 0x0 +#define MX8MP_IOMUXC_ENET_MDIO__SIM_M_HADDR16 0x058 0x2B8 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x05C 0x2BC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_TD3__AUDIOMIX_SAI6_TX_BCLK 0x05C 0x2BC 0x524 0x2 0x0 +#define MX8MP_IOMUXC_ENET_TD3__GPIO1_IO18 0x05C 0x2BC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_TD3__USDHC3_DATA6 0x05C 0x2BC 0x628 0x6 0x0 +#define MX8MP_IOMUXC_ENET_TD3__SIM_M_HADDR17 0x05C 0x2BC 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x060 0x2C0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x060 0x2C0 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ENET_TD2__AUDIOMIX_SAI6_RX_DATA00 0x060 0x2C0 0x51C 0x2 0x0 +#define MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19 0x060 0x2C0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_TD2__USDHC3_DATA7 0x060 0x2C0 0x62C 0x6 0x0 +#define MX8MP_IOMUXC_ENET_TD2__SIM_M_HADDR18 0x060 0x2C0 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x064 0x2C4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_TD1__AUDIOMIX_SAI6_RX_SYNC 0x064 0x2C4 0x520 0x2 0x0 +#define MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20 0x064 0x2C4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_TD1__USDHC3_CD_B 0x064 0x2C4 0x608 0x6 0x1 +#define MX8MP_IOMUXC_ENET_TD1__SIM_M_HADDR19 0x064 0x2C4 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x068 0x2C8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_TD0__AUDIOMIX_SAI6_RX_BCLK 0x068 0x2C8 0x518 0x2 0x0 +#define MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21 0x068 0x2C8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_TD0__USDHC3_WP 0x068 0x2C8 0x634 0x6 0x1 +#define MX8MP_IOMUXC_ENET_TD0__SIM_M_HADDR20 0x068 0x2C8 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x06C 0x2CC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SAI6_MCLK 0x06C 0x2CC 0x514 0x2 0x0 +#define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SPDIF_OUT 0x06C 0x2CC 0x000 0x3 0x0 +#define MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22 0x06C 0x2CC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_TX_CTL__USDHC3_DATA0 0x06C 0x2CC 0x610 0x6 0x0 +#define MX8MP_IOMUXC_ENET_TX_CTL__SIM_M_HADDR21 0x06C 0x2CC 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x070 0x2D0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_TXC__ENET_QOS_TX_ER 0x070 0x2D0 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ENET_TXC__AUDIOMIX_SAI7_TX_DATA00 0x070 0x2D0 0x000 0x2 0x0 +#define MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23 0x070 0x2D0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_TXC__USDHC3_DATA1 0x070 0x2D0 0x614 0x6 0x0 +#define MX8MP_IOMUXC_ENET_TXC__SIM_M_HADDR22 0x070 0x2D0 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x074 0x2D4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_SAI7_TX_SYNC 0x074 0x2D4 0x540 0x2 0x0 +#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_BIT_STREAM03 0x074 0x2D4 0x4CC 0x3 0x1 +#define MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24 0x074 0x2D4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_RX_CTL__USDHC3_DATA2 0x074 0x2D4 0x618 0x6 0x0 +#define MX8MP_IOMUXC_ENET_RX_CTL__SIM_M_HADDR23 0x074 0x2D4 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x078 0x2D8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x078 0x2D8 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_SAI7_TX_BCLK 0x078 0x2D8 0x53C 0x2 0x0 +#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_BIT_STREAM02 0x078 0x2D8 0x4C8 0x3 0x1 +#define MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25 0x078 0x2D8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_RXC__USDHC3_DATA3 0x078 0x2D8 0x61C 0x6 0x0 +#define MX8MP_IOMUXC_ENET_RXC__SIM_M_HADDR24 0x078 0x2D8 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x07C 0x2DC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_SAI7_RX_DATA00 0x07C 0x2DC 0x534 0x2 0x0 +#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_BIT_STREAM01 0x07C 0x2DC 0x4C4 0x3 0x1 +#define MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26 0x07C 0x2DC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_RD0__USDHC3_DATA4 0x07C 0x2DC 0x620 0x6 0x0 +#define MX8MP_IOMUXC_ENET_RD0__SIM_M_HADDR25 0x07C 0x2DC 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x080 0x2E0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_SAI7_RX_SYNC 0x080 0x2E0 0x538 0x2 0x0 +#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_BIT_STREAM00 0x080 0x2E0 0x4C0 0x3 0x1 +#define MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27 0x080 0x2E0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_RD1__USDHC3_RESET_B 0x080 0x2E0 0x000 0x6 0x0 +#define MX8MP_IOMUXC_ENET_RD1__SIM_M_HADDR26 0x080 0x2E0 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x084 0x2E4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_SAI7_RX_BCLK 0x084 0x2E4 0x530 0x2 0x0 +#define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_CLK 0x084 0x2E4 0x000 0x3 0x0 +#define MX8MP_IOMUXC_ENET_RD2__GPIO1_IO28 0x084 0x2E4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_RD2__USDHC3_CLK 0x084 0x2E4 0x604 0x6 0x0 +#define MX8MP_IOMUXC_ENET_RD2__SIM_M_HADDR27 0x084 0x2E4 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x088 0x2E8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SAI7_MCLK 0x088 0x2E8 0x52C 0x2 0x0 +#define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SPDIF_IN 0x088 0x2E8 0x544 0x3 0x0 +#define MX8MP_IOMUXC_ENET_RD3__GPIO1_IO29 0x088 0x2E8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_RD3__USDHC3_CMD 0x088 0x2E8 0x60C 0x6 0x0 +#define MX8MP_IOMUXC_ENET_RD3__SIM_M_HADDR28 0x088 0x2E8 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x08C 0x2EC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_CLK__ENET1_MDC 0x08C 0x2EC 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SD1_CLK__I2C5_SCL 0x08C 0x2EC 0x5C4 0x3 0x0 +#define MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x08C 0x2EC 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_CLK__UART1_DTE_RX 0x08C 0x2EC 0x5E8 0x4 0x0 +#define MX8MP_IOMUXC_SD1_CLK__GPIO2_IO00 0x08C 0x2EC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_CLK__SIM_M_HADDR29 0x08C 0x2EC 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x090 0x2F0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_CMD__ENET1_MDIO 0x090 0x2F0 0x57C 0x1 0x0 +#define MX8MP_IOMUXC_SD1_CMD__I2C5_SDA 0x090 0x2F0 0x5C8 0x3 0x0 +#define MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x090 0x2F0 0x5E8 0x4 0x1 +#define MX8MP_IOMUXC_SD1_CMD__UART1_DTE_TX 0x090 0x2F0 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_CMD__GPIO2_IO01 0x090 0x2F0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_CMD__SIM_M_HADDR30 0x090 0x2F0 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x094 0x2F4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_DATA0__ENET1_RGMII_TD1 0x094 0x2F4 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x094 0x2F4 0x5CC 0x3 0x0 +#define MX8MP_IOMUXC_SD1_DATA0__UART1_DCE_RTS 0x094 0x2F4 0x5E4 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA0__UART1_DTE_CTS 0x094 0x2F4 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x094 0x2F4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_DATA0__SIM_M_HADDR31 0x094 0x2F4 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x098 0x2F8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_DATA1__ENET1_RGMII_TD0 0x098 0x2F8 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x098 0x2F8 0x5D0 0x3 0x0 +#define MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS 0x098 0x2F8 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA1__UART1_DTE_RTS 0x098 0x2F8 0x5E4 0x4 0x1 +#define MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x098 0x2F8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_DATA1__SIM_M_HBURST00 0x098 0x2F8 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x09C 0x2FC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_DATA2__ENET1_RGMII_RD0 0x09C 0x2FC 0x580 0x1 0x0 +#define MX8MP_IOMUXC_SD1_DATA2__I2C4_SCL 0x09C 0x2FC 0x5BC 0x3 0x0 +#define MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x09C 0x2FC 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA2__UART2_DTE_RX 0x09C 0x2FC 0x5F0 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA2__GPIO2_IO04 0x09C 0x2FC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_DATA2__SIM_M_HBURST01 0x09C 0x2FC 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x0A0 0x300 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_DATA3__ENET1_RGMII_RD1 0x0A0 0x300 0x584 0x1 0x0 +#define MX8MP_IOMUXC_SD1_DATA3__I2C4_SDA 0x0A0 0x300 0x5C0 0x3 0x0 +#define MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x0A0 0x300 0x5F0 0x4 0x1 +#define MX8MP_IOMUXC_SD1_DATA3__UART2_DTE_TX 0x0A0 0x300 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA3__GPIO2_IO05 0x0A0 0x300 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_DATA3__SIM_M_HBURST02 0x0A0 0x300 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x0A4 0x304 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_DATA4__ENET1_RGMII_TX_CTL 0x0A4 0x304 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SD1_DATA4__I2C1_SCL 0x0A4 0x304 0x5A4 0x3 0x0 +#define MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x0A4 0x304 0x5EC 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA4__UART2_DTE_CTS 0x0A4 0x304 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x0A4 0x304 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_DATA4__SIM_M_HRESP 0x0A4 0x304 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x0A8 0x308 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_DATA5__ENET1_TX_ER 0x0A8 0x308 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA 0x0A8 0x308 0x5A8 0x3 0x0 +#define MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x0A8 0x308 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA5__UART2_DTE_RTS 0x0A8 0x308 0x5EC 0x4 0x1 +#define MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x0A8 0x308 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_DATA5__TPSMP_HDATA05 0x0A8 0x308 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x0AC 0x30C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_DATA6__ENET1_RGMII_RX_CTL 0x0AC 0x30C 0x588 0x1 0x0 +#define MX8MP_IOMUXC_SD1_DATA6__I2C2_SCL 0x0AC 0x30C 0x5AC 0x3 0x0 +#define MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x0AC 0x30C 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA6__UART3_DTE_RX 0x0AC 0x30C 0x5F8 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x0AC 0x30C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_DATA6__TPSMP_HDATA06 0x0AC 0x30C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x0B0 0x310 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_DATA7__ENET1_RX_ER 0x0B0 0x310 0x58C 0x1 0x0 +#define MX8MP_IOMUXC_SD1_DATA7__I2C2_SDA 0x0B0 0x310 0x5B0 0x3 0x0 +#define MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x0B0 0x310 0x5F8 0x4 0x1 +#define MX8MP_IOMUXC_SD1_DATA7__UART3_DTE_TX 0x0B0 0x310 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x0B0 0x310 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_DATA7__TPSMP_HDATA07 0x0B0 0x310 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x0B4 0x314 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_RESET_B__ENET1_TX_CLK 0x0B4 0x314 0x578 0x1 0x0 +#define MX8MP_IOMUXC_SD1_RESET_B__I2C3_SCL 0x0B4 0x314 0x5B4 0x3 0x0 +#define MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x0B4 0x314 0x5F4 0x4 0x0 +#define MX8MP_IOMUXC_SD1_RESET_B__UART3_DTE_CTS 0x0B4 0x314 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x0B4 0x314 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_RESET_B__ECSPI3_TEST_TRIG 0x0B4 0x314 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x0B8 0x318 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_STROBE__I2C3_SDA 0x0B8 0x318 0x5B8 0x3 0x0 +#define MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x0B8 0x318 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_STROBE__UART3_DTE_RTS 0x0B8 0x318 0x5F4 0x4 0x1 +#define MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x0B8 0x318 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_STROBE__USDHC3_TEST_TRIG 0x0B8 0x318 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x0BC 0x31C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0BC 0x31C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_CD_B__CCMSRCGPCMIX_TESTER_ACK 0x0BC 0x31C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x0C0 0x320 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_CLK__ECSPI2_SCLK 0x0C0 0x320 0x568 0x2 0x0 +#define MX8MP_IOMUXC_SD2_CLK__UART4_DCE_RX 0x0C0 0x320 0x600 0x3 0x0 +#define MX8MP_IOMUXC_SD2_CLK__UART4_DTE_TX 0x0C0 0x320 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x0C0 0x320 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0C0 0x320 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SD2_CLK__OBSERVE_MUX_OUT00 0x0C0 0x320 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x0C4 0x324 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_CMD__ECSPI2_MOSI 0x0C4 0x324 0x570 0x2 0x0 +#define MX8MP_IOMUXC_SD2_CMD__UART4_DCE_TX 0x0C4 0x324 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SD2_CMD__UART4_DTE_RX 0x0C4 0x324 0x600 0x3 0x1 +#define MX8MP_IOMUXC_SD2_CMD__AUDIOMIX_CLK 0x0C4 0x324 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x0C4 0x324 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0C4 0x324 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SD2_CMD__OBSERVE_MUX_OUT01 0x0C4 0x324 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x0C8 0x328 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_DATA0__I2C4_SDA 0x0C8 0x328 0x5C0 0x2 0x1 +#define MX8MP_IOMUXC_SD2_DATA0__UART2_DCE_RX 0x0C8 0x328 0x5F0 0x3 0x2 +#define MX8MP_IOMUXC_SD2_DATA0__UART2_DTE_TX 0x0C8 0x328 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SD2_DATA0__AUDIOMIX_BIT_STREAM00 0x0C8 0x328 0x4C0 0x4 0x2 +#define MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x0C8 0x328 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x0C8 0x328 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SD2_DATA0__OBSERVE_MUX_OUT02 0x0C8 0x328 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x0CC 0x32C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_DATA1__I2C4_SCL 0x0CC 0x32C 0x5BC 0x2 0x1 +#define MX8MP_IOMUXC_SD2_DATA1__UART2_DCE_TX 0x0CC 0x32C 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SD2_DATA1__UART2_DTE_RX 0x0CC 0x32C 0x5F0 0x3 0x3 +#define MX8MP_IOMUXC_SD2_DATA1__AUDIOMIX_BIT_STREAM01 0x0CC 0x32C 0x4C4 0x4 0x1 +#define MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x0CC 0x32C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0CC 0x32C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SD2_DATA1__OBSERVE_MUX_OUT03 0x0CC 0x32C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x0D0 0x330 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_DATA2__ECSPI2_SS0 0x0D0 0x330 0x574 0x2 0x0 +#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_SPDIF_OUT 0x0D0 0x330 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_BIT_STREAM02 0x0D0 0x330 0x4C8 0x4 0x1 +#define MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x0D0 0x330 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0D0 0x330 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SD2_DATA2__OBSERVE_MUX_OUT04 0x0D0 0x330 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x0D4 0x334 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_DATA3__ECSPI2_MISO 0x0D4 0x334 0x56C 0x2 0x0 +#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_SPDIF_IN 0x0D4 0x334 0x544 0x3 0x1 +#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_BIT_STREAM03 0x0D4 0x334 0x4CC 0x4 0x2 +#define MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x0D4 0x334 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0D4 0x334 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x0D8 0x338 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x0D8 0x338 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x0D8 0x338 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x0DC 0x33C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x0DC 0x33C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_WP__CORESIGHT_EVENTI 0x0DC 0x33C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SD2_WP__SIM_M_HMASTLOCK 0x0DC 0x33C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_ALE__RAWNAND_ALE 0x0E0 0x340 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x0E0 0x340 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_ALE__AUDIOMIX_SAI3_TX_BCLK 0x0E0 0x340 0x4E8 0x2 0x0 +#define MX8MP_IOMUXC_NAND_ALE__MEDIAMIX_ISP_FL_TRIG_0 0x0E0 0x340 0x5D4 0x3 0x1 +#define MX8MP_IOMUXC_NAND_ALE__UART3_DCE_RX 0x0E0 0x340 0x5F8 0x4 0x2 +#define MX8MP_IOMUXC_NAND_ALE__UART3_DTE_TX 0x0E0 0x340 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x0E0 0x340 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_ALE__CORESIGHT_TRACE_CLK 0x0E0 0x340 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_ALE__SIM_M_HPROT00 0x0E0 0x340 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_CE0_B__RAWNAND_CE0_B 0x0E4 0x344 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x0E4 0x344 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_CE0_B__AUDIOMIX_SAI3_TX_DATA00 0x0E4 0x344 0x000 0x2 0x0 +#define MX8MP_IOMUXC_NAND_CE0_B__MEDIAMIX_ISP_SHUTTER_TRIG_0 0x0E4 0x344 0x5DC 0x3 0x1 +#define MX8MP_IOMUXC_NAND_CE0_B__UART3_DCE_TX 0x0E4 0x344 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_CE0_B__UART3_DTE_RX 0x0E4 0x344 0x5F8 0x4 0x3 +#define MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x0E4 0x344 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_CE0_B__CORESIGHT_TRACE_CTL 0x0E4 0x344 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_CE0_B__SIM_M_HPROT01 0x0E4 0x344 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_CE1_B__RAWNAND_CE1_B 0x0E8 0x348 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_CE1_B__FLEXSPI_A_SS1_B 0x0E8 0x348 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x0E8 0x348 0x630 0x2 0x1 +#define MX8MP_IOMUXC_NAND_CE1_B__I2C4_SCL 0x0E8 0x348 0x5BC 0x4 0x2 +#define MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02 0x0E8 0x348 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_CE1_B__CORESIGHT_TRACE00 0x0E8 0x348 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_CE1_B__SIM_M_HPROT02 0x0E8 0x348 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_CE2_B__RAWNAND_CE2_B 0x0EC 0x34C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_CE2_B__FLEXSPI_B_SS0_B 0x0EC 0x34C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x0EC 0x34C 0x624 0x2 0x1 +#define MX8MP_IOMUXC_NAND_CE2_B__I2C4_SDA 0x0EC 0x34C 0x5C0 0x4 0x2 +#define MX8MP_IOMUXC_NAND_CE2_B__GPIO3_IO03 0x0EC 0x34C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_CE2_B__CORESIGHT_TRACE01 0x0EC 0x34C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_CE2_B__SIM_M_HPROT03 0x0EC 0x34C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_CE3_B__RAWNAND_CE3_B 0x0F0 0x350 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_CE3_B__FLEXSPI_B_SS1_B 0x0F0 0x350 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x0F0 0x350 0x628 0x2 0x1 +#define MX8MP_IOMUXC_NAND_CE3_B__I2C3_SDA 0x0F0 0x350 0x5B8 0x4 0x1 +#define MX8MP_IOMUXC_NAND_CE3_B__GPIO3_IO04 0x0F0 0x350 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_CE3_B__CORESIGHT_TRACE02 0x0F0 0x350 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_CE3_B__SIM_M_HADDR00 0x0F0 0x350 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_CLE__RAWNAND_CLE 0x0F4 0x354 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_CLE__FLEXSPI_B_SCLK 0x0F4 0x354 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x0F4 0x354 0x62C 0x2 0x1 +#define MX8MP_IOMUXC_NAND_CLE__UART4_DCE_RX 0x0F4 0x354 0x600 0x4 0x2 +#define MX8MP_IOMUXC_NAND_CLE__UART4_DTE_TX 0x0F4 0x354 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_CLE__GPIO3_IO05 0x0F4 0x354 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_CLE__CORESIGHT_TRACE03 0x0F4 0x354 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_CLE__SIM_M_HADDR01 0x0F4 0x354 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_DATA00__RAWNAND_DATA00 0x0F8 0x358 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x0F8 0x358 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DATA00__AUDIOMIX_SAI3_RX_DATA00 0x0F8 0x358 0x4E4 0x2 0x0 +#define MX8MP_IOMUXC_NAND_DATA00__MEDIAMIX_ISP_FLASH_TRIG_0 0x0F8 0x358 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA00__UART4_DCE_RX 0x0F8 0x358 0x600 0x4 0x3 +#define MX8MP_IOMUXC_NAND_DATA00__UART4_DTE_TX 0x0F8 0x358 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x0F8 0x358 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DATA00__CORESIGHT_TRACE04 0x0F8 0x358 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DATA00__SIM_M_HADDR02 0x0F8 0x358 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_DATA01__RAWNAND_DATA01 0x0FC 0x35C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x0FC 0x35C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DATA01__AUDIOMIX_SAI3_TX_SYNC 0x0FC 0x35C 0x4EC 0x2 0x0 +#define MX8MP_IOMUXC_NAND_DATA01__MEDIAMIX_ISP_PRELIGHT_TRIG_0 0x0FC 0x35C 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA01__UART4_DCE_TX 0x0FC 0x35C 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_DATA01__UART4_DTE_RX 0x0FC 0x35C 0x600 0x4 0x4 +#define MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x0FC 0x35C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DATA01__CORESIGHT_TRACE05 0x0FC 0x35C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DATA01__SIM_M_HADDR03 0x0FC 0x35C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_DATA02__RAWNAND_DATA02 0x100 0x360 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x100 0x360 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DATA02__USDHC3_CD_B 0x100 0x360 0x608 0x2 0x2 +#define MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS 0x100 0x360 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA02__UART4_DTE_RTS 0x100 0x360 0x5FC 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA02__I2C4_SDA 0x100 0x360 0x5C0 0x4 0x3 +#define MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x100 0x360 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DATA02__CORESIGHT_TRACE06 0x100 0x360 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DATA02__SIM_M_HADDR04 0x100 0x360 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_DATA03__RAWNAND_DATA03 0x104 0x364 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x104 0x364 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DATA03__USDHC3_WP 0x104 0x364 0x634 0x2 0x2 +#define MX8MP_IOMUXC_NAND_DATA03__UART4_DCE_RTS 0x104 0x364 0x5FC 0x3 0x1 +#define MX8MP_IOMUXC_NAND_DATA03__UART4_DTE_CTS 0x104 0x364 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA03__MEDIAMIX_ISP_FL_TRIG_1 0x104 0x364 0x5D8 0x4 0x1 +#define MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x104 0x364 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DATA03__CORESIGHT_TRACE07 0x104 0x364 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DATA03__SIM_M_HADDR05 0x104 0x364 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_DATA04__RAWNAND_DATA04 0x108 0x368 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_B_DATA00 0x108 0x368 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x108 0x368 0x610 0x2 0x1 +#define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_A_DATA04 0x108 0x368 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA04__MEDIAMIX_ISP_SHUTTER_TRIG_1 0x108 0x368 0x5E0 0x4 0x1 +#define MX8MP_IOMUXC_NAND_DATA04__GPIO3_IO10 0x108 0x368 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DATA04__CORESIGHT_TRACE08 0x108 0x368 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DATA04__SIM_M_HADDR06 0x108 0x368 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_DATA05__RAWNAND_DATA05 0x10C 0x36C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_B_DATA01 0x10C 0x36C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x10C 0x36C 0x614 0x2 0x1 +#define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_A_DATA05 0x10C 0x36C 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA05__MEDIAMIX_ISP_FLASH_TRIG_1 0x10C 0x36C 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_DATA05__GPIO3_IO11 0x10C 0x36C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DATA05__CORESIGHT_TRACE09 0x10C 0x36C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DATA05__SIM_M_HADDR07 0x10C 0x36C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_DATA06__RAWNAND_DATA06 0x110 0x370 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_B_DATA02 0x110 0x370 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x110 0x370 0x618 0x2 0x1 +#define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_A_DATA06 0x110 0x370 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA06__MEDIAMIX_ISP_PRELIGHT_TRIG_1 0x110 0x370 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_DATA06__GPIO3_IO12 0x110 0x370 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DATA06__CORESIGHT_TRACE10 0x110 0x370 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DATA06__SIM_M_HADDR08 0x110 0x370 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_DATA07__RAWNAND_DATA07 0x114 0x374 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_B_DATA03 0x114 0x374 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x114 0x374 0x61C 0x2 0x1 +#define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_A_DATA07 0x114 0x374 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA07__MEDIAMIX_ISP_SHUTTER_OPEN_1 0x114 0x374 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_DATA07__GPIO3_IO13 0x114 0x374 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DATA07__CORESIGHT_TRACE11 0x114 0x374 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DATA07__SIM_M_HADDR09 0x114 0x374 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_DQS__RAWNAND_DQS 0x118 0x378 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x118 0x378 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DQS__AUDIOMIX_SAI3_MCLK 0x118 0x378 0x4E0 0x2 0x0 +#define MX8MP_IOMUXC_NAND_DQS__MEDIAMIX_ISP_SHUTTER_OPEN_0 0x118 0x378 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DQS__I2C3_SCL 0x118 0x378 0x5B4 0x4 0x1 +#define MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x118 0x378 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DQS__CORESIGHT_TRACE12 0x118 0x378 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DQS__SIM_M_HADDR10 0x118 0x378 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_RE_B__RAWNAND_RE_B 0x11C 0x37C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_RE_B__FLEXSPI_B_DQS 0x11C 0x37C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x11C 0x37C 0x620 0x2 0x1 +#define MX8MP_IOMUXC_NAND_RE_B__UART4_DCE_TX 0x11C 0x37C 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_RE_B__UART4_DTE_RX 0x11C 0x37C 0x600 0x4 0x5 +#define MX8MP_IOMUXC_NAND_RE_B__GPIO3_IO15 0x11C 0x37C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_RE_B__CORESIGHT_TRACE13 0x11C 0x37C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_RE_B__SIM_M_HADDR11 0x11C 0x37C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_READY_B__RAWNAND_READY_B 0x120 0x380 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x120 0x380 0x000 0x2 0x0 +#define MX8MP_IOMUXC_NAND_READY_B__I2C3_SCL 0x120 0x380 0x5B4 0x4 0x2 +#define MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x120 0x380 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_READY_B__CORESIGHT_TRACE14 0x120 0x380 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_READY_B__SIM_M_HADDR12 0x120 0x380 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_WE_B__RAWNAND_WE_B 0x124 0x384 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x124 0x384 0x604 0x2 0x1 +#define MX8MP_IOMUXC_NAND_WE_B__I2C3_SDA 0x124 0x384 0x5B8 0x4 0x2 +#define MX8MP_IOMUXC_NAND_WE_B__GPIO3_IO17 0x124 0x384 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_WE_B__CORESIGHT_TRACE15 0x124 0x384 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_WE_B__SIM_M_HADDR13 0x124 0x384 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_WP_B__RAWNAND_WP_B 0x128 0x388 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x128 0x388 0x60C 0x2 0x1 +#define MX8MP_IOMUXC_NAND_WP_B__I2C4_SCL 0x128 0x388 0x5BC 0x4 0x3 +#define MX8MP_IOMUXC_NAND_WP_B__GPIO3_IO18 0x128 0x388 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_WP_B__CORESIGHT_EVENTO 0x128 0x388 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_WP_B__SIM_M_HADDR14 0x128 0x388 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x12C 0x38C 0x508 0x0 0x0 +#define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x12C 0x38C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x12C 0x38C 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x12C 0x38C 0x5CC 0x3 0x1 +#define MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x12C 0x38C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI5_RX_BCLK 0x130 0x390 0x4F4 0x0 0x0 +#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI1_TX_DATA01 0x130 0x390 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x130 0x390 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x130 0x390 0x5D0 0x3 0x1 +#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_CLK 0x130 0x390 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x130 0x390 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x134 0x394 0x4F8 0x0 0x0 +#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI1_TX_DATA02 0x134 0x394 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x134 0x394 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x134 0x394 0x5C4 0x3 0x1 +#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_BIT_STREAM00 0x134 0x394 0x4C0 0x4 0x3 +#define MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x134 0x394 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_RX_DATA01 0x138 0x398 0x4FC 0x0 0x0 +#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_DATA03 0x138 0x398 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x138 0x398 0x4D8 0x2 0x0 +#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0x138 0x398 0x510 0x3 0x0 +#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_BIT_STREAM01 0x138 0x398 0x4C4 0x4 0x3 +#define MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x138 0x398 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x138 0x398 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_RX_DATA02 0x13C 0x39C 0x500 0x0 0x0 +#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_DATA04 0x13C 0x39C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_SYNC 0x13C 0x39C 0x4D8 0x2 0x1 +#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0x13C 0x39C 0x50C 0x3 0x0 +#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_BIT_STREAM02 0x13C 0x39C 0x4C8 0x4 0x3 +#define MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x13C 0x39C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x13C 0x39C 0x54C 0x6 0x0 +#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_RX_DATA03 0x140 0x3A0 0x504 0x0 0x0 +#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_DATA05 0x140 0x3A0 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_SYNC 0x140 0x3A0 0x4D8 0x2 0x2 +#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0x140 0x3A0 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_BIT_STREAM03 0x140 0x3A0 0x4CC 0x4 0x3 +#define MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x140 0x3A0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x140 0x3A0 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0x144 0x3A4 0x4F0 0x0 0x0 +#define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x144 0x3A4 0x4D4 0x1 0x0 +#define MX8MP_IOMUXC_SAI5_MCLK__PWM1_OUT 0x144 0x3A4 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA 0x144 0x3A4 0x5C8 0x3 0x1 +#define MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x144 0x3A4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x144 0x3A4 0x550 0x6 0x0 +#define MX8MP_IOMUXC_SAI1_RXFS__AUDIOMIX_SAI1_RX_SYNC 0x148 0x3A8 0x4D0 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x148 0x3A8 0x508 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x148 0x3A8 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x148 0x3A8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_SAI1_RX_BCLK 0x14C 0x3AC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_SAI5_RX_BCLK 0x14C 0x3AC 0x4F4 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_CLK 0x14C 0x3AC 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x14C 0x3AC 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x14C 0x3AC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x150 0x3B0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x150 0x3B0 0x4F8 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_TX_DATA01 0x150 0x3B0 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_BIT_STREAM00 0x150 0x3B0 0x4C0 0x3 0x4 +#define MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x150 0x3B0 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x150 0x3B0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI1_RX_DATA01 0x154 0x3B4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI5_RX_DATA01 0x154 0x3B4 0x4FC 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_BIT_STREAM01 0x154 0x3B4 0x4C4 0x3 0x4 +#define MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x154 0x3B4 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x154 0x3B4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI1_RX_DATA02 0x158 0x3B8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI5_RX_DATA02 0x158 0x3B8 0x500 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_BIT_STREAM02 0x158 0x3B8 0x4C8 0x3 0x4 +#define MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x158 0x3B8 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x158 0x3B8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI1_RX_DATA03 0x15C 0x3BC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI5_RX_DATA03 0x15C 0x3BC 0x504 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_BIT_STREAM03 0x15C 0x3BC 0x4CC 0x3 0x4 +#define MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x15C 0x3BC 0x57C 0x4 0x1 +#define MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x15C 0x3BC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI1_RX_DATA04 0x160 0x3C0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_TX_BCLK 0x160 0x3C0 0x524 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_RX_BCLK 0x160 0x3C0 0x518 0x2 0x1 +#define MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x160 0x3C0 0x580 0x4 0x1 +#define MX8MP_IOMUXC_SAI1_RXD4__GPIO4_IO06 0x160 0x3C0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_RX_DATA05 0x164 0x3C4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_TX_DATA00 0x164 0x3C4 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_RX_DATA00 0x164 0x3C4 0x51C 0x2 0x1 +#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_RX_SYNC 0x164 0x3C4 0x4D0 0x3 0x1 +#define MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x164 0x3C4 0x584 0x4 0x1 +#define MX8MP_IOMUXC_SAI1_RXD5__GPIO4_IO07 0x164 0x3C4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI1_RX_DATA06 0x168 0x3C8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_TX_SYNC 0x168 0x3C8 0x528 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_RX_SYNC 0x168 0x3C8 0x520 0x2 0x1 +#define MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x168 0x3C8 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x168 0x3C8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_RX_DATA07 0x16C 0x3CC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI6_MCLK 0x16C 0x3CC 0x514 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_TX_SYNC 0x16C 0x3CC 0x4D8 0x2 0x3 +#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_TX_DATA04 0x16C 0x3CC 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x16C 0x3CC 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x16C 0x3CC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC 0x170 0x3D0 0x4D8 0x0 0x4 +#define MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI5_TX_SYNC 0x170 0x3D0 0x510 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x170 0x3D0 0x588 0x4 0x1 +#define MX8MP_IOMUXC_SAI1_TXFS__GPIO4_IO10 0x170 0x3D0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK 0x174 0x3D4 0x4D4 0x0 0x1 +#define MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI5_TX_BCLK 0x174 0x3D4 0x50C 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x174 0x3D4 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x174 0x3D4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 0x178 0x3D8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI5_TX_DATA00 0x178 0x3D8 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x178 0x3D8 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x178 0x3D8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 0x17C 0x3DC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI5_TX_DATA01 0x17C 0x3DC 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x17C 0x3DC 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x17C 0x3DC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 0x180 0x3E0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI5_TX_DATA02 0x180 0x3E0 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x180 0x3E0 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x180 0x3E0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03 0x184 0x3E4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI5_TX_DATA03 0x184 0x3E4 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x184 0x3E4 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x184 0x3E4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04 0x188 0x3E8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_RX_BCLK 0x188 0x3E8 0x518 0x1 0x2 +#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_TX_BCLK 0x188 0x3E8 0x524 0x2 0x2 +#define MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x188 0x3E8 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x188 0x3E8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI1_TX_DATA05 0x18C 0x3EC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_RX_DATA00 0x18C 0x3EC 0x51C 0x1 0x2 +#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_TX_DATA00 0x18C 0x3EC 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x18C 0x3EC 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x18C 0x3EC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI1_TX_DATA06 0x190 0x3F0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_RX_SYNC 0x190 0x3F0 0x520 0x1 0x2 +#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_TX_SYNC 0x190 0x3F0 0x528 0x2 0x2 +#define MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x190 0x3F0 0x58C 0x4 0x1 +#define MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x190 0x3F0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07 0x194 0x3F4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI6_MCLK 0x194 0x3F4 0x514 0x1 0x2 +#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_CLK 0x194 0x3F4 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI1_TXD7__ENET1_TX_ER 0x194 0x3F4 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x194 0x3F4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x198 0x3F8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI5_MCLK 0x198 0x3F8 0x4F0 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x198 0x3F8 0x4D4 0x2 0x2 +#define MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x198 0x3F8 0x578 0x4 0x1 +#define MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x198 0x3F8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_RX_SYNC 0x19C 0x3FC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_SYNC 0x19C 0x3FC 0x510 0x1 0x2 +#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_DATA01 0x19C 0x3FC 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_RX_DATA01 0x19C 0x3FC 0x4DC 0x3 0x0 +#define MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x19C 0x3FC 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI2_RXFS__UART1_DTE_RX 0x19C 0x3FC 0x5E8 0x4 0x2 +#define MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x19C 0x3FC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_BIT_STREAM02 0x19C 0x3FC 0x4C8 0x6 0x5 +#define MX8MP_IOMUXC_SAI2_RXFS__SIM_M_HSIZE00 0x19C 0x3FC 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI2_RX_BCLK 0x1A0 0x400 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK 0x1A0 0x400 0x50C 0x1 0x2 +#define MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x1A0 0x400 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x1A0 0x400 0x5E8 0x4 0x3 +#define MX8MP_IOMUXC_SAI2_RXC__UART1_DTE_TX 0x1A0 0x400 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x1A0 0x400 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_BIT_STREAM01 0x1A0 0x400 0x4C4 0x6 0x5 +#define MX8MP_IOMUXC_SAI2_RXC__SIM_M_HSIZE01 0x1A0 0x400 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0x1A4 0x404 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0x1A4 0x404 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x1A4 0x404 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_TX_DATA01 0x1A4 0x404 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1A4 0x404 0x5E4 0x4 0x2 +#define MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS 0x1A4 0x404 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x1A4 0x404 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_BIT_STREAM03 0x1A4 0x404 0x4CC 0x6 0x5 +#define MX8MP_IOMUXC_SAI2_RXD0__SIM_M_HSIZE02 0x1A4 0x404 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0x1A8 0x408 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI5_TX_DATA01 0x1A8 0x408 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI2_TXFS__ENET_QOS_1588_EVENT3_OUT 0x1A8 0x408 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_DATA01 0x1A8 0x408 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1A8 0x408 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS 0x1A8 0x408 0x5E4 0x4 0x3 +#define MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x1A8 0x408 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_BIT_STREAM02 0x1A8 0x408 0x4C8 0x6 0x6 +#define MX8MP_IOMUXC_SAI2_TXFS__SIM_M_HWRITE 0x1A8 0x408 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0x1AC 0x40C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI5_TX_DATA02 0x1AC 0x40C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x1AC 0x40C 0x54C 0x3 0x1 +#define MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1AC 0x40C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_BIT_STREAM01 0x1AC 0x40C 0x4C4 0x6 0x6 +#define MX8MP_IOMUXC_SAI2_TXC__SIM_M_HREADYOUT 0x1AC 0x40C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0x1B0 0x410 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI5_TX_DATA03 0x1B0 0x410 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN 0x1B0 0x410 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x1B0 0x410 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_AUX_IN 0x1B0 0x410 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x1B0 0x410 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI2_TXD0__CCMSRCGPCMIX_BOOT_MODE04 0x1B0 0x410 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SAI2_TXD0__TPSMP_CLK 0x1B0 0x410 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0x1B4 0x414 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI5_MCLK 0x1B4 0x414 0x4F0 0x1 0x2 +#define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_IN 0x1B4 0x414 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x1B4 0x414 0x550 0x3 0x1 +#define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_AUX_IN 0x1B4 0x414 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x1B4 0x414 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI3_MCLK 0x1B4 0x414 0x4E0 0x6 0x1 +#define MX8MP_IOMUXC_SAI2_MCLK__TPSMP_HDATA_DIR 0x1B4 0x414 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0x1B8 0x418 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI2_RX_DATA01 0x1B8 0x418 0x4DC 0x1 0x1 +#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x1B8 0x418 0x508 0x2 0x2 +#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01 0x1B8 0x418 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SPDIF_IN 0x1B8 0x418 0x544 0x4 0x2 +#define MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1B8 0x418 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_BIT_STREAM00 0x1B8 0x418 0x4C0 0x6 0x5 +#define MX8MP_IOMUXC_SAI3_RXFS__TPSMP_HTRANS00 0x1B8 0x418 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0x1BC 0x41C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI2_RX_DATA02 0x1BC 0x41C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI5_RX_BCLK 0x1BC 0x41C 0x4F4 0x2 0x2 +#define MX8MP_IOMUXC_SAI3_RXC__GPT1_CLK 0x1BC 0x41C 0x59C 0x3 0x0 +#define MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x1BC 0x41C 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI3_RXC__UART2_DTE_RTS 0x1BC 0x41C 0x5EC 0x4 0x2 +#define MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1BC 0x41C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_CLK 0x1BC 0x41C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SAI3_RXC__TPSMP_HTRANS01 0x1BC 0x41C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1C0 0x420 0x4E4 0x0 0x1 +#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI2_RX_DATA03 0x1C0 0x420 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 0x1C0 0x420 0x4F8 0x2 0x2 +#define MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x1C0 0x420 0x5EC 0x4 0x3 +#define MX8MP_IOMUXC_SAI3_RXD__UART2_DTE_CTS 0x1C0 0x420 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x1C0 0x420 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_BIT_STREAM01 0x1C0 0x420 0x4C4 0x6 0x7 +#define MX8MP_IOMUXC_SAI3_RXD__TPSMP_HDATA00 0x1C0 0x420 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1C4 0x424 0x4EC 0x0 0x1 +#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI2_TX_DATA01 0x1C4 0x424 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI5_RX_DATA01 0x1C4 0x424 0x4FC 0x2 0x2 +#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_DATA01 0x1C4 0x424 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI3_TXFS__UART2_DCE_RX 0x1C4 0x424 0x5F0 0x4 0x4 +#define MX8MP_IOMUXC_SAI3_TXFS__UART2_DTE_TX 0x1C4 0x424 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x1C4 0x424 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_BIT_STREAM03 0x1C4 0x424 0x4CC 0x6 0x6 +#define MX8MP_IOMUXC_SAI3_TXFS__TPSMP_HDATA01 0x1C4 0x424 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1C8 0x428 0x4E8 0x0 0x1 +#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI2_TX_DATA02 0x1C8 0x428 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI5_RX_DATA02 0x1C8 0x428 0x500 0x2 0x2 +#define MX8MP_IOMUXC_SAI3_TXC__GPT1_CAPTURE1 0x1C8 0x428 0x594 0x3 0x0 +#define MX8MP_IOMUXC_SAI3_TXC__UART2_DCE_TX 0x1C8 0x428 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI3_TXC__UART2_DTE_RX 0x1C8 0x428 0x5F0 0x4 0x5 +#define MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x1C8 0x428 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_BIT_STREAM02 0x1C8 0x428 0x4C8 0x6 0x7 +#define MX8MP_IOMUXC_SAI3_TXC__TPSMP_HDATA02 0x1C8 0x428 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x1CC 0x42C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI2_TX_DATA03 0x1CC 0x42C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI5_RX_DATA03 0x1CC 0x42C 0x504 0x2 0x2 +#define MX8MP_IOMUXC_SAI3_TXD__GPT1_CAPTURE2 0x1CC 0x42C 0x598 0x3 0x0 +#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SPDIF_EXT_CLK 0x1CC 0x42C 0x548 0x4 0x0 +#define MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x1CC 0x42C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI3_TXD__CCMSRCGPCMIX_BOOT_MODE05 0x1CC 0x42C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SAI3_TXD__TPSMP_HDATA03 0x1CC 0x42C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0x1D0 0x430 0x4E0 0x0 0x2 +#define MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x1D0 0x430 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI5_MCLK 0x1D0 0x430 0x4F0 0x2 0x3 +#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF_OUT 0x1D0 0x430 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1D0 0x430 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF_IN 0x1D0 0x430 0x544 0x6 0x3 +#define MX8MP_IOMUXC_SAI3_MCLK__TPSMP_HDATA04 0x1D0 0x430 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF_OUT 0x1D4 0x434 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x1D4 0x434 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x1D4 0x434 0x5C4 0x2 0x2 +#define MX8MP_IOMUXC_SPDIF_TX__GPT1_COMPARE1 0x1D4 0x434 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x1D4 0x434 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x1D4 0x434 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF_IN 0x1D8 0x438 0x544 0x0 0x4 +#define MX8MP_IOMUXC_SPDIF_RX__PWM2_OUT 0x1D8 0x438 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x1D8 0x438 0x5C8 0x2 0x2 +#define MX8MP_IOMUXC_SPDIF_RX__GPT1_COMPARE2 0x1D8 0x438 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x1D8 0x438 0x54C 0x4 0x2 +#define MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1D8 0x438 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPT1_COMPARE3 0x1DC 0x43C 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x1DC 0x43C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_SPDIF_EXT_CLK 0x1DC 0x43C 0x548 0x0 0x1 +#define MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x1DC 0x43C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1E0 0x440 0x558 0x0 0x0 +#define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x1E0 0x440 0x5F8 0x1 0x4 +#define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DTE_TX 0x1E0 0x440 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI1_SCLK__I2C1_SCL 0x1E0 0x440 0x5A4 0x2 0x1 +#define MX8MP_IOMUXC_ECSPI1_SCLK__AUDIOMIX_SAI7_RX_SYNC 0x1E0 0x440 0x538 0x3 0x1 +#define MX8MP_IOMUXC_ECSPI1_SCLK__GPIO5_IO06 0x1E0 0x440 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ECSPI1_SCLK__TPSMP_HDATA08 0x1E0 0x440 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1E4 0x444 0x560 0x0 0x0 +#define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x1E4 0x444 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DTE_RX 0x1E4 0x444 0x5F8 0x1 0x5 +#define MX8MP_IOMUXC_ECSPI1_MOSI__I2C1_SDA 0x1E4 0x444 0x5A8 0x2 0x1 +#define MX8MP_IOMUXC_ECSPI1_MOSI__AUDIOMIX_SAI7_RX_BCLK 0x1E4 0x444 0x530 0x3 0x1 +#define MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07 0x1E4 0x444 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ECSPI1_MOSI__TPSMP_HDATA09 0x1E4 0x444 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1E8 0x448 0x55C 0x0 0x0 +#define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x1E8 0x448 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DTE_RTS 0x1E8 0x448 0x5F4 0x1 0x2 +#define MX8MP_IOMUXC_ECSPI1_MISO__I2C2_SCL 0x1E8 0x448 0x5AC 0x2 0x1 +#define MX8MP_IOMUXC_ECSPI1_MISO__AUDIOMIX_SAI7_RX_DATA00 0x1E8 0x448 0x534 0x3 0x1 +#define MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x1E8 0x448 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ECSPI1_MISO__TPSMP_HDATA10 0x1E8 0x448 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0 0x1EC 0x44C 0x564 0x0 0x0 +#define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x1EC 0x44C 0x5F4 0x1 0x3 +#define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DTE_CTS 0x1EC 0x44C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI1_SS0__I2C2_SDA 0x1EC 0x44C 0x5B0 0x2 0x1 +#define MX8MP_IOMUXC_ECSPI1_SS0__AUDIOMIX_SAI7_TX_SYNC 0x1EC 0x44C 0x540 0x3 0x1 +#define MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1EC 0x44C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ECSPI1_SS0__TPSMP_HDATA11 0x1EC 0x44C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x1F0 0x450 0x568 0x0 0x1 +#define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1F0 0x450 0x600 0x1 0x6 +#define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DTE_TX 0x1F0 0x450 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI2_SCLK__I2C3_SCL 0x1F0 0x450 0x5B4 0x2 0x3 +#define MX8MP_IOMUXC_ECSPI2_SCLK__AUDIOMIX_SAI7_TX_BCLK 0x1F0 0x450 0x53C 0x3 0x1 +#define MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1F0 0x450 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ECSPI2_SCLK__TPSMP_HDATA12 0x1F0 0x450 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x1F4 0x454 0x570 0x0 0x1 +#define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1F4 0x454 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DTE_RX 0x1F4 0x454 0x600 0x1 0x7 +#define MX8MP_IOMUXC_ECSPI2_MOSI__I2C3_SDA 0x1F4 0x454 0x5B8 0x2 0x3 +#define MX8MP_IOMUXC_ECSPI2_MOSI__AUDIOMIX_SAI7_TX_DATA00 0x1F4 0x454 0x000 0x3 0x0 +#define MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1F4 0x454 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ECSPI2_MOSI__TPSMP_HDATA13 0x1F4 0x454 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1F8 0x458 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ECSPI2_MISO__TPSMP_HDATA14 0x1F8 0x458 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1F8 0x458 0x56C 0x0 0x1 +#define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1F8 0x458 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DTE_RTS 0x1F8 0x458 0x5FC 0x1 0x2 +#define MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL 0x1F8 0x458 0x5BC 0x2 0x4 +#define MX8MP_IOMUXC_ECSPI2_MISO__AUDIOMIX_SAI7_MCLK 0x1F8 0x458 0x52C 0x3 0x1 +#define MX8MP_IOMUXC_ECSPI2_MISO__CCMSRCGPCMIX_CLKO1 0x1F8 0x458 0x000 0x4 0x0 +#define MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0 0x1FC 0x45C 0x574 0x0 0x1 +#define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1FC 0x45C 0x5FC 0x1 0x3 +#define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DTE_CTS 0x1FC 0x45C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA 0x1FC 0x45C 0x5C0 0x2 0x4 +#define MX8MP_IOMUXC_ECSPI2_SS0__CCMSRCGPCMIX_CLKO2 0x1FC 0x45C 0x000 0x4 0x0 +#define MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1FC 0x45C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ECSPI2_SS0__TPSMP_HDATA15 0x1FC 0x45C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x200 0x460 0x5A4 0x0 0x2 +#define MX8MP_IOMUXC_I2C1_SCL__ENET_QOS_MDC 0x200 0x460 0x000 0x1 0x0 +#define MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x200 0x460 0x558 0x3 0x1 +#define MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x200 0x460 0x000 0x5 0x0 +#define MX8MP_IOMUXC_I2C1_SCL__TPSMP_HDATA16 0x200 0x460 0x000 0x7 0x0 +#define MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x204 0x464 0x5A8 0x0 0x2 +#define MX8MP_IOMUXC_I2C1_SDA__ENET_QOS_MDIO 0x204 0x464 0x590 0x1 0x2 +#define MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x204 0x464 0x560 0x3 0x1 +#define MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x204 0x464 0x000 0x5 0x0 +#define MX8MP_IOMUXC_I2C1_SDA__TPSMP_HDATA17 0x204 0x464 0x000 0x7 0x0 +#define MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x208 0x468 0x5AC 0x0 0x2 +#define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_IN 0x208 0x468 0x000 0x1 0x0 +#define MX8MP_IOMUXC_I2C2_SCL__USDHC3_CD_B 0x208 0x468 0x608 0x2 0x3 +#define MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x208 0x468 0x55C 0x3 0x1 +#define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_AUX_IN 0x208 0x468 0x000 0x4 0x0 +#define MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x208 0x468 0x000 0x5 0x0 +#define MX8MP_IOMUXC_I2C2_SCL__TPSMP_HDATA18 0x208 0x468 0x000 0x7 0x0 +#define MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x20C 0x46C 0x5B0 0x0 0x2 +#define MX8MP_IOMUXC_I2C2_SDA__ENET_QOS_1588_EVENT1_OUT 0x20C 0x46C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_I2C2_SDA__USDHC3_WP 0x20C 0x46C 0x634 0x2 0x3 +#define MX8MP_IOMUXC_I2C2_SDA__ECSPI1_SS0 0x20C 0x46C 0x564 0x3 0x1 +#define MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x20C 0x46C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_I2C2_SDA__TPSMP_HDATA19 0x20C 0x46C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x210 0x470 0x5B4 0x0 0x4 +#define MX8MP_IOMUXC_I2C3_SCL__PWM4_OUT 0x210 0x470 0x000 0x1 0x0 +#define MX8MP_IOMUXC_I2C3_SCL__GPT2_CLK 0x210 0x470 0x000 0x2 0x0 +#define MX8MP_IOMUXC_I2C3_SCL__ECSPI2_SCLK 0x210 0x470 0x568 0x3 0x2 +#define MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x210 0x470 0x000 0x5 0x0 +#define MX8MP_IOMUXC_I2C3_SCL__TPSMP_HDATA20 0x210 0x470 0x000 0x7 0x0 +#define MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x214 0x474 0x5B8 0x0 0x4 +#define MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x214 0x474 0x000 0x1 0x0 +#define MX8MP_IOMUXC_I2C3_SDA__GPT3_CLK 0x214 0x474 0x000 0x2 0x0 +#define MX8MP_IOMUXC_I2C3_SDA__ECSPI2_MOSI 0x214 0x474 0x570 0x3 0x2 +#define MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x214 0x474 0x000 0x5 0x0 +#define MX8MP_IOMUXC_I2C3_SDA__TPSMP_HDATA21 0x214 0x474 0x000 0x7 0x0 +#define MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x218 0x478 0x5BC 0x0 0x5 +#define MX8MP_IOMUXC_I2C4_SCL__PWM2_OUT 0x218 0x478 0x000 0x1 0x0 +#define MX8MP_IOMUXC_I2C4_SCL__HSIOMIX_PCIE_CLKREQ_B 0x218 0x478 0x5A0 0x2 0x0 +#define MX8MP_IOMUXC_I2C4_SCL__ECSPI2_MISO 0x218 0x478 0x56C 0x3 0x2 +#define MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x218 0x478 0x000 0x5 0x0 +#define MX8MP_IOMUXC_I2C4_SCL__TPSMP_HDATA22 0x218 0x478 0x000 0x7 0x0 +#define MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x21C 0x47C 0x5C0 0x0 0x5 +#define MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT 0x21C 0x47C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_I2C4_SDA__ECSPI2_SS0 0x21C 0x47C 0x574 0x3 0x2 +#define MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x21C 0x47C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_I2C4_SDA__TPSMP_HDATA23 0x21C 0x47C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x220 0x480 0x5E8 0x0 0x4 +#define MX8MP_IOMUXC_UART1_RXD__UART1_DTE_TX 0x220 0x480 0x000 0x0 0x0 +#define MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x220 0x480 0x000 0x1 0x0 +#define MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x220 0x480 0x000 0x5 0x0 +#define MX8MP_IOMUXC_UART1_RXD__TPSMP_HDATA24 0x220 0x480 0x000 0x7 0x0 +#define MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x224 0x484 0x000 0x0 0x0 +#define MX8MP_IOMUXC_UART1_TXD__UART1_DTE_RX 0x224 0x484 0x5E8 0x0 0x5 +#define MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x224 0x484 0x000 0x1 0x0 +#define MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x224 0x484 0x000 0x5 0x0 +#define MX8MP_IOMUXC_UART1_TXD__TPSMP_HDATA25 0x224 0x484 0x000 0x7 0x0 +#define MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x228 0x488 0x5F0 0x0 0x6 +#define MX8MP_IOMUXC_UART2_RXD__UART2_DTE_TX 0x228 0x488 0x000 0x0 0x0 +#define MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x228 0x488 0x000 0x1 0x0 +#define MX8MP_IOMUXC_UART2_RXD__GPT1_COMPARE3 0x228 0x488 0x000 0x3 0x0 +#define MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24 0x228 0x488 0x000 0x5 0x0 +#define MX8MP_IOMUXC_UART2_RXD__TPSMP_HDATA26 0x228 0x488 0x000 0x7 0x0 +#define MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x22C 0x48C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_UART2_TXD__UART2_DTE_RX 0x22C 0x48C 0x5F0 0x0 0x7 +#define MX8MP_IOMUXC_UART2_TXD__ECSPI3_SS0 0x22C 0x48C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_UART2_TXD__GPT1_COMPARE2 0x22C 0x48C 0x000 0x3 0x0 +#define MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x22C 0x48C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_UART2_TXD__TPSMP_HDATA27 0x22C 0x48C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x230 0x490 0x5F8 0x0 0x6 +#define MX8MP_IOMUXC_UART3_RXD__UART3_DTE_TX 0x230 0x490 0x000 0x0 0x0 +#define MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x230 0x490 0x000 0x1 0x0 +#define MX8MP_IOMUXC_UART3_RXD__UART1_DTE_RTS 0x230 0x490 0x5E4 0x1 0x4 +#define MX8MP_IOMUXC_UART3_RXD__USDHC3_RESET_B 0x230 0x490 0x000 0x2 0x0 +#define MX8MP_IOMUXC_UART3_RXD__GPT1_CAPTURE2 0x230 0x490 0x598 0x3 0x1 +#define MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x230 0x490 0x000 0x4 0x0 +#define MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x230 0x490 0x000 0x5 0x0 +#define MX8MP_IOMUXC_UART3_RXD__TPSMP_HDATA28 0x230 0x490 0x000 0x7 0x0 +#define MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x234 0x494 0x000 0x0 0x0 +#define MX8MP_IOMUXC_UART3_TXD__UART3_DTE_RX 0x234 0x494 0x5F8 0x0 0x7 +#define MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x234 0x494 0x5E4 0x1 0x5 +#define MX8MP_IOMUXC_UART3_TXD__UART1_DTE_CTS 0x234 0x494 0x000 0x1 0x0 +#define MX8MP_IOMUXC_UART3_TXD__USDHC3_VSELECT 0x234 0x494 0x000 0x2 0x0 +#define MX8MP_IOMUXC_UART3_TXD__GPT1_CLK 0x234 0x494 0x59C 0x3 0x1 +#define MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x234 0x494 0x550 0x4 0x2 +#define MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x234 0x494 0x000 0x5 0x0 +#define MX8MP_IOMUXC_UART3_TXD__TPSMP_HDATA29 0x234 0x494 0x000 0x7 0x0 +#define MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x238 0x498 0x600 0x0 0x8 +#define MX8MP_IOMUXC_UART4_RXD__UART4_DTE_TX 0x238 0x498 0x000 0x0 0x0 +#define MX8MP_IOMUXC_UART4_RXD__UART2_DCE_CTS 0x238 0x498 0x000 0x1 0x0 +#define MX8MP_IOMUXC_UART4_RXD__UART2_DTE_RTS 0x238 0x498 0x5EC 0x1 0x4 +#define MX8MP_IOMUXC_UART4_RXD__HSIOMIX_PCIE_CLKREQ_B 0x238 0x498 0x5A0 0x2 0x1 +#define MX8MP_IOMUXC_UART4_RXD__GPT1_COMPARE1 0x238 0x498 0x000 0x3 0x0 +#define MX8MP_IOMUXC_UART4_RXD__I2C6_SCL 0x238 0x498 0x5CC 0x4 0x2 +#define MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x238 0x498 0x000 0x5 0x0 +#define MX8MP_IOMUXC_UART4_RXD__TPSMP_HDATA30 0x238 0x498 0x000 0x7 0x0 +#define MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x23C 0x49C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_UART4_TXD__UART4_DTE_RX 0x23C 0x49C 0x600 0x0 0x9 +#define MX8MP_IOMUXC_UART4_TXD__UART2_DCE_RTS 0x23C 0x49C 0x5EC 0x1 0x5 +#define MX8MP_IOMUXC_UART4_TXD__UART2_DTE_CTS 0x23C 0x49C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_UART4_TXD__GPT1_CAPTURE1 0x23C 0x49C 0x594 0x3 0x1 +#define MX8MP_IOMUXC_UART4_TXD__I2C6_SDA 0x23C 0x49C 0x5D0 0x4 0x2 +#define MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x23C 0x49C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_UART4_TXD__TPSMP_HDATA31 0x23C 0x49C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_EARC_SCL 0x240 0x4A0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x240 0x4A0 0x5C4 0x3 0x3 +#define MX8MP_IOMUXC_HDMI_DDC_SCL__CAN1_TX 0x240 0x4A0 0x000 0x4 0x0 +#define MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x240 0x4A0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_HDMI_DDC_SCL__AUDIOMIX_test_out00 0x240 0x4A0 0x000 0x6 0x0 +#define MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_EARC_SDA 0x244 0x4A4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x244 0x4A4 0x5C8 0x3 0x3 +#define MX8MP_IOMUXC_HDMI_DDC_SDA__CAN1_RX 0x244 0x4A4 0x54C 0x4 0x3 +#define MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x244 0x4A4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_HDMI_DDC_SDA__AUDIOMIX_test_out01 0x244 0x4A4 0x000 0x6 0x0 +#define MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_EARC_CEC 0x248 0x4A8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_HDMI_CEC__I2C6_SCL 0x248 0x4A8 0x5CC 0x3 0x3 +#define MX8MP_IOMUXC_HDMI_CEC__CAN2_TX 0x248 0x4A8 0x000 0x4 0x0 +#define MX8MP_IOMUXC_HDMI_CEC__GPIO3_IO28 0x248 0x4A8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_EARC_DC_HPD 0x24C 0x4AC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_HDMI_HPD__AUDIOMIX_EARC_HDMI_HPD_O 0x24C 0x4AC 0x000 0x1 0x0 +#define MX8MP_IOMUXC_HDMI_HPD__I2C6_SDA 0x24C 0x4AC 0x5D0 0x3 0x3 +#define MX8MP_IOMUXC_HDMI_HPD__CAN2_RX 0x24C 0x4AC 0x550 0x4 0x3 +#define MX8MP_IOMUXC_HDMI_HPD__GPIO3_IO29 0x24C 0x4AC 0x000 0x5 0x0 + +#endif /* __DTS_IMX8MP_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi new file mode 100644 index 00000000000000..3e214af2ae2749 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -0,0 +1,2409 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "imx8mp-pinfunc.h" + +/ { + compatible = "fsl,imx8mp"; + interrupt-parent = <&gpc>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + isi0 = &isi_0; + isi1 = &isi_1; + csi0 = &mipi_csi_0; + csi1 = &mipi_csi_1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + idle-states { + entry-method = "psci"; + + cpu_pd_wait: cpu-pd-wait { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + + A53_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + clocks = <&clk IMX8MP_CLK_ARM>; + operating-points-v2 = <&a53_opp_table>; + enable-method = "psci"; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + }; + + A53_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + clocks = <&clk IMX8MP_CLK_ARM>; + operating-points-v2 = <&a53_opp_table>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + }; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + clocks = <&clk IMX8MP_CLK_ARM>; + operating-points-v2 = <&a53_opp_table>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + clocks = <&clk IMX8MP_CLK_ARM>; + operating-points-v2 = <&a53_opp_table>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + a53_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <850000>; + opp-supported-hw = <0x8a0>, <0x7>; + clock-latency-ns = <150000>; + opp-suspend; + }; + + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <950000>; + opp-supported-hw = <0xa0>, <0x7>; + clock-latency-ns = <150000>; + opp-suspend; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1000000>; + opp-supported-hw = <0x20>, <0x3>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + + ddr_pmu0: ddr_pmu@3d800000 { + compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; + reg = <0x0 0x3d800000 0x0 0x400000>; + interrupts = ; + }; + + edacmc: memory-controller@3d400000 { + compatible = "fsl,imx8mp-ddrc"; + reg = <0x0 0x3d400000 0x0 0x400000>; + interrupts = ; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + resmem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + +/* + * Memory reserved for optee usage. Please do not use. + * This will be automaticky added to dtb if OP-TEE is installed. + * optee@56000000 { + * reg = <0 0x56000000 0 0x2000000>; + * no-map; + * }; + */ + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x40000000 0 0xC0000000>; + linux,cma-default; + }; + + dsp_reserved: dsp@92400000 { + no-map; + reg = <0 0x92400000 0 0x2000000>; + }; + }; + + osc_32k: clock-osc-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "osc_32k"; + }; + + osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + clk_ext1: clock-ext1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + clk_ext2: clock-ext2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext2"; + }; + + clk_ext3: clock-ext3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext3"; + }; + + clk_ext4: clock-ext4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency= <133000000>; + clock-output-names = "clk_ext4"; + }; + + busfreq { /* BUSFREQ */ + compatible = "fsl,imx_busfreq"; + clocks = <&clk IMX8MP_DRAM_PLL_OUT>, <&clk IMX8MP_CLK_DRAM_ALT>, + <&clk IMX8MP_CLK_DRAM_APB>, <&clk IMX8MP_CLK_DRAM_APB>, + <&clk IMX8MP_CLK_DRAM_CORE>, <&clk IMX8MP_CLK_DRAM_ALT_ROOT>, + <&clk IMX8MP_SYS_PLL1_40M>, <&clk IMX8MP_SYS_PLL1_100M>, + <&clk IMX8MP_SYS_PLL2_333M>, <&clk IMX8MP_CLK_NOC>, + <&clk IMX8MP_CLK_AHB>, <&clk IMX8MP_CLK_MAIN_AXI>, + <&clk IMX8MP_CLK_24M>, <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_DRAM_PLL>; + clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", + "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m", + "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m", + "sys_pll1_800m", "dram_pll_div"; + }; + + power-domains { + compatible = "simple-bus"; + + /* HSIO SS */ + hsiomix_pd: hsiomix-pd { + compatible = "fsl,imx8m-pm-domain"; + active-wakeup; + rpm-always-on; + #power-domain-cells = <0>; + domain-index = <0>; + domain-name = "hsiomix"; + }; + + pcie_pd: pcie-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <1>; + domain-name = "pcie"; + parent-domains = <&hsiomix_pd>; + }; + + usb_otg1_pd: usbotg1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <2>; + domain-name = "usb_otg1"; + parent-domains = <&hsiomix_pd>; + }; + + + usb_otg2_pd: usbotg2-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <3>; + domain-name = "usb_otg2"; + parent-domains = <&hsiomix_pd>; + }; + + /* MLMIX */ + mlmix_pd: mlmix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <4>; + domain-name = "mlmix"; + clocks = <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>, + <&clk IMX8MP_CLK_NPU_ROOT>; + }; + + audiomix_pd: audiomix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <5>; + domain-name = "audiomix"; + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, + <&clk IMX8MP_CLK_AUDIO_AXI_DIV>; + }; + + gpumix_pd: gpumix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <6>; + domain-name = "gpumix"; + clocks = <&clk IMX8MP_CLK_GPU_ROOT>, <&clk IMX8MP_CLK_GPU_AHB>, + <&clk IMX8MP_CLK_GPU_AXI>; + }; + + gpu2d_pd: gpu2d-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <7>; + domain-name = "gpu2d"; + parent-domains = <&gpumix_pd>; + clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>; + }; + + gpu3d_pd: gpu3d-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <8>; + domain-name = "gpu3d"; + parent-domains = <&gpumix_pd>; + clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, + <&clk IMX8MP_CLK_GPU3D_SHADER_DIV>; + }; + + vpumix_pd: vpumix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <9>; + domain-name = "vpumix"; + clocks =<&clk IMX8MP_CLK_VPU_ROOT>; + }; + + vpu_g1_pd: vpug1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <10>; + domain-name = "vpu_g1"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; + }; + + vpu_g2_pd: vpug2-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <11>; + domain-name = "vpu_g2"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; + }; + + vpu_h1_pd: vpuh1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <12>; + domain-name = "vpu_h1"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; + }; + + mediamix_pd: mediamix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <13>; + domain-name = "mediamix"; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + }; + + ispdwp_pd: power-domain@14 { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <14>; + domain-name = "ispdwp"; + parent-domains = <&mediamix_pd>; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_DIV>; + }; + + mipi_phy1_pd: mipiphy1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <15>; + domain-name = "mipi_phy1"; + parent-domains = <&mediamix_pd>; + }; + + mipi_phy2_pd: mipiphy2-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <16>; + domain-name = "mipi_phy2"; + parent-domains = <&mediamix_pd>; + }; + + hdmimix_pd: hdmimix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <17>; + domain-name = "hdmimix"; + clocks = <&clk IMX8MP_CLK_HDMI_ROOT>, + <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_REF_266M>; + }; + + hdmi_phy_pd: hdmiphy-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <18>; + domain-name = "hdmi_phy"; + parent-domains = <&hdmimix_pd>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupt-parent = <&gic>; + interrupts = ; + interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <8000000>; + arm,no-tick-in-suspend; + interrupt-parent = <&gic>; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu 0x0>; + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + soc-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu 0x1>; + trips { + soc_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + soc_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x3e000000>; + + caam_sm: caam-sm@100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + + aips1: bus@30000000 { + compatible = "simple-bus"; + reg = <0x30000000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio1: gpio@30200000 { + compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; + reg = <0x30200000 0x10000>; + interrupts = , + ; + clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@30210000 { + compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; + reg = <0x30210000 0x10000>; + interrupts = , + ; + clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@30220000 { + compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; + reg = <0x30220000 0x10000>; + interrupts = , + ; + clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@30230000 { + compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; + reg = <0x30230000 0x10000>; + interrupts = , + ; + clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@30240000 { + compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; + reg = <0x30240000 0x10000>; + interrupts = , + ; + clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + tmu: tmu@30260000 { + compatible = "fsl,imx8mp-tmu"; + reg = <0x30260000 0x10000>; + clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; + #thermal-sensor-cells = <1>; + }; + + wdog1: watchdog@30280000 { + compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; + reg = <0x30280000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; + status = "disabled"; + }; + + iomuxc: pinctrl@30330000 { + compatible = "fsl,imx8mp-iomuxc"; + reg = <0x30330000 0x10000>; + }; + + gpr: iomuxc-gpr@30340000 { + compatible = "fsl,imx8mp-iomuxc-gpr", "fsl,imx7d-iomuxc-gpr", + "fsl,imx6q-iomuxc-gpr", "syscon"; + reg = <0x30340000 0x10000>; + }; + + ocotp: efuse@30350000 { + compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon"; + reg = <0x30350000 0x10000>; + clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; + /* For nvmem subnodes */ + #address-cells = <1>; + #size-cells = <1>; + + cpu_speed_grade: speed-grade@10 { + reg = <0x10 4>; + }; + + eth_mac1: mac-address@640 { + reg = <0x90 6>; + }; + + eth_mac2: mac-address@650 { + reg = <0x96 6>; + }; + }; + + anatop: anatop@30360000 { + compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop", + "syscon"; + reg = <0x30360000 0x10000>; + }; + + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; + clock-names = "ipg"; + }; + + snvs: snvs@30370000 { + compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; + reg = <0x30370000 0x10000>; + + snvs_rtc: snvs-rtc-lp{ + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap =<&snvs>; + offset = <0x34>; + interrupts = , + ; + clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; + clock-names = "snvs-rtc"; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; + clock-names = "snvs"; + linux,keycode = ; + wakeup-source; + }; + }; + + clk: clock-controller@30380000 { + compatible = "fsl,imx8mp-ccm"; + reg = <0x30380000 0x10000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, + <&clk_ext3>, <&clk_ext4>; + clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4"; + assigned-clocks = <&clk IMX8MP_CLK_NOC>, + <&clk IMX8MP_CLK_NOC_IO>, + <&clk IMX8MP_CLK_GIC>, + <&clk IMX8MP_CLK_AUDIO_AHB>, + <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, + <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>, + <&clk IMX8MP_AUDIO_PLL1>, + <&clk IMX8MP_AUDIO_PLL2>, + <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <1000000000>, + <800000000>, + <500000000>, + <400000000>, + <800000000>, + <400000000>, + <393216000>, + <361267200>, + <2079000000>; + }; + + src: src@30390000 { + compatible = "fsl,imx8mp-src", "fsl,imx8mq-src", "syscon"; + reg = <0x30390000 0x10000>; + interrupts = ; + #reset-cells = <1>; + }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mp-gpc"; + reg = <0x303a0000 0x10000>; + interrupt-parent = <&gic>; + interrupt-controller; + broken-wake-request-signals; + #interrupt-cells = <3>; + }; + }; + + aips2: bus@30400000 { + compatible = "simple-bus"; + reg = <0x30400000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pwm1: pwm@30660000 { + compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; + reg = <0x30660000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, + <&clk IMX8MP_CLK_PWM1_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@30670000 { + compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; + reg = <0x30670000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, + <&clk IMX8MP_CLK_PWM2_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@30680000 { + compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; + reg = <0x30680000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, + <&clk IMX8MP_CLK_PWM3_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@30690000 { + compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; + reg = <0x30690000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, + <&clk IMX8MP_CLK_PWM4_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + system_counter: timer@306a0000 { + compatible = "nxp,sysctr-timer"; + reg = <0x306a0000 0x20000>; + interrupts = ; + clocks = <&osc_24m>; + clock-names = "per"; + }; + }; + + aips3: bus@30800000 { + compatible = "simple-bus"; + reg = <0x30800000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ecspi1: spi@30820000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; + reg = <0x30820000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, + <&clk IMX8MP_CLK_ECSPI1_ROOT>; + clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi2: spi@30830000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; + reg = <0x30830000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, + <&clk IMX8MP_CLK_ECSPI2_ROOT>; + clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi3: spi@30840000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; + reg = <0x30840000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, + <&clk IMX8MP_CLK_ECSPI3_ROOT>; + clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart1: serial@30860000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_UART1_ROOT>, + <&clk IMX8MP_CLK_UART1_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart3: serial@30880000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_UART3_ROOT>, + <&clk IMX8MP_CLK_UART3_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial@30890000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_UART2_ROOT>, + <&clk IMX8MP_CLK_UART2_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + flexcan1: can@308c0000 { + compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan"; + reg = <0x308c0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_IPG_ROOT>, + <&clk IMX8MP_CLK_CAN1_ROOT>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8MP_CLK_CAN1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; + assigned-clock-rates = <40000000>; + fsl,clk-source= <0>; + fsl,stop-mode = <&gpr 0x10 4 0x10 20>; + status = "disabled"; + }; + + flexcan2: can@308d0000 { + compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan"; + reg = <0x308d0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_IPG_ROOT>, + <&clk IMX8MP_CLK_CAN2_ROOT>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8MP_CLK_CAN2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; + assigned-clock-rates = <40000000>; + fsl,clk-source= <0>; + fsl,stop-mode = <&gpr 0x10 5 0x10 21>; + status = "disabled"; + }; + + crypto: crypto@30900000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30900000 0x40000>; + ranges = <0 0x30900000 0x40000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_AHB>, + <&clk IMX8MP_CLK_IPG_ROOT>; + clock-names = "aclk", "ipg"; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + + sec_jr2: jr@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = ; + }; + }; + + i2c1: i2c@30a20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; + reg = <0x30a20000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; + status = "disabled"; + }; + + i2c2: i2c@30a30000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; + reg = <0x30a30000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; + status = "disabled"; + }; + + i2c3: i2c@30a40000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; + reg = <0x30a40000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; + status = "disabled"; + }; + + i2c4: i2c@30a50000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; + reg = <0x30a50000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; + status = "disabled"; + }; + + uart4: serial@30a60000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_UART4_ROOT>, + <&clk IMX8MP_CLK_UART4_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + mu: mu@30aa0000 { + compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_MU_ROOT>; + clock-names = "mu"; + #mbox-cells = <2>; + }; + + i2c5: i2c@30ad0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; + reg = <0x30ad0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; + status = "disabled"; + }; + + i2c6: i2c@30ae0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; + reg = <0x30ae0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; + status = "disabled"; + }; + + usdhc1: mmc@30b40000 { + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; + reg = <0x30b40000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_NAND_USDHC_BUS>, + <&clk IMX8MP_CLK_USDHC1_ROOT>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX8MP_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: mmc@30b50000 { + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; + reg = <0x30b50000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_NAND_USDHC_BUS>, + <&clk IMX8MP_CLK_USDHC2_ROOT>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc3: mmc@30b60000 { + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_NAND_USDHC_BUS>, + <&clk IMX8MP_CLK_USDHC3_ROOT>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + flexspi: spi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mm-fspi"; + reg = <0x30bb0000 0x10000>, <0x08000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = ; + clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, + <&clk IMX8MP_CLK_QSPI_ROOT>; + clock-names = "fspi", "fspi_en"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_QSPI>; + status = "disabled"; + }; + + sdma1: dma-controller@30bd0000 { + compatible = "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; + reg = <0x30bd0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, + <&clk IMX8MP_CLK_AHB>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + }; + + fec: ethernet@30be0000 { + compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; + reg = <0x30be0000 0x10000>; + interrupts = , + , + ; + clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, + <&clk IMX8MP_CLK_SIM_ENET_ROOT>, + <&clk IMX8MP_CLK_ENET_TIMER>, + <&clk IMX8MP_CLK_ENET_REF>, + <&clk IMX8MP_CLK_ENET_PHY_REF>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, + <&clk IMX8MP_CLK_ENET_TIMER>, + <&clk IMX8MP_CLK_ENET_REF>, + <&clk IMX8MP_CLK_ENET_TIMER>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_125M>; + assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; + nvmem-cells = <ð_mac1>; + nvmem-cell-names = "mac-address"; + nvmem_macaddr_swap; + stop-mode = <&gpr 0x10 3>; + fsl,wakeup_irq = <2>; + status = "disabled"; + }; + + eqos: ethernet@30bf0000 { + compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; + reg = <0x30bf0000 0x10000>; + interrupts = , + ; + interrupt-names = "eth_wake_irq", "macirq"; + clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, + <&clk IMX8MP_CLK_QOS_ENET_ROOT>, + <&clk IMX8MP_CLK_ENET_QOS_TIMER>, + <&clk IMX8MP_CLK_ENET_QOS>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; + assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, + <&clk IMX8MP_CLK_ENET_QOS_TIMER>, + <&clk IMX8MP_CLK_ENET_QOS>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_125M>; + assigned-clock-rates = <0>, <100000000>, <125000000>; + nvmem-cells = <ð_mac2>; + nvmem-cell-names = "mac-address"; + nvmem_macaddr_swap; + intf_mode = <&gpr 0x4>; + status = "disabled"; + }; + }; + + aips5: bus@30c00000 { + compatible = "simple-bus"; + reg = <0x30c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + spba-bus@30c00000 { + compatible = "fsl,spba-bus", "simple-bus"; + reg = <0x30c00000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sai1: sai@30c10000 { + compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x30c10000 0x10000>; + interrupts = ; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI1_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0 0xff 0xff>; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + sai2: sai@30c20000 { + compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x30c20000 0x10000>; + interrupts = ; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI2_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0 0xf 0xf>; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + sai3: sai@30c30000 { + compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x30c30000 0x10000>; + interrupts = ; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0 0x3 0x3>; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + sai5: sai@30c50000 { + compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x30c50000 0x10000>; + interrupts = ; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI5_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0 0xf 0xf>; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + sai6: sai@30c60000 { + compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x30c60000 0x10000>; + interrupts = ; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI6_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>, + <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + sai7: sai@30c80000 { + compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x30c80000 0x10000>; + interrupts = ; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI7_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + easrc: easrc@30c90000 { + compatible = "fsl,imx8mn-easrc"; + reg = <0x30c90000 0x10000>; + interrupts = ; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_ASRC_IPG>; + clock-names = "mem"; + dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, + <&sdma2 18 23 0> , <&sdma2 19 23 0>, + <&sdma2 20 23 0> , <&sdma2 21 23 0>, + <&sdma2 22 23 0> , <&sdma2 23 23 0>; + dma-names = "ctx0_rx", "ctx0_tx", + "ctx1_rx", "ctx1_tx", + "ctx2_rx", "ctx2_tx", + "ctx3_rx", "ctx3_tx"; + fsl,easrc-ram-script-name = "imx/easrc/easrc-imx8mn.bin"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + micfil: micfil@30ca0000 { + compatible = "fsl,imx8mp-micfil"; + reg = <0x30ca0000 0x10000>; + interrupts = , + , + , + ; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_PDM_IPG>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_PDM_ROOT>, + <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>, + <&clk IMX8MP_CLK_EXT3>; + clock-names = "ipg_clk", "ipg_clk_app", + "pll8k", "pll11k", "clkext3"; + dmas = <&sdma2 24 25 0x80000000>; + dma-names = "rx"; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + aud2htx: aud2htx@30cb0000 { + compatible = "fsl,imx8mp-aud2htx"; + reg = <0x30cb0000 0x10000>; + interrupts = ; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG>; + clock-names = "bus"; + dmas = <&sdma2 26 2 0>; + dma-names = "tx"; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + xcvr: xcvr@30cc0000 { + compatible = "fsl,imx8mp-xcvr"; + reg = <0x30cc0000 0x800>, + <0x30cc0800 0x400>, + <0x30cc0c00 0x080>, + <0x30cc0e00 0x080>; + reg-names = "ram", "regs", "rxfifo", + "txfifo"; + interrupts = /* XCVR IRQ 0 */ + , + /* XCVR IRQ 1 */ + , + /* XCVR PHY - SPDIF wakeup IRQ */ + ; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_IPG>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_PHY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>; + clock-names = "ipg", "phy", "spba", "pll_ipg"; + dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>; + dma-names = "rx", "tx"; + fsl,xcvr-fw = "imx/xcvr/xcvr-imx8mp.bin"; + resets = <&audiomix_reset 0>; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + }; + + sdma3: dma-controller@30e00000 { + compatible = "fsl,imx8mp-sdma", "fsl,imx7d-sdma"; + reg = <0x30e00000 0x10000>; + interrupts = ; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + fsl,ratio-1-1; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + sdma2: dma-controller@30e10000 { + compatible = "fsl,imx8mp-sdma", "fsl,imx7d-sdma"; + reg = <0x30e10000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>, + <&clk IMX8MP_CLK_AUDIO_AHB>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + fsl,ratio-1-1; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + audiomix: audiomix@30e20000 { + compatible = "fsl,imx8mp-audiomix"; + reg = <0x30e20000 0x10000>; + + audiomix_clk: clock-controller { + compatible = "fsl,imx8mp-audiomix-clk"; + #clock-cells = <1>; + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>; + clock-names = "audio_root"; + power-domains = <&audiomix_pd>; + }; + + audiomix_reset: reset-controller { + compatible = "fsl,imx8mp-audiomix-reset"; + power-domains = <&audiomix_pd>; + #reset-cells = <1>; + }; + + audiomix_dsp: audiomix_dsp { + compatible = "fsl,audiomix-dsp"; + }; + }; + + mu2: mu2@30e60000 { + compatible = "fsl,imx8-mu-dsp", "fsl,imx6sx-mu"; + reg = <0x30E60000 0x10000>; + interrupts = ; + fsl,dsp_ap_mu_id = <2>; + #mbox-cells = <2>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_MU2_ROOT>; + status = "okay"; + }; + }; + + aips4: bus@32c00000 { + compatible = "simple-bus"; + reg = <0x32c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mipi_dsi: mipi_dsi@32e60000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-mipi-dsim"; + reg = <0x32e60000 0x10000>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + clock-names = "cfg", "pll-ref"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + assigned-clock-rates = <27000000>; + interrupts = ; + power-domains = <&mipi_phy1_pd>; + status = "disabled"; + + port@0 { + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + + lcdif1: lcd-controller@32e80000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-lcdif1"; + reg = <0x32e80000 0x10000>; + clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "pix", "disp-axi", "disp-apb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <500000000>, <200000000>; + interrupts = ; + blk-ctl = <&mediamix_blk_ctl>; + power-domains = <&mediamix_pd>; + status = "disabled"; + + lcdif1_disp: port@0 { + reg = <0>; + + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + lcdif2: lcd-controller@32e90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-lcdif2"; + reg = <0x32e90000 0x10000>; + clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "pix", "disp-axi", "disp-apb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <1039500000>, <500000000>, <200000000>; + interrupts = ; + power-domains = <&mediamix_pd>; + status = "disabled"; + + lcdif2_disp: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + lcdif2_disp_ldb_ch0: endpoint@0 { + reg = <0>; + remote-endpoint = <&ldb_ch0>; + }; + + lcdif2_disp_ldb_ch1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ldb_ch1>; + }; + }; + }; + + mediamix_blk_ctl: blk-ctl@32ec0000 { + compatible = "fsl,imx8mp-mediamix-blk-ctl", + "syscon"; + reg = <0x32ec0000 0x10000>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + }; + + ldb: ldb@32ec005c { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ldb"; + clocks = <&clk IMX8MP_CLK_MEDIA_LDB_ROOT>; + clock-names = "ldb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + gpr = <&mediamix_blk_ctl>; + power-domains = <&mediamix_pd>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb_phy1>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb_ch0: endpoint { + remote-endpoint = <&lcdif2_disp_ldb_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb_phy2>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb_ch1: endpoint { + remote-endpoint = <&lcdif2_disp_ldb_ch1>; + }; + }; + }; + }; + + /* TODO for HDMI PHY power on */ + hdmi_blk: hdmi-blk@32fc0000 { + compatible = "syscon"; + reg = <0x32fc0000 0x1000>; + }; + + hdmimix: hdmimix@32fc0000 { + compatible = "fsl,imx8mp-audiomix", "fsl,imx8mp-hdmimix"; + reg = <0x32fc0000 0x1000>; + + hdmimix_clk: clock-controller { + compatible = "fsl,imx8mp-hdmimix-clk"; + #clock-cells = <1>; + clocks = <&clk IMX8MP_CLK_DUMMY>; + clock-names = "dummy"; + status = "disabled"; + }; + + hdmimix_reset: reset-controller { + compatible = "fsl,imx8mp-hdmimix-reset"; + #reset-cells = <1>; + status = "disabled"; + }; + }; + + irqsteer_hdmi: irqsteer@32fc2000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x32fc2000 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + fsl,channel = <1>; + fsl,num-irqs = <64>; + clocks = <&hdmimix_clk IMX8MP_CLK_HDMIMIX_IRQS_STEER_CLK>; + clock-names = "ipg"; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <200000000>; + resets = <&hdmimix_reset IMX_HDMIMIX_IRQ_STEER_RESET>; + status = "disabled"; + }; + + hdmi_pavi: hdmi-pai-pvi@32fc4000 { + compatible = "fsl,imx8mp-hdmi-pavi"; + reg = <0x32fc4000 0x1000>; + clocks = <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_VID_LINK_PIX_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_GPA_CLK>; + clock-names = "pvi_clk", "pai_clk"; + resets = <&hdmimix_reset IMX_HDMIMIX_HDMI_PAI_RESET>, + <&hdmimix_reset IMX_HDMIMIX_HDMI_PVI_RESET>; + reset-names = "pai_rst", "pvi_rst"; + status = "disabled"; + }; + + lcdif3: lcd-controller@32fc6000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-lcdif3"; + reg = <0x32fc6000 0x10000>; + clocks = <&hdmiphy 0>, + <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_APB>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_APB_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_B_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_XTAL24M_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_TX_PIX_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_APB_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_B_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_PDI_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_PIX_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_SPU_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_NOC_HDMI_CLK>; + clock-names = "pix", "disp-axi", "disp-apb", + "mix_apb","mix_axi", "xtl_24m", "mix_pix", "lcdif_apb", + "lcdif_axi", "lcdif_pdi", "lcdif_pix", "lcdif_spu", + "noc_hdmi"; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <500000000>, <200000000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_hdmi>; + resets = <&hdmimix_reset IMX_HDMIMIX_LCDIF_RESET>; + power-domains = <&hdmimix_pd>; + status = "disabled"; + + lcdif3_disp: port@0 { + reg = <0>; + + lcdif3_to_hdmi: endpoint { + remote-endpoint = <&hdmi_from_lcdif3>; + }; + }; + }; + + hdmi: hdmi@32fd8000 { + compatible = "fsl,imx8mp-hdmi"; + reg = <0x32fd8000 0x7eff>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_hdmi>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_24M>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PHY_INT_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PREP_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_SKP_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_SFR_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PIXEL_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_CEC_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_APB_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_HPI_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_FDCC_REF_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PIPE_CLK_SEL>; + clock-names = "iahb", "isfr", + "phy_int", "prep_clk", "skp_clk", "sfr_clk", "pix_clk", + "cec_clk", "apb_clk", "hpi_clk", "fdcc_ref", "pipe_clk"; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_24M>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <200000000>, <500000000>, <24000000>; + phys = <&hdmiphy>; + phy-names = "hdmi"; + resets = <&hdmimix_reset IMX_HDMIMIX_HDMI_TX_RESET>; + gpr = <&hdmi_blk>; + power-domains = <&hdmi_phy_pd>; + status = "disabled"; + + port@0 { + hdmi_from_lcdif3: endpoint { + remote-endpoint = <&lcdif3_to_hdmi>; + }; + }; + }; + + hdmiphy: hdmiphy@32fdff00 { + compatible = "fsl,samsung-hdmi-phy"; + reg = <0x32fdff00 0x100>; + #clock-cells = <1>; + clocks = <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PHY_APB_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_XTAL24M_CLK>; + clock-names = "apb", "ref"; + clock-output-names = "hdmi_phy"; + #phy-cells = <0>; + resets = <&hdmimix_reset IMX_HDMIMIX_HDMI_PHY_RESET>; + status = "disabled"; + }; + + mediamix_gasket0: gasket@32ec0060 { + compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; + reg = <0x32ec0060 0x28>; + }; + + mediamix_gasket1: gasket@32ec0090 { + compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; + reg = <0x32ec0090 0x28>; + }; + + ldb_phy: phy@32ec0128 { + compatible = "fsl,imx8mp-lvds-phy"; + #address-cells = <1>; + #size-cells = <0>; + gpr = <&mediamix_blk_ctl>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "apb"; + power-domains = <&mediamix_pd>; + status = "disabled"; + + ldb_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + + mediamix_gpr: media_gpr@32ec0008 { + compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; + reg = <0x32ec0008 0x4>; + }; + cameradev: camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + isi_0: isi@32e00000 { + compatible = "fsl,imx8mp-isi", "fsl,imx8mn-isi"; + reg = <0x32e00000 0x2000>; + interrupts = ; + interface = <2 0 2>; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + assigned-clock-rates = <500000000>, <200000000>; + no-reset-control; + power-domains = <&mediamix_pd>; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + + m2m_device{ + compatible = "imx-isi-m2m"; + status = "disabled"; + }; + }; + + isi_1: isi@32e02000 { + compatible = "fsl,imx8mp-isi", "fsl,imx8mn-isi"; + reg = <0x32e02000 0x2000>; + interrupts = ; + interface = <3 0 2>; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + assigned-clock-rates = <500000000>, <200000000>; + no-reset-control; + power-domains = <&mediamix_pd>; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + isp_0: isp@32e10000 { + compatible = "fsl,imx8mp-isp"; + reg = <0x32e10000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>; + clock-names = "isp_root"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; + power-domains = <&ispdwp_pd>; + status = "disabled"; + }; + + isp_1: isp@32e20000 { + compatible = "fsl,imx8mp-isp"; + reg = <0x32e20000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>; + clock-names = "isp_root"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; + power-domains = <&ispdwp_pd>; + status = "disabled"; + }; + + mipi_csi_0: csi@32e40000 { + compatible = "fsl,imx8mp-mipi-csi", "fsl,imx8mn-mipi-csi"; + reg = <0x32e40000 0x10000>; + interrupts = ; + clock-frequency = <500000000>; + clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "mipi_clk", "disp_axi", "disp_apb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <500000000>; + bus-width = <4>; + csi-gpr = <&mediamix_gasket0>; + csi-gpr2 = <&mediamix_gpr>; + gpr = <&mediamix_blk_ctl>; + no-reset-control; + power-domains = <&mipi_phy1_pd>; + status = "disabled"; + }; + + mipi_csi_1: csi@32e50000 { + compatible = "fsl,imx8mp-mipi-csi", "fsl,imx8mn-mipi-csi"; + reg = <0x32e50000 0x10000>; + interrupts = ; + clock-frequency = <266000000>; + clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "mipi_clk", "disp_axi", "disp_apb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <266000000>; + bus-width = <4>; + csi-gpr = <&mediamix_gasket1>; + csi-gpr2 = <&mediamix_gpr>; + gpr = <&mediamix_blk_ctl>; + no-reset-control; + power-domains = <&mipi_phy2_pd>; + status = "disabled"; + }; + }; + }; + }; + + pcie_phy: pcie-phy@32f00000 { + compatible = "fsl,imx8mp-pcie-phy"; + reg = <0x0 0x32f00000 0x0 0x10000>; + clocks = <&clk IMX8MP_CLK_PCIE_PHY>; + clock-names = "phy"; + assigned-clocks = <&clk IMX8MP_CLK_PCIE_PHY>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + #phy-cells = <0>; + status = "disabled"; + }; + + hsio_mix: hsio-mix@32f10000 { + compatible = "fsl,imx8mp-hsio-mix"; + reg = <0x0 0x32f10000 0x0 0x8>; + }; + + dma_apbh: dma-apbh@33000000 { + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0 0x33000000 0 0x2000>; + interrupts = , + , + , + ; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clk IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; + }; + + gpmi: gpmi-nand@33002000{ + compatible = "fsl,imx7d-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x33002000 0 0x2000>, <0 0x33004000 0 0x4000>; + reg-names = "gpmi-nand", "bch"; + interrupts = ; + interrupt-names = "bch"; + clocks = <&clk IMX8MP_CLK_NAND_ROOT>, + <&clk IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; + clock-names = "gpmi_io", "gpmi_bch_apb"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + pcie: pcie@33800000 { + compatible = "fsl,imx8mp-pcie", "snps,dw-pcie"; + reg = <0x0 0x33800000 0x0 0x400000>, + <0x0 0x1ff00000 0x0 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x0 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x18000000 0x0 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = , + ; /* eDMA */ + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + fsl,max-link-speed = <3>; + power-domains = <&pcie_pd>; + resets = <&src IMX8MQ_RESET_PCIEPHY>, + <&src IMX8MQ_RESET_PCIEPHY_PERST>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "pciephy_perst", "apps", "clkreq", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + fsl,imx8mp-hsio-mix = <&hsio_mix>; + status = "disabled"; + }; + + gpu_3d: gpu3d@38000000 { + compatible = "fsl,imx8-gpu"; + reg = <0x0 0x38000000 0x0 0x8000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, + <&clk IMX8MP_CLK_GPU3D_SHADER_DIV>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + clock-names = "core", "shader", "axi", "ahb"; + assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE_SRC>, + <&clk IMX8MP_CLK_GPU3D_SHADER_SRC>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <1000000000>, <1000000000>, + <800000000>, <400000000>; + power-domains = <&gpu3d_pd>; + status = "disabled"; + }; + + gpu_2d: gpu2d@38008000 { + compatible = "fsl,imx8-gpu"; + reg = <0x0 0x38008000 0x0 0x8000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + clock-names = "core", "axi", "ahb"; + assigned-clocks = <&clk IMX8MP_CLK_GPU2D_SRC>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <1000000000>, <800000000>, <400000000>; + power-domains = <&gpu2d_pd>; + status = "disabled"; + }; + + usb3_phy0: usb-phy@381f0040 { + compatible = "fsl,imx8mp-usb-phy"; + reg = <0 0x381f0040 0 0x40>; + clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; + clock-names = "phy"; + assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb3_0: usb@32f10100 { + compatible = "fsl,imx8mp-dwc3"; + reg = <0 0x32f10100 0 0x8>; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI_DIV>, + <&clk IMX8MP_CLK_USB_ROOT>; + clock-names = "hsio", "bus", "suspend"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; + interrupts = ; + power-domains = <&hsiomix_pd>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_dwc3_0: dwc3@38100000 { + compatible = "snps,dwc3"; + reg = <0 0x38100000 0 0x10000>; + interrupts = ; + phys = <&usb3_phy0>, <&usb3_phy0>; + phy-names = "usb2-phy", "usb3-phy"; + xhci-no-64bit-support; + usb3-resume-missing-cas; + snps,dis-u2-freeclk-exists-quirk; + snps,soft-itp-sync; + status = "disabled"; + }; + + }; + + usb3_phy1: usb-phy@382f0040 { + compatible = "fsl,imx8mp-usb-phy"; + reg = <0 0x382f0040 0 0x40>; + clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; + clock-names = "phy"; + assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb3_1: usb@32f10108 { + compatible = "fsl,imx8mp-dwc3"; + reg = <0 0x32f10108 0 0x8>; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI_DIV>, + <&clk IMX8MP_CLK_USB_ROOT>; + clock-names = "hsio", "bus", "suspend"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; + interrupts = ; + power-domains = <&hsiomix_pd>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_dwc3_1: dwc3@38200000 { + compatible = "snps,dwc3"; + reg = <0 0x38200000 0 0x10000>; + interrupts = ; + phys = <&usb3_phy1>, <&usb3_phy1>; + phy-names = "usb2-phy", "usb3-phy"; + xhci-no-64bit-support; + usb3-resume-missing-cas; + snps,dis-u2-freeclk-exists-quirk; + snps,soft-itp-sync; + status = "disabled"; + }; + }; + + vpu_g1: vpu_g1@38300000 { + compatible = "nxp,imx8mm-hantro","nxp,imx8mp-hantro"; + reg = <0x0 0x38300000 0x0 0x100000>; + reg-names = "regs_hantro"; + interrupts = ; + interrupt-names = "irq_hantro"; + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, <&clk IMX8MP_CLK_VPU_ROOT>; + clock-names = "clk_hantro", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>, <&clk IMX8MP_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL3_OUT>, <&clk IMX8MP_SYS_PLL3_OUT>; + assigned-clock-rates = <600000000>, <600000000>; + power-domains = <&vpu_g1_pd>; + status = "disabled"; + }; + + vpu_g2: vpu_g2@38310000 { + compatible = "nxp,imx8mm-hantro","nxp,imx8mp-hantro"; + reg = <0x0 0x38310000 0x0 0x100000>; + reg-names = "regs_hantro"; + interrupts = ; + interrupt-names = "irq_hantro"; + clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>, <&clk IMX8MP_CLK_VPU_ROOT>; + clock-names = "clk_hantro", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>, <&clk IMX8MP_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>, <&clk IMX8MP_SYS_PLL3_OUT>; + assigned-clock-rates = <400000000>, <600000000>; + power-domains = <&vpu_g2_pd>; + status = "disabled"; + }; + + vpu_vc8000e: vpu_vc8000e@38320000 { + compatible = "nxp,imx8mp-hantro-vc8000e"; + reg = <0x0 0x38320000 0x0 0x10000>; + reg-names = "regs_hantro_vc8000e"; + interrupts = ; + interrupt-names = "irq_hantro_vc8000e"; + clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>, <&clk IMX8MP_CLK_VPU_ROOT>; + clock-names = "clk_hantro_vc8000e", "clk_hantro_vc8000e_bus"; + assigned-clocks = <&clk IMX8MP_CLK_VPU_VC8000E>,<&clk IMX8MP_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>, <&clk IMX8MP_SYS_PLL3_OUT>; + assigned-clock-rates = <400000000>, <600000000>; + power-domains = <&vpu_h1_pd>; + status = "disabled"; + }; + + ml_vipsi: vipsi@38500000 { + compatible = "fsl,imx8-gpu", "fsl,imx8-vipsi"; + reg = <0x0 0x38500000 0x0 0x20000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_NPU_ROOT>, + <&clk IMX8MP_CLK_NPU_ROOT>, + <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>; + clock-names = "core", "shader", "axi", "ahb"; + assigned-clocks = <&clk IMX8MP_CLK_ML_SRC>, + <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <1000000000>, <800000000>, <400000000>; + power-domains = <&mlmix_pd>; + status = "disabled"; + }; + + dsp: dsp@3b6e8000 { + compatible = "fsl,imx8mp-dsp-v1"; + memory-region = <&dsp_reserved>; + reg = <0x0 0x3B6E8000 0x0 0x88000>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_DSP_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_MU2_ROOT>; + clock-names = "ocram", "core", "debug", "mu2"; + fsl,dsp-firmware = "imx/dsp/hifi4.bin"; + power-domains = <&audiomix_pd>; + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + mboxes = <&mu2 2 0>, + <&mu2 2 1>, + <&mu2 3 0>, + <&mu2 3 1>; + status = "disabled"; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&lcdif1_disp>, + <&lcdif2_disp>, + <&lcdif3_disp>; + }; + + imx_ion: imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; + }; + + mix_gpu_ml: mix_gpu_ml { + compatible = "fsl,imx8mp-gpu", "fsl,imx8-gpu-ss"; + cores = <&gpu_3d>, <&ml_vipsi>, <&gpu_2d>; + reg = <0x0 0x40000000 0x0 0xC0000000>, <0x0 0x0 0x0 0x10000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; + status = "disabled"; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx8mq-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + status = "disabled"; + }; + + i2c_rpbus_3: i2c-rpbus-3 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + etm0: etm@28440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x28440000 0x0 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A53_0>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + etm0_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port0>; + }; + }; + }; + }; + + etm1: etm@28540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x28540000 0x0 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A53_1>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + etm1_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port1>; + }; + }; + }; + }; + + etm2: etm@28640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x28640000 0x0 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A53_2>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + etm2_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port2>; + }; + }; + }; + }; + + etm3: etm@28740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x28740000 0x0 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A53_3>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + etm3_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port3>; + }; + }; + }; + }; + + funnel0: funnel { + /* + * non-configurable funnel don't show up on the AMBA + * bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-funnel"; + status = "disabled"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ca_funnel_in_port0: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + ca_funnel_in_port1: endpoint { + remote-endpoint = <&etm1_out_port>; + }; + }; + + port@2 { + reg = <2>; + ca_funnel_in_port2: endpoint { + remote-endpoint = <&etm2_out_port>; + }; + }; + + port@3 { + reg = <3>; + ca_funnel_in_port3: endpoint { + remote-endpoint = <&etm3_out_port>; + }; + }; + }; + + out-ports { + port { + ca_funnel_out_port0: endpoint { + remote-endpoint = <&hugo_funnel_in_port0>; + }; + }; + }; + + }; + + funnel1: funnel@28c03000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x28c03000 0x0 0x1000>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hugo_funnel_in_port0: endpoint { + remote-endpoint = <&ca_funnel_out_port0>; + }; + }; + + port@1 { + reg = <1>; + hugo_funnel_in_port1: endpoint { + /* M7 input */ + }; + }; + + port@2 { + reg = <2>; + hugo_funnel_in_port2: endpoint { + /* DSP input */ + }; + }; + /* the other input ports are not connect to anything */ + }; + + out-ports { + port { + hugo_funnel_out_port0: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + }; + }; + + etf@28c04000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x28c04000 0x0 0x1000>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + in-ports { + port { + etf_in_port: endpoint { + remote-endpoint = <&hugo_funnel_out_port0>; + }; + }; + }; + + out-ports { + port { + etf_out_port: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + }; + }; + + etr@28c06000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x28c06000 0x0 0x1000>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + in-ports { + port { + etr_in_port: endpoint { + remote-endpoint = <&etf_out_port>; + }; + }; + }; + }; + +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-ddr3l-val.dts b/arch/arm64/boot/dts/freescale/imx8mq-ddr3l-val.dts new file mode 100644 index 00000000000000..d2845266b21f78 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-ddr3l-val.dts @@ -0,0 +1,345 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017-2019 NXP + */ + +/dts-v1/; + +#include "imx8mq.dtsi" + +/ { + model = "NXP i.MX8MQ DDR3L ARM2"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + + chosen { + stdout-path = &uart1; + }; + + reg_usdhc2_vmmc: regulator-vsd-3v3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2>; + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + busfreq { + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56 + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56 + MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 + MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x82 + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x82 + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x82 + MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x82 + MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x82 + MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x82 + + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + >; + }; + + pinctrl_reg_usdhc2: regusdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS2_PLL_50M>; + assigned-clock-rates = <0>, <0>, <50000000>, <100000000>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&uart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val-gpmi-nand.dts b/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val-gpmi-nand.dts new file mode 100644 index 00000000000000..826ba6eb67b559 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val-gpmi-nand.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017-2019 NXP + */ + +#include "imx8mq-ddr4-val.dts" + +&iomuxc { + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 + MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 + MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 + MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 + MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 + MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 + MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 + MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 + MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 + MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 + MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 + MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 + MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 + MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 + MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 + >; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val.dts new file mode 100644 index 00000000000000..7d23d10796fb55 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val.dts @@ -0,0 +1,351 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017-2019 NXP + */ + +/dts-v1/; + +#include "imx8mq.dtsi" + +/ { + model = "NXP i.MX8MQ DDR4 ARM2"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + + chosen { + stdout-path = &uart1; + }; + + + + reg_usdhc2_vmmc: regulator-vsd-3v3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2>; + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + busfreq { + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + >; + }; + + pinctrl_reg_usdhc2: regusdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&uart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb_dwc3_0 { + status = "okay"; + dr_mode = "otg"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-ak4497.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-ak4497.dts new file mode 100644 index 00000000000000..61b4bb0b8af88c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-ak4497.dts @@ -0,0 +1,93 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mq-evk.dts" + +/ { + sound-ak4458 { + status = "disabled"; + }; + + sound-ak4497 { + status = "okay"; + }; +}; + +&iomuxc { + + pinctrl_sai1_pcm: sai1grp_pcm { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_dsd: sai1grp_dsd { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_dsd512: sai1grp_dsd512 { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; +}; + +&sai1 { + pinctrl-names = "default", "dsd", "dsd512"; + pinctrl-0 = <&pinctrl_sai1_pcm>; + pinctrl-1 = <&pinctrl_sai1_dsd>; + pinctrl-2 = <&pinctrl_sai1_dsd512>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL2_OUT>; + assigned-clock-rates = <45158400>; + fsl,sai-multi-lane; + fsl,dataline,dsd = <0 0xff 0x11>; + dmas = <&sdma2 8 25 0>, <&sdma2 9 25 0>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-audio-tdm.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-audio-tdm.dts new file mode 100644 index 00000000000000..3eba0b6bb06ebb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-audio-tdm.dts @@ -0,0 +1,25 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mq-evk.dts" + +/ { + sound-ak4458 { + fsl,tdm; + }; + + sound-ak5558 { + fsl,tdm; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-adv7535.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-adv7535.dts new file mode 100644 index 00000000000000..d98d6dc34f5519 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-adv7535.dts @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP. + */ + +#include "imx8mq-evk.dts" + +/ { + sound-hdmi { + status = "disabled"; + }; +}; + +&irqsteer { + status = "okay"; +}; + +/delete-node/ &hdmi; + +&lcdif { + status = "disabled"; +}; + +&dcss { + status = "okay"; + + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_CLK_DC_PIXEL>, + <&clk IMX8MQ_CLK_DISP_DTRC>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc"; + assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL>, + <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_CLK_DISP_AXI>, + <&clk IMX8MQ_CLK_DISP_RTRM>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_CLK_27M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>; + assigned-clock-rates = <600000000>, <0>, <0>, + <800000000>, + <400000000>; + + port@0 { + dcss_out: endpoint { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&adv_bridge { + status = "okay"; + + port@0 { + adv7535_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; +}; + +&mipi_dsi { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mipi_dsi_in: endpoint { + remote-endpoint = <&dcss_out>; + }; + }; + + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&adv7535_in>; + }; + }; + }; +}; + +&dphy { + status = "okay"; +}; + +&iomuxc { + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67191.dts new file mode 100644 index 00000000000000..bf678498c86350 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67191.dts @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP. + */ + +#include "imx8mq-evk.dts" + +/delete-node/&hdmi; + +&irqsteer { + status = "okay"; +}; + +&lcdif { + status = "disabled"; +}; + +&dcss { + status = "okay"; + + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_CLK_DC_PIXEL>, + <&clk IMX8MQ_CLK_DISP_DTRC>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc"; + assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL>, + <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_CLK_DISP_AXI>, + <&clk IMX8MQ_CLK_DISP_RTRM>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_CLK_27M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>; + assigned-clock-rates = <600000000>, <0>, <0>, + <800000000>, + <400000000>; + + port@0 { + dcss_out: endpoint { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&mipi_dsi { + status = "okay"; + fsl,clock-drop-level = <2>; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + pinctrl-names = "default"; + reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; + width-mm = <68>; + height-mm = <121>; + port { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mipi_dsi_in: endpoint { + remote-endpoint = <&dcss_out>; + }; + }; + + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&dphy { + status = "okay"; +}; + +&iomuxc { + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 + >; + }; +}; + +&synaptics_dsx_ts { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-dp.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-dp.dts new file mode 100644 index 00000000000000..912db538048990 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-dp.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP. + */ + +#include "imx8mq-evk.dts" + +&irqsteer { + status = "okay"; +}; + +&dcss { + status = "okay"; + disp-dev = "hdmi_disp"; + + port@0 { + dcss_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; +}; + +&hdmi { + compatible = "cdn,imx8mq-dp"; + lane-mapping = <0xc6>; + + status = "okay"; + + port@1 { + hdmi_in: endpoint { + remote-endpoint = <&dcss_out>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-dual-display.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-dual-display.dts new file mode 100644 index 00000000000000..49aadba32d9371 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-dual-display.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP. + */ + +#include "imx8mq-evk-lcdif-adv7535.dts" + +/ { + sound-hdmi { + status = "okay"; + }; +}; + +&irqsteer { + status = "okay"; +}; + +&dcss { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-inmate.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-inmate.dts new file mode 100644 index 00000000000000..2c61c7fd768ca7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-inmate.dts @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include + +/ { + model = "Freescale i.MX8MQ EVK"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial1 = &uart2; + mmc2 = &usdhc1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + osc_25m: clock-osc-25m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "osc_25m"; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + clk_dummy: clock@7 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + /* The clocks are configured by 1st OS */ + clk_400m: clock@8 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "400m"; + }; + clk_266m: clock@9 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <266000000>; + clock-output-names = "266m"; + }; + clk_80m: clock@10 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <80000000>; + clock-output-names = "80m"; + }; + + pci@bfb00000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 54 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xbfb00000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x3e000000>; + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; + + aips3: bus@30800000 { + compatible = "fsl,imx8mq-aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x30800000 0x30800000 0x400000>, + <0x08000000 0x08000000 0x10000000>; + + uart2: serial@30890000 { + compatible = "fsl,imx8mq-uart", + "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = ; + status = "disabled"; + }; + + usdhc1: mmc@30b40000 { + compatible = "fsl,imx8mq-usdhc", + "fsl,imx7d-usdhc"; + reg = <0x30b40000 0x10000>; + interrupts = ; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step = <2>; + status = "disabled"; + }; + }; + }; +}; + +&uart2 { + clocks = <&osc_25m>, + <&osc_25m>; + clock-names = "ipg", "per"; + /delete-property/ dmas; + /delete-property/ dmas-names; + status = "okay"; +}; + +&usdhc1 { + clocks = <&clk_dummy>, + <&clk_266m>, + <&clk_400m>; + /delete-property/assigned-clocks; + /delete-property/assigned-clock-rates; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-adv7535.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-adv7535.dts new file mode 100644 index 00000000000000..80488b745f684d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-adv7535.dts @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP. + */ + +#include "imx8mq-evk.dts" + +/ { + sound-hdmi { + status = "disabled"; + }; +}; + +&irqsteer { + status = "okay"; +}; + +&hdmi { + status = "disabled"; +}; + +&dcss { + status = "disabled"; +}; + +&lcdif { + status = "okay"; + max-memory-bandwidth = <314676293>; /* 1280x1024-32@60 */ + + assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>, + <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_CLK_27M>; + assigned-clock-rate = <126000000>, <0>, <0>, <1134000000>; + + port@0 { + lcdif_out: endpoint { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&adv_bridge { + status = "okay"; + + port@0 { + adv7535_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; +}; + +&mipi_dsi { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mipi_dsi_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; + + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&adv7535_in>; + }; + }; + }; +}; + +&dphy { + status = "okay"; +}; + +&iomuxc { + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-rm67191.dts new file mode 100644 index 00000000000000..7c1d7c60b539d9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-rm67191.dts @@ -0,0 +1,92 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mq-evk.dts" + +&lcdif { + status = "okay"; + max-memory-bandwidth = <497829888>; /* 1920x1080-32@60.02 */ + + assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>, + <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_CLK_27M>; + assigned-clock-rate = <126000000>, <0>, <0>, <1134000000>; + + port@0 { + lcdif_mipi_dsi: endpoint { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&mipi_dsi { + status = "okay"; + fsl,clock-drop-level = <2>; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + pinctrl-names = "default"; + reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; + width-mm = <68>; + height-mm = <121>; + port { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mipi_dsi_in: endpoint { + remote-endpoint = <&lcdif_mipi_dsi>; + }; + }; + + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&dphy { + status = "okay"; +}; + +&iomuxc { + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 + >; + }; +}; + +&synaptics_dsx_ts { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie1-m2.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie1-m2.dts new file mode 100644 index 00000000000000..652b3264402145 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie1-m2.dts @@ -0,0 +1,25 @@ +/* + * Copyright 2017-2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mq-evk.dts" + +/ { + modem_reset: modem-reset { + reset-gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&pcie0{ + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-pdm.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-pdm.dts new file mode 100644 index 00000000000000..0f5d7b73df5e73 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-pdm.dts @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mq-evk.dts" + +/ { + sound-pdm { + compatible = "fsl,imx-pdm-mic"; + model = "imx-pdm-audio"; + audio-cpu = <&sai3>; + decimation = <64>; + status = "okay"; + }; +}; + +&iomuxc { + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; + }; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-root.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-root.dts new file mode 100644 index 00000000000000..1b6a41ba7a7b0f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-root.dts @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mq-evk.dts" + +/ { + interrupt-parent = <&gic>; +}; + +&CPU_SLEEP { + /* We are not using GPC for now, need set 0 to avoid hang */ + arm,psci-suspend-param = <0x0>; +}; + +&clk { + init-on-array = ; +}; + +&iomuxc { + /* + * Used for the 2nd Linux. + * TODO: M4 may use these pins. + */ + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 + MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 + >; + }; +}; + +&{/busfreq} { + /* Disable busfreq, to avoid 1st Linux busfreq crash other inmates */ + status = "disabled"; +}; + +&resmem { + jh_reserved: jh@fdc00000 { + no-map; + reg = <0 0xfdc00000 0x0 0x400000>; + }; + + inmate_reserved: inmate@c0000000 { + no-map; + reg = <0 0xc0000000 0x0 0x3dc00000>; + }; + + loader_reserved: loader@bff00000 { + no-map; + reg = <0 0xbff00000 0x0 0x00100000>; + }; + + ivshmem_reserved: ivshmem@bfe00000 { + no-map; + reg = <0 0xbfe00000 0x0 0x00100000>; + }; + + ivshmem2_reserved: ivshmem2@bfd00000 { + no-map; + reg = <0 0xbfd00000 0x0 0x00100000>; + }; + + pci_reserved: pci@bfc00000 { + no-map; + reg = <0 0xbfb00000 0x0 0x00200000>; + }; +}; + +&uart1 { + /* uart2 is used by the 2nd OS, so configure pin and clk */ + pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart2>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1>, + <&clk IMX8MQ_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, + <&clk IMX8MQ_CLK_25M>; +}; + +&usdhc1 { + status = "disabled"; +}; + +&usdhc2 { + /* sdhc1 is used by 2nd linux, configure the pin */ + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2_200mhz>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-rpmsg.dts new file mode 100644 index 00000000000000..4fad48aa514a35 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-rpmsg.dts @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8mq-evk.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m4_reserved: m4@0x80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + rpmsg_reserved: rpmsg@0xb8000000 { + no-map; + reg = <0 0xb8200000 0 0x200000>; + }; + + vdev0vring0: vdev0vring0@b8000000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@b8008000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8008000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@b8400000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8400000 0 0x100000>; + no-map; + }; + }; + + imx8mq-cm4 { + compatible = "fsl,imx8mq-cm4"; + rsc-da = <0xb8000000>; + clocks = <&clk IMX8MQ_CLK_M4_DIV>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>; + syscon = <&src>; + }; +}; + +/* + * Regarding to the HW conflications, the following module should be disabled + * when M4 is running on evk board. + * gpt1, i2c2, pwm4, tmu, uart2 + */ + +&i2c2 { + status = "disabled"; +}; + +&pwm4 { + status = "disabled"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + * --0xb8000000~0xb800ffff: pingpong + */ + vdev-nums = <1>; + reg = <0x0 0xb8000000 0x0 0x10000>; + memory-region = <&vdevbuffer>; + status = "disabled"; +}; + +&tmu { + status = "disabled"; +}; + +&uart2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-usd-wifi.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-usd-wifi.dts new file mode 100644 index 00000000000000..d10faa4b23eb45 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-usd-wifi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mq-evk.dts" + +&usdhc2 { + /delete-property/ cd-gpios; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-usdhc2-m2.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-usdhc2-m2.dts new file mode 100644 index 00000000000000..33d7dc1a047f2e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-usdhc2-m2.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mq-evk.dts" + +/ { + modem_reset: modem-reset { + reset-gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; + }; + + usdhc2_pwrseq: usdhc2_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl_usdhc2 { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49 + MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x46 + >; +}; + +&pinctrl_usdhc2_100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49 + >; +}; + +&pinctrl_usdhc2_200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49 + >; +}; + +&pcie0{ + status = "disabled"; +}; + +&pcie1{ + status = "disabled"; +}; + +&usdhc2 { + pinctrl-assert-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + /delete-property/ cd-gpios; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; + mmc-pwrseq = <&usdhc2_pwrseq>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts old mode 100644 new mode 100755 index 05958124f173c6..e211234e80ff2c --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -6,6 +6,7 @@ /dts-v1/; +#include #include "imx8mq.dtsi" / { @@ -21,12 +22,66 @@ reg = <0x00000000 0x40000000 0 0xc0000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rpmsg_reserved: rpmsg@0xb8000000 { + no-map; + reg = <0 0xb8000000 0 0x400000>; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + resmem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x40000000 0 0x40000000>; + linux,cma-default; + }; + }; + pcie0_refclk: pcie0-refclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; + pcie1_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + ptn36043 { + compatible = "nxp,ptn36043"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ss_sel>; + switch-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + orientation-switch; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; + reg_usdhc2_vmmc: regulator-vsd-3v3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_usdhc2>; @@ -35,6 +90,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; enable-active-high; }; @@ -71,6 +127,8 @@ cpudai: simple-audio-card,cpu { sound-dai = <&sai2>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; }; link_codec: simple-audio-card,codec { @@ -78,6 +136,60 @@ clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; }; }; + + sound-hdmi { + compatible = "fsl,imx8mq-evk-cdnhdmi", + "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-hdmi"; + audio-cpu = <&sai4>; + protocol = <1>; + hdmi-out; + constraint-rate = <44100>, + <88200>, + <176400>, + <32000>, + <48000>, + <96000>, + <192000>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; + }; + + sound-hdmi-arc { + compatible = "fsl,imx-audio-spdif"; + model = "imx-hdmi-arc"; + spdif-controller = <&spdif2>; + spdif-in; + }; + + sound-ak4458 { + compatible = "fsl,imx-audio-ak4458-mq"; + model = "ak4458-audio"; + audio-cpu = <&sai1>; + audio-codec = <&ak4458_1>, <&ak4458_2>; + ak4458,pdn-gpio = <&gpio3 18 GPIO_ACTIVE_HIGH>; + }; + + sound-ak5558 { + compatible = "fsl,imx-audio-ak5558-mq"; + model = "ak5558-audio"; + audio-cpu = <&sai5>; + audio-codec = <&ak5558>; + }; + + sound-ak4497 { + compatible = "fsl,imx-audio-ak4497-mq"; + model = "ak4497-audio"; + audio-cpu = <&sai1>; + audio-codec = <&ak4497>; + status = "disabled"; + }; }; &A53_0 { @@ -96,6 +208,30 @@ cpu-supply = <&buck2_reg>; }; +&csi1_bridge { + fsl,mipi-mode; + fsl,two-8bit-sensor-mode; + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&csi1_mipi_ep>; + }; + }; +}; + +&csi2_bridge { + fsl,mipi-mode; + fsl,two-8bit-sensor-mode; + status = "okay"; + + port { + csi2_ep: endpoint { + remote-endpoint = <&csi2_mipi_ep>; + }; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; @@ -111,6 +247,41 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + at803x,eee-disabled; + }; + }; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port { + mipi1_sensor_ep: endpoint@0 { + remote-endpoint = <&ov5640_mipi1_ep>; + data-lanes = <1 2>; + bus-type = <4>; + }; + + csi1_mipi_ep: endpoint@1 { + remote-endpoint = <&csi1_ep>; + }; + }; +}; + +&mipi_csi_2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port { + mipi2_sensor_ep: endpoint@0 { + remote-endpoint = <&ov5640_mipi2_ep>; + data-lanes = <1 2>; + bus-type = <4>; + }; + + csi2_mipi_ep: endpoint@1 { + remote-endpoint = <&csi2_ep>; }; }; }; @@ -118,12 +289,83 @@ &sai2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>; - assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>; - assigned-clock-rates = <0>, <24576000>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default", "pcm_b2m", "dsd"; + pinctrl-0 = <&pinctrl_sai1_pcm>; + pinctrl-1 = <&pinctrl_sai1_pcm_b2m>; + pinctrl-2 = <&pinctrl_sai1_dsd>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI1_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, + <&clk IMX8MQ_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-multi-lane; + fsl,dataline,dsd = <0 0xff 0xff 2 0xff 0x11>; + dmas = <&sdma2 8 25 0>, <&sdma2 9 25 0>; status = "okay"; }; +&sai4 { + assigned-clocks = <&clk IMX8MQ_CLK_SAI4>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI4_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, + <&clk IMX8MQ_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + status = "okay"; +}; + +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI5_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, + <&clk IMX8MQ_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-asynchronous; + status = "okay"; +}; + +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, <&clk IMX8MQ_CLK_25M>, + <&clk IMX8MQ_CLK_SPDIF1>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_IPG_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_AUDIO_PLL1_OUT>, <&clk IMX8MQ_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4", + "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; + status = "okay"; +}; + +&spdif2 { + assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + + &gpio5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wifi_reset>; @@ -141,8 +383,31 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; + ov5640_mipi2: ov5640_mipi2@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi2_pwn>, <&pinctrl_csi_rst>; + clocks = <&clk IMX8MQ_CLK_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; + assigned-clock-rates = <20000000>; + csi_id = <1>; + pwn-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + mclk = <20000000>; + mclk_source = <0>; + port { + ov5640_mipi2_ep: endpoint { + remote-endpoint = <&mipi2_sensor_ep>; + }; + }; + }; + pmic@8 { compatible = "fsl,pfuze100"; + fsl,pfuze-support-disable-sw; reg = <0x8>; regulators { @@ -224,6 +489,127 @@ }; }; }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <3 8>; + + port { + typec_dr_sw: endpoint { + remote-endpoint = <&usb3_drd_sw>; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + synaptics_dsx_ts: synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_dsi_ts_int>; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "disabled"; + }; + + ak4458_1: ak4458@10 { + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + }; + + ak4458_2: ak4458@12 { + compatible = "asahi-kasei,ak4458"; + reg = <0x12>; + }; + + ak5558: ak5558@13 { + compatible = "asahi-kasei,ak5558"; + reg = <0x13>; + ak5558,pdn-gpio = <&gpio3 17 GPIO_ACTIVE_HIGH>; + }; + + ak4497: ak4497@11 { + compatible = "asahi-kasei,ak4497"; + reg = <0x11>; + ak4497,pdn-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; + }; + + adv_bridge: adv7535@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + pinctrl-0 = <&pinctrl_i2c1_dsi_ts_int>; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + status = "disabled"; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1_pwn>; + clocks = <&clk IMX8MQ_CLK_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; + assigned-clock-rates = <20000000>; + csi_id = <0>; + pwn-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + mclk = <20000000>; + mclk_source = <0>; + port { + ov5640_mipi1_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; + }; + }; + }; }; &pcie0 { @@ -235,6 +621,21 @@ <&clk IMX8MQ_CLK_PCIE1_PHY>, <&pcie0_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + hard-wired = <1>; + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + disable-gpio = <&gpio5 10 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcie1_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + reserved-region = <&rpmsg_reserved>; status = "okay"; }; @@ -242,39 +643,79 @@ power-supply = <&sw1a_reg>; }; +&pgc_vpu { + power-supply = <&sw1c_reg>; +}; + &snvs_pwrkey { status = "okay"; }; +&qspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash0: n25q256a@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-nor,ddr-quad-read-dummy = <6>; + }; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; status = "okay"; }; -&usb3_phy1 { +&uart3 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MQ_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; status = "okay"; }; -&usb_dwc3_1 { - dr_mode = "host"; +&usb3_phy0 { status = "okay"; }; -&qspi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; status = "okay"; - n25q256a: flash@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - spi-max-frequency = <29000000>; + port { + usb3_drd_sw: endpoint { + remote-endpoint = <&typec_dr_sw>; + }; }; }; +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -306,6 +747,19 @@ }; &iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 + MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 + MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x16 + >; + }; + pinctrl_buck2: vddarmgrp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 @@ -313,6 +767,24 @@ }; + pinctrl_csi1_pwn: csi1_pwn_grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 + >; + }; + pinctrl_csi2_pwn: csi2_pwn_grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 + >; + }; + + pinctrl_csi_rst: csi_rst_grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x59 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 @@ -340,6 +812,26 @@ >; }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f + >; + }; + + pinctrl_i2c1_dsi_ts_int: dsi_ts_int { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x19 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000067 + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000067 + >; + }; + pinctrl_pcie0: pcie0grp { fsl,pins = < MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76 @@ -347,6 +839,14 @@ >; }; + pinctrl_pcie1: pcie1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76 /* open drain, pull up */ + MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16 + MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16 + >; + }; + pinctrl_qspi: qspigrp { fsl,pins = < MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 @@ -371,7 +871,88 @@ MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 - MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 + >; + }; + + pinctrl_sai1_pcm: sai1grp_pcm { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_pcm_b2m: sai1grp_pcm_b2m { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_dsd: sai1grp_dsd { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6 + >; + }; + + pinctrl_spdif1: spdif1grp { + fsl,pins = < + MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + + pinctrl_ss_sel: usb3ssgrp{ + fsl,pins = < + MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16 + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x17059 >; }; @@ -382,6 +963,16 @@ >; }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 + MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 + MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49 + MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49 + MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 @@ -481,3 +1072,36 @@ >; }; }; + +&vpu { + status = "okay"; +}; + +&gpu3d { + status = "okay"; +}; + +&irqsteer { + status = "okay"; +}; + +&dcss { + status = "okay"; + + port@0 { + dcss_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; +}; + +&hdmi { + compatible = "cdn,imx8mq-hdmi"; + lane-mapping = <0xe4>; + status = "okay"; + port@1 { + hdmi_in: endpoint { + remote-endpoint = <&dcss_out>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi old mode 100644 new mode 100755 index 55a3d1c4bdf04c..4290f68ef2f8fd --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -20,6 +20,9 @@ #size-cells = <2>; aliases { + csi0 = &mipi_csi_1; + csi1 = &mipi_csi_2; + ethernet0 = &fec1; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -29,6 +32,8 @@ i2c1 = &i2c2; i2c2 = &i2c3; i2c3 = &i2c4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; @@ -103,6 +108,7 @@ #cooling-cells = <2>; nvmem-cells = <&cpu_speed_grade>; nvmem-cell-names = "speed_grade"; + cpu-idle-states = <&CPU_SLEEP>; }; A53_1: cpu@1 { @@ -115,6 +121,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; }; A53_2: cpu@2 { @@ -127,6 +134,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; }; A53_3: cpu@3 { @@ -139,11 +147,27 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; }; A53_L2: l2-cache0 { compatible = "cache"; }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + }; a53_opp_table: opp-table { @@ -228,34 +252,6 @@ }; }; }; - - gpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tmu 1>; - - trips { - gpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - vpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tmu 2>; - - trips { - vpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; }; timer { @@ -268,6 +264,25 @@ arm,no-tick-in-suspend; }; + busfreq { /* BUSFREQ */ + compatible = "fsl,imx_busfreq"; + clocks = <&clk IMX8MQ_DRAM_PLL_OUT>, <&clk IMX8MQ_CLK_DRAM_ALT>, + <&clk IMX8MQ_CLK_DRAM_APB>, <&clk IMX8MQ_CLK_DRAM_APB>, + <&clk IMX8MQ_CLK_DRAM_CORE>, <&clk IMX8MQ_CLK_DRAM_ALT_ROOT>, + <&clk IMX8MQ_SYS1_PLL_40M>, <&clk IMX8MQ_SYS1_PLL_400M>, + <&clk IMX8MQ_SYS1_PLL_100M>, <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_CLK_NOC>, <&clk IMX8MQ_CLK_MAIN_AXI>, + <&clk IMX8MQ_CLK_AHB>, <&clk IMX8MQ_CLK_25M>, + <&clk IMX8MQ_SYS2_PLL_333M>, <&clk IMX8MQ_SYS1_PLL_133M>; + clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", + "dram_core", "dram_alt_root", "sys1_pll_40m", "sys1_pll_400m", + "sys1_pll_100m", "sys1_pll_800m", "noc_div", "main_axi_src", + "ahb_div", "osc_25m", "sys2_pll_333m", "sys1_pll_133m"; + interrupts = , , + , ; + interrupt-name = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3"; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; @@ -275,12 +290,82 @@ ranges = <0x0 0x0 0x0 0x3e000000>; dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; + caam_sm: caam-sm@100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + bus@30000000 { /* AIPS1 */ compatible = "fsl,imx8mq-aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x30000000 0x30000000 0x400000>; + sai1: sai@30010000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x30010000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI1_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 8 1 0>, <&sdma2 9 1 0>; + dma-names = "rx", "tx"; + fsl,dataline = <0 0xff 0xff>; + status = "disabled"; + }; + + sai6: sai@30030000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x30030000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_SAI6_IPG>, + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI6_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + status = "disabled"; + }; + + sai5: sai@30040000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x30040000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI5_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0 0xf 0xf>; + status = "disabled"; + }; + + sai4: sai@30050000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x30050000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI4_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>; + dma-names = "rx", "tx"; + fsl,dataline = <0 0x0 0xf>; + status = "disabled"; + }; + gpio1: gpio@30200000 { compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; reg = <0x30200000 0x10000>; @@ -396,7 +481,7 @@ 0x00030005 0x00000053 0x00030006 0x0000005f 0x00030007 0x00000071>; - #thermal-sensor-cells = <1>; + #thermal-sensor-cells = <0>; }; wdog1: watchdog@30280000 { @@ -434,6 +519,21 @@ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; }; + lcdif: lcdif@30320000 { + compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif"; + reg = <0x30320000 0x10000>; + clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>; + clock-names = "pix"; + assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>, + <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_CLK_27M>; + interrupts = ; + status = "disabled"; + }; + iomuxc: iomuxc@30330000 { compatible = "fsl,imx8mq-iomuxc"; reg = <0x30330000 0x10000>; @@ -451,7 +551,7 @@ }; }; - ocotp: ocotp-ctrl@30350000 { + ocotp: efuse@30350000 { compatible = "fsl,imx8mq-ocotp", "syscon"; reg = <0x30350000 0x10000>; clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; @@ -461,6 +561,10 @@ cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; + + fec_mac_address: mac-address@640 { + reg = <0x90 6>; + }; }; anatop: syscon@30360000 { @@ -469,6 +573,20 @@ interrupts = ; }; + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + }; + snvs: snvs@30370000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x30370000 0x10000>; @@ -487,6 +605,8 @@ compatible = "fsl,sec-v4.0-pwrkey"; regmap = <&snvs>; interrupts = ; + clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; + clock-names = "snvs"; linux,keycode = ; wakeup-source; status = "disabled"; @@ -505,6 +625,16 @@ clock-names = "ckil", "osc_25m", "osc_27m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; + assigned-clocks = <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, + <&clk IMX8MQ_CLK_AUDIO_AHB>, + <&clk IMX8MQ_AUDIO_PLL1>, + <&clk IMX8MQ_AUDIO_PLL2>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, + <&clk IMX8MQ_SYS2_PLL_500M>; + assigned-clock-rates = <0>, + <0>, + <786432000>, + <722534400>; }; src: reset-controller@30390000 { @@ -518,6 +648,7 @@ reg = <0x303a0000 0x10000>; interrupt-parent = <&gic>; interrupt-controller; + broken-wake-request-signals; #interrupt-cells = <3>; pgc { @@ -668,10 +799,34 @@ ranges = <0x30800000 0x30800000 0x400000>, <0x08000000 0x08000000 0x10000000>; + spdif1: spdif@30810000 { + compatible = "fsl,imx8mm-spdif", "fsl,imx35-spdif"; + reg = <0x30810000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ + <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ + <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8MQ_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + ecspi1: spi@30820000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; + compatible = "fsl,imx8mq-ecspi", "fsl,imx6ul-ecspi"; reg = <0x30820000 0x10000>; interrupts = ; clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, @@ -683,7 +838,7 @@ ecspi2: spi@30830000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; + compatible = "fsl,imx8mq-ecspi", "fsl,imx6ul-ecspi"; reg = <0x30830000 0x10000>; interrupts = ; clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>, @@ -695,7 +850,7 @@ ecspi3: spi@30840000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; + compatible = "fsl,imx8mq-ecspi", "fsl,imx6ul-ecspi"; reg = <0x30840000 0x10000>; interrupts = ; clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>, @@ -737,20 +892,60 @@ status = "disabled"; }; + spdif2: spdif@308a0000 { + compatible = "fsl,imx8mm-spdif", "fsl,imx35-spdif"; + reg = <0x308a0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ + <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ + <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8MQ_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + sai2: sai@308b0000 { #sound-dai-cells = <0>; compatible = "fsl,imx8mq-sai"; reg = <0x308b0000 0x10000>; interrupts = ; clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_SAI2_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>; dma-names = "rx", "tx"; status = "disabled"; }; + sai3: sai@308c0000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x308c0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI3_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + crypto: crypto@30900000 { compatible = "fsl,sec-v4.0"; #address-cells = <1>; @@ -794,6 +989,47 @@ status = "disabled"; }; + mipi_dsi: mipi_dsi@30a00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mq-nwl-dsi"; + reg = <0x30a00000 0x300>; + clocks = <&clk IMX8MQ_CLK_DSI_CORE>, + <&clk IMX8MQ_CLK_DSI_AHB>, + <&clk IMX8MQ_CLK_DSI_IPG_DIV>, + <&clk IMX8MQ_CLK_DSI_PHY_REF>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_CLK_LCDIF_PIXEL>; + clock-names = "core", + "rx_esc", + "tx_esc", + "phy_ref", + "video_pll", + "lcdif"; + assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>, + <&clk IMX8MQ_CLK_DSI_CORE>, + <&clk IMX8MQ_CLK_DSI_AHB>, + <&clk IMX8MQ_CLK_DSI_IPG_DIV>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_SYS1_PLL_266M>, + <&clk IMX8MQ_SYS1_PLL_80M>; + assigned-clock-rates = <27000000>, + <266000000>, + <80000000>, + <20000000>; + interrupts = ; + power-domains = <&pgc_mipi>; + resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>, + <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>, + <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>, + <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>; + reset-names = "byte", "dpi", "esc", "pclk"; + mux-controls = <&mux 0>; + phys = <&dphy>; + phy-names = "dphy"; + status = "disabled"; + }; + i2c1: i2c@30a20000 { compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; reg = <0x30a20000 0x10000>; @@ -845,6 +1081,44 @@ status = "disabled"; }; + mipi_csi_1: mipi_csi1@30a70000 { + compatible = "fsl,mxc-mipi-csi2_yav"; + reg = <0x30a70000 0x1000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, + <&clk IMX8MQ_CLK_CSI1_ESC>, + <&clk IMX8MQ_CLK_CSI1_PHY_REF>; + clock-names = "clk_core", "clk_esc", "clk_pxl"; + assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, + <&clk IMX8MQ_CLK_CSI1_PHY_REF>, + <&clk IMX8MQ_CLK_CSI1_ESC>; + assigned-clock-rates = <133000000>, <100000000>, <66000000>; + power-domains = <&pgc_mipi_csi1>; + csis-phy-reset = <&src 0x4c 7>; + phy-gpr = <&iomuxc_gpr 0x88>; + status = "disabled"; + }; + + csi1_bridge: csi1_bridge@30a90000 { + compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi"; + reg = <0x30a90000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_CSI1_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + + mu: mu@30aa0000 { + compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_MU_ROOT>; + clock-names = "mu"; + #mbox-cells = <2>; + }; + usdhc1: mmc@30b40000 { compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; @@ -877,6 +1151,35 @@ status = "disabled"; }; + mipi_csi_2: mipi_csi2@30b60000 { + compatible = "fsl,mxc-mipi-csi2_yav"; + reg = <0x30b60000 0x1000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, + <&clk IMX8MQ_CLK_CSI2_ESC>, + <&clk IMX8MQ_CLK_CSI2_PHY_REF>; + clock-names = "clk_core", "clk_esc", "clk_pxl"; + assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, + <&clk IMX8MQ_CLK_CSI2_PHY_REF>, + <&clk IMX8MQ_CLK_CSI2_ESC>; + assigned-clock-rates = <133000000>, <100000000>, <66000000>; + power-domains = <&pgc_mipi_csi2>; + csis-phy-reset = <&src 0x50 7>; + phy-gpr = <&iomuxc_gpr 0xa4>; + status = "disabled"; + }; + + csi2_bridge: csi2_bridge@30b80000 { + compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi"; + reg = <0x30b80000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_CSI2_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + qspi0: spi@30bb0000 { #address-cells = <1>; #size-cells = <0>; @@ -917,6 +1220,11 @@ "enet_clk_ref", "enet_out"; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; + nvmem-cells = <&fec_mac_address>; + nvmem-cell-names = "mac-address"; + nvmem_macaddr_swap; + stop-mode = <&iomuxc_gpr 0x10 3>; + fsl,wakeup_irq = <2>; status = "disabled"; }; }; @@ -927,6 +1235,14 @@ #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; + hdmi: hdmi@32c00000 { + reg = <0x32c00000 0x100000>, + <0x32e40000 0x40000>; + interrupts = , + ; + interrupt-names = "plug_in", "plug_out"; + }; + irqsteer: interrupt-controller@32e2d000 { compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; reg = <0x32e2d000 0x1000>; @@ -938,6 +1254,35 @@ interrupt-controller; #interrupt-cells = <1>; }; + + dcss: display-controller@32e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mq-dcss"; + reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>; + interrupts = <6>, <8>, <9>, <16>, <17>; + interrupt-names = "ctx_ld", "ctxld_kick", "vblank", + "dtrc_ch1", "dtrc_ch2"; + interrupt-parent = <&irqsteer>; + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_VIDEO2_PLL_OUT>, + <&clk IMX8MQ_CLK_DISP_DTRC>, + <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>, + <&clk IMX8MQ_CLK_PHY_27MHZ>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc", "pll_src", + "pll_phy_ref"; + assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, + <&clk IMX8MQ_CLK_DISP_RTRM>, + <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_CLK_27M>; + assigned-clock-rates = <800000000>, + <400000000>; + status = "disabled"; + }; }; gpu: gpu@38000000 { @@ -962,6 +1307,7 @@ assigned-clock-rates = <800000000>, <800000000>, <800000000>, <800000000>, <0>; power-domains = <&pgc_gpu>; + status = "disabled"; }; usb_dwc3_0: usb@38100000 { @@ -981,6 +1327,7 @@ phy-names = "usb2-phy", "usb3-phy"; power-domains = <&pgc_otg1>; usb3-resume-missing-cas; + snps,power-down-scale = <2>; status = "disabled"; }; @@ -1013,6 +1360,7 @@ phy-names = "usb2-phy", "usb3-phy"; power-domains = <&pgc_otg2>; usb3-resume-missing-cas; + snps,power-down-scale = <2>; status = "disabled"; }; @@ -1028,6 +1376,35 @@ status = "disabled"; }; + dma_apbh: dma-apbh@33000000 { + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x33000000 0x2000>; + interrupts = , + , + , + ; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clk IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; + }; + + gpmi: gpmi-nand@33002000{ + compatible = "fsl,imx7d-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x33002000 0x2000>, <0x33004000 0x4000>; + reg-names = "gpmi-nand", "bch"; + interrupts = ; + interrupt-names = "bch"; + clocks = <&clk IMX8MQ_CLK_RAWNAND_ROOT>, + <&clk IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; + clock-names = "gpmi_io", "gpmi_bch_apb"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + pcie0: pcie@33800000 { compatible = "fsl,imx8mq-pcie"; reg = <0x33800000 0x400000>, @@ -1041,8 +1418,9 @@ 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ num-lanes = <1>; num-viewport = <4>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + ; /* eDMA */ + interrupt-names = "msi", "dma"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, @@ -1070,8 +1448,9 @@ 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ num-lanes = <1>; num-viewport = <4>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + ; /* eDMA */ + interrupt-names = "msi", "dma"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, @@ -1106,5 +1485,58 @@ interrupt-parent = <&gic>; interrupts = ; }; + + vpu: vpu@38300000 { + compatible = "nxp,imx8mq-hantro"; + reg = <0x38300000 0x200000>; + reg-names = "regs_hantro"; + interrupts = , ; + interrupt-names = "irq_hantro_g1", "irq_hantro_g2"; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, <&clk IMX8MQ_CLK_VPU_G2_ROOT>, <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; + clock-names = "clk_hantro_g1", "clk_hantro_g2", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, <&clk IMX8MQ_CLK_VPU_G2>, <&clk IMX8MQ_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_SYS1_PLL_800M>; + assigned-clock-rates = <600000000>, <600000000>, <800000000>; + power-domains = <&pgc_vpu>; + status = "disabled"; + }; + }; + + gpu3d: gpu3d@38000000 { + compatible = "fsl,imx8mq-gpu", "fsl,imx6q-gpu"; + reg = <0x0 0x38000000 0x0 0x40000>, <0x0 0x40000000 0x0 0xC0000000>, <0x0 0x0 0x0 0x10000000>; + reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem"; + interrupts = ; + interrupt-names = "irq_3d"; + clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, + <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, + <&clk IMX8MQ_CLK_GPU_AXI>, + <&clk IMX8MQ_CLK_GPU_AHB>; + clock-names = "gpu3d_clk", "gpu3d_shader_clk", "gpu3d_axi_clk", "gpu3d_ahb_clk"; + assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, + <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, + <&clk IMX8MQ_CLK_GPU_AXI>, + <&clk IMX8MQ_CLK_GPU_AHB>; + assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, + <&clk IMX8MQ_GPU_PLL_OUT>, + <&clk IMX8MQ_GPU_PLL_OUT>, + <&clk IMX8MQ_GPU_PLL_OUT>; + assigned-clock-rates = <800000000>, <800000000>, <800000000>, <800000000>; + power-domains = <&pgc_gpu>; + status = "disabled"; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx8mq-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8q-val.dtsi b/arch/arm64/boot/dts/freescale/imx8q-val.dtsi new file mode 100644 index 00000000000000..4e15f7ff1d367b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8q-val.dtsi @@ -0,0 +1,993 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/ { + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + user { + label = "heartbeat"; + gpios = <&lsio_gpio2 15 0>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + decoder_boot: decoder_boot@0x84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + }; + encoder_boot: encoder_boot@0x86000000 { + no-map; + reg = <0 0x86000000 0 0x400000>; + }; + /* + * reserved-memory layout + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + rpmsg_dma_reserved:rpmsg_dma@0x90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x100000>; + }; + decoder_rpc: decoder_rpc@0x92000000 { + no-map; + reg = <0 0x92000000 0 0x200000>; + }; + encoder_rpc: encoder_rpc@0x92200000 { + no-map; + reg = <0 0x92200000 0 0x200000>; + }; + dsp_reserved: dsp@0x92400000 { + no-map; + reg = <0 0x92400000 0 0x2000000>; + }; + encoder_reserved: encoder_reserved@0x94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_audio: regulator@0 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can_en: regulator-can-gen { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; + off-on-delay = <3000>; + enable-active-high; + }; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&codec>; + asrc-controller = <&asrc0>; + }; +}; + +&acm { + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&iomuxc { + imx8qm-val { + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + IMX8QM_ENET1_MDC_CONN_ENET1_MDC 0x06000020 + IMX8QM_ENET1_MDIO_CONN_ENET1_MDIO 0x06000020 + IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_hdmi_lpi2c0: hdmilpi2c0grp { + fsl,pins = < + IMX8QM_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL 0xc600004c + IMX8QM_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc600004c + IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc600004c + IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en { + fsl,pins = < + IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021 + >; + }; + + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = < + IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c + IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0xc600004c + IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + IMX8QM_GPT1_CLK_DMA_I2C2_SCL 0xc600004c + IMX8QM_GPT1_CAPTURE_DMA_I2C2_SDA 0xc600004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 + IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 + IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 + IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020 + IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 + >; + }; + + pinctrl_mlb: mlbgrp { + fsl,pins = < + IMX8QM_MLB_SIG_CONN_MLB_SIG 0x21 + IMX8QM_MLB_CLK_CONN_MLB_CLK 0x21 + IMX8QM_MLB_DATA_CONN_MLB_DATA 0x21 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + IMX8QM_ADC_IN2_LSIO_GPIO3_IO20 0x00000021 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 + IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 + IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan2grp { + fsl,pins = < + IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 + IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + IMX8QM_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021 + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 + IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 + >; + }; + + pinctrl_pcieb: pciebgrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x06000021 + IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 + IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_lvds0_pwm0: lvds0pwm0grp { + fsl,pins = < + IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_lvds1_pwm0: lvds1pwm0grp { + fsl,pins = < + IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_mipi_csi0_gpio: mipicsi0gpiogrp{ + fsl,pins = < + IMX8QM_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 0x00000021 + IMX8QM_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 0x00000021 + >; + }; + + pinctrl_mipi_csi1_gpio: mipicsi1gpiogrp{ + fsl,pins = < + IMX8QM_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 0x00000021 + IMX8QM_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 0x00000021 + >; + }; + }; +}; + +&lsio_gpio2 { + status = "okay"; +}; + +&lsio_gpio5 { + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + dr_mode = "host"; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + status = "disabled"; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt35xu512aba"; + spi-max-frequency = <133000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&gpio0_mipi_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0_gpio>; + status = "okay"; +}; + +&gpio0_mipi_csi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi1_gpio>; + status = "okay"; +}; + +&i2c_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6A>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&gpio0_mipi_csi0 0 GPIO_ACTIVE_HIGH>; + virtual-channel; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c_mipi_csi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "disabled"; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6A>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&gpio0_mipi_csi1 0 GPIO_ACTIVE_HIGH>; + virtual-channel; + port { + max9286_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c0_hdmi { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_lpi2c0>; + clock-frequency = <100000>; + status = "disabled"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + codec: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_a 2 1>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_c: gpio@1b { + compatible = "nxp,pca9557"; + reg = <0x1b>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_d: gpio@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + }; + + fxas2100x@20 { + compatible = "fsl,fxas2100x"; + reg = <0x20>; + }; + + fxos8700@1d { + compatible = "fsl,fxos8700"; + reg = <0x1d>; + }; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&lsio_gpio3>; + interrupts = <20 2>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&lpuart0 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "okay"; +}; + +&lpuart3 { /* GPS */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "okay"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "disabled"; + + /* Camera 0 MIPI CSI-2 (CSIS1) */ + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&max9286_1_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_1 { + status = "okay"; +}; + +&isi_2 { + status = "okay"; +}; + +&isi_3 { + status = "okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&gpu_3d1 { + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&pciea{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcieb{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&cm41_intmux { + status = "okay"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8qm-ddr4-val.dts new file mode 100644 index 00000000000000..d11def2e6e91d8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ddr4-val.dts @@ -0,0 +1,886 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include +#include "imx8qm.dtsi" + +/ { + model = "Freescale i.MX8QM DDR4 VALIDATION"; + compatible = "fsl,imx8qm-val", "fsl,imx8qm"; + + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + bcmdhd_fw = "/lib/firmware/bcm/1FD_BCM89359/fw_bcmdhd.bin"; + bcmdhd_nv = "/lib/firmware/bcm/1FD_BCM89359/bcmdhd.cal"; + }; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + user { + label = "heartbeat"; + gpios = <&lsio_gpio2 15 0>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + decoder_boot: decoder_boot@0x84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + }; + encoder_boot: encoder_boot@0x86000000 { + no-map; + reg = <0 0x86000000 0 0x400000>; + }; + /* + * reserved-memory layout + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + rpmsg_dma_reserved:rpmsg_dma@0x90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x100000>; + }; + decoder_rpc: decoder_rpc@0x92000000 { + no-map; + reg = <0 0x92000000 0 0x200000>; + }; + encoder_rpc: encoder_rpc@0x92200000 { + no-map; + reg = <0 0x92200000 0 0x200000>; + }; + dsp_reserved: dsp@0x92400000 { + no-map; + reg = <0 0x92400000 0 0x2000000>; + }; + encoder_reserved: encoder_reserved@0x94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_audio: regulator@0 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can_en: regulator-can-gen { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&pca9557_b 3 0>; + enable-active-high; + }; + }; +}; + +&acm { + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&asrc1 { + fsl,asrc-rate = <48000>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; + +&iomuxc { + imx8qm-val { + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + IMX8QM_ENET1_MDC_CONN_ENET1_MDC 0x06000020 + IMX8QM_ENET1_MDIO_CONN_ENET1_MDIO 0x06000020 + IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_hdmi_lpi2c0: hdmilpi2c0grp { + fsl,pins = < + IMX8QM_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL 0xc600004c + IMX8QM_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc600004c + IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc600004c + IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en { + fsl,pins = < + IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021 + >; + }; + + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = < + IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c + IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0xc600004c + IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + IMX8QM_GPT1_CLK_DMA_I2C2_SCL 0xc600004c + IMX8QM_GPT1_CAPTURE_DMA_I2C2_SDA 0xc600004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 + IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 + IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 + IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020 + IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 + >; + }; + + pinctrl_mlb: mlbgrp { + fsl,pins = < + IMX8QM_MLB_SIG_CONN_MLB_SIG 0x21 + IMX8QM_MLB_CLK_CONN_MLB_CLK 0x21 + IMX8QM_MLB_DATA_CONN_MLB_DATA 0x21 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + IMX8QM_ADC_IN2_LSIO_GPIO3_IO20 0x00000021 + >; + }; + + pinctrl_usdhc3_gpio: usdhc3grpgpio { + fsl,pins = < + IMX8QM_USDHC2_RESET_B_CONN_USDHC2_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + /* WP */ + IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + /* CD */ + IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + /* WP */ + IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000020 + /* CD */ + IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000020 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + /* WP */ + IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000020 + /* CD */ + IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000020 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 + IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 + IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan2grp { + fsl,pins = < + IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 + IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + IMX8QM_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021 + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 + IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 + >; + }; + + pinctrl_pcieb: pciebgrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x06000021 + IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 + IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_lvds0_pwm0: lvds0pwm0grp { + fsl,pins = < + IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_lvds1_pwm0: lvds1pwm0grp { + fsl,pins = < + IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_mipi_csi0_gpio: mipicsi0gpiogrp{ + fsl,pins = < + IMX8QM_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 0x00000021 + IMX8QM_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 0x00000021 + >; + }; + + pinctrl_mipi_csi1_gpio: mipicsi1gpiogrp{ + fsl,pins = < + IMX8QM_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 0x00000021 + IMX8QM_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 0x00000021 + >; + }; + }; +}; + +&lsio_gpio2 { + status = "okay"; +}; + +&lsio_gpio5 { + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>,<&pinctrl_usdhc3_gpio>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>,<&pinctrl_usdhc3_gpio>; + bus-width = <4>; + cd-gpios = <&lsio_gpio4 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio4 11 GPIO_ACTIVE_HIGH>; + no-1-8-v; + status = "okay"; + +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + dr_mode = "host"; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + status = "disabled"; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt35xu512aba"; + spi-max-frequency = <133000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&i2c0_hdmi { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_lpi2c0>; + clock-frequency = <100000>; + status = "disabled"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_c: gpio@1b { + compatible = "nxp,pca9557"; + reg = <0x1b>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_d: gpio@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + }; + + fxas2100x@20 { + compatible = "fsl,fxas2100x"; + reg = <0x20>; + }; + + fxos8700@1d { + compatible = "fsl,fxos8700"; + reg = <0x1d>; + }; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&lsio_gpio3>; + interrupts = <20 2>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&lpuart0 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "disabled"; +}; + +&lpuart3 { /* GPS */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "disabled"; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_1 { + status = "okay"; +}; + +&isi_2 { + status = "okay"; +}; + +&isi_3 { + status = "okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&gpu_3d1 { + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&pciea{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&pcieb{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&cm41_intmux { + status = "okay"; +}; + +&rpmsg1{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <1>; + reg = <0x0 0x90100000 0x0 0x10000>; + status = "okay"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&vpu_decoder { + core_type = <2>; + status = "okay"; +}; + +&vpu_encoder { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-enet2-tja1100.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-enet2-tja1100.dtsi new file mode 100644 index 00000000000000..13692cf40709ae --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-enet2-tja1100.dtsi @@ -0,0 +1,70 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* fec1 cannot attach to ethphy0 since the PHY address + * conflict with ethphy2. So eth0 should not work. + * There still enable fec1 to share the MDIO bus for fec2 due + * to board limitation. + */ +&fec1 { + /* PHY address should rework to 3 */ + phy-handle = <ðphy3>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + tja110x,refclk_in; + /delete-property/ at803x,eee-disabled; + /delete-property/ at803x,vddio-1p8v; + }; + + ethphy3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&fec2 { + pinctrl-0 = <&pinctrl_fec2_rmii>; + clocks = <&enet1_lpcg 4>, + <&enet1_lpcg 2>, + <&clk IMX_SC_R_ENET_0 IMX_SC_C_DISABLE_50>, + <&enet1_lpcg 0>, + <&enet1_lpcg 1>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + /delete-property/ phy-supply; +}; + +&iomuxc { + pinctrl_fec2_rmii: fec2rmiigrp { + fsl,pins = < + IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_OUT 0x06000020 + IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000020 + IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000020 + IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RMII_RX_ER 0x06000020 + IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000020 + IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000020 + IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000020 + IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000020 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca53.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca53.dts new file mode 100644 index 00000000000000..53f8bad38368da --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca53.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qm-lpddr4-val.dts" + +&thermal_zones { + /delete-node/ cpu-thermal1; + + pmic-thermal0 { + cooling-maps { + map0 { + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@100; + /delete-node/ cpu@101; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca72.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca72.dts new file mode 100644 index 00000000000000..e59fd9cddd7d25 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca72.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qm-lpddr4-val.dts" + +&thermal_zones { + /delete-node/ cpu-thermal0; + + pmic-thermal0 { + cooling-maps { + map0 { + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@0; + /delete-node/ cpu@1; + /delete-node/ cpu@2; + /delete-node/ cpu@3; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-dp.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-dp.dts new file mode 100644 index 00000000000000..c8ab941ed3960d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-dp.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ +/* + * DP only dts, disable ldb display. + */ +#include "imx8qm-lpddr4-val.dts" + +/ { + sound-hdmi { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-dp"; + audio-cpu = <&sai5>; + hdmi-out; + }; +}; + +&sai5 { + status = "okay"; +}; + +&sai5_lpcg { + status = "okay"; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&i2c1_lvds0 { + status = "disabled"; +}; + +&irqsteer_hdmi { + status = "okay"; +}; + +&hdmi_lpcg_i2c0 { + status = "okay"; +}; + +&hdmi_lpcg_lis_ipg { + status = "okay"; +}; + +&hdmi_lpcg_pwm_ipg { + status = "okay"; +}; + +&hdmi_lpcg_i2s { + status = "okay"; +}; + +&hdmi_lpcg_gpio_ipg { + status = "okay"; +}; + +&hdmi_lpcg_msi_hclk { + status = "okay"; +}; + +&hdmi_lpcg_pxl { + status = "okay"; +}; + +&hdmi_lpcg_phy { + status = "okay"; +}; + +&hdmi_lpcg_apb_mux_csr { + status = "okay"; +}; + +&hdmi_lpcg_apb_mux_ctrl { + status = "okay"; +}; + +&hdmi_lpcg_apb { + status = "okay"; +}; + +&hdmi { + compatible = "cdn,imx8qm-dp"; + firmware-name = "dpfw.bin"; + lane-mapping = <0x1b>; + status = "okay"; +}; + +&spdif1 { + status = "okay"; +}; + +&spdif1_lpcg { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi-slave.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi-slave.dts new file mode 100644 index 00000000000000..302cc251e3dff4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi-slave.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018~2019 NXP + */ + +#include "imx8qm-lpddr4-val-lpspi.dts" + +/delete-node/&spidev0; + +&pinctrl_lpspi3 { + fsl,pins = < + IMX8QM_SPI3_SCK_DMA_SPI3_SCK 0x600004c + IMX8QM_SPI3_SDO_DMA_SPI3_SDO 0x600004c + IMX8QM_SPI3_SDI_DMA_SPI3_SDI 0x600004c + IMX8QM_SPI3_CS0_DMA_SPI3_CS0 0x600004c + >; +}; + +&lpspi3 { + #address-cells = <0>; + pinctrl-0 = <&pinctrl_lpspi3>; + /delete-property/ cs-gpios; + spi-slave; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi.dts new file mode 100644 index 00000000000000..da0682d0eaab57 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017~2019 NXP + */ + +#include "imx8qm-lpddr4-val.dts" + +&iomuxc { + pinctrl_lpspi0: lpspi0grp { + fsl,pins = < + IMX8QM_SPI0_SCK_DMA_SPI0_SCK 0x600004c + IMX8QM_SPI0_SDO_DMA_SPI0_SDO 0x600004c + IMX8QM_SPI0_SDI_DMA_SPI0_SDI 0x600004c + >; + }; + + pinctrl_lpspi0_cs: lpspi0cs { + fsl,pins = < + IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05 0x21 + >; + }; + + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + IMX8QM_SPI3_SCK_DMA_SPI3_SCK 0x600004c + IMX8QM_SPI3_SDO_DMA_SPI3_SDO 0x600004c + IMX8QM_SPI3_SDI_DMA_SPI3_SDI 0x600004c + IMX8QM_SPI3_CS0_DMA_SPI3_CS0 0x600004c + >; + }; +}; + +&lpspi0 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>; + cs-gpios = <&lsio_gpio3 5 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash: at45db041e@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <5000000>; + reg = <0>; + }; +}; + +&lpspi3 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi3>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <30000000>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-mqs.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-mqs.dts new file mode 100644 index 00000000000000..6103a5c0478adc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-mqs.dts @@ -0,0 +1,79 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8qm-lpddr4-val.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif0>; + spdif-in; + spdif-out; + status = "disabled"; + }; + + sound-mqs { + compatible = "fsl,imx8qm-lpddr4-arm2-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + cpu-dai = <&sai1>; + audio-codec = <&mqs>; + asrc-controller = <&asrc1>; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_spdif0: spdif0grp { + fsl,pins = < + IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX 0xc6000040 + IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX 0xc6000040 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + IMX8QM_SPDIF0_TX_AUD_MQS_L 0xc6000061 + IMX8QM_SPDIF0_RX_AUD_MQS_R 0xc6000061 + >; + }; +}; + +&mqs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs>; + status = "okay"; +}; + +&spdif0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif0>; + status = "disabled"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-spdif.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-spdif.dts new file mode 100644 index 00000000000000..ec874258dbb6eb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-spdif.dts @@ -0,0 +1,86 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8qm-lpddr4-val.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif0>; + spdif-in; + spdif-out; + }; + + sound-mqs { + compatible = "fsl,imx8qm-lpddr4-arm2-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + cpu-dai = <&sai1>; + audio-codec = <&mqs>; + status = "disabled"; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_spdif0: spdif0grp { + fsl,pins = < + IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX 0xc6000040 + IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX 0xc6000040 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + IMX8QM_SPDIF0_TX_AUD_MQS_L 0xc6000061 + IMX8QM_SPDIF0_RX_AUD_MQS_R 0xc6000061 + >; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&mqs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs>; + status = "disabled"; +}; + +&spdif0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val.dts new file mode 100755 index 00000000000000..2e7db1cf5689b1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val.dts @@ -0,0 +1,627 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + */ + +/dts-v1/; + +#include +#include "imx8qm.dtsi" + +/ { + model = "Freescale i.MX8QM LPDDR4 Validation Board"; + compatible = "fsl,imx8qm-lpddr4-val", "fsl,imx8qm"; + + chosen { + stdout-path = &lpuart0; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + decoder_boot: decoder_boot@0x84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + }; + + encoder_boot: encoder_boot@0x86000000 { + no-map; + reg = <0 0x86000000 0 0x400000>; + }; + + /* + * reserved-memory layout + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + + rpmsg_dma_reserved:rpmsg_dma@0x90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x100000>; + }; + + decoder_rpc: decoder_rpc@0x92000000 { + no-map; + reg = <0 0x92000000 0 0x200000>; + }; + + encoder_rpc: encoder_rpc@0x92200000 { + no-map; + reg = <0 0x92200000 0 0x200000>; + }; + + dsp_reserved: dsp@0x92400000 { + no-map; + reg = <0 0x92400000 0 0x2000000>; + }; + + encoder_reserved: encoder_reserved@0x94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + + }; + + reg_can_en: regulator-can-en { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_usdhc2_vmmc: usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_audio: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&cs42888>; + asrc-controller = <&asrc0>; + }; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&asrc1 { + fsl,asrc-rate = <48000>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + + status = "okay"; +}; + +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + status = "okay"; +}; + +&dc0_pc { + status = "okay"; +}; + +&dc0_prg1 { + status = "okay"; +}; + +&dc0_prg2 { + status = "okay"; + +}; + +&dc0_prg3 { + status = "okay"; +}; + +&dc0_prg4 { + status = "okay"; +}; + +&dc0_prg5 { + status = "okay"; +}; + +&dc0_prg6 { + status = "okay"; +}; + +&dc0_prg7 { + status = "okay"; +}; + +&dc0_prg8 { + status = "okay"; +}; + +&dc0_prg9 { + status = "okay"; +}; + +&dc0_dpr1_channel1 { + status = "okay"; +}; + +&dc0_dpr1_channel2 { + status = "okay"; +}; + +&dc0_dpr1_channel3 { + status = "okay"; +}; + +&dc0_dpr2_channel1 { + status = "okay"; +}; + +&dc0_dpr2_channel2 { + status = "okay"; +}; + +&dc0_dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&dc1_pc { + status = "okay"; +}; + +&dc1_prg1 { + status = "okay"; +}; + +&dc1_prg2 { + status = "okay"; + +}; + +&dc1_prg3 { + status = "okay"; +}; + +&dc1_prg4 { + status = "okay"; +}; + +&dc1_prg5 { + status = "okay"; +}; + +&dc1_prg6 { + status = "okay"; +}; + +&dc1_prg7 { + status = "okay"; +}; + +&dc1_prg8 { + status = "okay"; +}; + +&dc1_prg9 { + status = "okay"; +}; + +&dc1_dpr1_channel1 { + status = "okay"; +}; + +&dc1_dpr1_channel2 { + status = "okay"; +}; + +&dc1_dpr1_channel3 { + status = "okay"; +}; + +&dc1_dpr2_channel1 { + status = "okay"; +}; + +&dc1_dpr2_channel2 { + status = "okay"; +}; + +&dc1_dpr2_channel3 { + status = "okay"; +}; + +&dpu2 { + status = "okay"; +}; + +&sai6 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai6_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai7 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai7_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_a 2 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>, <24576000>; + status = "okay"; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_c: gpio@1b { + compatible = "nxp,pca9557"; + reg = <0x1b>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_d: gpio@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + nvmem-cells = <&fec_mac0>; + nvmem-cell-names = "mac-address"; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 + IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 + IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins = < + IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 + IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 + >; + }; + + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = < + IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c + IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0xc600004c + IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 + IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-ca53.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-ca53.dts new file mode 100644 index 00000000000000..b37842fd49b25b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-ca53.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qm-mek.dts" + +&thermal_zones { + /delete-node/ cpu-thermal1; + + pmic-thermal0 { + cooling-maps { + map0 { + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@100; + /delete-node/ cpu@101; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-ca72.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-ca72.dts new file mode 100644 index 00000000000000..357a4ebc4799ad --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-ca72.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qm-mek.dts" + +&thermal_zones { + /delete-node/ cpu-thermal0; + + pmic-thermal0 { + cooling-maps { + map0 { + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@0; + /delete-node/ cpu@1; + /delete-node/ cpu@2; + /delete-node/ cpu@3; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-dom0.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-dom0.dts new file mode 100644 index 00000000000000..10c73dc964e165 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-dom0.dts @@ -0,0 +1,774 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include "imx8qm-mek.dts" +#include "imx8qm-xen.dtsi" + +/ { + model = "Freescale i.MX8QM MEK"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + + stdout-path = &lpuart0; + + /* Could be updated by U-Boot */ + module@0 { + bootargs = "earlycon=xen console=hvc0 loglevel=8 root=/dev/mmcblk1p2 rw rootwait"; + compatible = "xen,linux-zimage", "xen,multiboot-module"; + reg = <0x00000000 0x80a00000 0x00000000 0xf93a00>; + }; + }; + + domu { + /* + * There are 5 MUs, 0A is used by Dom0, 1A is used + * by ATF, so for DomU, 2A/3A/4A could be used. + * SC_R_MU_0A + * SC_R_MU_1A + * SC_R_MU_2A + * SC_R_MU_3A + * SC_R_MU_4A + * The rsrcs and pads will be configured by uboot scu_rm cmd + */ + #address-cells = <1>; + #size-cells = <0>; + doma { + compatible = "xen,domu"; + /* + * The name entry in VM configuration file + * needs to be same as here. + */ + domain_name = "DomU"; + /* + * The reg property will be updated by U-Boot to + * reflect the partition id. + */ + reg = <0>; + init_on_rsrcs = < + IMX_SC_R_MU_2A + >; + rsrcs = < + IMX_SC_R_MU_2A + IMX_SC_R_GPU_0_PID0 + IMX_SC_R_GPU_0_PID1 + IMX_SC_R_GPU_0_PID2 + IMX_SC_R_GPU_0_PID3 + IMX_SC_R_LVDS_0 + IMX_SC_R_LVDS_0_I2C_0 + IMX_SC_R_LVDS_0_PWM_0 + IMX_SC_R_DC_0 + IMX_SC_R_DC_0_BLIT0 + IMX_SC_R_DC_0_BLIT1 + IMX_SC_R_DC_0_BLIT2 + IMX_SC_R_DC_0_BLIT_OUT + IMX_SC_R_DC_0_WARP + IMX_SC_R_DC_0_VIDEO0 + IMX_SC_R_DC_0_VIDEO1 + IMX_SC_R_DC_0_FRAC0 + IMX_SC_R_DC_0_PLL_0 + IMX_SC_R_DC_0_PLL_1 + IMX_SC_R_SDHC_0 + /*vpu*/ + IMX_SC_R_VPU_PID0 + IMX_SC_R_VPU_PID1 + IMX_SC_R_VPU_PID2 + IMX_SC_R_VPU_PID3 + IMX_SC_R_VPU_PID4 + IMX_SC_R_VPU_PID5 + IMX_SC_R_VPU_PID6 + IMX_SC_R_VPU_PID7 + IMX_SC_R_VPU + IMX_SC_R_VPU_DEC_0 + IMX_SC_R_VPU_ENC_0 + IMX_SC_R_VPU_ENC_1 + IMX_SC_R_VPU_TS_0 + IMX_SC_R_VPU_MU_0 + IMX_SC_R_VPU_MU_1 + IMX_SC_R_VPU_MU_2 + IMX_SC_R_VPU_MU_3 + /* usbotg1 */ + IMX_SC_R_USB_0 + IMX_SC_R_USB_0_PHY + /* usbotg3 */ + IMX_SC_R_USB_2 + IMX_SC_R_USB_2_PHY + + /* ASRC0 */ + IMX_SC_R_DMA_2_CH0 + IMX_SC_R_DMA_2_CH1 + IMX_SC_R_DMA_2_CH2 + IMX_SC_R_DMA_2_CH3 + IMX_SC_R_DMA_2_CH4 + IMX_SC_R_DMA_2_CH5 + IMX_SC_R_DMA_2_CH6 + IMX_SC_R_DMA_2_CH7 + IMX_SC_R_DMA_2_CH8 + IMX_SC_R_DMA_2_CH9 + IMX_SC_R_DMA_2_CH10 + IMX_SC_R_DMA_2_CH11 + IMX_SC_R_DMA_2_CH12 + IMX_SC_R_DMA_2_CH13 + IMX_SC_R_DMA_2_CH14 + IMX_SC_R_DMA_2_CH15 + IMX_SC_R_DMA_2_CH16 + IMX_SC_R_DMA_2_CH17 + IMX_SC_R_DMA_2_CH18 + IMX_SC_R_DMA_2_CH19 + IMX_SC_R_DMA_2_CH20 + IMX_SC_R_AUDIO_CLK_0 + IMX_SC_R_AUDIO_CLK_1 + IMX_SC_R_MCLK_OUT_0 + IMX_SC_R_MCLK_OUT_1 + IMX_SC_R_AUDIO_PLL_0 + IMX_SC_R_AUDIO_PLL_1 + IMX_SC_R_ASRC_0 + IMX_SC_R_ASRC_1 + IMX_SC_R_ESAI_0 + IMX_SC_R_ESAI_1 + IMX_SC_R_SAI_0 + IMX_SC_R_SAI_1 + IMX_SC_R_SAI_2 + IMX_SC_R_SAI_3 + IMX_SC_R_SAI_4 + IMX_SC_R_SAI_5 + IMX_SC_R_SAI_6 + IMX_SC_R_SAI_7 + IMX_SC_R_SPDIF_0 + IMX_SC_R_SPDIF_1 + IMX_SC_R_MQS_0 + IMX_SC_R_DMA_3_CH0 + IMX_SC_R_DMA_3_CH1 + IMX_SC_R_DMA_3_CH2 + IMX_SC_R_DMA_3_CH3 + IMX_SC_R_DMA_3_CH4 + IMX_SC_R_DMA_3_CH5 + IMX_SC_R_DMA_3_CH6 + IMX_SC_R_DMA_3_CH7 + IMX_SC_R_DMA_3_CH8 + IMX_SC_R_DMA_3_CH9 + IMX_SC_R_DMA_3_CH10 + + IMX_SC_R_SATA_0 + IMX_SC_R_PCIE_A + IMX_SC_R_PCIE_B + IMX_SC_R_SERDES_0 + IMX_SC_R_SERDES_1 + IMX_SC_R_HSIO_GPIO + + IMX_SC_R_DMA_0_CH14 + IMX_SC_R_DMA_0_CH15 + IMX_SC_R_UART_1 + + IMX_SC_R_MIPI_0 + IMX_SC_R_MIPI_0_I2C_0 + IMX_SC_R_MIPI_0_I2C_1 + IMX_SC_R_MIPI_1 + IMX_SC_R_MIPI_1_I2C_0 + IMX_SC_R_MIPI_1_I2C_1 + + IMX_SC_R_HDMI_PLL_0 + IMX_SC_R_HDMI_PLL_1 + IMX_SC_R_HDMI + IMX_SC_R_HDMI_I2C_0 + IMX_SC_R_HDMI_I2S + + IMX_SC_R_CSI_0 + IMX_SC_R_CSI_0_I2C_0 + IMX_SC_R_CSI_1 + IMX_SC_R_CSI_1_I2C_0 + IMX_SC_R_ISI_CH0 + IMX_SC_R_ISI_CH1 + IMX_SC_R_ISI_CH2 + IMX_SC_R_ISI_CH3 + IMX_SC_R_ISI_CH4 + IMX_SC_R_ISI_CH5 + IMX_SC_R_ISI_CH6 + IMX_SC_R_ISI_CH7 + IMX_SC_R_MJPEG_DEC_MP + IMX_SC_R_MJPEG_DEC_S0 + IMX_SC_R_MJPEG_DEC_S1 + IMX_SC_R_MJPEG_DEC_S2 + IMX_SC_R_MJPEG_DEC_S3 + IMX_SC_R_MJPEG_ENC_MP + IMX_SC_R_MJPEG_ENC_S0 + IMX_SC_R_MJPEG_ENC_S1 + IMX_SC_R_MJPEG_ENC_S2 + IMX_SC_R_MJPEG_ENC_S3 + >; + pads = < + /* i2c1_lvds1 */ + IMX8QM_LVDS0_I2C1_SCL + IMX8QM_LVDS0_I2C1_SDA + /* emmc */ + IMX8QM_EMMC0_CLK + IMX8QM_EMMC0_CMD + IMX8QM_EMMC0_DATA0 + IMX8QM_EMMC0_DATA1 + IMX8QM_EMMC0_DATA2 + IMX8QM_EMMC0_DATA3 + IMX8QM_EMMC0_DATA4 + IMX8QM_EMMC0_DATA5 + IMX8QM_EMMC0_DATA6 + IMX8QM_EMMC0_DATA7 + IMX8QM_EMMC0_STROBE + IMX8QM_EMMC0_RESET_B + + /* lvds pwm */ + IMX8QM_LVDS0_GPIO00 + + /* usbotg1/3 */ + IMX8QM_USB_SS3_TC0 + IMX8QM_QSPI1A_SS0_B + IMX8QM_USB_SS3_TC3 + IMX8QM_QSPI1A_DATA0 + + /* ESAI0 */ + IMX8QM_ESAI0_FSR + IMX8QM_ESAI0_FST + IMX8QM_ESAI0_SCKR + IMX8QM_ESAI0_SCKT + IMX8QM_ESAI0_TX0 + IMX8QM_ESAI0_TX1 + IMX8QM_ESAI0_TX2_RX3 + IMX8QM_ESAI0_TX3_RX2 + IMX8QM_ESAI0_TX4_RX1 + IMX8QM_ESAI0_TX5_RX0 + /* SAI1 */ + IMX8QM_SAI1_RXD + IMX8QM_SAI1_RXC + IMX8QM_SAI1_RXFS + IMX8QM_SAI1_TXD + IMX8QM_SAI1_TXC + + IMX8QM_PCIE_CTRL0_CLKREQ_B + IMX8QM_PCIE_CTRL0_WAKE_B + IMX8QM_PCIE_CTRL0_PERST_B + IMX8QM_LVDS1_I2C0_SDA + IMX8QM_USDHC2_RESET_B + + IMX8QM_QSPI1A_DQS + IMX8QM_UART1_RX + IMX8QM_UART1_TX + IMX8QM_UART1_CTS_B + IMX8QM_UART1_RTS_B + + IMX8QM_MIPI_CSI0_I2C0_SCL + IMX8QM_MIPI_CSI0_I2C0_SDA + IMX8QM_MIPI_CSI1_I2C0_SCL + IMX8QM_MIPI_CSI1_I2C0_SDA + IMX8QM_MIPI_CSI1_GPIO0_00 + + IMX8QM_MIPI_CSI0_GPIO0_00 + IMX8QM_MIPI_CSI0_GPIO0_01 + IMX8QM_MIPI_CSI0_MCLK_OUT + + IMX8QM_USDHC2_WP + + IMX8QM_MIPI_DSI0_I2C0_SCL + IMX8QM_MIPI_DSI0_I2C0_SDA + IMX8QM_MIPI_DSI0_GPIO0_01 + + IMX8QM_MIPI_DSI1_I2C0_SCL + IMX8QM_MIPI_DSI1_I2C0_SDA + IMX8QM_MIPI_DSI1_GPIO0_01 + + IMX8QM_SCU_GPIO0_07 + + IMX8QM_SPI0_CS1 + IMX8QM_SPI2_CS1 + IMX8QM_SAI1_RXFS + IMX8QM_SAI1_RXC + >; + + gpios = <&lsio_gpio1 13 GPIO_ACTIVE_LOW>, + <&lsio_gpio1 19 GPIO_ACTIVE_LOW>, + <&lsio_gpio1 27 GPIO_ACTIVE_LOW>, + <&lsio_gpio1 28 GPIO_ACTIVE_LOW>, + <&lsio_gpio1 30 GPIO_ACTIVE_LOW>, + <&lsio_gpio4 1 GPIO_ACTIVE_LOW>, + <&lsio_gpio4 3 GPIO_ACTIVE_LOW>, + <&lsio_gpio4 6 GPIO_ACTIVE_LOW>, + <&lsio_gpio4 9 GPIO_ACTIVE_LOW>, + <&lsio_gpio4 11 GPIO_ACTIVE_HIGH>, + <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>, + <&lsio_gpio4 22 GPIO_ACTIVE_LOW>, + <&lsio_gpio4 25 GPIO_ACTIVE_HIGH>, + <&lsio_gpio4 26 GPIO_ACTIVE_HIGH>, + <&lsio_gpio4 27 GPIO_ACTIVE_LOW>, + <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + }; + }; + + /* Interrupt 33 is not used, use it virtual PL031 */ + rtc0: rtc@23000000 { + interrupts = ; + xen,passthrough; + }; + + gpio4_dummy: gpio4_dummy@0{ + /* Passthrough gpio4 interrupt to DomU */ + interrupts = ; + xen,passthrough; + }; + + gpio1_dummy: gpio1_dummy@0{ + /* Passthrough gpio1 interrupt to DomU */ + interrupts = ; + xen,passthrough; + }; + + reserved-device-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + decoder_boot@0x84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + xen,passthrough; + }; + encoder_boot@0x86000000 { + no-map; + reg = <0 0x86000000 0 0x400000>; + xen,passthrough; + }; + m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + xen,passthrough; + }; + rpmsg@0x90000000 { + no-map; + reg = <0 0x90200000 0 0x200000>; + xen,passthrough; + }; + decoder_rpc@0x92000000 { + no-map; + reg = <0 0x92000000 0 0x200000>; + xen,passthrough; + }; + encoder_rpc@0x92200000 { + no-map; + reg = <0 0x92200000 0 0x200000>; + xen,passthrough; + }; + dsp@0x92400000 { + no-map; + reg = <0 0x92400000 0 0x2000000>; + xen,passthrough; + }; + encoder_reserved@0x94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + xen,passthrough; + }; + ts_boot@0x95000000 { + no-map; + reg = <0 0x95000000 0 0x400000>; + xen,passthrough; + }; + }; +}; + +&{/reserved-memory} { + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0xa8000000 0 0x58000000>; + linux,cma-default; + }; +}; + +&smmu { + mmu-masters = <&dpu1 0x13>, <&gpu_3d0 0x15>, <&usdhc1 0x12>, <&edma0 0x14>, + <&vpu_decoder 0x7>, <&usbotg1 0x11>, <&usbotg3 0x4>, + <&pciea 0x8>, <&edma214 0x10>, <&isi_0 0x5>; +}; + +&edma0 { + #stream-id-cells = <1>; + iommus = <&smmu>; + xen,passthrough; +}; + +&gpu_3d0{ + #stream-id-cells = <1>; + iommus = <&smmu>; + xen,passthrough; +}; + +&gpu_3d1{ + status = "okay"; +}; + +&imx8_gpu_ss { + cores = <&gpu_3d1>; + reg = <0xa8000000 0x58000000>, <0x0 0x10000000>; + status = "okay"; +}; + +&lsio_mu1 { + /* not map for dom0, dom0 will mmio trap to xen */ + xen,no-map; +}; + +/ { + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu2_disp0>, <&dpu2_disp1>; + }; +}; + +&dc0_irqsteer { + reg = <0x56000000 0x20000>; + xen,passthrough; +}; + +&dc0_pc { + xen,passthrough; +}; + +&dc0_prg1 { + xen,passthrough; +}; + +&dc0_prg2 { + xen,passthrough; +}; + +&dc0_prg3 { + xen,passthrough; +}; + +&dc0_prg4 { + xen,passthrough; +}; + +&dc0_prg5 { + xen,passthrough; +}; + +&dc0_prg6 { + xen,passthrough; +}; + +&dc0_prg7 { + xen,passthrough; +}; + +&dc0_prg8 { + xen,passthrough; +}; + +&dc0_prg9 { + xen,passthrough; +}; + +&dc0_dpr1_channel1 { + xen,passthrough; +}; + +&dc0_dpr1_channel2 { + xen,passthrough; +}; + +&dc0_dpr1_channel3 { + xen,passthrough; +}; + +&dc0_dpr2_channel1 { + xen,passthrough; +}; + +&dc0_dpr2_channel2 { + xen,passthrough; +}; + +&dc0_dpr2_channel3 { + xen,passthrough; +}; + +&dpu1 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&irqsteer_lvds0 { + reg = <0x56240000 0x10000>; + xen,passthrough; +}; + +&lvds0_region { + xen,passthrough; +}; + +&i2c1_lvds0 { + xen,passthrough; +}; + +&ldb1_phy { + xen,passthrough; +}; + +&ldb1 { + xen,passthrough; +}; + +&usdhc1 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&sdhc0_lpcg { + xen,passthrough; +}; + +&lsio_mu2 { + xen,passthrough; +}; + +&lsio_gpio1 { + /* + * Use GPT1 interrupt for hack + * This could be removed when interrupt sharing be supported. + */ + interrupts = ; + xen,domu-irq; + xen,shared; +}; + +/* +&gpt0 { + /delete-property/ interrupts; + status = "disabled"; +}; +*/ + +&lsio_gpio4 { + /* + * Use GPT0 interrupt for hack + * This could be removed when interrupt sharing be supported. + */ + interrupts = ; + xen,domu-irq; + xen,shared; +}; + +&gpio0_mipi_csi0 { + xen,passthrough; +}; + +&gpio0_mipi_csi1 { + xen,passthrough; +}; + +/* vpu_subsys */ +&vpu_lpcg { + xen,passthrough; +}; + +&vpu_decoder { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; + fsl,sc_rsrc_id = , + , + , + , + , + , + , + , + , + ; +}; + +&vpu_encoder { + xen,passthrough; +}; + +&vpu_ts { + xen,passthrough; +}; + +&mu_m0 { + xen,passthrough; +}; + +&mu1_m0 { + xen,passthrough; +}; + +&mu2_m0 { + xen,passthrough; +}; + +&mu3_m0 { + xen,passthrough; +}; + +&vpu_enc_core0 { + xen,passthrough; +}; + +&vpu_enc_core1 { + xen,passthrough; +}; + +&usbotg1 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&usbmisc1 { + xen,passthrough; +}; + +&usbphy1 { + xen,passthrough; +}; + +&usb2_lpcg { + xen,passthrough; +}; + +&usbotg3 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&usb3phynop1 { + status = "disabled"; +}; + +&usb3_lpcg { + xen,passthrough; +}; + +&ptn5110 { + status = "disabled"; +}; + +&{/cbtl04gp} { + status = "disabled"; +}; + +&audio_subsys { + reg = <0 0x59000000 0 0x1000000>; + xen,passthrough; +}; + +/* Passthrough baseboard audio to DomU */ +&cs42888 { + xen,passthrough; +}; + +®_audio { + xen,passthrough; +}; + +&{/sound-cs42888} { + xen,passthrough; +}; + +&esai0 { + xen,passthrough; +}; + +&wm8960 { + xen,passthrough; +}; + +&hsio_subsys { + xen,passthrough; +}; + +&pciea { + #stream-id-cells = <1>; + iommus = <&smmu>; + xen,passthrough; + fsl,sc_rsrc_id = ; +}; + +&pcieb { + xen,passthrough; +}; + +&epdev_on { + status = "disabled"; +}; + +&lpuart1 { + xen,passthrough; +}; + +&modem_reset { + status = "disabled"; +}; + +&edma214 { + xen,passthrough; + #stream-id-cells = <1>; +}; + +&hdmi_subsys { + xen,passthrough; + reg = <0 0x56260000 0 0x10000>; +}; + +&img_subsys { + xen,passthrough; + reg = <0 0x58000000 0 0x1000000>; +}; + +&mipi0_subsys { + xen,passthrough; + reg = <0 0x56220000 0 0x10000>; +}; + +&mipi1_subsys { + xen,passthrough; + reg = <0 0x57220000 0 0x10000>; +}; + +&isi_0 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; + fsl,sc_rsrc_id = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + +&sc_pwrkey { + status = "disabled"; +}; + +&pwm_lvds0 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-domu.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-domu.dts new file mode 100644 index 00000000000000..5558e6e5d09502 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-domu.dts @@ -0,0 +1,1416 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * At current stage, M41 is not ready to communicate with XEN, so we + * we need a way to tell XEN uboot is running or linux is running. + * XEN will check the contents of this area. + * So reserve a page at the beginning of GUEST_RAM0_BASE to avoid Linux + * touch this area. + */ +/memreserve/ 0x80000000 0x1000; + +/ { + model = "Freescale i.MX8QM DOMU"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm", "xen,xenvm-4.10", "xen,xenvm"; + interrupt-parent = <&gic>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + aliases { + mmc0 = &usdhc1; + dpu0 = &dpu1; + ldb0 = &ldb1; + serial1 = &lpuart1; + isi0 = &isi_0; + isi1 = &isi_1; + isi2 = &isi_2; + isi3 = &isi_3; + isi4 = &isi_4; + isi5 = &isi_5; + isi6 = &isi_6; + isi7 = &isi_7; + csi0 = &mipi_csi_0; + csi1 = &mipi_csi_1; + dphy0 = &mipi0_dphy; + dphy1 = &mipi1_dphy; + mipi_dsi0 = &mipi0_dsi_host; + mipi_dsi1 = &mipi1_dsi_host; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x3>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "hvc"; + }; + + memory@80000000 { + device_type = "memory"; + /* Will be updated by U-Boot or XEN TOOL */ + reg = <0x00000000 0x80000000 0 0x80000000>; + }; + + /* + * The reserved memory will be used when using U-Boot loading android + * image. For booting kernel using xl tool, pass args: + * cma=960M@2400M-3584M + * For the rpmsg_reserved area, need xl tool to create for non-android. + */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + passthrough; + + decoder_boot: decoder_boot@0x84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + }; + encoder_boot: encoder_boot@0x86000000 { + no-map; + reg = <0 0x86000000 0 0x400000>; + }; + decoder_rpc: decoder_rpc@0x92000000 { + no-map; + reg = <0 0x92000000 0 0x200000>; + }; + encoder_rpc: encoder_rpc@0x92200000 { + no-map; + reg = <0 0x92200000 0 0x200000>; + }; + encoder_reserved: encoder_reserved@0x94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + }; + ts_boot: ts_boot@0x95000000 { + no-map; + reg = <0 0x95000000 0 0x400000>; + }; + + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90200000 0 0x200000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + + }; + + gic: interrupt-controller@3001000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0x0>; + interrupt-controller; + redistributor-stride = <0x20000>; + #redistributor-regions = <0x1>; + reg = <0x0 0x3001000 0 0x10000>, /* GIC Dist */ + <0x0 0x3020000 0 0x1000000>; /* GICR */ + interrupts = ; + interrupt-parent = <&gic>; + linux,phandle = <0xfde8>; + phandle = <0xfde8>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + ; + interrupt-parent = <&gic>; + clock-frequency = <8000000>; + }; + + hypervisor { + compatible = "xen,xen-4.11", "xen,xen"; + reg = <0x0 0x38000000 0x0 0x1000000>; + interrupts = ; + interrupt-parent = <&gic>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + clk0: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + rtc0: rtc@23000000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x0 0x23000000 0x0 0x1000>; + interrupts = ; + clocks = <&clk0>; + clock-names = "apb_pclk"; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_modem_reset>; + pinctrl-1 = <&pinctrl_modem_reset_sleep>; + reset-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + xen,passthrough; + }; + + passthrough { + compatible = "simple-bus"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + xtal32k: clock-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xtal_24MHz"; + }; + + scu { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", "tx1", "tx2", "tx3", + "rx0", "rx1", "rx2", "rx3", + "gip3"; + mboxes = <&lsio_mu2 0 0 + &lsio_mu2 0 1 + &lsio_mu2 0 2 + &lsio_mu2 0 3 + &lsio_mu2 1 0 + &lsio_mu2 1 1 + &lsio_mu2 1 2 + &lsio_mu2 1 3 + &lsio_mu2 3 3>; + + pd: imx8qx-pd { + compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + }; + + clk: clock-controller { + compatible = "fsl,imx8qm-clk", "fsl,scu-clk"; + #clock-cells = <2>; + clocks = <&xtal32k &xtal24m>; + clock-names = "xtal_32KHz", "xtal_24Mhz"; + }; + + iomuxc: pinctrl { + compatible = "fsl,imx8qm-iomuxc"; + }; + + }; + + #include "imx8-ss-conn.dtsi" + #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-gpu0.dtsi" + #include "imx8-ss-gpu1.dtsi" + #include "imx8-ss-vpu.dtsi" + + brcmfmac: brcmfmac { + compatible = "cypress,brcmfmac"; + pinctrl-names = "init", "idle", "default"; + pinctrl-0 = <&pinctrl_wifi_init>; + pinctrl-1 = <&pinctrl_wifi_init>; + pinctrl-2 = <&pinctrl_wifi>; + }; + + lvds_backlight0: lvds_backlight@0 { + compatible = "pwm-backlight"; + pwms = <&pwm_lvds0 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + }; + + display-subsystem { + xen,passthrough; + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu1_disp0>, <&dpu1_disp1>; + }; + + #include "imx8-ss-dc0.dtsi" + #include "imx8-ss-dc1.dtsi" + #include "imx8-ss-audio.dtsi" + #include "imx8-ss-hsio.dtsi" + #include "imx8-ss-dma.dtsi" + #include "imx8-ss-img.dtsi" + + sc_pwrkey: sc-powerkey { + compatible = "fsl,imx8-pwrkey"; + linux,keycode = ; + xen,passthrough; + }; + + reg_audio: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + xen,passthrough; + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_wlreg_on>; + pinctrl-1 = <&pinctrl_wlreg_on_sleep>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&lsio_gpio1 13 0>; + enable-active-high; + xen,passthrough; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&cs42888>; + asrc-controller = <&asrc0>; + status = "okay"; + xen,passthrough; + }; + + xen_i2c0: xen_i2c@0 { + compatible = "xen,i2c"; + be-adapter = "5a800000.i2c"; + status = "okay"; + xen,passthrough; + }; + + xen_i2c1: xen_i2c@1 { + compatible = "xen,i2c"; + be-adapter = "3b230000.i2c"; + xen,passthrough; + status = "okay"; + }; + + cbtl04gp { + compatible = "nxp,cbtl04gp"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec_mux>; + switch-gpios = <&lsio_gpio4 6 GPIO_ACTIVE_LOW>; + reset-gpios = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + orientation-switch; + xen,passthrough; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; +}; + +#include "imx8qm-ss-conn.dtsi" +#include "imx8qm-ss-lsio.dtsi" +#include "imx8qm-ss-dc.dtsi" +#include "imx8qm-ss-gpu.dtsi" +#include "imx8qm-ss-lvds.dtsi" +#include "imx8qm-ss-mipi.dtsi" +#include "imx8qm-ss-hdmi.dtsi" +#include "imx8qm-ss-audio.dtsi" +#include "imx8qm-ss-hsio.dtsi" +#include "imx8qm-ss-dma.dtsi" +#include "imx8qm-ss-mipi.dtsi" +#include "imx8qm-ss-hdmi.dtsi" +#include "imx8qm-ss-img.dtsi" + +&dc0_subsys { + xen,passthrough; +}; + +&dma_subsys { + xen,passthrough; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5a000000 0x0 0x5a000000 0x1000000>; + + + edma214: dma-controller@5a2e0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x5a2e0000 0x10000>, /* channel14 UART1 rx */ + <0x5a2f0000 0x10000>; /* channel15 UART1 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = , + ; + interrupt-names = "edma0-chan14-rx", "edma0-chan15-tx"; + power-domains = <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>; + power-domain-names = "edma0-chan14", "edma0-chan15"; + status = "okay"; + }; +}; + +&audio_subsys { + xen,passthrough; +}; + +&hsio_subsys { + xen,passthrough; +}; + +&lvds1_subsys { + xen,passthrough; +}; + +&hdmi_subsys { + xen,passthrough; +}; + +&lsio_mu1 { + status = "disabled"; +}; + +&lsio_mu2 { + status = "okay"; +}; + +&pwm_lvds0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_lvds0>; + status = "okay"; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb1_phy { + status="okay"; +}; + +&ldb1 { + status="okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&dc0_pc { + status="okay"; +}; + +&dc0_prg1 { + status="okay"; +}; + +&dc0_prg2 { + status="okay"; +}; + +&dc0_prg3 { + status="okay"; +}; + +&dc0_prg4 { + status="okay"; +}; + +&dc0_prg5 { + status="okay"; +}; + +&dc0_prg6 { + status="okay"; +}; + +&dc0_prg7 { + status="okay"; +}; + +&dc0_prg8 { + status="okay"; +}; + +&dc0_prg9 { + status="okay"; +}; + +&dc0_dpr1_channel1 { + status="okay"; +}; + +&dc0_dpr1_channel2 { + status="okay"; +}; + +&dc0_dpr1_channel3 { + status="okay"; +}; + +&dc0_dpr2_channel1 { + status="okay"; +}; + +&dc0_dpr2_channel2 { + status="okay"; +}; + +&dc0_dpr2_channel3 { + status="okay"; +}; + +&dpu1 { + status="okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&gpu_3d1 { + status = "disabled"; +}; + +&imx8_gpu_ss { + /* xen guests have 2GB of low RAM @ 2GB */ + reg = <0x80000000 0x80000000>, <0x0 0x10000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; + cores = <&gpu_3d0>; + status = "okay"; +}; + +&iomuxc { + + pinctrl_wifi: wifigrp{ + fsl,pins = < + IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 + >; + }; + + pinctrl_wifi_init: wifi_initgrp{ + fsl,pins = < + /* reserve pin init/idle_state to support multiple wlan cards */ + >; + }; + + pinctrl_pwm_lvds0: pwmlvds0grp { + fsl,pins = < + IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 + >; + }; + + pinctrl_typec_mux: typecmuxgrp { + fsl,pins = < + IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60 + IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 + IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021 + >; + }; + + pinctrl_wlreg_on: wlregongrp{ + fsl,pins = < + IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000 + >; + }; + + pinctrl_wlreg_on_sleep: wlregon_sleepgrp{ + fsl,pins = < + IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x07800000 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 + IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 + IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + + pinctrl_modem_reset: modemresetgrp { + fsl,pins = < + IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x06000021 + >; + }; + + pinctrl_modem_reset_sleep: modemreset_sleepgrp { + fsl,pins = < + IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x07800021 + >; + }; + + pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 { + fsl,pins = < + IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 + IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_i2c_mipi_csi1: i2c_mipi_csi1 { + fsl,pins = < + IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL 0xc2000020 + IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_mipi_csi0: mipi_csi0 { + fsl,pins = < + IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0xC0000041 + IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0xC0000041 + IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 + >; + }; + + pinctrl_mipi_csi1: mipi_csi1 { + fsl,pins = < + IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0xC0000041 + IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0xC0000041 + IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xC0000041 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + >; + }; + + pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x00000020 + >; + }; + + pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x00000020 + >; + }; +}; + +&usdhc1 { + /delete-property/ iommus; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&usdhc2 { + /delete-property/ iommus; + status = "disabled"; +}; + +&usdhc3 { + /delete-property/ iommus; + status = "disabled"; +}; + +&fec1 { + /delete-property/ iommus; + status = "disabled"; +}; + +&fec2 { + /delete-property/ iommus; + status = "disabled"; +}; + +&usbphy1 { + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usb3phynop1 { + status = "okay"; +}; + +&usbotg3 { + dr_mode = "otg"; + extcon = <&ptn5110>; + status = "okay"; + /delete-property/ iommus; +}; + +&xen_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + status = "okay"; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <11 2>; + }; + + fxos8700@1e { + compatible = "fsl,fxos8700"; + reg = <0x1e>; + interrupt-open-drain; + }; + + fxas2100x@20 { + compatible = "fsl,fxas2100x"; + reg = <0x20>; + interrupt-open-drain; + }; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + interrupt-open-drain; + }; + + ptn5110: tcpc@51 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x51>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + usb_con1: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "source"; + data-role = "dual"; + source-pdos = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&mu_m0{ + interrupts = ; +}; + +&mu1_m0{ + interrupts = ; +}; + +&mu2_m0{ + interrupts = ; + status = "okay"; +}; + +&mu3_m0{ + interrupts = ; + status = "okay"; +}; + +&vpu_decoder { + compatible = "nxp,imx8qm-b0-vpudec"; + boot-region = <&decoder_boot>; + rpc-region = <&decoder_rpc>; + reg-csr = <0x2d080000>; + core_type = <2>; + status = "okay"; +}; + +&vpu_ts { + compatible = "nxp,imx8qm-b0-vpu-ts"; + boot-region = <&ts_boot>; + reg-csr = <0x2d0b0000>; + status = "okay"; +}; + +&vpu_encoder { + compatible = "nxp,imx8qm-b0-vpuenc"; + boot-region = <&encoder_boot>; + rpc-region = <&encoder_rpc>; + reserved-region = <&encoder_reserved>; + reg-rpc-system = <0x40000000>; + resolution-max = <1920 1920>; + power-domains = <&pd IMX_SC_R_VPU_ENC_0>, <&pd IMX_SC_R_VPU_ENC_1>, + <&pd IMX_SC_R_VPU>; + power-domain-names = "vpuenc1", "vpuenc2", "vpu"; + mbox-names = "enc1_tx0", "enc1_tx1", "enc1_rx", + "enc2_tx0", "enc2_tx1", "enc2_rx"; + mboxes = <&mu1_m0 0 0 + &mu1_m0 0 1 + &mu1_m0 1 0 + &mu2_m0 0 0 + &mu2_m0 0 1 + &mu2_m0 1 0>; + status = "okay"; + + vpu_enc_core0: core0@1020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x1020000 0x20000>; + reg-csr = <0x1090000 0x10000>; + interrupts = ; + fsl,vpu_ap_mu_id = <17>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; + + vpu_enc_core1: core1@1040000 { + compatible = "fsl,imx8-mu2-vpu-m0"; + reg = <0x1040000 0x20000>; + reg-csr = <0x10A0000 0x10000>; + interrupts = ; + fsl,vpu_ap_mu_id = <18>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; +}; + +&lsio_gpio4 { + /delete-property/ power-domains; +}; + +&lsio_gpio1 { + /delete-property/ power-domains; +}; + +/* Audio */ +/*&dsp { + compatible = "fsl,imx8qm-dsp-v1"; + status = "okay"; +}; +*/ + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + fsl,txm-rxs; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + /*pinctrl-0 = <&pinctrl_sai1>;*/ + status = "disabled"; +}; + +&sai6 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai6_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "disabled"; +}; + +&sai7 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai7_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "disabled"; +}; + +&xen_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + status = "okay"; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&lsio_gpio4 25 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + fsl,txs-rxm; + status = "okay"; + }; +}; + +&sai6 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai6_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "disabled"; +}; + +&sai7 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai7_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "disabled"; +}; + +&sata { + /delete-property/ iommus; +}; + +&pciea{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + disable-gpio = <&lsio_gpio4 9 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + epdev_on-supply = <&epdev_on>; + reserved-region = <&rpmsg_reserved>; + status = "okay"; +}; + +&pcieb{ + status = "disabled"; +}; + +&edma2 { + status = "disabled"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "okay"; + dmas = <&edma214 15 0 0>, <&edma214 14 0 1>; +}; + +&img_subsys { + xen,passthrough; +}; + +&hdmi_subsys { + xen,passthrough; +}; + +&mipi0_subsys { + xen,passthrough; +}; + +&mipi1_subsys { + xen,passthrough; +}; + +&dsi_ipg_clk { + xen,passthrough; +}; + +&mipi_pll_div2_clk { + xen,passthrough; +}; + +&i2c0_mipi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi0_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge0: adv7535@3d { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port@0 { + reg = <0>; + adv7535_0_in: endpoint { + remote-endpoint = <&mipi0_adv_out>; + }; + }; + }; +}; + +&mipi0_dphy { + status = "okay"; +}; + +&mipi0_dsi_host { + status = "okay"; + + ports { + port@1 { + reg = <1>; + mipi0_adv_out: endpoint { + remote-endpoint = <&adv7535_0_in>; + }; + }; + }; +}; + +&i2c0_mipi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi1_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge1: adv7535@3d { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port@0 { + reg = <0>; + adv7535_1_in: endpoint { + remote-endpoint = <&mipi1_adv_out>; + }; + }; + }; +}; + +&mipi1_dphy { + status = "okay"; +}; + +&mipi1_dsi_host { + status = "okay"; + + ports { + port@1 { + reg = <1>; + mipi1_adv_out: endpoint { + remote-endpoint = <&adv7535_1_in>; + }; + }; + }; +}; + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; + + m2m_device { + status = "okay"; + }; +}; + +&isi_1 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_2 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_3 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_4 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_5 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_6 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_7 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&irqsteer_csi0 { + status = "okay"; +}; + +&irqsteer_csi1 { + status = "okay"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 1 MIPI CSI-2 (CSIS1) */ + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&max9286_1_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&jpegdec { + status = "okay"; +}; + +&jpegenc { + status = "okay"; +}; + +&i2c_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_mipi_csi0>; + clock-frequency = <100000>; + status = "okay"; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&lsio_gpio1 27 GPIO_ACTIVE_HIGH>; + virtual-channel; + status = "okay"; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c_mipi_csi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_mipi_csi1>; + clock-frequency = <100000>; + status = "okay"; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi1>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_HIGH>; + virtual-channel; + status = "okay"; + port { + max9286_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; + +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-dsi-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-dsi-rm67191.dts new file mode 100644 index 00000000000000..32ac9ca1b6a0ed --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-dsi-rm67191.dts @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qm-mek.dts" + +/delete-node/ &adv_bridge0; +/delete-node/ &adv_bridge1; + +&mipi0_dphy { + status = "okay"; +}; + +&mipi0_dsi_host { + status = "okay"; + fsl,clock-drop-level = <2>; + + panel@0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_0_1_en>; + pinctrl-names = "default"; + reset-gpios = <&lsio_gpio1 7 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; + width-mm = <68>; + height-mm = <121>; + + port@0 { + reg = <0>; + panel0_in: endpoint { + remote-endpoint = <&mipi0_panel_out>; + }; + }; + }; + + ports { + /delete-node/ port@1; + + port@1 { + reg = <1>; + mipi0_panel_out: endpoint { + remote-endpoint = <&panel0_in>; + }; + }; + }; +}; + +&mipi1_dphy { + status = "okay"; +}; + +&mipi1_dsi_host { + status = "okay"; + fsl,clock-drop-level = <2>; + + panel@0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "raydium,rm67191"; + reg = <0>; + reset-gpios = <&lsio_gpio1 7 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; + width-mm = <68>; + height-mm = <121>; + + port@0 { + reg = <0>; + panel1_in: endpoint { + remote-endpoint = <&mipi1_panel_out>; + }; + }; + }; + + ports { + /delete-node/ port@1; + + port@1 { + reg = <1>; + mipi1_panel_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en { + fsl,pins = < + IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-dsp.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-dsp.dts new file mode 100644 index 00000000000000..2dd8d4f031da4f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-dsp.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2018 + +#include "imx8qm-mek-rpmsg.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-wm8960 { + status = "disabled"; + }; + + dspaudio: dspaudio { + compatible = "fsl,dsp-audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + status = "okay"; + }; + + sound-dsp { + compatible = "fsl,imx-dsp-audio"; + model = "dsp-audio"; + cpu-dai = <&dspaudio>; + audio-codec = <&cs42888>; + audio-platform = <&dsp>; + }; +}; + +&edma0 { + compatible = "fsl,imx8qm-edma"; + reg = <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x592e0000 0x10000>, /* sai1 rx */ + <0x592f0000 0x10000>, /* sai1 tx */ + <0x59350000 0x10000>, + <0x59370000 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <8>; + interrupts = , /* spdif0 */ + , + , /* sai0 */ + , + , /* sai1 */ + , + , + ; + interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx", /* spdif0 */ + "edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */ + "edma2-chan14-rx", "edma2-chan15-tx", /* sai1 */ + "edma2-chan21-tx", /* gpt5 */ + "edma2-chan23-rx"; /* gpt7 */ + power-domains = <&pd IMX_SC_R_DMA_2_CH8>, <&pd IMX_SC_R_DMA_2_CH9>, + <&pd IMX_SC_R_DMA_2_CH12>, <&pd IMX_SC_R_DMA_2_CH13>, + <&pd IMX_SC_R_DMA_2_CH14>, <&pd IMX_SC_R_DMA_2_CH15>, + <&pd IMX_SC_R_DMA_2_CH21>, + <&pd IMX_SC_R_DMA_2_CH23>; + power-domain-names = "edma2-chan8", "edma2-chan9", + "edma2-chan12", "edma2-chan13", + "edma2-chan14", "edma2-chan15", + "edma2-chan21", + "edma2-chan23"; + status = "okay"; +}; + +&dsp { + compatible = "fsl,imx8qm-dsp-v1"; + reserved-region = <&dsp_reserved>; + reg = <0x556e8000 0x88000>; + clocks = <&esai0_lpcg 1>, + <&esai0_lpcg 0>, + <&asrc0_lpcg 0>, + <&asrc0_lpcg 1>, + <&aud_pll_div0_lpcg 0>, + <&aud_pll_div1_lpcg 0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>; + clock-names = "esai_ipg", "esai_mclk", "asrc_ipg", "asrc_mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3"; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>, + <&esai0_lpcg 0>; + audio-interface = "esai"; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + fsl,dsp-firmware = "imx/dsp/hifi4.bin"; + power-domains = <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_IRQSTR_DSP>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>, + <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_DMA_2_CH6>, + <&pd IMX_SC_R_DMA_2_CH7>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_DMA_2_CH0>, + <&pd IMX_SC_R_DMA_2_CH1>, + <&pd IMX_SC_R_DMA_2_CH2>, + <&pd IMX_SC_R_DMA_2_CH3>, + <&pd IMX_SC_R_DMA_2_CH4>, + <&pd IMX_SC_R_DMA_2_CH5>; + status = "okay"; +}; + +&esai0 { + status = "disabled"; +}; + +&asrc0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&wm8960 { + status = "disabled"; +}; + +&cs42888 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-enet2-tja1100.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-enet2-tja1100.dts new file mode 100644 index 00000000000000..61e7c4b644ce94 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-enet2-tja1100.dts @@ -0,0 +1,16 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8qm-mek.dts" +#include "imx8qm-enet2-tja1100.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi.dts new file mode 100644 index 00000000000000..10324988d63a00 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi.dts @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Sandor Yu + */ + /* HDMI Only driver, LVDS is disabled */ + +/dts-v1/; + +#include "imx8qm-mek-rpmsg.dts" + +/ { + sound-hdmi-tx { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-hdmi-tx"; + audio-cpu = <&sai5>; + protocol = <1>; + hdmi-out; + }; + + sound-hdmi-arc { + compatible = "fsl,imx-audio-spdif"; + model = "imx-hdmi-arc"; + spdif-controller = <&spdif1>; + spdif-in; + spdif-out; + }; +}; + +&sai5 { + status = "okay"; +}; + +&sai5_lpcg { + status = "okay"; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&ldb2_phy { + status = "disabled"; +}; + +&ldb2 { + status = "disabled"; +}; + +&mipi0_dsi_host { + status = "disabled"; +}; + +&mipi1_dphy { + status = "disabled"; +}; + +&mipi1_dsi_host { + status = "disabled"; +}; + +&mipi1_dphy { + status = "disabled"; +}; + +&irqsteer_hdmi { + status = "okay"; +}; + +&hdmi_lpcg_i2c0 { + status = "okay"; +}; + +&hdmi_lpcg_lis_ipg { + status = "okay"; +}; + +&hdmi_lpcg_pwm_ipg { + status = "okay"; +}; + +&hdmi_lpcg_i2s { + status = "okay"; +}; + +&hdmi_lpcg_gpio_ipg { + status = "okay"; +}; + +&hdmi_lpcg_msi_hclk { + status = "okay"; +}; + +&hdmi_lpcg_pxl { + status = "okay"; +}; + +&hdmi_lpcg_phy { + status = "okay"; +}; + +&hdmi_lpcg_apb_mux_csr { + status = "okay"; +}; + +&hdmi_lpcg_apb_mux_ctrl { + status = "okay"; +}; + +&hdmi_lpcg_apb { + status = "okay"; +}; + +&hdmi { + compatible = "cdn,imx8qm-hdmi"; + firmware-name = "hdmitxfw.bin"; + lane-mapping = <0x93>; + status = "okay"; +}; + +&spdif1 { + status = "okay"; +}; + +&spdif1_lpcg { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-inmate.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-inmate.dts new file mode 100644 index 00000000000000..47c622dce66767 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-inmate.dts @@ -0,0 +1,280 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "Freescale i.MX8QM MEK inmate"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + interrupt-parent = <&gic>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + aliases { + mmc0 = &usdhc1; + serial2 = &lpuart2; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x2>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x3>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + scu { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", "tx1", "tx2", "tx3", + "rx0", "rx1", "rx2", "rx3", + "gip3"; + mboxes = <&lsio_mu2 0 0 + &lsio_mu2 0 1 + &lsio_mu2 0 2 + &lsio_mu2 0 3 + &lsio_mu2 1 0 + &lsio_mu2 1 1 + &lsio_mu2 1 2 + &lsio_mu2 1 3 + &lsio_mu2 3 3>; + + pd: imx8qx-pd { + compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + }; + + clk: clock-controller { + compatible = "fsl,imx8qm-clk", "fsl,scu-clk"; + #clock-cells = <2>; + clocks = <&xtal32k &xtal24m>; + clock-names = "xtal_32KHz", "xtal_24Mhz"; + }; + + iomuxc: pinctrl { + compatible = "fsl,imx8qm-iomuxc"; + }; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + xtal32k: clock-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xtal_24MHz"; + }; + + pci@fd700000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, + <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, + <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, + <0 0 0 1 &gic GIC_SPI 127 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xfd700000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + /* For early console */ + serial@5a060000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a060000 0x0 0x1000>; + }; + + #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-adma.dtsi" + #include "imx8-ss-conn.dtsi" +}; + +#include "imx8qm-ss-lsio.dtsi" +#include "imx8qm-ss-dma.dtsi" +#include "imx8qm-ss-conn.dtsi" + +&edma0 { + status = "disabled"; +}; + +&edma1 { + status = "disabled"; +}; + +&edma2 { + status = "disabled"; +}; + +&acm { + status = "disabled"; +}; + +&lsio_mu1 { + status = "disabled"; +}; + +&lsio_mu2 { + status = "okay"; +}; + +&lsio_gpio0 { + status = "disabled"; +}; + +&lsio_gpio1 { + status = "disabled"; +}; + +&lsio_gpio2 { + status = "disabled"; +}; + +&lsio_gpio3 { + status = "disabled"; +}; + +&lsio_gpio4 { + status = "disabled"; +}; + +&lsio_gpio5 { + status = "disabled"; +}; + +&lsio_gpio6 { + status = "disabled"; +}; + +&lsio_gpio7 { + status = "disabled"; +}; + +&fec1 { + /delete-property/ iommus; +}; + +&fec2 { + /delete-property/ iommus; +}; + +&usdhc1 { + /delete-property/ iommus; +}; + +&usdhc2 { + /delete-property/ iommus; +}; + +&usdhc3 { + /delete-property/ iommus; +}; + +&usbotg3 { + /delete-property/ iommus; +}; + +&iomuxc { + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020 + IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; + /delete-property/ dma-names; + /delete-property/ dmas; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel-rpmsg.dts new file mode 100644 index 00000000000000..b57423235fc712 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel-rpmsg.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8qm-mek-rpmsg.dts" +#include "imx8qm-mek-jdi-wuxga-lvds1-panel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dts new file mode 100644 index 00000000000000..821f37d50e0552 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019,2020 NXP + */ + +#include "imx8qm-mek.dts" +#include "imx8qm-mek-jdi-wuxga-lvds1-panel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dtsi new file mode 100644 index 00000000000000..68e96d8118aa5f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +/ { + lvds1_panel { + compatible = "jdi,tx26d202vm0bwa"; + backlight = <&lvds_backlight1>; + + port { + panel_lvds1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&i2c1_lvds0 { + lvds-to-hdmi-bridge@4c { + status = "disabled"; + }; +}; + +/delete-node/ &it6263_1_in; + +&ldb2 { + status = "okay"; + fsl,dual-channel; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_lvds1_in>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640.dts new file mode 100644 index 00000000000000..e58913258af8e7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640.dts @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2019 + +#include "imx8qm-mek.dts" + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; + + m2m_device { + status = "okay"; + }; +}; + +&isi_1 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_2 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_3 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_4 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_5 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_6 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_7 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&mipi_csi_0 { + /delete-property/virtual-channel; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_0_ep>; + data-lanes = <1 2>; + bus-type = <4>; + }; + }; +}; + +&mipi_csi_1 { + /delete-property/virtual-channel; + + /* Camera 1 MIPI CSI-2 (CSIS0) */ + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&ov5640_mipi_1_ep>; + data-lanes = <1 2>; + bus-type = <4>; + }; + }; +}; + +&i2c_mipi_csi0 { + ov5640_mipi_0: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&xtal24m>; + clock-names = "xclk"; + csi_id = <0>; + powerdown-gpios = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>; + reset-gpios = <&lsio_gpio1 27 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_mipi_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2>; + clocks-lanes = <0>; + }; + }; + }; + + /delete-node/max9286_mipi@6a; +}; + +&i2c_mipi_csi1 { + ov5640_mipi_1: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi1>; + clocks = <&xtal24m>; + clock-names = "xclk"; + csi_id = <0>; + powerdown-gpios = <&lsio_gpio1 31 GPIO_ACTIVE_HIGH>; + reset-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_mipi_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2>; + clocks-lanes = <0>; + }; + }; + }; + + /delete-node/max9286_mipi@6a; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-root.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-root.dts new file mode 100644 index 00000000000000..55cb2af806e88c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-root.dts @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include "imx8qm-mek.dts" + +/ { + domu { + /* + * There are 5 MUs, 0A is used by root cell, 1A is used + * by ATF, so for non-root cell, 2A/3A/4A could be used. + * SC_R_MU_0A + * SC_R_MU_1A + * SC_R_MU_2A + * SC_R_MU_3A + * SC_R_MU_4A + * The rsrcs and pads will be configured by uboot scu_rm cmd + */ + #address-cells = <1>; + #size-cells = <0>; + doma { + /* + * This is not for domu, this is just reuse + * the method for jailhouse inmate non root cell + * Linux. + */ + compatible = "xen,domu"; + /* + * The reg property will be updated by U-Boot to + * reflect the partition id. + */ + reg = <0>; + init_on_rsrcs = < + IMX_SC_R_MU_2A + >; + rsrcs = < + IMX_SC_R_SDHC_0 + IMX_SC_R_UART_2 + IMX_SC_R_MU_2A + >; + pads = < + /* emmc */ + IMX8QM_EMMC0_CLK + IMX8QM_EMMC0_CMD + IMX8QM_EMMC0_DATA0 + IMX8QM_EMMC0_DATA1 + IMX8QM_EMMC0_DATA2 + IMX8QM_EMMC0_DATA3 + IMX8QM_EMMC0_DATA4 + IMX8QM_EMMC0_DATA5 + IMX8QM_EMMC0_DATA6 + IMX8QM_EMMC0_DATA7 + IMX8QM_EMMC0_STROBE + IMX8QM_EMMC0_RESET_B + /* lpuart2 */ + IMX8QM_UART0_RTS_B + IMX8QM_UART0_CTS_B + >; + }; + }; + +}; + +&{/reserved-memory} { + + jh_reserved: jh@0xfdc00000 { + no-map; + reg = <0x0 0xfdc00000 0x0 0x400000>; + }; + + loader_reserved: loader@0xfdb00000 { + no-map; + reg = <0x0 0xfdb00000 0x0 0x00100000>; + }; + + ivshmem_reserved: ivshmem@0xfd900000 { + no-map; + reg = <0x0 0xfd900000 0x0 0x00200000>; + }; + + pci_reserved: pci@0xfd700000 { + no-map; + reg = <0x0 0xfd700000 0x0 0x00200000>; + }; + + /* Decrease if no need such big memory */ + inmate_reserved: inmate@0xdf7000000 { + no-map; + reg = <0x0 0xdf700000 0x0 0x1e000000>; + }; +}; + +&smmu { + /* Jailhouse hypervisor will initialize SMMU and use it. */ + status = "disabled"; +}; + +&usdhc1 { + /* Let U-Boot program SID */ + iommus = <&smmu 0x10 0x7f80>; + /delete-property/ compatible; +}; + +&lpuart2 { + /* Let inmate linux use this for console */ + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-rpmsg.dts new file mode 100644 index 00000000000000..5639b0a8477051 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-rpmsg.dts @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2019 + +#include "imx8qm-mek.dts" + +/delete-node/ &cm41_i2c; + +&i2c_rpbus_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&lsio_gpio4 25 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + fsl,txs-rxm; + status = "okay"; + }; +}; + +&cm41_i2c_lpcg { + status = "disabled"; +}; + +®_can01_en { + status = "disabled"; +}; + +®_can2_en { + status = "disabled"; +}; + +®_can01_stby { + status = "disabled"; +}; + +®_can2_stby { + status = "disabled"; +}; + +&cm41_intmux { + status = "disabled"; +}; + +&can0_lpcg { + status = "disabled"; +}; + +&can1_lpcg { + status = "disabled"; +}; + +&can2_lpcg { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&flexcan3 { + status = "disabled"; +}; + +&flexspi0 { + status = "disabled"; +}; + +&lpuart2 { + status = "disabled"; +}; + +&uart2_lpcg { + status = "disabled"; +}; + +&imx8qm_cm40 { + /* Assume you have partitioned M4, so M4 is ont controled by Linux */ + /delete-property/ power-domains; +}; + +&imx8qm_cm41 { + /* Assume you have partitioned M4, so M4 is ont controled by Linux */ + /delete-property/ power-domains; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-cs42888.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-cs42888.dts new file mode 100644 index 00000000000000..021a63b8e0be39 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-cs42888.dts @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2020 + +#include "imx8qm-mek-rpmsg.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-wm8960 { + status = "disabled"; + }; + + esai0_port: esai-port { + #sound-dai-cells = <0>; + compatible = "fsl,esai-dai"; + + dai-index = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + + power-domains = <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_DMA_2_CH6>, + <&pd IMX_SC_R_DMA_2_CH7>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>; + + clocks = <&esai0_lpcg 1>, <&esai0_lpcg 0>, <&esai0_lpcg 1>, + <&clk_dummy>; + clock-names = "core", "extal", "fsys", "spba"; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + status="okay"; + }; + + sof-audio-cs42888 { + compatible = "simple-audio-card"; + label = "imx-cs42888"; + simple-audio-card,widgets = + "Line", "Line Out Jack", + "Line", "Line In Jack"; + simple-audio-card,routing = + "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "Line In Jack", + "AIN1R", "Line In Jack", + "AIN2L", "Line In Jack", + "AIN2R", "Line In Jack", + "Playback", "ESAI0.OUT"; + status = "okay"; + simple-audio-card,dai-link { + format = "i2s"; + cpu { + sound-dai = <&esai0_port>; + }; + plat { + sound-dai = <&dsp>; + }; + codec { + sound-dai = <&cs42888>; + }; + }; + }; +}; + +&edma0 { + compatible = "fsl,imx8qm-edma"; + reg = <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x592e0000 0x10000>, /* sai1 rx */ + <0x592f0000 0x10000>, /* sai1 tx */ + <0x59350000 0x10000>, + <0x59370000 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <8>; + interrupts = , /* spdif0 */ + , + , /* sai0 */ + , + , /* sai1 */ + , + , + ; + interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx", /* spdif0 */ + "edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */ + "edma2-chan14-rx", "edma2-chan15-tx", /* sai1 */ + "edma2-chan21-tx", /* gpt5 */ + "edma2-chan23-rx"; /* gpt7 */ + power-domains = <&pd IMX_SC_R_DMA_2_CH8>, + <&pd IMX_SC_R_DMA_2_CH9>, + <&pd IMX_SC_R_DMA_2_CH12>, + <&pd IMX_SC_R_DMA_2_CH13>, + <&pd IMX_SC_R_DMA_2_CH14>, + <&pd IMX_SC_R_DMA_2_CH15>, + <&pd IMX_SC_R_DMA_2_CH21>, + <&pd IMX_SC_R_DMA_2_CH23>; + power-domain-names = "edma2-chan8", "edma2-chan9", + "edma2-chan12", "edma2-chan13", + "edma2-chan14", "edma2-chan15", + "edma2-chan21", "edma2-chan23"; + status = "okay"; +}; + +&dsp { + compatible = "fsl,imx8qm-dsp"; + #sound-dai-cells = <0>; + tplg-name = "sof-imx8qxp-cs42888.tplg"; + machine-drv-name = "asoc-simple-card"; + status = "okay"; + power-domains = <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>, + <&pd IMX_SC_R_IRQSTR_DSP>; + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + mboxes = <&lsio_mu13 2 0>, + <&lsio_mu13 2 1>, + <&lsio_mu13 3 0>, + <&lsio_mu13 3 1>; +}; + +&amix { + status = "disabled"; +}; + +&esai0 { + status = "disabled"; +}; + +&asrc0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&wm8960 { + status = "disabled"; +}; + +&cs42888 { + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-wm8960.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-wm8960.dts new file mode 100644 index 00000000000000..24f20cf535344c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-wm8960.dts @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2018 + +#include "imx8qm-mek-rpmsg.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-wm8960 { + status = "disabled"; + }; + + sai1_port: sai-port { + #sound-dai-cells = <0>; + compatible = "fsl,sai-dai"; + + dai-index = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + + power-domains = <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_DMA_2_CH14>, + <&pd IMX_SC_R_DMA_2_CH15>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>; + + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + clocks = <&sai1_lpcg 1>, <&clk_dummy>, <&sai1_lpcg 0>, + <&clk_dummy>, <&clk_dummy>; + assigned-clocks = <&acm IMX_ADMA_ACM_SAI1_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>, + <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + status="okay"; + }; + + sof-sound-wm8960 { + compatible = "simple-audio-card"; + label = "wm8960-audio"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + hp-det-gpio = <&lsio_gpio1 0 0>; + mic-det-gpio = <&lsio_gpio1 0 0>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Speaker", "Ext Spk", + "Microphone", "Mic Jack"; + simple-audio-card,audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Mic Jack", + "RINPUT2", "Mic Jack", + "Playback", "SAI1.OUT", + "SAI1.IN", "Capture"; + simple-audio-card,dai-link { + format = "i2s"; + cpu { + sound-dai = <&sai1_port>; + }; + plat { + sound-dai = <&dsp>; + }; + sndcodec: codec { + sound-dai = <&wm8960>; + }; + }; + }; +}; + +&edma0 { + compatible = "fsl,imx8qm-edma"; + reg = <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x59350000 0x10000>, + <0x59370000 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <6>; + interrupts = , /* spdif0 */ + , + , /* sai0 */ + , + , + ; + interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx", /* spdif0 */ + "edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */ + "edma2-chan21-tx", /* gpt5 */ + "edma2-chan23-rx"; /* gpt7 */ + + power-domains = <&pd IMX_SC_R_DMA_2_CH8>, + <&pd IMX_SC_R_DMA_2_CH9>, + <&pd IMX_SC_R_DMA_2_CH12>, + <&pd IMX_SC_R_DMA_2_CH13>, + <&pd IMX_SC_R_DMA_2_CH21>, + <&pd IMX_SC_R_DMA_2_CH23>; + power-domain-names = "edma2-chan8", "edma2-chan9", + "edma2-chan12", "edma2-chan13", + "edma2-chan21", "edma2-chan23"; + status = "okay"; +}; + +&dsp { + compatible = "fsl,imx8qm-dsp"; + #sound-dai-cells = <0>; + tplg-name = "sof-imx8qxp-wm8960.tplg"; + machine-drv-name = "asoc-simple-card"; + status = "okay"; + power-domains = <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>, + <&pd IMX_SC_R_IRQSTR_DSP>; + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + mboxes = <&lsio_mu13 2 0>, + <&lsio_mu13 2 1>, + <&lsio_mu13 3 0>, + <&lsio_mu13 3 1>; +}; + +&wm8960 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&amix { + status = "disabled"; +}; + +&esai0 { + status = "disabled"; +}; + +&asrc0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&cs42888 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts new file mode 100755 index 00000000000000..85b63a463aea1e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -0,0 +1,1830 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng + */ + +/dts-v1/; + +#include +#include "imx8qm.dtsi" + +/ { + model = "Freescale i.MX8QM MEK"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + + chosen { + stdout-path = &lpuart0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + }; + + brcmfmac: brcmfmac { + compatible = "cypress,brcmfmac"; + pinctrl-names = "init", "idle", "default"; + pinctrl-0 = <&pinctrl_wifi_init>; + pinctrl-1 = <&pinctrl_wifi_init>; + pinctrl-2 = <&pinctrl_wifi>; + }; + + lvds_backlight0: lvds_backlight@0 { + compatible = "pwm-backlight"; + pwms = <&pwm_lvds0 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + lvds_backlight1: lvds_backlight@1 { + compatible = "pwm-backlight"; + pwms = <&pwm_lvds1 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_modem_reset>; + pinctrl-1 = <&pinctrl_modem_reset_sleep>; + reset-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + cbtl04gp { + compatible = "nxp,cbtl04gp"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec_mux>; + switch-gpios = <&lsio_gpio4 6 GPIO_ACTIVE_LOW>; + reset-gpios = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + orientation-switch; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + decoder_boot: decoder_boot@0x84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + }; + encoder_boot: encoder_boot@0x86000000 { + no-map; + reg = <0 0x86000000 0 0x400000>; + }; + /* + * reserved-memory layout + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90200000 0 0x200000>; + }; + decoder_rpc: decoder_rpc@0x92000000 { + no-map; + reg = <0 0x92000000 0 0x200000>; + }; + encoder_rpc: encoder_rpc@0x92200000 { + no-map; + reg = <0 0x92200000 0 0x200000>; + }; + dsp_reserved: dsp@0x92400000 { + no-map; + reg = <0 0x92400000 0 0x2000000>; + }; + encoder_reserved: encoder_reserved@0x94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + }; + ts_boot: ts_boot@0x95000000 { + no-map; + reg = <0 0x95000000 0 0x400000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_wlreg_on>; + pinctrl-1 = <&pinctrl_wlreg_on_sleep>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&lsio_gpio1 13 0>; + enable-active-high; + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <4800>; + enable-active-high; + }; + + reg_can01_en: regulator-can01-gen { + compatible = "regulator-fixed"; + regulator-name = "can01-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can2_en: regulator-can2-gen { + compatible = "regulator-fixed"; + regulator-name = "can2-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can01_stby: regulator-can01-stby { + compatible = "regulator-fixed"; + regulator-name = "can01-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can01_en>; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + regulator-name = "can2-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can2_en>; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_audio: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&cs42888>; + asrc-controller = <&asrc0>; + status = "okay"; + }; + + sound-wm8960 { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai1>; + audio-codec = <&wm8960>; + codec-master; + /* + * hp-det = ; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <2 0>; + hp-det-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; + mic-det-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Main MIC", + "RINPUT2", "Main MIC", + "Mic Jack", "MICB", + "Main MIC", "MICB", + "Playback", "CPU-Playback", + "CPU-Capture", "Capture"; + }; + + imx8qm_cm40: imx8qm_cm4@0 { + compatible = "fsl,imx8qm-cm4"; + rsc-da = <0x90000000>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu5 0 1 + &lsio_mu5 1 1 + &lsio_mu5 3 1>; + mub-partition = <3>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>, + <&vdev1vring0>, <&vdev1vring1>; + core-index = <0>; + core-id = ; + status = "okay"; + power-domains = <&pd IMX_SC_R_M4_0_PID0>, + <&pd IMX_SC_R_M4_0_MU_1A>; + }; + + imx8qm_cm41: imx8x_cm4@1 { + compatible = "fsl,imx8qm-cm4"; + rsc-da = <0x90100000>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu6 0 1 + &lsio_mu6 1 1 + &lsio_mu6 3 1>; + mub-partition = <4>; + memory-region = <&vdev2vring0>, <&vdev2vring1>, <&vdevbuffer>, + <&vdev3vring0>, <&vdev3vring1>; + core-index = <1>; + core-id = ; + status = "okay"; + power-domains = <&pd IMX_SC_R_M4_1_PID0>, + <&pd IMX_SC_R_M4_1_MU_1A>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + vdev0vring0: vdev0vring0@90000000 { + compatible = "shared-dma-pool"; + reg = <0 0x90000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@90008000 { + compatible = "shared-dma-pool"; + reg = <0 0x90008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@90010000 { + compatible = "shared-dma-pool"; + reg = <0 0x90010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@90018000 { + compatible = "shared-dma-pool"; + reg = <0 0x90018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer { + compatible = "shared-dma-pool"; + reg = <0 0x90400000 0 0x100000>; + no-map; + }; + + vdev2vring0: vdev0vring0@90100000 { + compatible = "shared-dma-pool"; + reg = <0 0x90100000 0 0x8000>; + no-map; + }; + + vdev2vring1: vdev0vring1@90108000 { + compatible = "shared-dma-pool"; + reg = <0 0x90108000 0 0x8000>; + no-map; + }; + + vdev3vring0: vdev1vring0@90110000 { + compatible = "shared-dma-pool"; + reg = <0 0x90110000 0 0x8000>; + no-map; + }; + + vdev3vring1: vdev1vring1@90118000 { + compatible = "shared-dma-pool"; + reg = <0 0x90118000 0 0x8000>; + no-map; + }; + }; +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cm41_i2c { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cm41_i2c>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&lsio_gpio4 25 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + fsl,txs-rxm; + status = "okay"; + }; +}; + +&cm41_intmux { + status = "okay"; +}; + +&dc0_pc { + status = "okay"; +}; + +&dc0_prg1 { + status = "okay"; +}; + +&dc0_prg2 { + status = "okay"; + +}; + +&dc0_prg3 { + status = "okay"; +}; + +&dc0_prg4 { + status = "okay"; +}; + +&dc0_prg5 { + status = "okay"; +}; + +&dc0_prg6 { + status = "okay"; +}; + +&dc0_prg7 { + status = "okay"; +}; + +&dc0_prg8 { + status = "okay"; +}; + +&dc0_prg9 { + status = "okay"; +}; + +&dc0_dpr1_channel1 { + status = "okay"; +}; + +&dc0_dpr1_channel2 { + status = "okay"; +}; + +&dc0_dpr1_channel3 { + status = "okay"; +}; + +&dc0_dpr2_channel1 { + status = "okay"; +}; + +&dc0_dpr2_channel2 { + status = "okay"; +}; + +&dc0_dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&dsp { + compatible = "fsl,imx8qm-dsp-v1"; + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + fsl,txm-rxs; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&sai6 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai6_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai7 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai7_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&pwm_lvds0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_lvds0>; + status = "okay"; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c0_mipi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi0_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge0: adv7535@3d { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port@0 { + reg = <0>; + adv7535_0_in: endpoint { + remote-endpoint = <&mipi0_adv_out>; + }; + }; + }; +}; + +&mipi0_dphy { + status = "okay"; +}; + +&mipi0_dsi_host { + status = "okay"; + + ports { + port@1 { + reg = <1>; + mipi0_adv_out: endpoint { + remote-endpoint = <&adv7535_0_in>; + }; + }; + }; +}; + +&i2c0_mipi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi1_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge1: adv7535@3d { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port@0 { + reg = <0>; + adv7535_1_in: endpoint { + remote-endpoint = <&mipi1_adv_out>; + }; + }; + }; +}; + +&mipi1_dphy { + status = "okay"; +}; + +&mipi1_dsi_host { + status = "okay"; + + ports { + port@1 { + reg = <1>; + mipi1_adv_out: endpoint { + remote-endpoint = <&adv7535_1_in>; + }; + }; + }; +}; + +&dc1_pc { + status = "okay"; +}; + +&dc1_prg1 { + status = "okay"; +}; + +&dc1_prg2 { + status = "okay"; + +}; + +&dc1_prg3 { + status = "okay"; +}; + +&dc1_prg4 { + status = "okay"; +}; + +&dc1_prg5 { + status = "okay"; +}; + +&dc1_prg6 { + status = "okay"; +}; + +&dc1_prg7 { + status = "okay"; +}; + +&dc1_prg8 { + status = "okay"; +}; + +&dc1_prg9 { + status = "okay"; +}; + +&dc1_dpr1_channel1 { + status = "okay"; +}; + +&dc1_dpr1_channel2 { + status = "okay"; +}; + +&dc1_dpr1_channel3 { + status = "okay"; +}; + +&dc1_dpr2_channel1 { + status = "okay"; +}; + +&dc1_dpr2_channel2 { + status = "okay"; +}; + +&dc1_dpr2_channel3 { + status = "okay"; +}; + +&dpu2 { + status = "okay"; +}; + +&pwm_lvds1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_lvds1>; + status = "okay"; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&lpspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>; + cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <30000000>; + }; +}; + +&emvsim0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sim0>; + status = "okay"; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "okay"; +}; + +&lpuart2 { /* Dbg console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "disabled"; +}; + +&lpuart3 { /* MKbus */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "disabled"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can01_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can01_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + nvmem-cells = <&fec_mac0>; + nvmem-cell-names = "mac-address"; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + nvmem-cells = <&fec_mac1>; + nvmem-cell-names = "mac-address"; + fsl,rgmii_rxc_dly; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&pciea{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + disable-gpio = <&lsio_gpio4 9 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + epdev_on-supply = <&epdev_on>; + reserved-region = <&rpmsg_reserved>; + status = "okay"; +}; + +&pcieb{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + status = "okay"; +}; + +&rpmsg0{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + memory-region = <&vdevbuffer>; + status = "disabled"; +}; + +&rpmsg1{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90100000 0x0 0x20000>; + memory-region = <&vdevbuffer>; + status = "disabled"; +}; + +&sata { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sata>; + clkreq-gpio = <&lsio_gpio4 30 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usb3phynop1 { + status = "okay"; +}; + +&usbotg3 { + dr_mode = "otg"; + extcon = <&ptn5110>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <11 2>; + }; + + fxos8700@1e { + compatible = "fsl,fxos8700"; + reg = <0x1e>; + interrupt-open-drain; + }; + + fxas2100x@20 { + compatible = "fsl,fxas2100x"; + reg = <0x20>; + interrupt-open-drain; + }; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + interrupt-open-drain; + }; + + ptn5110: tcpc@51 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x51>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + usb_con1: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "source"; + data-role = "dual"; + source-pdos = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; +}; + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; + + m2m_device { + status = "okay"; + }; +}; + +&isi_1 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_2 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_3 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_4 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_5 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_6 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_7 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&irqsteer_csi0 { + status = "okay"; +}; + +&irqsteer_csi1 { + status = "okay"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 1 MIPI CSI-2 (CSIS1) */ + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&max9286_1_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&jpegdec { + status = "okay"; +}; + +&jpegenc { + status = "okay"; +}; + +&i2c_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_mipi_csi0>; + clock-frequency = <100000>; + status = "okay"; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&lsio_gpio1 27 GPIO_ACTIVE_HIGH>; + virtual-channel; + status = "okay"; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c_mipi_csi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_mipi_csi1>; + clock-frequency = <100000>; + status = "okay"; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi1>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_HIGH>; + virtual-channel; + status = "okay"; + port { + max9286_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; + +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c + IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c + IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c + >; + }; + + pinctrl_cm41_i2c: cm41i2cgrp { + fsl,pins = < + IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA 0x0600004c + IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL 0x0600004c + >; + }; + + pinctrl_adc0: adc0grp { + fsl,pins = < + IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060 + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 + IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 + IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins = < + IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 + IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021 + IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c + IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0xc600004c + IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 0xc600004c + >; + }; + + pinctrl_lpspi2: lpspi2grp { + fsl,pins = < + IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x0600004c + IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x0600004c + IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x0600004c + IMX8QM_SPI2_CS0_DMA_SPI2_CS0 0x0600004c + >; + }; + + pinctrl_lpspi2_cs: lpspi2cs { + fsl,pins = < + IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x21 + >; + }; + + pinctrl_sim0: sim0grp { + fsl,pins = < + IMX8QM_SIM0_CLK_DMA_SIM0_CLK 0xc0000021 + IMX8QM_SIM0_IO_DMA_SIM0_IO 0xc2000021 + IMX8QM_SIM0_PD_DMA_SIM0_PD 0xc0000021 + IMX8QM_SIM0_POWER_EN_DMA_SIM0_POWER_EN 0xc0000021 + IMX8QM_SIM0_RST_DMA_SIM0_RST 0xc0000021 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 + IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 + IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 + IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020 + IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020 + IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 + >; + }; + + pinctrl_pwm_lvds0: pwmlvds0grp { + fsl,pins = < + IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_pwm_lvds1: pwmlvds1grp { + fsl,pins = < + IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_modem_reset: modemresetgrp { + fsl,pins = < + IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x06000021 + >; + }; + + pinctrl_modem_reset_sleep: modemreset_sleepgrp { + fsl,pins = < + IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x07800021 + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 + IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021 + >; + }; + + pinctrl_pcieb: pciebgrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 + IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 + >; + }; + + pinctrl_sata: satagrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x06000021 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0x06000040 + IMX8QM_SAI1_RXC_AUD_SAI1_RXC 0x06000040 + IMX8QM_SAI1_RXFS_AUD_SAI1_RXFS 0x06000040 + IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0x06000060 + IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0x06000040 + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 + >; + }; + + pinctrl_typec_mux: typecmuxgrp { + fsl,pins = < + IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60 + IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 { + fsl,pins = < + IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 + IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_i2c_mipi_csi1: i2c_mipi_csi1 { + fsl,pins = < + IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL 0xc2000020 + IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_mipi_csi0: mipi_csi0 { + fsl,pins = < + IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0xC0000041 + IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0xC0000041 + IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 + >; + }; + + pinctrl_mipi_csi1: mipi_csi1 { + fsl,pins = < + IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0xC0000041 + IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0xC0000041 + IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xC0000041 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_wifi: wifigrp{ + fsl,pins = < + IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 + >; + }; + + pinctrl_wifi_init: wifi_initgrp{ + fsl,pins = < + /* reserve pin init/idle_state to support multiple wlan cards */ + >; + }; + + pinctrl_wlreg_on: wlregongrp{ + fsl,pins = < + IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000 + >; + }; + + pinctrl_wlreg_on_sleep: wlregon_sleepgrp{ + fsl,pins = < + IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x07800000 + >; + }; + + pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x00000020 + >; + }; + + pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x00000020 + >; + }; + +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&gpu_3d0{ + status = "okay"; +}; + +&gpu_3d1{ + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&mu_m0{ + interrupts = ; +}; + +&mu1_m0{ + interrupts = ; +}; + +&mu2_m0{ + interrupts = ; + status = "okay"; +}; + +&mu3_m0{ + interrupts = ; + status = "okay"; +}; + +&vpu_decoder { + compatible = "nxp,imx8qm-b0-vpudec"; + boot-region = <&decoder_boot>; + rpc-region = <&decoder_rpc>; + reg-csr = <0x2d080000>; + core_type = <2>; + status = "okay"; +}; + +&vpu_ts { + compatible = "nxp,imx8qm-b0-vpu-ts"; + boot-region = <&ts_boot>; + reg-csr = <0x2d0b0000>; + status = "okay"; +}; + +&vpu_encoder { + compatible = "nxp,imx8qm-b0-vpuenc"; + boot-region = <&encoder_boot>; + rpc-region = <&encoder_rpc>; + reserved-region = <&encoder_reserved>; + reg-rpc-system = <0x40000000>; + resolution-max = <1920 1920>; + power-domains = <&pd IMX_SC_R_VPU_ENC_0>, <&pd IMX_SC_R_VPU_ENC_1>, + <&pd IMX_SC_R_VPU>; + power-domain-names = "vpuenc1", "vpuenc2", "vpu"; + mbox-names = "enc1_tx0", "enc1_tx1", "enc1_rx", + "enc2_tx0", "enc2_tx1", "enc2_rx"; + mboxes = <&mu1_m0 0 0 + &mu1_m0 0 1 + &mu1_m0 1 0 + &mu2_m0 0 0 + &mu2_m0 0 1 + &mu2_m0 1 0>; + status = "okay"; + + vpu_enc_core0: core0@1020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x1020000 0x20000>; + reg-csr = <0x1090000 0x10000>; + interrupts = ; + fsl,vpu_ap_mu_id = <17>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; + + vpu_enc_core1: core1@1040000 { + compatible = "fsl,imx8-mu2-vpu-m0"; + reg = <0x1040000 0x20000>; + reg-csr = <0x10A0000 0x10000>; + interrupts = ; + fsl,vpu_ap_mu_id = <18>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-pcieax2pciebx1.dts b/arch/arm64/boot/dts/freescale/imx8qm-pcieax2pciebx1.dts new file mode 100644 index 00000000000000..22738c54673aa3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-pcieax2pciebx1.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include +#include "imx8qm-mek.dts" + +/* + * Add the PCIeA x2 lanes and PCIeB x1 lane usecase + * hsio-cfg = + * NOTE: In this case, the HSIO nodes contained + * hsio-cfg = would be re-configured. + */ +&pciea{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + disable-gpio = <&lsio_gpio4 9 GPIO_ACTIVE_LOW>; + reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + epdev_on-supply = <&epdev_on>; + num-lanes = <2>; + clocks = <&pciea_lpcg 0>, + <&pciea_lpcg 1>, + <&pciea_lpcg 2>, + <&phyx2_lpcg 0>, + <&phyx2_crr0_lpcg 0>, + <&pciea_crr2_lpcg 0>, + <&misc_crr5_lpcg 0>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", + "pcie_phy", "phy_per","pcie_per", "misc_per"; + hsio-cfg = ; + status = "okay"; +}; + +&pcieb{ + ext_osc = <1>; + clocks = <&pcieb_lpcg 0>, + <&pcieb_lpcg 1>, + <&pcieb_lpcg 2>, + <&phyx1_lpcg 0>, + <&phyx2_lpcg 0>, + <&phyx1_crr1_lpcg 0>, + <&pcieb_crr3_lpcg 0>, + <&pciea_crr2_lpcg 0>, + <&misc_crr5_lpcg 0>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", + "pcie_phy", "pcie_phy_pclk", "phy_per", + "pcie_per", "pciex2_per", "misc_per"; + power-domains = <&pd IMX_SC_R_PCIE_B>, + <&pd IMX_SC_R_PCIE_A>, + <&pd IMX_SC_R_SERDES_0>, + <&pd IMX_SC_R_SERDES_1>, + <&pd IMX_SC_R_HSIO_GPIO>; + power-domain-names = "pcie", "pcie_per", "pcie_phy", + "pcie_serdes", "hsio_gpio"; + hsio-cfg = ; + status = "okay"; +}; + +&sata { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi new file mode 100644 index 00000000000000..708f2191005314 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +/delete-node/ &acm; +/delete-node/ &sai4; +/delete-node/ &sai5; +/delete-node/ &sai4_lpcg; +/delete-node/ &sai5_lpcg; + +/* edma2 called in imx8qm RM with the same address in edma0 of imx8qxp */ +&edma0{ + reg = <0x59200000 0x10000>, /* asrc0 */ + <0x59210000 0x10000>, + <0x59220000 0x10000>, + <0x59230000 0x10000>, + <0x59240000 0x10000>, + <0x59250000 0x10000>, + <0x59260000 0x10000>, /* esai0 rx */ + <0x59270000 0x10000>, /* esai0 tx */ + <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592A0000 0x10000>, /* spdif1 rx */ + <0x592B0000 0x10000>, /* spdif1 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x592e0000 0x10000>, /* sai1 rx */ + <0x592f0000 0x10000>, /* sai1 tx */ + <0x59300000 0x10000>, /* sai2 rx */ + <0x59310000 0x10000>, /* sai3 rx */ + <0x59320000 0x10000>, /* sai4 rx */ + <0x59330000 0x10000>; /* sai5 tx */ + dma-channels = <20>; + interrupts = , /* asrc0 */ + , + , + , + , + , + , /* esai0 */ + , + , /* spdif0 */ + , + , /* spdif1 */ + , + , /* sai0 */ + , + , /* sai1 */ + , + , /* sai2 */ + , /* sai3 */ + , /* sai4 */ + ; /* sai5 */ + interrupt-names = "edma2-chan0-rx", "edma2-chan1-rx", /* asrc0 */ + "edma2-chan2-rx", "edma2-chan3-tx", + "edma2-chan4-tx", "edma2-chan5-tx", + "edma2-chan6-rx", "edma2-chan7-tx", /* esai0 */ + "edma2-chan8-rx", "edma2-chan9-tx", /* spdif0 */ + "edma2-chan10-rx", "edma2-chan11-tx", /* spdif1 */ + "edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */ + "edma2-chan14-rx", "edma2-chan15-tx", /* sai1 */ + "edma2-chan16-rx", "edma2-chan17-tx", /* sai2, dai3 */ + "edma2-chan18-rx", "edma2-chan19-tx"; /* sai4, sai5 */ + power-domains = <&pd IMX_SC_R_DMA_2_CH0>, + <&pd IMX_SC_R_DMA_2_CH1>, + <&pd IMX_SC_R_DMA_2_CH2>, + <&pd IMX_SC_R_DMA_2_CH3>, + <&pd IMX_SC_R_DMA_2_CH4>, + <&pd IMX_SC_R_DMA_2_CH5>, + <&pd IMX_SC_R_DMA_2_CH6>, + <&pd IMX_SC_R_DMA_2_CH7>, + <&pd IMX_SC_R_DMA_2_CH8>, + <&pd IMX_SC_R_DMA_2_CH9>, + <&pd IMX_SC_R_DMA_2_CH10>, + <&pd IMX_SC_R_DMA_2_CH11>, + <&pd IMX_SC_R_DMA_2_CH12>, + <&pd IMX_SC_R_DMA_2_CH13>, + <&pd IMX_SC_R_DMA_2_CH14>, + <&pd IMX_SC_R_DMA_2_CH15>, + <&pd IMX_SC_R_DMA_2_CH16>, + <&pd IMX_SC_R_DMA_2_CH17>, + <&pd IMX_SC_R_DMA_2_CH18>, + <&pd IMX_SC_R_DMA_2_CH19>; + power-domain-names = "edma2-chan0", "edma2-chan1", + "edma2-chan2", "edma2-chan3", + "edma2-chan4", "edma2-chan5", + "edma2-chan6", "edma2-chan7", + "edma2-chan8", "edma2-chan9", + "edma2-chan10", "edma2-chan11", + "edma2-chan12", "edma2-chan13", + "edma2-chan14", "edma2-chan15", + "edma2-chan16", "edma2-chan17", + "edma2-chan18", "edma2-chan19"; +}; + +/* edma3 called in imx8qm RM with the same address in edma1 of imx8qxp */ +&edma1{ + reg = <0x59A00000 0x10000>, /* asrc1 */ + <0x59A10000 0x10000>, + <0x59A20000 0x10000>, + <0x59A30000 0x10000>, + <0x59A40000 0x10000>, + <0x59A50000 0x10000>, + <0x59A80000 0x10000>, /* sai6 rx */ + <0x59A90000 0x10000>, /* sai6 tx */ + <0x59AA0000 0x10000>; /* sai7 tx */ + dma-channels = <9>; + interrupts = , /* asrc1 */ + , + , + , + , + , + , /* sai6 */ + , + ; /* sai7 */ + interrupt-names = "edma3-chan0-rx", "edma3-chan1-rx", /* asrc1 */ + "edma3-chan2-rx", "edma3-chan3-tx", + "edma3-chan4-tx", "edma3-chan5-tx", + "edma3-chan8-rx", "edma3-chan9-tx", /* sai6 */ + "edma3-chan10-tx"; /* sai7 */ + power-domains = <&pd IMX_SC_R_DMA_3_CH0>, + <&pd IMX_SC_R_DMA_3_CH1>, + <&pd IMX_SC_R_DMA_3_CH2>, + <&pd IMX_SC_R_DMA_3_CH3>, + <&pd IMX_SC_R_DMA_3_CH4>, + <&pd IMX_SC_R_DMA_3_CH5>, + <&pd IMX_SC_R_DMA_3_CH8>, + <&pd IMX_SC_R_DMA_3_CH9>, + <&pd IMX_SC_R_DMA_3_CH10>; + power-domain-names = "edma3-chan0", "edma3-chan1", + "edma3-chan2", "edma3-chan3", + "edma3-chan4", "edma3-chan5", + "edma3-chan8", "edma3-chan9", + "edma3-chan10"; +}; + +&asrc0 { + clocks = <&asrc0_lpcg 0>, + <&asrc0_lpcg 1>, + <&aud_pll_div0_lpcg 0>, + <&aud_pll_div1_lpcg 0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_ASRC_0>; +}; + +&esai0 { + power-domains = <&pd IMX_SC_R_ESAI_0>; +}; + +&spdif0 { + power-domains = <&pd IMX_SC_R_SPDIF_0>; +}; + +&spdif1 { + power-domains = <&pd IMX_SC_R_SPDIF_1>; +}; + +&sai0 { + power-domains = <&pd IMX_SC_R_SAI_0>; +}; + +&sai1 { + power-domains = <&pd IMX_SC_R_SAI_1>; +}; + +&sai2 { + power-domains = <&pd IMX_SC_R_SAI_2>; +}; + +&sai3 { + power-domains = <&pd IMX_SC_R_SAI_3>; +}; + +&asrc1 { + clocks = <&asrc1_lpcg 0>, + <&asrc1_lpcg 1>, + <&aud_pll_div0_lpcg 0>, + <&aud_pll_div1_lpcg 0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_ASRC_1>; +}; + +&amix { + dais = <&sai6>, <&sai7>; +}; + +&asrc0_lpcg { + clocks = <&audio_ipg_clk>, + <&audio_ipg_clk>; + bit-offset = <0 8>; + clock-output-names = "asrc0_lpcg_ipg_clk", + "asrc0_lpcg_mem_clk"; +}; + +&esai0_lpcg { + bit-offset = <16 0>; + clock-output-names = "esai0_lpcg_extal_clk", + "esai0_lpcg_ipg_clk"; +}; + +&spdif0_lpcg { + bit-offset = <20 16>; + clock-output-names = "spdif0_lpcg_tx_clk", + "spdif0_lpcg_gclkw"; +}; + +&spdif1_lpcg { + bit-offset = <20 16>; + clock-output-names = "spdif1_lpcg_tx_clk", + "spdif1_lpcg_gclkw"; +}; + +&sai0_lpcg { + bit-offset = <16 0>; + clock-output-names = "sai0_lpcg_mclk", + "sai0_lpcg_ipg_clk"; +}; + +&sai1_lpcg { + bit-offset = <16 0>; + clock-output-names = "sai1_lpcg_mclk", + "sai1_lpcg_ipg_clk"; +}; + +&sai2_lpcg { + bit-offset = <16 0>; + clock-output-names = "sai2_lpcg_mclk", + "sai2_lpcg_ipg_clk"; +}; + +&sai3_lpcg { + bit-offset = <16 0>; + clock-output-names = "sai3_lpcg_mclk", + "sai3_lpcg_ipg_clk"; +}; + +&asrc1_lpcg { + clocks = <&audio_ipg_clk>, + <&audio_ipg_clk>; + bit-offset = <0 8>; + clock-output-names = "asrc1_lpcg_ipg_clk", + "asrc1_lpcg_mem_clk"; +}; + +&mqs0_lpcg { + bit-offset = <16 0>; + clock-output-names = "mqs0_lpcg_mclk", + "mqs0_lpcg_ipg_clk"; +}; + +&dsp_lpcg { + status = "disabled"; +}; + +&dsp_ram_lpcg { + status = "disabled"; +}; + +&audio_subsys { + acm: acm@59e00000 { + compatible = "nxp,imx8qm-acm"; + reg = <0x59e00000 0x1D0000>; + #clock-cells = <1>; + power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_MCLK_OUT_0>, + <&pd IMX_SC_R_MCLK_OUT_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_ASRC_1>, + <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_ESAI_1>, + <&pd IMX_SC_R_SAI_0>, + <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_SAI_2>, + <&pd IMX_SC_R_SAI_3>, + <&pd IMX_SC_R_SAI_4>, + <&pd IMX_SC_R_SAI_5>, + <&pd IMX_SC_R_SAI_6>, + <&pd IMX_SC_R_SAI_7>, + <&pd IMX_SC_R_SPDIF_0>, + <&pd IMX_SC_R_SPDIF_1>, + <&pd IMX_SC_R_MQS_0>; + }; + + sai4: sai@59080000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59080000 0x10000>; + interrupts = ; + clocks = <&sai4_lpcg 1>, + <&clk_dummy>, + <&sai4_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma0 18 0 1>; + fsl,dataline = <0 0xf 0x0>; + power-domains = <&pd IMX_SC_R_SAI_4>; + status = "disabled"; + }; + + sai5: sai@59090000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59090000 0x10000>; + interrupts = ; + clocks = <&sai5_lpcg 1>, + <&clk_dummy>, + <&sai5_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "tx"; + dmas = <&edma0 19 0 0>; + fsl,dataline = <0 0x0 0xf>; + power-domains = <&pd IMX_SC_R_SAI_5>; + status = "disabled"; + }; + + esai1: esai@59810000 { + compatible = "fsl,imx8qm-esai", "fsl,imx6ull-esai"; + reg = <0x59810000 0x10000>; + interrupts = ; + clocks = <&esai1_lpcg 1>, + <&esai1_lpcg 0>, + <&esai1_lpcg 1>, + <&clk_dummy>; + clock-names = "core", "extal", "fsys", "spba"; + dmas = <&edma1 6 0 1>, <&edma1 7 0 0>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_ESAI_1>; + status = "disabled"; + }; + + sai6: sai@59820000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59820000 0x10000>; + interrupts = ; + clocks = <&sai6_lpcg 1>, + <&clk_dummy>, + <&sai6_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma1 8 0 1>, <&edma1 9 0 0>; + power-domains = <&pd IMX_SC_R_SAI_6>; + status = "disabled"; + }; + + sai7: sai@59830000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59830000 0x10000>; + interrupts = ; + clocks = <&sai7_lpcg 1>, + <&clk_dummy>, + <&sai7_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "tx"; + dmas = <&edma1 10 0 0>; + power-domains = <&pd IMX_SC_R_SAI_7>; + status = "disabled"; + }; + + sai4_lpcg: clock-controller@59480000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59480000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <16 0>; + clock-output-names = "sai4_lpcg_mclk", + "sai4_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_4>; + status = "disabled"; + }; + + sai5_lpcg: clock-controller@59490000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59490000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <16 0>; + clock-output-names = "sai5_lpcg_mclk", + "sai5_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_5>; + status = "disabled"; + }; + + esai1_lpcg: clock-controller@59c10000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c10000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_ESAI1_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <16 0>; + clock-output-names = "esai1_lpcg_extal_clk", + "esai1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ESAI_1>; + }; + + sai6_lpcg: clock-controller@59c20000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c20000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <16 0>; + clock-output-names = "sai6_lpcg_mclk", + "sai6_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_6>; + }; + + sai7_lpcg: clock-controller@59c30000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c30000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <16 0>; + clock-output-names = "sai7_lpcg_mclk", + "sai7_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_7>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi new file mode 100644 index 00000000000000..00ebdc6fc875de --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +&fec1 { + compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec"; + iommus = <&smmu 0x12 0x7f80>; +}; + +&fec2 { + compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec"; + iommus = <&smmu 0x12 0x7f80>; +}; + +&usdhc1 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc"; + iommus = <&smmu 0x11 0x7f80>; +}; + +&usdhc2 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc"; + iommus = <&smmu 0x11 0x7f80>; +}; + +&usdhc3 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc"; + iommus = <&smmu 0x11 0x7f80>; +}; + +&usbotg3 { + iommus = <&smmu 0x4 0x7f80>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi new file mode 100644 index 00000000000000..e0c93f2aeddc03 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019 NXP + */ + +&dpu1 { + compatible = "fsl,imx8qm-dpu"; + + dpu1_disp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + dpu1_disp0_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_disp>; + }; + + dpu1_disp0_mipi0: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi0_dsi_in>; + }; + }; + + dpu1_disp1: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + dpu1_disp1_ldb1_ch0: endpoint@0 { + remote-endpoint = <&ldb1_ch0>; + }; + + dpu1_disp1_ldb1_ch1: endpoint@1 { + remote-endpoint = <&ldb1_ch1>; + }; + }; +}; + +&dpu2 { + compatible = "fsl,imx8qm-dpu"; + + dpu2_disp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + dpu2_disp0_mipi1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_dsi_in>; + }; + + }; + + dpu2_disp1: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + dpu2_disp1_ldb2_ch0: endpoint@0 { + remote-endpoint = <&ldb2_ch0>; + }; + + dpu2_disp1_ldb2_ch1: endpoint@1 { + remote-endpoint = <&ldb2_ch1>; + }; + }; +}; + +/ { + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu1_disp0>, <&dpu1_disp1>, + <&dpu2_disp0>, <&dpu2_disp1>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-ddr.dtsi new file mode 100644 index 00000000000000..e47b12a765560f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-ddr.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +&ddr_subsys { + ddr_pmu1: ddr-pmu@5c120000 { + compatible = "fsl,imx8-ddr-pmu"; + reg = <0x5c120000 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + }; +}; + +&ddr_pmu0 { + interrupts = ; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi new file mode 100644 index 00000000000000..b9b364b0ecc89b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + * Dong Aisheng + */ + +&dma_subsys { + uart4_lpcg: clock-controller@5a4a0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a4a0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart4_lpcg_baud_clk", + "uart4_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_UART_4>; + }; + + can1_lpcg: clock-controller@5ace0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ace0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>, <&dma_ipg_clk>; + bit-offset = <0 16 20>; + clock-output-names = "can1_lpcg_pe_clk", + "can1_lpcg_ipg_clk", + "can1_lpcg_chi_clk"; + power-domains = <&pd IMX_SC_R_CAN_1>; + }; + + can2_lpcg: clock-controller@5acf0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5acf0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>, <&dma_ipg_clk>; + bit-offset = <0 16 20>; + clock-output-names = "can2_lpcg_pe_clk", + "can2_lpcg_ipg_clk", + "can2_lpcg_chi_clk"; + power-domains = <&pd IMX_SC_R_CAN_2>; + }; +}; + +&flexcan1 { + fsl,clk-source = <1>; +}; + +&flexcan2 { + clocks = <&can1_lpcg 1>, + <&can1_lpcg 0>; + assigned-clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>; + fsl,clk-source = <1>; +}; + +&flexcan3 { + clocks = <&can2_lpcg 1>, + <&can2_lpcg 0>; + assigned-clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>; + fsl,clk-source = <1>; +}; + +&lpspi2 { + compatible = "fsl,imx8qm-lpspi", "fsl,imx7ulp-spi"; +}; + +/* edma0 called in imx8qm RM with the same address in edma2 of imx8qxp */ +&edma2 { + reg = <0x5a200000 0x10000>, /* channel0 LPSPI0 rx */ + <0x5a210000 0x10000>, /* channel1 LPSPI0 tx */ + <0x5a260000 0x10000>, /* channel6 LPSPI3 rx */ + <0x5a270000 0x10000>, /* channel7 LPSPI3 tx */ + <0x5a2c0000 0x10000>, /* channel12 UART0 rx */ + <0x5a2d0000 0x10000>, /* channel13 UART0 tx */ + <0x5a2e0000 0x10000>, /* channel14 UART1 rx */ + <0x5a2f0000 0x10000>, /* channel15 UART1 tx */ + <0x5a300000 0x10000>, /* channel16 UART2 rx */ + <0x5a310000 0x10000>, /* channel17 UART2 tx */ + <0x5a320000 0x10000>, /* channel18 UART3 rx */ + <0x5a330000 0x10000>, /* channel19 UART3 tx */ + <0x5a340000 0x10000>, /* channel20 UART4 rx */ + <0x5a350000 0x10000>; /* channel21 UART4 tx */ + #dma-cells = <3>; + dma-channels = <14>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "edma0-chan0-rx", "edma0-chan1-tx", + "edma0-chan6-rx", "edma0-chan7-tx", + "edma0-chan12-rx", "edma0-chan13-tx", + "edma0-chan14-rx", "edma0-chan15-tx", + "edma0-chan16-rx", "edma0-chan17-tx", + "edma0-chan18-rx", "edma0-chan19-tx", + "edma0-chan20-rx", "edma0-chan21-tx"; + power-domains = <&pd IMX_SC_R_DMA_0_CH0>, + <&pd IMX_SC_R_DMA_0_CH1>, + <&pd IMX_SC_R_DMA_0_CH6>, + <&pd IMX_SC_R_DMA_0_CH7>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>, + <&pd IMX_SC_R_DMA_0_CH16>, + <&pd IMX_SC_R_DMA_0_CH17>, + <&pd IMX_SC_R_DMA_0_CH18>, + <&pd IMX_SC_R_DMA_0_CH19>, + <&pd IMX_SC_R_DMA_0_CH20>, + <&pd IMX_SC_R_DMA_0_CH21>; + power-domain-names = "edma0-chan0", "edma0-chan1", + "edma0-chan6", "edma0-chan7", + "edma0-chan12", "edma0-chan13", + "edma0-chan14", "edma0-chan15", + "edma0-chan16", "edma0-chan17", + "edma0-chan18", "edma0-chan19", + "edma0-chan20", "edma0-chan21"; + status = "okay"; +}; + +&lpuart0 { + compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; +}; + +&lpuart1 { + compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; + power-domains = <&pd IMX_SC_R_UART_1>; + dmas = <&edma2 15 0 0>, + <&edma2 14 0 1>; +}; + +&lpuart2 { + compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; +}; + +&lpuart3 { + compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; +}; + +&i2c0 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&i2c1 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&i2c2 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&i2c3 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-gpu.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-gpu.dtsi new file mode 100644 index 00000000000000..90b670b15276a8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-gpu.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +&gpu_3d0 { + assigned-clock-rates = <800000000>, <1000000000>; + fsl,sc_gpu_pid = ; +}; + +&gpu1_subsys { + imx8_gpu_ss: imx8_gpu1_ss { + compatible = "fsl,imx8qm-gpu", "fsl,imx8-gpu-ss"; + cores = <&gpu_3d0>, <&gpu_3d1>; + reg = <0x80000000 0x80000000>, <0x0 0x10000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; + depth-compression = <0>; + /**/ + operating-points = < + /*overdrive*/ 800000 0 /*The first tuple is for core clock frequency*/ + 1000000 0 /*The second tuple is for shader clock frequency*/ + /*nominal*/ 650000 0 + 700000 0 + /*underdrive*/ 400000 0 /*core/shader clock share the same frequency on underdrive mode*/ + >; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hdmi.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hdmi.dtsi new file mode 100644 index 00000000000000..049416cb629acf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hdmi.dtsi @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Sandor Yu + */ + +#include + +/ { + hdmi_subsys: bus@56260000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x56260000 0x0 0x56260000 0x10000>; + + irqsteer_hdmi: irqsteer@56260000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x56260000 0x1000>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + interrupts = ; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&hdmi_lpcg_lis_ipg 0>; + clock-names = "ipg"; + assigned-clocks = <&clk IMX_SC_R_HDMI_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; + assigned-clock-rates = <800000000>, <84375000>; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_i2c0: clock-controller@56263000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263000 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI_I2C_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; + bit-offset = <0 16>; + clock-output-names = "hdmi_lpcg_i2c0_clk", + "hdmi_lpcg_i2c0_ipg_clk"; + power-domains = <&pd IMX_SC_R_HDMI_I2C_0>; + status = "disabled"; + }; + + hdmi_lpcg_lis_ipg: clock-controller@56263004 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263004 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; + bit-offset = <16>; + clock-output-names = "hdmi_lpcg_lis_ipg_clk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_pwm_ipg: clock-controller@56263008 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263008 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; + bit-offset = <16>; + clock-output-names = "hdmi_lpcg_pwm_ipg_clk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_i2s: clock-controller@5626300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5626300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI_I2S IMX_SC_PM_CLK_MISC0>; + bit-offset = <0>; + clock-output-names = "hdmi_lpcg_i2s_clk"; + power-domains = <&pd IMX_SC_R_HDMI_I2S>; + status = "disabled"; + }; + + hdmi_lpcg_gpio_ipg: clock-controller@56263010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263010 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; + bit-offset = <16>; + clock-output-names = "hdmi_lpcg_gpio_ipg_clk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_msi_hclk: clock-controller@56263014 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263014 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; + bit-offset = <0>; + clock-output-names = "hdmi_lpcg_msi_hclk_clk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_pxl: clock-controller@56263018 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263018 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC0>; + bit-offset = <0>; + clock-output-names = "hdmi_lpcg_pxl_clk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_phy: clock-controller@5626301c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5626301c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; + bit-offset = <0 16>; + clock-output-names = "hdmi_lpcg_phy_vif_clk", + "hdmi_lpcg_phy_pclk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_apb_mux_csr: clock-controller@56263020 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263020 0x4>; + #clock-cells = <1>; + clocks = <&hdmi_lpcg_apb 0>; + bit-offset = <16>; + clock-output-names = "hdmi_lpcg_apb_mux_csr_clk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_apb_mux_ctrl: clock-controller@56263024 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263024 0x4>; + #clock-cells = <1>; + clocks = <&hdmi_lpcg_apb 0>; + bit-offset = <16>; + clock-output-names = "hdmi_lpcg_apb_mux_ctrl_clk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_apb: clock-controller@56263028 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263028 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; + bit-offset = <16>; + clock-output-names = "hdmi_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + i2c0_hdmi: i2c@56266000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x56266000 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_hdmi>; + clocks = <&hdmi_lpcg_i2c0 0>, + <&hdmi_lpcg_i2c0 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_HDMI_I2C_0 IMX_SC_PM_CLK_MISC2>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_HDMI_I2C_0>; + status = "disabled"; + }; + + hdmi:hdmi@56268000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x56268000 0x1000>, + <0x56261000 0x1000>; + interrupt-parent = <&irqsteer_hdmi>; + interrupts = <10>, <13>; + interrupt-names = "plug_in", "plug_out"; + status = "disabled"; + + clocks = <&clk IMX_SC_R_HDMI_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_HDMI_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC3>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC1>, + <&hdmi_lpcg_phy 1>, + <&hdmi_lpcg_msi_hclk 0>, + <&hdmi_lpcg_pxl 0>, + <&hdmi_lpcg_phy 0>, + <&hdmi_lpcg_lis_ipg 0>, + <&hdmi_lpcg_apb 0>, + <&hdmi_lpcg_apb_mux_csr 0>, + <&hdmi_lpcg_apb_mux_ctrl 0>, + <&clk IMX_SC_R_HDMI_I2S IMX_SC_PM_CLK_BYPASS>, + <&hdmi_lpcg_i2s 0>; + clock-names = "dig_pll", "av_pll", "clk_ipg", + "clk_core", "clk_pxl", "clk_pxl_mux", + "clk_pxl_link", "lpcg_hdp", "lpcg_msi", + "lpcg_pxl", "lpcg_vif", "lpcg_lis", + "lpcg_apb", "lpcg_apb_csr", "lpcg_apb_ctrl", + "clk_i2s_bypass", "lpcg_i2s"; + assigned-clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC3>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC1>; + assigned-clock-parents = <&clk IMX_SC_R_HDMI_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_HDMI_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_HDMI_PLL_1 IMX_SC_PM_CLK_PLL>; + power-domains = <&pd IMX_SC_R_HDMI>, + <&pd IMX_SC_R_HDMI_PLL_0>, + <&pd IMX_SC_R_HDMI_PLL_1>; + power-domain-names = "hdmi", "pll0", "pll1"; + + port@0 { + reg = <0>; + hdmi_disp: endpoint { + remote-endpoint = <&dpu1_disp0_hdmi>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi new file mode 100644 index 00000000000000..e62957d0187cf0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi @@ -0,0 +1,219 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Richard Zhu + */ + +&hsio_subsys { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + pciea_lpcg: clock-controller@5f050000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f050000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_axi_clk>, <&hsio_axi_clk>, <&hsio_axi_clk>; + bit-offset = <16 20 24>; + clock-output-names = "hsio_pciea_mstr_axi_clk", + "hsio_pciea_slv_axi_clk", + "hsio_pciea_dbi_axi_clk"; + power-domains = <&pd IMX_SC_R_PCIE_A>; + }; + + sata_lpcg: clock-controller@5f070000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f070000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_axi_clk>; + bit-offset = <16>; + clock-output-names = "hsio_sata_clk"; + power-domains = <&pd IMX_SC_R_SATA_0>; + }; + + phyx2_lpcg: clock-controller@5f080000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f080000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_refa_clk>, <&hsio_per_clk>, + <&hsio_refa_clk>, <&hsio_per_clk>; + bit-offset = <0 4 16 20>; + clock-output-names = "hsio_phyx2_pclk_0", + "hsio_phyx2_pclk_1", + "hsio_phyx2_apbclk_0", + "hsio_phyx2_apbclk_1"; + power-domains = <&pd IMX_SC_R_SERDES_0>; + }; + + phyx1_lpcg: clock-controller@5f090000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f090000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_refa_clk>, <&hsio_per_clk>, + <&hsio_per_clk>, <&hsio_per_clk>; + bit-offset = <0 4 8 16>; + clock-output-names = "hsio_phyx1_pclk", + "hsio_phyx1_epcs_tx_clk", + "hsio_phyx1_epcs_rx_clk", + "hsio_phyx1_apb_clk"; + power-domains = <&pd IMX_SC_R_SERDES_1>; + }; + + phyx2_crr0_lpcg: clock-controller@5f0a0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f0a0000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_per_clk>; + bit-offset = <16>; + clock-output-names = "hsio_phyx2_per_clk"; + power-domains = <&pd IMX_SC_R_SERDES_0>; + }; + + pciea_crr2_lpcg: clock-controller@5f0c0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f0c0000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_per_clk>; + bit-offset = <16>; + clock-output-names = "hsio_pciea_per_clk"; + power-domains = <&pd IMX_SC_R_PCIE_A>; + }; + + sata_crr4_lpcg: clock-controller@5f0e0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f0e0000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_per_clk>; + bit-offset = <16>; + clock-output-names = "hsio_sata_per_clk"; + power-domains = <&pd IMX_SC_R_SATA_0>; + }; + + pciea: pcie@0x5f000000 { + compatible = "fsl,imx8qm-pcie","snps,dw-pcie"; + reg = <0x5f000000 0x10000>, /* Controller reg */ + <0x6ff00000 0x80000>, /* PCI cfg space */ + <0x5f080000 0xf0000>; /* lpcg, csr, msic, gpio */ + reg-names = "dbi", "config", "hsio"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x00000000 0x6ff80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x60000000 0x60000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + num-viewport = <4>; + interrupts = , + ; /* eDMA */ + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 73 4>, + <0 0 0 2 &gic 0 74 4>, + <0 0 0 3 &gic 0 75 4>, + <0 0 0 4 &gic 0 76 4>; + /* + * Set these clocks in default, then clocks should be + * refined for exact hw design of imx8 pcie. + */ + clocks = <&pciea_lpcg 0>, + <&pciea_lpcg 1>, + <&pciea_lpcg 2>, + <&phyx2_lpcg 0>, + <&phyx2_crr0_lpcg 0>, + <&pciea_crr2_lpcg 0>, + <&misc_crr5_lpcg 0>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", + "pcie_phy", "phy_per", "pcie_per", "misc_per"; + power-domains = <&pd IMX_SC_R_PCIE_A>, + <&pd IMX_SC_R_SERDES_0>, + <&pd IMX_SC_R_HSIO_GPIO>; + power-domain-names = "pcie", "pcie_phy", "hsio_gpio"; + fsl,max-link-speed = <3>; + hsio-cfg = ; + local-addr = <0x40000000>; + status = "disabled"; + }; + + pcieb: pcie@0x5f010000 { + compatible = "fsl,imx8qm-pcie","snps,dw-pcie"; + reg = <0x5f010000 0x10000>, /* Controller reg */ + <0x7ff00000 0x80000>, /* PCI cfg space */ + <0x5f080000 0xf0000>; /* lpcg, csr, msic, gpio */ + reg-names = "dbi", "config", "hsio"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x00000000 0x7ff80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x70000000 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + num-viewport = <4>; + interrupts = , + ; /* eDMA */ + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 105 4>, + <0 0 0 2 &gic 0 106 4>, + <0 0 0 3 &gic 0 107 4>, + <0 0 0 4 &gic 0 108 4>; + clocks = <&pcieb_lpcg 0>, + <&pcieb_lpcg 1>, + <&pcieb_lpcg 2>, + <&phyx2_lpcg 1>, + <&phyx2_lpcg 0>, + <&phyx2_crr0_lpcg 0>, + <&pcieb_crr3_lpcg 0>, + <&pciea_crr2_lpcg 0>, + <&misc_crr5_lpcg 0>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", + "pcie_phy", "pcie_phy_pclk", "phy_per", + "pcie_per", "pciex2_per", "misc_per"; + power-domains = <&pd IMX_SC_R_PCIE_B>, + <&pd IMX_SC_R_PCIE_A>, + <&pd IMX_SC_R_SERDES_0>, + <&pd IMX_SC_R_HSIO_GPIO>; + power-domain-names = "pcie", "pcie_per", "pcie_phy", + "hsio_gpio"; + fsl,max-link-speed = <3>; + hsio-cfg = ; + local-addr = <0x80000000>; + status = "disabled"; + }; + + sata: sata@5f020000 { + compatible = "fsl,imx8qm-ahci"; + reg = <0x5f020000 0x10000>, /* Controller reg */ + <0x5f1a0000 0x10000>, /* PHY reg */ + <0x5f080000 0xf0000>; /* lpcg, csr, msic, gpio */ + reg-names = "ctl", "phy", "hsio"; + interrupts = ; + clocks = <&sata_lpcg 0>, + <&phyx1_lpcg 0>, + <&phyx1_lpcg 1>, + <&phyx1_lpcg 2>, + <&phyx2_crr0_lpcg 0>, + <&phyx1_crr1_lpcg 0>, + <&pciea_crr2_lpcg 0>, + <&pcieb_crr3_lpcg 0>, + <&sata_crr4_lpcg 0>, + <&misc_crr5_lpcg 0>, + <&phyx2_lpcg 0>, + <&phyx2_lpcg 1>, + <&phyx1_lpcg 3>; + clock-names = "sata", "sata_ref", "epcs_tx", "epcs_rx", + "per_clk0", "per_clk1", "per_clk2", + "per_clk3", "per_clk4", "per_clk5", + "phy_pclk0", "phy_pclk1", "phy_apbclk"; + power-domains = <&pd IMX_SC_R_SATA_0>, + <&pd IMX_SC_R_PCIE_A>, + <&pd IMX_SC_R_PCIE_B>, + <&pd IMX_SC_R_SERDES_0>, + <&pd IMX_SC_R_SERDES_1>, + <&pd IMX_SC_R_HSIO_GPIO>; + fsl,sc_rsrc_id = ; + iommus = <&smmu 0x13 0x7f80>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi new file mode 100644 index 00000000000000..a1baeeac02fe68 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +&pi0_pxl_lpcg { + status = "disabled"; +}; + +&pi0_ipg_lpcg { + status = "disabled"; +}; + +&pi0_misc_lpcg { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi new file mode 100644 index 00000000000000..d5875e7aa65b46 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ +&lsio_subsys { + lsio_mu6: mailbox@5d210000 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; + reg = <0x5d210000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_MU_6A>; + }; +}; + +&lsio_gpio0 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio1 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio2 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio3 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio4 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio5 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio6 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio7 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +}; + +&lsio_mu0 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu1 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu2 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu3 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu4 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi new file mode 100644 index 00000000000000..788250766632c3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi @@ -0,0 +1,353 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019 NXP + */ + +/ { + lvds1_subsys: bus@56240000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x56240000 0x0 0x56240000 0x10000>; + + lvds0_ipg_clk: clock-lvds-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "lvds0_ipg_clk"; + }; + + lvds0_lis_lpcg: clock-controller@56243000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243000 0x4>; + #clock-cells = <1>; + clocks = <&lvds0_ipg_clk>; + bit-offset = <16>; + clock-output-names = "lvds0_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + }; + + lvds0_pwm_lpcg: clock-controller@5624300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5624300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>, + <&lvds0_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "lvds0_pwm_lpcg_clk", + "lvds0_pwm_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_0_PWM_0>; + }; + + lvds0_i2c0_lpcg: clock-controller@56243010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243010 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&lvds0_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "lvds0_i2c0_lpcg_clk", + "lvds0_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; + }; + + lvds0_i2c1_lpcg: clock-controller@56243014 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243014 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&lvds0_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "lvds0_i2c1_lpcg_clk", + "lvds0_i2c1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; + }; + + irqsteer_lvds0: irqsteer@56240000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x56240000 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&lvds0_lis_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + }; + + lvds0_region: lvds_region@56241000 { + compatible = "syscon"; + reg = <0x56241000 0xf0>; + }; + + ldb1_phy: ldb_phy@56241000 { + compatible = "mixel,lvds-phy"; + reg = <0x56241000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>; + clock-names = "phy"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + status = "disabled"; + + ldb1_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb1_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + + ldb1: ldb@562410e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-ldb"; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + gpr = <&lvds0_region>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb1_phy1>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_ch0: endpoint { + remote-endpoint = <&dpu1_disp1_ldb1_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb1_phy2>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_ch1: endpoint { + remote-endpoint = <&dpu1_disp1_ldb1_ch1>; + }; + }; + }; + }; + + pwm_lvds0: pwm@56244000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x56244000 0x1000>; + clocks = <&lvds0_pwm_lpcg 0>, + <&lvds0_pwm_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd IMX_SC_R_LVDS_0_PWM_0>; + status = "disabled"; + }; + + i2c1_lvds0: i2c@56247000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56247000 0x4000>; + interrupts = <9>; + interrupt-parent = <&irqsteer_lvds0>; + clocks = <&lvds0_i2c0_lpcg 0>, + <&lvds0_i2c0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; + status = "disabled"; + }; + }; + + lvds2_subsys: bus@57240000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x57240000 0x0 0x57240000 0x10000>; + + lvds1_ipg_clk: clock-lvds-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "lvds1_ipg_clk"; + }; + + lvds1_lis_lpcg: clock-controller@57243000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57243000 0x4>; + #clock-cells = <1>; + clocks = <&lvds1_ipg_clk>; + bit-offset = <16>; + clock-output-names = "lvds1_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_1>; + }; + + lvds1_pwm_lpcg: clock-controller@5724300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5724300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>, + <&lvds1_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "lvds1_pwm_lpcg_clk", + "lvds1_pwm_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>; + }; + + lvds1_i2c0_lpcg: clock-controller@57243010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57243010 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>, + <&lvds1_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "lvds1_i2c0_lpcg_clk", + "lvds1_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>; + }; + + lvds1_i2c1_lpcg: clock-controller@57243014 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57243014 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>, + <&lvds1_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "lvds1_i2c1_lpcg_clk", + "lvds1_i2c1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>; + }; + + irqsteer_lvds1: irqsteer@57240000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x57240000 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&lvds1_lis_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_LVDS_1>; + }; + + lvds1_region: lvds_region@57241000 { + compatible = "syscon"; + reg = <0x57241000 0xf0>; + }; + + ldb2_phy: ldb_phy@57241000 { + compatible = "mixel,lvds-phy"; + reg = <0x57241000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_PHY>; + clock-names = "phy"; + power-domains = <&pd IMX_SC_R_LVDS_1>; + status = "disabled"; + + ldb2_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb2_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + + ldb2: ldb@572410e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-ldb"; + clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass"; + power-domains = <&pd IMX_SC_R_LVDS_1>; + gpr = <&lvds1_region>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb2_phy1>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_ch0: endpoint { + remote-endpoint = <&dpu2_disp1_ldb2_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb2_phy2>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_ch1: endpoint { + remote-endpoint = <&dpu2_disp1_ldb2_ch1>; + }; + }; + }; + }; + + pwm_lvds1: pwm@57244000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x57244000 0x1000>; + clocks = <&lvds1_pwm_lpcg 0>, + <&lvds1_pwm_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>; + status = "disabled"; + }; + + i2c1_lvds1: i2c@57247000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x57247000 0x4000>; + interrupts = <9>; + interrupt-parent = <&irqsteer_lvds1>; + clocks = <&lvds1_i2c0_lpcg 0>, + <&lvds1_i2c0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi new file mode 100644 index 00000000000000..ba166abbab3cff --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi @@ -0,0 +1,352 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019 NXP + */ + +/ { + dsi_ipg_clk: clock-dsi-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "dsi_ipg_clk"; + }; + + mipi_pll_div2_clk: clock-mipi-div2-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <432000000>; + clock-output-names = "mipi_pll_div2_clk"; + }; + + mipi0_subsys: bus@56220000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x56220000 0x0 0x56220000 0x10000>; + + mipi0_lis_lpcg: clock-controller@56223000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223000 0x4>; + #clock-cells = <1>; + clocks = <&dsi_ipg_clk>; + bit-offset = <0>; + clock-output-names = "mipi0_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + mipi0_i2c0_lpcg_clk: clock-controller@5622301c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5622301c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_MISC2>; + bit-offset = <0>; + clock-output-names = "mipi0_i2c0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + }; + + mipi0_i2c0_lpcg_ipg_s_clk: clock-controller@56223018 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223018 0x4>; + #clock-cells = <1>; + clocks = <&dsi_ipg_clk>; + bit-offset = <0>; + clock-output-names = "mipi0_i2c0_lpcg_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + }; + + mipi0_i2c0_lpcg_ipg_clk: clock-controller@56223014 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223014 0x4>; + #clock-cells = <1>; + clocks = <&mipi0_i2c0_lpcg_ipg_s_clk 0>; + bit-offset = <0>; + clock-output-names = "mipi0_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + }; + + mipi0_i2c1_lpcg_clk: clock-controller@5622302c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5622302c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_0_I2C_1 IMX_SC_PM_CLK_MISC2>; + bit-offset = <0>; + clock-output-names = "mipi0_i2c1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>; + }; + + mipi0_i2c1_lpcg_ipg_s_clk: clock-controller@56223028 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223028 0x4>; + #clock-cells = <1>; + clocks = <&dsi_ipg_clk>; + bit-offset = <0>; + clock-output-names = "mipi0_i2c1_lpcg_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>; + }; + + mipi0_i2c1_lpcg_ipg_clk: clock-controller@56223024 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223024 0x4>; + #clock-cells = <1>; + clocks = <&mipi0_i2c1_lpcg_ipg_s_clk 0>; + bit-offset = <0>; + clock-output-names = "mipi0_i2c1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>; + }; + + irqsteer_mipi0: irqsteer@56220000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x56220000 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&mipi0_lis_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + i2c0_mipi0: i2c@56226000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56226000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_mipi0>; + clocks = <&mipi0_i2c0_lpcg_clk 0>, + <&mipi0_i2c0_lpcg_ipg_clk 0>; + clock-names = "per", "ipg"; + assigned-clocks = <&mipi0_i2c0_lpcg_clk 0>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + status = "disabled"; + }; + + mipi0_csr: csr@56221000 { + compatible = "syscon"; + reg = <0x56221000 0x240>; + }; + + mipi0_dphy: dphy@56228300 { + compatible = "fsl,imx8qm-mipi-dphy"; + reg = <0x56228300 0x100>; + clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>; + clock-names = "phy_ref"; + #phy-cells = <0>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + status = "disabled"; + }; + + mipi0_dsi_host: dsi_host@56228000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-nwl-dsi"; + reg = <0x56228000 0x300>; + clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_MST_BUS>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_SLV_BUS>, + <&mipi_pll_div2_clk>; + clock-names = "pixel", + "bypass", + "phy_ref", + "tx_esc", + "rx_esc", + "phy_parent"; + interrupts = <16>; + interrupt-parent = <&irqsteer_mipi0>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + phys = <&mipi0_dphy>; + phy-names = "dphy"; + csr = <&mipi0_csr>; + use-disp-ss; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + mipi0_dsi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dpu1_disp0_mipi0>; + }; + }; + }; + }; + }; + + mipi1_subsys: bus@57220000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x57220000 0x0 0x57220000 0x10000>; + + mipi1_lis_lpcg: clock-controller@57223000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57223000 0x4>; + #clock-cells = <1>; + clocks = <&dsi_ipg_clk>; + bit-offset = <0>; + clock-output-names = "mipi1_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1>; + }; + + mipi1_i2c0_lpcg_clk: clock-controller@5722301c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5722301c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_MISC2>; + bit-offset = <0>; + clock-output-names = "mipi1_i2c0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + }; + + mipi1_i2c0_lpcg_ipg_s_clk: clock-controller@57223018 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57223018 0x4>; + #clock-cells = <1>; + clocks = <&dsi_ipg_clk>; + bit-offset = <0>; + clock-output-names = "mipi1_i2c0_lpcg_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + }; + + mipi1_i2c0_lpcg_ipg_clk: clock-controller@57223014 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57223014 0x4>; + #clock-cells = <1>; + clocks = <&mipi1_i2c0_lpcg_ipg_s_clk 0>; + bit-offset = <0>; + clock-output-names = "mipi1_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + }; + + mipi1_i2c1_lpcg_clk: clock-controller@5722302c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5722302c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_1_I2C_1 IMX_SC_PM_CLK_MISC2>; + bit-offset = <0>; + clock-output-names = "mipi1_i2c1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>; + }; + + mipi1_i2c1_lpcg_ipg_s_clk: clock-controller@57223028 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57223028 0x4>; + #clock-cells = <1>; + clocks = <&dsi_ipg_clk>; + bit-offset = <0>; + clock-output-names = "mipi1_i2c1_lpcg_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>; + }; + + mipi1_i2c1_lpcg_ipg_clk: clock-controller@57223024 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57223024 0x4>; + #clock-cells = <1>; + clocks = <&mipi1_i2c1_lpcg_ipg_s_clk 0>; + bit-offset = <0>; + clock-output-names = "mipi1_i2c1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>; + }; + + irqsteer_mipi1: irqsteer@57220000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x57220000 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&mipi1_lis_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_MIPI_1>; + }; + + i2c0_mipi1: i2c@57226000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x57226000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_mipi1>; + clocks = <&mipi1_i2c0_lpcg_clk 0>, + <&mipi1_i2c0_lpcg_ipg_clk 0>; + clock-names = "per", "ipg"; + assigned-clocks = <&mipi1_i2c0_lpcg_clk 0>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + status = "disabled"; + }; + + mipi1_csr: csr@57221000 { + compatible = "syscon"; + reg = <0x57221000 0x240>; + }; + + mipi1_dphy: dphy@57228300 { + compatible = "fsl,imx8qm-mipi-dphy"; + reg = <0x57228300 0x100>; + clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>; + clock-names = "phy_ref"; + #phy-cells = <0>; + power-domains = <&pd IMX_SC_R_MIPI_1>; + status = "disabled"; + }; + + mipi1_dsi_host: dsi_host@57228000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-nwl-dsi"; + reg = <0x57228000 0x300>; + clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_MST_BUS>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_SLV_BUS>, + <&mipi_pll_div2_clk>; + clock-names = "pixel", + "bypass", + "phy_ref", + "tx_esc", + "rx_esc", + "phy_parent"; + interrupts = <16>; + interrupt-parent = <&irqsteer_mipi1>; + power-domains = <&pd IMX_SC_R_MIPI_1>; + phys = <&mipi1_dphy>; + phy-names = "dphy"; + csr = <&mipi1_csr>; + use-disp-ss; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + mipi1_dsi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dpu2_disp0_mipi1>; + }; + }; + }; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/freescale/imx8qm-xen.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-xen.dtsi new file mode 100644 index 00000000000000..39fcd8b5c8bc6f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-xen.dtsi @@ -0,0 +1,341 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +&usdhc1 { + /delete-property/ iommus; +}; + +&usdhc2 { + /delete-property/ iommus; +}; + +&usdhc3 { + /delete-property/ iommus; +}; + +&fec1 { + /delete-property/ iommus; +}; + +&fec2 { + /delete-property/ iommus; +}; + +&sata { + /delete-property/ iommus; +}; + +&usbotg3 { + /delete-property/ iommus; +}; + +&smmu { + /* xen only supports legacy bindings for now */ + #iommu-cells = <0>; +}; + +&dpu1 { + fsl,sc_rsrc_id = , + , + , + , + , + , + , + , + ; +}; + +&dpu2 { + fsl,sc_rsrc_id = , + , + , + , + , + , + , + , + ; +}; + +/* edma2 called in imx8qm RM with the same address in edma0 of imx8qxp */ +&edma0{ + fsl,sc_rsrc_id = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + +&edma1 { + xen,passthrough; +}; + +&acm { + xen,passthrough; +}; + +&asrc0 { + xen,passthrough; +}; + +&esai0 { + xen,passthrough; +}; + +&spdif0 { + xen,passthrough; +}; + +&spdif1 { + xen,passthrough; +}; + +&sai0 { + xen,passthrough; +}; + +&sai1 { + xen,passthrough; +}; + +&sai2 { + xen,passthrough; +}; + +&sai3 { + xen,passthrough; +}; + +&asrc1 { + xen,passthrough; +}; + +&amix { + xen,passthrough; +}; + +&asrc0_lpcg { + xen,passthrough; +}; + +&esai0_lpcg { + xen,passthrough; +}; + +&spdif0_lpcg { + xen,passthrough; +}; + +&spdif1_lpcg { + xen,passthrough; +}; + +&sai0_lpcg { + xen,passthrough; +}; + +&sai1_lpcg { + xen,passthrough; +}; + +&sai2_lpcg { + xen,passthrough; +}; + +&sai3_lpcg { + xen,passthrough; +}; + +&asrc1_lpcg { + xen,passthrough; +}; + +&mqs0_lpcg { + xen,passthrough; +}; + +&dsp_lpcg { + xen,passthrough; +}; + +&dsp_ram_lpcg { + xen,passthrough; +}; + +&sai4 { + xen,passthrough; +}; + +&sai5 { + xen,passthrough; +}; + +&esai1 { + xen,passthrough; +}; + +&sai6 { + xen,passthrough; +}; + +&sai7 { + xen,passthrough; +}; + +&sai4_lpcg { + xen,passthrough; +}; + +&sai5_lpcg { + xen,passthrough; +}; + +&esai1_lpcg { + xen,passthrough; +}; + +&sai6_lpcg { + xen,passthrough; +}; + +&sai7_lpcg { + xen,passthrough; +}; + +&amix_lpcg { + xen,passthrough; +}; + +&aud_rec0_lpcg { + xen,passthrough; +}; + +&aud_rec1_lpcg { + xen,passthrough; +}; + +&aud_pll_div0_lpcg { + xen,passthrough; +}; + +&aud_pll_div1_lpcg { + xen,passthrough; +}; + +&mclkout0_lpcg { + xen,passthrough; +}; + +&mclkout1_lpcg { + xen,passthrough; +}; + +/ { + +dma_subsys: bus@5a000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5a000000 0x0 0x5a000000 0x1000000>; + + /* edma0 called in imx8qm RM with the same address in edma2 of imx8qxp */ + edma214: dma-controller@5a2e0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x5a2e0000 0x10000>, /* channel14 UART1 rx */ + <0x5a2f0000 0x10000>; /* channel15 UART1 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = , + ; + interrupt-names = "edma0-chan14-rx", "edma0-chan15-tx"; + power-domains = <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>; + power-domain-names = "edma0-chan14", "edma0-chan15"; + status = "okay"; + fsl,sc_rsrc_id = , + ; + }; +}; +}; + +&edma2 { + reg = <0x5a200000 0x10000>, /* channel0 LPSPI0 rx */ + <0x5a210000 0x10000>, /* channel1 LPSPI0 tx */ + <0x5a260000 0x10000>, /* channel6 LPSPI3 rx */ + <0x5a270000 0x10000>, /* channel7 LPSPI3 tx */ + <0x5a2c0000 0x10000>, /* channel12 UART0 rx */ + <0x5a2d0000 0x10000>, /* channel13 UART0 tx */ + <0x5a300000 0x10000>, /* channel16 UART2 rx */ + <0x5a310000 0x10000>, /* channel17 UART2 tx */ + <0x5a320000 0x10000>, /* channel18 UART3 rx */ + <0x5a330000 0x10000>, /* channel19 UART3 tx */ + <0x5a340000 0x10000>, /* channel20 UART4 rx */ + <0x5a350000 0x10000>; /* channel21 UART4 tx */ + #dma-cells = <3>; + dma-channels = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "edma0-chan0-rx", "edma0-chan1-tx", + "edma0-chan6-rx", "edma0-chan7-tx", + "edma0-chan12-rx", "edma0-chan13-tx", + "edma0-chan16-rx", "edma0-chan17-tx", + "edma0-chan18-rx", "edma0-chan19-tx", + "edma0-chan20-rx", "edma0-chan21-tx"; + power-domains = <&pd IMX_SC_R_DMA_0_CH0>, + <&pd IMX_SC_R_DMA_0_CH1>, + <&pd IMX_SC_R_DMA_0_CH6>, + <&pd IMX_SC_R_DMA_0_CH7>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH16>, + <&pd IMX_SC_R_DMA_0_CH17>, + <&pd IMX_SC_R_DMA_0_CH18>, + <&pd IMX_SC_R_DMA_0_CH19>, + <&pd IMX_SC_R_DMA_0_CH20>, + <&pd IMX_SC_R_DMA_0_CH21>; + power-domain-names = "edma0-chan0", "edma0-chan1", + "edma0-chan6", "edma0-chan7", + "edma0-chan12", "edma0-chan13", + "edma0-chan16", "edma0-chan17", + "edma0-chan18", "edma0-chan19", + "edma0-chan20", "edma0-chan21"; + status = "okay"; +}; + +&lpspi0 { +}; + +&lpuart1 { + dmas = <&edma214 15 0 0>, <&edma214 14 0 1>; +}; + +&lpuart2 { +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi new file mode 100755 index 00000000000000..3b684e8b2ecc7a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -0,0 +1,557 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &fec1; + ethernet1 = &fec2; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + isi0 = &isi_0; + isi1 = &isi_1; + isi2 = &isi_2; + isi3 = &isi_3; + isi4 = &isi_4; + isi5 = &isi_5; + isi6 = &isi_6; + isi7 = &isi_7; + csi0 = &mipi_csi_0; + csi1 = &mipi_csi_1; + mu1 = &lsio_mu1; + can0 = &flexcan1; + can1 = &flexcan2; + can2 = &flexcan3; + dpu0 = &dpu1; + dpu1 = &dpu2; + ldb0 = &ldb1; + ldb1 = &ldb2; + i2c0 = &i2c_rpbus_0; + i2c1 = &i2c_rpbus_1; + dphy0 = &mipi0_dphy; + dphy1 = &mipi1_dphy; + mipi_dsi0 = &mipi0_dsi_host; + mipi_dsi1 = &mipi1_dsi_host; + }; + + cpus: cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&A53_0>; + }; + core1 { + cpu = <&A53_1>; + }; + core2 { + cpu = <&A53_2>; + }; + core3 { + cpu = <&A53_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&A72_0>; + }; + core1 { + cpu = <&A72_1>; + }; + }; + }; + + A53_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + #cooling-cells = <2>; + }; + + A53_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + #cooling-cells = <2>; + }; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + #cooling-cells = <2>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + #cooling-cells = <2>; + }; + + A72_0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x0 0x100>; + clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; + enable-method = "psci"; + next-level-cache = <&A72_L2>; + operating-points-v2 = <&a72_opp_table>; + #cooling-cells = <2>; + }; + + A72_1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x0 0x101>; + clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; + enable-method = "psci"; + next-level-cache = <&A72_L2>; + operating-points-v2 = <&a72_opp_table>; + #cooling-cells = <2>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + + A72_L2: l2-cache1 { + compatible = "cache"; + }; + }; + + a53_opp_table: a53-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000>; + clock-latency-ns = <150000>; + }; + + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + + a72_opp_table: a72-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + }; + + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + }; + + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + }; + + opp-1596000000 { + opp-hz = /bits/ 64 <1596000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xC0000>, /* GICR */ + <0x0 0x52000000 0 0x2000>, /* GICC */ + <0x0 0x52010000 0 0x1000>, /* GICH */ + <0x0 0x52020000 0 0x20000>; /* GICV */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + xtal32k: clock-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xtal_24MHz"; + }; + + smmu: iommu@51400000 { + compatible = "arm,mmu-500"; + interrupt-parent = <&gic>; + reg = <0 0x51400000 0 0x40000>; + #global-interrupts = <1>; + #iommu-cells = <2>; + interrupts = <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>; + }; + + scu { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", "tx1", "tx2", "tx3", + "rx0", "rx1", "rx2", "rx3", + "gip3"; + mboxes = <&lsio_mu1 0 0 + &lsio_mu1 0 1 + &lsio_mu1 0 2 + &lsio_mu1 0 3 + &lsio_mu1 1 0 + &lsio_mu1 1 1 + &lsio_mu1 1 2 + &lsio_mu1 1 3 + &lsio_mu1 3 3>; + + pd: imx8qx-pd { + compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + wakeup-irq = <235 236 237 258 262 267 271 + 345 346 347 348>; + }; + + clk: clock-controller { + compatible = "fsl,imx8qm-clk", "fsl,scu-clk"; + #clock-cells = <2>; + clocks = <&xtal32k &xtal24m>; + clock-names = "xtal_32KHz", "xtal_24Mhz"; + }; + + iomuxc: pinctrl { + compatible = "fsl,imx8qm-iomuxc"; + }; + + ocotp: imx8qm-ocotp { + compatible = "fsl,imx8qm-scu-ocotp"; + #address-cells = <1>; + #size-cells = <1>; + read-only; + + fec_mac0: mac@1c4 { + reg = <0x1c4 6>; + }; + + fec_mac1: mac@1c6 { + reg = <0x1c6 6>; + }; + }; + + rtc: rtc { + compatible = "fsl,imx8qm-sc-rtc"; + }; + + watchdog { + compatible = "fsl,imx8qm-sc-wdt", "fsl,imx-sc-wdt"; + timeout-sec = <60>; + }; + + tsens: thermal-sensor { + compatible = "fsl,imx8qm-sc-thermal"; + tsens-num = <6>; + #thermal-sensor-cells = <1>; + }; + + secvio: secvio { + compatible = "fsl,imx-sc-secvio"; + nvmem = <&ocotp>; + }; + }; + + thermal_zones: thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_A53>; + trips { + cpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_A72>; + trips { + cpu_alert1: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit1: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert1>; + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_GPU_0_PID0>; + trips { + gpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_GPU_1_PID0>; + trips { + gpu_alert1: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit1: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + drc-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_DRC_0>; + trips { + drc_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + drc_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + rpmsg0: rpmsg0{ + compatible = "fsl,imx8qm-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu5 0 1 + &lsio_mu5 1 1 + &lsio_mu5 3 1>; + mub-partition = <3>; + status = "disabled"; + }; + + rpmsg1: rpmsg1{ + compatible = "fsl,imx8qm-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu6 0 1 + &lsio_mu6 1 1 + &lsio_mu6 3 1>; + mub-partition = <4>; + status = "disabled"; + }; + + sc_pwrkey: sc-powerkey { + compatible = "fsl,imx8-pwrkey"; + linux,keycode = ; + wakeup-source; + }; + + vpu_subsys_dsp: bus@55000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x55000000 0x0 0x55000000 0x1000000>; + + dsp: dsp@556e8000 { + compatible = "fsl,imx8qm-dsp"; + reg = <0x556e8000 0x88000>; + clocks = <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "ipg", "ocram", "core"; + fsl,dsp-firmware = "imx/dsp/hifi4.bin"; + power-domains = <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>; + memory-region = <&dsp_reserved>; + fixup-offset = <0x4000000>; + status = "disabled"; + }; + }; + + /* sorted in register address */ + #include "imx8-ss-security.dtsi" + #include "imx8-ss-cm41.dtsi" + #include "imx8-ss-adma.dtsi" + #include "imx8-ss-conn.dtsi" + #include "imx8-ss-ddr.dtsi" + #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-hsio.dtsi" + #include "imx8-ss-img.dtsi" + #include "imx8-ss-dc0.dtsi" + #include "imx8-ss-dc1.dtsi" + #include "imx8-ss-gpu0.dtsi" + #include "imx8-ss-gpu1.dtsi" + #include "imx8-ss-vpu.dtsi" +}; + +#include "imx8qm-ss-audio.dtsi" +#include "imx8qm-ss-dma.dtsi" +#include "imx8qm-ss-conn.dtsi" +#include "imx8qm-ss-ddr.dtsi" +#include "imx8qm-ss-lsio.dtsi" +#include "imx8qm-ss-hsio.dtsi" +#include "imx8qm-ss-dc.dtsi" +#include "imx8qm-ss-lvds.dtsi" +#include "imx8qm-ss-mipi.dtsi" +#include "imx8qm-ss-hdmi.dtsi" +#include "imx8qm-ss-img.dtsi" +#include "imx8qm-ss-gpu.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qp-lpddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8qp-lpddr4-val.dts new file mode 100644 index 00000000000000..882b52adc03db1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp-lpddr4-val.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qp.dtsi" +#include "imx8q-val.dtsi" + +/ { + model = "Freescale i.MX8QP Validation Board"; + compatible = "fsl,imx8qp-val", "fsl,imx8qp", "fsl,imx8qm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qp.dtsi b/arch/arm64/boot/dts/freescale/imx8qp.dtsi new file mode 100644 index 00000000000000..ab657da22882a4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include "imx8qm.dtsi" + +/ { + model = "Freescale i.MX8QP"; + compatible = "fsl,imx8qp", "fsl,imx8qm"; +}; + +&cpus { + cpu-map { + cluster1 { + /delete-node/ core1; + }; + }; + /delete-node/ cpu@101; +}; + +&gpu_3d0 { + assigned-clock-rates = <625000000>, <625000000>; +}; + +&gpu_3d1 { + assigned-clock-rates = <625000000>, <625000000>; +}; + +&imx8_gpu_ss {/**/ + operating-points = < + /*nominal*/ 625000 0 + 625000 0 +/*underdrive*/ 400000 0 /*core/shader clock share the same frequency on underdrive mode*/ + >; +}; + +&thermal_zones { + cpu-thermal1 { + cooling-maps { + map0 { + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-17x17-val.dts b/arch/arm64/boot/dts/freescale/imx8qxp-17x17-val.dts new file mode 100644 index 00000000000000..4587edd5ddf839 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-17x17-val.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qxp.dtsi" +#include "imx8x-17x17-val.dtsi" + +/ { + model = "Freescale i.MX8QXP 17x17 Validation Board"; + compatible = "fsl,imx8qxp-17x17-val", "fsl,imx8qxp"; +}; + diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts index 91eef9754101f5..ee1610b5db6641 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts @@ -13,13 +13,13 @@ compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp"; aliases { - serial1 = &adma_lpuart1; - serial2 = &adma_lpuart2; - serial3 = &adma_lpuart3; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; }; chosen { - stdout-path = &adma_lpuart2; + stdout-path = &lpuart2; }; memory@80000000 { @@ -82,7 +82,7 @@ }; /* BT */ -&adma_lpuart0 { +&lpuart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; uart-has-rtscts; @@ -90,21 +90,21 @@ }; /* LS-UART0 */ -&adma_lpuart1 { +&lpuart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart1>; status = "okay"; }; /* Debug */ -&adma_lpuart2 { +&lpuart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart2>; status = "okay"; }; /* PCI-E UART */ -&adma_lpuart3 { +&lpuart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart3>; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ddr3l-val.dts b/arch/arm64/boot/dts/freescale/imx8qxp-ddr3l-val.dts new file mode 100644 index 00000000000000..05411ec714a60b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ddr3l-val.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qxp-lpddr4-val.dts" + +/ { + model = "Freescale i.MX8QXP DDR3L VALIDATION"; + compatible = "fsl,imx8qxp-ddr3l-val", "fsl,imx8qxp"; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x14000000>; + alloc-ranges = <0 0x96000000 0 0x14000000>; + linux,cma-default; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-enet2-tja1100.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-enet2-tja1100.dtsi new file mode 100644 index 00000000000000..d8d5b37196dfeb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-enet2-tja1100.dtsi @@ -0,0 +1,57 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&fec1 { + status = "disabled"; +}; + +&fec2 { + pinctrl-0 = <&pinctrl_fec2_rmii>; + clocks = <&enet1_lpcg 4>, + <&enet1_lpcg 2>, + <&clk IMX_SC_R_ENET_1 IMX_SC_C_DISABLE_50>, + <&enet1_lpcg 0>, + <&enet1_lpcg 1>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + /delete-property/ phy-supply; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + tja110x,refclk_in; + }; + }; +}; + +&iomuxc { + pinctrl_fec2_rmii: fec2rmiigrp { + fsl,pins = < + IMX8QXP_ENET0_MDC_CONN_ENET1_MDC 0x06000020 + IMX8QXP_ENET0_MDIO_CONN_ENET1_MDIO 0x06000020 + IMX8QXP_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT 0x06000020 + IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x06000020 + IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x06000020 + IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER 0x06000020 + IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x06000020 + IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x06000020 + IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x06000020 + IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x06000020 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-a0.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-a0.dts new file mode 100644 index 00000000000000..74695fd4a8e030 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-a0.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qxp-lpddr4-val.dts" + +&vpu_encoder { + status = "disabled"; +}; + +&vpu_decoder { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-gpmi-nand.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-gpmi-nand.dts new file mode 100644 index 00000000000000..369c942694e656 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-gpmi-nand.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017 NXP + */ + +#include "imx8qxp-lpddr4-val.dts" + +&iomuxc { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_NAND_READY_B 0x0e00004c + IMX8QXP_EMMC0_DATA0_CONN_NAND_DATA00 0x0e00004c + IMX8QXP_EMMC0_DATA1_CONN_NAND_DATA01 0x0e00004c + IMX8QXP_EMMC0_DATA2_CONN_NAND_DATA02 0x0e00004c + IMX8QXP_EMMC0_DATA3_CONN_NAND_DATA03 0x0e00004c + IMX8QXP_EMMC0_DATA4_CONN_NAND_DATA04 0x0e00004c + IMX8QXP_EMMC0_DATA5_CONN_NAND_DATA05 0x0e00004c + IMX8QXP_EMMC0_DATA6_CONN_NAND_DATA06 0x0e00004c + IMX8QXP_EMMC0_DATA7_CONN_NAND_DATA07 0x0e00004c + IMX8QXP_EMMC0_STROBE_CONN_NAND_CLE 0x0e00004c + IMX8QXP_EMMC0_RESET_B_CONN_NAND_WP_B 0x0e00004c + + IMX8QXP_USDHC1_DATA0_CONN_NAND_CE1_B 0x0e00004c + IMX8QXP_USDHC1_DATA2_CONN_NAND_WE_B 0x0e00004c + IMX8QXP_USDHC1_DATA3_CONN_NAND_ALE 0x0e00004c + IMX8QXP_USDHC1_CMD_CONN_NAND_CE0_B 0x0e00004c + + /* i.MX8QXP NAND use nand_re_dqs_pins */ + IMX8QXP_USDHC1_CD_B_CONN_NAND_DQS 0x0e00004c + IMX8QXP_USDHC1_VSELECT_CONN_NAND_RE_B 0x0e00004c + + >; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +/* Disabled the usdhc1/usdhc2 since pin conflict */ +&usdhc1 { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi-slave.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi-slave.dts new file mode 100644 index 00000000000000..ef997e2f936160 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi-slave.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017~2019 NXP + */ + +#include "imx8qxp-lpddr4-val-lpspi.dts" + +/delete-node/&spidev0; + +&pinctrl_lpspi2 { + fsl,pins = < + IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x600004c + IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x600004c + IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x600004c + IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0 0x600004c + >; +}; + +&lpspi2 { + #address-cells = <0>; + pinctrl-0 = <&pinctrl_lpspi2>; + /delete-property/ cs-gpios; + spi-slave; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi.dts new file mode 100644 index 00000000000000..bc4535647fc43e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017~2019 NXP + */ + +#include "imx8qxp-lpddr4-val.dts" + +&iomuxc { + pinctrl_lpspi0: lpspi0grp { + fsl,pins = < + IMX8QXP_SPI0_SCK_ADMA_SPI0_SCK 0x600004c + IMX8QXP_SPI0_SDO_ADMA_SPI0_SDO 0x600004c + IMX8QXP_SPI0_SDI_ADMA_SPI0_SDI 0x600004c + >; + }; + + pinctrl_lpspi0_cs: lpspi0cs { + fsl,pins = < + IMX8QXP_SPI0_CS0_LSIO_GPIO1_IO08 0x21 + >; + }; + + pinctrl_lpspi2: lpspi2grp { + fsl,pins = < + IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x600004c + IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x600004c + IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x600004c + IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0 0x600004c + >; + }; +}; + +&lpspi0 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>; + cs-gpios = <&lsio_gpio1 8 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash: at45db041e@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <5000000>; + reg = <0>; + }; +}; + +&lpspi2 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mlb.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mlb.dts new file mode 100644 index 00000000000000..f4a180867eae7c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mlb.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017~2019 NXP + */ + +#include "imx8qxp-lpddr4-val.dts" + +&esai0 { + status = "disabled"; +}; + +&mlb { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mqs.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mqs.dts new file mode 100644 index 00000000000000..dacf725d2487db --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mqs.dts @@ -0,0 +1,60 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8qxp-lpddr4-val.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-mqs { + compatible = "fsl,imx8qxp-lpddr4-arm2-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + cpu-dai = <&sai1>; + audio-codec = <&mqs>; + asrc-controller = <&asrc1>; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_mqs: mqsgrp { + fsl,pins = < + IMX8QXP_SPDIF0_TX_ADMA_MQS_L 0xc6000061 + IMX8QXP_SPDIF0_RX_ADMA_MQS_R 0xc6000061 + >; + }; +}; + +&mqs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-spdif.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-spdif.dts new file mode 100644 index 00000000000000..81ec0d0e9b98dc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-spdif.dts @@ -0,0 +1,56 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8qxp-lpddr4-val.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif0>; + spdif-in; + spdif-out; + }; +}; + +&iomuxc { + pinctrl_spdif0: spdif0grp { + fsl,pins = < + IMX8QXP_SPDIF0_TX_ADMA_SPDIF0_TX 0xc6000040 + IMX8QXP_SPDIF0_RX_ADMA_SPDIF0_RX 0xc6000040 + >; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&spdif0 { + compatible = "fsl,imx8qm-spdif"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif0>; + assigned-clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&spdif0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts new file mode 100755 index 00000000000000..e53b7e67020222 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts @@ -0,0 +1,541 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017~2018 NXP + */ + +/dts-v1/; + +#include +#include "imx8qxp.dtsi" + +/ { + model = "Freescale i.MX8QXP LPDDR4 Validation Board"; + compatible = "fsl,imx8qxp-lpddr4-val", "fsl,imx8qxp"; + + chosen { + stdout-path = &lpuart0; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + + rpmsg_dma_reserved:rpmsg_dma@0x90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x100000>; + }; + + decoder_boot: decoder-boot@84000000 { + reg = <0 0x84000000 0 0x2000000>; + no-map; + }; + + encoder_boot: encoder-boot@86000000 { + reg = <0 0x86000000 0 0x200000>; + no-map; + }; + + decoder_rpc: decoder-rpc@0x92000000 { + reg = <0 0x92000000 0 0x200000>; + no-map; + }; + + encoder_rpc: encoder-rpc@0x92200000 { + reg = <0 0x92200000 0 0x200000>; + no-map; + }; + + encoder_reserved: encoder_reserved@94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + }; + + reg_can_en: regulator-can-en { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_usdhc2_vmmc: usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator-usbotg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pca9557_b 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_audio: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&cs42888>; + asrc-controller = <&asrc0>; + status = "okay"; + }; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&asrc1 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + status = "okay"; +}; + +&sai4 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai4_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai5 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai5_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + nvmem-cells = <&fec_mac0>; + nvmem-cell-names = "mac-address"; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + status = "disabled"; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&mlb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mlb>; + status = "disabled"; +}; + +&usbphy1 { + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usb3phynop1 { + status = "okay"; +}; + +&usbotg3 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 497>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&irqsteer_csi0 { + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&i2c_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_mipi_csi0>; + clock-frequency = <100000>; + status = "okay"; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_a 2 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>, <24576000>; + }; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 { + fsl,pins = < + IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 + IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 + IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 + IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 + IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 + IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 + IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 + IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 + IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 + IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 + IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 + IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 + IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 + IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins = < + IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 + IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; +}; + + pinctrl_lpi2c3: lpi2cgrp { + fsl,pins = < + IMX8QXP_SPI3_CS1_ADMA_I2C3_SCL 0x06000020 + IMX8QXP_MCLK_IN1_ADMA_I2C3_SDA 0x06000020 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 + IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_mlb: mlbgrp { + fsl,pins = < + IMX8QXP_ESAI0_SCKT_CONN_MLB_SIG 0x21 + IMX8QXP_ESAI0_FST_CONN_MLB_CLK 0x21 + IMX8QXP_ESAI0_TX0_CONN_MLB_DATA 0x21 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 + IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 + IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 + >; + }; + + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-a0.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-a0.dts new file mode 100644 index 00000000000000..16b0261ded57d1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-a0.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qxp-mek.dts" + +&vpu_encoder { + status = "disabled"; +}; + +&vpu_decoder { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-dom0.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dom0.dts new file mode 100644 index 00000000000000..9cd0ea20937f2a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dom0.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qxp-mek-rpmsg.dts" + +/ { + chosen { + #address-cells = <2>; + #size-cells = <2>; + + stdout-path = &lpuart0; + + module@0 { + bootargs = "earlycon=xen console=hvc0 root=/dev/mmcblk1p2 rootwait rw"; + compatible = "xen,linux-zimage", "xen,multiboot-module"; + /* The size will be override by uboot command */ + reg = <0x00000000 0x80a00000 0x00000000 0xf93a00>; + }; + + }; + + reserved-memory { + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x30000000>; + alloc-ranges = <0 0xb0000000 0 0x40000000>; + linux,cma-default; + }; + }; + + rtc0: rtc@23000000 { + interrupts = ; + xen,passthrough; + }; +}; + +&imx8_gpu_ss { + reg = <0xa8000000 0x58000000>, <0x0 0x10000000>; + status = "okay"; +}; + +&lsio_mu1 { + /* not map for dom0, dom0 will mmio trap to xen */ + xen,no-map; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif-rpmsg.dts new file mode 100644 index 00000000000000..24a37064267489 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif-rpmsg.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8qxp-mek-rpmsg.dts" +#include "imx8x-mek-dpu-lcdif.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif.dts new file mode 100644 index 00000000000000..2d3bd4eb2c896d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8qxp-mek.dts" +#include "imx8x-mek-dpu-lcdif.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191-rpmsg.dts new file mode 100644 index 00000000000000..614705c26b39c8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191-rpmsg.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8qxp-mek-dsi-rm67191.dts" +#include "imx8x-mek-rpmsg.dtsi" + diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191.dts new file mode 100644 index 00000000000000..d17639e0afd64b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191.dts @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qxp-mek.dts" + +/delete-node/ &adv_bridge0; +/delete-node/ &adv_bridge1; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&ldb2_phy { + status = "disabled"; +}; + +&ldb2 { + status = "disabled"; +}; + +&lvds_bridge0 { + status = "disabled"; +}; + +&lvds_bridge1 { + status = "disabled"; +}; + +&mipi0_dphy { + status = "okay"; +}; + +&mipi0_dsi_host { + status = "okay"; + fsl,clock-drop-level = <2>; + + panel@0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "raydium,rm67191"; + reg = <0>; + reset-gpios = <&pca9557_a 6 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; + width-mm = <68>; + height-mm = <121>; + + port@0 { + reg = <0>; + panel0_in: endpoint { + remote-endpoint = <&mipi0_panel_out>; + }; + }; + }; + + ports { + /delete-node/ port@1; + + port@1 { + reg = <1>; + mipi0_panel_out: endpoint { + remote-endpoint = <&panel0_in>; + }; + }; + }; +}; + +&mipi1_dphy { + status = "okay"; +}; + +&mipi1_dsi_host { + status = "okay"; + fsl,clock-drop-level = <2>; + + panel@0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "raydium,rm67191"; + reg = <0>; + reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; + width-mm = <68>; + height-mm = <121>; + + port@0 { + reg = <0>; + panel1_in: endpoint { + remote-endpoint = <&mipi1_panel_out>; + }; + }; + }; + + ports { + /delete-node/ port@1; + + port@1 { + reg = <1>; + mipi1_panel_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsp.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsp.dts new file mode 100644 index 00000000000000..1ed49861de3c1c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsp.dts @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2018 + +#include "imx8qxp-mek-rpmsg.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-wm8960 { + status = "disabled"; + }; + + dspaudio: dspaudio { + compatible = "fsl,dsp-audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + status = "okay"; + }; + + sound-dsp { + compatible = "fsl,imx-dsp-audio"; + model = "dsp-audio"; + cpu-dai = <&dspaudio>; + audio-codec = <&cs42888>; + audio-platform = <&dsp>; + }; +}; + +&edma0 { + compatible = "fsl,imx8qm-edma"; + reg = <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x592e0000 0x10000>, /* sai1 rx */ + <0x592f0000 0x10000>, /* sai1 tx */ + <0x59350000 0x10000>, + <0x59370000 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <8>; + interrupts = , /* spdif0 */ + , + , /* sai0 */ + , + , /* sai1 */ + , + , + ; + interrupt-names = "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ + "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ + "edma0-chan21-tx", /* gpt5 */ + "edma0-chan23-rx"; /* gpt7 */ + power-domains = <&pd IMX_SC_R_DMA_0_CH8>, + <&pd IMX_SC_R_DMA_0_CH9>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>, + <&pd IMX_SC_R_DMA_0_CH21>, + <&pd IMX_SC_R_DMA_0_CH23>; + power-domain-names = "edma0-chan8", "edma0-chan9", + "edma0-chan12", "edma0-chan13", + "edma0-chan14", "edma0-chan15", + "edma0-chan21", "edma0-chan23"; + status = "okay"; +}; + +&dsp { + compatible = "fsl,imx8qxp-dsp-v1"; + reserved-region = <&dsp_reserved>; + reg = <0x596e8000 0x88000>; + clocks = <&esai0_lpcg 1>, + <&esai0_lpcg 0>, + <&asrc0_lpcg 0>, + <&clk_dummy>, + <&aud_pll_div0_lpcg 0>, + <&aud_pll_div1_lpcg 0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>; + clock-names = "esai_ipg", "esai_mclk", "asrc_ipg", "asrc_mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3"; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>, + <&esai0_lpcg 0>; + audio-interface = "esai"; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + fsl,dsp-firmware = "imx/dsp/hifi4.bin"; + power-domains = <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_IRQSTR_DSP>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>, + <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_DMA_0_CH6>, + <&pd IMX_SC_R_DMA_0_CH7>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_DMA_0_CH0>, + <&pd IMX_SC_R_DMA_0_CH1>, + <&pd IMX_SC_R_DMA_0_CH2>, + <&pd IMX_SC_R_DMA_0_CH3>, + <&pd IMX_SC_R_DMA_0_CH4>, + <&pd IMX_SC_R_DMA_0_CH5>; +}; + +&esai0 { + status = "disabled"; +}; + +&asrc0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&wm8960 { + status = "disabled"; +}; + +&cs42888 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2-tja1100.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2-tja1100.dts new file mode 100644 index 00000000000000..7651dc6fa68237 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2-tja1100.dts @@ -0,0 +1,16 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8qxp-mek-enet2.dts" +#include "imx8qxp-enet2-tja1100.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2.dts new file mode 100644 index 00000000000000..2a77456c74dad2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2.dts @@ -0,0 +1,27 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8qxp-mek.dts" + +&esai0 { + status = "disabled"; +}; + +ðphy1 { + status = "okay"; +}; + +&fec2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-inmate.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-inmate.dts new file mode 100644 index 00000000000000..89669251f81cd5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-inmate.dts @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "Freescale i.MX8QXP MEK Inmate"; + compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; + interrupt-parent = <&gic>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + aliases { + mmc0 = &usdhc1; + serial2 = &lpuart2; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x2>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x3>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + scu { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", "tx1", "tx2", "tx3", + "rx0", "rx1", "rx2", "rx3", + "gip3"; + mboxes = <&lsio_mu2 0 0 + &lsio_mu2 0 1 + &lsio_mu2 0 2 + &lsio_mu2 0 3 + &lsio_mu2 1 0 + &lsio_mu2 1 1 + &lsio_mu2 1 2 + &lsio_mu2 1 3 + &lsio_mu2 3 3>; + + pd: imx8qx-pd { + compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + }; + + clk: clock-controller { + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; + #clock-cells = <2>; + clocks = <&xtal32k &xtal24m>; + clock-names = "xtal_32KHz", "xtal_24Mhz"; + }; + + iomuxc: pinctrl { + compatible = "fsl,imx8qxp-iomuxc"; + }; + }; + + soc { + compatible = "fsl,imx8qxp-soc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + xtal32k: clock-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xtal_24MHz"; + }; + + pci@fd700000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 70 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 71 IRQ_TYPE_EDGE_RISING>, + <0 0 0 3 &gic GIC_SPI 72 IRQ_TYPE_EDGE_RISING>, + <0 0 0 4 &gic GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xfd700000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + /* For early console */ + serial@5a060000 { + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x0 0x5a060000 0x0 0x1000>; + }; + + #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-adma.dtsi" + #include "imx8-ss-conn.dtsi" +}; + +#include "imx8qxp-ss-lsio.dtsi" +#include "imx8qxp-ss-adma.dtsi" +#include "imx8qxp-ss-conn.dtsi" + +&edma0 { + status = "disabled"; +}; + +&edma1 { + status = "disabled"; +}; + +&acm { + status = "disabled"; +}; + +&iomuxc { + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 + IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&lsio_mu1 { + status = "disabled"; +}; + +&lsio_mu2 { + status = "okay"; +}; + +&lsio_gpio0 { + status = "disabled"; +}; + +&lsio_gpio1 { + status = "disabled"; +}; + +&lsio_gpio2 { + status = "disabled"; +}; + +&lsio_gpio3 { + status = "disabled"; +}; + +&lsio_gpio4 { + status = "disabled"; +}; + +&lsio_gpio5 { + status = "disabled"; +}; + +&lsio_gpio6 { + status = "disabled"; +}; + +&lsio_gpio7 { + status = "disabled"; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; + /delete-property/ dma-names; + /delete-property/ dmas; +}; + +/delete-node/ &lpuart0; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel-rpmsg.dts new file mode 100644 index 00000000000000..8debd826171b69 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel-rpmsg.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8qxp-mek-rpmsg.dts" +#include "imx8x-mek-it6263-lvds0-dual-channel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel.dts new file mode 100644 index 00000000000000..07bb468e227d02 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019,2020 NXP + */ + +#include "imx8qxp-mek.dts" +#include "imx8x-mek-it6263-lvds0-dual-channel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel-rpmsg.dts new file mode 100644 index 00000000000000..26cead50be3c57 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel-rpmsg.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8qxp-mek-rpmsg.dts" +#include "imx8x-mek-it6263-lvds1-dual-channel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel.dts new file mode 100644 index 00000000000000..406047eb5cd06a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019,2020 NXP + */ + +#include "imx8qxp-mek.dts" +#include "imx8x-mek-it6263-lvds1-dual-channel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel-rpmsg.dts new file mode 100644 index 00000000000000..8903d2d99a6689 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel-rpmsg.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8qxp-mek-rpmsg.dts" +#include "imx8x-mek-jdi-wuxga-lvds0-panel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel.dts new file mode 100644 index 00000000000000..5027beb1cef069 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019,2020 NXP + */ + +#include "imx8qxp-mek.dts" +#include "imx8x-mek-jdi-wuxga-lvds0-panel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel-rpmsg.dts new file mode 100644 index 00000000000000..01560ad50724cf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel-rpmsg.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8qxp-mek-rpmsg.dts" +#include "imx8x-mek-jdi-wuxga-lvds1-panel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel.dts new file mode 100644 index 00000000000000..1982c4afa84f7d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019,2020 NXP + */ + +#include "imx8qxp-mek.dts" +#include "imx8x-mek-jdi-wuxga-lvds1-panel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-rpmsg.dts new file mode 100644 index 00000000000000..b3e60868970189 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-rpmsg.dts @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2020 +#include "imx8qxp-mek-ov5640.dts" +#include "imx8x-mek-rpmsg.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640.dts new file mode 100644 index 00000000000000..2ceac305f7accc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640.dts @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2019 + +#include "imx8qxp-mek.dts" + +&isi_1 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_2 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_3 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + /delete-property/virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <1 2>; + }; + }; +}; + +&i2c_mipi_csi0 { + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&xtal24m>; + clock-names = "xclk"; + csi_id = <0>; + powerdown-gpios = <&lsio_gpio3 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&lsio_gpio3 8 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_mipi_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2>; + clocks-lanes = <0>; + }; + }; + }; + + /delete-node/max9286_mipi@6a; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-root.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-root.dts new file mode 100644 index 00000000000000..5f4ee5adbec897 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-root.dts @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2019 + +#include "imx8qxp-mek-rpmsg.dts" + +/ { + domu { + /* + * There are 5 MUs, 0A is used by root cell, 1A is used + * by ATF, so for non-root cell, 2A/3A/4A could be used. + * SC_R_MU_0A + * SC_R_MU_1A + * SC_R_MU_2A + * SC_R_MU_3A + * SC_R_MU_4A + * The rsrcs and pads will be configured by uboot scu_rm cmd + */ + #address-cells = <1>; + #size-cells = <0>; + doma { + /* + * This is not for domu, this is just reuse + * the method for jailhouse inmate non root cell + * Linux. + */ + compatible = "xen,domu"; + /* + * The reg property will be updated by U-Boot to + * reflect the partition id. + */ + reg = <0>; + init_on_rsrcs = < + IMX_SC_R_MU_2A + >; + rsrcs = < + IMX_SC_R_SDHC_0 + IMX_SC_R_UART_2 + IMX_SC_R_MU_2A + >; + pads = < + /* emmc */ + IMX8QXP_EMMC0_CLK + IMX8QXP_EMMC0_CMD + IMX8QXP_EMMC0_DATA0 + IMX8QXP_EMMC0_DATA1 + IMX8QXP_EMMC0_DATA2 + IMX8QXP_EMMC0_DATA3 + IMX8QXP_EMMC0_DATA4 + IMX8QXP_EMMC0_DATA5 + IMX8QXP_EMMC0_DATA6 + IMX8QXP_EMMC0_DATA7 + IMX8QXP_EMMC0_STROBE + /* lpuart2 */ + IMX8QXP_UART2_TX + IMX8QXP_UART2_RX + >; + }; + }; + +}; + +&{/reserved-memory} { + + jh_reserved: jh@fdc00000 { + no-map; + reg = <0x0 0xfdc00000 0x0 0x400000>; + }; + + loader_reserved: loader@fdb00000 { + no-map; + reg = <0x0 0xfdb00000 0x0 0x00100000>; + }; + + ivshmem_reserved: ivshmem@fd900000 { + no-map; + reg = <0x0 0xfd900000 0x0 0x00200000>; + }; + + pci_reserved: pci@fd700000 { + no-map; + reg = <0x0 0xfd700000 0x0 0x00200000>; + }; + + /* Decrease if no need such big memory */ + inmate_reserved: inmate@df7000000 { + no-map; + reg = <0x0 0xdf700000 0x0 0x1e000000>; + }; +}; + +&usdhc1 { + /delete-property/ compatible; +}; + +&lpuart2 { + /* Let inmate linux use this for console */ + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-rpmsg.dts new file mode 100644 index 00000000000000..412f32a4b8b8df --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-rpmsg.dts @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2019 + +#include "imx8qxp-mek.dts" +#include "imx8x-mek-rpmsg.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-cs42888.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-cs42888.dts new file mode 100644 index 00000000000000..dcfdbed0ebff35 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-cs42888.dts @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2018 + +#include "imx8qxp-mek-rpmsg.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-wm8960 { + status = "disabled"; + }; + + esai0_port: esai-port { + #sound-dai-cells = <0>; + compatible = "fsl,esai-dai"; + + dai-index = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + + power-domains = <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_DMA_0_CH6>, + <&pd IMX_SC_R_DMA_0_CH7>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>; + + clocks = <&esai0_lpcg 1>, <&esai0_lpcg 0>, <&esai0_lpcg 1>, + <&clk_dummy>; + clock-names = "core", "extal", "fsys", "spba"; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + status="okay"; + }; + + sof-audio-cs42888 { + compatible = "simple-audio-card"; + label = "imx-cs42888"; + simple-audio-card,widgets = + "Line", "Line Out Jack", + "Line", "Line In Jack"; + simple-audio-card,routing = + "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "Line In Jack", + "AIN1R", "Line In Jack", + "AIN2L", "Line In Jack", + "AIN2R", "Line In Jack", + "Playback", "ESAI0.OUT"; + status = "okay"; + simple-audio-card,dai-link { + format = "i2s"; + cpu { + sound-dai = <&esai0_port>; + }; + plat { + sound-dai = <&dsp>; + }; + codec { + sound-dai = <&cs42888>; + }; + }; + }; +}; + +&edma0 { + compatible = "fsl,imx8qm-edma"; + reg = <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x592e0000 0x10000>, /* sai1 rx */ + <0x592f0000 0x10000>, /* sai1 tx */ + <0x59350000 0x10000>, + <0x59370000 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <8>; + interrupts = , /* spdif0 */ + , + , /* sai0 */ + , + , /* sai1 */ + , + , + ; + interrupt-names = "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ + "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ + "edma0-chan21-tx", /* gpt5 */ + "edma0-chan23-rx"; /* gpt7 */ + power-domains = <&pd IMX_SC_R_DMA_0_CH8>, + <&pd IMX_SC_R_DMA_0_CH9>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>, + <&pd IMX_SC_R_DMA_0_CH21>, + <&pd IMX_SC_R_DMA_0_CH23>; + power-domain-names = "edma0-chan8", "edma0-chan9", + "edma0-chan12", "edma0-chan13", + "edma0-chan14", "edma0-chan15", + "edma0-chan21", "edma0-chan23"; + status = "okay"; +}; + +&dsp { + #sound-dai-cells = <0>; + compatible = "fsl,imx8qxp-dsp"; + reg = <0x596e8000 0x88000>; + tplg-name = "sof-imx8qxp-cs42888.tplg"; + machine-drv-name = "asoc-simple-card"; + status = "okay"; +}; + +&amix { + status = "disabled"; +}; + +&esai0 { + status = "disabled"; +}; + +&asrc0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&wm8960 { + status = "disabled"; +}; + +&cs42888 { + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-wm8960.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-wm8960.dts new file mode 100644 index 00000000000000..a8dc94e4565e01 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-wm8960.dts @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2018 + +#include "imx8qxp-mek-rpmsg.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-wm8960 { + status = "disabled"; + }; + + sai1_port: sai-port { + #sound-dai-cells = <0>; + compatible = "fsl,sai-dai"; + + dai-index = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + + power-domains = <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>; + + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + clocks = <&sai1_lpcg 1>, <&clk_dummy>, <&sai1_lpcg 0>, + <&clk_dummy>, <&clk_dummy>; + assigned-clocks = <&acm IMX_ADMA_ACM_SAI1_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>, + <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + status="okay"; + }; + + sof-sound-wm8960 { + compatible = "simple-audio-card"; + label = "wm8960-audio"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + hp-det-gpio = <&lsio_gpio1 0 0>; + mic-det-gpio = <&lsio_gpio1 0 0>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Speaker", "Ext Spk", + "Microphone", "Mic Jack"; + simple-audio-card,audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Mic Jack", + "RINPUT2", "Mic Jack", + "Playback", "SAI1.OUT", + "SAI1.IN", "Capture"; + simple-audio-card,dai-link { + format = "i2s"; + cpu { + sound-dai = <&sai1_port>; + }; + plat { + sound-dai = <&dsp>; + }; + sndcodec: codec { + sound-dai = <&wm8960>; + }; + }; + }; +}; + +&edma0 { + compatible = "fsl,imx8qm-edma"; + reg = <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x59350000 0x10000>, + <0x59370000 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <6>; + interrupts = , /* spdif0 */ + , + , /* sai0 */ + , + , + ; + interrupt-names = "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ + "edma0-chan21-tx", /* gpt5 */ + "edma0-chan23-rx"; /* gpt7 */ + + power-domains = <&pd IMX_SC_R_DMA_0_CH8>, + <&pd IMX_SC_R_DMA_0_CH9>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH21>, + <&pd IMX_SC_R_DMA_0_CH23>; + power-domain-names = "edma0-chan8", "edma0-chan9", + "edma0-chan12", "edma0-chan13", + "edma0-chan21", "edma0-chan23"; + status = "okay"; +}; + +&dsp { + #sound-dai-cells = <0>; + compatible = "fsl,imx8qxp-dsp"; + reg = <0x596e8000 0x88000>; + tplg-name = "sof-imx8qxp-wm8960.tplg"; + machine-drv-name = "asoc-simple-card"; + status = "okay"; +}; + +&wm8960 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&amix { + status = "disabled"; +}; + +&esai0 { + status = "disabled"; +}; + +&asrc0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&cs42888 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 8148196902dd53..715a52a5abbecd 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -1,231 +1,14 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2017~2018 NXP + * Copyright 2017-2020 NXP */ /dts-v1/; #include "imx8qxp.dtsi" +#include "imx8x-mek.dtsi" / { model = "Freescale i.MX8QXP MEK"; compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; - - chosen { - stdout-path = &adma_lpuart0; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x40000000>; - }; - - reg_usdhc2_vmmc: usdhc2-vmmc { - compatible = "regulator-fixed"; - regulator-name = "SD1_SPWR"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&adma_lpuart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart0>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; - -&adma_i2c1 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; - status = "okay"; - - i2c-switch@71 { - compatible = "nxp,pca9646", "nxp,pca9546"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - max7322: gpio@68 { - compatible = "maxim,max7322"; - reg = <0x68>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - pressure-sensor@60 { - compatible = "fsl,mpl3115"; - reg = <0x60>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - pca9557_a: gpio@1a { - compatible = "nxp,pca9557"; - reg = <0x1a>; - gpio-controller; - #gpio-cells = <2>; - }; - - pca9557_b: gpio@1d { - compatible = "nxp,pca9557"; - reg = <0x1d>; - gpio-controller; - #gpio-cells = <2>; - }; - - light-sensor@44 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_isl29023>; - compatible = "isil,isl29023"; - reg = <0x44>; - interrupt-parent = <&lsio_gpio1>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - }; - }; - }; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <8>; - no-sd; - no-sdio; - non-removable; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; - wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 - IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 - IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 - IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 - IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 - IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 - IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 - IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 - IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 - IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 - IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 - IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 - IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 - IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 - >; - }; - - pinctrl_ioexp_rst: ioexp_rst_grp { - fsl,pins = < - IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 - >; - }; - - pinctrl_isl29023: isl29023grp { - fsl,pins = < - IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021 - >; - }; - - pinctrl_lpi2c1: lpi2c1grp { - fsl,pins = < - IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 - IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 - >; - }; - - pinctrl_lpuart0: lpuart0grp { - fsl,pins = < - IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 - IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 - IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 - IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 - IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 - IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 - IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 - IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 - IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 - IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 - IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 - IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 - IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 - IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 - IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 - IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 - >; - }; -}; - -&adma_dsp { - status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi new file mode 100644 index 00000000000000..096df87e0c9981 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + * Dong Aisheng + */ + +&dma_ipg_clk { + clock-frequency = <160000000>; +}; + +&audio_ipg_clk { + clock-frequency = <160000000>; +}; + +&lpuart0 { + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; +}; + +&lpuart1 { + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; +}; + +&lpuart2 { + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; +}; + +&lpuart3 { + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; +}; + +&i2c0 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&i2c1 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&i2c2 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&i2c3 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&audio_subsys { + + dsp: dsp@596e8000 { + compatible = "fsl,imx8qxp-dsp"; + reg = <0x596e8000 0x88000>; + clocks = <&dsp_lpcg 1>, + <&dsp_ram_lpcg 0>, + <&dsp_lpcg 2>; + clock-names = "ipg", "ocram", "core"; + fsl,dsp-firmware = "imx/dsp/hifi4.bin"; + power-domains = <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>, + <&pd IMX_SC_R_IRQSTR_DSP>; + mbox-names = "txdb0", "txdb1", + "rxdb0", "rxdb1"; + mboxes = <&lsio_mu13 2 0>, + <&lsio_mu13 2 1>, + <&lsio_mu13 3 0>, + <&lsio_mu13 3 1>; + status = "disabled"; + }; +}; + +&dma_subsys { + lcdif_mux_regs: mux-regs@5a170000 { + compatible = "fsl,imx8qxp-lcdif-mux-regs", "syscon"; + reg = <0x5a170000 0x4>; + }; + + adma_pwm: pwm@5a190000 { + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; + reg = <0x5a190000 0x1000>; + clocks = <&adma_pwm_lpcg 0>, <&adma_pwm_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>; + status = "disabled"; + }; + + adma_pwm_lpcg: clock-controller@5a590000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a590000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "adma_pwm_lpcg_clk", + "adma_pwm_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi new file mode 100644 index 00000000000000..f8ad22a7d1e22c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + * Dong Aisheng + */ + +&usdhc1 { + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; +}; + +&usdhc2 { + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; +}; + +&fec1 { + compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec"; +}; + +&fec2 { + compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi new file mode 100644 index 00000000000000..a929c3a2341a70 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019 NXP + */ + +&dpu1 { + compatible = "fsl,imx8qxp-dpu"; + + dpu_disp0: port@0 { + reg = <0>; + + dpu_disp0_ldb1_ch0: endpoint@0 { + remote-endpoint = <&ldb1_ch0>; + }; + + dpu_disp0_ldb1_ch1: endpoint@1 { + remote-endpoint = <&ldb1_ch1>; + }; + + dpu_disp0_mipi_dsi: endpoint@2 { + remote-endpoint = <&mipi0_dsi_in>; + }; + }; + + dpu_disp1: port@1 { + reg = <1>; + + dpu_disp1_ldb2_ch0: endpoint@0 { + remote-endpoint = <&ldb2_ch0>; + }; + + dpu_disp1_ldb2_ch1: endpoint@1 { + remote-endpoint = <&ldb2_ch1>; + }; + + dpu_disp1_mipi_dsi: endpoint@2 { + remote-endpoint = <&mipi1_dsi_in>; + }; + + dpu_disp1_lcdif: endpoint@3 { + }; + }; +}; + +/ { + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu_disp0>, <&dpu_disp1>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-gpu.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-gpu.dtsi new file mode 100644 index 00000000000000..424a25582434cf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-gpu.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +&gpu0_subsys { + imx8_gpu_ss: imx8_gpu0_ss { + compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss"; + cores = <&gpu_3d0>; + reg = <0x80000000 0x80000000>, <0x0 0x10000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi new file mode 100644 index 00000000000000..4fae19e5edb43b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + * Richard Zhu + */ + +&hsio_subsys { + phyx1_lpcg: clock-controller@5f090000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f090000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_refb_clk>, <&hsio_per_clk>, + <&hsio_per_clk>, <&hsio_per_clk>; + bit-offset = <0 4 8 16>; + clock-output-names = "hsio_phyx1_pclk", + "hsio_phyx1_epcs_tx_clk", + "hsio_phyx1_epcs_rx_clk", + "hsio_phyx1_apb_clk"; + power-domains = <&pd IMX_SC_R_SERDES_1>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi new file mode 100644 index 00000000000000..b455ed6fc483bd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +&csi1_pxl_lpcg { + status = "disabled"; +}; + +&csi1_core_lpcg { + status = "disabled"; +}; + +&csi1_esc_lpcg { + status = "disabled"; +}; + +&irqsteer_csi1 { + status = "disabled"; +}; + +&i2c_mipi_csi1 { + status = "disabled"; +}; + +&gpio0_mipi_csi1 { + status = "disabled"; +}; + +&mipi_csi_1 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi new file mode 100644 index 00000000000000..48ffdb001a337a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + * Dong Aisheng + */ + +&lsio_gpio0 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio1 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio2 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio3 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio4 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio5 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio6 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio7 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +}; + +&lsio_mu0 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu1 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu2 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu3 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu4 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi new file mode 100644 index 00000000000000..c8b5468f2d86c9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi @@ -0,0 +1,425 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019 NXP + */ + +/ { + lvds_subsys: bus@56220000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x56220000 0x0 0x56220000 0x30000>; + + mipi_ipg_clk: clock-mipi-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "mipi_ipg_clk"; + }; + + mipi_pll_div2_clk: clock-mipi-div2-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <432000000>; + clock-output-names = "mipi_pll_div2_clk"; + }; + + mipi0_lis_lpcg: clock-controller@56223000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223000 0x4>; + #clock-cells = <1>; + clocks = <&mipi_ipg_clk>; + bit-offset = <16>; + clock-output-names = "mipi0_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + mipi0_pwm_lpcg: clock-controller@5622300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5622300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>, + <&mipi_ipg_clk>, + <&mipi_ipg_clk>; + bit-offset = <0 16 4>; + clock-output-names = "mipi0_pwm_lpcg_clk", + "mipi0_pwm_lpcg_ipg_clk", + "mipi0_pwm_lpcg_32k_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>; + }; + + mipi0_i2c0_lpcg: clock-controller@56223010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223010 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&mipi_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "mipi0_i2c0_lpcg_clk", + "mipi0_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + }; + + mipi1_lis_lpcg: clock-controller@56243000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243000 0x4>; + #clock-cells = <1>; + clocks = <&mipi_ipg_clk>; + bit-offset = <16>; + clock-output-names = "mipi1_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1>; + }; + + mipi1_pwm_lpcg: clock-controller@5624300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5624300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>, + <&mipi_ipg_clk>, + <&mipi_ipg_clk>; + bit-offset = <0 16 4>; + clock-output-names = "mipi1_pwm_lpcg_clk", + "mipi1_pwm_lpcg_ipg_clk", + "mipi1_pwm_lpcg_32k_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>; + }; + + mipi1_i2c0_lpcg: clock-controller@56243010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243010 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>, + <&mipi_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "mipi1_i2c0_lpcg_clk", + "mipi1_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + }; + + irqsteer_mipi_lvds0: irqsteer@56220000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x56220000 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&mipi0_lis_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + lvds_region1: lvds_region@56221000 { + compatible = "syscon"; + reg = <0x56221000 0xf0>; + }; + + ldb1_phy: ldb_phy@56221000 { + compatible = "mixel,lvds-combo-phy"; + reg = <0x56221000 0x100>, <0x56228000 0x1000>; + #phy-cells = <0>; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC3>; + clock-names = "phy"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + status = "disabled"; + }; + + ldb1: ldb@562210e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass", + "aux_pixel", "aux_bypass"; + power-domains = <&pd IMX_SC_R_LVDS_0>, + <&pd IMX_SC_R_LVDS_1>; + power-domain-names = "main", "aux"; + gpr = <&lvds_region1>; + fsl,auxldb = <&ldb2>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb1_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_ch0: endpoint { + remote-endpoint = <&dpu_disp0_ldb1_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb1_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_ch1: endpoint { + remote-endpoint = <&dpu_disp0_ldb1_ch1>; + }; + }; + }; + }; + + pwm_mipi_lvds0: pwm@56224000 { + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; + reg = <0x56224000 0x1000>; + clocks = <&mipi0_pwm_lpcg 0>, + <&mipi0_pwm_lpcg 1>, + <&mipi0_pwm_lpcg 2>; + clock-names = "per", "ipg", "32k"; + assigned-clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>; + status = "disabled"; + }; + + i2c0_mipi_lvds0: i2c@56226000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56226000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_mipi_lvds0>; + clocks = <&mipi0_i2c0_lpcg 0>, + <&mipi0_i2c0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + status = "disabled"; + }; + + mipi0_dphy: dphy@56228300 { + compatible = "fsl,imx8qm-mipi-dphy"; + reg = <0x56228300 0x100>; + clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>; + clock-names = "phy_ref"; + #phy-cells = <0>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + status = "disabled"; + }; + + mipi0_dsi_host: dsi_host@56228000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qx-nwl-dsi"; + reg = <0x56228000 0x300>; + clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_MST_BUS>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_SLV_BUS>, + <&mipi_pll_div2_clk>; + clock-names = "pixel", + "bypass", + "phy_ref", + "tx_esc", + "rx_esc", + "phy_parent"; + interrupts = <16>; + interrupt-parent = <&irqsteer_mipi_lvds0>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + phys = <&mipi0_dphy>; + phy-names = "dphy"; + csr = <&lvds_region1>; + use-disp-ss; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + mipi0_dsi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dpu_disp0_mipi_dsi>; + }; + }; + }; + }; + + irqsteer_mipi_lvds1: irqsteer@56240000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x56240000 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&mipi1_lis_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_MIPI_1>; + }; + + lvds_region2: lvds_region@56241000 { + compatible = "syscon"; + reg = <0x56241000 0xf0>; + }; + + ldb2_phy: ldb_phy@56241000 { + compatible = "mixel,lvds-combo-phy"; + reg = <0x56241000 0x100>, <0x56248000 0x1000>; + #phy-cells = <0>; + clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC3>; + clock-names = "phy"; + power-domains = <&pd IMX_SC_R_LVDS_1>; + status = "disabled"; + }; + + ldb2: ldb@562410e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass", + "aux_pixel", "aux_bypass"; + power-domains = <&pd IMX_SC_R_LVDS_1>, + <&pd IMX_SC_R_LVDS_0>; + power-domain-names = "main", "aux"; + gpr = <&lvds_region2>; + fsl,auxldb = <&ldb1>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb2_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_ch0: endpoint { + remote-endpoint = <&dpu_disp1_ldb2_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb2_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_ch1: endpoint { + remote-endpoint = <&dpu_disp1_ldb2_ch1>; + }; + }; + }; + }; + + pwm_mipi_lvds1: pwm@56244000 { + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; + reg = <0x56244000 0x1000>; + clocks = <&mipi1_pwm_lpcg 0>, + <&mipi1_pwm_lpcg 1>, + <&mipi1_pwm_lpcg 2>; + clock-names = "per", "ipg", "32k"; + assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>; + status = "disabled"; + }; + + i2c0_mipi_lvds1: i2c@56246000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56246000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_mipi_lvds1>; + clocks = <&mipi1_i2c0_lpcg 0>, + <&mipi1_i2c0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + status = "disabled"; + }; + + mipi1_dphy: dphy@56248300 { + compatible = "fsl,imx8qx-mipi-dphy"; + reg = <0x56248300 0x100>; + clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>; + clock-names = "phy_ref"; + #phy-cells = <0>; + power-domains = <&pd IMX_SC_R_MIPI_1>; + status = "disabled"; + }; + + mipi1_dsi_host: dsi_host@56248000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qx-nwl-dsi"; + reg = <0x56248000 0x300>; + clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_MST_BUS>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_SLV_BUS>, + <&mipi_pll_div2_clk>; + clock-names = "pixel", + "bypass", + "phy_ref", + "tx_esc", + "rx_esc", + "phy_parent"; + interrupts = <16>; + interrupt-parent = <&irqsteer_mipi_lvds1>; + power-domains = <&pd IMX_SC_R_MIPI_1>; + phys = <&mipi1_dphy>; + phy-names = "dphy"; + csr = <&lvds_region2>; + use-disp-ss; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + mipi1_dsi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dpu_disp1_mipi_dsi>; + }; + }; + }; + }; + + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 1133b412182aba..2fa28b89d52a4c 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP + * Copyright 2017-2019 NXP * Dong Aisheng */ @@ -9,7 +9,9 @@ #include #include #include +#include #include +#include / { interrupt-parent = <&gic>; @@ -17,6 +19,8 @@ #size-cells = <2>; aliases { + ethernet0 = &fec1; + ethernet1 = &fec2; gpio0 = &lsio_gpio0; gpio1 = &lsio_gpio1; gpio2 = &lsio_gpio2; @@ -25,17 +29,40 @@ gpio5 = &lsio_gpio5; gpio6 = &lsio_gpio6; gpio7 = &lsio_gpio7; + dpu0 = &dpu1; + ldb0 = &ldb1; + ldb1 = &ldb2; mmc0 = &usdhc1; mmc1 = &usdhc2; mmc2 = &usdhc3; mu1 = &lsio_mu1; - serial0 = &adma_lpuart0; - serial1 = &adma_lpuart1; - serial2 = &adma_lpuart2; - serial3 = &adma_lpuart3; + serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + isi0 = &isi_0; + isi1 = &isi_1; + isi2 = &isi_2; + isi3 = &isi_3; + isi4 = &isi_4; + isi5 = &isi_5; + isi6 = &isi_6; + isi7 = &isi_7; + csi0 = &mipi_csi_0; + can0 = &flexcan1; + can1 = &flexcan2; + can2 = &flexcan3; + i2c1 = &i2c_rpbus_1; + i2c5 = &i2c_rpbus_5; + i2c12 = &i2c_rpbus_12; + i2c13 = &i2c_rpbus_13; + i2c14 = &i2c_rpbus_14; + i2c15 = &i2c_rpbus_15; + mipi_dsi0 = &mipi0_dsi_host; + mipi_dsi1 = &mipi1_dsi_host; }; - cpus { + cpus: cpus { #address-cells = <2>; #size-cells = <0>; @@ -46,7 +73,7 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&A35_L2>; - clocks = <&clk IMX_A35_CLK>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; #cooling-cells = <2>; }; @@ -57,7 +84,7 @@ reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&A35_L2>; - clocks = <&clk IMX_A35_CLK>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; #cooling-cells = <2>; }; @@ -68,7 +95,7 @@ reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&A35_L2>; - clocks = <&clk IMX_A35_CLK>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; #cooling-cells = <2>; }; @@ -79,7 +106,7 @@ reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&A35_L2>; - clocks = <&clk IMX_A35_CLK>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; #cooling-cells = <2>; }; @@ -152,9 +179,16 @@ &lsio_mu1 1 3 &lsio_mu1 3 3>; + pd: imx8qx-pd { + compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + wakeup-irq = <235 236 237 258 262 267 271 + 345 346 347 348>; + }; + clk: clock-controller { - compatible = "fsl,imx8qxp-clk"; - #clock-cells = <1>; + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; + #clock-cells = <2>; clocks = <&xtal32k &xtal24m>; clock-names = "xtal_32KHz", "xtal_24Mhz"; }; @@ -167,21 +201,40 @@ compatible = "fsl,imx8qxp-scu-ocotp"; #address-cells = <1>; #size-cells = <1>; - }; + read-only; - pd: imx8qx-pd { - compatible = "fsl,imx8qxp-scu-pd"; - #power-domain-cells = <1>; + fec_mac0: mac@2c4 { + reg = <0x2c4 6>; + }; + + fec_mac1: mac@2c6 { + reg = <0x2c6 6>; + }; }; rtc: rtc { compatible = "fsl,imx8qxp-sc-rtc"; }; + secvio: secvio { + compatible = "fsl,imx-sc-secvio"; + nvmem = <&ocotp>; + }; + watchdog { compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; timeout-sec = <60>; }; + + tsens: thermal-sensor { + compatible = "fsl,imx8qxp-sc-thermal"; + tsens-num = <2>; + #thermal-sensor-cells = <1>; + }; + }; + + soc { + compatible = "fsl,imx8qxp-soc"; }; timer { @@ -192,6 +245,43 @@ ; /* Hypervisor */ }; + thermal_zones: thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 355>; + trips { + cpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + xtal32k: clock-xtal32k { compatible = "fixed-clock"; #clock-cells = <0>; @@ -206,395 +296,71 @@ clock-output-names = "xtal_24MHz"; }; - adma_subsys: bus@59000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x59000000 0x0 0x59000000 0x2000000>; - - adma_lpcg: clock-controller@59000000 { - compatible = "fsl,imx8qxp-lpcg-adma"; - reg = <0x59000000 0x2000000>; - #clock-cells = <1>; - }; - - adma_dsp: dsp@596e8000 { - compatible = "fsl,imx8qxp-dsp"; - reg = <0x596e8000 0x88000>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>; - clock-names = "ipg", "ocram", "core"; - power-domains = <&pd IMX_SC_R_MU_13A>, - <&pd IMX_SC_R_MU_13B>, - <&pd IMX_SC_R_DSP>, - <&pd IMX_SC_R_DSP_RAM>; - mbox-names = "txdb0", "txdb1", - "rxdb0", "rxdb1"; - mboxes = <&lsio_mu13 2 0>, - <&lsio_mu13 2 1>, - <&lsio_mu13 3 0>, - <&lsio_mu13 3 1>; - memory-region = <&dsp_reserved>; - status = "disabled"; - }; - - adma_lpuart0: serial@5a060000 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x5a060000 0x1000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; - clock-names = "ipg", "baud"; - power-domains = <&pd IMX_SC_R_UART_0>; - status = "disabled"; - }; - - adma_lpuart1: serial@5a070000 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x5a070000 0x1000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; - clock-names = "ipg", "baud"; - power-domains = <&pd IMX_SC_R_UART_1>; - status = "disabled"; - }; - - adma_lpuart2: serial@5a080000 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x5a080000 0x1000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; - clock-names = "ipg", "baud"; - power-domains = <&pd IMX_SC_R_UART_2>; - status = "disabled"; - }; - - adma_lpuart3: serial@5a090000 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x5a090000 0x1000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; - clock-names = "ipg", "baud"; - power-domains = <&pd IMX_SC_R_UART_3>; - status = "disabled"; - }; - - adma_i2c0: i2c@5a800000 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x5a800000 0x4000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; - clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_0>; - status = "disabled"; - }; - - adma_i2c1: i2c@5a810000 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x5a810000 0x4000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; - clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_1>; - status = "disabled"; - }; - - adma_i2c2: i2c@5a820000 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x5a820000 0x4000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; - clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_2>; - status = "disabled"; - }; - - adma_i2c3: i2c@5a830000 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x5a830000 0x4000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; - clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_3>; - status = "disabled"; - }; + imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; }; - conn_subsys: bus@5b000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; - - conn_lpcg: clock-controller@5b200000 { - compatible = "fsl,imx8qxp-lpcg-conn"; - reg = <0x5b200000 0xb0000>; - #clock-cells = <1>; - }; - - usdhc1: mmc@5b010000 { - compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; - interrupt-parent = <&gic>; - interrupts = ; - reg = <0x5b010000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; - clock-names = "ipg", "per", "ahb"; - assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; - assigned-clock-rates = <200000000>; - power-domains = <&pd IMX_SC_R_SDHC_0>; - status = "disabled"; - }; - - usdhc2: mmc@5b020000 { - compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; - interrupt-parent = <&gic>; - interrupts = ; - reg = <0x5b020000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; - clock-names = "ipg", "per", "ahb"; - assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; - assigned-clock-rates = <200000000>; - power-domains = <&pd IMX_SC_R_SDHC_1>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - status = "disabled"; - }; - - usdhc3: mmc@5b030000 { - compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; - interrupt-parent = <&gic>; - interrupts = ; - reg = <0x5b030000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; - clock-names = "ipg", "per", "ahb"; - assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>; - assigned-clock-rates = <200000000>; - power-domains = <&pd IMX_SC_R_SDHC_2>; - status = "disabled"; - }; - - fec1: ethernet@5b040000 { - compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; - reg = <0x5b040000 0x10000>; - interrupts = , - , - , - ; - clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; - clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; - power-domains = <&pd IMX_SC_R_ENET_0>; - status = "disabled"; - }; - - fec2: ethernet@5b050000 { - compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; - reg = <0x5b050000 0x10000>; - interrupts = , - , - , - ; - clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; - clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; - power-domains = <&pd IMX_SC_R_ENET_1>; - status = "disabled"; - }; + rpmsg: rpmsg{ + compatible = "fsl,imx8qxp-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu5 0 1 + &lsio_mu5 1 1 + &lsio_mu5 3 1>; + mub-partition = <3>; + status = "disabled"; }; - ddr_subsyss: bus@5c000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; - - ddr-pmu@5c020000 { - compatible = "fsl,imx8-ddr-pmu"; - reg = <0x5c020000 0x10000>; - interrupt-parent = <&gic>; - interrupts = ; - }; + sc_pwrkey: sc-powerkey { + compatible = "fsl,imx8-pwrkey"; + linux,keycode = ; + wakeup-source; }; - lsio_subsys: bus@5d000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; - - lsio_gpio0: gpio@5d080000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d080000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_0>; - }; - - lsio_gpio1: gpio@5d090000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d090000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_1>; - }; - - lsio_gpio2: gpio@5d0a0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0a0000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_2>; - }; - - lsio_gpio3: gpio@5d0b0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0b0000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_3>; - }; - - lsio_gpio4: gpio@5d0c0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0c0000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_4>; - }; - - lsio_gpio5: gpio@5d0d0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0d0000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_5>; - }; - - lsio_gpio6: gpio@5d0e0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0e0000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_6>; - }; - - lsio_gpio7: gpio@5d0f0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0f0000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_7>; - }; - - lsio_mu0: mailbox@5d1b0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1b0000 0x10000>; - interrupts = ; - #mbox-cells = <2>; - status = "disabled"; - }; - - lsio_mu1: mailbox@5d1c0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1c0000 0x10000>; - interrupts = ; - #mbox-cells = <2>; - }; - - lsio_mu2: mailbox@5d1d0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1d0000 0x10000>; - interrupts = ; - #mbox-cells = <2>; - status = "disabled"; - }; - - lsio_mu3: mailbox@5d1e0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1e0000 0x10000>; - interrupts = ; - #mbox-cells = <2>; - status = "disabled"; - }; + /* sorted in register address */ + #include "imx8-ss-security.dtsi" + #include "imx8-ss-cm40.dtsi" + #include "imx8-ss-vpu.dtsi" + #include "imx8-ss-dc0.dtsi" + #include "imx8-ss-adma.dtsi" + #include "imx8-ss-conn.dtsi" + #include "imx8-ss-ddr.dtsi" + #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-hsio.dtsi" + #include "imx8-ss-img.dtsi" + #include "imx8-ss-gpu0.dtsi" +}; - lsio_mu4: mailbox@5d1f0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1f0000 0x10000>; - interrupts = ; - #mbox-cells = <2>; - status = "disabled"; - }; +#include "imx8qxp-ss-adma.dtsi" +#include "imx8qxp-ss-conn.dtsi" +#include "imx8qxp-ss-lsio.dtsi" +#include "imx8qxp-ss-hsio.dtsi" +#include "imx8qxp-ss-img.dtsi" +#include "imx8qxp-ss-dc.dtsi" +#include "imx8qxp-ss-lvds.dtsi" +#include "imx8qxp-ss-gpu.dtsi" + +&edma2 { + status = "okay"; +}; - lsio_mu13: mailbox@5d280000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d280000 0x10000>; - interrupts = ; - #mbox-cells = <2>; - power-domains = <&pd IMX_SC_R_MU_13A>; - }; +&A35_0 { + operating-points = < + /* kHz uV*/ + /* voltage is maintained by SCFW, so no need here */ + 1200000 0 + 900000 0 + >; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + clock-latency = <61036>; + #cooling-cells = <2>; +}; - lsio_lpcg: clock-controller@5d400000 { - compatible = "fsl,imx8qxp-lpcg-lsio"; - reg = <0x5d400000 0x400000>; - #clock-cells = <1>; - }; - }; +&dsp { + memory-region = <&dsp_reserved>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8x-17x17-val.dtsi b/arch/arm64/boot/dts/freescale/imx8x-17x17-val.dtsi new file mode 100644 index 00000000000000..7a609d29836a68 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-17x17-val.dtsi @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include "imx8x-val.dtsi" + +/ { + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x14000000>; + alloc-ranges = <0 0x96000000 0 0x14000000>; + linux,cma-default; + }; + }; + + regulators { + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&pca9557_a 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&iomuxc { + imx8qxp-lpddr4-arm2 { + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + >; + }; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + /delete-node/ gpio@68; + /delete-node/ typec@3d; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c2 { + status = "disabled"; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + /delete-node/ gpio@18; + /delete-node/ gpio@19; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c_mipi_csi0 { + status = "disabled"; +}; + +&mipi_csi_0 { + status = "disabled"; +}; + +&gpio0_mipi_csi0 { + status = "disabled"; +}; + +&pcieb{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + disable-gpio = <&pca9557_a 5 GPIO_ACTIVE_LOW>; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + epdev_on-supply = <&epdev_on>; + status = "okay"; +}; + +&usdhc2 { + status = "disabled"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + /delete-node/ mt35xu512aba@0; + + flash0: mt25qu512abb@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt25qu512abb"; + spi-max-frequency = <29000000>; + }; +}; + +&adc0 { + status = "disabled"; +}; + +&usbotg1 { + /delete-property/ pinctrl-names; + /delete-property/ pinctrl-0; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek-dpu-lcdif.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek-dpu-lcdif.dtsi new file mode 100644 index 00000000000000..d4fe033cb939fe --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-mek-dpu-lcdif.dtsi @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/ { + panel { + compatible = "sii,43wvf1g"; + backlight = <&lcdif_backlight>; + status = "okay"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + display@disp1 { + compatible = "fsl,imx-lcdif-mux-display"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; + clock-names = "bypass_div", "pixel"; + assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; + assigned-clock-parents = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>; + fsl,lcdif-mux-regs = <&lcdif_mux_regs>; + fsl,interface-pix-fmt = "rgb666"; + power-domains = <&pd IMX_SC_R_LCD_0>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&dpu_disp1_lcdif>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + lcdif_backlight: lcdif-backlight { + compatible = "pwm-backlight"; + pwms = <&adma_pwm 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; +}; + +&dpu_disp1_lcdif { + remote-endpoint = <&lcd_display_in>; +}; + +&iomuxc { + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x40000000 + >; + }; +}; + +&sai1 { + status = "disabled"; +}; + +&esai0 { + status = "disabled"; +}; + +&lpuart1 { + status = "disabled"; +}; + +&adma_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdifpwm>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds0-dual-channel.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds0-dual-channel.dtsi new file mode 100644 index 00000000000000..fc09e0f65ca7db --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds0-dual-channel.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +&i2c0_mipi_lvds0 { + lvds-to-hdmi-bridge@4c { + split-mode; + }; +}; + +&ldb1 { + fsl,dual-channel; +}; + +&ldb2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds1-dual-channel.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds1-dual-channel.dtsi new file mode 100644 index 00000000000000..77e32fd2826e1e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds1-dual-channel.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +&i2c0_mipi_lvds1 { + lvds-to-hdmi-bridge@4c { + split-mode; + }; +}; + +&ldb1 { + status = "disabled"; +}; + +&ldb2 { + fsl,dual-channel; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds0-panel.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds0-panel.dtsi new file mode 100644 index 00000000000000..51a744ed8ba1be --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds0-panel.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +/ { + lvds0_panel { + compatible = "jdi,tx26d202vm0bwa"; + backlight = <&lvds_backlight1>; + + port { + panel_lvds0_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +/delete-node/ &it6263_0_in; + +&ldb1 { + fsl,dual-channel; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_lvds0_in>; + }; + }; + }; +}; + +&ldb2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds1-panel.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds1-panel.dtsi new file mode 100644 index 00000000000000..58255c03b8542f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds1-panel.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +/ { + lvds1_panel { + compatible = "jdi,tx26d202vm0bwa"; + backlight = <&lvds_backlight0>; + + port { + panel_lvds1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +/delete-node/ &it6263_1_in; + +&ldb2 { + fsl,dual-channel; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_lvds1_in>; + }; + }; + }; +}; + +&ldb1 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek-rpmsg.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek-rpmsg.dtsi new file mode 100644 index 00000000000000..47243b55d06bcc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-mek-rpmsg.dtsi @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/delete-node/ &cm40_i2c; +/delete-node/ &i2c1; + +&i2c_rpbus_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x50>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + usb_con1: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "source"; + data-role = "dual"; + source-pdos = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&i2c_rpbus_5 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_b 1 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + fsl,txs-rxm; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_parallel_csi>; + clocks = <&pi0_misc_lpcg 0>; + assigned-clocks = <&pi0_misc_lpcg 0>; + assigned-clock-rates = <24000000>; + clock-names = "xclk"; + powerdown-gpios = <&lsio_gpio3 2 GPIO_ACTIVE_HIGH>; + reset-gpios = <&lsio_gpio3 3 GPIO_ACTIVE_LOW>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <¶llel_csi_ep>; + bus-type = <5>; /* V4L2_FWNODE_BUS_TYPE_PARALLEL */ + bus-width = <8>; + vsync-active = <0>; + hsync-active = <1>; + pclk-sample = <1>; + }; + }; + }; +}; + +&i2c_rpbus_12 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c_rpbus_14 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + fxos8700@1e { + compatible = "fsl,fxos8700"; + reg = <0x1e>; + interrupt-open-drain; + }; + + fxas2100x@21 { + compatible = "fsl,fxas2100x"; + reg = <0x21>; + interrupt-open-drain; + }; + + pressure-sensor@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + interrupt-open-drain; + }; +}; + +&i2c_rpbus_15 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pca9557_a: gpio@1a { + compatible = "nxp,pca9557"; + reg = <0x1a>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@1d { + compatible = "nxp,pca9557"; + reg = <0x1d>; + gpio-controller; + #gpio-cells = <2>; + }; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <2 2>; + }; +}; + +&cm40_i2c_lpcg { + status = "disabled"; +}; + +&i2c1_lpcg { + status = "disabled"; +}; + +&can0_lpcg { + status = "disabled"; +}; + +®_can_en { + status = "disabled"; +}; + +®_can_stby { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&cm40_intmux { + status = "disabled"; +}; + +&flexspi0 { + status = "disabled"; +}; + +&lpuart3 { + status = "disabled"; +}; + +&uart3_lpcg { + status = "disabled"; +}; + +&imx8x_cm4 { + /* Assume you have partitioned M4, so M4 is ont controled by Linux */ + /delete-property/ power-domains; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek.dtsi new file mode 100644 index 00000000000000..80ac2b39a4d789 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-mek.dtsi @@ -0,0 +1,1495 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2020 NXP + */ + +#include +/ { + chosen { + stdout-path = &lpuart0; + }; + + brcmfmac: brcmfmac { + compatible = "cypress,brcmfmac"; + pinctrl-names = "init", "idle", "default"; + pinctrl-0 = <&pinctrl_wifi_init>; + pinctrl-1 = <&pinctrl_wifi_init>; + pinctrl-2 = <&pinctrl_wifi>; + }; + + lvds_backlight0: lvds_backlight@0 { + compatible = "pwm-backlight"; + pwms = <&pwm_mipi_lvds0 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + lvds_backlight1: lvds_backlight@1 { + compatible = "pwm-backlight"; + pwms = <&pwm_mipi_lvds1 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&pca9557_a 1 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + cbtl04gp { + compatible = "nxp,cbtl04gp"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec_mux>; + switch-gpios = <&lsio_gpio5 9 GPIO_ACTIVE_LOW>; + reset-gpios = <&pca9557_a 7 GPIO_ACTIVE_HIGH>; + orientation-switch; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90200000 0 0x200000>; + }; + + decoder_boot: decoder-boot@84000000 { + reg = <0 0x84000000 0 0x2000000>; + no-map; + }; + + encoder_boot: encoder-boot@86000000 { + reg = <0 0x86000000 0 0x200000>; + no-map; + }; + + decoder_rpc: decoder-rpc@0x92000000 { + reg = <0 0x92000000 0 0x200000>; + no-map; + }; + + encoder_rpc: encoder-rpc@0x92200000 { + reg = <0 0x92200000 0 0x200000>; + no-map; + }; + encoder_reserved: encoder_reserved@94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + }; + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + }; + + reg_usdhc2_vmmc: usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <3480>; + enable-active-high; + }; + + reg_can_en: regulator-can-en { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator-usbotg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pca9557_b 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_audio: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&cs42888>; + asrc-controller = <&asrc0>; + status = "okay"; + }; + + sound-wm8960 { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai1>; + audio-codec = <&wm8960>; + codec-master; + /* + * hp-det = ; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <2 0>; + hp-det-gpios = <&lsio_gpio1 0 0>; + mic-det-gpios = <&lsio_gpio1 0 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Main MIC", + "RINPUT2", "Main MIC", + "Mic Jack", "MICB", + "Main MIC", "MICB", + "Playback", "CPU-Playback", + "CPU-Capture", "Capture"; + }; + + imx8x_cm4: imx8x_cm4@0 { + compatible = "fsl,imx8qxp-cm4"; + rsc-da = <0x90000000>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu5 0 1 + &lsio_mu5 1 1 + &lsio_mu5 3 1>; + mub-partition = <3>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>, + <&vdev1vring0>, <&vdev1vring1>; + core-index = <0>; + core-id = ; + status = "okay"; + power-domains = <&pd IMX_SC_R_M4_0_PID0>, + <&pd IMX_SC_R_M4_0_MU_1A>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + vdev0vring0: vdev0vring0@90000000 { + compatible = "shared-dma-pool"; + reg = <0 0x90000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@90008000 { + compatible = "shared-dma-pool"; + reg = <0 0x90008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@90010000 { + compatible = "shared-dma-pool"; + reg = <0 0x90010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@90018000 { + compatible = "shared-dma-pool"; + reg = <0 0x90018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer { + compatible = "shared-dma-pool"; + reg = <0 0x90400000 0 0x100000>; + no-map; + }; + }; + +}; + +&cm40_i2c { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_cm40_i2c>; + pinctrl-1 = <&pinctrl_cm40_i2c_gpio>; + scl-gpios = <&lsio_gpio1 10 GPIO_ACTIVE_HIGH>; + sda-gpios = <&lsio_gpio1 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_b 1 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + fsl,txs-rxm; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_parallel_csi>; + clocks = <&pi0_misc_lpcg 0>; + assigned-clocks = <&pi0_misc_lpcg 0>; + assigned-clock-rates = <24000000>; + clock-names = "xclk"; + powerdown-gpios = <&lsio_gpio3 2 GPIO_ACTIVE_HIGH>; + reset-gpios = <&lsio_gpio3 3 GPIO_ACTIVE_LOW>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <¶llel_csi_ep>; + bus-type = <5>; /* V4L2_FWNODE_BUS_TYPE_PARALLEL */ + bus-width = <8>; + vsync-active = <0>; + hsync-active = <1>; + pclk-sample = <1>; + }; + }; + }; +}; + +&cm40_intmux { + status = "okay"; +}; + +&dc0_pc { + status = "okay"; +}; + +&dc0_prg1 { + status = "okay"; +}; + +&dc0_prg2 { + status = "okay"; + +}; + +&dc0_prg3 { + status = "okay"; +}; + +&dc0_prg4 { + status = "okay"; +}; + +&dc0_prg5 { + status = "okay"; +}; + +&dc0_prg6 { + status = "okay"; +}; + +&dc0_prg7 { + status = "okay"; +}; + +&dc0_prg8 { + status = "okay"; +}; + +&dc0_prg9 { + status = "okay"; +}; + +&dc0_dpr1_channel1 { + status = "okay"; +}; + +&dc0_dpr1_channel2 { + status = "okay"; +}; + +&dc0_dpr1_channel3 { + status = "okay"; +}; + +&dc0_dpr2_channel1 { + status = "okay"; +}; + +&dc0_dpr2_channel2 { + status = "okay"; +}; + +&dc0_dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&pwm_mipi_lvds0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_mipi_lvds0>; + status = "okay"; +}; + +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; + status = "okay"; + + lvds_bridge0: lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + reset-gpios = <&pca9557_a 6 GPIO_ACTIVE_LOW>; + + port { + it6263_0_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + adv_bridge0: adv7535@3d { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port@0 { + reg = <0>; + adv7535_0_in: endpoint { + remote-endpoint = <&mipi0_adv_out>; + }; + }; + }; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&mipi0_dphy { + status = "okay"; +}; + +&mipi0_dsi_host { + status = "okay"; + + ports { + port@1 { + reg = <1>; + mipi0_adv_out: endpoint { + remote-endpoint = <&adv7535_0_in>; + }; + }; + }; +}; + +&pwm_mipi_lvds1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_mipi_lvds1>; + status = "okay"; +}; + +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; + clock-frequency = <100000>; + status = "okay"; + + lvds_bridge1: lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; + + port { + it6263_1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; + + adv_bridge1: adv7535@3d { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + interrupt-parent = <&lsio_gpio2>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port@0 { + reg = <0>; + adv7535_1_in: endpoint { + remote-endpoint = <&mipi1_adv_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&mipi1_dphy { + status = "okay"; +}; + +&mipi1_dsi_host { + status = "okay"; + + ports { + port@1 { + reg = <1>; + mipi1_adv_out: endpoint { + remote-endpoint = <&adv7535_1_in>; + }; + }; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "okay"; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; +}; + +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&dsp { + compatible = "fsl,imx8qxp-dsp-v1"; + status = "okay"; +}; + +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + fsl,txm-rxs; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&sai4 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai4_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai5 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai5_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + nvmem-cells = <&fec_mac0>; + nvmem-cell-names = "mac-address"; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + status = "disabled"; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + nvmem-cells = <&fec_mac1>; + nvmem-cell-names = "mac-address"; + fsl,rgmii_rxc_dly; + status = "disabled"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9646", "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + fxos8700@1e { + compatible = "fsl,fxos8700"; + reg = <0x1e>; + interrupt-open-drain; + }; + + fxas2100x@21 { + compatible = "fsl,fxas2100x"; + reg = <0x21>; + interrupt-open-drain; + }; + + pressure-sensor@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + interrupt-open-drain; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + pca9557_a: gpio@1a { + compatible = "nxp,pca9557"; + reg = <0x1a>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@1d { + compatible = "nxp,pca9557"; + reg = <0x1d>; + gpio-controller; + #gpio-cells = <2>; + }; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + }; + }; + }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x50>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + usb_con1: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "source"; + data-role = "dual"; + source-pdos = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&pcieb{ + compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + disable-gpio = <&pca9557_a 2 GPIO_ACTIVE_LOW>; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + reserved-region = <&rpmsg_reserved>; + status = "okay"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + memory-region = <&vdevbuffer>; + status = "disabled"; +}; + +&usbphy1 { + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usb3phynop1 { + status = "okay"; +}; + +&usbotg3 { + dr_mode = "otg"; + extcon = <&ptn5110>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&vpu_decoder { + boot-region = <&decoder_boot>; + rpc-region = <&decoder_rpc>; + reg-csr = <0x2d040000>; + core_type = <1>; + status = "okay"; +}; + +&vpu_encoder { + boot-region = <&encoder_boot>; + rpc-region = <&encoder_rpc>; + reserved-region = <&encoder_reserved>; + reg-rpc-system = <0x40000000>; + resolution-max = <1920 1920>; + mbox-names = "enc1_tx0", "enc1_tx1", "enc1_rx"; + mboxes = <&mu1_m0 0 0 + &mu1_m0 0 1 + &mu1_m0 1 0>; + status = "okay"; + + core0@1020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x1020000 0x20000>; + reg-csr = <0x1050000 0x10000>; + interrupts = ; + fsl,vpu_ap_mu_id = <17>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; + + m2m_device { + status = "okay"; + }; +}; + +&isi_1 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_2 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_3 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_4 { + interface = <6 0 2>; + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&irqsteer_csi0 { + status = "okay"; +}; + + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&cameradev { + parallel_csi; + status = "okay"; +}; + +¶llel_csi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port@0 { + reg = <0>; + parallel_csi_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&jpegdec { + status = "okay"; +}; + +&jpegenc { + status = "okay"; +}; + +&i2c_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_mipi_csi0>; + clock-frequency = <100000>; + status = "okay"; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&lsio_gpio3 7 GPIO_ACTIVE_HIGH>; + virtual-channel; + status = "okay"; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 497>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + >; + }; + + pinctrl_cm40_i2c: cm40i2cgrp { + fsl,pins = < + IMX8QXP_ADC_IN1_M40_I2C0_SDA 0x0600004c + IMX8QXP_ADC_IN0_M40_I2C0_SCL 0x0600004c + >; + }; + + pinctrl_cm40_i2c_gpio: cm40i2cgrp-gpio { + fsl,pins = < + IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09 0xc600004c + IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10 0xc600004c + >; + }; + + pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { + fsl,pins = < + IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + IMX8QXP_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 0x00000020 + >; + }; + + pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { + fsl,pins = < + IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x00000020 + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 + IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 + IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 + IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 + IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 + IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 + IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 + IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 + IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 + IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 + IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060 + IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060 + IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060 + IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060 + IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060 + IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_ioexp_rst: ioexp_rst_grp { + fsl,pins = < + IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021 + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 + IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 + IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 + IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 + IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QXP_UART1_TX_ADMA_UART1_TX 0x06000020 + IMX8QXP_UART1_RX_ADMA_UART1_RX 0x06000020 + IMX8QXP_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 + IMX8QXP_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 + >; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 + IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 + IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 + >; + }; + + pinctrl_pcieb: pcieagrp{ + fsl,pins = < + IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 + IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + >; + }; + + pinctrl_pwm_mipi_lvds0: mipi_lvds0_pwm_grp { + fsl,pins = < + IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_pwm_mipi_lvds1: mipi_lvds1_pwm_grp { + fsl,pins = < + IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD 0x06000040 + IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC 0x06000040 + IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040 + IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD 0x06000060 + IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x06000040 + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021 + >; + }; + + pinctrl_typec_mux: typecmuxgrp { + fsl,pins = < + IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 + IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 + IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 + >; + }; + + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 { + fsl,pins = < + IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 + IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_mipi_csi0: mipi_csi0 { + fsl,pins = < + IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xC0000041 + IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xC0000041 + IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 + >; + }; + + pinctrl_parallel_csi: parallelcsigrp { + fsl,pins = < + IMX8QXP_CSI_D00_CI_PI_D02 0xC0000041 + IMX8QXP_CSI_D01_CI_PI_D03 0xC0000041 + IMX8QXP_CSI_D02_CI_PI_D04 0xC0000041 + IMX8QXP_CSI_D03_CI_PI_D05 0xC0000041 + IMX8QXP_CSI_D04_CI_PI_D06 0xC0000041 + IMX8QXP_CSI_D05_CI_PI_D07 0xC0000041 + IMX8QXP_CSI_D06_CI_PI_D08 0xC0000041 + IMX8QXP_CSI_D07_CI_PI_D09 0xC0000041 + + IMX8QXP_CSI_MCLK_CI_PI_MCLK 0xC0000041 + IMX8QXP_CSI_PCLK_CI_PI_PCLK 0xC0000041 + IMX8QXP_CSI_HSYNC_CI_PI_HSYNC 0xC0000041 + IMX8QXP_CSI_VSYNC_CI_PI_VSYNC 0xC0000041 + IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0xC0000041 + IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0xC0000041 + >; + }; + + pinctrl_wifi: wifigrp{ + fsl,pins = < + IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 + >; + }; + + pinctrl_wifi_init: wifi_initgrp{ + fsl,pins = < + /* reserve pin init/idle_state to support multiple wlan cards */ + >; + }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x00000060 + IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x00000060 + IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x00000060 + IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x00000060 + IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x00000060 + IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x00000060 + IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x00000060 + IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x00000060 + IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x00000060 + IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x00000060 + IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x00000060 + IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x00000060 + IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x00000060 + IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x00000060 + IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x00000060 + IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x00000060 + IMX8QXP_UART1_RTS_B_ADMA_LCDIF_D16 0x00000060 + IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x00000060 + IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x00000060 + IMX8QXP_SPI3_CS1_ADMA_LCDIF_RESET 0x00000060 + IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x00000060 + IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x00000060 + IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x00000060 + >; + }; + + pinctrl_lcdifpwm: lcdifpwmgrp { + fsl,pins = < + IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x00000060 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8x-val.dtsi b/arch/arm64/boot/dts/freescale/imx8x-val.dtsi new file mode 100644 index 00000000000000..d6d0274b5bf190 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-val.dtsi @@ -0,0 +1,840 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + */ + +/ { + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + off-on-delay = <2720>; + enable-active-high; + }; + + reg_can_en: regulator-can-gen { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_audio: fixedregulator@0 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_baseboard: fixedregulator@1 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "baseboard_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + gpio = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_adc_vref_1v8: adc_vref_1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&codec>; + asrc-controller = <&asrc0>; + status = "okay"; + }; +}; + +&acm { + status = "okay"; +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_adc_vref_1v8>; + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&asrc1 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&esai0 { + compatible = "fsl,imx8qm-esai"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + status = "okay"; +}; + +&sai4 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai4_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai5 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai5_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + imx8qxp-lpddr4-arm2 { + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0xc600004c + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + >; + }; + + pinctrl_adc0: adc0grp { + fsl,pins = < + IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60 + IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60 + >; + }; + + pinctrl_csi0_lpi2c0: csi0lpi2c0grp { + fsl,pins = < + IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 + IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 + IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 + IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 + IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 + IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 + IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 + IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 + IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 + IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 + IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 + IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 + IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060 + IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060 + IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060 + IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060 + IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060 + IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 + IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 + IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan2grp { + fsl,pins = < + IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 + IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 + >; + }; + + pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { + fsl,pins = < + IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + >; + }; + + pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { + fsl,pins = < + IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + >; + }; + + pinctrl_ptn5150: ptn5150 { + fsl,pins = < + IMX8QXP_SPI0_CS1_LSIO_GPIO1_IO07 0x00000021 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_lpi2c1: lpi1cgrp { + fsl,pins = < + IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 + IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 + >; + }; + + pinctrl_lpi2c3: lpi2cgrp { + fsl,pins = < + IMX8QXP_SPI3_CS1_ADMA_I2C3_SCL 0x06000020 + IMX8QXP_MCLK_IN1_ADMA_I2C3_SDA 0x06000020 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QXP_UART0_RX_ADMA_UART0_RX 0x0600002c + IMX8QXP_UART0_TX_ADMA_UART0_TX 0x0600002c + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QXP_UART1_TX_ADMA_UART1_TX 0x0600002c + IMX8QXP_UART1_RX_ADMA_UART1_RX 0x0600002c + IMX8QXP_UART1_RTS_B_ADMA_UART1_RTS_B 0x0600002c + IMX8QXP_UART1_CTS_B_ADMA_UART1_CTS_B 0x0600002c + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x0600002c + IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x0600002c + >; + }; + + pinctrl_mlb: mlbgrp { + fsl,pins = < + IMX8QXP_ESAI0_SCKT_CONN_MLB_SIG 0x21 + IMX8QXP_ESAI0_FST_CONN_MLB_CLK 0x21 + IMX8QXP_ESAI0_TX0_CONN_MLB_DATA 0x21 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 + IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 + IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_pcieb: pciebgrp{ + fsl,pins = < + IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 + IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + IMX8QXP_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_mipi_csi0_gpio: mipicsi0gpiogrp{ + fsl,pins = < + IMX8QXP_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 0x00000021 + IMX8QXP_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 0x00000021 + >; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + status = "disabled"; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "disabled"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&gpio0_mipi_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0_gpio>; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_1 { + status = "okay"; +}; + +&isi_2 { + status = "okay"; +}; + +&isi_3 { + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt35xu512aba"; + spi-max-frequency = <133000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&i2c_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + codec: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_a 2 1>; + status = "okay"; + }; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6A>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&gpio0_mipi_csi0 0 GPIO_ACTIVE_HIGH>; + virtual-channel; + status = "okay"; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + typec_ptn5150: typec@3d { + compatible = "nxp,ptn5150"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ptn5150>; + reg = <0x3d>; + connect-gpios = <&lsio_gpio1 7 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&pcieb{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&cm40_intmux { + status = "okay"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <1>; + reg = <0x0 0x90000000 0x0 0x10000>; + status = "okay"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&vpu_encoder { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi b/arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi new file mode 100644 index 00000000000000..0a68ec4c0026c4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi @@ -0,0 +1,55 @@ +/* + * QorIQ BMan SDK Portals device tree nodes + * + * Copyright 2011-2016 Freescale Semiconductor Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) + */ + +&bportals { + bman-portal@0 { + cell-index = <0>; + }; + + bman-portal@10000 { + cell-index = <1>; + }; + + bman-portal@20000 { + cell-index = <2>; + }; + + bman-portal@30000 { + cell-index = <3>; + }; + + bman-portal@40000 { + cell-index = <4>; + }; + + bman-portal@50000 { + cell-index = <5>; + }; + + bman-portal@60000 { + cell-index = <6>; + }; + + bman-portal@70000 { + cell-index = <7>; + }; + + bman-portal@80000 { + cell-index = <8>; + }; + + bman-portal@90000 { + cell-index = <9>; + }; + + bman-bpids@0 { + compatible = "fsl,bpid-range"; + fsl,bpid-range = <32 32>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi b/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi new file mode 100644 index 00000000000000..d3ae39944bf43c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi @@ -0,0 +1,72 @@ +/* + * QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x400000 ] + * + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +fsldpaa: fsl,dpaa { + compatible = "fsl,ls1043a-dpaa", "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + dma-coherent; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + dma-coherent; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + dma-coherent; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + dma-coherent; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + dma-coherent; + }; + ethernet@5 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet5>; + dma-coherent; + }; + ethernet@8 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet6>; + dma-coherent; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi index dbd2fc3ba790ee..801b6d095a2911 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi @@ -9,16 +9,17 @@ fman@1a00000 { fman0_rx_0x10: port@90000 { cell-index = <0x10>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx"; reg = <0x90000 0x1000>; fsl,fman-10g-port; }; fman0_tx_0x30: port@b0000 { cell-index = <0x30>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx"; reg = <0xb0000 0x1000>; fsl,fman-10g-port; + fsl,qman-channel-id = <0x800>; }; ethernet@f0000 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi index 6fc5d256005715..dad547c4445002 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi @@ -9,16 +9,17 @@ fman@1a00000 { fman0_rx_0x11: port@91000 { cell-index = <0x11>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx"; reg = <0x91000 0x1000>; fsl,fman-10g-port; }; fman0_tx_0x31: port@b1000 { cell-index = <0x31>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx"; reg = <0xb1000 0x1000>; fsl,fman-10g-port; + fsl,qman-channel-id = <0x801>; }; ethernet@f2000 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi index 4e02276fcf993f..60ed4473ef841b 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi @@ -9,14 +9,15 @@ fman@1a00000 { fman0_rx_0x08: port@88000 { cell-index = <0x8>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; reg = <0x88000 0x1000>; }; fman0_tx_0x28: port@a8000 { cell-index = <0x28>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; reg = <0xa8000 0x1000>; + fsl,qman-channel-id = <0x802>; }; ethernet@e0000 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi index 0312fa43fa777a..69de2c1ff0c046 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi @@ -9,14 +9,15 @@ fman@1a00000 { fman0_rx_0x09: port@89000 { cell-index = <0x9>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; reg = <0x89000 0x1000>; }; fman0_tx_0x29: port@a9000 { cell-index = <0x29>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; reg = <0xa9000 0x1000>; + fsl,qman-channel-id = <0x803>; }; ethernet@e2000 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi index af2df07971dd9b..981bbfcaaa2919 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi @@ -9,14 +9,15 @@ fman@1a00000 { fman0_rx_0x0a: port@8a000 { cell-index = <0xa>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; reg = <0x8a000 0x1000>; }; fman0_tx_0x2a: port@aa000 { cell-index = <0x2a>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; reg = <0xaa000 0x1000>; + fsl,qman-channel-id = <0x804>; }; ethernet@e4000 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi index 4ac98dc8b22793..956b1b9df6962e 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi @@ -9,14 +9,15 @@ fman@1a00000 { fman0_rx_0x0b: port@8b000 { cell-index = <0xb>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; reg = <0x8b000 0x1000>; }; fman0_tx_0x2b: port@ab000 { cell-index = <0x2b>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; reg = <0xab000 0x1000>; + fsl,qman-channel-id = <0x805>; }; ethernet@e6000 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi index bd932d8b0160ba..52899ce69580ad 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi @@ -9,14 +9,15 @@ fman@1a00000 { fman0_rx_0x0c: port@8c000 { cell-index = <0xc>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; reg = <0x8c000 0x1000>; }; fman0_tx_0x2c: port@ac000 { cell-index = <0x2c>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; reg = <0xac000 0x1000>; + fsl,qman-channel-id = <0x806>; }; ethernet@e8000 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi index 7de1c5203f3e20..fe8c4c29bb5c20 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi @@ -9,14 +9,15 @@ fman@1a00000 { fman0_rx_0x0d: port@8d000 { cell-index = <0xd>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; reg = <0x8d000 0x1000>; }; fman0_tx_0x2d: port@ad000 { cell-index = <0x2d>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; reg = <0xad000 0x1000>; + fsl,qman-channel-id = <0x807>; }; ethernet@ea000 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi new file mode 100644 index 00000000000000..2d0df20db55e6c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi @@ -0,0 +1,47 @@ +/* + * QorIQ FMan v3 OH ports device tree + * + * Copyright 2012-2015 Freescale Semiconductor Inc. + * + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) + */ + +fman@1a00000 { + + fman0_oh1: port@82000 { + cell-index = <0>; + compatible = "fsl,fman-port-oh"; + reg = <0x82000 0x1000>; + }; + + fman0_oh2: port@83000 { + cell-index = <1>; + compatible = "fsl,fman-port-oh"; + reg = <0x83000 0x1000>; + }; + + fman0_oh3: port@84000 { + cell-index = <2>; + compatible = "fsl,fman-port-oh"; + reg = <0x84000 0x1000>; + }; + + fman0_oh4: port@85000 { + cell-index = <3>; + compatible = "fsl,fman-port-oh"; + reg = <0x85000 0x1000>; + }; + + fman0_oh5: port@86000 { + cell-index = <4>; + compatible = "fsl,fman-port-oh"; + reg = <0x86000 0x1000>; + }; + + fman0_oh6: port@87000 { + cell-index = <5>; + compatible = "fsl,fman-port-oh"; + reg = <0x87000 0x1000>; + }; + +}; diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi index 263b972a6d1e9f..a10a00543d08ab 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi @@ -20,45 +20,95 @@ fman0: fman@1a00000 { fsl,qman-channel-range = <0x800 0x10>; ptimer-handle = <&ptp_timer0>; + cc { + compatible = "fsl,fman-cc"; + }; + muram@0 { compatible = "fsl,fman-muram"; reg = <0x0 0x60000>; }; + bmi@80000 { + compatible = "fsl,fman-bmi"; + reg = <0x80000 0x400>; + }; + + qmi@80400 { + compatible = "fsl,fman-qmi"; + reg = <0x80400 0x400>; + }; + fman0_oh_0x2: port@82000 { cell-index = <0x2>; compatible = "fsl,fman-v3-port-oh"; reg = <0x82000 0x1000>; + fsl,qman-channel-id = <0x809>; }; fman0_oh_0x3: port@83000 { cell-index = <0x3>; compatible = "fsl,fman-v3-port-oh"; reg = <0x83000 0x1000>; + fsl,qman-channel-id = <0x80a>; }; fman0_oh_0x4: port@84000 { cell-index = <0x4>; compatible = "fsl,fman-v3-port-oh"; reg = <0x84000 0x1000>; + fsl,qman-channel-id = <0x80b>; }; fman0_oh_0x5: port@85000 { cell-index = <0x5>; compatible = "fsl,fman-v3-port-oh"; reg = <0x85000 0x1000>; + fsl,qman-channel-id = <0x80c>; }; fman0_oh_0x6: port@86000 { cell-index = <0x6>; compatible = "fsl,fman-v3-port-oh"; reg = <0x86000 0x1000>; + fsl,qman-channel-id = <0x80d>; }; fman0_oh_0x7: port@87000 { cell-index = <0x7>; compatible = "fsl,fman-v3-port-oh"; reg = <0x87000 0x1000>; + fsl,qman-channel-id = <0x80e>; + }; + + policer@c0000 { + compatible = "fsl,fman-policer"; + reg = <0xc0000 0x1000>; + }; + + keygen@c1000 { + compatible = "fsl,fman-keygen"; + reg = <0xc1000 0x1000>; + }; + + dma@c2000 { + compatible = "fsl,fman-dma"; + reg = <0xc2000 0x1000>; + }; + + fpm@c3000 { + compatible = "fsl,fman-fpm"; + reg = <0xc3000 0x1000>; + }; + + parser@c7000 { + compatible = "fsl,fman-parser"; + reg = <0xc7000 0x1000>; + }; + + vsps@dc000 { + compatible = "fsl,fman-vsps"; + reg = <0xdc000 0x1000>; }; mdio0: mdio@fc000 { @@ -77,7 +127,7 @@ fman0: fman@1a00000 { }; ptp_timer0: ptp-timer@1afe000 { - compatible = "fsl,fman-ptp-timer"; + compatible = "fsl,fman-ptp-timer", "fsl,fman-rtc"; reg = <0x0 0x1afe000 0x0 0x1000>; interrupts = ; clocks = <&clockgen 3 0>; diff --git a/arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi b/arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi new file mode 100644 index 00000000000000..d3abfaf6efdef2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi @@ -0,0 +1,38 @@ +/* + * QorIQ QMan SDK Portals device tree nodes + * + * Copyright 2011-2016 Freescale Semiconductor Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) + */ + +&qportals { + qman-fqids@0 { + compatible = "fsl,fqid-range"; + fsl,fqid-range = <256 256>; + }; + + qman-fqids@1 { + compatible = "fsl,fqid-range"; + fsl,fqid-range = <32768 32768>; + }; + + qman-pools@0 { + compatible = "fsl,pool-channel-range"; + fsl,pool-channel-range = <0x401 0xf>; + }; + + qman-cgrids@0 { + compatible = "fsl,cgrid-range"; + fsl,cgrid-range = <0 256>; + }; + + qman-ceetm@0 { + compatible = "fsl,qman-ceetm"; + fsl,ceetm-lfqid-range = <0xf00000 0x1000>; + fsl,ceetm-sp-range = <0 16>; + fsl,ceetm-lni-range = <0 8>; + fsl,ceetm-channel-range = <0 32>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/s32v234-evb.dts b/arch/arm64/boot/dts/freescale/s32v234-evb.dts new file mode 100644 index 00000000000000..d26845a39de820 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32v234-evb.dts @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2017,2019 NXP + */ + +/dts-v1/; +#include "s32v234.dtsi" + +/ { + model = "NXP S32V234-EVB2 Board"; + compatible = "fsl,s32v234-evb", "fsl,s32v234"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&siul2 { + status = "okay"; + s32v234-evb { + + /* Format of pins: MSCR_IDX PAD_CONFIGURATION If you know the + * IMCR_IDX instead of MSCR_IDX, add 512 to it as the Reference + * Manual states. + */ + + pinctrl_can0: can0grp { + fsl,pins = < + S32V234_PAD_PA2__CAN_FD0_TXD + S32V234_PAD_PA3__CAN_FD0_RXD_OUT + S32V234_PAD_PA3__CAN_FD0_RXD_IN + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + S32V234_PAD_PA4__CAN_FD1_TXD + S32V234_PAD_PA5__CAN_FD1_RXD_OUT + S32V234_PAD_PA5__CAN_FD1_RXD_IN + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + S32V234_PAD_PA12__UART0_TXD + S32V234_PAD_PA11__UART0_RXD_OUT + S32V234_PAD_PA11__UART0_RXD_IN + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + S32V234_PAD_PA14__UART1_TXD + S32V234_PAD_PA13__UART1_RXD_OUT + S32V234_PAD_PA13__UART1_RXD_IN + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + S32V234_PAD_PK6__USDHC_CLK_OUT + S32V234_PAD_PK6__USDHC_CLK_IN + S32V234_PAD_PK7__USDHC_CMD_OUT + S32V234_PAD_PK7__USDHC_CMD_IN + S32V234_PAD_PK8__USDHC_DAT0_OUT + S32V234_PAD_PK8__USDHC_DAT0_IN + S32V234_PAD_PK9__USDHC_DAT1_OUT + S32V234_PAD_PK9__USDHC_DAT1_IN + S32V234_PAD_PK10__USDHC_DAT2_OUT + S32V234_PAD_PK10__USDHC_DAT2_IN + S32V234_PAD_PK11__USDHC_DAT3_OUT + S32V234_PAD_PK11__USDHC_DAT3_IN + S32V234_PAD_PK15__USDHC_DAT4_OUT + S32V234_PAD_PK15__USDHC_DAT4_IN + S32V234_PAD_PL0__USDHC_DAT5_OUT + S32V234_PAD_PL0__USDHC_DAT5_IN + S32V234_PAD_PL1__USDHC_DAT6_OUT + S32V234_PAD_PL1__USDHC_DAT6_IN + S32V234_PAD_PL2__USDHC_DAT7_OUT + S32V234_PAD_PL2__USDHC_DAT7_IN + >; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc0 { + no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc0>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/s32v234-sbc.dts b/arch/arm64/boot/dts/freescale/s32v234-sbc.dts new file mode 100644 index 00000000000000..a481a196992804 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32v234-sbc.dts @@ -0,0 +1,183 @@ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 MicroSys Electronics GmbH + * Copyright 2018-2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; + +#include "s32v234.dtsi" + +/ { + model = "Freescale S32V234"; + compatible = "fsl,s32v234-sbc", "fsl,s32v234"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + +&siul2 { + status = "okay"; + + s32v234-sbc { + /* Format of pins: MSCR_IDX PAD_CONFIGURATION If you know the + * IMCR_IDX instead of MSCR_IDX, add 512 to it as the Reference + * Manual states. + */ + + pinctrl_can0: can0grp { + fsl,pins = < + S32V234_PAD_PA2__CAN_FD0_TXD + S32V234_PAD_PA3__CAN_FD0_RXD_OUT + S32V234_PAD_PA3__CAN_FD0_RXD_IN + /* + * Configure pin C12 as GPIO[6] in MSCR#6. + * Effect: the S-pin at CAN is not longer + * flowting at ~0.75V, but driven to low ~0.0V. + */ + S32V234_MSCR_PA6 (PAD_CTL_MUX_MODE_ALT0 \ + | PAD_CTL_OBE \ + | PAD_CTL_DSE_34 \ + | PAD_CTL_PUS_33K_UP) + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + S32V234_PAD_PA4__CAN_FD1_TXD + S32V234_PAD_PA5__CAN_FD1_RXD_OUT + S32V234_PAD_PA5__CAN_FD1_RXD_IN + /* + * Configure pin C11 as GPIO[7] in MSCR#7. + * Effect: the S-pin at CAN is not longer + * flowting at ~0.39V, but driven to low ~0.0V. + */ + S32V234_MSCR_PA7 (PAD_CTL_MUX_MODE_ALT0 \ + | PAD_CTL_OBE \ + | PAD_CTL_DSE_34 \ + | PAD_CTL_PUS_33K_UP) + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + S32V234_PAD_PC13__MDC + S32V234_PAD_PC14__MDIO_OUT + S32v234_PAD_PC14__MDIO_IN + S32V234_PAD_PC15__TXCLK_OUT + S32V234_PAD_PC15__TXCLK_IN + S32V234_PAD_PD0__RXCLK_OUT + S32V234_PAD_PD0__RXCLK_IN + S32V234_PAD_PD1__RX_D0_OUT + S32V234_PAD_PD1__RX_D0_IN + S32V234_PAD_PD2__RX_D1_OUT + S32V234_PAD_PD2__RX_D1_IN + S32V234_PAD_PD3__RX_D2_OUT + S32V234_PAD_PD3__RX_D2_IN + S32V234_PAD_PD4__RX_D3_OUT + S32V234_PAD_PD4__RX_D3_IN + S32V234_PAD_PD4__RX_DV_OUT + S32V234_PAD_PD4__RX_DV_IN + S32V234_PAD_PD7__TX_D0_OUT + S32V234_PAD_PD8__TX_D1_OUT + S32V234_PAD_PD9__TX_D2_OUT + S32V234_PAD_PD10__TX_D3_OUT + S32V234_PAD_PD11__TX_EN_OUT + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + S32V234_PAD_PA12__UART0_TXD + S32V234_PAD_PA11__UART0_RXD_OUT + S32V234_PAD_PA11__UART0_RXD_IN + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + S32V234_PAD_PA14__UART1_TXD + S32V234_PAD_PA13__UART1_RXD_OUT + S32V234_PAD_PA13__UART1_RXD_IN + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + S32V234_PAD_PK6__USDHC_CLK_OUT + S32V234_PAD_PK6__USDHC_CLK_IN + S32V234_PAD_PK7__USDHC_CMD_OUT + S32V234_PAD_PK7__USDHC_CMD_IN + S32V234_PAD_PK8__USDHC_DAT0_OUT + S32V234_PAD_PK8__USDHC_DAT0_IN + S32V234_PAD_PK9__USDHC_DAT1_OUT + S32V234_PAD_PK9__USDHC_DAT1_IN + S32V234_PAD_PK10__USDHC_DAT2_OUT + S32V234_PAD_PK10__USDHC_DAT2_IN + S32V234_PAD_PK11__USDHC_DAT3_OUT + S32V234_PAD_PK11__USDHC_DAT3_IN + S32V234_PAD_PK15__USDHC_DAT4_OUT + S32V234_PAD_PK15__USDHC_DAT4_IN + S32V234_PAD_PL0__USDHC_DAT5_OUT + S32V234_PAD_PL0__USDHC_DAT5_IN + S32V234_PAD_PL1__USDHC_DAT6_OUT + S32V234_PAD_PL1__USDHC_DAT6_IN + S32V234_PAD_PL2__USDHC_DAT7_OUT + S32V234_PAD_PL2__USDHC_DAT7_IN + >; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc0 { + no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc0>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/dts/freescale/s32v234.dtsi new file mode 100644 index 00000000000000..47db198b36ade2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + */ + +#include +#include +#include + +/memreserve/ 0x80000000 0x00010000; + +/ { + compatible = "fsl,s32v234"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + can0 = &can0; + can1 = &can1; + serial0 = &uart0; + serial1 = &uart1; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + firc { + compatible = "fixed-clock"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + fxosc { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x80000000>; + next-level-cache = <&cluster0_l2_cache>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x80000000>; + next-level-cache = <&cluster0_l2_cache>; + }; + + cpu2: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x100>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x80000000>; + next-level-cache = <&cluster1_l2_cache>; + }; + + cpu3: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x101>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x80000000>; + next-level-cache = <&cluster1_l2_cache>; + }; + + cluster0_l2_cache: l2-cache0 { + compatible = "cache"; + }; + + cluster1_l2_cache: l2-cache1 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + /* clock-frequency might be modified by u-boot, depending on the + * chip version. + */ + clock-frequency = <10000000>; + }; + + gic: interrupt-controller@7d001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x7d001000 0 0x1000>, + <0 0x7d002000 0 0x2000>, + <0 0x7d004000 0 0x2000>, + <0 0x7d006000 0 0x2000>; + interrupts = ; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + aips0: aips-bus@40000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + reg = <0x0 0x40000000 0x0 0x7d000>; + ranges; + + fec: ethernet@40032000 { + compatible = "fsl,s32v234-fec"; + reg = <0x0 0x40032000 0x0 0x1000>; + interrupt-names = "int0", "int1", "int2", "pps"; + interrupts = , + , + , + ; + clocks = <&clks S32V234_CLK_SYS6>, + <&clks S32V234_CLK_SYS3>, + <&clks S32V234_CLK_ENET_TIME>, + <&clks S32V234_CLK_ENET>, + <&clks S32V234_CLK_ENET_TIME>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", + "enet_out"; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; + status = "disabled"; + }; + + clks: mc_cgm0@4003c000 { + compatible = "fsl,s32v234-mc_cgm0"; + reg = <0x0 0x4003C000 0x0 0x1000>; + #clock-cells = <1>; + }; + + mc_cgm1: mc_cgm1@4003F000 { + compatible = "fsl,s32v234-mc_cgm1"; + reg = <0x0 0x4003F000 0x0 0x1000>; + }; + + mc_cgm2: mc_cgm2@40042000 { + compatible = "fsl,s32v234-mc_cgm2"; + reg = <0x0 0x40042000 0x0 0x1000>; + }; + + mc_cgm3: mc_cgm3@40045000 { + compatible = "fsl,s32v234-mc_cgm3"; + reg = <0x0 0x40045000 0x0 0x1000>; + }; + + mc_me: mc_me@4004a000 { + compatible = "fsl,s32v234-mc_me"; + reg = <0x0 0x4004A000 0x0 0x1000>; + }; + + uart0: serial@40053000 { + compatible = "fsl,s32v234-linflexuart"; + reg = <0x0 0x40053000 0x0 0x1000>; + interrupts = ; + clocks = <&clks S32V234_CLK_LIN>; + clock-names = "lin"; + status = "disabled"; + }; + + can0: flexcan@40055000 { + compatible = "fsl,s32v234-flexcan"; + reg = <0x0 0x40055000 0x0 0x1000>; + interrupts = ; + clocks = <&clks S32V234_CLK_CAN>, + <&clks S32V234_CLK_CAN>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + usdhc0: usdhc@4005d000 { + compatible = "fsl,s32v234-usdhc"; + reg = <0x0 0x4005D000 0x0 0x1000>; + interrupts = <0 28 4>; + clocks = <&clks S32V234_CLK_SDHC>, + <&clks S32V234_CLK_SDHC>, + <&clks S32V234_CLK_SDHC>; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + status = "disabled"; + }; + + siul2: siul@4006c000 { + compatible = "fsl,s32v234-siul2"; + reg = <0x0 0x4006C000 0x0 0x1794>; + status = "disabled"; + }; + + src: src@4007c000 { + compatible = "fsl,s32v234-src"; + reg = <0x0 0x4007C000 0x0 0x1000>; + #reset-cells = <1>; + }; + }; + + aips1: aips-bus@40080000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + reg = <0x0 0x40080000 0x0 0x70000>; + ranges; + + uart1: serial@400bc000 { + compatible = "fsl,s32v234-linflexuart"; + reg = <0x0 0x400bc000 0x0 0x1000>; + interrupts = ; + clocks = <&clks S32V234_CLK_LIN>; + clock-names = "lin"; + status = "disabled"; + }; + + can1: flexcan@400be000 { + compatible = "fsl,s32v234-flexcan"; + reg = <0x0 0x400be000 0x0 0x1000>; + interrupts = ; + clocks = <&clks S32V234_CLK_CAN>, + <&clks S32V234_CLK_CAN>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 47cd831fcf4456..9abf0cb1dd67f6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -309,8 +309,9 @@ compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03400000 0x0 0x10000>; interrupts = ; - clocks = <&bpmp TEGRA186_CLK_SDMMC1>; - clock-names = "sdhci"; + clocks = <&bpmp TEGRA186_CLK_SDMMC1>, + <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; resets = <&bpmp TEGRA186_RESET_SDMMC1>; reset-names = "sdhci"; iommus = <&smmu TEGRA186_SID_SDMMC1>; @@ -335,8 +336,9 @@ compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03420000 0x0 0x10000>; interrupts = ; - clocks = <&bpmp TEGRA186_CLK_SDMMC2>; - clock-names = "sdhci"; + clocks = <&bpmp TEGRA186_CLK_SDMMC2>, + <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; resets = <&bpmp TEGRA186_RESET_SDMMC2>; reset-names = "sdhci"; iommus = <&smmu TEGRA186_SID_SDMMC2>; @@ -356,8 +358,9 @@ compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03440000 0x0 0x10000>; interrupts = ; - clocks = <&bpmp TEGRA186_CLK_SDMMC3>; - clock-names = "sdhci"; + clocks = <&bpmp TEGRA186_CLK_SDMMC3>, + <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; resets = <&bpmp TEGRA186_RESET_SDMMC3>; reset-names = "sdhci"; iommus = <&smmu TEGRA186_SID_SDMMC3>; @@ -379,8 +382,9 @@ compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03460000 0x0 0x10000>; interrupts = ; - clocks = <&bpmp TEGRA186_CLK_SDMMC4>; - clock-names = "sdhci"; + clocks = <&bpmp TEGRA186_CLK_SDMMC4>, + <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, <&bpmp TEGRA186_CLK_PLLC4_VCO>; assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 2f3926719434a1..5728255bd0c1af 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -403,8 +403,9 @@ compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; reg = <0x03400000 0x10000>; interrupts = ; - clocks = <&bpmp TEGRA194_CLK_SDMMC1>; - clock-names = "sdhci"; + clocks = <&bpmp TEGRA194_CLK_SDMMC1>, + <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; resets = <&bpmp TEGRA194_RESET_SDMMC1>; reset-names = "sdhci"; nvidia,pad-autocal-pull-up-offset-3v3-timeout = @@ -425,8 +426,9 @@ compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; reg = <0x03440000 0x10000>; interrupts = ; - clocks = <&bpmp TEGRA194_CLK_SDMMC3>; - clock-names = "sdhci"; + clocks = <&bpmp TEGRA194_CLK_SDMMC3>, + <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; resets = <&bpmp TEGRA194_RESET_SDMMC3>; reset-names = "sdhci"; nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; @@ -448,8 +450,9 @@ compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; reg = <0x03460000 0x10000>; interrupts = ; - clocks = <&bpmp TEGRA194_CLK_SDMMC4>; - clock-names = "sdhci"; + clocks = <&bpmp TEGRA194_CLK_SDMMC4>, + <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, <&bpmp TEGRA194_CLK_PLLC4>; assigned-clock-parents = diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 659753118e96f3..078d2506365c09 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1116,8 +1116,9 @@ compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0000 0x0 0x200>; interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; - clock-names = "sdhci"; + clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, + <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; + clock-names = "sdhci", "tmclk"; resets = <&tegra_car 14>; reset-names = "sdhci"; pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", @@ -1144,8 +1145,9 @@ compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0200 0x0 0x200>; interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; - clock-names = "sdhci"; + clocks = <&tegra_car TEGRA210_CLK_SDMMC2>, + <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; + clock-names = "sdhci", "tmclk"; resets = <&tegra_car 9>; reset-names = "sdhci"; pinctrl-names = "sdmmc-1v8-drv"; @@ -1161,8 +1163,9 @@ compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0400 0x0 0x200>; interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; - clock-names = "sdhci"; + clocks = <&tegra_car TEGRA210_CLK_SDMMC3>, + <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; + clock-names = "sdhci", "tmclk"; resets = <&tegra_car 69>; reset-names = "sdhci"; pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", @@ -1184,8 +1187,9 @@ compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0600 0x0 0x200>; interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; - clock-names = "sdhci"; + clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, + <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; + clock-names = "sdhci", "tmclk"; resets = <&tegra_car 15>; reset-names = "sdhci"; pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index c9a867ac32d48d..12309e8a623755 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -25,6 +25,7 @@ CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y CONFIG_USER_NS=y CONFIG_SCHED_AUTOGROUP=y +CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_KALLSYMS_ALL=y # CONFIG_COMPAT_BRK is not set @@ -48,6 +49,8 @@ CONFIG_ARCH_MXC=y CONFIG_ARCH_QCOM=y CONFIG_ARCH_RENESAS=y CONFIG_ARCH_ROCKCHIP=y +CONFIG_ARCH_S32=y +CONFIG_SOC_S32V234=y CONFIG_ARCH_SEATTLE=y CONFIG_ARCH_STRATIX10=y CONFIG_ARCH_SYNQUACER=y @@ -69,29 +72,31 @@ CONFIG_CRASH_DUMP=y CONFIG_XEN=y CONFIG_COMPAT=y CONFIG_RANDOMIZE_BASE=y -CONFIG_HIBERNATION=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y CONFIG_ARM_CPUIDLE=y CONFIG_ARM_PSCI_CPUIDLE=y CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_POWERSAVE=m CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y CONFIG_CPUFREQ_DT=y CONFIG_ACPI_CPPC_CPUFREQ=m CONFIG_ARM_ARMADA_37XX_CPUFREQ=y CONFIG_ARM_SCPI_CPUFREQ=y -CONFIG_ARM_IMX_CPUFREQ_DT=m +CONFIG_ARM_IMX_CPUFREQ_DT=y CONFIG_ARM_RASPBERRYPI_CPUFREQ=m CONFIG_ARM_TEGRA186_CPUFREQ=y +CONFIG_QORIQ_CPUFREQ=y CONFIG_ARM_SCPI_PROTOCOL=y CONFIG_RASPBERRYPI_FIRMWARE=y CONFIG_INTEL_STRATIX10_SERVICE=y -CONFIG_TI_SCI_PROTOCOL=y CONFIG_EFI_CAPSULE_LOADER=y +CONFIG_IMX_DSP=y CONFIG_IMX_SCU=y CONFIG_IMX_SCU_PD=y CONFIG_ACPI=y @@ -121,7 +126,6 @@ CONFIG_MODULE_UNLOAD=y CONFIG_KSM=y CONFIG_MEMORY_FAILURE=y CONFIG_TRANSPARENT_HUGEPAGE=y -CONFIG_CMA=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -130,7 +134,7 @@ CONFIG_IP_MULTICAST=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y -CONFIG_IPV6=m +CONFIG_IPV6_SIT=m CONFIG_NETFILTER=y CONFIG_NF_CONNTRACK=m CONFIG_NF_CONNTRACK_EVENTS=y @@ -152,27 +156,42 @@ CONFIG_IP6_NF_NAT=m CONFIG_IP6_NF_TARGET_MASQUERADE=m CONFIG_BRIDGE=m CONFIG_BRIDGE_VLAN_FILTERING=y -CONFIG_VLAN_8021Q=m CONFIG_VLAN_8021Q_GVRP=y CONFIG_VLAN_8021Q_MVRP=y +CONFIG_LLC2=y +CONFIG_TSN=y +CONFIG_NET_SWITCHDEV=y CONFIG_QRTR=m CONFIG_QRTR_SMD=m CONFIG_QRTR_TUN=m CONFIG_BPF_JIT=y -CONFIG_BT=m -CONFIG_BT_HIDP=m +CONFIG_CAN=m +CONFIG_CAN_FLEXCAN=m +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y # CONFIG_BT_HS is not set # CONFIG_BT_LE is not set CONFIG_BT_LEDS=y # CONFIG_BT_DEBUGFS is not set CONFIG_BT_HCIBTUSB=m -CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_3WIRE=y CONFIG_BT_HCIUART_BCM=y -CONFIG_CFG80211=m -CONFIG_MAC80211=m +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIVHCI=y +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=y CONFIG_MAC80211_LEDS=y -CONFIG_RFKILL=m CONFIG_NET_9P=y CONFIG_NET_9P_VIRTIO=y CONFIG_PCI=y @@ -190,6 +209,7 @@ CONFIG_PCIE_ALTERA_MSI=y CONFIG_PCI_HOST_THUNDER_PEM=y CONFIG_PCI_HOST_THUNDER_ECAM=y CONFIG_PCIE_ROCKCHIP_HOST=m +CONFIG_PCI_IMX6=y CONFIG_PCI_LAYERSCAPE=y CONFIG_PCI_HISI=y CONFIG_PCIE_QCOM=y @@ -197,25 +217,44 @@ CONFIG_PCIE_ARMADA_8K=y CONFIG_PCIE_KIRIN=y CONFIG_PCIE_HISI_STB=y CONFIG_PCIE_TEGRA194=m +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_FW_LOADER_USER_HELPER=y CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y CONFIG_HISILICON_LPC=y CONFIG_SIMPLE_PM_BUS=y +CONFIG_FSL_MC_BUS=y +CONFIG_FSL_MC_UAPI_SUPPORT=y CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y -CONFIG_MTD_M25P80=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_SST25L=y CONFIG_MTD_RAW_NAND=y CONFIG_MTD_NAND_DENALI_DT=y CONFIG_MTD_NAND_MARVELL=y +CONFIG_MTD_NAND_FSL_IFC=y +CONFIG_MTD_NAND_GPMI_NAND=y CONFIG_MTD_NAND_QCOM=y CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +CONFIG_MTD_UBI=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=m CONFIG_VIRTIO_BLK=y -CONFIG_BLK_DEV_NVME=m +CONFIG_BLK_DEV_NVME=y +CONFIG_SENSORS_FXOS8700=y +CONFIG_SENSORS_FXAS2100X=y CONFIG_SRAM=y +CONFIG_EEPROM_AT24=y CONFIG_EEPROM_AT25=m # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=y @@ -230,6 +269,7 @@ CONFIG_SCSI_UFS_HISI=y CONFIG_ATA=y CONFIG_SATA_AHCI=y CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y CONFIG_AHCI_CEVA=y CONFIG_AHCI_MVEBU=y CONFIG_AHCI_XGENE=y @@ -256,27 +296,29 @@ CONFIG_BNX2X=m CONFIG_MACB=y CONFIG_THUNDER_NIC_PF=y CONFIG_FEC=y +CONFIG_FSL_SDK_DPAA_ETH=y +CONFIG_FSL_DPAA2_ETH=y +CONFIG_FSL_ENETC=y +CONFIG_FSL_ENETC_VF=y +CONFIG_FSL_ENETC_MDIO=y +CONFIG_ENETC_TSN=y CONFIG_HIX5HD2_GMAC=y CONFIG_HNS_DSAF=y CONFIG_HNS_ENET=y CONFIG_HNS3=y CONFIG_HNS3_HCLGE=y CONFIG_HNS3_ENET=y +CONFIG_E1000=y CONFIG_E1000E=y CONFIG_IGB=y CONFIG_IGBVF=y -CONFIG_MLX4_EN=m -CONFIG_MLX4_CORE=m -CONFIG_MLX4_DEBUG=y -CONFIG_MLX4_CORE_GEN2=y -CONFIG_MLX5_CORE=m -CONFIG_MLX5_CORE_EN=y -CONFIG_MLX5_EN_ARFS=y -CONFIG_MLX5_EN_RXNFC=y -CONFIG_MLX5_MPFS=y CONFIG_MVNETA=y CONFIG_MVPP2=y CONFIG_SKY2=y +CONFIG_MLX4_EN=m +CONFIG_MLX5_CORE=m +CONFIG_MLX5_CORE_EN=y +CONFIG_MSCC_OCELOT_SWITCH=y CONFIG_QCOM_EMAC=m CONFIG_RAVB=y CONFIG_SMC91X=y @@ -284,14 +326,19 @@ CONFIG_SMSC911X=y CONFIG_SNI_AVE=y CONFIG_SNI_NETSEC=y CONFIG_STMMAC_ETH=m -CONFIG_MDIO_BUS_MUX_MMIOREG=y -CONFIG_AT803X_PHY=m +CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y +CONFIG_AQUANTIA_PHY=y +CONFIG_AT803X_PHY=y +CONFIG_INPHI_PHY=y CONFIG_MARVELL_PHY=m CONFIG_MARVELL_10G_PHY=m CONFIG_MESON_GXL_PHY=m CONFIG_MICREL_PHY=y -CONFIG_REALTEK_PHY=m +CONFIG_MICROSEMI_PHY=y +CONFIG_NXP_TJA11XX_PHY=y +CONFIG_REALTEK_PHY=y CONFIG_ROCKCHIP_PHY=y +CONFIG_VITESSE_PHY=y CONFIG_USB_PEGASUS=m CONFIG_USB_RTL8150=m CONFIG_USB_RTL8152=m @@ -303,23 +350,25 @@ CONFIG_USB_NET_SMSC75XX=m CONFIG_USB_NET_SMSC95XX=m CONFIG_USB_NET_PLUSB=m CONFIG_USB_NET_MCS7830=m -CONFIG_ATH10K=m -CONFIG_ATH10K_PCI=m CONFIG_BRCMFMAC=m -CONFIG_MWIFIEX=m -CONFIG_MWIFIEX_PCIE=m +CONFIG_BRCMFMAC_PCIE=y +CONFIG_HOSTAP=y CONFIG_WL18XX=m CONFIG_WLCORE_SDIO=m CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_ADC=m CONFIG_KEYBOARD_GPIO=y -CONFIG_KEYBOARD_SNVS_PWRKEY=m +CONFIG_KEYBOARD_SNVS_PWRKEY=y +CONFIG_KEYBOARD_IMX_SC_PWRKEY=y CONFIG_KEYBOARD_CROS_EC=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=m CONFIG_INPUT_MISC=y CONFIG_INPUT_PM8941_PWRKEY=y CONFIG_INPUT_HISI_POWERKEY=y +CONFIG_INPUT_MPL3115=y +CONFIG_INPUT_ISL29023=y # CONFIG_SERIO_SERPORT is not set CONFIG_SERIO_AMBAKMI=y CONFIG_LEGACY_PTY_COUNT=16 @@ -352,6 +401,8 @@ CONFIG_SERIAL_XILINX_PS_UART=y CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y CONFIG_SERIAL_FSL_LPUART=y CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_FSL_LINFLEXUART=y +CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y CONFIG_SERIAL_MVEBU_UART=y CONFIG_SERIAL_DEV_BUS=y CONFIG_VIRTIO_CONSOLE=y @@ -374,6 +425,7 @@ CONFIG_I2C_PXA=y CONFIG_I2C_QCOM_GENI=m CONFIG_I2C_QUP=y CONFIG_I2C_RK3X=y +CONFIG_I2C_RPBUS=y CONFIG_I2C_SH_MOBILE=y CONFIG_I2C_TEGRA=y CONFIG_I2C_UNIPHIER_F=y @@ -383,8 +435,11 @@ CONFIG_SPI=y CONFIG_SPI_ARMADA_3700=y CONFIG_SPI_BCM2835=m CONFIG_SPI_BCM2835AUX=m +CONFIG_SPI_FSL_LPSPI=y +CONFIG_SPI_FSL_QUADSPI=y CONFIG_SPI_NXP_FLEXSPI=y -CONFIG_SPI_IMX=m +CONFIG_SPI_IMX=y +CONFIG_SPI_FSL_DSPI=y CONFIG_SPI_MESON_SPICC=m CONFIG_SPI_MESON_SPIFC=m CONFIG_SPI_ORION=y @@ -392,17 +447,23 @@ CONFIG_SPI_PL022=y CONFIG_SPI_ROCKCHIP=y CONFIG_SPI_QUP=y CONFIG_SPI_S3C64XX=y -CONFIG_SPI_SPIDEV=m CONFIG_SPI_SUN6I=y +CONFIG_SPI_SPIDEV=y +CONFIG_SPI_SLAVE=y +CONFIG_SPI_SLAVE_TIME=y +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y CONFIG_SPMI=y CONFIG_PINCTRL_SINGLE=y CONFIG_PINCTRL_MAX77620=y CONFIG_PINCTRL_IMX8MM=y CONFIG_PINCTRL_IMX8MN=y CONFIG_PINCTRL_IMX8MQ=y +CONFIG_PINCTRL_IMX8QM=y CONFIG_PINCTRL_IMX8QXP=y +CONFIG_PINCTRL_IMX8DXL=y CONFIG_PINCTRL_IPQ8074=y CONFIG_PINCTRL_MSM8916=y +CONFIG_PINCTRL_S32V234=y CONFIG_PINCTRL_MSM8994=y CONFIG_PINCTRL_MSM8996=y CONFIG_PINCTRL_MSM8998=y @@ -411,8 +472,10 @@ CONFIG_PINCTRL_QDF2XXX=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y CONFIG_PINCTRL_SDM845=y CONFIG_PINCTRL_SM8150=y +CONFIG_GPIO_SYSFS=y CONFIG_GPIO_DWAPB=y CONFIG_GPIO_MB86S7X=y +CONFIG_GPIO_MPC8XXX=y CONFIG_GPIO_PL061=y CONFIG_GPIO_RCAR=y CONFIG_GPIO_UNIPHIER=y @@ -436,10 +499,14 @@ CONFIG_SENSORS_PWM_FAN=m CONFIG_SENSORS_RASPBERRYPI_HWMON=m CONFIG_SENSORS_INA2XX=m CONFIG_SENSORS_INA3221=m +CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y CONFIG_CPU_THERMAL=y CONFIG_THERMAL_EMULATION=y -CONFIG_QORIQ_THERMAL=m +CONFIG_IMX_SC_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_IMX8MM_THERMAL=y +CONFIG_QORIQ_THERMAL=y CONFIG_ROCKCHIP_THERMAL=m CONFIG_RCAR_THERMAL=y CONFIG_RCAR_GEN3_THERMAL=y @@ -451,12 +518,13 @@ CONFIG_TEGRA_BPMP_THERMAL=m CONFIG_QCOM_TSENS=y CONFIG_UNIPHIER_THERMAL=y CONFIG_WATCHDOG=y +CONFIG_ARM_SBSA_WATCHDOG=y CONFIG_ARM_SP805_WATCHDOG=y CONFIG_S3C2410_WATCHDOG=y CONFIG_DW_WATCHDOG=y CONFIG_SUNXI_WATCHDOG=m CONFIG_IMX2_WDT=y -CONFIG_IMX_SC_WDT=m +CONFIG_IMX_SC_WDT=y CONFIG_MESON_GXBB_WATCHDOG=m CONFIG_MESON_WATCHDOG=m CONFIG_RENESAS_WDT=y @@ -466,9 +534,8 @@ CONFIG_MFD_ALTERA_SYSMGR=y CONFIG_MFD_BD9571MWV=y CONFIG_MFD_AXP20X_I2C=y CONFIG_MFD_AXP20X_RSB=y -CONFIG_MFD_CROS_EC=y -CONFIG_MFD_CROS_EC_CHARDEV=m CONFIG_MFD_EXYNOS_LPASS=m +CONFIG_MFD_IMX_AUDIOMIX=y CONFIG_MFD_HI6421_PMIC=y CONFIG_MFD_HI655X_PMIC=y CONFIG_MFD_MAX77620=y @@ -476,6 +543,7 @@ CONFIG_MFD_SPMI_PMIC=y CONFIG_MFD_RK808=y CONFIG_MFD_SEC_CORE=y CONFIG_MFD_ROHM_BD718XX=y +CONFIG_MFD_PCA9450=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_AXP20X=y CONFIG_REGULATOR_BD718XX=y @@ -486,6 +554,7 @@ CONFIG_REGULATOR_HI6421V530=y CONFIG_REGULATOR_HI655X=y CONFIG_REGULATOR_MAX77620=y CONFIG_REGULATOR_MAX8973=y +CONFIG_REGULATOR_PCA9450=y CONFIG_REGULATOR_PFUZE100=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_QCOM_RPMH=y @@ -499,7 +568,7 @@ CONFIG_RC_DECODERS=y CONFIG_RC_DEVICES=y CONFIG_IR_MESON=m CONFIG_IR_SUNXI=m -CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_ANALOG_TV_SUPPORT=y CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y @@ -509,6 +578,11 @@ CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_MEDIA_USB_SUPPORT=y CONFIG_USB_VIDEO_CLASS=m CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MX8_CAPTURE=y +CONFIG_VIDEO_MXC_CAPTURE=y +CONFIG_VIDEO_MXC_CSI_CAMERA=y +CONFIG_MXC_MIPI_CSI=y +CONFIG_MXC_CAMERA_OV5640_MIPI_V2=y CONFIG_VIDEO_SUN6I_CSI=m CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m @@ -516,8 +590,12 @@ CONFIG_VIDEO_SAMSUNG_S5P_MFC=m CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m CONFIG_VIDEO_RENESAS_FCP=m CONFIG_VIDEO_RENESAS_VSP1=m -CONFIG_DRM=m +CONFIG_VIDEO_OV5640=y +CONFIG_IMX_DPU_CORE=y +CONFIG_IMX_LCDIF_CORE=y +CONFIG_DRM=y CONFIG_DRM_I2C_NXP_TDA998X=m +CONFIG_DRM_MALI_DISPLAY=m CONFIG_DRM_NOUVEAU=m CONFIG_DRM_EXYNOS=m CONFIG_DRM_EXYNOS5433_DECON=y @@ -538,22 +616,36 @@ CONFIG_DRM_SUN8I_DW_HDMI=m CONFIG_DRM_SUN8I_MIXER=m CONFIG_DRM_MSM=m CONFIG_DRM_TEGRA=m -CONFIG_DRM_PANEL_SIMPLE=m +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_PANEL_RAYDIUM_RM67191=y +CONFIG_DRM_PANEL_SEIKO_43WVF1G=y CONFIG_DRM_SII902X=m -CONFIG_DRM_I2C_ADV7511=m +CONFIG_DRM_I2C_ADV7511=y +CONFIG_DRM_NWL_MIPI_DSI=y +CONFIG_DRM_CDNS_HDMI_CEC=y +CONFIG_DRM_ITE_IT6263=y +CONFIG_DRM_IMX=y +CONFIG_DRM_IMX_LCDIF_MUX_DISPLAY=y +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y +CONFIG_DRM_IMX_TVE=y +CONFIG_DRM_IMX_LDB=y +CONFIG_DRM_IMX_HDMI=y +CONFIG_DRM_IMX_SEC_DSIM=y +CONFIG_DRM_IMX_CDNS_MHDP=y +CONFIG_DRM_IMX_DCSS=y CONFIG_DRM_VC4=m CONFIG_DRM_ETNAVIV=m CONFIG_DRM_HISI_HIBMC=m CONFIG_DRM_HISI_KIRIN=m +CONFIG_DRM_MXSFB=y CONFIG_DRM_MESON=m CONFIG_DRM_PL111=m CONFIG_DRM_LIMA=m CONFIG_DRM_PANFROST=m -CONFIG_FB=y -CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_ARMCLCD=y CONFIG_FB_EFI=y CONFIG_BACKLIGHT_GENERIC=m -CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_PWM=y CONFIG_BACKLIGHT_LP855X=m CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set @@ -562,8 +654,26 @@ CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_HDA_TEGRA=m CONFIG_SND_HDA_CODEC_HDMI=m +CONFIG_SND_USB_AUDIO=m CONFIG_SND_SOC=y CONFIG_SND_BCM2835_SOC_I2S=m +CONFIG_SND_SOC_FSL_EASRC=y +CONFIG_SND_SOC_FSL_DAI=m +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_IMX_AK4458=y +CONFIG_SND_SOC_IMX_AK5558=y +CONFIG_SND_SOC_IMX_AK4497=y +CONFIG_SND_SOC_IMX_WM8960=y +CONFIG_SND_SOC_IMX_WM8524=y +CONFIG_SND_SOC_IMX_CS42888=y +CONFIG_SND_SOC_IMX_MICFIL=y +CONFIG_SND_SOC_IMX_RPMSG=y +CONFIG_SND_SOC_IMX_MQS=y +CONFIG_SND_SOC_IMX_SPDIF=y +CONFIG_SND_SOC_IMX_AUDMIX=y +CONFIG_SND_SOC_IMX_PDM_MIC=y +CONFIG_SND_SOC_IMX_DSP=y +CONFIG_SND_SOC_IMX_CDNHDMI=y CONFIG_SND_MESON_AXG_SOUND_CARD=m CONFIG_SND_SOC_ROCKCHIP=m CONFIG_SND_SOC_ROCKCHIP_SPDIF=m @@ -571,14 +681,19 @@ CONFIG_SND_SOC_ROCKCHIP_RT5645=m CONFIG_SND_SOC_RK3399_GRU_SOUND=m CONFIG_SND_SOC_SAMSUNG=y CONFIG_SND_SOC_RCAR=m +CONFIG_SND_SOC_SOF_TOPLEVEL=y +CONFIG_SND_SOC_SOF_OF=m +CONFIG_SND_SOC_SOF_IMX_TOPLEVEL=y +CONFIG_SND_SOC_SOF_IMX8_SUPPORT=y CONFIG_SND_SUN4I_SPDIF=m CONFIG_SND_SOC_AK4613=m CONFIG_SND_SOC_ES7134=m CONFIG_SND_SOC_ES7241=m CONFIG_SND_SOC_PCM3168A_I2C=m +CONFIG_SND_SOC_SGTL5000=m CONFIG_SND_SOC_TAS571X=m -CONFIG_SND_SIMPLE_CARD=m -CONFIG_SND_AUDIO_GRAPH_CARD=m +CONFIG_SND_SIMPLE_CARD=y +CONFIG_SND_AUDIO_GRAPH_CARD=y CONFIG_I2C_HID=m CONFIG_USB=y CONFIG_USB_OTG=y @@ -591,7 +706,11 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_EXYNOS=y CONFIG_USB_OHCI_HCD_PLATFORM=y CONFIG_USB_RENESAS_USBHS=m +CONFIG_USB_ACM=m CONFIG_USB_STORAGE=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y CONFIG_USB_MUSB_HDRC=y CONFIG_USB_MUSB_SUNXI=y CONFIG_USB_DWC3=y @@ -600,14 +719,42 @@ CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_UDC=y CONFIG_USB_CHIPIDEA_HOST=y CONFIG_USB_ISP1760=y +CONFIG_USB_TEST=m +CONFIG_USB_EHSET_TEST_FIXTURE=m CONFIG_USB_HSIC_USB3503=y CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MXS_PHY=y CONFIG_USB_ULPI=y CONFIG_USB_GADGET=y CONFIG_USB_RENESAS_USBHS_UDC=m CONFIG_USB_RENESAS_USB3=m -CONFIG_TYPEC=m -CONFIG_TYPEC_HD3SS3220=m +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_USB_ETH=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_TYPEC=y +CONFIG_TYPEC_TCPM=y +CONFIG_TYPEC_TCPCI=y +CONFIG_TYPEC_SWITCH_GPIO=y CONFIG_MMC=y CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_ARMMMCI=y @@ -646,11 +793,14 @@ CONFIG_LEDS_TRIGGER_PANIC=y CONFIG_EDAC=y CONFIG_EDAC_GHES=y CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_MAX77686=y CONFIG_RTC_DRV_RK808=m +CONFIG_RTC_DRV_PCF85363=y CONFIG_RTC_DRV_RX8581=m CONFIG_RTC_DRV_S5M=y CONFIG_RTC_DRV_DS3232=y +CONFIG_RTC_DRV_PCF2127=y CONFIG_RTC_DRV_EFI=y CONFIG_RTC_DRV_CROS_EC=y CONFIG_RTC_DRV_S3C=y @@ -658,17 +808,19 @@ CONFIG_RTC_DRV_PL031=y CONFIG_RTC_DRV_SUN6I=y CONFIG_RTC_DRV_ARMADA38X=y CONFIG_RTC_DRV_TEGRA=y -CONFIG_RTC_DRV_SNVS=m -CONFIG_RTC_DRV_IMX_SC=m +CONFIG_RTC_DRV_SNVS=y +CONFIG_RTC_DRV_IMX_SC=y CONFIG_RTC_DRV_XGENE=y CONFIG_DMADEVICES=y -CONFIG_FSL_EDMA=y CONFIG_DMA_BCM2835=m CONFIG_DMA_SUN6I=m +CONFIG_FSL_EDMA=y +CONFIG_FSL_EDMA_V3=y CONFIG_IMX_SDMA=y CONFIG_K3_DMA=y CONFIG_MV_XOR=y CONFIG_MV_XOR_V2=y +CONFIG_MXS_DMA=y CONFIG_PL330_DMA=y CONFIG_TEGRA20_APB_DMA=y CONFIG_QCOM_BAM_DMA=y @@ -676,20 +828,36 @@ CONFIG_QCOM_HIDMA_MGMT=y CONFIG_QCOM_HIDMA=y CONFIG_RCAR_DMAC=y CONFIG_RENESAS_USB_DMAC=m +CONFIG_DMATEST=y +CONFIG_UIO=y +CONFIG_UIO_PCI_GENERIC=y CONFIG_VFIO=y CONFIG_VFIO_PCI=y +CONFIG_VFIO_FSL_MC=y CONFIG_VIRTIO_PCI=y CONFIG_VIRTIO_BALLOON=y CONFIG_VIRTIO_MMIO=y CONFIG_XEN_GNTDEV=y CONFIG_XEN_GRANT_DEV_ALLOC=y +CONFIG_STAGING=y +CONFIG_STAGING_MEDIA=y +CONFIG_VIDEO_IMX_CAPTURE=y +CONFIG_ION=y +CONFIG_ION_SYSTEM_HEAP=y +CONFIG_ION_CMA_HEAP=y +CONFIG_FSL_DPAA2=y +CONFIG_FSL_DPAA2_ETHSW=y +CONFIG_FSL_DPAA2_MAC=y +CONFIG_FSL_SDK_DPA=y +CONFIG_FSL_PPFE=y +CONFIG_FSL_PPFE_UTIL_DISABLED=y +CONFIG_MFD_CROS_EC=y CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_SPI=y CONFIG_COMMON_CLK_RK808=y CONFIG_COMMON_CLK_SCPI=y CONFIG_COMMON_CLK_CS2000_CP=y CONFIG_COMMON_CLK_S2MPS11=y -CONFIG_CLK_QORIQ=y CONFIG_COMMON_CLK_PWM=y CONFIG_CLK_RASPBERRYPI=m CONFIG_CLK_IMX8MM=y @@ -716,7 +884,6 @@ CONFIG_ARM_MHU=y CONFIG_IMX_MBOX=y CONFIG_PLATFORM_MHU=y CONFIG_BCM2835_MBOX=y -CONFIG_TI_MESSAGE_MANAGER=y CONFIG_QCOM_APCS_IPC=y CONFIG_ROCKCHIP_IOMMU=y CONFIG_TEGRA_IOMMU_SMMU=y @@ -731,8 +898,9 @@ CONFIG_RPMSG_QCOM_GLINK_RPM=y CONFIG_RPMSG_QCOM_GLINK_SMEM=m CONFIG_RPMSG_QCOM_SMD=y CONFIG_RASPBERRYPI_POWER=y +CONFIG_FSL_MC_DPIO=y +CONFIG_FSL_QIXIS=y CONFIG_IMX_SCU_SOC=y -CONFIG_QCOM_COMMAND_DB=y CONFIG_QCOM_GENI_SE=y CONFIG_QCOM_GLINK_SSR=m CONFIG_QCOM_RPMH=y @@ -756,24 +924,21 @@ CONFIG_ARCH_TEGRA_186_SOC=y CONFIG_ARCH_TEGRA_194_SOC=y CONFIG_ARCH_K3_AM6_SOC=y CONFIG_ARCH_K3_J721E_SOC=y -CONFIG_SOC_TI=y CONFIG_TI_SCI_PM_DOMAINS=y -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y CONFIG_EXTCON_USB_GPIO=y CONFIG_EXTCON_USBC_CROS_EC=y -CONFIG_MEMORY=y CONFIG_IIO=y CONFIG_EXYNOS_ADC=y +CONFIG_IMX8QXP_ADC=y CONFIG_ROCKCHIP_SARADC=m CONFIG_IIO_CROS_EC_SENSORS_CORE=m CONFIG_IIO_CROS_EC_SENSORS=m CONFIG_IIO_CROS_EC_LIGHT_PROX=m -CONFIG_SENSORS_ISL29018=m CONFIG_IIO_CROS_EC_BARO=m -CONFIG_MPL3115=m CONFIG_PWM=y CONFIG_PWM_BCM2835=m CONFIG_PWM_CROS_EC=m +CONFIG_PWM_IMX27=y CONFIG_PWM_MESON=m CONFIG_PWM_RCAR=m CONFIG_PWM_ROCKCHIP=y @@ -783,6 +948,7 @@ CONFIG_PWM_TEGRA=m CONFIG_RESET_TI_SCI=y CONFIG_PHY_XGENE=y CONFIG_PHY_SUN4I_USB=y +CONFIG_PHY_MIXEL_MIPI_DPHY=y CONFIG_PHY_HI6220_USB=y CONFIG_PHY_HISTB_COMBPHY=y CONFIG_PHY_HISI_INNO_USB2=y @@ -801,15 +967,15 @@ CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PHY_UNIPHIER_USB2=y CONFIG_PHY_UNIPHIER_USB3=y CONFIG_PHY_TEGRA_XUSB=y -CONFIG_FSL_IMX8_DDR_PMU=m +CONFIG_FSL_IMX8_DDR_PMU=y CONFIG_HISI_PMU=y CONFIG_QCOM_L2_PMU=y CONFIG_QCOM_L3_PMU=y -CONFIG_NVMEM_SUNXI_SID=y CONFIG_NVMEM_IMX_OCOTP=y CONFIG_NVMEM_IMX_OCOTP_SCU=y CONFIG_QCOM_QFPROM=y CONFIG_ROCKCHIP_EFUSE=y +CONFIG_NVMEM_SUNXI_SID=y CONFIG_UNIPHIER_EFUSE=y CONFIG_MESON_EFUSE=m CONFIG_FPGA=y @@ -820,6 +986,10 @@ CONFIG_FPGA_REGION=m CONFIG_OF_FPGA_REGION=m CONFIG_TEE=y CONFIG_OPTEE=y +CONFIG_MUX_MMIO=y +CONFIG_MXC_SIM=y +CONFIG_MXC_EMVSIM=y +CONFIG_MXC_MLB150=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_EXT4_FS_POSIX_ACL=y @@ -834,8 +1004,9 @@ CONFIG_CUSE=m CONFIG_OVERLAY_FS=m CONFIG_VFAT_FS=y CONFIG_HUGETLBFS=y -CONFIG_CONFIGFS_FS=y CONFIG_EFIVAR_FS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y CONFIG_SQUASHFS=y CONFIG_NFS_FS=y CONFIG_NFS_V4=y @@ -846,10 +1017,38 @@ CONFIG_9P_FS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y CONFIG_SECURITY=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_TEST=m CONFIG_CRYPTO_ECHAINIV=y CONFIG_CRYPTO_ANSI_CPRNG=y -CONFIG_DMA_CMA=y -CONFIG_CMA_SIZE_MBYTES=32 +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_TLS=m +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y +CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=y +CONFIG_CMA_SIZE_MBYTES=320 CONFIG_PRINTK_TIME=y CONFIG_DEBUG_INFO=y CONFIG_DEBUG_FS=y diff --git a/arch/arm64/configs/imx.config b/arch/arm64/configs/imx.config new file mode 100644 index 00000000000000..50ad407c2f612a --- /dev/null +++ b/arch/arm64/configs/imx.config @@ -0,0 +1,35 @@ +# imx specific options +# +# required by GPU +CONFIG_FORCE_MAX_ZONEORDER=14 + +# disable other ARCH +CONFIG_ARCH_AGILEX=n +CONFIG_ARCH_SUNXI=n +CONFIG_ARCH_ALPINE=n +CONFIG_ARCH_BCM2835=n +CONFIG_ARCH_BCM_IPROC=n +CONFIG_ARCH_BERLIN=n +CONFIG_ARCH_BRCMSTB=n +CONFIG_ARCH_EXYNOS=n +CONFIG_ARCH_K3=n +CONFIG_ARCH_LG1K=n +CONFIG_ARCH_HISI=n +CONFIG_ARCH_MEDIATEK=n +CONFIG_ARCH_MESON=n +CONFIG_ARCH_MVEBU=n +CONFIG_ARCH_QCOM=n +CONFIG_ARCH_RENESAS=n +CONFIG_ARCH_ROCKCHIP=n +CONFIG_ARCH_SEATTLE=n +CONFIG_ARCH_STRATIX10=n +CONFIG_ARCH_SYNQUACER=n +CONFIG_ARCH_TEGRA=n +CONFIG_ARCH_SPRD=n +CONFIG_ARCH_THUNDER=n +CONFIG_ARCH_THUNDER2=n +CONFIG_ARCH_UNIPHIER=n +CONFIG_ARCH_VEXPRESS=n +CONFIG_ARCH_XGENE=n +CONFIG_ARCH_ZX=n +CONFIG_ARCH_ZYNQMP=n diff --git a/arch/arm64/configs/imx_v8_defconfig b/arch/arm64/configs/imx_v8_defconfig new file mode 100644 index 00000000000000..7ca52b2c20c714 --- /dev/null +++ b/arch/arm64/configs/imx_v8_defconfig @@ -0,0 +1,853 @@ +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_NUMA_BALANCING=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_USER_NS=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_COMPAT_BRK is not set +CONFIG_PROFILING=y +CONFIG_ARCH_LAYERSCAPE=y +CONFIG_ARCH_MXC=y +CONFIG_ARCH_S32=y +CONFIG_SOC_S32V234=y +CONFIG_ARM64_VA_BITS_48=y +CONFIG_SCHED_MC=y +CONFIG_NUMA=y +CONFIG_SECCOMP=y +CONFIG_KEXEC=y +CONFIG_CRASH_DUMP=y +CONFIG_XEN=y +CONFIG_FORCE_MAX_ZONEORDER=14 +CONFIG_COMPAT=y +CONFIG_RANDOMIZE_BASE=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +CONFIG_ARM_CPUIDLE=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPUFREQ_DT=y +CONFIG_ACPI_CPPC_CPUFREQ=m +CONFIG_ARM_SCPI_CPUFREQ=y +CONFIG_ARM_IMX_CPUFREQ_DT=y +CONFIG_QORIQ_CPUFREQ=y +CONFIG_ARM_SCPI_PROTOCOL=y +CONFIG_EFI_CAPSULE_LOADER=y +CONFIG_IMX_DSP=y +CONFIG_IMX_SCU=y +CONFIG_IMX_SCU_PD=y +CONFIG_IMX_SECO_MU=y +CONFIG_ACPI=y +CONFIG_ACPI_APEI=y +CONFIG_ACPI_APEI_GHES=y +CONFIG_ACPI_APEI_PCIEAER=y +CONFIG_ACPI_APEI_MEMORY_FAILURE=y +CONFIG_ACPI_APEI_EINJ=y +CONFIG_VIRTUALIZATION=y +CONFIG_KVM=y +CONFIG_ARM64_CRYPTO=y +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_SHA512_ARM64_CE=m +CONFIG_CRYPTO_SHA3_ARM64=m +CONFIG_CRYPTO_SM3_ARM64_CE=m +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_CHACHA20_NEON=m +CONFIG_CRYPTO_AES_ARM64_BS=m +CONFIG_JUMP_LABEL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_KSM=y +CONFIG_MEMORY_FAILURE=y +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IPV6_SIT=m +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_LLC2=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_MULTIQ=y +CONFIG_NET_SCH_CBS=y +CONFIG_NET_SCH_TAPRIO=y +CONFIG_NET_SCH_MQPRIO=y +CONFIG_NET_CLS_BASIC=y +CONFIG_NET_CLS_TCINDEX=y +CONFIG_TSN=y +CONFIG_NET_SWITCHDEV=y +CONFIG_BPF_JIT=y +CONFIG_NET_PKTGEN=y +CONFIG_CAN=m +CONFIG_CAN_FLEXCAN=m +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +# CONFIG_BT_HS is not set +# CONFIG_BT_LE is not set +CONFIG_BT_LEDS=y +# CONFIG_BT_DEBUGFS is not set +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIVHCI=y +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=y +CONFIG_MAC80211_LEDS=y +CONFIG_NET_9P=y +CONFIG_NET_9P_VIRTIO=y +CONFIG_PCI=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCI_IOV=y +CONFIG_HOTPLUG_PCI=y +CONFIG_HOTPLUG_PCI_ACPI=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCI_XGENE=y +CONFIG_PCIE_ALTERA=y +CONFIG_PCIE_ALTERA_MSI=y +CONFIG_PCI_HOST_THUNDER_PEM=y +CONFIG_PCI_HOST_THUNDER_ECAM=y +CONFIG_PCI_IMX6=y +CONFIG_PCI_LAYERSCAPE=y +CONFIG_PCI_HISI=y +CONFIG_PCIE_KIRIN=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y +CONFIG_BRCMSTB_GISB_ARB=y +CONFIG_SIMPLE_PM_BUS=y +CONFIG_VEXPRESS_CONFIG=y +CONFIG_FSL_MC_BUS=y +CONFIG_FSL_MC_UAPI_SUPPORT=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_NAND_DENALI_DT=y +CONFIG_MTD_NAND_GPMI_NAND=y +CONFIG_MTD_NAND_FSL_IFC=y +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NBD=m +CONFIG_XEN_BLKDEV_BACKEND=m +CONFIG_VIRTIO_BLK=y +CONFIG_BLK_DEV_NVME=y +CONFIG_SENSORS_FXOS8700=y +CONFIG_SENSORS_FXAS2100X=y +CONFIG_SRAM=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=m +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_HISI_SAS=y +CONFIG_SCSI_HISI_SAS_PCI=y +CONFIG_SCSI_MPT3SAS=m +CONFIG_SCSI_UFSHCD=y +CONFIG_SCSI_UFSHCD_PLATFORM=y +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +CONFIG_AHCI_CEVA=y +CONFIG_AHCI_XGENE=y +CONFIG_AHCI_QORIQ=y +CONFIG_SATA_SIL24=y +CONFIG_PATA_PLATFORM=y +CONFIG_PATA_OF_PLATFORM=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_MIRROR=m +CONFIG_DM_ZERO=m +CONFIG_NETDEVICES=y +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_TUN=y +CONFIG_VETH=m +CONFIG_VIRTIO_NET=y +CONFIG_AMD_XGBE=y +CONFIG_ATL1C=m +CONFIG_BNX2X=m +CONFIG_MACB=y +CONFIG_THUNDER_NIC_PF=y +CONFIG_FEC=y +CONFIG_FSL_SDK_DPAA_ETH=y +CONFIG_FSL_DPAA2_ETH=y +CONFIG_FSL_ENETC=y +CONFIG_FSL_ENETC_VF=y +CONFIG_FSL_ENETC_MDIO=y +CONFIG_HIX5HD2_GMAC=y +CONFIG_HNS_DSAF=y +CONFIG_HNS_ENET=y +CONFIG_HNS3=y +CONFIG_HNS3_HCLGE=y +CONFIG_HNS3_ENET=y +CONFIG_E1000=y +CONFIG_E1000E=y +CONFIG_IGB=y +CONFIG_IGBVF=y +CONFIG_MVMDIO=y +CONFIG_SKY2=y +CONFIG_MLX4_EN=m +CONFIG_MLX5_CORE=m +CONFIG_MLX5_CORE_EN=y +CONFIG_MSCC_OCELOT_SWITCH=y +CONFIG_QCOM_EMAC=m +CONFIG_SMC91X=y +CONFIG_SMSC911X=y +CONFIG_STMMAC_ETH=y +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y +CONFIG_AQUANTIA_PHY=y +CONFIG_AT803X_PHY=y +CONFIG_INPHI_PHY=y +CONFIG_MARVELL_PHY=m +CONFIG_MARVELL_10G_PHY=m +CONFIG_MICREL_PHY=y +CONFIG_MICROSEMI_PHY=y +CONFIG_NXP_TJA11XX_PHY=y +CONFIG_REALTEK_PHY=y +CONFIG_ROCKCHIP_PHY=y +CONFIG_VITESSE_PHY=y +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_USBNET=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_PCIE=y +CONFIG_HOSTAP=y +CONFIG_MXMWIFIEX=m +CONFIG_WL18XX=m +CONFIG_WLCORE_SDIO=m +CONFIG_IVSHMEM_NET=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_ADC=m +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_SNVS_PWRKEY=y +CONFIG_KEYBOARD_IMX_SC_PWRKEY=y +CONFIG_KEYBOARD_CROS_EC=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_MPL3115=y +CONFIG_INPUT_ISL29023=y +# CONFIG_SERIO_SERPORT is not set +CONFIG_SERIO_AMBAKMI=y +CONFIG_LEGACY_PTY_COUNT=16 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_FSL_LINFLEXUART=y +CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_VIRTIO_CONSOLE=y +CONFIG_IPMI_HANDLER=m +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_SI=m +CONFIG_TCG_TPM=y +CONFIG_TCG_TIS_I2C_INFINEON=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_GPIO=m +CONFIG_I2C_IMX=y +CONFIG_I2C_IMX_LPI2C=y +CONFIG_I2C_RK3X=y +CONFIG_I2C_RPBUS=y +CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_XEN_I2C_BACKEND=y +CONFIG_I2C_SLAVE=y +CONFIG_SPI=y +CONFIG_SPI_FSL_LPSPI=y +CONFIG_SPI_FSL_QUADSPI=y +CONFIG_SPI_NXP_FLEXSPI=y +CONFIG_SPI_IMX=y +CONFIG_SPI_FSL_DSPI=y +CONFIG_SPI_PL022=y +CONFIG_SPI_ROCKCHIP=y +CONFIG_SPI_SPIDEV=y +CONFIG_SPI_SLAVE=y +CONFIG_SPI_SLAVE_TIME=y +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y +CONFIG_SPMI=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_MAX77620=y +CONFIG_PINCTRL_IMX8MM=y +CONFIG_PINCTRL_IMX8MN=y +CONFIG_PINCTRL_IMX8MP=y +CONFIG_PINCTRL_IMX8MQ=y +CONFIG_PINCTRL_IMX8QM=y +CONFIG_PINCTRL_IMX8QXP=y +CONFIG_PINCTRL_IMX8DXL=y +CONFIG_PINCTRL_S32V234=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_DWAPB=y +CONFIG_GPIO_MB86S7X=y +CONFIG_GPIO_MPC8XXX=y +CONFIG_GPIO_PL061=y +CONFIG_GPIO_XGENE=y +CONFIG_GPIO_MAX732X=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_MAX77620=y +CONFIG_POWER_AVS=y +CONFIG_POWER_RESET_BRCMSTB=y +CONFIG_POWER_RESET_VEXPRESS=y +CONFIG_POWER_RESET_XGENE=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_BATTERY_SBS=m +CONFIG_BATTERY_BQ27XXX=y +CONFIG_SENSORS_ARM_SCPI=y +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_INA3221=m +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y +CONFIG_CPU_THERMAL=y +CONFIG_THERMAL_EMULATION=y +CONFIG_IMX_SC_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_IMX8MM_THERMAL=y +CONFIG_QORIQ_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_ARM_SP805_WATCHDOG=y +CONFIG_ARM_SBSA_WATCHDOG=y +CONFIG_DW_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_IMX_SC_WDT=y +CONFIG_XEN_WDT=y +CONFIG_MFD_BD9571MWV=y +CONFIG_MFD_AXP20X_I2C=y +CONFIG_MFD_IMX_AUDIOMIX=y +CONFIG_MFD_HI6421_PMIC=y +CONFIG_MFD_MAX77620=y +CONFIG_MFD_RK808=y +CONFIG_MFD_SEC_CORE=y +CONFIG_MFD_ROHM_BD718XX=y +CONFIG_MFD_PCA9450=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_AXP20X=y +CONFIG_REGULATOR_BD718XX=y +CONFIG_REGULATOR_BD9571MWV=y +CONFIG_REGULATOR_FAN53555=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_HI6421V530=y +CONFIG_REGULATOR_MAX77620=y +CONFIG_REGULATOR_MAX8973=y +CONFIG_REGULATOR_PCA9450=y +CONFIG_REGULATOR_PFUZE100=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_QCOM_SPMI=y +CONFIG_REGULATOR_RK808=y +CONFIG_REGULATOR_S2MPS11=y +CONFIG_REGULATOR_VCTRL=m +CONFIG_RC_CORE=m +CONFIG_RC_DECODERS=y +CONFIG_RC_DEVICES=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_DVB_NET is not set +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MX8_CAPTURE=y +CONFIG_VIDEO_MXC_CAPTURE=y +CONFIG_VIDEO_MXC_CSI_CAMERA=y +CONFIG_MXC_MIPI_CSI=y +CONFIG_MXC_CAMERA_OV5640_MIPI_V2=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_OV5640=y +CONFIG_IMX_DPU_CORE=y +CONFIG_IMX_LCDIF_CORE=y +CONFIG_IMX_LCDIFV3_CORE=y +CONFIG_DRM=y +CONFIG_DRM_I2C_NXP_TDA998X=m +CONFIG_DRM_MALI_DISPLAY=m +CONFIG_DRM_NOUVEAU=m +CONFIG_DRM_RCAR_LVDS=m +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_PANEL_RAYDIUM_RM67191=y +CONFIG_DRM_PANEL_SEIKO_43WVF1G=y +CONFIG_DRM_FSL_IMX_LVDS_BRIDGE=y +CONFIG_DRM_SII902X=m +CONFIG_DRM_I2C_ADV7511=y +CONFIG_DRM_NWL_MIPI_DSI=y +CONFIG_DRM_CDNS_HDMI_CEC=y +CONFIG_DRM_DW_HDMI_I2S_AUDIO=m +CONFIG_DRM_DW_HDMI_GP_AUDIO=y +CONFIG_DRM_DW_HDMI_CEC=y +CONFIG_DRM_ITE_IT6263=y +CONFIG_DRM_IMX=y +CONFIG_DRM_IMX_LCDIF_MUX_DISPLAY=y +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y +CONFIG_DRM_IMX_TVE=y +CONFIG_DRM_IMX_LDB=y +CONFIG_DRM_IMX8QM_LDB=y +CONFIG_DRM_IMX8QXP_LDB=y +CONFIG_DRM_IMX8MP_LDB=y +CONFIG_DRM_IMX_HDMI=y +CONFIG_DRM_IMX_SEC_DSIM=y +CONFIG_DRM_IMX_CDNS_MHDP=y +CONFIG_DRM_IMX_DCSS=y +CONFIG_DRM_ETNAVIV=m +CONFIG_DRM_HISI_HIBMC=m +CONFIG_DRM_HISI_KIRIN=m +CONFIG_DRM_MXSFB=y +CONFIG_DRM_PL111=m +CONFIG_DRM_LIMA=m +CONFIG_DRM_PANFROST=m +CONFIG_FB_ARMCLCD=y +CONFIG_FB_EFI=y +CONFIG_BACKLIGHT_GENERIC=m +CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_LP855X=m +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_SOC=y +CONFIG_SND_SOC_FSL_DAI=m +CONFIG_SND_SOC_FSL_EASRC=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_IMX_AK4458=y +CONFIG_SND_SOC_IMX_AK5558=y +CONFIG_SND_SOC_IMX_AK4497=y +CONFIG_SND_SOC_IMX_WM8960=y +CONFIG_SND_SOC_IMX_WM8524=y +CONFIG_SND_SOC_IMX_CS42888=y +CONFIG_SND_SOC_IMX_MICFIL=y +CONFIG_SND_SOC_IMX_RPMSG=y +CONFIG_SND_SOC_IMX_MQS=y +CONFIG_SND_SOC_IMX_SPDIF=y +CONFIG_SND_SOC_IMX_AUDMIX=y +CONFIG_SND_SOC_IMX_PDM_MIC=y +CONFIG_SND_SOC_IMX_DSP=y +CONFIG_SND_SOC_IMX_CDNHDMI=y +CONFIG_SND_SOC_IMX_XCVR=y +CONFIG_SND_SOC_SOF_TOPLEVEL=y +CONFIG_SND_SOC_SOF_OF=m +CONFIG_SND_SOC_SOF_IMX_TOPLEVEL=y +CONFIG_SND_SOC_SOF_IMX8_SUPPORT=m +CONFIG_SND_SOC_SOF_IMX8M_SUPPORT=m +CONFIG_SND_SOC_AK4613=m +CONFIG_SND_SOC_BT_SCO=y +CONFIG_SND_SOC_DMIC=m +CONFIG_SND_SOC_ES7134=m +CONFIG_SND_SOC_ES7241=m +CONFIG_SND_SOC_MAX98357A=m +CONFIG_SND_SOC_PCM3168A_I2C=m +CONFIG_SND_SOC_SGTL5000=m +CONFIG_SND_SOC_SPDIF=m +CONFIG_SND_SOC_TAS571X=m +CONFIG_SND_SIMPLE_CARD=y +CONFIG_SND_AUDIO_GRAPH_CARD=y +CONFIG_I2C_HID=m +CONFIG_USB=y +CONFIG_USB_OTG=y +CONFIG_USB_OTG_WHITELIST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_HCD_TEST_MODE=y +CONFIG_USB_ACM=m +CONFIG_USB_STORAGE=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC2=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_ISP1760=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_CONSOLE=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=y +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_TEST=m +CONFIG_USB_EHSET_TEST_FIXTURE=m +CONFIG_USB_HSIC_USB3503=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_USB_SNP_UDC_PLAT=y +CONFIG_USB_BDC_UDC=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_USB_ETH=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_TYPEC=y +CONFIG_TYPEC_TCPM=y +CONFIG_TYPEC_TCPCI=y +CONFIG_TYPEC_SWITCH_GPIO=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_ARMMMCI=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ACPI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_ARASAN=y +CONFIG_MMC_SDHCI_OF_ESDHC=y +CONFIG_MMC_SDHCI_CADENCE=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MMC_SDHCI_F_SDH30=y +CONFIG_MMC_SPI=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_EXYNOS=y +CONFIG_MMC_DW_HI3798CV200=y +CONFIG_MMC_DW_K3=y +CONFIG_MMC_SDHCI_XENON=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_EDAC=y +CONFIG_EDAC_GHES=y +CONFIG_EDAC_SYNOPSYS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_MAX77686=y +CONFIG_RTC_DRV_RK808=m +CONFIG_RTC_DRV_PCF85363=y +CONFIG_RTC_DRV_RX8581=m +CONFIG_RTC_DRV_S5M=y +CONFIG_RTC_DRV_DS3232=y +CONFIG_RTC_DRV_PCF2127=y +CONFIG_RTC_DRV_EFI=y +CONFIG_RTC_DRV_CROS_EC=y +CONFIG_RTC_DRV_PL031=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_RTC_DRV_IMX_SC=y +CONFIG_DMADEVICES=y +CONFIG_BCM_SBA_RAID=m +CONFIG_FSL_EDMA=y +CONFIG_FSL_EDMA_V3=y +CONFIG_IMX_SDMA=y +CONFIG_MV_XOR_V2=y +CONFIG_MXS_DMA=y +CONFIG_PL330_DMA=y +CONFIG_QCOM_HIDMA_MGMT=y +CONFIG_QCOM_HIDMA=y +CONFIG_DMATEST=y +CONFIG_UIO=y +CONFIG_UIO_PCI_GENERIC=y +CONFIG_UIO_IVSHMEM=y +CONFIG_VFIO=y +CONFIG_VFIO_PCI=y +CONFIG_VFIO_FSL_MC=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_BALLOON=y +CONFIG_VIRTIO_MMIO=y +CONFIG_XEN_GNTDEV=y +CONFIG_XEN_GRANT_DEV_ALLOC=y +CONFIG_STAGING=y +CONFIG_STAGING_MEDIA=y +CONFIG_VIDEO_IMX_CAPTURE=y +CONFIG_ION=y +CONFIG_ION_SYSTEM_HEAP=y +CONFIG_ION_CMA_HEAP=y +CONFIG_FSL_DPAA2=y +CONFIG_FSL_DPAA2_ETHSW=y +CONFIG_FSL_DPAA2_MAC=y +CONFIG_FSL_SDK_DPA=y +CONFIG_FSL_PPFE=y +CONFIG_FSL_PPFE_UTIL_DISABLED=y +CONFIG_MFD_CROS_EC=y +CONFIG_CROS_EC_I2C=y +CONFIG_CROS_EC_SPI=y +CONFIG_COMMON_CLK_VERSATILE=y +CONFIG_CLK_SP810=y +CONFIG_CLK_VEXPRESS_OSC=y +CONFIG_COMMON_CLK_RK808=y +CONFIG_COMMON_CLK_SCPI=y +CONFIG_COMMON_CLK_CS2000_CP=y +CONFIG_COMMON_CLK_S2MPS11=y +CONFIG_COMMON_CLK_XGENE=y +CONFIG_COMMON_CLK_PWM=y +CONFIG_CLK_IMX8MM=y +CONFIG_CLK_IMX8MN=y +CONFIG_CLK_IMX8MP=y +CONFIG_CLK_IMX8MQ=y +CONFIG_CLK_IMX8QXP=y +CONFIG_HWSPINLOCK=y +CONFIG_ARM_MHU=y +CONFIG_IMX_MBOX=y +CONFIG_PLATFORM_MHU=y +CONFIG_ARM_SMMU=y +CONFIG_ARM_SMMU_V3=y +CONFIG_REMOTEPROC=y +CONFIG_IMX_REMOTEPROC=y +CONFIG_RPMSG_QCOM_GLINK_RPM=y +CONFIG_SOC_BRCMSTB=y +CONFIG_FSL_MC_DPIO=y +CONFIG_FSL_QIXIS=y +CONFIG_IMX_SCU_SOC=y +CONFIG_SECVIO_SC=y +CONFIG_SOC_TI=y +CONFIG_EXTCON_USB_GPIO=y +CONFIG_EXTCON_USBC_CROS_EC=y +CONFIG_IIO=y +CONFIG_IMX8QXP_ADC=y +CONFIG_IIO_CROS_EC_SENSORS_CORE=m +CONFIG_IIO_CROS_EC_SENSORS=m +CONFIG_IIO_CROS_EC_LIGHT_PROX=m +CONFIG_IIO_CROS_EC_BARO=m +CONFIG_PWM=y +CONFIG_PWM_CROS_EC=m +CONFIG_PWM_IMX27=y +CONFIG_PHY_XGENE=y +CONFIG_PHY_MIXEL_LVDS=y +CONFIG_PHY_MIXEL_LVDS_COMBO=y +CONFIG_PHY_FSL_IMX8MP_LVDS=y +CONFIG_PHY_MIXEL_MIPI_DPHY=y +CONFIG_PHY_SAMSUNG_HDMI_PHY=y +CONFIG_PHY_QCOM_USB_HS=y +CONFIG_PHY_SAMSUNG_USB2=y +CONFIG_FSL_IMX8_DDR_PMU=y +CONFIG_HISI_PMU=y +CONFIG_NVMEM_IMX_OCOTP=y +CONFIG_NVMEM_IMX_OCOTP_SCU=y +CONFIG_FPGA=y +CONFIG_FPGA_BRIDGE=m +CONFIG_ALTERA_FREEZE_BRIDGE=m +CONFIG_FPGA_REGION=m +CONFIG_OF_FPGA_REGION=m +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_MUX_MMIO=y +CONFIG_MXC_SIM=y +CONFIG_MXC_EMVSIM=y +CONFIG_MXC_MLB150=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_VFAT_FS=y +CONFIG_HUGETLBFS=y +CONFIG_EFIVAR_FS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_SQUASHFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_9P_FS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_SECURITY=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_TLS=m +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y +CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=y +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_STREEBOG=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_TEA=m +CONFIG_INDIRECT_PIO=y +CONFIG_CMA_SIZE_MBYTES=320 +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_FTRACE is not set +CONFIG_MEMTEST=y +CONFIG_CORESIGHT=y +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y +CONFIG_CORESIGHT_SOURCE_ETM4X=y diff --git a/arch/arm64/configs/lsdk.config b/arch/arm64/configs/lsdk.config new file mode 100644 index 00000000000000..ca9ca8d7054728 --- /dev/null +++ b/arch/arm64/configs/lsdk.config @@ -0,0 +1,164 @@ +#uio +CONFIG_UIO=y +CONFIG_UIO_CIF=y +CONFIG_UIO_PDRV_GENIRQ=y +CONFIG_UIO_DMEM_GENIRQ=y +CONFIG_UIO_AEC=y +CONFIG_UIO_SERCOS3=y +CONFIG_UIO_PCI_GENERIC=y +CONFIG_UIO_NETX=y +CONFIG_UIO_MF624=y +# general options +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SLAB=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODVERSIONS=y +CONFIG_BLK_DEV_RAM=y +CONFIG_PID_IN_CONTEXTIDR=y +CONFIG_EXPERT=y +CONFIG_CHECKPOINT_RESTORE=y +# virtualization +CONFIG_VHOST_NET=y +CONFIG_KVM_ARM_MAX_VCPUS=8 +# network and misc +CONFIG_NET_DSA=y +CONFIG_NET_DSA_MSCC_FELIX=y +CONFIG_MSCC_FELIX_SWITCH_TSN=y +CONFIG_INET_ESP=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_CRYPTO_USER=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_BLK_DEV_THROTTLING=y +CONFIG_CFQ_GROUP_IOSCHED=y +CONFIG_TMPFS_XATTR=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y +CONFIG_NETFILTER_NETLINK=y +CONFIG_NETFILTER_XTABLES=y +CONFIG_NETFILTER_XT_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_NAT=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_NF_TABLES=y +CONFIG_NFT_CT=y +CONFIG_NFT_RBTREE=y +CONFIG_NFT_MASQ=y +CONFIG_NFT_NAT=y +CONFIG_NFT_COMPAT=y +CONFIG_NF_DEFRAG_IPV4=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +CONFIG_NF_TABLES_IPV4=y +CONFIG_NF_NAT_IPV4=y +CONFIG_NF_NAT_MASQUERADE_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_MANGLE=y +CONFIG_NF_TABLES_BRIDGE=y +CONFIG_BRIDGE_NF_EBTABLES=y +CONFIG_BRIDGE_EBT_T_NAT=y +CONFIG_BRIDGE_EBT_DNAT=y +CONFIG_BRIDGE_EBT_SNAT=y +CONFIG_UNIX_DIAG=y +CONFIG_PACKET_DIAG=y +CONFIG_NETLINK_DIAG=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y + +# disable unneeded options and override default options set by defconfig to deduce the size of modules +# CONFIG_USB_NET_DRIVERS is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_BACKLIGHT_GENERIC is not set +# CONFIG_TEGRA_HOST1X is not set +# CONFIG_BT is not set +# CONFIG_CFG80211 is not set +# CONFIG_MAC80211 is not set +# CONFIG_DRM_TEGRA is not set +# CONFIG_DRM_EXYNOS is not set +# CONFIG_DRM_MSM is not set +# CONFIG_DRM_VC4 is not set +# CONFIG_DRM_HISI_HIBMC is not set +# CONFIG_DRM_HISI_KIRIN is not set +# CONFIG_DRM_MESON is not set +# CONFIG_DRM_ROCKCHIP is not set +# CONFIG_DRM_RCAR_DU is not set +# CONFIG_USB_RENESAS_USBHS is not set +# CONFIG_QCOM_EMAC is not set +# CONFIG_SND_SOC_ROCKCHIP is not set + +CONFIG_IPV6=y +CONFIG_NF_NAT_IPV6=y +CONFIG_NF_NAT_MASQUERADE_IPV6=y +CONFIG_NF_REJECT_IPV6=y +CONFIG_IPV6_SIT=y +CONFIG_NF_LOG_IPV6=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_VLAN_8021Q=y +CONFIG_BRIDGE=y +CONFIG_MACVLAN=y +CONFIG_MACVTAP=y +CONFIG_BTRFS_FS=y +CONFIG_FUSE_FS=y +CONFIG_SQUASHFS_XZ=y + +# lxc +CONFIG_UNIX_DIAG=y +CONFIG_PACKET_DIAG=y +CONFIG_NETLINK_DIAG=y +CONFIG_CGROUP_FREEZER=y + +# sound +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y + +# docker +CONFIG_OVERLAY_FS=y + +# enable iommu passthrough by default for performance +CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y + +# disable the "disable_bypass" temporarily to workaround the MC issue with it +CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=n + +# decrease the default number of CPUs to the maximum available on NXP +# platforms to increase performance +CONFIG_NR_CPUS=16 + +#Qos +CONFIG_NETFILTER_INGRESS=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_MULTIQ=y +CONFIG_NET_SCH_MQPRIO=y +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=y +CONFIG_NET_CLS_TCINDEX=y +CONFIG_NET_CLS_U32=y +CONFIG_NET_CLS_FLOWER=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_U32=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_PEDIT=y +CONFIG_NET_ACT_SKBEDIT=y +CONFIG_NET_ACT_VLAN=y +CONFIG_NET_ACT_SKBMOD=y +# CONFIG_NET_PKTGEN is not set +CONFIG_USB_NET_DRIVERS=y +CONFIG_USB_RTL8152=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_AX8817X=y +CONFIG_USB_NET_AX88179_178A=y diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h index 323cb306bd2884..0b4bbc602222c8 100644 --- a/arch/arm64/include/asm/io.h +++ b/arch/arm64/include/asm/io.h @@ -170,6 +170,7 @@ extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size); #define ioremap_nocache(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE)) #define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC)) #define ioremap_wt(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE)) +#define ioremap_cache_ns(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NS)) /* * PCI configuration space mapping function. diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index ddf9d762ac6229..a4ffd9b55e72ca 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -72,11 +72,12 @@ * IMO: Override CPSR.I and enable signaling with VI * FMO: Override CPSR.F and enable signaling with VF * SWIO: Turn set/way invalidates into set/way clean+invalidate + * PTW: Take a stage2 fault if a stage1 walk steps in device memory */ #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \ HCR_TVM | HCR_BSU_IS | HCR_FB | HCR_TAC | \ HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \ - HCR_FMO | HCR_IMO) + HCR_FMO | HCR_IMO | HCR_PTW ) #define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF) #define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK) #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H) diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h index 44a243754c1b88..64d79b28843440 100644 --- a/arch/arm64/include/asm/kvm_asm.h +++ b/arch/arm64/include/asm/kvm_asm.h @@ -88,6 +88,34 @@ extern u32 __kvm_get_mdcr_el2(void); *__hyp_this_cpu_ptr(sym); \ }) +#define __KVM_EXTABLE(from, to) \ + " .pushsection __kvm_ex_table, \"a\"\n" \ + " .align 3\n" \ + " .long (" #from " - .), (" #to " - .)\n" \ + " .popsection\n" + + +#define __kvm_at(at_op, addr) \ +( { \ + int __kvm_at_err = 0; \ + u64 spsr, elr; \ + asm volatile( \ + " mrs %1, spsr_el2\n" \ + " mrs %2, elr_el2\n" \ + "1: at "at_op", %3\n" \ + " isb\n" \ + " b 9f\n" \ + "2: msr spsr_el2, %1\n" \ + " msr elr_el2, %2\n" \ + " mov %w0, %4\n" \ + "9:\n" \ + __KVM_EXTABLE(1b, 2b) \ + : "+r" (__kvm_at_err), "=&r" (spsr), "=&r" (elr) \ + : "r" (addr), "i" (-EFAULT)); \ + __kvm_at_err; \ +} ) + + #else /* __ASSEMBLY__ */ .macro hyp_adr_this_cpu reg, sym, tmp @@ -113,6 +141,21 @@ extern u32 __kvm_get_mdcr_el2(void); kern_hyp_va \vcpu .endm +/* + * KVM extable for unexpected exceptions. + * In the same format _asm_extable, but output to a different section so that + * it can be mapped to EL2. The KVM version is not sorted. The caller must + * ensure: + * x18 has the hypervisor value to allow any Shadow-Call-Stack instrumented + * code to write to it, and that SPSR_EL2 and ELR_EL2 are restored by the fixup. + */ +.macro _kvm_extable, from, to + .pushsection __kvm_ex_table, "a" + .align 3 + .long (\from - .), (\to - .) + .popsection +.endm + #endif #endif /* __ARM_KVM_ASM_H__ */ diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h index befe37d4bc0e5c..dd4b4d5afa478f 100644 --- a/arch/arm64/include/asm/kvm_mmu.h +++ b/arch/arm64/include/asm/kvm_mmu.h @@ -156,7 +156,8 @@ void stage2_unmap_vm(struct kvm *kvm); int kvm_alloc_stage2_pgd(struct kvm *kvm); void kvm_free_stage2_pgd(struct kvm *kvm); int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa, - phys_addr_t pa, unsigned long size, bool writable); + phys_addr_t pa, unsigned long size, bool writable, + pgprot_t prot); int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run); @@ -341,8 +342,16 @@ static inline void __invalidate_icache_guest_page(kvm_pfn_t pfn, static inline void __kvm_flush_dcache_pte(pte_t pte) { if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) { - struct page *page = pte_page(pte); - kvm_flush_dcache_to_poc(page_address(page), PAGE_SIZE); + if (pfn_valid(pte_pfn(pte))) { + struct page *page = pte_page(pte); + + kvm_flush_dcache_to_poc(page_address(page), PAGE_SIZE); + } else { + void __iomem *va = ioremap_cache_ns(pte_pfn(pte) << PAGE_SHIFT, PAGE_SIZE); + + kvm_flush_dcache_to_poc(va, PAGE_SIZE); + iounmap(va); + } } } diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h index 3df60f97da1f2c..a0f789fa25f395 100644 --- a/arch/arm64/include/asm/pgtable-hwdef.h +++ b/arch/arm64/include/asm/pgtable-hwdef.h @@ -215,6 +215,7 @@ #define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x)) #define TCR_TxSZ_WIDTH 6 #define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET) +#define TCR_T1SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET) #define TCR_EPD0_SHIFT 7 #define TCR_EPD0_MASK (UL(1) << TCR_EPD0_SHIFT) diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h index 99b0a32e25c1f4..233f7828a6cd0b 100644 --- a/arch/arm64/include/asm/pgtable-prot.h +++ b/arch/arm64/include/asm/pgtable-prot.h @@ -37,6 +37,7 @@ #define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC)) #define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT)) #define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL)) +#define PROT_NORMAL_NS (PTE_TYPE_PAGE | PTE_AF | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL)) #define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE)) #define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL)) @@ -77,6 +78,7 @@ }) #define PAGE_S2 __pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(NORMAL) | PTE_S2_RDONLY | PAGE_S2_XN) +#define PAGE_S2_NS __pgprot(PAGE_S2_MEMATTR(NORMAL) | PTE_S2_RDWR | PTE_TYPE_PAGE | PTE_AF) #define PAGE_S2_DEVICE __pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_S2_XN) #define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN) diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 41dd4b1f0ccbaf..cc9564ce57a006 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -414,6 +414,11 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd) __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) #define pgprot_writecombine(prot) \ __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) +#define pgprot_cached(prot) \ + __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL) | \ + PTE_PXN | PTE_UXN) +#define pgprot_cached_ns(prot) \ + __pgprot(pgprot_val(pgprot_cached(prot)) ^ PTE_SHARED) #define pgprot_device(prot) \ __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) /* diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index bc39490647259a..6042814301ed5c 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -15,6 +15,12 @@ #include #include +#ifdef CONFIG_IMX_SCU_SOC +extern bool TKT340553_SW_WORKAROUND; +#else +#define TKT340553_SW_WORKAROUND 0 +#endif + /* * Raw TLBI operations. * @@ -149,8 +155,12 @@ static inline void flush_tlb_mm(struct mm_struct *mm) unsigned long asid = __TLBI_VADDR(0, ASID(mm)); dsb(ishst); - __tlbi(aside1is, asid); - __tlbi_user(aside1is, asid); + if (TKT340553_SW_WORKAROUND) { + __tlbi(vmalle1is); + } else { + __tlbi(aside1is, asid); + __tlbi_user(aside1is, asid); + } dsb(ish); } @@ -160,8 +170,12 @@ static inline void flush_tlb_page_nosync(struct vm_area_struct *vma, unsigned long addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm)); dsb(ishst); - __tlbi(vale1is, addr); - __tlbi_user(vale1is, addr); + if (TKT340553_SW_WORKAROUND) { + __tlbi(vmalle1is); + } else { + __tlbi(vale1is, addr); + __tlbi_user(vale1is, addr); + } } static inline void flush_tlb_page(struct vm_area_struct *vma, @@ -183,6 +197,7 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, { unsigned long asid = ASID(vma->vm_mm); unsigned long addr; + unsigned long mask = (1 << 20) - 1; start = round_down(start, stride); end = round_up(end, stride); @@ -197,10 +212,13 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, start = __TLBI_VADDR(start, asid); end = __TLBI_VADDR(end, asid); + mask <<= 24; dsb(ishst); for (addr = start; addr < end; addr += stride) { - if (last_level) { + if (TKT340553_SW_WORKAROUND) { + __tlbi(vmalle1is); + } else if (last_level) { __tlbi(vale1is, addr); __tlbi_user(vale1is, addr); } else { @@ -208,6 +226,7 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, __tlbi_user(vae1is, addr); } } + dsb(ish); } @@ -234,8 +253,12 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end end = __TLBI_VADDR(end, 0); dsb(ishst); - for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12)) - __tlbi(vaale1is, addr); + for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12)) { + if (TKT340553_SW_WORKAROUND) + __tlbi(vmalle1is); + else + __tlbi(vaale1is, addr); + } dsb(ish); isb(); } @@ -249,7 +272,10 @@ static inline void __flush_tlb_kernel_pgtable(unsigned long kaddr) unsigned long addr = __TLBI_VADDR(kaddr, 0); dsb(ishst); - __tlbi(vaae1is, addr); + if (TKT340553_SW_WORKAROUND) + __tlbi(vmalle1is); + else + __tlbi(vaae1is, addr); dsb(ish); isb(); } diff --git a/arch/arm64/include/asm/virt.h b/arch/arm64/include/asm/virt.h index 0958ed6191aa34..b1b48353e3b3f9 100644 --- a/arch/arm64/include/asm/virt.h +++ b/arch/arm64/include/asm/virt.h @@ -62,6 +62,8 @@ */ extern u32 __boot_cpu_mode[2]; +extern char __hyp_stub_vectors[]; + void __hyp_set_vectors(phys_addr_t phys_vector_base); void __hyp_reset_vectors(void); diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index f400cb29b811a9..933f7a2eab5902 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -563,9 +563,27 @@ init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *ca } } +#ifdef CONFIG_IMX_SCU_SOC +extern bool TKT340553_SW_WORKAROUND; +#else +#define TKT340553_SW_WORKAROUND 0 +#endif + static void __init init_cpu_hwcaps_indirect_list(void) { init_cpu_hwcaps_indirect_list_from_array(arm64_features); +#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE +#if defined(CONFIG_ARM64_ERRATUM_826319) || \ + defined(CONFIG_ARM64_ERRATUM_827319) || \ + defined(CONFIG_ARM64_ERRATUM_824069) + if (TKT340553_SW_WORKAROUND) { + struct midr_range *midr_range_list = + (struct midr_range *)(arm64_errata[0].midr_range_list); + + midr_range_list[0].rv_max = MIDR_CPU_VAR_REV(0, 4); + } +#endif +#endif init_cpu_hwcaps_indirect_list_from_array(arm64_errata); } diff --git a/arch/arm64/kernel/crash_core.c b/arch/arm64/kernel/crash_core.c index ca4c3e12d8c599..f78310ba65eae9 100644 --- a/arch/arm64/kernel/crash_core.c +++ b/arch/arm64/kernel/crash_core.c @@ -7,6 +7,13 @@ #include #include +static inline u64 get_tcr_el1_t1sz(void); + +static inline u64 get_tcr_el1_t1sz(void) +{ + return (read_sysreg(tcr_el1) & TCR_T1SZ_MASK) >> TCR_T1SZ_OFFSET; +} + void arch_crash_save_vmcoreinfo(void) { VMCOREINFO_NUMBER(VA_BITS); @@ -15,5 +22,7 @@ void arch_crash_save_vmcoreinfo(void) kimage_voffset); vmcoreinfo_append_str("NUMBER(PHYS_OFFSET)=0x%llx\n", PHYS_OFFSET); + vmcoreinfo_append_str("NUMBER(tcr_el1_t1sz)=0x%llx\n", + get_tcr_el1_t1sz()); vmcoreinfo_append_str("KERNELOFFSET=%lx\n", kaslr_offset()); } diff --git a/arch/arm64/kernel/hyp-stub.S b/arch/arm64/kernel/hyp-stub.S index 73d46070b31500..abfea3b78f7fea 100644 --- a/arch/arm64/kernel/hyp-stub.S +++ b/arch/arm64/kernel/hyp-stub.S @@ -42,6 +42,7 @@ ENTRY(__hyp_stub_vectors) ventry el1_fiq_invalid // FIQ 32-bit EL1 ventry el1_error_invalid // Error 32-bit EL1 ENDPROC(__hyp_stub_vectors) +EXPORT_SYMBOL(__hyp_stub_vectors); .align 11 diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c index 570988c7a7ffa9..95c06f634f4985 100644 --- a/arch/arm64/kernel/pci.c +++ b/arch/arm64/kernel/pci.c @@ -13,11 +13,14 @@ #include #include #include +#include #include #include #include #include +#include "../../../drivers/pci/pcie/portdrv.h" + #ifdef CONFIG_ACPI /* * Try to assign the IRQ number when probing a new device @@ -31,6 +34,47 @@ int pcibios_alloc_irq(struct pci_dev *dev) } #endif +/* + * Check device tree if the service interrupts are there + */ +int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask) +{ + int ret, count = 0; + struct device_node *np = NULL; + + if (dev->bus->dev.of_node) + np = dev->bus->dev.of_node; + + if (np == NULL) + return 0; + + if (!IS_ENABLED(CONFIG_OF_IRQ)) + return 0; + + /* If root port doesn't support MSI/MSI-X/INTx in RC mode, + * request irq for aer + */ + if (mask & PCIE_PORT_SERVICE_AER) { + ret = of_irq_get_byname(np, "aer"); + if (ret > 0) { + irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret; + count++; + } + } + + if (mask & PCIE_PORT_SERVICE_PME) { + ret = of_irq_get_byname(np, "pme"); + if (ret > 0) { + irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret; + count++; + } + } + + /* TODO: add more service interrupts if there it is in the device tree*/ + + return count; +} + /* * raw_pci_read/write - Platform-specific PCI config space access. */ diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index 4e3e9d9c81517c..ace993b5664c4e 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -426,6 +426,34 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs) uaccess_ttbr0_disable(); \ } +#define __user_cache_maint_ivau(insn, address, res) \ + do { \ + if (address >= user_addr_max()) { \ + res = -EFAULT; \ + } else { \ + uaccess_ttbr0_enable(); \ + asm volatile ( \ + "1: " insn "\n" \ + " mov %w0, #0\n" \ + "2:\n" \ + " .pushsection .fixup,\"ax\"\n" \ + " .align 2\n" \ + "3: mov %w0, %w2\n" \ + " b 2b\n" \ + " .popsection\n" \ + _ASM_EXTABLE(1b, 3b) \ + : "=r" (res) \ + : "r" (address), "i" (-EFAULT)); \ + uaccess_ttbr0_disable(); \ + } \ + } while (0) + +#ifdef CONFIG_IMX_SCU_SOC +extern bool TKT340553_SW_WORKAROUND; +#else +#define TKT340553_SW_WORKAROUND 0 +#endif + static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs) { unsigned long address; @@ -452,7 +480,10 @@ static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs) __user_cache_maint("dc civac", address, ret); break; case ESR_ELx_SYS64_ISS_CRM_IC_IVAU: /* IC IVAU */ - __user_cache_maint("ic ivau", address, ret); + if (TKT340553_SW_WORKAROUND) + __user_cache_maint_ivau("ic ialluis", address, ret); + else + __user_cache_maint("ic ivau", address, ret); break; default: force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc); diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S index 8d0374ffdd2d6e..4f77de8ce1384b 100644 --- a/arch/arm64/kernel/vmlinux.lds.S +++ b/arch/arm64/kernel/vmlinux.lds.S @@ -24,6 +24,13 @@ ENTRY(_text) jiffies = jiffies_64; + +#define HYPERVISOR_EXTABLE \ + . = ALIGN(SZ_8); \ + __start___kvm_ex_table = .; \ + *(__kvm_ex_table) \ + __stop___kvm_ex_table = .; + #define HYPERVISOR_TEXT \ /* \ * Align to 4 KB so that \ @@ -39,6 +46,7 @@ jiffies = jiffies_64; __hyp_idmap_text_end = .; \ __hyp_text_start = .; \ *(.hyp.text) \ + HYPERVISOR_EXTABLE \ __hyp_text_end = .; #define IDMAP_TEXT \ diff --git a/arch/arm64/kvm/hyp/entry.S b/arch/arm64/kvm/hyp/entry.S index e5cc8d66bf537e..dc3d7bc2292fd0 100644 --- a/arch/arm64/kvm/hyp/entry.S +++ b/arch/arm64/kvm/hyp/entry.S @@ -173,20 +173,23 @@ alternative_endif // This is our single instruction exception window. A pending // SError is guaranteed to occur at the earliest when we unmask // it, and at the latest just after the ISB. - .global abort_guest_exit_start abort_guest_exit_start: isb - .global abort_guest_exit_end abort_guest_exit_end: msr daifset, #4 // Mask aborts + ret + + _kvm_extable abort_guest_exit_start, 9997f + _kvm_extable abort_guest_exit_end, 9997f +9997: + msr daifset, #4 // Mask aborts + mov x0, #(1 << ARM_EXIT_WITH_SERROR_BIT) - // If the exception took place, restore the EL1 exception - // context so that we can report some information. - // Merge the exception code with the SError pending bit. - tbz x0, #ARM_EXIT_WITH_SERROR_BIT, 1f + // restore the EL1 exception context so that we can report some + // information. Merge the exception code with the SError pending bit. msr elr_el2, x2 msr esr_el2, x3 msr spsr_el2, x4 diff --git a/arch/arm64/kvm/hyp/hyp-entry.S b/arch/arm64/kvm/hyp/hyp-entry.S index ffa68d5713f1d8..f36aad0f207bb5 100644 --- a/arch/arm64/kvm/hyp/hyp-entry.S +++ b/arch/arm64/kvm/hyp/hyp-entry.S @@ -15,6 +15,30 @@ #include #include +.macro save_caller_saved_regs_vect + /* x0 and x1 were saved in the vector entry */ + stp x2, x3, [sp, #-16]! + stp x4, x5, [sp, #-16]! + stp x6, x7, [sp, #-16]! + stp x8, x9, [sp, #-16]! + stp x10, x11, [sp, #-16]! + stp x12, x13, [sp, #-16]! + stp x14, x15, [sp, #-16]! + stp x16, x17, [sp, #-16]! +.endm + +.macro restore_caller_saved_regs_vect + ldp x16, x17, [sp], #16 + ldp x14, x15, [sp], #16 + ldp x12, x13, [sp], #16 + ldp x10, x11, [sp], #16 + ldp x8, x9, [sp], #16 + ldp x6, x7, [sp], #16 + ldp x4, x5, [sp], #16 + ldp x2, x3, [sp], #16 + ldp x0, x1, [sp], #16 +.endm + .text .pushsection .hyp.text, "ax" @@ -142,13 +166,19 @@ el1_error: b __guest_exit el2_sync: - /* Check for illegal exception return, otherwise panic */ + /* Check for illegal exception return */ mrs x0, spsr_el2 + tbnz x0, #20, 1f - /* if this was something else, then panic! */ - tst x0, #PSR_IL_BIT - b.eq __hyp_panic + save_caller_saved_regs_vect + stp x29, x30, [sp, #-16]! + bl kvm_unexpected_el2_exception + ldp x29, x30, [sp], #16 + restore_caller_saved_regs_vect + eret + +1: /* Let's attempt a recovery from the illegal exception return */ get_vcpu_ptr x1, x0 mov x0, #ARM_EXCEPTION_IL @@ -156,27 +186,14 @@ el2_sync: el2_error: - ldp x0, x1, [sp], #16 + save_caller_saved_regs_vect + stp x29, x30, [sp, #-16]! + + bl kvm_unexpected_el2_exception + + ldp x29, x30, [sp], #16 + restore_caller_saved_regs_vect - /* - * Only two possibilities: - * 1) Either we come from the exit path, having just unmasked - * PSTATE.A: change the return code to an EL2 fault, and - * carry on, as we're already in a sane state to handle it. - * 2) Or we come from anywhere else, and that's a bug: we panic. - * - * For (1), x0 contains the original return code and x1 doesn't - * contain anything meaningful at that stage. We can reuse them - * as temp registers. - * For (2), who cares? - */ - mrs x0, elr_el2 - adr x1, abort_guest_exit_start - cmp x0, x1 - adr x1, abort_guest_exit_end - ccmp x0, x1, #4, ne - b.ne __hyp_panic - mov x0, #(1 << ARM_EXIT_WITH_SERROR_BIT) eret sb diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c index 6f4838b475d0dd..65660b6144740f 100644 --- a/arch/arm64/kvm/hyp/switch.c +++ b/arch/arm64/kvm/hyp/switch.c @@ -14,6 +14,7 @@ #include #include +#include #include #include #include @@ -25,6 +26,9 @@ #include #include +extern struct exception_table_entry __start___kvm_ex_table; +extern struct exception_table_entry __stop___kvm_ex_table; + /* Check whether the FP regs were dirtied while in the host-side run loop: */ static bool __hyp_text update_fp_enabled(struct kvm_vcpu *vcpu) { @@ -257,10 +261,10 @@ static bool __hyp_text __translate_far_to_hpfar(u64 far, u64 *hpfar) * saved the guest context yet, and we may return early... */ par = read_sysreg(par_el1); - asm volatile("at s1e1r, %0" : : "r" (far)); - isb(); - - tmp = read_sysreg(par_el1); + if (!__kvm_at("s1e1r", far)) + tmp = read_sysreg(par_el1); + else + tmp = SYS_PAR_EL1_F; /* back to the guest */ write_sysreg(par, par_el1); if (unlikely(tmp & SYS_PAR_EL1_F)) @@ -791,3 +795,30 @@ void __hyp_text __noreturn hyp_panic(struct kvm_cpu_context *host_ctxt) unreachable(); } + +asmlinkage void __hyp_text kvm_unexpected_el2_exception(void) +{ + unsigned long addr, fixup; + struct kvm_cpu_context *host_ctxt; + struct exception_table_entry *entry, *end; + unsigned long elr_el2 = read_sysreg(elr_el2); + + entry = hyp_symbol_addr(__start___kvm_ex_table); + end = hyp_symbol_addr(__stop___kvm_ex_table); + host_ctxt = &__hyp_this_cpu_ptr(kvm_host_data)->host_ctxt; + + while (entry < end) { + addr = (unsigned long)&entry->insn + entry->insn; + fixup = (unsigned long)&entry->fixup + entry->fixup; + + if (addr != elr_el2) { + entry++; + continue; + } + + write_sysreg(fixup, elr_el2); + return; + } + + hyp_panic(host_ctxt); +} diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c index eb0efc5557f302..d4c852745deb94 100644 --- a/arch/arm64/kvm/hyp/tlb.c +++ b/arch/arm64/kvm/hyp/tlb.c @@ -16,6 +16,12 @@ struct tlb_inv_context { u64 sctlr; }; +#ifdef CONFIG_IMX_SCU_SOC +extern bool TKT340553_SW_WORKAROUND; +#else +#define TKT340553_SW_WORKAROUND 0 +#endif + static void __hyp_text __tlb_switch_to_guest_vhe(struct kvm *kvm, struct tlb_inv_context *cxt) { @@ -126,8 +132,12 @@ void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa) * Instead, we invalidate Stage-2 for this IPA, and the * whole of Stage-1. Weep... */ - ipa >>= 12; - __tlbi(ipas2e1is, ipa); + if (TKT340553_SW_WORKAROUND) { + __tlbi(vmalls12e1is); + } else { + ipa >>= 12; + __tlbi(ipas2e1is, ipa); + } /* * We have to ensure completion of the invalidation at Stage-2, diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c index 9239416e93d4e9..1cab08bd8f7b7a 100644 --- a/arch/arm64/mm/dma-mapping.c +++ b/arch/arm64/mm/dma-mapping.c @@ -57,3 +57,4 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, dev->dma_ops = &xen_swiotlb_dma_ops; #endif } +EXPORT_SYMBOL(arch_setup_dma_ops); diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c index 45c00a54909c9b..2417fbf727c03b 100644 --- a/arch/arm64/mm/init.c +++ b/arch/arm64/mm/init.c @@ -416,6 +416,8 @@ void __init arm64_memblock_init(void) initrd_end = initrd_start + phys_initrd_size; } + reserve_elfcorehdr(); + early_init_fdt_scan_reserved_mem(); /* 4GB maximum for 32-bit only capable devices */ @@ -426,8 +428,6 @@ void __init arm64_memblock_init(void) reserve_crashkernel(); - reserve_elfcorehdr(); - high_memory = __va(memblock_end_of_DRAM() - 1) + 1; dma_contiguous_reserve(arm64_dma_phys_limit); diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index ad620637cbd119..e924ddd546187e 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -322,7 +322,7 @@ config ARCH_HIBERNATION_POSSIBLE config ARCH_SUSPEND_POSSIBLE def_bool y depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx || \ - (PPC_85xx && !PPC_E500MC) || PPC_86xx || PPC_PSERIES \ + FSL_SOC_BOOKE || PPC_86xx || PPC_PSERIES \ || 44x || 40x config ARCH_SUSPEND_NONZERO_CPU @@ -978,8 +978,6 @@ config FSL_PCI config FSL_PMC bool - default y - depends on SUSPEND && (PPC_85xx || PPC_86xx) help Freescale MPC85xx/MPC86xx power management controller support (suspend/resume). For MPC83xx see platforms/83xx/suspend.c diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile index 37ac731a556b86..099d047219f9ce 100644 --- a/arch/powerpc/Makefile +++ b/arch/powerpc/Makefile @@ -352,6 +352,31 @@ corenet64_smp_defconfig: $(call merge_into_defconfig,corenet_basic_defconfig,\ 85xx-64bit 85xx-smp altivec 85xx-hw fsl-emb-nonhw dpaa) +PHONY += corenet32_smp_sdk_defconfig +corenet32_smp_sdk_defconfig: + $(call merge_into_defconfig,corenet_basic_defconfig,\ + 85xx-32bit 85xx-smp 85xx-hw fsl-emb-nonhw sdk_dpaa) + +PHONY += corenet32_fmanv3l_smp_sdk_defconfig +corenet32_fmanv3l_smp_sdk_defconfig: + $(call merge_into_defconfig,corenet_basic_defconfig,\ + 85xx-32bit 85xx-smp 85xx-hw fsl-emb-nonhw sdk_dpaa fmanv3l) + +PHONY += corenet64_smp_sdk_defconfig +corenet64_smp_sdk_defconfig: + $(call merge_into_defconfig,corenet_basic_defconfig,\ + 85xx-64bit 85xx-smp altivec 85xx-hw fsl-emb-nonhw sdk_dpaa) + +PHONY += corenet64_fmanv3l_smp_sdk_defconfig +corenet64_fmanv3l_smp_sdk_defconfig: + $(call merge_into_defconfig,corenet_basic_defconfig,\ + 85xx-64bit 85xx-smp altivec 85xx-hw fsl-emb-nonhw sdk_dpaa fmanv3l) + +PHONY += corenet64_fmanv3h_smp_sdk_defconfig +corenet64_fmanv3h_smp_sdk_defconfig: + $(call merge_into_defconfig,corenet_basic_defconfig,\ + 85xx-64bit 85xx-smp altivec 85xx-hw fsl-emb-nonhw sdk_dpaa fmanv3h) + PHONY += mpc86xx_defconfig mpc86xx_defconfig: $(call merge_into_defconfig,mpc86xx_basic_defconfig,\ diff --git a/arch/powerpc/boot/dts/fsl/b4420qds-sdk.dts b/arch/powerpc/boot/dts/fsl/b4420qds-sdk.dts new file mode 100644 index 00000000000000..974838fdf86b99 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/b4420qds-sdk.dts @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "b4420qds.dts" diff --git a/arch/powerpc/boot/dts/fsl/b4860qds-sdk.dts b/arch/powerpc/boot/dts/fsl/b4860qds-sdk.dts new file mode 100644 index 00000000000000..d708f9b8599780 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/b4860qds-sdk.dts @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "b4860qds.dts" diff --git a/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi index 41935709ebe87e..fba40a1bccc046 100644 --- a/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi @@ -199,6 +199,10 @@ /include/ "pq3-dma-0.dtsi" /include/ "pq3-etsec1-0.dtsi" + enet0: ethernet@24000 { + fsl,wake-on-filer; + fsl,pmc-handle = <&etsec1_clk>; + }; /include/ "pq3-etsec1-timer-0.dtsi" usb@22000 { @@ -222,9 +226,10 @@ }; /include/ "pq3-etsec1-2.dtsi" - - ethernet@26000 { + enet2: ethernet@26000 { cell-index = <1>; + fsl,wake-on-filer; + fsl,pmc-handle = <&etsec3_clk>; }; usb@2b000 { @@ -249,4 +254,9 @@ reg = <0xe0000 0x1000>; fsl,has-rstcr; }; + +/include/ "pq3-power.dtsi" + power@e0070 { + compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc"; + }; }; diff --git a/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi index b68eb119faef30..ea7416af7ee3ed 100644 --- a/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi @@ -188,4 +188,6 @@ reg = <0xe0000 0x1000>; fsl,has-rstcr; }; + +/include/ "pq3-power.dtsi" }; diff --git a/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi index 579d76cb8e329d..dddb7374508d6b 100644 --- a/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi @@ -156,4 +156,6 @@ reg = <0xe0000 0x1000>; fsl,has-rstcr; }; + +/include/ "pq3-power.dtsi" }; diff --git a/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi index 49294cf36b4e63..40a6cff770327d 100644 --- a/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi @@ -193,4 +193,6 @@ reg = <0xe0000 0x1000>; fsl,has-rstcr; }; + +/include/ "pq3-power.dtsi" }; diff --git a/arch/powerpc/boot/dts/fsl/p1010rdb-pb.dts b/arch/powerpc/boot/dts/fsl/p1010rdb-pb.dts index 3a94acbb3c0331..ce3346d77858f4 100644 --- a/arch/powerpc/boot/dts/fsl/p1010rdb-pb.dts +++ b/arch/powerpc/boot/dts/fsl/p1010rdb-pb.dts @@ -29,3 +29,19 @@ }; /include/ "p1010si-post.dtsi" + +&pci0 { + pcie@0 { + interrupt-map = < + /* IDSEL 0x0 */ + /* + *irq[4:5] are active-high + *irq[6:7] are active-low + */ + 0000 0x0 0x0 0x1 &mpic 0x4 0x2 0x0 0x0 + 0000 0x0 0x0 0x2 &mpic 0x5 0x2 0x0 0x0 + 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 + 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 + >; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/p1010rdb-pb_36b.dts b/arch/powerpc/boot/dts/fsl/p1010rdb-pb_36b.dts index 4cf255fedc96e9..83590354f9a098 100644 --- a/arch/powerpc/boot/dts/fsl/p1010rdb-pb_36b.dts +++ b/arch/powerpc/boot/dts/fsl/p1010rdb-pb_36b.dts @@ -56,3 +56,19 @@ }; /include/ "p1010si-post.dtsi" + +&pci0 { + pcie@0 { + interrupt-map = < + /* IDSEL 0x0 */ + /* + *irq[4:5] are active-high + *irq[6:7] are active-low + */ + 0000 0x0 0x0 0x1 &mpic 0x4 0x2 0x0 0x0 + 0000 0x0 0x0 0x2 &mpic 0x5 0x2 0x0 0x0 + 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 + 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 + >; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/p1010rdb.dtsi b/arch/powerpc/boot/dts/fsl/p1010rdb.dtsi index 2ca9cee2ddeb25..ef49a7d6c69dd5 100644 --- a/arch/powerpc/boot/dts/fsl/p1010rdb.dtsi +++ b/arch/powerpc/boot/dts/fsl/p1010rdb.dtsi @@ -215,19 +215,3 @@ phy-connection-type = "sgmii"; }; }; - -&pci0 { - pcie@0 { - interrupt-map = < - /* IDSEL 0x0 */ - /* - *irq[4:5] are active-high - *irq[6:7] are active-low - */ - 0000 0x0 0x0 0x1 &mpic 0x4 0x2 0x0 0x0 - 0000 0x0 0x0 0x2 &mpic 0x5 0x2 0x0 0x0 - 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 - 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 - >; - }; -}; diff --git a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi index 1b4aafc1f6a27b..47b62a800be055 100644 --- a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi @@ -173,6 +173,8 @@ /include/ "pq3-etsec2-0.dtsi" enet0: ethernet@b0000 { + fsl,pmc-handle = <&etsec1_clk>; + queue-group@b0000 { fsl,rx-bit-map = <0xff>; fsl,tx-bit-map = <0xff>; @@ -181,6 +183,8 @@ /include/ "pq3-etsec2-1.dtsi" enet1: ethernet@b1000 { + fsl,pmc-handle = <&etsec2_clk>; + queue-group@b1000 { fsl,rx-bit-map = <0xff>; fsl,tx-bit-map = <0xff>; @@ -189,6 +193,8 @@ /include/ "pq3-etsec2-2.dtsi" enet2: ethernet@b2000 { + fsl,pmc-handle = <&etsec3_clk>; + queue-group@b2000 { fsl,rx-bit-map = <0xff>; fsl,tx-bit-map = <0xff>; @@ -201,4 +207,6 @@ reg = <0xe0000 0x1000>; fsl,has-rstcr; }; + +/include/ "pq3-power.dtsi" }; diff --git a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi index 642dc3a83d0e35..cc4c7461003bb9 100644 --- a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi @@ -163,14 +163,17 @@ /include/ "pq3-etsec2-0.dtsi" enet0: enet0_grp2: ethernet@b0000 { + fsl,pmc-handle = <&etsec1_clk>; }; /include/ "pq3-etsec2-1.dtsi" enet1: enet1_grp2: ethernet@b1000 { + fsl,pmc-handle = <&etsec2_clk>; }; /include/ "pq3-etsec2-2.dtsi" enet2: enet2_grp2: ethernet@b2000 { + fsl,pmc-handle = <&etsec3_clk>; }; global-utilities@e0000 { @@ -178,6 +181,8 @@ reg = <0xe0000 0x1000>; fsl,has-rstcr; }; + +/include/ "pq3-power.dtsi" }; /include/ "pq3-etsec2-grp2-0.dtsi" diff --git a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi index 407cb5fd0f5bad..378195db9fca5f 100644 --- a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi @@ -159,14 +159,17 @@ /include/ "pq3-etsec2-0.dtsi" enet0: enet0_grp2: ethernet@b0000 { + fsl,pmc-handle = <&etsec1_clk>; }; /include/ "pq3-etsec2-1.dtsi" enet1: enet1_grp2: ethernet@b1000 { + fsl,pmc-handle = <&etsec2_clk>; }; /include/ "pq3-etsec2-2.dtsi" enet2: enet2_grp2: ethernet@b2000 { + fsl,pmc-handle = <&etsec3_clk>; }; global-utilities@e0000 { @@ -174,6 +177,8 @@ reg = <0xe0000 0x1000>; fsl,has-rstcr; }; + +/include/ "pq3-power.dtsi" }; &qe { diff --git a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi index 5f51b7bfc06404..6ac21e81344ad8 100644 --- a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi @@ -225,11 +225,13 @@ /include/ "pq3-etsec2-0.dtsi" enet0: enet0_grp2: ethernet@b0000 { fsl,wake-on-filer; + fsl,pmc-handle = <&etsec1_clk>; }; /include/ "pq3-etsec2-1.dtsi" enet1: enet1_grp2: ethernet@b1000 { fsl,wake-on-filer; + fsl,pmc-handle = <&etsec2_clk>; }; global-utilities@e0000 { @@ -238,9 +240,10 @@ fsl,has-rstcr; }; - power@e0070{ - compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc"; - reg = <0xe0070 0x20>; +/include/ "pq3-power.dtsi" + power@e0070 { + compatible = "fsl,p1022-pmc", "fsl,mpc8536-pmc", + "fsl,mpc8548-pmc"; }; }; diff --git a/arch/powerpc/boot/dts/fsl/p1023rdb-sdk.dts b/arch/powerpc/boot/dts/fsl/p1023rdb-sdk.dts new file mode 100644 index 00000000000000..85ccbfc9dc890f --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/p1023rdb-sdk.dts @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "p1023rdb.dts" + +&soc { + fman0: fman@100000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + compatible = "fsl,fman", "simple-bus"; + ranges = <0 0x100000 0x100000>; + reg = <0x100000 0x100000>; + clock-frequency = <0>; + interrupts = < + 24 2 0 0 + 16 2 0 0>; + cc@0 { + compatible = "fsl,fman-cc"; + }; + muram@0 { + compatible = "fsl,fman-muram"; + reg = <0x0 0x10000>; + }; + bmi@80000 { + compatible = "fsl,fman-bmi"; + reg = <0x80000 0x400>; + }; + qmi@80400 { + compatible = "fsl,fman-qmi"; + reg = <0x80400 0x400>; + }; + policer@c0000 { + compatible = "fsl,fman-policer"; + reg = <0xc0000 0x1000>; + }; + keygen@c1000 { + compatible = "fsl,fman-keygen"; + reg = <0xc1000 0x1000>; + }; + dma@c2000 { + compatible = "fsl,fman-dma"; + reg = <0xc2000 0x1000>; + }; + fpm@c3000 { + compatible = "fsl,fman-fpm"; + reg = <0xc3000 0x1000>; + }; + parser@c7000 { + compatible = "fsl,fman-parser"; + reg = <0xc7000 0x1000>; + }; + fman0_rx0: port@88000 { + cell-index = <0>; + compatible = "fsl,fman-port-1g-rx"; + reg = <0x88000 0x1000>; + }; + fman0_rx1: port@89000 { + cell-index = <1>; + compatible = "fsl,fman-port-1g-rx"; + reg = <0x89000 0x1000>; + }; + fman0_tx0: port@a8000 { + cell-index = <0>; + compatible = "fsl,fman-port-1g-tx"; + reg = <0xa8000 0x1000>; + fsl,qman-channel-id = <0x40>; + }; + fman0_tx1: port@a9000 { + cell-index = <1>; + compatible = "fsl,fman-port-1g-tx"; + reg = <0xa9000 0x1000>; + fsl,qman-channel-id = <0x41>; + }; + fman0_oh1: port@82000 { + cell-index = <1>; + compatible = "fsl,fman-port-oh"; + reg = <0x82000 0x1000>; + fsl,qman-channel-id = <0x43>; + }; + fman0_oh2: port@83000 { + cell-index = <2>; + compatible = "fsl,fman-port-oh"; + reg = <0x83000 0x1000>; + fsl,qman-channel-id = <0x44>; + }; + fman0_oh3: port@84000 { + cell-index = <3>; + compatible = "fsl,fman-port-oh"; + reg = <0x84000 0x1000>; + fsl,qman-channel-id = <0x45>; + }; + fman0_oh4: port@85000 { + cell-index = <4>; + compatible = "fsl,fman-port-oh"; + reg = <0x85000 0x1000>; + fsl,qman-channel-id = <0x46>; + }; + enet0: ethernet@e0000 { + cell-index = <0>; + compatible = "fsl,fman-dtsec"; + reg = <0xe0000 0x1000>; + fsl,port-handles = <&fman0_rx0 &fman0_tx0>; + }; + enet1: ethernet@e2000 { + cell-index = <1>; + compatible = "fsl,fman-dtsec"; + reg = <0xe2000 0x1000>; + fsl,port-handles = <&fman0_rx1 &fman0_tx1>; + }; + mdio0: mdio@e1120 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,fman-mdio"; + reg = <0xe1120 0xee0>; + interrupts = <26 1 0 0>; + }; + }; +}; + +&bportals { + compatible = "fsl,bpid-range"; + fsl,bpid-range = <32 32>; +}; diff --git a/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi index 884e01bcb2432e..2c4787cbf395fe 100644 --- a/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi @@ -175,6 +175,10 @@ compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr"; }; /include/ "pq3-etsec1-0.dtsi" + enet0: ethernet@24000 { + fsl,pmc-handle = <&etsec1_clk>; + + }; /include/ "pq3-etsec1-timer-0.dtsi" ptp_clock@24e00 { @@ -183,7 +187,15 @@ /include/ "pq3-etsec1-1.dtsi" + enet1: ethernet@25000 { + fsl,pmc-handle = <&etsec2_clk>; + }; + /include/ "pq3-etsec1-2.dtsi" + enet2: ethernet@26000 { + fsl,pmc-handle = <&etsec3_clk>; + }; + /include/ "pq3-esdhc-0.dtsi" sdhc@2e000 { compatible = "fsl,p2020-esdhc", "fsl,esdhc"; @@ -198,4 +210,6 @@ reg = <0xe0000 0x1000>; fsl,has-rstcr; }; + +/include/ "pq3-power.dtsi" }; diff --git a/arch/powerpc/boot/dts/fsl/p2041rdb-sdk.dts b/arch/powerpc/boot/dts/fsl/p2041rdb-sdk.dts new file mode 100644 index 00000000000000..4c8371b316a8d2 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/p2041rdb-sdk.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "p2041rdb.dts" + +/include/ "qoriq-fman-0-sdk.dtsi" +/include/ "qoriq-dpaa-eth.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman1-portals-sdk.dtsi" diff --git a/arch/powerpc/boot/dts/fsl/p3041ds-sdk.dts b/arch/powerpc/boot/dts/fsl/p3041ds-sdk.dts new file mode 100644 index 00000000000000..6f473416a51b3a --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/p3041ds-sdk.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "p3041ds.dts" + +/include/ "qoriq-fman-0-sdk.dtsi" +/include/ "qoriq-dpaa-eth.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman1-portals-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@2 { + status = "disabled"; + }; + }; +}; + diff --git a/arch/powerpc/boot/dts/fsl/p4080ds-sdk.dts b/arch/powerpc/boot/dts/fsl/p4080ds-sdk.dts new file mode 100644 index 00000000000000..6b2dbfc1e08be0 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/p4080ds-sdk.dts @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "p4080ds.dts" + +/ { + + aliases { + phy_rgmii = &phyrgmii; + phy5_slot3 = &phy5slot3; + phy6_slot3 = &phy6slot3; + phy7_slot3 = &phy7slot3; + phy8_slot3 = &phy8slot3; + emi1_slot3 = &p4080mdio2; + emi1_slot4 = &p4080mdio1; + emi1_slot5 = &p4080mdio3; + emi1_rgmii = &p4080mdio0; + emi2_slot4 = &p4080xmdio1; + emi2_slot5 = &p4080xmdio3; + }; +}; + +/include/ "qoriq-fman-0-sdk.dtsi" +/include/ "qoriq-fman-1-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman1-portals-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + ethernet@5 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet5>; + }; + ethernet@6 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet6>; + }; + ethernet@7 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet7>; + }; + ethernet@8 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet8>; + }; + ethernet@9 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet9>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/p5020ds-sdk.dts b/arch/powerpc/boot/dts/fsl/p5020ds-sdk.dts new file mode 100644 index 00000000000000..42240a85054dd3 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/p5020ds-sdk.dts @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "p5020ds.dts" + +/include/ "qoriq-fman-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman1-portals-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + status = "disabled"; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + ethernet@5 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet5>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/p5040ds-sdk.dts b/arch/powerpc/boot/dts/fsl/p5040ds-sdk.dts new file mode 100644 index 00000000000000..d5af499a19624c --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/p5040ds-sdk.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "p5040ds.dts" + +/include/ "qoriq-fman-0-sdk.dtsi" +/include/ "qoriq-fman-1-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman1-portals-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + status = "disabled"; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + ethernet@5 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet5>; + }; + ethernet@6 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet6>; + status = "disabled"; + }; + ethernet@7 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet7>; + }; + ethernet@8 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet8>; + }; + ethernet@9 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet9>; + }; + ethernet@10 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet10>; + }; + ethernet@11 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet11>; + }; + }; +}; + diff --git a/arch/powerpc/boot/dts/fsl/pq3-power.dtsi b/arch/powerpc/boot/dts/fsl/pq3-power.dtsi new file mode 100644 index 00000000000000..5a760b3855bc16 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/pq3-power.dtsi @@ -0,0 +1,48 @@ +/* + * PQ3 Power Management device tree stub + * + * Copyright 2012-2013 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +power@e0070 { + compatible = "fsl,mpc8548-pmc"; + reg = <0xe0070 0x20>; + + etsec1_clk: soc-clk@24 { + fsl,pmcdr-mask = <0x00000080>; + }; + etsec2_clk: soc-clk@25 { + fsl,pmcdr-mask = <0x00000040>; + }; + etsec3_clk: soc-clk@26 { + fsl,pmcdr-mask = <0x00000020>; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-bman-portals-sdk.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-bman-portals-sdk.dtsi new file mode 100644 index 00000000000000..130393056e1cdf --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-bman-portals-sdk.dtsi @@ -0,0 +1,80 @@ +/* + * QorIQ BMan Portal device tree stub for 10 portals + * + * Copyright 2011 - 2014 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +&bportals { + bman-portal@0 { + cell-index = <0>; + }; + + bman-portal@4000 { + cell-index = <1>; + }; + + bman-portal@8000 { + cell-index = <2>; + }; + + bman-portal@c000 { + cell-index = <3>; + }; + + bman-portal@10000 { + cell-index = <4>; + }; + + bman-portal@14000 { + cell-index = <5>; + }; + + bman-portal@18000 { + cell-index = <6>; + }; + + bman-portal@1c000 { + cell-index = <7>; + }; + + bman-portal@20000 { + cell-index = <8>; + }; + + bman-portal@24000 { + cell-index = <9>; + }; + + bman-bpids@0 { + compatible = "fsl,bpid-range"; + fsl,bpid-range = <32 32>; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-dpaa-eth.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-dpaa-eth.dtsi new file mode 100644 index 00000000000000..d12b19191030bc --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-dpaa-eth.dtsi @@ -0,0 +1,62 @@ +/* + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + ethernet@5 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet5>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-10g-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-10g-0.dtsi index eb77675c255a11..29c4c834989051 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-10g-0.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-10g-0.dtsi @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x10: port@90000 { cell-index = <0x10>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-10g-rx"; reg = <0x90000 0x1000>; }; fman0_tx_0x30: port@b0000 { cell-index = <0x30>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-10g-tx"; reg = <0xb0000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-0.dtsi index b965bc219baea9..f8f44eb639fe07 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-0.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-0.dtsi @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x08: port@88000 { cell-index = <0x8>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x88000 0x1000>; }; fman0_tx_0x28: port@a8000 { cell-index = <0x28>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xa8000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-1.dtsi index 9eb6e6dd7cf977..4e55ac7b0e34a0 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-1.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-1.dtsi @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x09: port@89000 { cell-index = <0x9>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x89000 0x1000>; }; fman0_tx_0x29: port@a9000 { cell-index = <0x29>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xa9000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-2.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-2.dtsi index 092b8993674379..4c537954bfbb6b 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-2.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-2.dtsi @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x0a: port@8a000 { cell-index = <0xa>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x8a000 0x1000>; }; fman0_tx_0x2a: port@aa000 { cell-index = <0x2a>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xaa000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-3.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-3.dtsi index 2df0dc87604567..1d458ed65c6818 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-3.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-3.dtsi @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x0b: port@8b000 { cell-index = <0xb>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x8b000 0x1000>; }; fman0_tx_0x2b: port@ab000 { cell-index = <0x2b>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xab000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-4.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-4.dtsi index 5fceb2438fdc4e..e2f4dc73e42ead 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-4.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-4.dtsi @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x0c: port@8c000 { cell-index = <0xc>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x8c000 0x1000>; }; fman0_tx_0x2c: port@ac000 { cell-index = <0x2c>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xac000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-chosen-fifo-resize.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-chosen-fifo-resize.dtsi new file mode 100644 index 00000000000000..46189b62a2115f --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-chosen-fifo-resize.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2018 NXP + */ + +&soc { + chosen { + name = "chosen"; + dpaa-extended-args { + fman0-extd-args { + cell-index = <0>; + compatible = "fsl,fman-extended-args"; + total-fifo-size = <0x27000>; + fman0_oh1-extd-args { + cell-index = <1>; + compatible = "fsl,fman-port-op-extended-args"; + fifo-size = <0x800 0x0>; + num-dmas = <0x1 0x1>; + num-tnums = <0x1 0x4>; + }; + fman0_rx0-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman0_tx0-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman0_rx1-extd-args { + cell-index = <1>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman0_tx1-extd-args { + cell-index = <1>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman0_rx2-extd-args { + cell-index = <2>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman0_tx2-extd-args { + cell-index = <2>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman0_rx3-extd-args { + cell-index = <3>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman0_tx3-extd-args { + cell-index = <3>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman0_rx4-extd-args { + cell-index = <4>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman0_tx4-extd-args { + cell-index = <4>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman0_rx8-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-10g-rx-extended-args"; + fifo-size = <0x7000 0x3000>; + num-dmas = <0x8 0x8>; + num-tnums = <0x10 0x8>; + }; + fman0_tx8-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-10g-tx-extended-args"; + fifo-size = <0x4000 0x0>; + num-dmas = <0x8 0x0>; + num-tnums = <0x10 0x8>; + }; + }; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-sdk.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-sdk.dtsi new file mode 100644 index 00000000000000..41bf8dee7b5ad8 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-sdk.dtsi @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +&fman0 { + compatible = "fsl,fman", "simple-bus"; + + /* tx - 1g - 0 */ + port@a8000 { + fsl,qman-channel-id = <0x41>; + }; + /* tx - 1g - 1 */ + port@a9000 { + fsl,qman-channel-id = <0x42>; + }; + /* tx - 1g - 2 */ + port@aa000 { + fsl,qman-channel-id = <0x43>; + }; + /* tx - 1g - 3 */ + port@ab000 { + fsl,qman-channel-id = <0x44>; + }; + /* tx - 1g - 4 */ + port@ac000 { + fsl,qman-channel-id = <0x45>; + }; + /* tx - 10g - 0 */ + port@b0000 { + fsl,qman-channel-id = <0x40>; + }; + /* offline 0 */ + port@81000 { + fsl,qman-channel-id = <0x46>; + }; + /* offline 1 */ + port@82000 { + fsl,qman-channel-id = <0x47>; + }; + /* offline 2 */ + port@83000 { + fsl,qman-channel-id = <0x48>; + }; + /* offline 3 */ + port@84000 { + fsl,qman-channel-id = <0x49>; + }; + /* offline 4 */ + port@85000 { + fsl,qman-channel-id = <0x4a>; + }; + /* offline 5 */ + port@86000 { + fsl,qman-channel-id = <0x4b>; + }; + + policer@c0000 { + compatible = "fsl,fman-policer"; + reg = <0xc0000 0x1000>; + }; + + keygen@c1000 { + compatible = "fsl,fman-keygen"; + reg = <0xc1000 0x1000>; + }; + + dma@c2000 { + compatible = "fsl,fman-dma"; + reg = <0xc2000 0x1000>; + }; + + fpm@c3000 { + compatible = "fsl,fman-fpm"; + reg = <0xc3000 0x1000>; + }; + + parser@c7000 { + compatible = "fsl,fman-parser"; + reg = <0xc7000 0x1000>; + }; +}; + diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-10g-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-10g-0.dtsi index 83ae87b69d92a2..3e2ef2b104144c 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-10g-0.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-10g-0.dtsi @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x10: port@90000 { cell-index = <0x10>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-10g-rx"; reg = <0x90000 0x1000>; }; fman1_tx_0x30: port@b0000 { cell-index = <0x30>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-10g-tx"; reg = <0xb0000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-0.dtsi index b0f0e36a4eac75..8b41c39af8c178 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-0.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-0.dtsi @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x08: port@88000 { cell-index = <0x8>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x88000 0x1000>; }; fman1_tx_0x28: port@a8000 { cell-index = <0x28>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xa8000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-1.dtsi index a3a79f8552a32b..91dad61ba25c8b 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-1.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-1.dtsi @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x09: port@89000 { cell-index = <0x9>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x89000 0x1000>; }; fman1_tx_0x29: port@a9000 { cell-index = <0x29>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xa9000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-2.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-2.dtsi index 96a69a84b8a8d2..26ed88f2f741ea 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-2.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-2.dtsi @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x0a: port@8a000 { cell-index = <0xa>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x8a000 0x1000>; }; fman1_tx_0x2a: port@aa000 { cell-index = <0x2a>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xaa000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-3.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-3.dtsi index 7405d1940133c0..dd708f3842199c 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-3.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-3.dtsi @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x0b: port@8b000 { cell-index = <0xb>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x8b000 0x1000>; }; fman1_tx_0x2b: port@ab000 { cell-index = <0x2b>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xab000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-4.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-4.dtsi index f49ad69e5212f8..0c6aba079e1c06 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-4.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-4.dtsi @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x0c: port@8c000 { cell-index = <0xc>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x8c000 0x1000>; }; fman1_tx_0x2c: port@ac000 { cell-index = <0x2c>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xac000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-chosen-fifo-resize.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-chosen-fifo-resize.dtsi new file mode 100644 index 00000000000000..90f47c9a299565 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-chosen-fifo-resize.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2018 NXP + */ + +&soc { + chosen { + name = "chosen"; + dpaa-extended-args { + fman1-extd-args { + cell-index = <1>; + compatible = "fsl,fman-extended-args"; + total-fifo-size = <0x27000>; + fman1_oh1-extd-args { + cell-index = <1>; + compatible = "fsl,fman-port-op-extended-args"; + fifo-size = <0x800 0x0>; + num-dmas = <0x1 0x1>; + num-tnums = <0x1 0x4>; + }; + fman1_rx0-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman1_tx0-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman1_rx1-extd-args { + cell-index = <1>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman1_tx1-extd-args { + cell-index = <1>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman1_rx2-extd-args { + cell-index = <2>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman1_tx2-extd-args { + cell-index = <2>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman1_rx3-extd-args { + cell-index = <3>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman1_tx3-extd-args { + cell-index = <3>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman1_rx4-extd-args { + cell-index = <4>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman1_tx4-extd-args { + cell-index = <4>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman1_rx8-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-10g-rx-extended-args"; + fifo-size = <0x7000 0x3000>; + num-dmas = <0x8 0x8>; + num-tnums = <0x10 0x8>; + }; + fman1_tx8-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-10g-tx-extended-args"; + fifo-size = <0x4000 0x0>; + num-dmas = <0x8 0x0>; + num-tnums = <0x10 0x8>; + }; + }; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-sdk.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-sdk.dtsi new file mode 100644 index 00000000000000..cba95e0e5ae641 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-sdk.dtsi @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +&fman1 { + compatible = "fsl,fman", "simple-bus"; + + /* tx - 1g - 0 */ + port@a8000 { + fsl,qman-channel-id = <0x61>; + }; + /* tx - 1g - 1 */ + port@a9000 { + fsl,qman-channel-id = <0x62>; + }; + /* tx - 1g - 2 */ + port@aa000 { + fsl,qman-channel-id = <0x63>; + }; + /* tx - 1g - 3 */ + port@ab000 { + fsl,qman-channel-id = <0x64>; + }; + /* tx - 1g - 4 */ + port@ac000 { + fsl,qman-channel-id = <0x65>; + }; + /* tx - 10g - 0 */ + port@b0000 { + fsl,qman-channel-id = <0x60>; + }; + /* offline 0 */ + port@81000 { + fsl,qman-channel-id = <0x66>; + }; + /* offline 1 */ + port@82000 { + fsl,qman-channel-id = <0x67>; + }; + /* offline 2 */ + port@83000 { + fsl,qman-channel-id = <0x68>; + }; + /* offline 3 */ + port@84000 { + fsl,qman-channel-id = <0x69>; + }; + /* offline 4 */ + port@85000 { + fsl,qman-channel-id = <0x6a>; + }; + /* offline 5 */ + port@86000 { + fsl,qman-channel-id = <0x6b>; + }; + + policer@c0000 { + compatible = "fsl,fman-policer"; + reg = <0xc0000 0x1000>; + }; + + keygen@c1000 { + compatible = "fsl,fman-keygen"; + reg = <0xc1000 0x1000>; + }; + + dma@c2000 { + compatible = "fsl,fman-dma"; + reg = <0xc2000 0x1000>; + }; + + fpm@c3000 { + compatible = "fsl,fman-fpm"; + reg = <0xc3000 0x1000>; + }; + + parser@c7000 { + compatible = "fsl,fman-parser"; + reg = <0xc7000 0x1000>; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi index baa0c503e741b8..8c239cd0f1d831 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi @@ -35,7 +35,7 @@ fman@400000 { fman0_rx_0x08: port@88000 { cell-index = <0x8>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-10g-rx"; reg = <0x88000 0x1000>; fsl,fman-10g-port; fsl,fman-best-effort-port; @@ -43,7 +43,7 @@ fman@400000 { fman0_tx_0x28: port@a8000 { cell-index = <0x28>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-10g-tx"; reg = <0xa8000 0x1000>; fsl,fman-10g-port; fsl,fman-best-effort-port; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi index 93095600e8086f..f310f457339040 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi @@ -35,14 +35,14 @@ fman@400000 { fman0_rx_0x10: port@90000 { cell-index = <0x10>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx"; reg = <0x90000 0x1000>; fsl,fman-10g-port; }; fman0_tx_0x30: port@b0000 { cell-index = <0x30>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx"; reg = <0xb0000 0x1000>; fsl,fman-10g-port; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi index ff4bd38f064599..5b530754631826 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi @@ -35,7 +35,7 @@ fman@400000 { fman0_rx_0x09: port@89000 { cell-index = <0x9>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-10g-rx"; reg = <0x89000 0x1000>; fsl,fman-10g-port; fsl,fman-best-effort-port; @@ -43,7 +43,7 @@ fman@400000 { fman0_tx_0x29: port@a9000 { cell-index = <0x29>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-10g-tx"; reg = <0xa9000 0x1000>; fsl,fman-10g-port; fsl,fman-best-effort-port; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi index 1fa38ed6f59e26..f42856e56f3e15 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi @@ -35,14 +35,14 @@ fman@400000 { fman0_rx_0x11: port@91000 { cell-index = <0x11>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx"; reg = <0x91000 0x1000>; fsl,fman-10g-port; }; fman0_tx_0x31: port@b1000 { cell-index = <0x31>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx"; reg = <0xb1000 0x1000>; fsl,fman-10g-port; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi index a8cc9780c0c422..eab7e908a87b3e 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x08: port@88000 { cell-index = <0x8>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x88000 0x1000>; }; fman0_tx_0x28: port@a8000 { cell-index = <0x28>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xa8000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi index 8b8bd70c93823d..2e37b6c973b170 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x09: port@89000 { cell-index = <0x9>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x89000 0x1000>; }; fman0_tx_0x29: port@a9000 { cell-index = <0x29>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xa9000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi index 619c880b54d8d3..be3e7c8729f769 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x0a: port@8a000 { cell-index = <0xa>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x8a000 0x1000>; }; fman0_tx_0x2a: port@aa000 { cell-index = <0x2a>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xaa000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi index d7ebb73a400d06..5fab79e7b3457a 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x0b: port@8b000 { cell-index = <0xb>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x8b000 0x1000>; }; fman0_tx_0x2b: port@ab000 { cell-index = <0x2b>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xab000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi index b151d696a0699b..7675c7b028fe0a 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x0c: port@8c000 { cell-index = <0xc>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x8c000 0x1000>; }; fman0_tx_0x2c: port@ac000 { cell-index = <0x2c>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xac000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi index adc0ae0013a3ce..dbab7e1349a02b 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x0d: port@8d000 { cell-index = <0xd>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x8d000 0x1000>; }; fman0_tx_0x2d: port@ad000 { cell-index = <0x2d>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xad000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-sdk.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-sdk.dtsi new file mode 100644 index 00000000000000..a21ae92f7d1308 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-sdk.dtsi @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +&fman0 { + compatible = "fsl,fman", "simple-bus"; + + /* tx - 10g - 2 */ + port@a8000 { + fsl,qman-channel-id = <0x802>; + }; + /* tx - 10g - 3 */ + port@a9000 { + fsl,qman-channel-id = <0x803>; + }; + /* tx - 1g - 2 */ + port@aa000 { + fsl,qman-channel-id = <0x804>; + }; + /* tx - 1g - 3 */ + port@ab000 { + fsl,qman-channel-id = <0x805>; + }; + /* tx - 1g - 4 */ + port@ac000 { + fsl,qman-channel-id = <0x806>; + }; + /* tx - 1g - 5 */ + port@ad000 { + fsl,qman-channel-id = <0x807>; + }; + /* tx - 10g - 0 */ + port@b0000 { + fsl,qman-channel-id = <0x800>; + }; + /* tx - 10g - 1 */ + port@b1000 { + fsl,qman-channel-id = <0x801>; + }; + /* offline - 1 */ + port@82000 { + fsl,qman-channel-id = <0x809>; + }; + /* offline - 2 */ + port@83000 { + fsl,qman-channel-id = <0x80a>; + }; + /* offline - 3 */ + port@84000 { + fsl,qman-channel-id = <0x80b>; + }; + /* offline - 4 */ + port@85000 { + fsl,qman-channel-id = <0x80c>; + }; + /* offline - 5 */ + port@86000 { + fsl,qman-channel-id = <0x80d>; + }; + /* offline - 6 */ + port@87000 { + fsl,qman-channel-id = <0x80e>; + }; + + policer@c0000 { + compatible = "fsl,fman-policer"; + reg = <0xc0000 0x1000>; + }; + + keygen@c1000 { + compatible = "fsl,fman-keygen"; + reg = <0xc1000 0x1000>; + }; + + dma@c2000 { + compatible = "fsl,fman-dma"; + reg = <0xc2000 0x1000>; + }; + + fpm@c3000 { + compatible = "fsl,fman-fpm"; + reg = <0xc3000 0x1000>; + }; + + parser@c7000 { + compatible = "fsl,fman-parser"; + reg = <0xc7000 0x1000>; + }; + + vsps@dc000 { + compatible = "fsl,fman-vsps"; + reg = <0xdc000 0x1000>; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi index 435047e0e250e2..58780bb2db135e 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi @@ -35,14 +35,14 @@ fman@500000 { fman1_rx_0x10: port@90000 { cell-index = <0x10>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-10g-rx"; reg = <0x90000 0x1000>; fsl,fman-10g-port; }; fman1_tx_0x30: port@b0000 { cell-index = <0x30>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-10g-tx"; reg = <0xb0000 0x1000>; fsl,fman-10g-port; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi index c098657cca0a7b..0da76c16acf3c3 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi @@ -35,14 +35,14 @@ fman@500000 { fman1_rx_0x11: port@91000 { cell-index = <0x11>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-10g-rx"; reg = <0x91000 0x1000>; fsl,fman-10g-port; }; fman1_tx_0x31: port@b1000 { cell-index = <0x31>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-10g-tx"; reg = <0xb1000 0x1000>; fsl,fman-10g-port; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi index 9d06824815f342..e1d7067b1b581d 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x08: port@88000 { cell-index = <0x8>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x88000 0x1000>; }; fman1_tx_0x28: port@a8000 { cell-index = <0x28>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xa8000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi index 70e947730c4ba7..1db943eae81b26 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x09: port@89000 { cell-index = <0x9>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x89000 0x1000>; }; fman1_tx_0x29: port@a9000 { cell-index = <0x29>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xa9000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi index ad96e652959596..08346b532eba9b 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x0a: port@8a000 { cell-index = <0xa>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x8a000 0x1000>; }; fman1_tx_0x2a: port@aa000 { cell-index = <0x2a>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xaa000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi index 034bc4b71f7a50..11ee2e9660839a 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x0b: port@8b000 { cell-index = <0xb>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x8b000 0x1000>; }; fman1_tx_0x2b: port@ab000 { cell-index = <0x2b>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xab000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi index 93ca23d82b39ba..ad6cc1636f8506 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x0c: port@8c000 { cell-index = <0xc>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x8c000 0x1000>; }; fman1_tx_0x2c: port@ac000 { cell-index = <0x2c>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xac000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi index 23b3117a2fd2a3..f64a6c47b99b61 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x0d: port@8d000 { cell-index = <0xd>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x8d000 0x1000>; }; fman1_tx_0x2d: port@ad000 { cell-index = <0x2d>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xad000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-sdk.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-sdk.dtsi new file mode 100644 index 00000000000000..397017ac910a4c --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-sdk.dtsi @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +&fman1 { + compatible = "fsl,fman", "simple-bus"; + + /* tx - 1g - 0 */ + port@a8000 { + fsl,qman-channel-id = <0x822>; + }; + /* tx - 1g - 1 */ + port@a9000 { + fsl,qman-channel-id = <0x823>; + }; + /* tx - 1g - 2 */ + port@aa000 { + fsl,qman-channel-id = <0x824>; + }; + /* tx - 1g - 3 */ + port@ab000 { + fsl,qman-channel-id = <0x825>; + }; + /* tx - 1g - 4 */ + port@ac000 { + fsl,qman-channel-id = <0x826>; + }; + /* tx - 1g - 5 */ + port@ad000 { + fsl,qman-channel-id = <0x827>; + }; + /* tx - 10g - 0 */ + port@b0000 { + fsl,qman-channel-id = <0x820>; + }; + /* tx - 10g - 1 */ + port@b1000 { + fsl,qman-channel-id = <0x821>; + }; + /* offline - 1 */ + port@82000 { + fsl,qman-channel-id = <0x829>; + }; + /* offline - 2 */ + port@83000 { + fsl,qman-channel-id = <0x82a>; + }; + /* offline - 3 */ + port@84000 { + fsl,qman-channel-id = <0x82b>; + }; + /* offline - 4 */ + port@85000 { + fsl,qman-channel-id = <0x82c>; + }; + /* offline - 5 */ + port@86000 { + fsl,qman-channel-id = <0x82d>; + }; + /* offline - 6 */ + port@87000 { + fsl,qman-channel-id = <0x82e>; + }; + + policer@c0000 { + compatible = "fsl,fman-policer"; + reg = <0xc0000 0x1000>; + }; + + keygen@c1000 { + compatible = "fsl,fman-keygen"; + reg = <0xc1000 0x1000>; + }; + + dma@c2000 { + compatible = "fsl,fman-dma"; + reg = <0xc2000 0x1000>; + }; + + fpm@c3000 { + compatible = "fsl,fman-fpm"; + reg = <0xc3000 0x1000>; + }; + + parser@c7000 { + compatible = "fsl,fman-parser"; + reg = <0xc7000 0x1000>; + }; + + vsps@dc000 { + compatible = "fsl,fman-vsps"; + reg = <0xdc000 0x1000>; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-qman1-portals-sdk.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-qman1-portals-sdk.dtsi new file mode 100644 index 00000000000000..91266d19fbe2b3 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-qman1-portals-sdk.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +&qportals { + qman-fqids@0 { + compatible = "fsl,fqid-range"; + fsl,fqid-range = <256 256>; + }; + qman-fqids@1 { + compatible = "fsl,fqid-range"; + fsl,fqid-range = <32768 32768>; + }; + qman-pools@0 { + compatible = "fsl,pool-channel-range"; + fsl,pool-channel-range = <0x21 0xf>; + }; + qman-cgrids@0 { + compatible = "fsl,cgrid-range"; + fsl,cgrid-range = <0 256>; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm0-32-sdk.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm0-32-sdk.dtsi new file mode 100644 index 00000000000000..a6205b1a4929d2 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm0-32-sdk.dtsi @@ -0,0 +1,42 @@ +/* + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2017 - 2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +&qportals { + qman-ceetm@0 { + compatible = "fsl,qman-ceetm"; + fsl,ceetm-lfqid-range = <0xf00000 0x1000>; + fsl,ceetm-sp-range = <0 16>; + fsl,ceetm-lni-range = <0 8>; + fsl,ceetm-channel-range = <0 32>; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm0-8-sdk.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm0-8-sdk.dtsi new file mode 100644 index 00000000000000..779ab5ebb80547 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm0-8-sdk.dtsi @@ -0,0 +1,42 @@ +/* + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2017 - 2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +&qportals { + qman-ceetm@0 { + compatible = "fsl,qman-ceetm"; + fsl,ceetm-lfqid-range = <0xf00000 0x1000>; + fsl,ceetm-sp-range = <0 16>; + fsl,ceetm-lni-range = <0 8>; + fsl,ceetm-channel-range = <0 8>; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm1-32-sdk.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm1-32-sdk.dtsi new file mode 100644 index 00000000000000..2c75f4d168ae38 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm1-32-sdk.dtsi @@ -0,0 +1,42 @@ +/* + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2017 - 2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +&qportals { + qman-ceetm@1 { + compatible = "fsl,qman-ceetm"; + fsl,ceetm-lfqid-range = <0xf10000 0x1000>; + fsl,ceetm-sp-range = <0 16>; + fsl,ceetm-lni-range = <0 8>; + fsl,ceetm-channel-range = <0 32>; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-qman3-portals-sdk.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-qman3-portals-sdk.dtsi new file mode 100644 index 00000000000000..d8cb5390a305ed --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-qman3-portals-sdk.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +&qportals { + qman-fqids@0 { + compatible = "fsl,fqid-range"; + fsl,fqid-range = <256 512>; + }; + qman-fqids@1 { + compatible = "fsl,fqid-range"; + fsl,fqid-range = <32768 32768>; + }; + qman-pools@0 { + compatible = "fsl,pool-channel-range"; + fsl,pool-channel-range = <0x401 0xf>; + }; + qman-cgrids@0 { + compatible = "fsl,cgrid-range"; + fsl,cgrid-range = <0 256>; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/t1023rdb-sdk.dts b/arch/powerpc/boot/dts/fsl/t1023rdb-sdk.dts new file mode 100644 index 00000000000000..6a88f1e1f61e55 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t1023rdb-sdk.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t1023rdb.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-8-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/t1023rdb.dts b/arch/powerpc/boot/dts/fsl/t1023rdb.dts index 5ba6fbfca2742b..a7affbe0f789fa 100644 --- a/arch/powerpc/boot/dts/fsl/t1023rdb.dts +++ b/arch/powerpc/boot/dts/fsl/t1023rdb.dts @@ -142,23 +142,23 @@ }; fman@400000 { - fm1mac1: ethernet@e0000 { + enet0: ethernet@e0000 { phy-handle = <&sgmii_rtk_phy2>; phy-connection-type = "sgmii"; sleep = <&rcpm 0x80000000>; }; - fm1mac2: ethernet@e2000 { + enet1: ethernet@e2000 { sleep = <&rcpm 0x40000000>; }; - fm1mac3: ethernet@e4000 { + enet2: ethernet@e4000 { phy-handle = <&sgmii_aqr_phy3>; phy-connection-type = "sgmii-2500"; sleep = <&rcpm 0x20000000>; }; - fm1mac4: ethernet@e6000 { + enet3: ethernet@e6000 { phy-handle = <&rgmii_rtk_phy1>; phy-connection-type = "rgmii"; sleep = <&rcpm 0x10000000>; diff --git a/arch/powerpc/boot/dts/fsl/t1024qds-sdk.dts b/arch/powerpc/boot/dts/fsl/t1024qds-sdk.dts new file mode 100644 index 00000000000000..a1b812d763fcda --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t1024qds-sdk.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t1024qds.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-8-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "fsl,ls1043a-dpaa", "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/t1024rdb-sdk.dts b/arch/powerpc/boot/dts/fsl/t1024rdb-sdk.dts new file mode 100644 index 00000000000000..a49b97dbf2a4af --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t1024rdb-sdk.dts @@ -0,0 +1,28 @@ +#include "t1024rdb.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-8-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/t1024rdb.dts b/arch/powerpc/boot/dts/fsl/t1024rdb.dts index 73a645324bc17b..645caff98ed1fe 100644 --- a/arch/powerpc/boot/dts/fsl/t1024rdb.dts +++ b/arch/powerpc/boot/dts/fsl/t1024rdb.dts @@ -91,7 +91,7 @@ board-control@2,0 { #address-cells = <1>; #size-cells = <1>; - compatible = "fsl,t1024-cpld"; + compatible = "fsl,t1024-cpld", "fsl,deepsleep-cpld"; reg = <3 0 0x300>; ranges = <0 3 0 0x300>; bank-width = <1>; @@ -175,23 +175,23 @@ }; fman@400000 { - fm1mac1: ethernet@e0000 { + enet0: ethernet@e0000 { phy-handle = <&xg_aqr105_phy3>; phy-connection-type = "xgmii"; sleep = <&rcpm 0x80000000>; }; - fm1mac2: ethernet@e2000 { + enet1: ethernet@e2000 { sleep = <&rcpm 0x40000000>; }; - fm1mac3: ethernet@e4000 { + enet2: ethernet@e4000 { phy-handle = <&rgmii_phy2>; phy-connection-type = "rgmii"; sleep = <&rcpm 0x20000000>; }; - fm1mac4: ethernet@e6000 { + enet3: ethernet@e6000 { phy-handle = <&rgmii_phy1>; phy-connection-type = "rgmii"; sleep = <&rcpm 0x10000000>; diff --git a/arch/powerpc/boot/dts/fsl/t1040d4rdb-sdk.dts b/arch/powerpc/boot/dts/fsl/t1040d4rdb-sdk.dts new file mode 100644 index 00000000000000..97439ff5ae32bc --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t1040d4rdb-sdk.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t1040d4rdb.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-8-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/t1040qds-sdk.dts b/arch/powerpc/boot/dts/fsl/t1040qds-sdk.dts new file mode 100644 index 00000000000000..c316c9b56de6f3 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t1040qds-sdk.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t1040qds.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-8-sdk.dtsi" diff --git a/arch/powerpc/boot/dts/fsl/t1040rdb-sdk.dts b/arch/powerpc/boot/dts/fsl/t1040rdb-sdk.dts new file mode 100644 index 00000000000000..ef1e80bcf484a7 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t1040rdb-sdk.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t1040rdb.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-8-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/t1040rdb.dts b/arch/powerpc/boot/dts/fsl/t1040rdb.dts index 65ff34c4902569..825665c470e40e 100644 --- a/arch/powerpc/boot/dts/fsl/t1040rdb.dts +++ b/arch/powerpc/boot/dts/fsl/t1040rdb.dts @@ -70,7 +70,7 @@ ifc: localbus@ffe124000 { cpld@3,0 { - compatible = "fsl,t1040rdb-cpld"; + compatible = "fsl,t104xrdb-cpld", "fsl,deepsleep-cpld"; }; }; }; diff --git a/arch/powerpc/boot/dts/fsl/t1042d4rdb-sdk.dts b/arch/powerpc/boot/dts/fsl/t1042d4rdb-sdk.dts new file mode 100644 index 00000000000000..6c3d636b5a3a87 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t1042d4rdb-sdk.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t1042d4rdb.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-8-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/t1042qds-sdk.dts b/arch/powerpc/boot/dts/fsl/t1042qds-sdk.dts new file mode 100644 index 00000000000000..e9c68d063fe807 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t1042qds-sdk.dts @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t1042qds.dts" diff --git a/arch/powerpc/boot/dts/fsl/t1042rdb-sdk.dts b/arch/powerpc/boot/dts/fsl/t1042rdb-sdk.dts new file mode 100644 index 00000000000000..38f7032441b5f2 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t1042rdb-sdk.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t1042rdb.dts" + + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-8-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/t1042rdb.dts b/arch/powerpc/boot/dts/fsl/t1042rdb.dts index 3ebb712224cbe0..099764322b33cc 100644 --- a/arch/powerpc/boot/dts/fsl/t1042rdb.dts +++ b/arch/powerpc/boot/dts/fsl/t1042rdb.dts @@ -68,7 +68,7 @@ ifc: localbus@ffe124000 { cpld@3,0 { - compatible = "fsl,t1042rdb-cpld"; + compatible = "fsl,t104xrdb-cpld", "fsl,deepsleep-cpld"; }; }; }; diff --git a/arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts b/arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts index 8ec3ff45e6fc70..b10cab1a347bfe 100644 --- a/arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts +++ b/arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts @@ -41,7 +41,7 @@ ifc: localbus@ffe124000 { cpld@3,0 { - compatible = "fsl,t1042rdb_pi-cpld"; + compatible = "fsl,t104xrdb-cpld", "fsl,deepsleep-cpld"; }; }; diff --git a/arch/powerpc/boot/dts/fsl/t2080qds-sdk.dts b/arch/powerpc/boot/dts/fsl/t2080qds-sdk.dts new file mode 100644 index 00000000000000..898ea467b56aea --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t2080qds-sdk.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t2080qds.dts" + +/include/ "qoriq-fman-0-sdk.dtsi" +/include/ "qoriq-dpaa-eth.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-32-sdk.dtsi" diff --git a/arch/powerpc/boot/dts/fsl/t2080rdb-sdk.dts b/arch/powerpc/boot/dts/fsl/t2080rdb-sdk.dts new file mode 100644 index 00000000000000..b3a5d7526c200e --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t2080rdb-sdk.dts @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t2080rdb.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-32-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + ethernet@5 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet5>; + }; + ethernet@6 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet6>; + }; + ethernet@7 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet7>; + }; + }; +}; + +&bportals { + bman-portal@28000 { + cell-index = <0xa>; + }; + + bman-portal@2c000 { + cell-index = <0xb>; + }; + + bman-portal@30000 { + cell-index = <0xc>; + }; + + bman-portal@34000 { + cell-index = <0xd>; + }; + + bman-portal@38000 { + cell-index = <0xe>; + }; + + bman-portal@3c000 { + cell-index = <0xf>; + }; + + bman-portal@40000 { + cell-index = <0x10>; + }; + + bman-portal@44000 { + cell-index = <0x11>; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/t2081qds-sdk.dts b/arch/powerpc/boot/dts/fsl/t2081qds-sdk.dts new file mode 100644 index 00000000000000..2dcec8a5939ba5 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t2081qds-sdk.dts @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "t2081qds.dts" diff --git a/arch/powerpc/boot/dts/fsl/t4240qds-sdk.dts b/arch/powerpc/boot/dts/fsl/t4240qds-sdk.dts new file mode 100644 index 00000000000000..db27e43751ee00 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t4240qds-sdk.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "t4240qds.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-dpaa-eth.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-32-sdk.dtsi" diff --git a/arch/powerpc/boot/dts/fsl/t4240rdb-sdk.dts b/arch/powerpc/boot/dts/fsl/t4240rdb-sdk.dts new file mode 100644 index 00000000000000..4698f916330f8d --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t4240rdb-sdk.dts @@ -0,0 +1,249 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "t4240rdb.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-fman3-1-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-32-sdk.dtsi" +/include/ "qoriq-qman3-ceetm1-32-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + status = "disabled"; + }; + ethernet@5 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet5>; + status = "disabled"; + }; + ethernet@6 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet6>; + }; + ethernet@7 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet7>; + }; + ethernet@8 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet8>; + }; + ethernet@9 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet9>; + }; + ethernet@10 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet10>; + }; + ethernet@11 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet11>; + }; + ethernet@12 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet12>; + status = "disabled"; + }; + ethernet@13 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet13>; + status = "disabled"; + }; + ethernet@14 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet14>; + }; + ethernet@15 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet15>; + }; + }; +}; + +&bportals { + bman-portal@28000 { + cell-index = <0xa>; + }; + + bman-portal@2c000 { + cell-index = <0xb>; + }; + + bman-portal@30000 { + cell-index = <0xc>; + }; + + bman-portal@34000 { + cell-index = <0xd>; + }; + + bman-portal@38000 { + cell-index = <0xe>; + }; + + bman-portal@3c000 { + cell-index = <0xf>; + }; + + bman-portal@40000 { + cell-index = <0x10>; + }; + + bman-portal@44000 { + cell-index = <0x11>; + }; + + bman-portal@48000 { + cell-index = <0x12>; + }; + + bman-portal@4c000 { + cell-index = <0x13>; + }; + + bman-portal@50000 { + cell-index = <0x14>; + }; + + bman-portal@54000 { + cell-index = <0x15>; + }; + + bman-portal@58000 { + cell-index = <0x16>; + }; + + bman-portal@5c000 { + cell-index = <0x17>; + }; + + bman-portal@60000 { + cell-index = <0x18>; + }; + + bman-portal@64000 { + cell-index = <0x19>; + }; + + bman-portal@68000 { + cell-index = <0x1a>; + }; + + bman-portal@6c000 { + cell-index = <0x1b>; + }; + + bman-portal@70000 { + cell-index = <0x1c>; + }; + + bman-portal@74000 { + cell-index = <0x1d>; + }; + + bman-portal@78000 { + cell-index = <0x1e>; + }; + + bman-portal@7c000 { + cell-index = <0x1f>; + }; + + bman-portal@80000 { + cell-index = <0x20>; + }; + + bman-portal@84000 { + cell-index = <0x21>; + }; + + bman-portal@88000 { + cell-index = <0x22>; + }; + + bman-portal@8c000 { + cell-index = <0x23>; + }; + + bman-portal@90000 { + cell-index = <0x24>; + }; + + bman-portal@94000 { + cell-index = <0x25>; + }; + + bman-portal@98000 { + cell-index = <0x26>; + }; + + bman-portal@9c000 { + cell-index = <0x27>; + }; + + bman-portal@a0000 { + cell-index = <0x28>; + }; + + bman-portal@a4000 { + cell-index = <0x29>; + }; + + bman-portal@a8000 { + cell-index = <0x2a>; + }; + + bman-portal@ac000 { + cell-index = <0x2b>; + }; + + bman-portal@b0000 { + cell-index = <0x2c>; + }; + + bman-portal@b4000 { + cell-index = <0x2d>; + }; + + bman-portal@b8000 { + cell-index = <0x2e>; + }; + + bman-portal@bc000 { + cell-index = <0x2f>; + }; + + bman-portal@c0000 { + cell-index = <0x30>; + }; + + bman-portal@c4000 { + cell-index = <0x31>; + }; +}; diff --git a/arch/powerpc/configs/85xx/p1023_sdk_defconfig b/arch/powerpc/configs/85xx/p1023_sdk_defconfig new file mode 100644 index 00000000000000..64b304bc269dee --- /dev/null +++ b/arch/powerpc/configs/85xx/p1023_sdk_defconfig @@ -0,0 +1,200 @@ +CONFIG_PPC_85xx=y +CONFIG_SMP=y +CONFIG_NR_CPUS=2 +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_AUDIT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_RCU_FANOUT=32 +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PARTITION_ADVANCED=y +CONFIG_MAC_PARTITION=y +CONFIG_PHYSICAL_START=0x00000000 +CONFIG_P1023_RDB=y +CONFIG_P1023_RDS=y +# CONFIG_QUICC_ENGINE is not set +# CONFIG_CPM is not set +# CONFIG_CPM2 is not set +# CONFIG_QE_GPIO is not set +CONFIG_CPM2=y +CONFIG_HIGHMEM=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_MISC=m +CONFIG_MATH_EMULATION=y +CONFIG_SWIOTLB=y +CONFIG_PCI=y +CONFIG_PCIEPORTBUS=y +# CONFIG_PCIEAER is not set +# CONFIG_PCIEASPM is not set +CONFIG_PCI_MSI=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=y +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_ARPD=y +CONFIG_INET_ESP=y +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_IPV6=y +CONFIG_IP_SCTP=m +CONFIG_VLAN_8021Q=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_FSL_ELBC=y +CONFIG_PROC_DEVICETREE=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=131072 +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_LEGACY=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=y +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_LOGGING=y +CONFIG_ATA=y +CONFIG_SATA_FSL=y +CONFIG_SATA_SIL24=y +CONFIG_NETDEVICES=y +CONFIG_DUMMY=y +CONFIG_HAS_FSL_QBMAN=y +CONFIG_FS_ENET=y +CONFIG_FSL_PQ_MDIO=y +CONFIG_FMAN_P1023=y +CONFIG_FSL_DPAA_ETH=y +CONFIG_E1000E=y +CONFIG_ATHEROS_PHY=y +CONFIG_PHYLIB=y +CONFIG_AT803X_PHY=y +CONFIG_MARVELL_PHY=y +CONFIG_DAVICOM_PHY=y +CONFIG_CICADA_PHY=y +CONFIG_VITESSE_PHY=y +CONFIG_FIXED_PHY=y +CONFIG_INPUT_FF_MEMLESS=m +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DETECT_IRQ=y +CONFIG_SERIAL_8250_RSA=y +CONFIG_HW_RANDOM=y +CONFIG_NVRAM=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_CPM=m +CONFIG_I2C_MPC=y +CONFIG_GPIO_MPC8XXX=y +# CONFIG_HWMON is not set +CONFIG_VIDEO_OUTPUT_CONTROL=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +# CONFIG_SND_SUPPORT_OLD_API is not set +CONFIG_USB=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_MON=y +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_STORAGE=y +CONFIG_EDAC=y +CONFIG_EDAC_MM_EDAC=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_CMOS=y +CONFIG_DMADEVICES=y +CONFIG_FSL_DMA=y +# CONFIG_NET_DMA is not set +CONFIG_STAGING=y +CONFIG_MEMORY=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_NTFS_FS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_ADFS_FS=m +CONFIG_AFFS_FS=m +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_BEFS_FS=m +CONFIG_BFS_FS=m +CONFIG_EFS_FS=m +CONFIG_CRAMFS=y +CONFIG_VXFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +CONFIG_NFS_FS=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=y +CONFIG_CRC_T10DIF=y +CONFIG_FRAME_WARN=8092 +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +CONFIG_STRICT_DEVMEM=y +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DEV_FSL_CAAM=y diff --git a/arch/powerpc/configs/fmanv3h.config b/arch/powerpc/configs/fmanv3h.config new file mode 100644 index 00000000000000..9d6bdd12988c42 --- /dev/null +++ b/arch/powerpc/configs/fmanv3h.config @@ -0,0 +1 @@ +CONFIG_FMAN_V3H=y diff --git a/arch/powerpc/configs/fmanv3l.config b/arch/powerpc/configs/fmanv3l.config new file mode 100644 index 00000000000000..60f56f939c4e36 --- /dev/null +++ b/arch/powerpc/configs/fmanv3l.config @@ -0,0 +1 @@ +CONFIG_FMAN_V3L=y diff --git a/arch/powerpc/configs/sdk_dpaa.config b/arch/powerpc/configs/sdk_dpaa.config new file mode 100644 index 00000000000000..78db185b6ca129 --- /dev/null +++ b/arch/powerpc/configs/sdk_dpaa.config @@ -0,0 +1,7 @@ +CONFIG_STAGING=y +CONFIG_FSL_SDK_BMAN=y +CONFIG_FSL_SDK_QMAN=y +CONFIG_FSL_SDK_DPA=y +CONFIG_FSL_SDK_FMAN=y +CONFIG_FSL_SDK_DPAA_ETH=y +CONFIG_CORTINA_PHY=y diff --git a/arch/powerpc/include/asm/cacheflush.h b/arch/powerpc/include/asm/cacheflush.h index 4a1c9f0200e1bf..17502bb520c457 100644 --- a/arch/powerpc/include/asm/cacheflush.h +++ b/arch/powerpc/include/asm/cacheflush.h @@ -42,7 +42,14 @@ extern void flush_dcache_page(struct page *page); #define flush_dcache_mmap_lock(mapping) do { } while (0) #define flush_dcache_mmap_unlock(mapping) do { } while (0) -void flush_icache_range(unsigned long start, unsigned long stop); +extern void __flush_disable_L1(void); +#ifdef CONFIG_FSL_SOC_BOOKE +extern void flush_dcache_L1(void); +#else +#define flush_dcache_L1() do { } while (0) +#endif + +extern void flush_icache_range(unsigned long, unsigned long); extern void flush_icache_user_range(struct vm_area_struct *vma, struct page *page, unsigned long addr, int len); diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index cf00ff0d121def..3cbd71daf1ec27 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h @@ -43,6 +43,14 @@ extern int machine_check_e500mc(struct pt_regs *regs); extern int machine_check_e500(struct pt_regs *regs); extern int machine_check_e200(struct pt_regs *regs); extern int machine_check_47x(struct pt_regs *regs); + +#if defined(CONFIG_E500) || defined(CONFIG_PPC_E500MC) +extern void __flush_caches_e500v2(void); +extern void __flush_caches_e500mc(void); +extern void __flush_caches_e5500(void); +extern void __flush_caches_e6500(void); +#endif + int machine_check_8xx(struct pt_regs *regs); int machine_check_83xx(struct pt_regs *regs); @@ -70,6 +78,10 @@ struct cpu_spec { /* flush caches inside the current cpu */ void (*cpu_down_flush)(void); +#if defined(CONFIG_E500) || defined(CONFIG_PPC_E500MC) + /* flush caches of the cpu which is running the function */ + void (*cpu_flush_caches)(void); +#endif /* number of performance monitor counters */ unsigned int num_pmcs; enum powerpc_pmc_type pmc_type; diff --git a/arch/powerpc/include/asm/fsl_pm.h b/arch/powerpc/include/asm/fsl_pm.h index 61a4c977320f63..07bc1050196993 100644 --- a/arch/powerpc/include/asm/fsl_pm.h +++ b/arch/powerpc/include/asm/fsl_pm.h @@ -7,6 +7,9 @@ #ifndef __PPC_FSL_PM_H #define __PPC_FSL_PM_H +#ifndef __ASSEMBLY__ +#include + #define E500_PM_PH10 1 #define E500_PM_PH15 2 #define E500_PM_PH20 3 @@ -42,6 +45,34 @@ struct fsl_pm_ops { extern const struct fsl_pm_ops *qoriq_pm_ops; +struct fsm_reg_vals { + u32 offset; + u32 value; +}; + +void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val); +void fsl_epu_setup_default(void __iomem *epu_base); +void fsl_npc_setup_default(void __iomem *npc_base); +void fsl_fsm_clean(void __iomem *base, struct fsm_reg_vals *val); +void fsl_epu_clean_default(void __iomem *epu_base); + +extern int fsl_dp_iomap(void); +extern void fsl_dp_iounmap(void); + +extern int fsl_enter_epu_deepsleep(void); +extern void fsl_dp_enter_low(void __iomem *ccsr_base, void __iomem *dcsr_base, + void __iomem *pld_base, int pld_flag); +extern void fsl_booke_deep_sleep_resume(void); + int __init fsl_rcpm_init(void); +void set_pm_suspend_state(suspend_state_t state); +suspend_state_t pm_suspend_state(void); + +void fsl_set_power_except(struct device *dev, int on); +#endif /* __ASSEMBLY__ */ + +#define T1040QDS_TETRA_FLAG 1 +#define T104xRDB_CPLD_FLAG 2 + #endif /* __PPC_FSL_PM_H */ diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile index dc0780f930d5b7..021a5b0a9123b4 100644 --- a/arch/powerpc/kernel/Makefile +++ b/arch/powerpc/kernel/Makefile @@ -78,6 +78,7 @@ obj-$(CONFIG_CRASH_DUMP) += crash_dump.o ifneq ($(CONFIG_FA_DUMP)$(CONFIG_PRESERVE_FA_DUMP),) obj-y += fadump.o endif +obj-$(CONFIG_FSL_SOC) += fsl_pm.o ifdef CONFIG_PPC32 obj-$(CONFIG_E500) += idle_e500.o endif diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c index 5c0a1e17219b75..58c9da1f70d17e 100644 --- a/arch/powerpc/kernel/asm-offsets.c +++ b/arch/powerpc/kernel/asm-offsets.c @@ -365,6 +365,9 @@ int main(void) OFFSET(CPU_SPEC_FEATURES, cpu_spec, cpu_features); OFFSET(CPU_SPEC_SETUP, cpu_spec, cpu_setup); OFFSET(CPU_SPEC_RESTORE, cpu_spec, cpu_restore); +#if defined(CONFIG_E500) || defined(CONFIG_PPC_E500MC) + OFFSET(CPU_FLUSH_CACHES, cpu_spec, cpu_flush_caches); +#endif OFFSET(pbe_address, pbe, address); OFFSET(pbe_orig_address, pbe, orig_address); diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S index 2b4f3ec0acf7d9..1b543b5fed59b2 100644 --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S @@ -340,3 +340,84 @@ _GLOBAL(cpu_down_flush_e5500) /* L1 Data Cache of e6500 contains no modified data, no flush is required */ _GLOBAL(cpu_down_flush_e6500) blr + +_GLOBAL(__flush_caches_e500v2) + mflr r0 + bl flush_dcache_L1 + mtlr r0 + blr + +_GLOBAL(__flush_caches_e500mc) +_GLOBAL(__flush_caches_e5500) + mflr r0 + bl flush_dcache_L1 + bl flush_backside_L2_cache + mtlr r0 + blr + +/* L1 Data Cache of e6500 contains no modified data, no flush is required */ +_GLOBAL(__flush_caches_e6500) + blr + + /* r3 = virtual address of L2 controller, WIMG = 01xx */ +_GLOBAL(flush_disable_L2) + /* It's a write-through cache, so only invalidation is needed. */ + mbar + isync + lwz r4, 0(r3) + li r5, 1 + rlwimi r4, r5, 30, 0xc0000000 + stw r4, 0(r3) + + /* Wait for the invalidate to finish */ +1: lwz r4, 0(r3) + andis. r4, r4, 0x4000 + bne 1b + mbar + + blr + + /* r3 = virtual address of L2 controller, WIMG = 01xx */ +_GLOBAL(invalidate_enable_L2) + mbar + isync + lwz r4, 0(r3) + li r5, 3 + rlwimi r4, r5, 30, 0xc0000000 + stw r4, 0(r3) + + /* Wait for the invalidate to finish */ +1: lwz r4, 0(r3) + andis. r4, r4, 0x4000 + bne 1b + mbar + + blr + +/* Flush L1 d-cache, invalidate and disable d-cache and i-cache */ +_GLOBAL(__flush_disable_L1) + mflr r10 + bl flush_dcache_L1 /* Flush L1 d-cache */ + mtlr r10 + + mfspr r4, SPRN_L1CSR0 /* Invalidate and disable d-cache */ + li r5, 2 + rlwimi r4, r5, 0, 3 + + msync + isync + mtspr SPRN_L1CSR0, r4 + isync + +1: mfspr r4, SPRN_L1CSR0 /* Wait for the invalidate to finish */ + andi. r4, r4, 2 + bne 1b + + mfspr r4, SPRN_L1CSR1 /* Invalidate and disable i-cache */ + li r5, 2 + rlwimi r4, r5, 0, 3 + + mtspr SPRN_L1CSR1, r4 + isync + + blr diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index 245be4fafe134a..a099347404db44 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -2051,6 +2051,7 @@ static struct cpu_spec __initdata cpu_specs[] = { .machine_check = machine_check_e500, .platform = "ppc8548", .cpu_down_flush = cpu_down_flush_e500v2, + .cpu_flush_caches = __flush_caches_e500v2, }, #else { /* e500mc */ @@ -2071,6 +2072,7 @@ static struct cpu_spec __initdata cpu_specs[] = { .machine_check = machine_check_e500mc, .platform = "ppce500mc", .cpu_down_flush = cpu_down_flush_e500mc, + .cpu_flush_caches = __flush_caches_e500mc, }, #endif /* CONFIG_PPC_E500MC */ #endif /* CONFIG_PPC32 */ @@ -2096,6 +2098,7 @@ static struct cpu_spec __initdata cpu_specs[] = { .machine_check = machine_check_e500mc, .platform = "ppce5500", .cpu_down_flush = cpu_down_flush_e5500, + .cpu_flush_caches = __flush_caches_e5500, }, { /* e6500 */ .pvr_mask = 0xffff0000, @@ -2119,6 +2122,7 @@ static struct cpu_spec __initdata cpu_specs[] = { .machine_check = machine_check_e500mc, .platform = "ppce6500", .cpu_down_flush = cpu_down_flush_e6500, + .cpu_flush_caches = __flush_caches_e6500, }, #endif /* CONFIG_PPC_E500MC */ #ifdef CONFIG_PPC32 diff --git a/arch/powerpc/kernel/fsl_booke_entry_mapping.S b/arch/powerpc/kernel/fsl_booke_entry_mapping.S index ea065282b3035a..0e3484d3b66323 100644 --- a/arch/powerpc/kernel/fsl_booke_entry_mapping.S +++ b/arch/powerpc/kernel/fsl_booke_entry_mapping.S @@ -174,6 +174,10 @@ skpinv: addi r6,r6,1 /* Increment */ lis r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_NEEDED)@h ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_NEEDED)@l mtspr SPRN_MAS2,r6 +#ifdef ENTRY_DEEPSLEEP_SETUP + LOAD_REG_IMMEDIATE(r8, MEMORY_START) + ori r8,r8,(MAS3_SX|MAS3_SW|MAS3_SR) +#endif mtspr SPRN_MAS3,r8 tlbwe @@ -216,12 +220,18 @@ next_tlb_setup: #error You need to specify the mapping or not use this at all. #endif +#ifdef ENTRY_DEEPSLEEP_SETUP + LOAD_REG_ADDR(r6, 2f) + mfmsr r7 + rlwinm r7,r7,0,~(MSR_IS|MSR_DS) +#else lis r7,MSR_KERNEL@h ori r7,r7,MSR_KERNEL@l bl 1f /* Find our address */ 1: mflr r9 rlwimi r6,r9,0,20,31 addi r6,r6,(2f - 1b) +#endif mtspr SPRN_SRR0,r6 mtspr SPRN_SRR1,r7 rfi /* start execution out of TLB1[0] entry */ diff --git a/arch/powerpc/kernel/fsl_pm.c b/arch/powerpc/kernel/fsl_pm.c new file mode 100644 index 00000000000000..24a179fd878467 --- /dev/null +++ b/arch/powerpc/kernel/fsl_pm.c @@ -0,0 +1,49 @@ +/* + * Freescale General Power Management Implementation + * + * Copyright 2018 NXP + * Author: Wang Dongsheng + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +static suspend_state_t pm_state; + +void set_pm_suspend_state(suspend_state_t state) +{ + pm_state = state; +} + +suspend_state_t pm_suspend_state(void) +{ + return pm_state; +} diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S index 780f527eabd2c4..53aa8f23e09fd3 100644 --- a/arch/powerpc/kernel/head_64.S +++ b/arch/powerpc/kernel/head_64.S @@ -860,7 +860,7 @@ _GLOBAL(start_secondary_resume) /* * This subroutine clobbers r11 and r12 */ -enable_64b_mode: +_GLOBAL(enable_64b_mode) mfmsr r11 /* grab the current MSR */ #ifdef CONFIG_PPC_BOOK3E oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h index c750ac9ec7130e..3b520aa5523e5c 100644 --- a/arch/powerpc/mm/mmu_decl.h +++ b/arch/powerpc/mm/mmu_decl.h @@ -89,6 +89,12 @@ void print_system_hash_info(void); #endif /* CONFIG_PPC_MMU_NOHASH */ +void settlbcam(int index, unsigned long virt, phys_addr_t phys, + unsigned long size, unsigned long flags, unsigned int pid); + +void cleartlbcam(unsigned long virt, unsigned int pid); + + #ifdef CONFIG_PPC32 void hash_preload(struct mm_struct *mm, unsigned long ea); diff --git a/arch/powerpc/mm/nohash/fsl_booke.c b/arch/powerpc/mm/nohash/fsl_booke.c index 556e3cd52a35f4..e454a69ce6bcad 100644 --- a/arch/powerpc/mm/nohash/fsl_booke.c +++ b/arch/powerpc/mm/nohash/fsl_booke.c @@ -102,7 +102,7 @@ unsigned long p_block_mapped(phys_addr_t pa) * an unsigned long (for example, 32-bit implementations cannot support a 4GB * size). */ -static void settlbcam(int index, unsigned long virt, phys_addr_t phys, +void settlbcam(int index, unsigned long virt, phys_addr_t phys, unsigned long size, unsigned long flags, unsigned int pid) { unsigned int tsize; @@ -140,6 +140,18 @@ static void settlbcam(int index, unsigned long virt, phys_addr_t phys, tlbcam_addrs[index].phys = phys; } +void cleartlbcam(unsigned long virt, unsigned int pid) +{ + int i = 0; + for (i = 0; i < NUM_TLBCAMS; i++) { + if (tlbcam_addrs[i].start == virt) { + TLBCAM[i].MAS1 = 0; + loadcam_entry(i); + return; + } + } +} + unsigned long calc_cam_sz(unsigned long ram, unsigned long virt, phys_addr_t phys) { diff --git a/arch/powerpc/platforms/83xx/km83xx.c b/arch/powerpc/platforms/83xx/km83xx.c index 273145aed90a1f..5c6227f7bc3785 100644 --- a/arch/powerpc/platforms/83xx/km83xx.c +++ b/arch/powerpc/platforms/83xx/km83xx.c @@ -34,7 +34,6 @@ #include #include #include -#include #include "mpc83xx.h" diff --git a/arch/powerpc/platforms/83xx/misc.c b/arch/powerpc/platforms/83xx/misc.c index f46d7bf3b14019..6935a5b9fbd138 100644 --- a/arch/powerpc/platforms/83xx/misc.c +++ b/arch/powerpc/platforms/83xx/misc.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include @@ -90,24 +89,9 @@ void __init mpc83xx_ipic_init_IRQ(void) } #ifdef CONFIG_QUICC_ENGINE -void __init mpc83xx_qe_init_IRQ(void) -{ - struct device_node *np; - - np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); - if (!np) { - np = of_find_node_by_type(NULL, "qeic"); - if (!np) - return; - } - qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic); - of_node_put(np); -} - void __init mpc83xx_ipic_and_qe_init_IRQ(void) { mpc83xx_ipic_init_IRQ(); - mpc83xx_qe_init_IRQ(); } #endif /* CONFIG_QUICC_ENGINE */ diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c index b428835e5919eb..1c73af104d1906 100644 --- a/arch/powerpc/platforms/83xx/mpc832x_mds.c +++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c @@ -33,7 +33,6 @@ #include #include #include -#include #include "mpc83xx.h" diff --git a/arch/powerpc/platforms/83xx/mpc832x_rdb.c b/arch/powerpc/platforms/83xx/mpc832x_rdb.c index 4588ce632484e1..87f68ca0625579 100644 --- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c +++ b/arch/powerpc/platforms/83xx/mpc832x_rdb.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c index 4a4efa906d356d..5b484da9533ee5 100644 --- a/arch/powerpc/platforms/83xx/mpc836x_mds.c +++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c @@ -41,7 +41,6 @@ #include #include #include -#include #include "mpc83xx.h" diff --git a/arch/powerpc/platforms/83xx/mpc836x_rdk.c b/arch/powerpc/platforms/83xx/mpc836x_rdk.c index 9923059cb111c2..b7119e443920a8 100644 --- a/arch/powerpc/platforms/83xx/mpc836x_rdk.c +++ b/arch/powerpc/platforms/83xx/mpc836x_rdk.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig index fa3d29dcb57e79..a933e74ca65fff 100644 --- a/arch/powerpc/platforms/85xx/Kconfig +++ b/arch/powerpc/platforms/85xx/Kconfig @@ -10,6 +10,8 @@ menuconfig FSL_SOC_BOOKE select SERIAL_8250_EXTENDED if SERIAL_8250 select SERIAL_8250_SHARE_IRQ if SERIAL_8250 select FSL_CORENET_RCPM if PPC_E500MC + select FSL_QORIQ_PM if SUSPEND && PPC_E500MC + select FSL_PMC if SUSPEND && !PPC_E500MC default y if FSL_SOC_BOOKE @@ -292,3 +294,7 @@ endif # FSL_SOC_BOOKE config TQM85xx bool + +config FSL_QORIQ_PM + bool + select FSL_SLEEP_FSM diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile index d1dd0dca5ebf02..8e9f3699a6a7f5 100644 --- a/arch/powerpc/platforms/85xx/Makefile +++ b/arch/powerpc/platforms/85xx/Makefile @@ -3,7 +3,9 @@ # Makefile for the PowerPC 85xx linux kernel. # obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_SUSPEND) += sleep.o obj-$(CONFIG_FSL_PMC) += mpc85xx_pm_ops.o +obj-$(CONFIG_FSL_QORIQ_PM) += qoriq_pm.o deepsleep.o obj-y += common.o diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c index 7ee2c6628f6462..8c1bb39416423e 100644 --- a/arch/powerpc/platforms/85xx/corenet_generic.c +++ b/arch/powerpc/platforms/85xx/corenet_generic.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include @@ -38,8 +37,6 @@ void __init corenet_gen_pic_init(void) unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU | MPIC_NO_RESET; - struct device_node *np; - if (ppc_md.get_irq == mpic_get_coreint_irq) flags |= MPIC_ENABLE_COREINT; @@ -47,13 +44,6 @@ void __init corenet_gen_pic_init(void) BUG_ON(mpic == NULL); mpic_init(mpic); - - np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); - if (np) { - qe_ic_init(np, 0, qe_ic_cascade_low_mpic, - qe_ic_cascade_high_mpic); - of_node_put(np); - } } /* diff --git a/arch/powerpc/platforms/85xx/deepsleep.c b/arch/powerpc/platforms/85xx/deepsleep.c new file mode 100644 index 00000000000000..73992b4fedccb9 --- /dev/null +++ b/arch/powerpc/platforms/85xx/deepsleep.c @@ -0,0 +1,349 @@ +/* + * Support deep sleep feature for T104x + * + * Copyright 2018 NXP + * Author: Chenhui Zhao + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define SIZE_1MB 0x100000 +#define SIZE_2MB 0x200000 + +#define CPC_CPCHDBCR0 0x10f00 +#define CPC_CPCHDBCR0_SPEC_DIS 0x08000000 + +#define CCSR_SCFG_DPSLPCR 0xfc000 +#define CCSR_SCFG_DPSLPCR_WDRR_EN 0x1 +#define CCSR_SCFG_SPARECR2 0xfc504 +#define CCSR_SCFG_SPARECR3 0xfc508 + +#define CCSR_GPIO1_GPDIR 0x130000 +#define CCSR_GPIO1_GPODR 0x130004 +#define CCSR_GPIO1_GPDAT 0x130008 +#define CCSR_GPIO1_GPDIR_29 0x4 + +#define RCPM_BLOCK_OFFSET 0x00022000 +#define EPU_BLOCK_OFFSET 0x00000000 +#define NPC_BLOCK_OFFSET 0x00001000 + +#define CSTTACR0 0xb00 +#define CG1CR0 0x31c + +#define CCSR_LAW_BASE 0xC00 +#define DCFG_BRR 0xE4 /* boot release register */ +#define LCC_BSTRH 0x20 /* Boot space translation register high */ +#define LCC_BSTRL 0x24 /* Boot space translation register low */ +#define LCC_BSTAR 0x28 /* Boot space translation attribute register */ +#define RCPM_PCTBENR 0x1A0 /* Physical Core Timebase Enable Register */ +#define RCPM_BASE 0xE2000 +#define DCFG_BASE 0xE0000 + +/* 128 bytes buffer for restoring data broke by DDR training initialization */ +#define DDR_BUF_SIZE 128 +static u8 ddr_buff[DDR_BUF_SIZE] __aligned(64); + +static void *dcsr_base, *ccsr_base, *pld_base; +static int pld_flag; + +/* for law */ +struct fsl_law { + u32 lawbarh; /* LAWn base address high */ + u32 lawbarl; /* LAWn base address low */ + u32 lawar; /* LAWn attributes */ + u32 reserved; +}; + +struct fsl_law *saved_law; +static u32 num_laws; + +/* for nonboot cpu */ +struct fsl_bstr { + u32 bstrh; + u32 bstrl; + u32 bstar; + u32 cpu_mask; +}; +static struct fsl_bstr saved_bstr; + +int fsl_dp_iomap(void) +{ + struct device_node *np; + int ret = 0; + phys_addr_t ccsr_phy_addr, dcsr_phy_addr; + + saved_law = NULL; + ccsr_base = NULL; + dcsr_base = NULL; + pld_base = NULL; + + ccsr_phy_addr = get_immrbase(); + if (ccsr_phy_addr == -1) { + pr_err("%s: Can't get the address of CCSR\n", __func__); + ret = -EINVAL; + goto ccsr_err; + } + ccsr_base = ioremap(ccsr_phy_addr, SIZE_2MB); + if (!ccsr_base) { + ret = -ENOMEM; + goto ccsr_err; + } + + dcsr_phy_addr = get_dcsrbase(); + if (dcsr_phy_addr == -1) { + pr_err("%s: Can't get the address of DCSR\n", __func__); + ret = -EINVAL; + goto dcsr_err; + } + dcsr_base = ioremap(dcsr_phy_addr, SIZE_1MB); + if (!dcsr_base) { + ret = -ENOMEM; + goto dcsr_err; + } + + np = of_find_compatible_node(NULL, NULL, "fsl,tetra-fpga"); + if (np) { + pld_flag = T1040QDS_TETRA_FLAG; + } else { + np = of_find_compatible_node(NULL, NULL, "fsl,deepsleep-cpld"); + if (np) { + pld_flag = T104xRDB_CPLD_FLAG; + } else { + pr_err("%s: Can't find the FPGA/CPLD node\n", + __func__); + ret = -EINVAL; + goto pld_err; + } + } + pld_base = of_iomap(np, 0); + of_node_put(np); + + np = of_find_compatible_node(NULL, NULL, "fsl,corenet-law"); + if (!np) { + pr_err("%s: Can't find the node of \"law\"\n", __func__); + ret = -EINVAL; + goto alloc_err; + } + ret = of_property_read_u32(np, "fsl,num-laws", &num_laws); + if (ret) { + ret = -EINVAL; + goto alloc_err; + } + + saved_law = kzalloc(sizeof(*saved_law) * num_laws, GFP_KERNEL); + if (!saved_law) { + ret = -ENOMEM; + goto alloc_err; + } + of_node_put(np); + + return 0; + +alloc_err: + iounmap(pld_base); + pld_base = NULL; +pld_err: + iounmap(dcsr_base); + dcsr_base = NULL; +dcsr_err: + iounmap(ccsr_base); + ccsr_base = NULL; +ccsr_err: + return ret; +} + +void fsl_dp_iounmap(void) +{ + if (dcsr_base) { + iounmap(dcsr_base); + dcsr_base = NULL; + } + + if (ccsr_base) { + iounmap(ccsr_base); + ccsr_base = NULL; + } + + if (pld_base) { + iounmap(pld_base); + pld_base = NULL; + } + + kfree(saved_law); + saved_law = NULL; +} + +static void fsl_dp_ddr_save(void *ccsr_base) +{ + u32 ddr_buff_addr; + + /* + * DDR training initialization will break 128 bytes at the beginning + * of DDR, therefore, save them so that the bootloader will restore + * them. Assume that DDR is mapped to the address space started with + * CONFIG_PAGE_OFFSET. + */ + memcpy(ddr_buff, (void *)CONFIG_PAGE_OFFSET, DDR_BUF_SIZE); + + /* assume ddr_buff is in the physical address space of 4GB */ + ddr_buff_addr = (u32)(__pa(ddr_buff) & 0xffffffff); + + /* + * the bootloader will restore the first 128 bytes of DDR from + * the location indicated by the register SPARECR3 + */ + out_be32(ccsr_base + CCSR_SCFG_SPARECR3, ddr_buff_addr); +} + +static void fsl_dp_mp_save(void *ccsr) +{ + struct fsl_bstr *dst = &saved_bstr; + + dst->bstrh = in_be32(ccsr + LCC_BSTRH); + dst->bstrl = in_be32(ccsr + LCC_BSTRL); + dst->bstar = in_be32(ccsr + LCC_BSTAR); + dst->cpu_mask = in_be32(ccsr + DCFG_BASE + DCFG_BRR); +} + +static void fsl_dp_mp_restore(void *ccsr) +{ + struct fsl_bstr *src = &saved_bstr; + + out_be32(ccsr + LCC_BSTRH, src->bstrh); + out_be32(ccsr + LCC_BSTRL, src->bstrl); + out_be32(ccsr + LCC_BSTAR, src->bstar); + + /* release the nonboot cpus */ + out_be32(ccsr + DCFG_BASE + DCFG_BRR, src->cpu_mask); + + /* enable the time base */ + out_be32(ccsr + RCPM_BASE + RCPM_PCTBENR, src->cpu_mask); + /* read back to sync write */ + in_be32(ccsr + RCPM_BASE + RCPM_PCTBENR); +} + +static void fsl_dp_law_save(void *ccsr) +{ + int i; + struct fsl_law *dst = saved_law; + struct fsl_law *src = (void *)(ccsr + CCSR_LAW_BASE); + + for (i = 0; i < num_laws; i++) { + dst->lawbarh = in_be32(&src->lawbarh); + dst->lawbarl = in_be32(&src->lawbarl); + dst->lawar = in_be32(&src->lawar); + dst++; + src++; + } +} + +static void fsl_dp_law_restore(void *ccsr) +{ + int i; + struct fsl_law *src = saved_law; + struct fsl_law *dst = (void *)(ccsr + CCSR_LAW_BASE); + + for (i = 0; i < num_laws - 1; i++) { + out_be32(&dst->lawar, 0); + out_be32(&dst->lawbarl, src->lawbarl); + out_be32(&dst->lawbarh, src->lawbarh); + out_be32(&dst->lawar, src->lawar); + + /* Read back so that we sync the writes */ + in_be32(&dst->lawar); + src++; + dst++; + } +} + +static void fsl_dp_set_resume_pointer(void *ccsr_base) +{ + u32 resume_addr; + + /* the bootloader will finally jump to this address to return kernel */ +#ifdef CONFIG_PPC32 + resume_addr = (u32)(__pa(fsl_booke_deep_sleep_resume)); +#else + resume_addr = (u32)(__pa(*(u64 *)fsl_booke_deep_sleep_resume) + & 0xffffffff); +#endif + + /* use the register SPARECR2 to save the resume address */ + out_be32(ccsr_base + CCSR_SCFG_SPARECR2, resume_addr); + +} + +int fsl_enter_epu_deepsleep(void) +{ + fsl_dp_ddr_save(ccsr_base); + + fsl_dp_set_resume_pointer(ccsr_base); + + fsl_dp_mp_save(ccsr_base); + fsl_dp_law_save(ccsr_base); + /* enable Warm Device Reset request. */ + setbits32(ccsr_base + CCSR_SCFG_DPSLPCR, CCSR_SCFG_DPSLPCR_WDRR_EN); + + /* set GPIO1_29 as an output pin (not open-drain), and output 0 */ + clrbits32(ccsr_base + CCSR_GPIO1_GPDAT, CCSR_GPIO1_GPDIR_29); + clrbits32(ccsr_base + CCSR_GPIO1_GPODR, CCSR_GPIO1_GPDIR_29); + setbits32(ccsr_base + CCSR_GPIO1_GPDIR, CCSR_GPIO1_GPDIR_29); + + /* + * Disable CPC speculation to avoid deep sleep hang, especially + * in secure boot mode. This bit will be cleared automatically + * when resuming from deep sleep. + */ + setbits32(ccsr_base + CPC_CPCHDBCR0, CPC_CPCHDBCR0_SPEC_DIS); + + fsl_epu_setup_default(dcsr_base + EPU_BLOCK_OFFSET); + fsl_npc_setup_default(dcsr_base + NPC_BLOCK_OFFSET); + out_be32(dcsr_base + RCPM_BLOCK_OFFSET + CSTTACR0, 0x00001001); + out_be32(dcsr_base + RCPM_BLOCK_OFFSET + CG1CR0, 0x00000001); + + fsl_dp_enter_low(ccsr_base, dcsr_base, pld_base, pld_flag); + + fsl_dp_law_restore(ccsr_base); + fsl_dp_mp_restore(ccsr_base); + + /* disable Warm Device Reset request */ + clrbits32(ccsr_base + CCSR_SCFG_DPSLPCR, CCSR_SCFG_DPSLPCR_WDRR_EN); + + fsl_epu_clean_default(dcsr_base + EPU_BLOCK_OFFSET); + + return 0; +} diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c index 5ca254256c475e..7d3129030395c4 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c @@ -45,7 +45,6 @@ #include #include #include -#include #include #include #include "smp.h" @@ -279,20 +278,6 @@ static void __init mpc85xx_mds_qeic_init(void) of_node_put(np); return; } - - np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); - if (!np) { - np = of_find_node_by_type(NULL, "qeic"); - if (!np) - return; - } - - if (machine_is(p1021_mds)) - qe_ic_init(np, 0, qe_ic_cascade_low_mpic, - qe_ic_cascade_high_mpic); - else - qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL); - of_node_put(np); } #else static void __init mpc85xx_mds_qe_init(void) { } diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c index d3c540ee558ff5..14b5a61d49c1d5 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include @@ -44,10 +43,6 @@ void __init mpc85xx_rdb_pic_init(void) { struct mpic *mpic; -#ifdef CONFIG_QUICC_ENGINE - struct device_node *np; -#endif - if (of_machine_is_compatible("fsl,MPC85XXRDB-CAMP")) { mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET | MPIC_BIG_ENDIAN | @@ -62,18 +57,6 @@ void __init mpc85xx_rdb_pic_init(void) BUG_ON(mpic == NULL); mpic_init(mpic); - -#ifdef CONFIG_QUICC_ENGINE - np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); - if (np) { - qe_ic_init(np, 0, qe_ic_cascade_low_mpic, - qe_ic_cascade_high_mpic); - of_node_put(np); - - } else - pr_err("%s: Could not find qe-ic node\n", __func__); -#endif - } /* diff --git a/arch/powerpc/platforms/85xx/qoriq_pm.c b/arch/powerpc/platforms/85xx/qoriq_pm.c new file mode 100644 index 00000000000000..9390944c53f0ee --- /dev/null +++ b/arch/powerpc/platforms/85xx/qoriq_pm.c @@ -0,0 +1,222 @@ +/* + * Support Power Management feature + * + * Copyright 2018 NXP + * Author: Chenhui Zhao + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +#include + +#define FSL_SLEEP 0x1 +#define FSL_DEEP_SLEEP 0x2 + +int (*fsl_enter_deepsleep)(void); + +/* specify the sleep state of the present platform */ +unsigned int sleep_pm_state; +/* supported sleep modes by the present platform */ +static unsigned int sleep_modes; + +/** + * fsl_set_power_except - set which IP block is not powerdown when sleep, + * such as MAC, USB, etc. + * + * @dev: a pointer to the struct device + * @on: if 1, do not power down; if 0, power down. + */ +void fsl_set_power_except(struct device *dev, int on) +{ + u32 value[2]; + u32 pw_mask; + int ret; + struct device_node *mac_node; + const phandle *phandle_prop; + + if (dev && !strncmp(dev->bus->name, "usb", 3)) { + struct usb_device *udev = container_of(dev, + struct usb_device, dev); + struct device *controller = udev->bus->controller; + + ret = of_property_read_u32_array(controller->parent->of_node, + "sleep", value, 2); + } else + ret = of_property_read_u32_array(dev->of_node, "sleep", + value, 2); + + if (ret) { + /* search fman mac node */ + phandle_prop = of_get_property(dev->of_node, "fsl,fman-mac", + NULL); + if (phandle_prop == NULL) + goto err; + + mac_node = of_find_node_by_phandle(*phandle_prop); + ret = of_property_read_u32_array(mac_node, "sleep", value, 2); + of_node_put(mac_node); + if (ret) + goto err; + } + /* get the second value, it is a mask */ + pw_mask = value[1]; + qoriq_pm_ops->set_ip_power(on, pw_mask); + return; + +err: + dev_err(dev, "Can not set wakeup sources\n"); +} +EXPORT_SYMBOL_GPL(fsl_set_power_except); + +void qoriq_set_wakeup_source(struct device *dev, void *enable) +{ + if (!device_may_wakeup(dev)) + return; + + fsl_set_power_except(dev, *((int *)enable)); +} + +static int qoriq_suspend_enter(suspend_state_t state) +{ + int ret = 0; + int cpu; + + switch (state) { + case PM_SUSPEND_STANDBY: + + if (cur_cpu_spec->cpu_flush_caches) + cur_cpu_spec->cpu_flush_caches(); + + ret = qoriq_pm_ops->plat_enter_sleep(); + + break; + + case PM_SUSPEND_MEM: + + cpu = smp_processor_id(); + qoriq_pm_ops->irq_mask(cpu); + + ret = fsl_enter_deepsleep(); + + qoriq_pm_ops->irq_unmask(cpu); + + break; + + default: + ret = -EINVAL; + + } + + return ret; +} + +static int qoriq_suspend_valid(suspend_state_t state) +{ + set_pm_suspend_state(state); + + if (state == PM_SUSPEND_STANDBY && (sleep_modes & FSL_SLEEP)) + return 1; + + if (state == PM_SUSPEND_MEM && (sleep_modes & FSL_DEEP_SLEEP)) + return 1; + + set_pm_suspend_state(PM_SUSPEND_ON); + return 0; +} + +static int qoriq_suspend_begin(suspend_state_t state) +{ + const int enable = 1; + + dpm_for_each_dev((void *)&enable, qoriq_set_wakeup_source); + + if (state == PM_SUSPEND_MEM) + return fsl_dp_iomap(); + + return 0; +} + +static void qoriq_suspend_end(void) +{ + const int enable = 0; + + dpm_for_each_dev((void *)&enable, qoriq_set_wakeup_source); + + set_pm_suspend_state(PM_SUSPEND_ON); + fsl_dp_iounmap(); +} + +static const struct platform_suspend_ops qoriq_suspend_ops = { + .valid = qoriq_suspend_valid, + .enter = qoriq_suspend_enter, + .begin = qoriq_suspend_begin, + .end = qoriq_suspend_end, +}; + +static const struct of_device_id deepsleep_matches[] = { + { + .compatible = "fsl,t1040-rcpm", + }, + { + .compatible = "fsl,t1024-rcpm", + }, + { + .compatible = "fsl,t1023-rcpm", + }, + {}, +}; + +static int __init qoriq_suspend_init(void) +{ + struct device_node *np; + + sleep_modes = FSL_SLEEP; + sleep_pm_state = PLAT_PM_SLEEP; + + np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-rcpm-2.0"); + if (np) + sleep_pm_state = PLAT_PM_LPM20; + + np = of_find_matching_node_and_match(NULL, deepsleep_matches, NULL); + if (np) { + fsl_enter_deepsleep = fsl_enter_epu_deepsleep; + sleep_modes |= FSL_DEEP_SLEEP; + } + + suspend_set_ops(&qoriq_suspend_ops); + set_pm_suspend_state(PM_SUSPEND_ON); + + return 0; +} +arch_initcall(qoriq_suspend_init); diff --git a/arch/powerpc/platforms/85xx/sleep.S b/arch/powerpc/platforms/85xx/sleep.S new file mode 100644 index 00000000000000..b7942edce2f06a --- /dev/null +++ b/arch/powerpc/platforms/85xx/sleep.S @@ -0,0 +1,1192 @@ +/* + * Enter and leave deep sleep/sleep state + * + * Copyright 2018 NXP + * Author: Scott Wood + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. +*/ + +#include +#include +#include +#include +#include +#include + +/* + * the number of bytes occupied by one register + * the value of 8 is compatible with both 32-bit and 64-bit registers + */ +#define STRIDE_SIZE 8 + +/* GPR0 - GPR31 */ +#define BOOKE_GPR0_OFF 0x0000 +#define BOOKE_GPR_COUNT 32 +/* IVOR0 - IVOR42 */ +#define BOOKE_IVOR0_OFF (BOOKE_GPR0_OFF + BOOKE_GPR_COUNT * STRIDE_SIZE) +#define BOOKE_IVOR_COUNT 43 +/* SPRG0 - SPRG9 */ +#define BOOKE_SPRG0_OFF (BOOKE_IVOR0_OFF + BOOKE_IVOR_COUNT * STRIDE_SIZE) +#define BOOKE_SPRG_COUNT 10 +/* IVPR */ +#define BOOKE_IVPR_OFF (BOOKE_SPRG0_OFF + BOOKE_SPRG_COUNT * STRIDE_SIZE) + +#define BOOKE_LR_OFF (BOOKE_IVPR_OFF + STRIDE_SIZE) +#define BOOKE_MSR_OFF (BOOKE_LR_OFF + STRIDE_SIZE) +#define BOOKE_TBU_OFF (BOOKE_MSR_OFF + STRIDE_SIZE) +#define BOOKE_TBL_OFF (BOOKE_TBU_OFF + STRIDE_SIZE) +#define BOOKE_EPCR_OFF (BOOKE_TBL_OFF + STRIDE_SIZE) +#define BOOKE_HID0_OFF (BOOKE_EPCR_OFF + STRIDE_SIZE) +#define BOOKE_PIR_OFF (BOOKE_HID0_OFF + STRIDE_SIZE) +#define BOOKE_PID0_OFF (BOOKE_PIR_OFF + STRIDE_SIZE) +#define BOOKE_BUCSR_OFF (BOOKE_PID0_OFF + STRIDE_SIZE) + +#define BUFFER_SIZE (BOOKE_BUCSR_OFF + STRIDE_SIZE) + +#undef SAVE_GPR +#define SAVE_GPR(gpr, offset) \ + PPC_STL gpr, offset(r10) + +#define RESTORE_GPR(gpr, offset) \ + PPC_LL gpr, offset(r10) + +#define SAVE_SPR(spr, offset) \ + mfspr r0, spr ;\ + PPC_STL r0, offset(r10) + +#define RESTORE_SPR(spr, offset) \ + PPC_LL r0, offset(r10) ;\ + mtspr spr, r0 + +#define SAVE_ALL_GPR \ + SAVE_GPR(r1, BOOKE_GPR0_OFF + STRIDE_SIZE * 1) ;\ + SAVE_GPR(r2, BOOKE_GPR0_OFF + STRIDE_SIZE * 2) ;\ + SAVE_GPR(r13, BOOKE_GPR0_OFF + STRIDE_SIZE * 13) ;\ + SAVE_GPR(r14, BOOKE_GPR0_OFF + STRIDE_SIZE * 14) ;\ + SAVE_GPR(r15, BOOKE_GPR0_OFF + STRIDE_SIZE * 15) ;\ + SAVE_GPR(r16, BOOKE_GPR0_OFF + STRIDE_SIZE * 16) ;\ + SAVE_GPR(r17, BOOKE_GPR0_OFF + STRIDE_SIZE * 17) ;\ + SAVE_GPR(r18, BOOKE_GPR0_OFF + STRIDE_SIZE * 18) ;\ + SAVE_GPR(r19, BOOKE_GPR0_OFF + STRIDE_SIZE * 19) ;\ + SAVE_GPR(r20, BOOKE_GPR0_OFF + STRIDE_SIZE * 20) ;\ + SAVE_GPR(r21, BOOKE_GPR0_OFF + STRIDE_SIZE * 21) ;\ + SAVE_GPR(r22, BOOKE_GPR0_OFF + STRIDE_SIZE * 22) ;\ + SAVE_GPR(r23, BOOKE_GPR0_OFF + STRIDE_SIZE * 23) ;\ + SAVE_GPR(r24, BOOKE_GPR0_OFF + STRIDE_SIZE * 24) ;\ + SAVE_GPR(r25, BOOKE_GPR0_OFF + STRIDE_SIZE * 25) ;\ + SAVE_GPR(r26, BOOKE_GPR0_OFF + STRIDE_SIZE * 26) ;\ + SAVE_GPR(r27, BOOKE_GPR0_OFF + STRIDE_SIZE * 27) ;\ + SAVE_GPR(r28, BOOKE_GPR0_OFF + STRIDE_SIZE * 28) ;\ + SAVE_GPR(r29, BOOKE_GPR0_OFF + STRIDE_SIZE * 29) ;\ + SAVE_GPR(r30, BOOKE_GPR0_OFF + STRIDE_SIZE * 30) ;\ + SAVE_GPR(r31, BOOKE_GPR0_OFF + STRIDE_SIZE * 31) + +#define RESTORE_ALL_GPR \ + RESTORE_GPR(r1, BOOKE_GPR0_OFF + STRIDE_SIZE * 1) ;\ + RESTORE_GPR(r2, BOOKE_GPR0_OFF + STRIDE_SIZE * 2) ;\ + RESTORE_GPR(r13, BOOKE_GPR0_OFF + STRIDE_SIZE * 13) ;\ + RESTORE_GPR(r14, BOOKE_GPR0_OFF + STRIDE_SIZE * 14) ;\ + RESTORE_GPR(r15, BOOKE_GPR0_OFF + STRIDE_SIZE * 15) ;\ + RESTORE_GPR(r16, BOOKE_GPR0_OFF + STRIDE_SIZE * 16) ;\ + RESTORE_GPR(r17, BOOKE_GPR0_OFF + STRIDE_SIZE * 17) ;\ + RESTORE_GPR(r18, BOOKE_GPR0_OFF + STRIDE_SIZE * 18) ;\ + RESTORE_GPR(r19, BOOKE_GPR0_OFF + STRIDE_SIZE * 19) ;\ + RESTORE_GPR(r20, BOOKE_GPR0_OFF + STRIDE_SIZE * 20) ;\ + RESTORE_GPR(r21, BOOKE_GPR0_OFF + STRIDE_SIZE * 21) ;\ + RESTORE_GPR(r22, BOOKE_GPR0_OFF + STRIDE_SIZE * 22) ;\ + RESTORE_GPR(r23, BOOKE_GPR0_OFF + STRIDE_SIZE * 23) ;\ + RESTORE_GPR(r24, BOOKE_GPR0_OFF + STRIDE_SIZE * 24) ;\ + RESTORE_GPR(r25, BOOKE_GPR0_OFF + STRIDE_SIZE * 25) ;\ + RESTORE_GPR(r26, BOOKE_GPR0_OFF + STRIDE_SIZE * 26) ;\ + RESTORE_GPR(r27, BOOKE_GPR0_OFF + STRIDE_SIZE * 27) ;\ + RESTORE_GPR(r28, BOOKE_GPR0_OFF + STRIDE_SIZE * 28) ;\ + RESTORE_GPR(r29, BOOKE_GPR0_OFF + STRIDE_SIZE * 29) ;\ + RESTORE_GPR(r30, BOOKE_GPR0_OFF + STRIDE_SIZE * 30) ;\ + RESTORE_GPR(r31, BOOKE_GPR0_OFF + STRIDE_SIZE * 31) + +#define SAVE_ALL_SPRG \ + SAVE_SPR(SPRN_SPRG0, BOOKE_SPRG0_OFF + STRIDE_SIZE * 0) ;\ + SAVE_SPR(SPRN_SPRG1, BOOKE_SPRG0_OFF + STRIDE_SIZE * 1) ;\ + SAVE_SPR(SPRN_SPRG2, BOOKE_SPRG0_OFF + STRIDE_SIZE * 2) ;\ + SAVE_SPR(SPRN_SPRG3, BOOKE_SPRG0_OFF + STRIDE_SIZE * 3) ;\ + SAVE_SPR(SPRN_SPRG4, BOOKE_SPRG0_OFF + STRIDE_SIZE * 4) ;\ + SAVE_SPR(SPRN_SPRG5, BOOKE_SPRG0_OFF + STRIDE_SIZE * 5) ;\ + SAVE_SPR(SPRN_SPRG6, BOOKE_SPRG0_OFF + STRIDE_SIZE * 6) ;\ + SAVE_SPR(SPRN_SPRG7, BOOKE_SPRG0_OFF + STRIDE_SIZE * 7) ;\ + SAVE_SPR(SPRN_SPRG8, BOOKE_SPRG0_OFF + STRIDE_SIZE * 8) ;\ + SAVE_SPR(SPRN_SPRG9, BOOKE_SPRG0_OFF + STRIDE_SIZE * 9) + +#define RESTORE_ALL_SPRG \ + RESTORE_SPR(SPRN_SPRG0, BOOKE_SPRG0_OFF + STRIDE_SIZE * 0) ;\ + RESTORE_SPR(SPRN_SPRG1, BOOKE_SPRG0_OFF + STRIDE_SIZE * 1) ;\ + RESTORE_SPR(SPRN_SPRG2, BOOKE_SPRG0_OFF + STRIDE_SIZE * 2) ;\ + RESTORE_SPR(SPRN_SPRG3, BOOKE_SPRG0_OFF + STRIDE_SIZE * 3) ;\ + RESTORE_SPR(SPRN_SPRG4, BOOKE_SPRG0_OFF + STRIDE_SIZE * 4) ;\ + RESTORE_SPR(SPRN_SPRG5, BOOKE_SPRG0_OFF + STRIDE_SIZE * 5) ;\ + RESTORE_SPR(SPRN_SPRG6, BOOKE_SPRG0_OFF + STRIDE_SIZE * 6) ;\ + RESTORE_SPR(SPRN_SPRG7, BOOKE_SPRG0_OFF + STRIDE_SIZE * 7) ;\ + RESTORE_SPR(SPRN_SPRG8, BOOKE_SPRG0_OFF + STRIDE_SIZE * 8) ;\ + RESTORE_SPR(SPRN_SPRG9, BOOKE_SPRG0_OFF + STRIDE_SIZE * 9) + +#define SAVE_ALL_IVOR \ + SAVE_SPR(SPRN_IVOR0, BOOKE_IVOR0_OFF + STRIDE_SIZE * 0) ;\ + SAVE_SPR(SPRN_IVOR1, BOOKE_IVOR0_OFF + STRIDE_SIZE * 1) ;\ + SAVE_SPR(SPRN_IVOR2, BOOKE_IVOR0_OFF + STRIDE_SIZE * 2) ;\ + SAVE_SPR(SPRN_IVOR3, BOOKE_IVOR0_OFF + STRIDE_SIZE * 3) ;\ + SAVE_SPR(SPRN_IVOR4, BOOKE_IVOR0_OFF + STRIDE_SIZE * 4) ;\ + SAVE_SPR(SPRN_IVOR5, BOOKE_IVOR0_OFF + STRIDE_SIZE * 5) ;\ + SAVE_SPR(SPRN_IVOR6, BOOKE_IVOR0_OFF + STRIDE_SIZE * 6) ;\ + SAVE_SPR(SPRN_IVOR7, BOOKE_IVOR0_OFF + STRIDE_SIZE * 7) ;\ + SAVE_SPR(SPRN_IVOR8, BOOKE_IVOR0_OFF + STRIDE_SIZE * 8) ;\ + SAVE_SPR(SPRN_IVOR9, BOOKE_IVOR0_OFF + STRIDE_SIZE * 9) ;\ + SAVE_SPR(SPRN_IVOR10, BOOKE_IVOR0_OFF + STRIDE_SIZE * 10) ;\ + SAVE_SPR(SPRN_IVOR11, BOOKE_IVOR0_OFF + STRIDE_SIZE * 11) ;\ + SAVE_SPR(SPRN_IVOR12, BOOKE_IVOR0_OFF + STRIDE_SIZE * 12) ;\ + SAVE_SPR(SPRN_IVOR13, BOOKE_IVOR0_OFF + STRIDE_SIZE * 13) ;\ + SAVE_SPR(SPRN_IVOR14, BOOKE_IVOR0_OFF + STRIDE_SIZE * 14) ;\ + SAVE_SPR(SPRN_IVOR15, BOOKE_IVOR0_OFF + STRIDE_SIZE * 15) ;\ + SAVE_SPR(SPRN_IVOR35, BOOKE_IVOR0_OFF + STRIDE_SIZE * 35) ;\ + SAVE_SPR(SPRN_IVOR36, BOOKE_IVOR0_OFF + STRIDE_SIZE * 36) ;\ + SAVE_SPR(SPRN_IVOR37, BOOKE_IVOR0_OFF + STRIDE_SIZE * 37) ;\ + SAVE_SPR(SPRN_IVOR38, BOOKE_IVOR0_OFF + STRIDE_SIZE * 38) ;\ + SAVE_SPR(SPRN_IVOR39, BOOKE_IVOR0_OFF + STRIDE_SIZE * 39) ;\ + SAVE_SPR(SPRN_IVOR40, BOOKE_IVOR0_OFF + STRIDE_SIZE * 40) ;\ + SAVE_SPR(SPRN_IVOR41, BOOKE_IVOR0_OFF + STRIDE_SIZE * 41) + +#define RESTORE_ALL_IVOR \ + RESTORE_SPR(SPRN_IVOR0, BOOKE_IVOR0_OFF + STRIDE_SIZE * 0) ;\ + RESTORE_SPR(SPRN_IVOR1, BOOKE_IVOR0_OFF + STRIDE_SIZE * 1) ;\ + RESTORE_SPR(SPRN_IVOR2, BOOKE_IVOR0_OFF + STRIDE_SIZE * 2) ;\ + RESTORE_SPR(SPRN_IVOR3, BOOKE_IVOR0_OFF + STRIDE_SIZE * 3) ;\ + RESTORE_SPR(SPRN_IVOR4, BOOKE_IVOR0_OFF + STRIDE_SIZE * 4) ;\ + RESTORE_SPR(SPRN_IVOR5, BOOKE_IVOR0_OFF + STRIDE_SIZE * 5) ;\ + RESTORE_SPR(SPRN_IVOR6, BOOKE_IVOR0_OFF + STRIDE_SIZE * 6) ;\ + RESTORE_SPR(SPRN_IVOR7, BOOKE_IVOR0_OFF + STRIDE_SIZE * 7) ;\ + RESTORE_SPR(SPRN_IVOR8, BOOKE_IVOR0_OFF + STRIDE_SIZE * 8) ;\ + RESTORE_SPR(SPRN_IVOR9, BOOKE_IVOR0_OFF + STRIDE_SIZE * 9) ;\ + RESTORE_SPR(SPRN_IVOR10, BOOKE_IVOR0_OFF + STRIDE_SIZE * 10) ;\ + RESTORE_SPR(SPRN_IVOR11, BOOKE_IVOR0_OFF + STRIDE_SIZE * 11) ;\ + RESTORE_SPR(SPRN_IVOR12, BOOKE_IVOR0_OFF + STRIDE_SIZE * 12) ;\ + RESTORE_SPR(SPRN_IVOR13, BOOKE_IVOR0_OFF + STRIDE_SIZE * 13) ;\ + RESTORE_SPR(SPRN_IVOR14, BOOKE_IVOR0_OFF + STRIDE_SIZE * 14) ;\ + RESTORE_SPR(SPRN_IVOR15, BOOKE_IVOR0_OFF + STRIDE_SIZE * 15) ;\ + RESTORE_SPR(SPRN_IVOR35, BOOKE_IVOR0_OFF + STRIDE_SIZE * 35) ;\ + RESTORE_SPR(SPRN_IVOR36, BOOKE_IVOR0_OFF + STRIDE_SIZE * 36) ;\ + RESTORE_SPR(SPRN_IVOR37, BOOKE_IVOR0_OFF + STRIDE_SIZE * 37) ;\ + RESTORE_SPR(SPRN_IVOR38, BOOKE_IVOR0_OFF + STRIDE_SIZE * 38) ;\ + RESTORE_SPR(SPRN_IVOR39, BOOKE_IVOR0_OFF + STRIDE_SIZE * 39) ;\ + RESTORE_SPR(SPRN_IVOR40, BOOKE_IVOR0_OFF + STRIDE_SIZE * 40) ;\ + RESTORE_SPR(SPRN_IVOR41, BOOKE_IVOR0_OFF + STRIDE_SIZE * 41) + +/* reset time base to prevent from overflow */ +#define DELAY(count) \ + li r3, count; \ + li r4, 0; \ + mtspr SPRN_TBWL, r4; \ +101: mfspr r4, SPRN_TBRL; \ + cmpw r4, r3; \ + blt 101b + +#define FSL_DIS_ALL_IRQ \ + mfmsr r8; \ + rlwinm r8, r8, 0, ~MSR_CE; \ + rlwinm r8, r8, 0, ~MSR_ME; \ + rlwinm r8, r8, 0, ~MSR_EE; \ + rlwinm r8, r8, 0, ~MSR_DE; \ + mtmsr r8; \ + isync + +#ifndef CONFIG_PPC_E500MC +#define SS_TB 0x00 +#define SS_HID 0x08 /* 2 HIDs */ +#define SS_IAC 0x10 /* 2 IACs */ +#define SS_DAC 0x18 /* 2 DACs */ +#define SS_DBCR 0x20 /* 3 DBCRs */ +#define SS_PID 0x2c /* 3 PIDs */ +#define SS_SPRG 0x38 /* 8 SPRGs */ +#define SS_IVOR 0x58 /* 20 interrupt vectors */ +#define SS_TCR 0xa8 +#define SS_BUCSR 0xac +#define SS_L1CSR 0xb0 /* 2 L1CSRs */ +#define SS_MSR 0xb8 +#define SS_USPRG 0xbc +#define SS_GPREG 0xc0 /* r12-r31 */ +#define SS_LR 0x110 +#define SS_CR 0x114 +#define SS_SP 0x118 +#define SS_CURRENT 0x11c +#define SS_IVPR 0x120 +#define SS_BPTR 0x124 + + +#define STATE_SAVE_SIZE 0x128 + + .section .data + .align 5 +mpc85xx_sleep_save_area: + .space STATE_SAVE_SIZE +ccsrbase_low: + .long 0 +ccsrbase_high: + .long 0 +powmgtreq: + .long 0 + + .section .text + .align 12 + + /* + * r3 = high word of physical address of CCSR + * r4 = low word of physical address of CCSR + * r5 = JOG or deep sleep request + * JOG-0x00200000, deep sleep-0x00100000 + */ +_GLOBAL(mpc85xx_enter_deep_sleep) + lis r6, ccsrbase_low@ha + stw r4, ccsrbase_low@l(r6) + lis r6, ccsrbase_high@ha + stw r3, ccsrbase_high@l(r6) + + lis r6, powmgtreq@ha + stw r5, powmgtreq@l(r6) + + lis r10, mpc85xx_sleep_save_area@h + ori r10, r10, mpc85xx_sleep_save_area@l + + mfspr r5, SPRN_HID0 + mfspr r6, SPRN_HID1 + + stw r5, SS_HID+0(r10) + stw r6, SS_HID+4(r10) + + mfspr r4, SPRN_IAC1 + mfspr r5, SPRN_IAC2 + mfspr r6, SPRN_DAC1 + mfspr r7, SPRN_DAC2 + + stw r4, SS_IAC+0(r10) + stw r5, SS_IAC+4(r10) + stw r6, SS_DAC+0(r10) + stw r7, SS_DAC+4(r10) + + mfspr r4, SPRN_DBCR0 + mfspr r5, SPRN_DBCR1 + mfspr r6, SPRN_DBCR2 + + stw r4, SS_DBCR+0(r10) + stw r5, SS_DBCR+4(r10) + stw r6, SS_DBCR+8(r10) + + mfspr r4, SPRN_PID0 + mfspr r5, SPRN_PID1 + mfspr r6, SPRN_PID2 + + stw r4, SS_PID+0(r10) + stw r5, SS_PID+4(r10) + stw r6, SS_PID+8(r10) + + mfspr r4, SPRN_SPRG0 + mfspr r5, SPRN_SPRG1 + mfspr r6, SPRN_SPRG2 + mfspr r7, SPRN_SPRG3 + + stw r4, SS_SPRG+0x00(r10) + stw r5, SS_SPRG+0x04(r10) + stw r6, SS_SPRG+0x08(r10) + stw r7, SS_SPRG+0x0c(r10) + + mfspr r4, SPRN_SPRG4 + mfspr r5, SPRN_SPRG5 + mfspr r6, SPRN_SPRG6 + mfspr r7, SPRN_SPRG7 + + stw r4, SS_SPRG+0x10(r10) + stw r5, SS_SPRG+0x14(r10) + stw r6, SS_SPRG+0x18(r10) + stw r7, SS_SPRG+0x1c(r10) + + mfspr r4, SPRN_IVPR + stw r4, SS_IVPR(r10) + + mfspr r4, SPRN_IVOR0 + mfspr r5, SPRN_IVOR1 + mfspr r6, SPRN_IVOR2 + mfspr r7, SPRN_IVOR3 + + stw r4, SS_IVOR+0x00(r10) + stw r5, SS_IVOR+0x04(r10) + stw r6, SS_IVOR+0x08(r10) + stw r7, SS_IVOR+0x0c(r10) + + mfspr r4, SPRN_IVOR4 + mfspr r5, SPRN_IVOR5 + mfspr r6, SPRN_IVOR6 + mfspr r7, SPRN_IVOR7 + + stw r4, SS_IVOR+0x10(r10) + stw r5, SS_IVOR+0x14(r10) + stw r6, SS_IVOR+0x18(r10) + stw r7, SS_IVOR+0x1c(r10) + + mfspr r4, SPRN_IVOR8 + mfspr r5, SPRN_IVOR9 + mfspr r6, SPRN_IVOR10 + mfspr r7, SPRN_IVOR11 + + stw r4, SS_IVOR+0x20(r10) + stw r5, SS_IVOR+0x24(r10) + stw r6, SS_IVOR+0x28(r10) + stw r7, SS_IVOR+0x2c(r10) + + mfspr r4, SPRN_IVOR12 + mfspr r5, SPRN_IVOR13 + mfspr r6, SPRN_IVOR14 + mfspr r7, SPRN_IVOR15 + + stw r4, SS_IVOR+0x30(r10) + stw r5, SS_IVOR+0x34(r10) + stw r6, SS_IVOR+0x38(r10) + stw r7, SS_IVOR+0x3c(r10) + + mfspr r4, SPRN_IVOR32 + mfspr r5, SPRN_IVOR33 + mfspr r6, SPRN_IVOR34 + mfspr r7, SPRN_IVOR35 + + stw r4, SS_IVOR+0x40(r10) + stw r5, SS_IVOR+0x44(r10) + stw r6, SS_IVOR+0x48(r10) + stw r7, SS_IVOR+0x4c(r10) + + mfspr r4, SPRN_TCR + mfspr r5, SPRN_BUCSR + mfspr r6, SPRN_L1CSR0 + mfspr r7, SPRN_L1CSR1 + mfspr r8, SPRN_USPRG0 + + stw r4, SS_TCR(r10) + stw r5, SS_BUCSR(r10) + stw r6, SS_L1CSR+0(r10) + stw r7, SS_L1CSR+4(r10) + stw r8, SS_USPRG+0(r10) + + stmw r12, SS_GPREG(r10) + + mfmsr r4 + mflr r5 + mfcr r6 + + stw r4, SS_MSR(r10) + stw r5, SS_LR(r10) + stw r6, SS_CR(r10) + stw r1, SS_SP(r10) + stw r2, SS_CURRENT(r10) + +1: mftbu r4 + mftb r5 + mftbu r6 + cmpw r4, r6 + bne 1b + + stw r4, SS_TB+0(r10) + stw r5, SS_TB+4(r10) + + lis r5, ccsrbase_low@ha + lwz r4, ccsrbase_low@l(r5) + lis r5, ccsrbase_high@ha + lwz r3, ccsrbase_high@l(r5) + + /* Disable machine checks and critical exceptions */ + mfmsr r5 + rlwinm r5, r5, 0, ~MSR_CE + rlwinm r5, r5, 0, ~MSR_ME + mtmsr r5 + isync + + /* Use TLB1[15] to map the CCSR at 0xf0000000 */ + lis r5, 0x100f + mtspr SPRN_MAS0, r5 + lis r5, 0xc000 + ori r5, r5, 0x0500 + mtspr SPRN_MAS1, r5 + lis r5, 0xf000 + ori r5, r5, 0x000a + mtspr SPRN_MAS2, r5 + rlwinm r5, r4, 0, 0xfffff000 + ori r5, r5, 0x0005 + mtspr SPRN_MAS3, r5 + mtspr SPRN_MAS7, r3 + isync + tlbwe + isync + + lis r3, 0xf000 + lwz r4, 0x20(r3) + stw r4, SS_BPTR(r10) + + lis r3, 0xf002 /* L2 cache controller at CCSR+0x20000 */ + bl flush_disable_L2 + bl __flush_disable_L1 + + /* Enable I-cache, so as not to upset the bus + * with our loop. + */ + + mfspr r4, SPRN_L1CSR1 + ori r4, r4, 1 + mtspr SPRN_L1CSR1, r4 + isync + + /* Set boot page translation */ + lis r3, 0xf000 + lis r4, (mpc85xx_deep_resume - PAGE_OFFSET)@h + ori r4, r4, (mpc85xx_deep_resume - PAGE_OFFSET)@l + rlwinm r4, r4, 20, 0x000fffff + oris r4, r4, 0x8000 + stw r4, 0x20(r3) + lwz r4, 0x20(r3) /* read-back to flush write */ + twi 0, r4, 0 + isync + + /* Disable the decrementer */ + mfspr r4, SPRN_TCR + rlwinm r4, r4, 0, ~TCR_DIE + mtspr SPRN_TCR, r4 + + mfspr r4, SPRN_TSR + oris r4, r4, TSR_DIS@h + mtspr SPRN_TSR, r4 + + /* set PMRCCR[VRCNT] to wait power stable for 40ms */ + lis r3, 0xf00e + lwz r4, 0x84(r3) + clrlwi r4, r4, 16 + oris r4, r4, 0x12a3 + stw r4, 0x84(r3) + lwz r4, 0x84(r3) + + /* set deep sleep bit in POWMGTSCR */ + lis r3, powmgtreq@ha + lwz r8, powmgtreq@l(r3) + + lis r3, 0xf00e + lwz r4, 0x80(r3) + or r4, r4, r8 + stw r4, 0x80(r3) + lwz r4, 0x80(r3) /* read-back to flush write */ + twi 0, r4, 0 + isync + + mftb r5 +1: /* spin until either we enter deep sleep, or the sleep process is + * aborted due to a pending wakeup event. Wait some time between + * accesses, so we don't flood the bus and prevent the pmc from + * detecting an idle system. + */ + + mftb r4 + subf r7, r5, r4 + cmpwi r7, 1000 + blt 1b + mr r5, r4 + + lwz r6, 0x80(r3) + andis. r6, r6, 0x0010 + bne 1b + b 2f + +2: mfspr r4, SPRN_PIR + andi. r4, r4, 1 +99: bne 99b + + /* Establish a temporary 64MB 0->0 mapping in TLB1[1]. */ + lis r4, 0x1001 + mtspr SPRN_MAS0, r4 + lis r4, 0xc000 + ori r4, r4, 0x0800 + mtspr SPRN_MAS1, r4 + li r4, 0 + mtspr SPRN_MAS2, r4 + li r4, 0x0015 + mtspr SPRN_MAS3, r4 + li r4, 0 + mtspr SPRN_MAS7, r4 + isync + tlbwe + isync + + lis r3, (3f - PAGE_OFFSET)@h + ori r3, r3, (3f - PAGE_OFFSET)@l + mtctr r3 + bctr + + /* Locate the resume vector in the last word of the current page. */ + . = mpc85xx_enter_deep_sleep + 0xffc +mpc85xx_deep_resume: + b 2b + +3: + /* Restore the contents of TLB1[0]. It is assumed that it covers + * the currently executing code and the sleep save area, and that + * it does not alias our temporary mapping (which is at virtual zero). + */ + lis r3, (TLBCAM - PAGE_OFFSET)@h + ori r3, r3, (TLBCAM - PAGE_OFFSET)@l + + lwz r4, 0(r3) + lwz r5, 4(r3) + lwz r6, 8(r3) + lwz r7, 12(r3) + lwz r8, 16(r3) + + mtspr SPRN_MAS0, r4 + mtspr SPRN_MAS1, r5 + mtspr SPRN_MAS2, r6 + mtspr SPRN_MAS3, r7 + mtspr SPRN_MAS7, r8 + + isync + tlbwe + isync + + /* Access the ccsrbase address with TLB1[0] */ + lis r5, ccsrbase_low@ha + lwz r4, ccsrbase_low@l(r5) + lis r5, ccsrbase_high@ha + lwz r3, ccsrbase_high@l(r5) + + /* Use TLB1[15] to map the CCSR at 0xf0000000 */ + lis r5, 0x100f + mtspr SPRN_MAS0, r5 + lis r5, 0xc000 + ori r5, r5, 0x0500 + mtspr SPRN_MAS1, r5 + lis r5, 0xf000 + ori r5, r5, 0x000a + mtspr SPRN_MAS2, r5 + rlwinm r5, r4, 0, 0xfffff000 + ori r5, r5, 0x0005 + mtspr SPRN_MAS3, r5 + mtspr SPRN_MAS7, r3 + isync + tlbwe + isync + + lis r3, 0xf002 /* L2 cache controller at CCSR+0x20000 */ + bl invalidate_enable_L2 + + /* Access the MEM(r10) with TLB1[0] */ + lis r10, mpc85xx_sleep_save_area@h + ori r10, r10, mpc85xx_sleep_save_area@l + + lis r3, 0xf000 + lwz r4, SS_BPTR(r10) + stw r4, 0x20(r3) /* restore BPTR */ + + /* Program shift running space to PAGE_OFFSET */ + mfmsr r3 + lis r4, 1f@h + ori r4, r4, 1f@l + + mtsrr1 r3 + mtsrr0 r4 + rfi + +1: /* Restore the rest of TLB1, in ascending order so that + * the TLB1[1] gets invalidated first. + * + * XXX: It's better to invalidate the temporary mapping + * TLB1[15] for CCSR before restore any TLB1 entry include 0. + */ + lis r4, 0x100f + mtspr SPRN_MAS0, r4 + lis r4, 0 + mtspr SPRN_MAS1, r4 + isync + tlbwe + isync + + lis r3, (TLBCAM + 5*4 - 4)@h + ori r3, r3, (TLBCAM + 5*4 - 4)@l + li r4, 15 + mtctr r4 + +2: + lwz r5, 4(r3) + lwz r6, 8(r3) + lwz r7, 12(r3) + lwz r8, 16(r3) + lwzu r9, 20(r3) + + mtspr SPRN_MAS0, r5 + mtspr SPRN_MAS1, r6 + mtspr SPRN_MAS2, r7 + mtspr SPRN_MAS3, r8 + mtspr SPRN_MAS7, r9 + + isync + tlbwe + isync + bdnz 2b + + lis r10, mpc85xx_sleep_save_area@h + ori r10, r10, mpc85xx_sleep_save_area@l + + lwz r5, SS_HID+0(r10) + lwz r6, SS_HID+4(r10) + + isync + mtspr SPRN_HID0, r5 + isync + + msync + mtspr SPRN_HID1, r6 + isync + + lwz r4, SS_IAC+0(r10) + lwz r5, SS_IAC+4(r10) + lwz r6, SS_DAC+0(r10) + lwz r7, SS_DAC+4(r10) + + mtspr SPRN_IAC1, r4 + mtspr SPRN_IAC2, r5 + mtspr SPRN_DAC1, r6 + mtspr SPRN_DAC2, r7 + + lwz r4, SS_DBCR+0(r10) + lwz r5, SS_DBCR+4(r10) + lwz r6, SS_DBCR+8(r10) + + mtspr SPRN_DBCR0, r4 + mtspr SPRN_DBCR1, r5 + mtspr SPRN_DBCR2, r6 + + lwz r4, SS_PID+0(r10) + lwz r5, SS_PID+4(r10) + lwz r6, SS_PID+8(r10) + + mtspr SPRN_PID0, r4 + mtspr SPRN_PID1, r5 + mtspr SPRN_PID2, r6 + + lwz r4, SS_SPRG+0x00(r10) + lwz r5, SS_SPRG+0x04(r10) + lwz r6, SS_SPRG+0x08(r10) + lwz r7, SS_SPRG+0x0c(r10) + + mtspr SPRN_SPRG0, r4 + mtspr SPRN_SPRG1, r5 + mtspr SPRN_SPRG2, r6 + mtspr SPRN_SPRG3, r7 + + lwz r4, SS_SPRG+0x10(r10) + lwz r5, SS_SPRG+0x14(r10) + lwz r6, SS_SPRG+0x18(r10) + lwz r7, SS_SPRG+0x1c(r10) + + mtspr SPRN_SPRG4, r4 + mtspr SPRN_SPRG5, r5 + mtspr SPRN_SPRG6, r6 + mtspr SPRN_SPRG7, r7 + + lwz r4, SS_IVPR(r10) + mtspr SPRN_IVPR, r4 + + lwz r4, SS_IVOR+0x00(r10) + lwz r5, SS_IVOR+0x04(r10) + lwz r6, SS_IVOR+0x08(r10) + lwz r7, SS_IVOR+0x0c(r10) + + mtspr SPRN_IVOR0, r4 + mtspr SPRN_IVOR1, r5 + mtspr SPRN_IVOR2, r6 + mtspr SPRN_IVOR3, r7 + + lwz r4, SS_IVOR+0x10(r10) + lwz r5, SS_IVOR+0x14(r10) + lwz r6, SS_IVOR+0x18(r10) + lwz r7, SS_IVOR+0x1c(r10) + + mtspr SPRN_IVOR4, r4 + mtspr SPRN_IVOR5, r5 + mtspr SPRN_IVOR6, r6 + mtspr SPRN_IVOR7, r7 + + lwz r4, SS_IVOR+0x20(r10) + lwz r5, SS_IVOR+0x24(r10) + lwz r6, SS_IVOR+0x28(r10) + lwz r7, SS_IVOR+0x2c(r10) + + mtspr SPRN_IVOR8, r4 + mtspr SPRN_IVOR9, r5 + mtspr SPRN_IVOR10, r6 + mtspr SPRN_IVOR11, r7 + + lwz r4, SS_IVOR+0x30(r10) + lwz r5, SS_IVOR+0x34(r10) + lwz r6, SS_IVOR+0x38(r10) + lwz r7, SS_IVOR+0x3c(r10) + + mtspr SPRN_IVOR12, r4 + mtspr SPRN_IVOR13, r5 + mtspr SPRN_IVOR14, r6 + mtspr SPRN_IVOR15, r7 + + lwz r4, SS_IVOR+0x40(r10) + lwz r5, SS_IVOR+0x44(r10) + lwz r6, SS_IVOR+0x48(r10) + lwz r7, SS_IVOR+0x4c(r10) + + mtspr SPRN_IVOR32, r4 + mtspr SPRN_IVOR33, r5 + mtspr SPRN_IVOR34, r6 + mtspr SPRN_IVOR35, r7 + + lwz r4, SS_TCR(r10) + lwz r5, SS_BUCSR(r10) + lwz r6, SS_L1CSR+0(r10) + lwz r7, SS_L1CSR+4(r10) + lwz r8, SS_USPRG+0(r10) + + mtspr SPRN_TCR, r4 + mtspr SPRN_BUCSR, r5 + + msync + isync + mtspr SPRN_L1CSR0, r6 + isync + + mtspr SPRN_L1CSR1, r7 + isync + + mtspr SPRN_USPRG0, r8 + + lmw r12, SS_GPREG(r10) + + lwz r1, SS_SP(r10) + lwz r2, SS_CURRENT(r10) + lwz r4, SS_MSR(r10) + lwz r5, SS_LR(r10) + lwz r6, SS_CR(r10) + + msync + mtmsr r4 + isync + + mtlr r5 + mtcr r6 + + li r4, 0 + mtspr SPRN_TBWL, r4 + + lwz r4, SS_TB+0(r10) + lwz r5, SS_TB+4(r10) + + mtspr SPRN_TBWU, r4 + mtspr SPRN_TBWL, r5 + + lis r3, 1 + mtdec r3 + + blr + +#else /* CONFIG_PPC_E500MC */ + + .section .data + .align 6 +regs_buffer: + .space BUFFER_SIZE + + .section .text +/* + * Save CPU registers + * r3 : the base address of the buffer which stores the values of registers + */ +e5500_cpu_state_save: + /* store the base address to r10 */ + mr r10, r3 + + SAVE_ALL_GPR + SAVE_ALL_SPRG + SAVE_ALL_IVOR + + SAVE_SPR(SPRN_IVPR, BOOKE_IVPR_OFF) + SAVE_SPR(SPRN_PID0, BOOKE_PID0_OFF) + SAVE_SPR(SPRN_EPCR, BOOKE_EPCR_OFF) + SAVE_SPR(SPRN_HID0, BOOKE_HID0_OFF) + SAVE_SPR(SPRN_PIR, BOOKE_PIR_OFF) + SAVE_SPR(SPRN_BUCSR, BOOKE_BUCSR_OFF) +1: + mfspr r5, SPRN_TBRU + mfspr r4, SPRN_TBRL + SAVE_GPR(r5, BOOKE_TBU_OFF) + SAVE_GPR(r4, BOOKE_TBL_OFF) + mfspr r3, SPRN_TBRU + cmpw r3, r5 + bne 1b + + blr + +/* + * Restore CPU registers + * r3 : the base address of the buffer which stores the values of registers + */ +e5500_cpu_state_restore: + /* store the base address to r10 */ + mr r10, r3 + + RESTORE_ALL_GPR + RESTORE_ALL_SPRG + RESTORE_ALL_IVOR + + RESTORE_SPR(SPRN_IVPR, BOOKE_IVPR_OFF) + RESTORE_SPR(SPRN_PID0, BOOKE_PID0_OFF) + RESTORE_SPR(SPRN_EPCR, BOOKE_EPCR_OFF) + RESTORE_SPR(SPRN_HID0, BOOKE_HID0_OFF) + RESTORE_SPR(SPRN_PIR, BOOKE_PIR_OFF) + RESTORE_SPR(SPRN_BUCSR, BOOKE_BUCSR_OFF) + + li r0, 0 + mtspr SPRN_TBWL, r0 + RESTORE_SPR(SPRN_TBWU, BOOKE_TBU_OFF) + RESTORE_SPR(SPRN_TBWL, BOOKE_TBL_OFF) + + blr + +#define CPC_CPCCSR0 0x0 +#define CPC_CPCCSR0_CPCFL 0x800 + +/* + * Flush the CPC cache. + * r3 : the base address of CPC + */ +flush_cpc_cache: + lwz r6, CPC_CPCCSR0(r3) + ori r6, r6, CPC_CPCCSR0_CPCFL + stw r6, CPC_CPCCSR0(r3) + sync + + /* Wait until completing the flush */ +1: lwz r6, CPC_CPCCSR0(r3) + andi. r6, r6, CPC_CPCCSR0_CPCFL + bne 1b + + blr + +/* + * the last stage to enter deep sleep + * + */ + .align 6 +_GLOBAL(fsl_dp_enter_low) +deepsleep_start: + LOAD_REG_ADDR(r9, buf_tmp) + /* save the return address and MSR */ + mflr r8 + PPC_STL r8, 0(r9) + mfmsr r8 + PPC_STL r8, 8(r9) + mfspr r8, SPRN_TCR + PPC_STL r8, 16(r9) + mfcr r8 + PPC_STL r8, 24(r9) + li r8, 0 + mtspr SPRN_TCR, r8 + + /* save the parameters */ + PPC_STL r3, 32(r9) + PPC_STL r4, 40(r9) + PPC_STL r5, 48(r9) + PPC_STL r6, 56(r9) + + LOAD_REG_ADDR(r3, regs_buffer) + bl e5500_cpu_state_save + + /* restore the parameters */ + LOAD_REG_ADDR(r9, buf_tmp) + PPC_LL r31, 32(r9) + PPC_LL r30, 40(r9) + PPC_LL r29, 48(r9) + PPC_LL r28, 56(r9) + + /* flush caches inside CPU */ + LOAD_REG_ADDR(r3, cur_cpu_spec) + PPC_LL r3, 0(r3) + PPC_LL r3, CPU_FLUSH_CACHES(r3) + PPC_LCMPI 0, r3, 0 + beq 6f +#ifdef CONFIG_PPC64 + PPC_LL r3, 0(r3) +#endif + mtctr r3 + bctrl +6: + /* Flush the CPC cache */ +#define CPC_OFFSET 0x10000 + mr r3, r31 + addis r3, r3, CPC_OFFSET@h + bl flush_cpc_cache + + /* prefecth TLB */ +#define CCSR_GPIO1_GPDAT 0x130008 +#define CCSR_GPIO1_GPDAT_29 0x4 + LOAD_REG_IMMEDIATE(r11, CCSR_GPIO1_GPDAT) + add r11, r31, r11 + lwz r10, 0(r11) + +#define CCSR_RCPM_PCPH15SETR 0xe20b4 +#define CCSR_RCPM_PCPH15SETR_CORE0 0x1 + LOAD_REG_IMMEDIATE(r12, CCSR_RCPM_PCPH15SETR) + add r12, r31, r12 + lwz r10, 0(r12) + +#define CCSR_DDR_SDRAM_CFG_2 0x8114 +#define CCSR_DDR_SDRAM_CFG_2_FRC_SR 0x80000000 + LOAD_REG_IMMEDIATE(r13, CCSR_DDR_SDRAM_CFG_2) + add r13, r31, r13 + lwz r10, 0(r13) + +#define DCSR_EPU_EPGCR 0x000 +#define DCSR_EPU_EPGCR_GCE 0x80000000 + li r14, DCSR_EPU_EPGCR + add r14, r30, r14 + lwz r10, 0(r14) + +#define DCSR_EPU_EPECR15 0x33C +#define DCSR_EPU_EPECR15_IC0 0x80000000 + li r15, DCSR_EPU_EPECR15 + add r15, r30, r15 + lwz r10, 0(r15) + +#define CCSR_SCFG_QMIFRSTCR 0xfc40c +#define CCSR_SCFG_QMIFRSTCR_QMIFRST 0x80000000 + LOAD_REG_IMMEDIATE(r16, CCSR_SCFG_QMIFRSTCR) + add r16, r31, r16 + lwz r10, 0(r16) + +/* + * There are two kind of register maps, one for T1040QDS and + * the other for T104xRDB. + */ +#define T104XRDB_CPLD_MISCCSR 0x17 +#define T104XRDB_CPLD_MISCCSR_SLEEPEN 0x40 +#define T1040QDS_QIXIS_PWR_CTL2 0x21 +#define T1040QDS_QIXIS_PWR_CTL2_PCTL 0x2 + li r3, T1040QDS_QIXIS_PWR_CTL2 + PPC_LCMPI 0, r28, T1040QDS_TETRA_FLAG + beq 20f + li r3, T104XRDB_CPLD_MISCCSR +20: add r29, r29, r3 + lbz r10, 0(r29) + sync + + LOAD_REG_ADDR(r8, deepsleep_start) + LOAD_REG_ADDR(r9, deepsleep_end) + + /* prefecth code to cache so that executing code after disable DDR */ +1: icbtls 2, 0, r8 + addi r8, r8, 64 + cmpw r8, r9 + blt 1b + sync + + FSL_DIS_ALL_IRQ + + /* + * Place DDR controller in self refresh mode. + * From here on, can't access DDR any more. + */ + lwz r10, 0(r13) + oris r10, r10, CCSR_DDR_SDRAM_CFG_2_FRC_SR@h + stw r10, 0(r13) + lwz r10, 0(r13) + sync + + DELAY(500) + + /* + * Enable deep sleep signals by write external CPLD/FPGA register. + * The bootloader will disable them when wakeup from deep sleep. + */ + lbz r10, 0(r29) + li r3, T1040QDS_QIXIS_PWR_CTL2_PCTL + PPC_LCMPI 0, r28, T1040QDS_TETRA_FLAG + beq 22f + li r3, T104XRDB_CPLD_MISCCSR_SLEEPEN +22: or r10, r10, r3 + stb r10, 0(r29) + lbz r10, 0(r29) + sync + + /* + * Set GPIO1_29 to lock the signal MCKE down during deep sleep. + * The bootloader will clear it when wakeup. + */ + lwz r10, 0(r11) + ori r10, r10, CCSR_GPIO1_GPDAT_29 + stw r10, 0(r11) + lwz r10, 0(r11) + + DELAY(100) + + /* Reset QMan system bus interface */ + lwz r10, 0(r16) + oris r10, r10, CCSR_SCFG_QMIFRSTCR_QMIFRST@h + stw r10, 0(r16) + lwz r10, 0(r16) + + /* Enable all EPU Counters */ + li r10, 0 + oris r10, r10, DCSR_EPU_EPGCR_GCE@h + stw r10, 0(r14) + lwz r10, 0(r14) + + /* Enable SCU15 to trigger on RCPM Concentrator 0 */ + lwz r10, 0(r15) + oris r10, r10, DCSR_EPU_EPECR15_IC0@h + stw r10, 0(r15) + lwz r10, 0(r15) + + /* put Core0 in PH15 mode, trigger EPU FSM */ + lwz r10, 0(r12) + ori r10, r10, CCSR_RCPM_PCPH15SETR_CORE0 + stw r10, 0(r12) +2: + b 2b + + /* + * Leave some space to prevent prefeching instruction + * beyond deepsleep_end. The space also can be used as heap. + */ +buf_tmp: + .space 128 + .align 6 +deepsleep_end: + + .align 12 +#ifdef CONFIG_PPC32 +_GLOBAL(fsl_booke_deep_sleep_resume) + /* disable interrupts */ + FSL_DIS_ALL_IRQ + +#define ENTRY_DEEPSLEEP_SETUP +#define ENTRY_MAPPING_BOOT_SETUP +#include <../../kernel/fsl_booke_entry_mapping.S> +#undef ENTRY_DEEPSLEEP_SETUP +#undef ENTRY_MAPPING_BOOT_SETUP + + li r3, 0 + mfspr r4, SPRN_PIR + bl call_setup_cpu + + /* Load each CAM entry */ + LOAD_REG_ADDR(r3, tlbcam_index) + lwz r3, 0(r3) + mtctr r3 + li r9, 0 +3: mr r3, r9 + bl loadcam_entry + addi r9, r9, 1 + bdnz 3b + + /* restore cpu registers */ + LOAD_REG_ADDR(r3, regs_buffer) + bl e5500_cpu_state_restore + + /* restore return address */ + LOAD_REG_ADDR(r3, buf_tmp) + lwz r4, 16(r3) + mtspr SPRN_TCR, r4 + lwz r4, 0(r3) + mtlr r4 + lwz r4, 8(r3) + mtmsr r4 + lwz r4, 24(r3) + mtcr r4 + + blr + +#else /* CONFIG_PPC32 */ + +_GLOBAL(fsl_booke_deep_sleep_resume) + /* disable interrupts */ + FSL_DIS_ALL_IRQ + + /* switch to 64-bit mode */ + bl .enable_64b_mode + + /* set TOC pointer */ + bl .relative_toc + + /* setup initial TLBs, switch to kernel space ... */ + bl .start_initialization_book3e + + /* address space changed, set TOC pointer again */ + bl .relative_toc + + /* call a cpu state restore handler */ + LOAD_REG_ADDR(r23, cur_cpu_spec) + ld r23,0(r23) + ld r23,CPU_SPEC_RESTORE(r23) + cmpdi 0,r23,0 + beq 1f + ld r23,0(r23) + mtctr r23 + bctrl +1: + LOAD_REG_ADDR(r3, regs_buffer) + bl e5500_cpu_state_restore + + /* Load each CAM entry */ + LOAD_REG_ADDR(r3, tlbcam_index) + lwz r3, 0(r3) + mtctr r3 + li r0, 0 +3: mr r3, r0 + bl loadcam_entry + addi r0, r0, 1 + bdnz 3b + + /* restore return address */ + LOAD_REG_ADDR(r3, buf_tmp) + ld r4, 16(r3) + mtspr SPRN_TCR, r4 + ld r4, 0(r3) + mtlr r4 + ld r4, 8(r3) + mtmsr r4 + ld r4, 24(r3) + mtcr r4 + + blr + +#endif /* CONFIG_PPC32 */ + +#endif diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c index 720b0c0f03bafd..b099f560712009 100644 --- a/arch/powerpc/platforms/85xx/twr_p102x.c +++ b/arch/powerpc/platforms/85xx/twr_p102x.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include @@ -31,26 +30,12 @@ static void __init twr_p1025_pic_init(void) { struct mpic *mpic; -#ifdef CONFIG_QUICC_ENGINE - struct device_node *np; -#endif - mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU, 0, 256, " OpenPIC "); BUG_ON(mpic == NULL); mpic_init(mpic); - -#ifdef CONFIG_QUICC_ENGINE - np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); - if (np) { - qe_ic_init(np, 0, qe_ic_cascade_low_mpic, - qe_ic_cascade_high_mpic); - of_node_put(np); - } else - pr_err("Could not find qe-ic node\n"); -#endif } /* ************************************************************************ diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig index 07a9d60c618a1c..76965a9e648172 100644 --- a/arch/powerpc/platforms/86xx/Kconfig +++ b/arch/powerpc/platforms/86xx/Kconfig @@ -5,6 +5,7 @@ menuconfig PPC_86xx depends on PPC_BOOK3S_32 select FSL_SOC select ALTIVEC + select FSL_PMC if SUSPEND help The Freescale E600 SoCs have 74xx cores. diff --git a/arch/powerpc/sysdev/fsl_pmc.c b/arch/powerpc/sysdev/fsl_pmc.c index 76896de970ca9f..e72c03d32702c6 100644 --- a/arch/powerpc/sysdev/fsl_pmc.c +++ b/arch/powerpc/sysdev/fsl_pmc.c @@ -16,54 +16,192 @@ #include #include #include +#include +#include + +#include +#include +#include struct pmc_regs { __be32 devdisr; __be32 devdisr2; - __be32 :32; - __be32 :32; - __be32 pmcsr; -#define PMCSR_SLP (1 << 17) + __be32 res1; + __be32 res2; + __be32 powmgtcsr; +#define POWMGTCSR_SLP 0x00020000 +#define POWMGTCSR_DPSLP 0x00100000 +#define POWMGTCSR_LOSSLESS 0x00400000 + __be32 res3[2]; + __be32 pmcdr; }; -static struct device *pmc_dev; static struct pmc_regs __iomem *pmc_regs; +static unsigned int pmc_flag; + +#define PMC_SLEEP 0x1 +#define PMC_DEEP_SLEEP 0x2 +#define PMC_LOSSLESS 0x4 + +/** + * mpc85xx_pmc_set_wake - enable devices as wakeup event source + * @dev: a device affected + * @enable: True to enable event generation; false to disable + * + * This enables the device as a wakeup event source, or disables it. + * + * RETURN VALUE: + * 0 is returned on success. + * -EINVAL is returned if device is not supposed to wake up the system. + * -ENODEV is returned if PMC is unavailable. + * Error code depending on the platform is returned if both the platform and + * the native mechanism fail to enable the generation of wake-up events + */ +int mpc85xx_pmc_set_wake(struct device *dev, bool enable) +{ + int ret = 0; + struct device_node *clk_np; + const u32 *prop; + u32 pmcdr_mask; + + if (!pmc_regs) { + dev_err(dev, "%s: PMC is unavailable\n", __func__); + return -ENODEV; + } + + if (enable && !device_may_wakeup(dev)) + return -EINVAL; + + clk_np = of_parse_phandle(dev->of_node, "fsl,pmc-handle", 0); + if (!clk_np) + return -EINVAL; + + prop = of_get_property(clk_np, "fsl,pmcdr-mask", NULL); + if (!prop) { + ret = -EINVAL; + goto out; + } + pmcdr_mask = be32_to_cpup(prop); + + if (enable) + /* clear to enable clock in low power mode */ + clrbits32(&pmc_regs->pmcdr, pmcdr_mask); + else + setbits32(&pmc_regs->pmcdr, pmcdr_mask); + +out: + of_node_put(clk_np); + return ret; +} +EXPORT_SYMBOL_GPL(mpc85xx_pmc_set_wake); + +/** + * mpc85xx_pmc_set_lossless_ethernet - enable lossless ethernet + * in (deep) sleep mode + * @enable: True to enable event generation; false to disable + */ +void mpc85xx_pmc_set_lossless_ethernet(int enable) +{ + if (pmc_flag & PMC_LOSSLESS) { + if (enable) + setbits32(&pmc_regs->powmgtcsr, POWMGTCSR_LOSSLESS); + else + clrbits32(&pmc_regs->powmgtcsr, POWMGTCSR_LOSSLESS); + } +} +EXPORT_SYMBOL_GPL(mpc85xx_pmc_set_lossless_ethernet); static int pmc_suspend_enter(suspend_state_t state) { - int ret; + int ret = 0; + int result; + + switch (state) { +#ifdef CONFIG_PPC_85xx + case PM_SUSPEND_MEM: +#ifdef CONFIG_SPE + enable_kernel_spe(); +#endif +#ifdef CONFIG_PPC_FPU + enable_kernel_fp(); +#endif + + pr_debug("%s: Entering deep sleep\n", __func__); + + local_irq_disable(); + mpc85xx_enter_deep_sleep(get_immrbase(), POWMGTCSR_DPSLP); + + pr_debug("%s: Resumed from deep sleep\n", __func__); + break; +#endif - setbits32(&pmc_regs->pmcsr, PMCSR_SLP); - /* At this point, the CPU is asleep. */ + case PM_SUSPEND_STANDBY: + local_irq_disable(); + flush_dcache_L1(); - /* Upon resume, wait for SLP bit to be clear. */ - ret = spin_event_timeout((in_be32(&pmc_regs->pmcsr) & PMCSR_SLP) == 0, - 10000, 10) ? 0 : -ETIMEDOUT; - if (ret) - dev_err(pmc_dev, "tired waiting for SLP bit to clear\n"); + setbits32(&pmc_regs->powmgtcsr, POWMGTCSR_SLP); + /* At this point, the CPU is asleep. */ + + /* Upon resume, wait for SLP bit to be clear. */ + result = spin_event_timeout( + (in_be32(&pmc_regs->powmgtcsr) & POWMGTCSR_SLP) == 0, + 10000, 10); + if (!result) { + pr_err("%s: timeout waiting for SLP bit " + "to be cleared\n", __func__); + ret = -ETIMEDOUT; + } + break; + + default: + ret = -EINVAL; + + } return ret; } static int pmc_suspend_valid(suspend_state_t state) { - if (state != PM_SUSPEND_STANDBY) - return 0; - return 1; + set_pm_suspend_state(state); + + if (((pmc_flag & PMC_SLEEP) && (state == PM_SUSPEND_STANDBY)) || + ((pmc_flag & PMC_DEEP_SLEEP) && (state == PM_SUSPEND_MEM))) + return 1; + + set_pm_suspend_state(PM_SUSPEND_ON); + return 0; +} + +static void pmc_suspend_end(void) +{ + set_pm_suspend_state(PM_SUSPEND_ON); } static const struct platform_suspend_ops pmc_suspend_ops = { .valid = pmc_suspend_valid, .enter = pmc_suspend_enter, + .end = pmc_suspend_end, }; -static int pmc_probe(struct platform_device *ofdev) +static int pmc_probe(struct platform_device *pdev) { - pmc_regs = of_iomap(ofdev->dev.of_node, 0); + struct device_node *np = pdev->dev.of_node; + + pmc_regs = of_iomap(np, 0); if (!pmc_regs) return -ENOMEM; - pmc_dev = &ofdev->dev; + pmc_flag = PMC_SLEEP; + if (of_device_is_compatible(np, "fsl,mpc8536-pmc")) + pmc_flag |= PMC_DEEP_SLEEP; + + if (of_device_is_compatible(np, "fsl,p1022-pmc")) + pmc_flag |= PMC_DEEP_SLEEP | PMC_LOSSLESS; + suspend_set_ops(&pmc_suspend_ops); + set_pm_suspend_state(PM_SUSPEND_ON); + + pr_info("Freescale PMC driver\n"); return 0; } diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c index 90ad1616160430..21af6d5c075a84 100644 --- a/arch/powerpc/sysdev/fsl_soc.c +++ b/arch/powerpc/sysdev/fsl_soc.c @@ -42,6 +42,37 @@ extern void init_fcc_ioports(struct fs_platform_info*); extern void init_fec_ioports(struct fs_platform_info*); extern void init_smc_ioports(struct fs_uart_platform_info*); static phys_addr_t immrbase = -1; +static phys_addr_t dcsrbase = -1; + +phys_addr_t get_dcsrbase(void) +{ + struct device_node *np; + const __be32 *prop; + int size; + u32 naddr; + + if (dcsrbase != -1) + return dcsrbase; + + np = of_find_compatible_node(NULL, NULL, "fsl,dcsr"); + if (!np) + return -1; + + prop = of_get_property(np, "#address-cells", &size); + if (prop && size == 4) + naddr = be32_to_cpup(prop); + else + naddr = 2; + + prop = of_get_property(np, "ranges", NULL); + if (prop) + dcsrbase = of_translate_address(np, prop + naddr); + + of_node_put(np); + + return dcsrbase; +} +EXPORT_SYMBOL(get_dcsrbase); phys_addr_t get_immrbase(void) { diff --git a/arch/powerpc/sysdev/fsl_soc.h b/arch/powerpc/sysdev/fsl_soc.h index db11b06eb38fdc..674ed672bd62a4 100644 --- a/arch/powerpc/sysdev/fsl_soc.h +++ b/arch/powerpc/sysdev/fsl_soc.h @@ -7,6 +7,7 @@ struct spi_device; +extern phys_addr_t get_dcsrbase(void); extern phys_addr_t get_immrbase(void); #if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) extern u32 get_brgfreq(void); @@ -44,5 +45,22 @@ extern struct platform_diu_data_ops diu_ops; void __noreturn fsl_hv_restart(char *cmd); void __noreturn fsl_hv_halt(void); +/* + * Cast the ccsrbar to 64-bit parameter so that the assembly + * code can be compatible with both 32-bit & 36-bit. + */ +extern void mpc85xx_enter_deep_sleep(u64 ccsrbar, u32 powmgtreq); + +#ifdef CONFIG_FSL_PMC +int mpc85xx_pmc_set_wake(struct device *dev, bool enable); +void mpc85xx_pmc_set_lossless_ethernet(int enable); +#else +static inline int mpc85xx_pmc_set_wake(struct device *dev, bool enable) +{ + return -ENODEV; +} +#define mpc85xx_pmc_set_lossless_ethernet(enable) do { } while (0) +#endif + #endif #endif diff --git a/block/blk-map.c b/block/blk-map.c index b0790268ed9d9a..8b56d551f78ae0 100644 --- a/block/blk-map.c +++ b/block/blk-map.c @@ -205,6 +205,12 @@ int blk_rq_unmap_user(struct bio *bio) } EXPORT_SYMBOL(blk_rq_unmap_user); +#ifdef CONFIG_AHCI_IMX +extern void *sg_io_buffer_hack; +#else +#define sg_io_buffer_hack NULL +#endif + /** * blk_rq_map_kern - map kernel data to a request, for passthrough requests * @q: request queue where request should be inserted @@ -232,7 +238,14 @@ int blk_rq_map_kern(struct request_queue *q, struct request *rq, void *kbuf, if (!len || !kbuf) return -EINVAL; - do_copy = !blk_rq_aligned(q, addr, len) || object_is_on_stack(kbuf); +#ifdef CONFIG_AHCI_IMX + if (kbuf == sg_io_buffer_hack) + do_copy = 0; + else +#endif + do_copy = !blk_rq_aligned(q, addr, len) + || object_is_on_stack(kbuf); + if (do_copy) bio = bio_copy_kern(q, kbuf, len, gfp_mask, reading); else diff --git a/block/scsi_ioctl.c b/block/scsi_ioctl.c index f5e0ad65e86acf..6c894f178e059d 100644 --- a/block/scsi_ioctl.c +++ b/block/scsi_ioctl.c @@ -239,6 +239,12 @@ static int blk_fill_sghdr_rq(struct request_queue *q, struct request *rq, return 0; } +#ifdef CONFIG_AHCI_IMX +extern void *sg_io_buffer_hack; +#else +#define sg_io_buffer_hack NULL +#endif + static int blk_complete_sghdr_rq(struct request *rq, struct sg_io_hdr *hdr, struct bio *bio) { @@ -268,7 +274,12 @@ static int blk_complete_sghdr_rq(struct request *rq, struct sg_io_hdr *hdr, ret = -EFAULT; } - r = blk_rq_unmap_user(bio); + if (sg_io_buffer_hack && !hdr->iovec_count) + r = copy_to_user(hdr->dxferp, sg_io_buffer_hack, + hdr->dxfer_len); + else + r = blk_rq_unmap_user(bio); + if (!ret) ret = r; @@ -292,6 +303,9 @@ static int sg_io(struct request_queue *q, struct gendisk *bd_disk, if (hdr->dxfer_len > (queue_max_hw_sectors(q) << 9)) return -EIO; + if (sg_io_buffer_hack && hdr->dxfer_len > 0x10000) + return -EIO; + if (hdr->dxfer_len) switch (hdr->dxfer_direction) { default: @@ -338,9 +352,14 @@ static int sg_io(struct request_queue *q, struct gendisk *bd_disk, ret = blk_rq_map_user_iov(q, rq, NULL, &i, GFP_KERNEL); kfree(iov); - } else if (hdr->dxfer_len) - ret = blk_rq_map_user(q, rq, NULL, hdr->dxferp, hdr->dxfer_len, - GFP_KERNEL); + } else if (hdr->dxfer_len) { + if (sg_io_buffer_hack) + ret = blk_rq_map_kern(q, rq, sg_io_buffer_hack, + hdr->dxfer_len, GFP_KERNEL); + else + ret = blk_rq_map_user(q, rq, NULL, hdr->dxferp, + hdr->dxfer_len, GFP_KERNEL); + } if (ret) goto out_free_cdb; diff --git a/crypto/Kconfig b/crypto/Kconfig index b2cc0ad3792adc..871491a52e7dad 100644 --- a/crypto/Kconfig +++ b/crypto/Kconfig @@ -342,6 +342,26 @@ config CRYPTO_ECHAINIV a sequence number xored with a salt. This is the default algorithm for CBC. +config CRYPTO_TLS + tristate "TLS support" + select CRYPTO_AEAD + select CRYPTO_BLKCIPHER + select CRYPTO_MANAGER + select CRYPTO_HASH + select CRYPTO_NULL + select CRYPTO_AUTHENC + help + Support for TLS 1.0 record encryption and decryption + + This module adds support for encryption/decryption of TLS 1.0 frames + using blockcipher algorithms. The name of the resulting algorithm is + "tls10(hmac(),cbc())". By default, the generic base + algorithms are used (e.g. aes-generic, sha1-generic), but hardware + accelerated versions will be used automatically if available. + + User-space applications (OpenSSL, GnuTLS) can offload TLS 1.0 + operations through AF_ALG or cryptodev interfaces + comment "Block modes" config CRYPTO_CBC diff --git a/crypto/Makefile b/crypto/Makefile index aa740c8492b9d1..7feffa47ebae70 100644 --- a/crypto/Makefile +++ b/crypto/Makefile @@ -143,6 +143,7 @@ obj-$(CONFIG_CRYPTO_CRC32) += crc32_generic.o obj-$(CONFIG_CRYPTO_CRCT10DIF) += crct10dif_common.o crct10dif_generic.o obj-$(CONFIG_CRYPTO_AUTHENC) += authenc.o authencesn.o obj-$(CONFIG_CRYPTO_LZO) += lzo.o lzo-rle.o +obj-$(CONFIG_CRYPTO_TLS) += tls.o obj-$(CONFIG_CRYPTO_LZ4) += lz4.o obj-$(CONFIG_CRYPTO_LZ4HC) += lz4hc.o obj-$(CONFIG_CRYPTO_XXHASH) += xxhash_generic.o diff --git a/crypto/tcrypt.c b/crypto/tcrypt.c index 83ad0b1fab30a5..633e8075d22c55 100644 --- a/crypto/tcrypt.c +++ b/crypto/tcrypt.c @@ -71,9 +71,8 @@ static char *check[] = { "cast6", "arc4", "michael_mic", "deflate", "crc32c", "tea", "xtea", "khazad", "wp512", "wp384", "wp256", "tnepres", "xeta", "fcrypt", "camellia", "seed", "salsa20", "rmd128", "rmd160", "rmd256", "rmd320", - "lzo", "lzo-rle", "cts", "sha3-224", "sha3-256", "sha3-384", - "sha3-512", "streebog256", "streebog512", - NULL + "lzo", "lzo-rle", "cts", "zlib", "sha3-224", "sha3-256", "sha3-384", + "sha3-512", "streebog256", "streebog512", "rsa", NULL }; static u32 block_sizes[] = { 16, 64, 256, 1024, 1472, 8192, 0 }; @@ -257,7 +256,7 @@ static void test_mb_aead_speed(const char *algo, int enc, int secs, unsigned int i, j, iv_len; const char *key; const char *e; - void *assoc; + void *assoc, *assoc_out; u32 *b_size; char *iv; int ret; @@ -377,6 +376,8 @@ static void test_mb_aead_speed(const char *algo, int enc, int secs, assoc = cur->axbuf[0]; memset(assoc, 0xff, aad_size); + assoc_out = cur->axbuf[1]; + memset(assoc_out, 0xff, aad_size); sg_init_aead(cur->sg, cur->xbuf, *b_size + (enc ? 0 : authsize), @@ -384,7 +385,7 @@ static void test_mb_aead_speed(const char *algo, int enc, int secs, sg_init_aead(cur->sgout, cur->xoutbuf, *b_size + (enc ? authsize : 0), - assoc, aad_size); + assoc_out, aad_size); aead_request_set_ad(cur->req, aad_size); @@ -402,6 +403,9 @@ static void test_mb_aead_speed(const char *algo, int enc, int secs, ret); break; } + + memset(assoc, 0xff, aad_size); + memset(assoc_out, 0xff, aad_size); } aead_request_set_crypt(cur->req, cur->sg, @@ -528,7 +532,7 @@ static void test_aead_speed(const char *algo, int enc, unsigned int secs, struct scatterlist *sg; struct scatterlist *sgout; const char *e; - void *assoc; + void *assoc, *assoc_out; char *iv; char *xbuf[XBUFSIZE]; char *xoutbuf[XBUFSIZE]; @@ -591,6 +595,8 @@ static void test_aead_speed(const char *algo, int enc, unsigned int secs, do { assoc = axbuf[0]; memset(assoc, 0xff, aad_size); + assoc_out = axbuf[1]; + memset(assoc_out, 0xff, aad_size); if ((*keysize + *b_size) > TVMEMSIZE * PAGE_SIZE) { pr_err("template (%u) too big for tvmem (%lu)\n", @@ -630,7 +636,7 @@ static void test_aead_speed(const char *algo, int enc, unsigned int secs, assoc, aad_size); sg_init_aead(sgout, xoutbuf, - *b_size + (enc ? authsize : 0), assoc, + *b_size + (enc ? authsize : 0), assoc_out, aad_size); aead_request_set_ad(req, aad_size); @@ -652,6 +658,9 @@ static void test_aead_speed(const char *algo, int enc, unsigned int secs, ret); break; } + + memset(assoc, 0xff, aad_size); + memset(assoc_out, 0xff, aad_size); } aead_request_set_crypt(req, sg, sgout, @@ -1983,6 +1992,10 @@ static int do_test(const char *alg, u32 type, u32 mask, int m, u32 num_mb) ret += tcrypt_test("hmac(streebog512)"); break; + case 117: + ret += tcrypt_test("rsa"); + break; + case 150: ret += tcrypt_test("ansi_cprng"); break; @@ -2049,6 +2062,9 @@ static int do_test(const char *alg, u32 type, u32 mask, int m, u32 num_mb) ret += tcrypt_test("cbc(sm4)"); ret += tcrypt_test("ctr(sm4)"); break; + case 192: + ret += tcrypt_test("tls10(hmac(sha1),cbc(aes))"); + break; case 200: test_cipher_speed("ecb(aes)", ENCRYPT, sec, NULL, 0, speed_template_16_24_32); diff --git a/crypto/testmgr.c b/crypto/testmgr.c index 7473c5bc06b1af..a8b7fb608e2ed6 100644 --- a/crypto/testmgr.c +++ b/crypto/testmgr.c @@ -111,6 +111,13 @@ struct drbg_test_suite { unsigned int count; }; +struct tls_test_suite { + struct { + struct tls_testvec *vecs; + unsigned int count; + } enc, dec; +}; + struct akcipher_test_suite { const struct akcipher_testvec *vecs; unsigned int count; @@ -135,6 +142,7 @@ struct alg_test_desc { struct hash_test_suite hash; struct cprng_test_suite cprng; struct drbg_test_suite drbg; + struct tls_test_suite tls; struct akcipher_test_suite akcipher; struct kpp_test_suite kpp; } suite; @@ -2294,6 +2302,227 @@ static int test_aead(const char *driver, int enc, return 0; } +static int __test_tls(struct crypto_aead *tfm, int enc, + struct tls_testvec *template, unsigned int tcount, + const bool diff_dst) +{ + const char *algo = crypto_tfm_alg_driver_name(crypto_aead_tfm(tfm)); + unsigned int i, k, authsize; + char *q; + struct aead_request *req; + struct scatterlist *sg; + struct scatterlist *sgout; + const char *e, *d; + struct crypto_wait wait; + void *input; + void *output; + void *assoc; + char *iv; + char *key; + char *xbuf[XBUFSIZE]; + char *xoutbuf[XBUFSIZE]; + char *axbuf[XBUFSIZE]; + int ret = -ENOMEM; + + if (testmgr_alloc_buf(xbuf)) + goto out_noxbuf; + + if (diff_dst && testmgr_alloc_buf(xoutbuf)) + goto out_nooutbuf; + + if (testmgr_alloc_buf(axbuf)) + goto out_noaxbuf; + + iv = kzalloc(MAX_IVLEN, GFP_KERNEL); + if (!iv) + goto out_noiv; + + key = kzalloc(MAX_KEYLEN, GFP_KERNEL); + if (!key) + goto out_nokey; + + sg = kmalloc(sizeof(*sg) * 8 * (diff_dst ? 2 : 1), GFP_KERNEL); + if (!sg) + goto out_nosg; + + sgout = sg + 8; + + d = diff_dst ? "-ddst" : ""; + e = enc ? "encryption" : "decryption"; + + crypto_init_wait(&wait); + + req = aead_request_alloc(tfm, GFP_KERNEL); + if (!req) { + pr_err("alg: tls%s: Failed to allocate request for %s\n", + d, algo); + goto out; + } + + aead_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, + crypto_req_done, &wait); + + for (i = 0; i < tcount; i++) { + input = xbuf[0]; + assoc = axbuf[0]; + + ret = -EINVAL; + if (WARN_ON(template[i].ilen > PAGE_SIZE || + template[i].alen > PAGE_SIZE)) + goto out; + + memcpy(assoc, template[i].assoc, template[i].alen); + memcpy(input, template[i].input, template[i].ilen); + + if (template[i].iv) + memcpy(iv, template[i].iv, MAX_IVLEN); + else + memset(iv, 0, MAX_IVLEN); + + crypto_aead_clear_flags(tfm, ~0); + + if (template[i].klen > MAX_KEYLEN) { + pr_err("alg: aead%s: setkey failed on test %d for %s: key size %d > %d\n", + d, i, algo, template[i].klen, MAX_KEYLEN); + ret = -EINVAL; + goto out; + } + memcpy(key, template[i].key, template[i].klen); + + ret = crypto_aead_setkey(tfm, key, template[i].klen); + if ((!ret) == template[i].fail) { + pr_err("alg: tls%s: setkey failed on test %d for %s: flags=%x\n", + d, i, algo, crypto_aead_get_flags(tfm)); + goto out; + } else if (ret) + continue; + + authsize = 20; + ret = crypto_aead_setauthsize(tfm, authsize); + if (ret) { + pr_err("alg: aead%s: Failed to set authsize to %u on test %d for %s\n", + d, authsize, i, algo); + goto out; + } + + k = !!template[i].alen; + sg_init_table(sg, k + 1); + sg_set_buf(&sg[0], assoc, template[i].alen); + sg_set_buf(&sg[k], input, (enc ? template[i].rlen : + template[i].ilen)); + output = input; + + if (diff_dst) { + sg_init_table(sgout, k + 1); + sg_set_buf(&sgout[0], assoc, template[i].alen); + + output = xoutbuf[0]; + sg_set_buf(&sgout[k], output, + (enc ? template[i].rlen : template[i].ilen)); + } + + aead_request_set_crypt(req, sg, (diff_dst) ? sgout : sg, + template[i].ilen, iv); + + aead_request_set_ad(req, template[i].alen); + + ret = crypto_wait_req(enc ? crypto_aead_encrypt(req) + : crypto_aead_decrypt(req), &wait); + + switch (ret) { + case 0: + if (template[i].novrfy) { + /* verification was supposed to fail */ + pr_err("alg: tls%s: %s failed on test %d for %s: ret was 0, expected -EBADMSG\n", + d, e, i, algo); + /* so really, we got a bad message */ + ret = -EBADMSG; + goto out; + } + break; + case -EBADMSG: + /* verification failure was expected */ + if (template[i].novrfy) + continue; + /* fall through */ + default: + pr_err("alg: tls%s: %s failed on test %d for %s: ret=%d\n", + d, e, i, algo, -ret); + goto out; + } + + q = output; + if (memcmp(q, template[i].result, template[i].rlen)) { + pr_err("alg: tls%s: Test %d failed on %s for %s\n", + d, i, e, algo); + hexdump(q, template[i].rlen); + pr_err("should be:\n"); + hexdump(template[i].result, template[i].rlen); + ret = -EINVAL; + goto out; + } + } + +out: + aead_request_free(req); + + kfree(sg); +out_nosg: + kfree(key); +out_nokey: + kfree(iv); +out_noiv: + testmgr_free_buf(axbuf); +out_noaxbuf: + if (diff_dst) + testmgr_free_buf(xoutbuf); +out_nooutbuf: + testmgr_free_buf(xbuf); +out_noxbuf: + return ret; +} + +static int test_tls(struct crypto_aead *tfm, int enc, + struct tls_testvec *template, unsigned int tcount) +{ + int ret; + /* test 'dst == src' case */ + ret = __test_tls(tfm, enc, template, tcount, false); + if (ret) + return ret; + /* test 'dst != src' case */ + return __test_tls(tfm, enc, template, tcount, true); +} + +static int alg_test_tls(const struct alg_test_desc *desc, const char *driver, + u32 type, u32 mask) +{ + struct crypto_aead *tfm; + int err = 0; + + tfm = crypto_alloc_aead(driver, type, mask); + if (IS_ERR(tfm)) { + pr_err("alg: aead: Failed to load transform for %s: %ld\n", + driver, PTR_ERR(tfm)); + return PTR_ERR(tfm); + } + + if (desc->suite.tls.enc.vecs) { + err = test_tls(tfm, ENCRYPT, desc->suite.tls.enc.vecs, + desc->suite.tls.enc.count); + if (err) + goto out; + } + + if (!err && desc->suite.tls.dec.vecs) + err = test_tls(tfm, DECRYPT, desc->suite.tls.dec.vecs, + desc->suite.tls.dec.count); + +out: + crypto_free_aead(tfm); + return err; +} + static int alg_test_aead(const struct alg_test_desc *desc, const char *driver, u32 type, u32 mask) { @@ -5011,6 +5240,15 @@ static const struct alg_test_desc alg_test_descs[] = { .suite = { .hash = __VECS(tgr192_tv_template) } + }, { + .alg = "tls10(hmac(sha1),cbc(aes))", + .test = alg_test_tls, + .suite = { + .tls = { + .enc = __VECS(tls_enc_tv_template), + .dec = __VECS(tls_dec_tv_template) + } + } }, { .alg = "vmac64(aes)", .test = alg_test_hash, diff --git a/crypto/testmgr.h b/crypto/testmgr.h index ef7d21f39d4a94..b98df22249bee0 100644 --- a/crypto/testmgr.h +++ b/crypto/testmgr.h @@ -21,7 +21,12 @@ #define _CRYPTO_TESTMGR_H #include +#include +#define MAX_DIGEST_SIZE 64 +#define MAX_TAP 8 + +#define MAX_KEYLEN 160 #define MAX_IVLEN 32 /* @@ -140,6 +145,20 @@ struct drbg_testvec { size_t expectedlen; }; +struct tls_testvec { + char *key; /* wrapped keys for encryption and authentication */ + char *iv; /* initialization vector */ + char *input; /* input data */ + char *assoc; /* associated data: seq num, type, version, input len */ + char *result; /* result data */ + unsigned char fail; /* the test failure is expected */ + unsigned char novrfy; /* dec verification failure expected */ + unsigned char klen; /* key length */ + unsigned short ilen; /* input data length */ + unsigned short alen; /* associated data length */ + unsigned short rlen; /* result length */ +}; + struct akcipher_testvec { const unsigned char *key; const unsigned char *params; @@ -170,6 +189,211 @@ struct kpp_testvec { static const char zeroed_string[48]; +/* + * TLS1.0 synthetic test vectors + */ +static struct tls_testvec tls_enc_tv_template[] = { + { +#ifdef __LITTLE_ENDIAN + .key = "\x08\x00" /* rta length */ + "\x01\x00" /* rta type */ +#else + .key = "\x00\x08" /* rta length */ + "\x00\x01" /* rta type */ +#endif + "\x00\x00\x00\x10" /* enc key length */ + "authenticationkey20benckeyis16_bytes", + .klen = 8 + 20 + 16, + .iv = "iv0123456789abcd", + .input = "Single block msg", + .ilen = 16, + .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07" + "\x00\x03\x01\x00\x10", + .alen = 13, + .result = "\xd5\xac\xb\xd2\xac\xad\x3f\xb1" + "\x59\x79\x1e\x91\x5f\x52\x14\x9c" + "\xc0\x75\xd8\x4c\x97\x0f\x07\x73" + "\xdc\x89\x47\x49\x49\xcb\x30\x6b" + "\x1b\x45\x23\xa1\xd0\x51\xcf\x02" + "\x2e\xa8\x5d\xa0\xfe\xca\x82\x61", + .rlen = 16 + 20 + 12, + }, { +#ifdef __LITTLE_ENDIAN + .key = "\x08\x00" /* rta length */ + "\x01\x00" /* rta type */ +#else + .key = "\x00\x08" /* rta length */ + "\x00\x01" /* rta type */ +#endif + "\x00\x00\x00\x10" /* enc key length */ + "authenticationkey20benckeyis16_bytes", + .klen = 8 + 20 + 16, + .iv = "iv0123456789abcd", + .input = "", + .ilen = 0, + .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07" + "\x00\x03\x01\x00\x00", + .alen = 13, + .result = "\x58\x2a\x11\xc\x86\x8e\x4b\x67" + "\x2d\x16\x26\x1a\xac\x4b\xe2\x1a" + "\xe9\x6a\xcc\x4d\x6f\x79\x8a\x45" + "\x1f\x4e\x27\xf2\xa7\x59\xb4\x5a", + .rlen = 20 + 12, + }, { +#ifdef __LITTLE_ENDIAN + .key = "\x08\x00" /* rta length */ + "\x01\x00" /* rta type */ +#else + .key = "\x00\x08" /* rta length */ + "\x00\x01" /* rta type */ +#endif + "\x00\x00\x00\x10" /* enc key length */ + "authenticationkey20benckeyis16_bytes", + .klen = 8 + 20 + 16, + .iv = "iv0123456789abcd", + .input = "285 bytes plaintext285 bytes plaintext285 bytes" + " plaintext285 bytes plaintext285 bytes plaintext285" + " bytes plaintext285 bytes plaintext285 bytes" + " plaintext285 bytes plaintext285 bytes plaintext285" + " bytes plaintext285 bytes plaintext285 bytes" + " plaintext285 bytes plaintext285 bytes plaintext285" + " bytes plaintext285 bytes plaintext", + .ilen = 285, + .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07" + "\x00\x03\x01\x01\x1d", + .alen = 13, + .result = "\x80\x23\x82\x44\x14\x2a\x1d\x94\xc\xc2\x1d\xd" + "\x3a\x32\x89\x4c\x57\x30\xa8\x89\x76\x46\xcc\x90" + "\x1d\x88\xb8\xa6\x1a\x58\xe\x2d\xeb\x2c\xc7\x3a" + "\x52\x4e\xdb\xb3\x1e\x83\x11\xf5\x3c\xce\x6e\x94" + "\xd3\x26\x6a\x9a\xd\xbd\xc7\x98\xb9\xb3\x3a\x51" + "\x1e\x4\x84\x8a\x8f\x54\x9a\x51\x69\x9c\xce\x31" + "\x8d\x5d\x8b\xee\x5f\x70\xc\xc9\xb8\x50\x54\xf8" + "\xb2\x4a\x7a\xcd\xeb\x7a\x82\x81\xc6\x41\xc8\x50" + "\x91\x8d\xc8\xed\xcd\x40\x8f\x55\xd1\xec\xc9\xac" + "\x15\x18\xf9\x20\xa0\xed\x18\xa1\xe3\x56\xe3\x14" + "\xe5\xe8\x66\x63\x20\xed\xe4\x62\x9d\xa3\xa4\x1d" + "\x81\x89\x18\xf2\x36\xae\xc8\x8a\x2b\xbc\xc3\xb8" + "\x80\xf\x97\x21\x36\x39\x8\x84\x23\x18\x9e\x9c" + "\x72\x32\x75\x2d\x2e\xf9\x60\xb\xe8\xcc\xd9\x74" + "\x4\x1b\x8e\x99\xc1\x94\xee\xd0\xac\x4e\xfc\x7e" + "\xf1\x96\xb3\xe7\x14\xb8\xf2\xc\x25\x97\x82\x6b" + "\xbd\x0\x65\xab\x5c\xe3\x16\xfb\x68\xef\xea\x9d" + "\xff\x44\x1d\x2a\x44\xf5\xc8\x56\x77\xb7\xbf\x13" + "\xc8\x54\xdb\x92\xfe\x16\x4c\xbe\x18\xe9\xb\x8d" + "\xb\xd4\x43\x58\x43\xaa\xf4\x3\x80\x97\x62\xd5" + "\xdf\x3c\x28\xaa\xee\x48\x4b\x55\x41\x1b\x31\x2" + "\xbe\xa0\x1c\xbd\xb7\x22\x2a\xe5\x53\x72\x73\x20" + "\x44\x4f\xe6\x1\x2b\x34\x33\x11\x7d\xfb\x10\xc1" + "\x66\x7c\xa6\xf4\x48\x36\x5e\x2\xda\x41\x4b\x3e" + "\xe7\x80\x17\x17\xce\xf1\x3e\x6a\x8e\x26\xf3\xb7" + "\x2b\x85\xd\x31\x8d\xba\x6c\x22\xb4\x28\x55\x7e" + "\x2a\x9e\x26\xf1\x3d\x21\xac\x65", + .rlen = 285 + 20 + 15, + } +}; + +static struct tls_testvec tls_dec_tv_template[] = { + { +#ifdef __LITTLE_ENDIAN + .key = "\x08\x00" /* rta length */ + "\x01\x00" /* rta type */ +#else + .key = "\x00\x08" /* rta length */ + "\x00\x01" /* rta type */ +#endif + "\x00\x00\x00\x10" /* enc key length */ + "authenticationkey20benckeyis16_bytes", + .klen = 8 + 20 + 16, + .iv = "iv0123456789abcd", + .input = "\xd5\xac\xb\xd2\xac\xad\x3f\xb1" + "\x59\x79\x1e\x91\x5f\x52\x14\x9c" + "\xc0\x75\xd8\x4c\x97\x0f\x07\x73" + "\xdc\x89\x47\x49\x49\xcb\x30\x6b" + "\x1b\x45\x23\xa1\xd0\x51\xcf\x02" + "\x2e\xa8\x5d\xa0\xfe\xca\x82\x61", + .ilen = 16 + 20 + 12, + .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07" + "\x00\x03\x01\x00\x30", + .alen = 13, + .result = "Single block msg", + .rlen = 16, + }, { +#ifdef __LITTLE_ENDIAN + .key = "\x08\x00" /* rta length */ + "\x01\x00" /* rta type */ +#else + .key = "\x00\x08" /* rta length */ + "\x00\x01" /* rta type */ +#endif + "\x00\x00\x00\x10" /* enc key length */ + "authenticationkey20benckeyis16_bytes", + .klen = 8 + 20 + 16, + .iv = "iv0123456789abcd", + .input = "\x58\x2a\x11\xc\x86\x8e\x4b\x67" + "\x2d\x16\x26\x1a\xac\x4b\xe2\x1a" + "\xe9\x6a\xcc\x4d\x6f\x79\x8a\x45" + "\x1f\x4e\x27\xf2\xa7\x59\xb4\x5a", + .ilen = 20 + 12, + .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07" + "\x00\x03\x01\x00\x20", + .alen = 13, + .result = "", + .rlen = 0, + }, { +#ifdef __LITTLE_ENDIAN + .key = "\x08\x00" /* rta length */ + "\x01\x00" /* rta type */ +#else + .key = "\x00\x08" /* rta length */ + "\x00\x01" /* rta type */ +#endif + "\x00\x00\x00\x10" /* enc key length */ + "authenticationkey20benckeyis16_bytes", + .klen = 8 + 20 + 16, + .iv = "iv0123456789abcd", + .input = "\x80\x23\x82\x44\x14\x2a\x1d\x94\xc\xc2\x1d\xd" + "\x3a\x32\x89\x4c\x57\x30\xa8\x89\x76\x46\xcc\x90" + "\x1d\x88\xb8\xa6\x1a\x58\xe\x2d\xeb\x2c\xc7\x3a" + "\x52\x4e\xdb\xb3\x1e\x83\x11\xf5\x3c\xce\x6e\x94" + "\xd3\x26\x6a\x9a\xd\xbd\xc7\x98\xb9\xb3\x3a\x51" + "\x1e\x4\x84\x8a\x8f\x54\x9a\x51\x69\x9c\xce\x31" + "\x8d\x5d\x8b\xee\x5f\x70\xc\xc9\xb8\x50\x54\xf8" + "\xb2\x4a\x7a\xcd\xeb\x7a\x82\x81\xc6\x41\xc8\x50" + "\x91\x8d\xc8\xed\xcd\x40\x8f\x55\xd1\xec\xc9\xac" + "\x15\x18\xf9\x20\xa0\xed\x18\xa1\xe3\x56\xe3\x14" + "\xe5\xe8\x66\x63\x20\xed\xe4\x62\x9d\xa3\xa4\x1d" + "\x81\x89\x18\xf2\x36\xae\xc8\x8a\x2b\xbc\xc3\xb8" + "\x80\xf\x97\x21\x36\x39\x8\x84\x23\x18\x9e\x9c" + "\x72\x32\x75\x2d\x2e\xf9\x60\xb\xe8\xcc\xd9\x74" + "\x4\x1b\x8e\x99\xc1\x94\xee\xd0\xac\x4e\xfc\x7e" + "\xf1\x96\xb3\xe7\x14\xb8\xf2\xc\x25\x97\x82\x6b" + "\xbd\x0\x65\xab\x5c\xe3\x16\xfb\x68\xef\xea\x9d" + "\xff\x44\x1d\x2a\x44\xf5\xc8\x56\x77\xb7\xbf\x13" + "\xc8\x54\xdb\x92\xfe\x16\x4c\xbe\x18\xe9\xb\x8d" + "\xb\xd4\x43\x58\x43\xaa\xf4\x3\x80\x97\x62\xd5" + "\xdf\x3c\x28\xaa\xee\x48\x4b\x55\x41\x1b\x31\x2" + "\xbe\xa0\x1c\xbd\xb7\x22\x2a\xe5\x53\x72\x73\x20" + "\x44\x4f\xe6\x1\x2b\x34\x33\x11\x7d\xfb\x10\xc1" + "\x66\x7c\xa6\xf4\x48\x36\x5e\x2\xda\x41\x4b\x3e" + "\xe7\x80\x17\x17\xce\xf1\x3e\x6a\x8e\x26\xf3\xb7" + "\x2b\x85\xd\x31\x8d\xba\x6c\x22\xb4\x28\x55\x7e" + "\x2a\x9e\x26\xf1\x3d\x21\xac\x65", + + .ilen = 285 + 20 + 15, + .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07" + "\x00\x03\x01\x01\x40", + .alen = 13, + .result = "285 bytes plaintext285 bytes plaintext285 bytes" + " plaintext285 bytes plaintext285 bytes plaintext285" + " bytes plaintext285 bytes plaintext285 bytes" + " plaintext285 bytes plaintext285 bytes plaintext285" + " bytes plaintext285 bytes plaintext285 bytes" + " plaintext285 bytes plaintext285 bytes plaintext", + .rlen = 285, + } +}; + /* * RSA test vectors. Borrowed from openSSL. */ diff --git a/crypto/tls.c b/crypto/tls.c new file mode 100644 index 00000000000000..fb21bfbaf9abe9 --- /dev/null +++ b/crypto/tls.c @@ -0,0 +1,608 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2017 NXP Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct tls_instance_ctx { + struct crypto_ahash_spawn auth; + struct crypto_skcipher_spawn enc; +}; + +struct crypto_tls_ctx { + unsigned int reqoff; + struct crypto_ahash *auth; + struct crypto_skcipher *enc; + struct crypto_sync_skcipher *null; +}; + +struct tls_request_ctx { + /* + * cryptlen holds the payload length in the case of encryption or + * payload_len + icv_len + padding_len in case of decryption + */ + unsigned int cryptlen; + /* working space for partial results */ + struct scatterlist tmp[2]; + struct scatterlist cipher[2]; + struct scatterlist dst[2]; + char tail[]; +}; + +struct async_op { + struct completion completion; + int err; +}; + +static void tls_async_op_done(struct crypto_async_request *req, int err) +{ + struct async_op *areq = req->data; + + if (err == -EINPROGRESS) + return; + + areq->err = err; + complete(&areq->completion); +} + +static int crypto_tls_setkey(struct crypto_aead *tls, const u8 *key, + unsigned int keylen) +{ + struct crypto_tls_ctx *ctx = crypto_aead_ctx(tls); + struct crypto_ahash *auth = ctx->auth; + struct crypto_skcipher *enc = ctx->enc; + struct crypto_authenc_keys keys; + int err = -EINVAL; + + if (crypto_authenc_extractkeys(&keys, key, keylen) != 0) + goto badkey; + + crypto_ahash_clear_flags(auth, CRYPTO_TFM_REQ_MASK); + crypto_ahash_set_flags(auth, crypto_aead_get_flags(tls) & + CRYPTO_TFM_REQ_MASK); + err = crypto_ahash_setkey(auth, keys.authkey, keys.authkeylen); + crypto_aead_set_flags(tls, crypto_ahash_get_flags(auth) & + CRYPTO_TFM_RES_MASK); + + if (err) + goto out; + + crypto_skcipher_clear_flags(enc, CRYPTO_TFM_REQ_MASK); + crypto_skcipher_set_flags(enc, crypto_aead_get_flags(tls) & + CRYPTO_TFM_REQ_MASK); + err = crypto_skcipher_setkey(enc, keys.enckey, keys.enckeylen); + crypto_aead_set_flags(tls, crypto_skcipher_get_flags(enc) & + CRYPTO_TFM_RES_MASK); + +out: + return err; + +badkey: + crypto_aead_set_flags(tls, CRYPTO_TFM_RES_BAD_KEY_LEN); + goto out; +} + +/** + * crypto_tls_genicv - Calculate hmac digest for a TLS record + * @hash: (output) buffer to save the digest into + * @src: (input) scatterlist with the assoc and payload data + * @srclen: (input) size of the source buffer (assoclen + cryptlen) + * @req: (input) aead request + **/ +static int crypto_tls_genicv(u8 *hash, struct scatterlist *src, + unsigned int srclen, struct aead_request *req) +{ + struct crypto_aead *tls = crypto_aead_reqtfm(req); + struct crypto_tls_ctx *ctx = crypto_aead_ctx(tls); + struct tls_request_ctx *treq_ctx = aead_request_ctx(req); + struct async_op ahash_op; + struct ahash_request *ahreq = (void *)(treq_ctx->tail + ctx->reqoff); + unsigned int flags = CRYPTO_TFM_REQ_MAY_SLEEP; + int err = -EBADMSG; + + /* Bail out if the request assoc len is 0 */ + if (!req->assoclen) + return err; + + init_completion(&ahash_op.completion); + + /* the hash transform to be executed comes from the original request */ + ahash_request_set_tfm(ahreq, ctx->auth); + /* prepare the hash request with input data and result pointer */ + ahash_request_set_crypt(ahreq, src, hash, srclen); + /* set the notifier for when the async hash function returns */ + ahash_request_set_callback(ahreq, aead_request_flags(req) & flags, + tls_async_op_done, &ahash_op); + + /* Calculate the digest on the given data. The result is put in hash */ + err = crypto_ahash_digest(ahreq); + if (err == -EINPROGRESS) { + err = wait_for_completion_interruptible(&ahash_op.completion); + if (!err) + err = ahash_op.err; + } + + return err; +} + +/** + * crypto_tls_gen_padicv - Calculate and pad hmac digest for a TLS record + * @hash: (output) buffer to save the digest and padding into + * @phashlen: (output) the size of digest + padding + * @req: (input) aead request + **/ +static int crypto_tls_gen_padicv(u8 *hash, unsigned int *phashlen, + struct aead_request *req) +{ + struct crypto_aead *tls = crypto_aead_reqtfm(req); + unsigned int hash_size = crypto_aead_authsize(tls); + unsigned int block_size = crypto_aead_blocksize(tls); + unsigned int srclen = req->cryptlen + hash_size; + unsigned int icvlen = req->cryptlen + req->assoclen; + unsigned int padlen; + int err; + + err = crypto_tls_genicv(hash, req->src, icvlen, req); + if (err) + goto out; + + /* add padding after digest */ + padlen = block_size - (srclen % block_size); + memset(hash + hash_size, padlen - 1, padlen); + + *phashlen = hash_size + padlen; +out: + return err; +} + +static int crypto_tls_copy_data(struct aead_request *req, + struct scatterlist *src, + struct scatterlist *dst, + unsigned int len) +{ + struct crypto_aead *tls = crypto_aead_reqtfm(req); + struct crypto_tls_ctx *ctx = crypto_aead_ctx(tls); + SYNC_SKCIPHER_REQUEST_ON_STACK(skreq, ctx->null); + + skcipher_request_set_sync_tfm(skreq, ctx->null); + skcipher_request_set_callback(skreq, aead_request_flags(req), + NULL, NULL); + skcipher_request_set_crypt(skreq, src, dst, len, NULL); + + return crypto_skcipher_encrypt(skreq); +} + +static int crypto_tls_encrypt(struct aead_request *req) +{ + struct crypto_aead *tls = crypto_aead_reqtfm(req); + struct crypto_tls_ctx *ctx = crypto_aead_ctx(tls); + struct tls_request_ctx *treq_ctx = aead_request_ctx(req); + struct skcipher_request *skreq; + struct scatterlist *cipher = treq_ctx->cipher; + struct scatterlist *tmp = treq_ctx->tmp; + struct scatterlist *sg, *src, *dst; + unsigned int cryptlen, phashlen; + u8 *hash = treq_ctx->tail; + int err; + + /* + * The hash result is saved at the beginning of the tls request ctx + * and is aligned as required by the hash transform. Enough space was + * allocated in crypto_tls_init_tfm to accommodate the difference. The + * requests themselves start later at treq_ctx->tail + ctx->reqoff so + * the result is not overwritten by the second (cipher) request. + */ + hash = (u8 *)ALIGN((unsigned long)hash + + crypto_ahash_alignmask(ctx->auth), + crypto_ahash_alignmask(ctx->auth) + 1); + + /* + * STEP 1: create ICV together with necessary padding + */ + err = crypto_tls_gen_padicv(hash, &phashlen, req); + if (err) + return err; + + /* + * STEP 2: Hash and padding are combined with the payload + * depending on the form it arrives. Scatter tables must have at least + * one page of data before chaining with another table and can't have + * an empty data page. The following code addresses these requirements. + * + * If the payload is empty, only the hash is encrypted, otherwise the + * payload scatterlist is merged with the hash. A special merging case + * is when the payload has only one page of data. In that case the + * payload page is moved to another scatterlist and prepared there for + * encryption. + */ + if (req->cryptlen) { + src = scatterwalk_ffwd(tmp, req->src, req->assoclen); + + sg_init_table(cipher, 2); + sg_set_buf(cipher + 1, hash, phashlen); + + if (sg_is_last(src)) { + sg_set_page(cipher, sg_page(src), req->cryptlen, + src->offset); + src = cipher; + } else { + unsigned int rem_len = req->cryptlen; + + for (sg = src; rem_len > sg->length; sg = sg_next(sg)) + rem_len -= min(rem_len, sg->length); + + sg_set_page(cipher, sg_page(sg), rem_len, sg->offset); + sg_chain(sg, 1, cipher); + } + } else { + sg_init_one(cipher, hash, phashlen); + src = cipher; + } + + /** + * If src != dst copy the associated data from source to destination. + * In both cases fast-forward passed the associated data in the dest. + */ + if (req->src != req->dst) { + err = crypto_tls_copy_data(req, req->src, req->dst, + req->assoclen); + if (err) + return err; + } + dst = scatterwalk_ffwd(treq_ctx->dst, req->dst, req->assoclen); + + /* + * STEP 3: encrypt the frame and return the result + */ + cryptlen = req->cryptlen + phashlen; + + /* + * The hash and the cipher are applied at different times and their + * requests can use the same memory space without interference + */ + skreq = (void *)(treq_ctx->tail + ctx->reqoff); + skcipher_request_set_tfm(skreq, ctx->enc); + skcipher_request_set_crypt(skreq, src, dst, cryptlen, req->iv); + skcipher_request_set_callback(skreq, aead_request_flags(req), + req->base.complete, req->base.data); + /* + * Apply the cipher transform. The result will be in req->dst when the + * asynchronuous call terminates + */ + err = crypto_skcipher_encrypt(skreq); + + return err; +} + +static int crypto_tls_decrypt(struct aead_request *req) +{ + struct crypto_aead *tls = crypto_aead_reqtfm(req); + struct crypto_tls_ctx *ctx = crypto_aead_ctx(tls); + struct tls_request_ctx *treq_ctx = aead_request_ctx(req); + unsigned int cryptlen = req->cryptlen; + unsigned int hash_size = crypto_aead_authsize(tls); + unsigned int block_size = crypto_aead_blocksize(tls); + struct skcipher_request *skreq = (void *)(treq_ctx->tail + ctx->reqoff); + struct scatterlist *tmp = treq_ctx->tmp; + struct scatterlist *src, *dst; + + u8 padding[255]; /* padding can be 0-255 bytes */ + u8 pad_size; + u16 *len_field; + u8 *ihash, *hash = treq_ctx->tail; + + int paderr = 0; + int err = -EINVAL; + int i; + struct async_op ciph_op; + + /* + * Rule out bad packets. The input packet length must be at least one + * byte more than the hash_size + */ + if (cryptlen <= hash_size || cryptlen % block_size) + goto out; + + /* + * Step 1 - Decrypt the source. Fast-forward past the associated data + * to the encrypted data. The result will be overwritten in place so + * that the decrypted data will be adjacent to the associated data. The + * last step (computing the hash) will have it's input data already + * prepared and ready to be accessed at req->src. + */ + src = scatterwalk_ffwd(tmp, req->src, req->assoclen); + dst = src; + + init_completion(&ciph_op.completion); + skcipher_request_set_tfm(skreq, ctx->enc); + skcipher_request_set_callback(skreq, aead_request_flags(req), + tls_async_op_done, &ciph_op); + skcipher_request_set_crypt(skreq, src, dst, cryptlen, req->iv); + err = crypto_skcipher_decrypt(skreq); + if (err == -EINPROGRESS) { + err = wait_for_completion_interruptible(&ciph_op.completion); + if (!err) + err = ciph_op.err; + } + if (err) + goto out; + + /* + * Step 2 - Verify padding + * Retrieve the last byte of the payload; this is the padding size. + */ + cryptlen -= 1; + scatterwalk_map_and_copy(&pad_size, dst, cryptlen, 1, 0); + + /* RFC recommendation for invalid padding size. */ + if (cryptlen < pad_size + hash_size) { + pad_size = 0; + paderr = -EBADMSG; + } + cryptlen -= pad_size; + scatterwalk_map_and_copy(padding, dst, cryptlen, pad_size, 0); + + /* Padding content must be equal with pad_size. We verify it all */ + for (i = 0; i < pad_size; i++) + if (padding[i] != pad_size) + paderr = -EBADMSG; + + /* + * Step 3 - Verify hash + * Align the digest result as required by the hash transform. Enough + * space was allocated in crypto_tls_init_tfm + */ + hash = (u8 *)ALIGN((unsigned long)hash + + crypto_ahash_alignmask(ctx->auth), + crypto_ahash_alignmask(ctx->auth) + 1); + /* + * Two bytes at the end of the associated data make the length field. + * It must be updated with the length of the cleartext message before + * the hash is calculated. + */ + len_field = sg_virt(req->src) + req->assoclen - 2; + cryptlen -= hash_size; + *len_field = htons(cryptlen); + + /* This is the hash from the decrypted packet. Save it for later */ + ihash = hash + hash_size; + scatterwalk_map_and_copy(ihash, dst, cryptlen, hash_size, 0); + + /* Now compute and compare our ICV with the one from the packet */ + err = crypto_tls_genicv(hash, req->src, cryptlen + req->assoclen, req); + if (!err) + err = memcmp(hash, ihash, hash_size) ? -EBADMSG : 0; + + if (req->src != req->dst) { + err = crypto_tls_copy_data(req, req->src, req->dst, cryptlen + + req->assoclen); + if (err) + goto out; + } + + /* return the first found error */ + if (paderr) + err = paderr; + +out: + aead_request_complete(req, err); + return err; +} + +static int crypto_tls_init_tfm(struct crypto_aead *tfm) +{ + struct aead_instance *inst = aead_alg_instance(tfm); + struct tls_instance_ctx *ictx = aead_instance_ctx(inst); + struct crypto_tls_ctx *ctx = crypto_aead_ctx(tfm); + struct crypto_ahash *auth; + struct crypto_skcipher *enc; + struct crypto_sync_skcipher *null; + int err; + + auth = crypto_spawn_ahash(&ictx->auth); + if (IS_ERR(auth)) + return PTR_ERR(auth); + + enc = crypto_spawn_skcipher(&ictx->enc); + err = PTR_ERR(enc); + if (IS_ERR(enc)) + goto err_free_ahash; + + null = crypto_get_default_null_skcipher(); + err = PTR_ERR(null); + if (IS_ERR(null)) + goto err_free_skcipher; + + ctx->auth = auth; + ctx->enc = enc; + ctx->null = null; + + /* + * Allow enough space for two digests. The two digests will be compared + * during the decryption phase. One will come from the decrypted packet + * and the other will be calculated. For encryption, one digest is + * padded (up to a cipher blocksize) and chained with the payload + */ + ctx->reqoff = ALIGN(crypto_ahash_digestsize(auth) + + crypto_ahash_alignmask(auth), + crypto_ahash_alignmask(auth) + 1) + + max(crypto_ahash_digestsize(auth), + crypto_skcipher_blocksize(enc)); + + crypto_aead_set_reqsize(tfm, + sizeof(struct tls_request_ctx) + + ctx->reqoff + + max_t(unsigned int, + crypto_ahash_reqsize(auth) + + sizeof(struct ahash_request), + crypto_skcipher_reqsize(enc) + + sizeof(struct skcipher_request))); + + return 0; + +err_free_skcipher: + crypto_free_skcipher(enc); +err_free_ahash: + crypto_free_ahash(auth); + return err; +} + +static void crypto_tls_exit_tfm(struct crypto_aead *tfm) +{ + struct crypto_tls_ctx *ctx = crypto_aead_ctx(tfm); + + crypto_free_ahash(ctx->auth); + crypto_free_skcipher(ctx->enc); + crypto_put_default_null_skcipher(); +} + +static void crypto_tls_free(struct aead_instance *inst) +{ + struct tls_instance_ctx *ctx = aead_instance_ctx(inst); + + crypto_drop_skcipher(&ctx->enc); + crypto_drop_ahash(&ctx->auth); + kfree(inst); +} + +static int crypto_tls_create(struct crypto_template *tmpl, struct rtattr **tb) +{ + struct crypto_attr_type *algt; + struct aead_instance *inst; + struct hash_alg_common *auth; + struct crypto_alg *auth_base; + struct skcipher_alg *enc; + struct tls_instance_ctx *ctx; + const char *enc_name; + int err; + + algt = crypto_get_attr_type(tb); + if (IS_ERR(algt)) + return PTR_ERR(algt); + + if ((algt->type ^ CRYPTO_ALG_TYPE_AEAD) & algt->mask) + return -EINVAL; + + auth = ahash_attr_alg(tb[1], CRYPTO_ALG_TYPE_HASH, + CRYPTO_ALG_TYPE_AHASH_MASK | + crypto_requires_sync(algt->type, algt->mask)); + if (IS_ERR(auth)) + return PTR_ERR(auth); + + auth_base = &auth->base; + + enc_name = crypto_attr_alg_name(tb[2]); + err = PTR_ERR(enc_name); + if (IS_ERR(enc_name)) + goto out_put_auth; + + inst = kzalloc(sizeof(*inst) + sizeof(*ctx), GFP_KERNEL); + err = -ENOMEM; + if (!inst) + goto out_put_auth; + + ctx = aead_instance_ctx(inst); + + err = crypto_init_ahash_spawn(&ctx->auth, auth, + aead_crypto_instance(inst)); + if (err) + goto err_free_inst; + + crypto_set_skcipher_spawn(&ctx->enc, aead_crypto_instance(inst)); + err = crypto_grab_skcipher(&ctx->enc, enc_name, 0, + crypto_requires_sync(algt->type, + algt->mask)); + if (err) + goto err_drop_auth; + + enc = crypto_spawn_skcipher_alg(&ctx->enc); + + err = -ENAMETOOLONG; + if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME, + "tls10(%s,%s)", auth_base->cra_name, + enc->base.cra_name) >= CRYPTO_MAX_ALG_NAME) + goto err_drop_enc; + + if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME, + "tls10(%s,%s)", auth_base->cra_driver_name, + enc->base.cra_driver_name) >= CRYPTO_MAX_ALG_NAME) + goto err_drop_enc; + + inst->alg.base.cra_flags = (auth_base->cra_flags | + enc->base.cra_flags) & CRYPTO_ALG_ASYNC; + inst->alg.base.cra_priority = enc->base.cra_priority * 10 + + auth_base->cra_priority; + inst->alg.base.cra_blocksize = enc->base.cra_blocksize; + inst->alg.base.cra_alignmask = auth_base->cra_alignmask | + enc->base.cra_alignmask; + inst->alg.base.cra_ctxsize = sizeof(struct crypto_tls_ctx); + + inst->alg.ivsize = crypto_skcipher_alg_ivsize(enc); + inst->alg.chunksize = crypto_skcipher_alg_chunksize(enc); + inst->alg.maxauthsize = auth->digestsize; + + inst->alg.init = crypto_tls_init_tfm; + inst->alg.exit = crypto_tls_exit_tfm; + + inst->alg.setkey = crypto_tls_setkey; + inst->alg.encrypt = crypto_tls_encrypt; + inst->alg.decrypt = crypto_tls_decrypt; + + inst->free = crypto_tls_free; + + err = aead_register_instance(tmpl, inst); + if (err) + goto err_drop_enc; + +out: + crypto_mod_put(auth_base); + return err; + +err_drop_enc: + crypto_drop_skcipher(&ctx->enc); +err_drop_auth: + crypto_drop_ahash(&ctx->auth); +err_free_inst: + kfree(inst); +out_put_auth: + goto out; +} + +static struct crypto_template crypto_tls_tmpl = { + .name = "tls10", + .create = crypto_tls_create, + .module = THIS_MODULE, +}; + +static int __init crypto_tls_module_init(void) +{ + return crypto_register_template(&crypto_tls_tmpl); +} + +static void __exit crypto_tls_module_exit(void) +{ + crypto_unregister_template(&crypto_tls_tmpl); +} + +module_init(crypto_tls_module_init); +module_exit(crypto_tls_module_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("TLS 1.0 record encryption"); +MODULE_ALIAS_CRYPTO("tls10"); diff --git a/drivers/Kconfig b/drivers/Kconfig index 8befa53f43beb5..3986e201fe6f7b 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -228,4 +228,5 @@ source "drivers/interconnect/Kconfig" source "drivers/counter/Kconfig" +source "drivers/mxc/Kconfig" endmenu diff --git a/drivers/Makefile b/drivers/Makefile index aaef17cc651287..5792caca1bb150 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -186,3 +186,4 @@ obj-$(CONFIG_SIOX) += siox/ obj-$(CONFIG_GNSS) += gnss/ obj-$(CONFIG_INTERCONNECT) += interconnect/ obj-$(CONFIG_COUNTER) += counter/ +obj-y += mxc/ diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c index bfc617cc8ac598..e69af4d2c303a6 100644 --- a/drivers/ata/ahci_imx.c +++ b/drivers/ata/ahci_imx.c @@ -44,9 +44,23 @@ enum { IMX_CLOCK_RESET = 0x7f3f, IMX_CLOCK_RESET_RESET = 1 << 0, /* IMX8QM HSIO AHCI definitions */ - IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET = 0x03, - IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET = 0x09, - IMX8QM_SATA_PHY_IMPED_RATIO_85OHM = 0x6c, + IMX8QM_SATA_PHY_REG03_RX_IMPED_RATIO = 0x03, + IMX8QM_SATA_PHY_REG09_TX_IMPED_RATIO = 0x09, + IMX8QM_SATA_PHY_REG10_TX_POST_CURSOR_RATIO = 0x0a, + IMX8QM_SATA_PHY_GEN1_TX_POST_CURSOR_RATIO = 0x15, + IMX8QM_SATA_PHY_IMPED_RATIO_100OHM = 0x5d, + IMX8QM_SATA_PHY_REG22_TX_POST_CURSOR_RATIO = 0x16, + IMX8QM_SATA_PHY_GEN2_TX_POST_CURSOR_RATIO = 0x00, + IMX8QM_SATA_PHY_REG24_TX_AMP_RATIO_MARGIN0 = 0x18, + IMX8QM_SATA_PHY_TX_AMP_RATIO_MARGIN0 = 0x64, + IMX8QM_SATA_PHY_REG25_TX_AMP_RATIO_MARGIN1 = 0x19, + IMX8QM_SATA_PHY_TX_AMP_RATIO_MARGIN1 = 0x70, + IMX8QM_SATA_PHY_REG26_TX_AMP_RATIO_MARGIN2 = 0x1a, + IMX8QM_SATA_PHY_TX_AMP_RATIO_MARGIN2 = 0x69, + IMX8QM_SATA_PHY_REG48_PMA_STATUS = 0x30, + IMX8QM_SATA_PHY_REG48_PMA_RDY = BIT(7), + IMX8QM_SATA_PHY_REG128_UPDATE_SETTING = 0x80, + IMX8QM_SATA_PHY_UPDATE_SETTING = 0x01, IMX8QM_LPCG_PHYX2_OFFSET = 0x00000, IMX8QM_CSR_PHYX2_OFFSET = 0x90000, IMX8QM_CSR_PHYX1_OFFSET = 0xa0000, @@ -56,10 +70,31 @@ enum { IMX8QM_CSR_SATA_OFFSET = 0xd0000, IMX8QM_CSR_PCIE_CTRL2_OFFSET = 0x8, IMX8QM_CSR_MISC_OFFSET = 0xe0000, + /* IMX8QM SATA specific control registers */ + IMX8QM_SATA_PPCFG_OFFSET = 0xa8, + IMX8QM_SATA_PPCFG_FORCE_PHY_RDY = BIT(20), + IMX8QM_SATA_PPCFG_BIST_PATTERN_MASK = 0x7 << 21, + IMX8QM_SATA_PPCFG_BIST_PATTERN_OFFSET = 21, + IMX8QM_SATA_PPCFG_BIST_PATTERN_EN = BIT(24), + IMX8QM_SATA_PPCFG_BIST_PATTERN_NOALIGNS = BIT(26), + IMX8QM_SATA_PP2CFG_OFFSET = 0xac, + IMX8QM_SATA_PP2CFG_COMINIT_NEGATE_MIN = 0x28 << 24, + IMX8QM_SATA_PP2CFG_COMINT_BURST_GAP = 0x18 << 16, + IMX8QM_SATA_PP2CFG_COMINT_BURST_GAP_MAX = 0x2b << 8, + IMX8QM_SATA_PP2CFG_COMINT_BURST_GAP_MIN = 0x1b << 0, + IMX8QM_SATA_PP3CFG_OFFSET = 0xb0, + IMX8QM_SATA_PP3CFG_COMWAKE_NEGATE_MIN = 0x0e << 24, + IMX8QM_SATA_PP3CFG_COMWAKE_BURST_GAP = 0x08 << 16, + IMX8QM_SATA_PP3CFG_COMWAKE_BURST_GAP_MAX = 0x0f << 8, + IMX8QM_SATA_PP3CFG_COMWAKE_BURST_GAP_MIN = 0x01 << 0, + IMX8QM_SATA_AHCI_VEND_PTC = 0xc8, + IMX8QM_SATA_AHCI_VEND_PTC_RXWM_MASK = 0x7f, + IMX8QM_SATA_AHCI_VEND_PTC_RXWM = 0x29, IMX8QM_LPCG_PHYX2_PCLK0_MASK = (0x3 << 16), IMX8QM_LPCG_PHYX2_PCLK1_MASK = (0x3 << 20), IMX8QM_PHY_APB_RSTN_0 = BIT(0), + IMX8QM_PHY_APB_RSTN_1 = BIT(1), IMX8QM_PHY_MODE_SATA = BIT(19), IMX8QM_PHY_MODE_MASK = (0xf << 17), IMX8QM_PHY_PIPE_RSTN_0 = BIT(24), @@ -76,7 +111,10 @@ enum { IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0 = BIT(29), IMX8QM_SATA_CTRL_RESET_N = BIT(12), IMX8QM_SATA_CTRL_EPCS_PHYRESET_N = BIT(7), + IMX8QM_SATA_CTRL_EPCS_TXDEEMP_SEL = BIT(6), + IMX8QM_SATA_CTRL_EPCS_TXDEEMP = BIT(5), IMX8QM_CTRL_BUTTON_RST_N = BIT(21), + IMX8QM_CTRL_PERST_N = BIT(22), IMX8QM_CTRL_POWER_UP_RST_N = BIT(23), IMX8QM_CTRL_LTSSM_ENABLE = BIT(4), }; @@ -99,6 +137,12 @@ struct imx_ahci_priv { struct clk *phy_apbclk; struct clk *phy_pclk0; struct clk *phy_pclk1; + struct clk *per_clk0; + struct clk *per_clk1; + struct clk *per_clk2; + struct clk *per_clk3; + struct clk *per_clk4; + struct clk *per_clk5; void __iomem *phy_base; int clkreq_gpio; struct regmap *gpr; @@ -106,14 +150,70 @@ struct imx_ahci_priv { bool first_time; u32 phy_params; u32 imped_ratio; + u32 ext_osc; }; +void *sg_io_buffer_hack; + static int ahci_imx_hotplug; module_param_named(hotplug, ahci_imx_hotplug, int, 0644); MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)"); +static int bist_enable; +module_param_named(bist, bist_enable, int, 0644); +MODULE_PARM_DESC(bist, "AHCI IMX bist mode enable(1 = enable)"); + static void ahci_imx_host_stop(struct ata_host *host); +static bool imx_sata_readable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case IMX8QM_LPCG_PHYX2_OFFSET: + case IMX8QM_CSR_PHYX2_OFFSET: + case IMX8QM_CSR_PHYX1_OFFSET: + case IMX8QM_CSR_PCIEA_OFFSET: + case IMX8QM_CSR_PCIEB_OFFSET: + case IMX8QM_CSR_SATA_OFFSET: + case IMX8QM_CSR_MISC_OFFSET: + case IMX8QM_CSR_PHYX2_OFFSET + IMX8QM_CSR_PHYX_STTS0_OFFSET: + case IMX8QM_CSR_PHYX1_OFFSET + IMX8QM_CSR_PHYX_STTS0_OFFSET: + case IMX8QM_CSR_PCIEA_OFFSET + IMX8QM_CSR_PCIE_CTRL2_OFFSET: + case IMX8QM_CSR_PCIEB_OFFSET + IMX8QM_CSR_PCIE_CTRL2_OFFSET: + return true; + default: + return false; + } +} + +static bool imx_sata_writeable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case IMX8QM_LPCG_PHYX2_OFFSET: + case IMX8QM_CSR_PHYX2_OFFSET: + case IMX8QM_CSR_PHYX1_OFFSET: + case IMX8QM_CSR_PCIEA_OFFSET: + case IMX8QM_CSR_PCIEB_OFFSET: + case IMX8QM_CSR_SATA_OFFSET: + case IMX8QM_CSR_MISC_OFFSET: + case IMX8QM_CSR_PCIEA_OFFSET + IMX8QM_CSR_PCIE_CTRL2_OFFSET: + case IMX8QM_CSR_PCIEB_OFFSET + IMX8QM_CSR_PCIE_CTRL2_OFFSET: + return true; + default: + return false; + } +} + +static const struct regmap_config imx_sata_regconfig = { + .max_register = IMX8QM_CSR_MISC_OFFSET, + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .val_format_endian = REGMAP_ENDIAN_NATIVE, + .num_reg_defaults_raw = IMX8QM_CSR_MISC_OFFSET / sizeof(uint32_t) + 1, + .readable_reg = imx_sata_readable_reg, + .writeable_reg = imx_sata_writeable_reg, + .cache_type = REGCACHE_NONE, +}; static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert) { int timeout = 10; @@ -442,11 +542,9 @@ static struct attribute *fsl_sata_ahci_attrs[] = { }; ATTRIBUTE_GROUPS(fsl_sata_ahci); -static int imx8_sata_enable(struct ahci_host_priv *hpriv) +static int imx8_sata_clk_enable(struct imx_ahci_priv *imxpriv) { - u32 val, reg; - int i, ret; - struct imx_ahci_priv *imxpriv = hpriv->plat_data; + int ret; struct device *dev = &imxpriv->ahci_pdev->dev; /* configure the hsio for sata */ @@ -475,6 +573,92 @@ static int imx8_sata_enable(struct ahci_host_priv *hpriv) dev_err(dev, "can't enable phy_apbclk.\n"); goto disable_epcs_rx_clk; } + ret = clk_prepare_enable(imxpriv->per_clk0); + if (ret < 0) { + dev_err(dev, "can't enable per_clk.\n"); + goto disable_phy_apbclk; + } + ret = clk_prepare_enable(imxpriv->per_clk1); + if (ret < 0) { + dev_err(dev, "can't enable per_clk.\n"); + goto disable_per_clk0; + } + ret = clk_prepare_enable(imxpriv->per_clk2); + if (ret < 0) { + dev_err(dev, "can't enable per_clk.\n"); + goto disable_per_clk1; + } + ret = clk_prepare_enable(imxpriv->per_clk3); + if (ret < 0) { + dev_err(dev, "can't enable per_clk.\n"); + goto disable_per_clk2; + } + ret = clk_prepare_enable(imxpriv->per_clk4); + if (ret < 0) { + dev_err(dev, "can't enable per_clk.\n"); + goto disable_per_clk3; + } + ret = clk_prepare_enable(imxpriv->per_clk5); + if (ret < 0) + dev_err(dev, "can't enable per_clk.\n"); + else + return 0; + + clk_disable_unprepare(imxpriv->per_clk4); +disable_per_clk3: + clk_disable_unprepare(imxpriv->per_clk3); +disable_per_clk2: + clk_disable_unprepare(imxpriv->per_clk2); +disable_per_clk1: + clk_disable_unprepare(imxpriv->per_clk1); +disable_per_clk0: + clk_disable_unprepare(imxpriv->per_clk0); +disable_phy_apbclk: + clk_disable_unprepare(imxpriv->phy_apbclk); +disable_epcs_rx_clk: + clk_disable_unprepare(imxpriv->epcs_rx_clk); +disable_epcs_tx_clk: + clk_disable_unprepare(imxpriv->epcs_tx_clk); +disable_phy_pclk1: + clk_disable_unprepare(imxpriv->phy_pclk1); +disable_phy_pclk0: + clk_disable_unprepare(imxpriv->phy_pclk0); + return ret; +} + +static void imx8_sata_clk_disable(struct imx_ahci_priv *imxpriv) +{ + regmap_update_bits(imxpriv->gpr, + IMX8QM_LPCG_PHYX2_OFFSET, + IMX8QM_LPCG_PHYX2_PCLK0_MASK | + IMX8QM_LPCG_PHYX2_PCLK1_MASK, 0); + clk_disable_unprepare(imxpriv->epcs_rx_clk); + clk_disable_unprepare(imxpriv->epcs_tx_clk); + clk_disable_unprepare(imxpriv->per_clk5); + clk_disable_unprepare(imxpriv->per_clk4); + clk_disable_unprepare(imxpriv->per_clk3); + clk_disable_unprepare(imxpriv->per_clk2); + clk_disable_unprepare(imxpriv->per_clk1); + clk_disable_unprepare(imxpriv->per_clk0); +} + +static int imx8_sata_enable(struct ahci_host_priv *hpriv) +{ + u32 val, reg; + int i, ret; + struct imx_ahci_priv *imxpriv = hpriv->plat_data; + struct device *dev = &imxpriv->ahci_pdev->dev; + + ret = imx8_sata_clk_enable(imxpriv); + if (ret) + return ret; + + /* PHYX2 APB reset */ + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_PHYX2_OFFSET, + IMX8QM_PHY_APB_RSTN_0 | IMX8QM_PHY_APB_RSTN_1, + IMX8QM_PHY_APB_RSTN_0 | IMX8QM_PHY_APB_RSTN_1); + /* Configure PHYx2 PIPE_RSTN */ regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEA_OFFSET + IMX8QM_CSR_PCIE_CTRL2_OFFSET, &val); @@ -498,14 +682,13 @@ static int imx8_sata_enable(struct ahci_host_priv *hpriv) IMX8QM_PHY_PIPE_RSTN_1 | IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1); } - if (((reg | val) & IMX8QM_CTRL_LTSSM_ENABLE) == 0) { - /* The links of both PCIA and PCIEB of HSIO are down */ - regmap_update_bits(imxpriv->gpr, - IMX8QM_LPCG_PHYX2_OFFSET, - IMX8QM_LPCG_PHYX2_PCLK0_MASK | - IMX8QM_LPCG_PHYX2_PCLK1_MASK, - 0); - } + + regmap_update_bits(imxpriv->gpr, + IMX8QM_LPCG_PHYX2_OFFSET, + IMX8QM_LPCG_PHYX2_PCLK0_MASK | + IMX8QM_LPCG_PHYX2_PCLK1_MASK, + IMX8QM_LPCG_PHYX2_PCLK0_MASK | + IMX8QM_LPCG_PHYX2_PCLK1_MASK); /* set PWR_RST and BT_RST of csr_pciea */ val = IMX8QM_CSR_PCIEA_OFFSET + IMX8QM_CSR_PCIE_CTRL2_OFFSET; @@ -513,6 +696,8 @@ static int imx8_sata_enable(struct ahci_host_priv *hpriv) val, IMX8QM_CTRL_BUTTON_RST_N, IMX8QM_CTRL_BUTTON_RST_N); + regmap_update_bits(imxpriv->gpr, val, IMX8QM_CTRL_PERST_N, + IMX8QM_CTRL_PERST_N); regmap_update_bits(imxpriv->gpr, val, IMX8QM_CTRL_POWER_UP_RST_N, @@ -524,18 +709,32 @@ static int imx8_sata_enable(struct ahci_host_priv *hpriv) IMX8QM_PHY_MODE_MASK, IMX8QM_PHY_MODE_SATA); - /* - * BIT0 RXENA 1, BIT1 TXENA 0 - * BIT12 PHY_X1_EPCS_SEL 1. - */ - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_MISC_OFFSET, - IMX8QM_MISC_IOB_RXENA, - IMX8QM_MISC_IOB_RXENA); - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_MISC_OFFSET, - IMX8QM_MISC_IOB_TXENA, - 0); + if (imxpriv->ext_osc) { + dev_info(dev, "external osc is used.\n"); + /* + * bit0 rx ena 1, bit1 tx ena 0 + * bit12 PHY_X1_EPCS_SEL 1. + */ + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_IOB_RXENA, + IMX8QM_MISC_IOB_RXENA); + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_IOB_TXENA, + 0); + } else { + dev_info(dev, "internal pll is used.\n"); + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_IOB_RXENA, + 0); + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_IOB_TXENA, + IMX8QM_MISC_IOB_TXENA); + + } regmap_update_bits(imxpriv->gpr, IMX8QM_CSR_MISC_OFFSET, IMX8QM_MISC_PHYX1_EPCS_SEL, @@ -560,6 +759,21 @@ static int imx8_sata_enable(struct ahci_host_priv *hpriv) IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 | IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0); + /* APB reset */ + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_PHYX1_OFFSET, + IMX8QM_PHY_APB_RSTN_0, + IMX8QM_PHY_APB_RSTN_0); + + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_SATA_OFFSET, + IMX8QM_SATA_CTRL_EPCS_TXDEEMP, + IMX8QM_SATA_CTRL_EPCS_TXDEEMP); + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_SATA_OFFSET, + IMX8QM_SATA_CTRL_EPCS_TXDEEMP_SEL, + IMX8QM_SATA_CTRL_EPCS_TXDEEMP_SEL); + /* clear PHY RST, then set it */ regmap_update_bits(imxpriv->gpr, IMX8QM_CSR_SATA_OFFSET, @@ -586,12 +800,6 @@ static int imx8_sata_enable(struct ahci_host_priv *hpriv) IMX8QM_SATA_CTRL_RESET_N, IMX8QM_SATA_CTRL_RESET_N); - /* APB reset */ - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_PHYX1_OFFSET, - IMX8QM_PHY_APB_RSTN_0, - IMX8QM_PHY_APB_RSTN_0); - for (i = 0; i < 100; i++) { reg = IMX8QM_CSR_PHYX1_OFFSET + IMX8QM_CSR_PHYX_STTS0_OFFSET; @@ -606,18 +814,68 @@ static int imx8_sata_enable(struct ahci_host_priv *hpriv) dev_err(dev, "TX PLL of the PHY is not locked\n"); ret = -ENODEV; } else { - writeb(imxpriv->imped_ratio, imxpriv->phy_base + - IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET); - writeb(imxpriv->imped_ratio, imxpriv->phy_base + - IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET); - reg = readb(imxpriv->phy_base + - IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET); + for (i = 0; i < 1000; i++) { + reg = readb(imxpriv->phy_base + + IMX8QM_SATA_PHY_REG48_PMA_STATUS); + if (reg & IMX8QM_SATA_PHY_REG48_PMA_RDY) + break; + udelay(10); + } + if ((reg & IMX8QM_SATA_PHY_REG48_PMA_RDY) == 0) { + dev_err(dev, "Calibration is NOT finished.\n"); + ret = -ENODEV; + goto err_out; + } + + writeb(imxpriv->imped_ratio, imxpriv->phy_base + + IMX8QM_SATA_PHY_REG03_RX_IMPED_RATIO); + writeb(imxpriv->imped_ratio, imxpriv->phy_base + + IMX8QM_SATA_PHY_REG09_TX_IMPED_RATIO); + reg = readb(imxpriv->phy_base + + IMX8QM_SATA_PHY_REG03_RX_IMPED_RATIO); if (unlikely(reg != imxpriv->imped_ratio)) dev_info(dev, "Can't set PHY RX impedance ratio.\n"); - reg = readb(imxpriv->phy_base + - IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET); + reg = readb(imxpriv->phy_base + + IMX8QM_SATA_PHY_REG09_TX_IMPED_RATIO); if (unlikely(reg != imxpriv->imped_ratio)) dev_info(dev, "Can't set PHY TX impedance ratio.\n"); + + /* RxWaterMark setting */ + val = readl(hpriv->mmio + IMX8QM_SATA_AHCI_VEND_PTC); + val &= ~IMX8QM_SATA_AHCI_VEND_PTC_RXWM_MASK; + val |= IMX8QM_SATA_AHCI_VEND_PTC_RXWM; + writel(val, hpriv->mmio + IMX8QM_SATA_AHCI_VEND_PTC); + + /* Configure the tx_amplitude to pass the tests. */ + writeb(IMX8QM_SATA_PHY_TX_AMP_RATIO_MARGIN0, imxpriv->phy_base + + IMX8QM_SATA_PHY_REG24_TX_AMP_RATIO_MARGIN0); + writeb(IMX8QM_SATA_PHY_TX_AMP_RATIO_MARGIN1, imxpriv->phy_base + + IMX8QM_SATA_PHY_REG25_TX_AMP_RATIO_MARGIN1); + writeb(IMX8QM_SATA_PHY_TX_AMP_RATIO_MARGIN2, imxpriv->phy_base + + IMX8QM_SATA_PHY_REG26_TX_AMP_RATIO_MARGIN2); + + /* Adjust the OOB COMINIT/COMWAKE to pass the tests. */ + writeb(IMX8QM_SATA_PHY_GEN1_TX_POST_CURSOR_RATIO, + imxpriv->phy_base + + IMX8QM_SATA_PHY_REG10_TX_POST_CURSOR_RATIO); + writeb(IMX8QM_SATA_PHY_GEN2_TX_POST_CURSOR_RATIO, + imxpriv->phy_base + + IMX8QM_SATA_PHY_REG22_TX_POST_CURSOR_RATIO); + + writeb(IMX8QM_SATA_PHY_UPDATE_SETTING, imxpriv->phy_base + + IMX8QM_SATA_PHY_REG128_UPDATE_SETTING); + + reg = IMX8QM_SATA_PP2CFG_COMINIT_NEGATE_MIN | + IMX8QM_SATA_PP2CFG_COMINT_BURST_GAP | + IMX8QM_SATA_PP2CFG_COMINT_BURST_GAP_MAX | + IMX8QM_SATA_PP2CFG_COMINT_BURST_GAP_MIN; + writel(reg, hpriv->mmio + IMX8QM_SATA_PP2CFG_OFFSET); + reg = IMX8QM_SATA_PP3CFG_COMWAKE_NEGATE_MIN | + IMX8QM_SATA_PP3CFG_COMWAKE_BURST_GAP | + IMX8QM_SATA_PP3CFG_COMWAKE_BURST_GAP_MAX | + IMX8QM_SATA_PP3CFG_COMWAKE_BURST_GAP_MIN; + writel(reg, hpriv->mmio + IMX8QM_SATA_PP3CFG_OFFSET); + usleep_range(50, 100); /* @@ -630,15 +888,11 @@ static int imx8_sata_enable(struct ahci_host_priv *hpriv) return ret; } +err_out: clk_disable_unprepare(imxpriv->phy_apbclk); -disable_epcs_rx_clk: - clk_disable_unprepare(imxpriv->epcs_rx_clk); -disable_epcs_tx_clk: - clk_disable_unprepare(imxpriv->epcs_tx_clk); -disable_phy_pclk1: clk_disable_unprepare(imxpriv->phy_pclk1); -disable_phy_pclk0: clk_disable_unprepare(imxpriv->phy_pclk0); + imx8_sata_clk_disable(imxpriv); return ret; } @@ -692,6 +946,9 @@ static int imx_sata_enable(struct ahci_host_priv *hpriv) } } else if (imxpriv->type == AHCI_IMX8QM) { ret = imx8_sata_enable(hpriv); + if (ret) + goto disable_clk; + } usleep_range(1000, 2000); @@ -730,8 +987,7 @@ static void imx_sata_disable(struct ahci_host_priv *hpriv) break; case AHCI_IMX8QM: - clk_disable_unprepare(imxpriv->epcs_rx_clk); - clk_disable_unprepare(imxpriv->epcs_tx_clk); + imx8_sata_clk_disable(imxpriv); break; default: @@ -754,7 +1010,8 @@ static void ahci_imx_error_handler(struct ata_port *ap) ahci_error_handler(ap); - if (!(imxpriv->first_time) || ahci_imx_hotplug) + if (!(imxpriv->first_time) || ahci_imx_hotplug || + (imxpriv->type == AHCI_IMX8QM)) return; imxpriv->first_time = false; @@ -980,13 +1237,26 @@ static struct scsi_host_template ahci_platform_sht = { static int imx8_sata_probe(struct device *dev, struct imx_ahci_priv *imxpriv) { - int ret; - struct resource *phy_res; + void __iomem *iomem; + struct resource *res, *phy_res; struct platform_device *pdev = imxpriv->ahci_pdev; struct device_node *np = dev->of_node; + struct regmap_config regconfig = imx_sata_regconfig; + + if (!(dev->bus_dma_mask)) { + dev->bus_dma_mask = DMA_BIT_MASK(32); + dev_info(dev, "imx8qm sata only supports 32bit dma.\n"); + } + if (of_property_read_u32(np, "ext_osc", &imxpriv->ext_osc) < 0) { + dev_info(dev, "ext_osc is not specified.\n"); + /* Use the external osc as ref clk defaultly. */ + imxpriv->ext_osc = 1; + } - if (of_property_read_u32(np, "fsl,phy-imp", &imxpriv->imped_ratio)) - imxpriv->imped_ratio = IMX8QM_SATA_PHY_IMPED_RATIO_85OHM; + if (of_property_read_u32(np, "fsl,phy-imp", &imxpriv->imped_ratio)) { + dev_info(dev, "phy impedance ratio is not specified.\n"); + imxpriv->imped_ratio = IMX8QM_SATA_PHY_IMPED_RATIO_100OHM; + } phy_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); if (phy_res) { imxpriv->phy_base = devm_ioremap(dev, phy_res->start, @@ -999,11 +1269,19 @@ static int imx8_sata_probe(struct device *dev, struct imx_ahci_priv *imxpriv) dev_err(dev, "missing *phy* reg region.\n"); return -ENOMEM; } - imxpriv->gpr = - syscon_regmap_lookup_by_phandle(np, "hsio"); - if (IS_ERR(imxpriv->gpr)) { - dev_err(dev, "unable to find gpr registers\n"); - return PTR_ERR(imxpriv->gpr); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hsio"); + if (res) { + iomem = devm_ioremap(dev, res->start, resource_size(res)); + if (IS_ERR(iomem)) + return PTR_ERR(iomem); + imxpriv->gpr = devm_regmap_init_mmio(dev, iomem, ®config); + if (IS_ERR(imxpriv->gpr)) { + dev_err(dev, "failed to init register map\n"); + return PTR_ERR(imxpriv->gpr); + } + } else { + dev_err(dev, "missing *hsio* reg region.\n"); + return -ENOMEM; } imxpriv->epcs_tx_clk = devm_clk_get(dev, "epcs_tx"); @@ -1031,19 +1309,43 @@ static int imx8_sata_probe(struct device *dev, struct imx_ahci_priv *imxpriv) dev_err(dev, "can't get phy_apbclk clock.\n"); return PTR_ERR(imxpriv->phy_apbclk); } + imxpriv->per_clk0 = devm_clk_get(dev, "per_clk0"); + if (IS_ERR(imxpriv->per_clk0)) { + dev_err(dev, "can't get per_clk0 clock.\n"); + return PTR_ERR(imxpriv->per_clk0); + } + imxpriv->per_clk1 = devm_clk_get(dev, "per_clk1"); + if (IS_ERR(imxpriv->per_clk1)) { + dev_err(dev, "can't get per_clk1 clock.\n"); + return PTR_ERR(imxpriv->per_clk1); + } + imxpriv->per_clk2 = devm_clk_get(dev, "per_clk2"); + if (IS_ERR(imxpriv->per_clk2)) { + dev_err(dev, "can't get per_clk2 clock.\n"); + return PTR_ERR(imxpriv->per_clk2); + } + imxpriv->per_clk3 = devm_clk_get(dev, "per_clk3"); + if (IS_ERR(imxpriv->per_clk3)) { + dev_err(dev, "can't get per_clk3 clock.\n"); + return PTR_ERR(imxpriv->per_clk3); + } + imxpriv->per_clk4 = devm_clk_get(dev, "per_clk4"); + if (IS_ERR(imxpriv->per_clk4)) { + dev_err(dev, "can't get per_clk4 clock.\n"); + return PTR_ERR(imxpriv->per_clk4); + } + imxpriv->per_clk5 = devm_clk_get(dev, "per_clk5"); + if (IS_ERR(imxpriv->per_clk5)) { + dev_err(dev, "can't get per_clk5 clock.\n"); + return PTR_ERR(imxpriv->per_clk5); + } /* Fetch GPIO, then enable the external OSC */ imxpriv->clkreq_gpio = of_get_named_gpio(np, "clkreq-gpio", 0); if (gpio_is_valid(imxpriv->clkreq_gpio)) { - ret = devm_gpio_request_one(dev, imxpriv->clkreq_gpio, + devm_gpio_request_one(dev, imxpriv->clkreq_gpio, GPIOF_OUT_INIT_LOW, "SATA CLKREQ"); - if (ret == -EBUSY) { - dev_info(dev, "clkreq had been initialized.\n"); - } else if (ret) { - dev_err(dev, "%d unable to get clkreq.\n", ret); - return ret; - } } else if (imxpriv->clkreq_gpio == -EPROBE_DEFER) { return imxpriv->clkreq_gpio; } @@ -1051,6 +1353,104 @@ static int imx8_sata_probe(struct device *dev, struct imx_ahci_priv *imxpriv) return 0; } +static ssize_t ahci_bist_pattern_show(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + u32 bist_pattern; + struct ahci_host_priv *hpriv = dev_get_drvdata(dev); + + bist_pattern = readl(hpriv->mmio + IMX8QM_SATA_PPCFG_OFFSET); + bist_pattern = bist_pattern & IMX8QM_SATA_PPCFG_BIST_PATTERN_MASK; + bist_pattern = bist_pattern >> IMX8QM_SATA_PPCFG_BIST_PATTERN_OFFSET; + return sprintf(buf, "imx-ahci-bist-pattern %s%s%s%s.\n", + (BIT(0) << bist_pattern) & BIT(0) ? "LBP " : "", + (BIT(0) << bist_pattern) & BIT(1) ? "LFTP " : "", + (BIT(0) << bist_pattern) & BIT(2) ? "MFTP " : "", + (BIT(0) << bist_pattern) & BIT(3) ? "HFTP " : ""); +} + +static ssize_t ahci_bist_pattern_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + int ret; + u32 bist_pattern, val, timeout; + struct ahci_host_priv *hpriv = dev_get_drvdata(dev); + + ret = sscanf(buf, "%x\n", &bist_pattern); + if (ret != 1) + return -EINVAL; + if ((bist_pattern > 3)) { + dev_err(dev, "LBP 0, LFTP 1, MFTP 2, HFTP 3.\n"); + return -1; + } + dev_info(dev, "Try to enable %s%s%s%s pattern.\n", + (BIT(0) << bist_pattern) & BIT(0) ? "LBP " : "", + (BIT(0) << bist_pattern) & BIT(1) ? "LFTP " : "", + (BIT(0) << bist_pattern) & BIT(2) ? "MFTP " : "", + (BIT(0) << bist_pattern) & BIT(3) ? "HFTP " : ""); + + dev_info(dev, "Clear BIST enable.\n"); + val = readl(hpriv->mmio + IMX8QM_SATA_PPCFG_OFFSET); + writel(val & (~IMX8QM_SATA_PPCFG_BIST_PATTERN_EN), + hpriv->mmio + IMX8QM_SATA_PPCFG_OFFSET); + + /* put device into listen mode, first set PxSCTL.DET to 0 */ + dev_info(dev, "Turn off device detection.\n"); + val = readl(hpriv->mmio + 0x100 + PORT_SCR_CTL); + writel(val & ~0xf, hpriv->mmio + 0x100 + PORT_SCR_CTL); + + dev_info(dev, "Force phy ready, then wait.\n"); + val = readl(hpriv->mmio + IMX8QM_SATA_PPCFG_OFFSET); + writel(val | IMX8QM_SATA_PPCFG_FORCE_PHY_RDY, + hpriv->mmio + IMX8QM_SATA_PPCFG_OFFSET); + + timeout = 1000; + do { + val = readl(hpriv->mmio + 0x100 + PORT_SCR_STAT); + if ((val & 0xf) > 1) + break; + mdelay(1); + } while (--timeout); + if (timeout == 0) + dev_info(dev, "Error, wait for phy ready timeout.\n"); + else + dev_info(dev, "Get phy ready, and Gen%d mode is set.\n", + (val & 0xF0) >> 4); + + /* clear SError */ + dev_info(dev, "Clear error reg.\n"); + val = readl(hpriv->mmio + 0x100 + PORT_SCR_ERR); + writel(val, hpriv->mmio + 0x100 + PORT_SCR_ERR); + + dev_info(dev, "Select BIST pattern.\n"); + val = readl(hpriv->mmio + IMX8QM_SATA_PPCFG_OFFSET); + val &= (~IMX8QM_SATA_PPCFG_BIST_PATTERN_MASK); + val |= (bist_pattern << IMX8QM_SATA_PPCFG_BIST_PATTERN_OFFSET); + writel(val, hpriv->mmio + IMX8QM_SATA_PPCFG_OFFSET); + + dev_info(dev, "Set no aligns in BIST pattern.\n"); + val = readl(hpriv->mmio + IMX8QM_SATA_PPCFG_OFFSET); + writel(val | IMX8QM_SATA_PPCFG_BIST_PATTERN_NOALIGNS, + hpriv->mmio + IMX8QM_SATA_PPCFG_OFFSET); + + dev_info(dev, "BIST enable.\n"); + val = readl(hpriv->mmio + IMX8QM_SATA_PPCFG_OFFSET); + writel(val | IMX8QM_SATA_PPCFG_BIST_PATTERN_EN, + hpriv->mmio + IMX8QM_SATA_PPCFG_OFFSET); + + return count; +} + +static DEVICE_ATTR_RW(ahci_bist_pattern); + +static struct attribute *imx_ahci_attrs[] = { + &dev_attr_ahci_bist_pattern.attr, + NULL +}; + +static struct attribute_group imx_ahci_attrgroup = { + .attrs = imx_ahci_attrs, +}; static int imx_ahci_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1085,12 +1485,6 @@ static int imx_ahci_probe(struct platform_device *pdev) return PTR_ERR(imxpriv->sata_ref_clk); } - imxpriv->ahb_clk = devm_clk_get(dev, "ahb"); - if (IS_ERR(imxpriv->ahb_clk)) { - dev_err(dev, "can't get ahb clock.\n"); - return PTR_ERR(imxpriv->ahb_clk); - } - if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) { u32 reg_value; @@ -1167,20 +1561,68 @@ static int imx_ahci_probe(struct platform_device *pdev) writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL); } - reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000; - writel(reg_val, hpriv->mmio + IMX_TIMER1MS); + imxpriv->ahb_clk = devm_clk_get(dev, "ahb"); + if (IS_ERR(imxpriv->ahb_clk)) { + dev_info(dev, "no ahb clock.\n"); + } else { + /* + * AHB clock is only used to configure the vendor specified + * TIMER1MS register. Set it if the AHB clock is defined. + */ + reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000; + writel(reg_val, hpriv->mmio + IMX_TIMER1MS); + } - ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info, - &ahci_platform_sht); - if (ret) - goto disable_sata; + /* + * Due to IP bug on the Synopsis 3.00 SATA version, + * which is present on mx6q, and not on mx53, + * we should use sg_tablesize = 1 for reliable operation + */ + if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) { + dma_addr_t dma; - return 0; + ahci_platform_sht.sg_tablesize = 1; + + sg_io_buffer_hack = dma_alloc_coherent(dev, 0x10000, + &dma, GFP_KERNEL); + if (!sg_io_buffer_hack) { + ret = -ENOMEM; + goto disable_sata; + } + } + + if (imxpriv->type == AHCI_IMX8QM && bist_enable) { + dev_info(dev, "AHCI SATA compliance test patterns.\n"); + ret = clk_prepare_enable(imxpriv->phy_pclk0); + if (ret < 0) + dev_err(dev, "can't enable phy pclk0.\n"); + ret = clk_prepare_enable(imxpriv->phy_pclk1); + if (ret < 0) + dev_err(dev, "can't enable phy pclk1.\n"); + ret = clk_prepare_enable(imxpriv->phy_apbclk); + if (ret < 0) + dev_err(dev, "can't get sata_phy_apbclk clock.\n"); + + dev_set_drvdata(dev, hpriv); + ret = sysfs_create_group(&pdev->dev.kobj, &imx_ahci_attrgroup); + if (ret) + ret = -EINVAL; + dev_info(dev, "Register AHCI SATA BIST sysfile callback.\n"); + } else { + + ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info, + &ahci_platform_sht); + if (ret) + goto disable_sata; + } + + return ret; disable_sata: imx_sata_disable(hpriv); disable_clk: clk_disable_unprepare(imxpriv->sata_clk); + return ret; } @@ -1234,7 +1676,21 @@ static struct platform_driver imx_ahci_driver = { .pm = &ahci_imx_pm_ops, }, }; -module_platform_driver(imx_ahci_driver); + +static int __init imx_ahci_init(void) +{ + int ret; + + ret = platform_driver_register(&imx_ahci_driver); + if (ret) + pr_err("Unable to initialize imx ahci driver\n"); + else + pr_info("imx ahci driver is registered.\n"); + + return ret; +} + +device_initcall(imx_ahci_init); MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver"); MODULE_AUTHOR("Richard Zhu "); diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c index a330307d320152..e057164ac9bbce 100644 --- a/drivers/ata/ahci_qoriq.c +++ b/drivers/ata/ahci_qoriq.c @@ -6,6 +6,7 @@ * Tang Yuantian */ +#include #include #include #include @@ -47,6 +48,27 @@ #define ECC_DIS_ARMV8_CH2 0x80000000 #define ECC_DIS_LS1088A 0x40000000 +/* errata for lx2160 */ +#define RCWSR29_BASE 0x1E00170 +#define SERDES2_BASE 0x1EB0000 +#define DEVICE_CONFIG_REG_BASE 0x1E00000 +#define SERDES2_LNAX_RX_CR(x) (0x840 + (0x100 * (x))) +#define SERDES2_LNAX_RX_CBR(x) (0x8C0 + (0x100 * (x))) +#define SYS_VER_REG 0xA4 +#define LN_RX_RST 0x80000010 +#define LN_RX_RST_DONE 0x3 +#define LN_RX_MASK 0xf +#define LX2160A_VER1 0x1 + +#define SERDES2_LNAA 0 +#define SERDES2_LNAB 1 +#define SERDES2_LNAC 2 +#define SERDES2_LNAD 3 +#define SERDES2_LNAE 4 +#define SERDES2_LNAF 5 +#define SERDES2_LNAG 6 +#define SERDES2_LNAH 7 + enum ahci_qoriq_type { AHCI_LS1021A, AHCI_LS1028A, @@ -80,6 +102,132 @@ static const struct of_device_id ahci_qoriq_of_match[] = { }; MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match); +static const struct acpi_device_id ahci_qoriq_acpi_match[] = { + {"NXP0004", .driver_data = (kernel_ulong_t)AHCI_LX2160A}, + { } +}; +MODULE_DEVICE_TABLE(acpi, ahci_qoriq_acpi_match); + +static void fsl_sata_errata_379364(bool select) +{ + int val = 0; + void __iomem *rcw_base = NULL; + void __iomem *serdes_base = NULL; + void __iomem *dev_con_base = NULL; + + if (select) { + dev_con_base = ioremap(DEVICE_CONFIG_REG_BASE, PAGE_SIZE); + if (!dev_con_base) + return; + + val = (readl(dev_con_base + SYS_VER_REG) & GENMASK(7, 4)) >> 4; + if (val != LX2160A_VER1) + goto dev_unmap; + + /* + * Add few msec delay. + * Check for corresponding serdes lane RST_DONE . + * apply lane reset. + */ + + serdes_base = ioremap(SERDES2_BASE, PAGE_SIZE); + if (!serdes_base) + goto dev_unmap; + + rcw_base = ioremap(RCWSR29_BASE, PAGE_SIZE); + if (!rcw_base) + goto serdes_unmap; + + msleep(20); + + val = (readl(rcw_base) & GENMASK(25, 21)) >> 21; + + switch (val) { + case 1: + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAC)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAC)); + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAD)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAD)); + break; + + case 4: + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAG)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAG)); + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAH)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAH)); + break; + + case 5: + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAE)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAE)); + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAF)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAF)); + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAG)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAG)); + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAH)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAH)); + break; + + case 8: + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAC)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAC)); + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAD)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAD)); + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAE)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAE)); + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAF)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAF)); + break; + + case 12: + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAG)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAG)); + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAH)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAH)); + break; + + default: + break; + } + } else { + return; + } + + iounmap(rcw_base); +serdes_unmap: + iounmap(serdes_base); +dev_unmap: + iounmap(dev_con_base); +} + static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class, unsigned long deadline) { @@ -95,6 +243,7 @@ static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class, bool online; int rc; bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A); + bool lx2160a_workaround = (qoriq_priv->type == AHCI_LX2160A); DPRINTK("ENTER\n"); @@ -121,6 +270,8 @@ static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class, tf.command = ATA_BUSY; ata_tf_to_fis(&tf, 0, 0, d2h_fis); + fsl_sata_errata_379364(lx2160a_workaround); + rc = sata_link_hardreset(link, timing, deadline, &online, ahci_check_ready); @@ -255,6 +406,7 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv) static int ahci_qoriq_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; + const struct acpi_device_id *acpi_id; struct device *dev = &pdev->dev; struct ahci_host_priv *hpriv; struct ahci_qoriq_priv *qoriq_priv; @@ -267,19 +419,21 @@ static int ahci_qoriq_probe(struct platform_device *pdev) return PTR_ERR(hpriv); of_id = of_match_node(ahci_qoriq_of_match, np); - if (!of_id) + acpi_id = acpi_match_device(ahci_qoriq_acpi_match, &pdev->dev); + if (!(of_id || acpi_id)) return -ENODEV; qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL); if (!qoriq_priv) return -ENOMEM; - qoriq_priv->type = (enum ahci_qoriq_type)of_id->data; + if (of_id) + qoriq_priv->type = (enum ahci_qoriq_type)of_id->data; + else + qoriq_priv->type = (enum ahci_qoriq_type)acpi_id->driver_data; if (unlikely(!ecc_initialized)) { - res = platform_get_resource_byname(pdev, - IORESOURCE_MEM, - "sata-ecc"); + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); if (res) { qoriq_priv->ecc_addr = devm_ioremap_resource(dev, res); @@ -288,7 +442,8 @@ static int ahci_qoriq_probe(struct platform_device *pdev) } } - qoriq_priv->is_dmacoherent = of_dma_is_coherent(np); + if (device_get_dma_attr(&pdev->dev) == DEV_DMA_COHERENT) + qoriq_priv->is_dmacoherent = true; rc = ahci_platform_enable_resources(hpriv); if (rc) @@ -354,6 +509,7 @@ static struct platform_driver ahci_qoriq_driver = { .driver = { .name = DRV_NAME, .of_match_table = ahci_qoriq_of_match, + .acpi_match_table = ahci_qoriq_acpi_match, .pm = &ahci_qoriq_pm_ops, }, }; diff --git a/drivers/base/core.c b/drivers/base/core.c index 94df2ba1bbed7c..8a973958d11a08 100644 --- a/drivers/base/core.c +++ b/drivers/base/core.c @@ -1320,6 +1320,34 @@ static ssize_t online_store(struct device *dev, struct device_attribute *attr, } static DEVICE_ATTR_RW(online); +static ssize_t suppliers_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct device_link *link; + size_t count = 0; + + list_for_each_entry(link, &dev->links.suppliers, c_node) + count += scnprintf(buf + count, PAGE_SIZE - count, "%s\n", + dev_name(link->supplier)); + + return count; +} +static DEVICE_ATTR_RO(suppliers); + +static ssize_t consumers_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct device_link *link; + size_t count = 0; + + list_for_each_entry(link, &dev->links.consumers, s_node) + count += scnprintf(buf + count, PAGE_SIZE - count, "%s\n", + dev_name(link->consumer)); + + return count; +} +static DEVICE_ATTR_RO(consumers); + int device_add_groups(struct device *dev, const struct attribute_group **groups) { return sysfs_create_groups(&dev->kobj, groups); @@ -1491,8 +1519,20 @@ static int device_add_attrs(struct device *dev) goto err_remove_dev_groups; } + error = device_create_file(dev, &dev_attr_suppliers); + if (error) + goto err_remove_online; + + error = device_create_file(dev, &dev_attr_consumers); + if (error) + goto err_remove_suppliers; + return 0; + err_remove_suppliers: + device_remove_file(dev, &dev_attr_suppliers); + err_remove_online: + device_remove_file(dev, &dev_attr_online); err_remove_dev_groups: device_remove_groups(dev, dev->groups); err_remove_type_groups: @@ -1510,6 +1550,8 @@ static void device_remove_attrs(struct device *dev) struct class *class = dev->class; const struct device_type *type = dev->type; + device_remove_file(dev, &dev_attr_consumers); + device_remove_file(dev, &dev_attr_suppliers); device_remove_file(dev, &dev_attr_online); device_remove_groups(dev, dev->groups); diff --git a/drivers/base/dd.c b/drivers/base/dd.c index 1d5dd37f3abe46..f8746aa3c14bcf 100644 --- a/drivers/base/dd.c +++ b/drivers/base/dd.c @@ -102,14 +102,6 @@ static void deferred_probe_work_func(struct work_struct *work) */ mutex_unlock(&deferred_probe_mutex); - /* - * Force the device to the end of the dpm_list since - * the PM code assumes that the order we add things to - * the list is a good order for suspend but deferred - * probe makes that very unsafe. - */ - device_pm_move_to_tail(dev); - dev_dbg(dev, "Retrying from deferred list\n"); bus_probe_device(dev); mutex_lock(&deferred_probe_mutex); @@ -380,6 +372,14 @@ static void driver_bound(struct device *dev) device_pm_check_callbacks(dev); + /* + * Force the device to the end of the dpm_list since + * the PM code assumes that the order we add things to + * the list is a good order for suspend but deferred + * probe makes that very unsafe. + */ + device_pm_move_to_tail(dev); + /* * Make sure the device is no longer in one of the deferred lists and * kick off retrying all pending devices diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c index 8428d02cfe5896..3dadc7df9aedca 100644 --- a/drivers/base/power/domain.c +++ b/drivers/base/power/domain.c @@ -448,6 +448,9 @@ static int _genpd_power_off(struct generic_pm_domain *genpd, bool timed) if (!genpd->power_off) return 0; + if (atomic_read(&genpd->sd_count) > 0) + return -EBUSY; + if (!timed) return genpd->power_off(genpd); @@ -497,6 +500,7 @@ static int genpd_power_off(struct generic_pm_domain *genpd, bool one_dev_on, struct pm_domain_data *pdd; struct gpd_link *link; unsigned int not_suspended = 0; + int ret; /* * Do not try to power off the domain in the following situations: @@ -544,24 +548,21 @@ static int genpd_power_off(struct generic_pm_domain *genpd, bool one_dev_on, if (!genpd->gov) genpd->state_idx = 0; - if (genpd->power_off) { - int ret; + /* Choose the deepest state if no devices using this domain */ + if (!genpd->device_count) + genpd->state_idx = genpd->state_count - 1; - if (atomic_read(&genpd->sd_count) > 0) - return -EBUSY; - - /* - * If sd_count > 0 at this point, one of the subdomains hasn't - * managed to call genpd_power_on() for the master yet after - * incrementing it. In that case genpd_power_on() will wait - * for us to drop the lock, so we can call .power_off() and let - * the genpd_power_on() restore power for us (this shouldn't - * happen very often). - */ - ret = _genpd_power_off(genpd, true); - if (ret) - return ret; - } + /* + * If sd_count > 0 at this point, one of the subdomains hasn't + * managed to call genpd_power_on() for the master yet after + * incrementing it. In that case genpd_power_on() will wait + * for us to drop the lock, so we can call .power_off() and let + * the genpd_power_on() restore power for us (this shouldn't + * happen very often). + */ + ret = _genpd_power_off(genpd, true); + if (ret) + return ret; genpd->status = GPD_STATE_POWER_OFF; genpd_update_accounting(genpd); @@ -960,11 +961,20 @@ static void genpd_sync_power_off(struct generic_pm_domain *genpd, bool use_lock, { struct gpd_link *link; - if (!genpd_status_on(genpd) || genpd_is_always_on(genpd)) + /* + * Give the power domain a chance to switch to the deepest state in + * case it's already off but in an intermediate low power state. + */ + genpd->state_idx_saved = genpd->state_idx; + + if (genpd_is_always_on(genpd)) return; - if (genpd->suspended_count != genpd->device_count - || atomic_read(&genpd->sd_count) > 0) + if (!genpd_status_on(genpd) && + genpd->state_idx == (genpd->state_count - 1)) + return; + + if (genpd->suspended_count != genpd->device_count) return; /* Choose the deepest state when suspending */ @@ -972,6 +982,9 @@ static void genpd_sync_power_off(struct generic_pm_domain *genpd, bool use_lock, if (_genpd_power_off(genpd, false)) return; + if (genpd->status == GPD_STATE_POWER_OFF) + return; + genpd->status = GPD_STATE_POWER_OFF; list_for_each_entry(link, &genpd->slave_links, slave_node) { @@ -1019,6 +1032,9 @@ static void genpd_sync_power_on(struct generic_pm_domain *genpd, bool use_lock, _genpd_power_on(genpd, false); + /* restore save power domain state after resume */ + genpd->state_idx = genpd->state_idx_saved; + genpd->status = GPD_STATE_ACTIVE; } @@ -1829,7 +1845,7 @@ int pm_genpd_init(struct generic_pm_domain *genpd, return ret; } } else if (!gov && genpd->state_count > 1) { - pr_warn("%s: no governor for states\n", genpd->name); + pr_debug("%s: no governor for states\n", genpd->name); } device_initialize(&genpd->dev); diff --git a/drivers/base/power/wakeup.c b/drivers/base/power/wakeup.c index 92f0960e901456..6dffcb71b86c9f 100644 --- a/drivers/base/power/wakeup.c +++ b/drivers/base/power/wakeup.c @@ -249,6 +249,60 @@ void wakeup_source_unregister(struct wakeup_source *ws) } EXPORT_SYMBOL_GPL(wakeup_source_unregister); +/** + * wakeup_sources_read_lock - Lock wakeup source list for read. + * + * Returns an index of srcu lock for struct wakeup_srcu. + * This index must be passed to the matching wakeup_sources_read_unlock(). + */ +int wakeup_sources_read_lock(void) +{ + return srcu_read_lock(&wakeup_srcu); +} +EXPORT_SYMBOL_GPL(wakeup_sources_read_lock); + +/** + * wakeup_sources_read_unlock - Unlock wakeup source list. + * @idx: return value from corresponding wakeup_sources_read_lock() + */ +void wakeup_sources_read_unlock(int idx) +{ + srcu_read_unlock(&wakeup_srcu, idx); +} +EXPORT_SYMBOL_GPL(wakeup_sources_read_unlock); + +/** + * wakeup_sources_walk_start - Begin a walk on wakeup source list + * + * Returns first object of the list of wakeup sources. + * + * Note that to be safe, wakeup sources list needs to be locked by calling + * wakeup_source_read_lock() for this. + */ +struct wakeup_source *wakeup_sources_walk_start(void) +{ + struct list_head *ws_head = &wakeup_sources; + + return list_entry_rcu(ws_head->next, struct wakeup_source, entry); +} +EXPORT_SYMBOL_GPL(wakeup_sources_walk_start); + +/** + * wakeup_sources_walk_next - Get next wakeup source from the list + * @ws: Previous wakeup source object + * + * Note that to be safe, wakeup sources list needs to be locked by calling + * wakeup_source_read_lock() for this. + */ +struct wakeup_source *wakeup_sources_walk_next(struct wakeup_source *ws) +{ + struct list_head *ws_head = &wakeup_sources; + + return list_next_or_null_rcu(ws_head, &ws->entry, + struct wakeup_source, entry); +} +EXPORT_SYMBOL_GPL(wakeup_sources_walk_next); + /** * device_wakeup_attach - Attach a wakeup source object to a device object. * @dev: Device to handle. diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c index 927ebde1607be8..f4e4bf0b571b41 100644 --- a/drivers/base/regmap/regmap.c +++ b/drivers/base/regmap/regmap.c @@ -1140,8 +1140,6 @@ struct regmap *__regmap_init(struct device *dev, ret = regmap_attach_dev(dev, map, config); if (ret != 0) goto err_regcache; - } else { - regmap_debugfs_init(map, config->name); } return map; diff --git a/drivers/bus/fsl-mc/Kconfig b/drivers/bus/fsl-mc/Kconfig index c23c77c9b7057e..cde6f408b7b4c6 100644 --- a/drivers/bus/fsl-mc/Kconfig +++ b/drivers/bus/fsl-mc/Kconfig @@ -14,3 +14,10 @@ config FSL_MC_BUS architecture. The fsl-mc bus driver handles discovery of DPAA2 objects (which are represented as Linux devices) and binding objects to drivers. + +config FSL_MC_UAPI_SUPPORT + bool "Management Complex (MC) userspace support" + depends on FSL_MC_BUS + help + Provides userspace support for creating/destroying/configuring + DPAA2 objects in the Management Complex. diff --git a/drivers/bus/fsl-mc/Makefile b/drivers/bus/fsl-mc/Makefile index 3c518c7e8374b1..4ae292a30e5304 100644 --- a/drivers/bus/fsl-mc/Makefile +++ b/drivers/bus/fsl-mc/Makefile @@ -16,3 +16,6 @@ mc-bus-driver-objs := fsl-mc-bus.o \ fsl-mc-allocator.o \ fsl-mc-msi.o \ dpmcp.o + +# MC userspace support +obj-$(CONFIG_FSL_MC_UAPI_SUPPORT) += fsl-mc-uapi.o diff --git a/drivers/bus/fsl-mc/dprc-driver.c b/drivers/bus/fsl-mc/dprc-driver.c index 52c7e15143d6d6..0c9b712536005c 100644 --- a/drivers/bus/fsl-mc/dprc-driver.c +++ b/drivers/bus/fsl-mc/dprc-driver.c @@ -3,6 +3,7 @@ * Freescale data path resource container (DPRC) driver * * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2019 NXP * Author: German Rivera * */ @@ -156,6 +157,8 @@ static void check_plugged_state_change(struct fsl_mc_device *mc_dev, * dprc_add_new_devices - Adds devices to the logical bus for a DPRC * * @mc_bus_dev: pointer to the fsl-mc device that represents a DPRC object + * @driver_override: driver override to apply to new objects found in the + * DPRC, or NULL, if none. * @obj_desc_array: array of device descriptors for child devices currently * present in the physical DPRC. * @num_child_objects_in_mc: number of entries in obj_desc_array @@ -165,6 +168,7 @@ static void check_plugged_state_change(struct fsl_mc_device *mc_dev, * in the physical DPRC. */ static void dprc_add_new_devices(struct fsl_mc_device *mc_bus_dev, + const char *driver_override, struct fsl_mc_obj_desc *obj_desc_array, int num_child_objects_in_mc) { @@ -189,7 +193,7 @@ static void dprc_add_new_devices(struct fsl_mc_device *mc_bus_dev, } error = fsl_mc_device_add(obj_desc, NULL, &mc_bus_dev->dev, - &child_dev); + driver_override, &child_dev); if (error < 0) continue; } @@ -199,6 +203,10 @@ static void dprc_add_new_devices(struct fsl_mc_device *mc_bus_dev, * dprc_scan_objects - Discover objects in a DPRC * * @mc_bus_dev: pointer to the fsl-mc device that represents a DPRC object + * @driver_override: driver override to apply to new objects found in the + * DPRC, or NULL, if none. + * @alloc_interrupts: if true the function allocates the interrupt pool, + * otherwise the interrupt allocation is delayed * @total_irq_count: If argument is provided the function populates the * total number of IRQs created by objects in the DPRC. * @@ -214,8 +222,10 @@ static void dprc_add_new_devices(struct fsl_mc_device *mc_bus_dev, * populated before they can get allocation requests from probe callbacks * of the device drivers for the non-allocatable devices. */ -static int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev, - unsigned int *total_irq_count) +int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev, + const char *driver_override, + bool alloc_interrupts, + unsigned int *total_irq_count) { int num_child_objects; int dprc_get_obj_failures; @@ -296,26 +306,27 @@ static int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev, * Allocate IRQ's before binding the scanned devices with their * respective drivers. */ - if (dev_get_msi_domain(&mc_bus_dev->dev) && !mc_bus->irq_resources) { - if (irq_count > FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS) { - dev_warn(&mc_bus_dev->dev, - "IRQs needed (%u) exceed IRQs preallocated (%u)\n", - irq_count, FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS); - } + if (alloc_interrupts) { + if (dev_get_msi_domain(&mc_bus_dev->dev) && !mc_bus->irq_resources) { + if (irq_count > FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS) { + dev_warn(&mc_bus_dev->dev, + "IRQs needed (%u) exceed IRQs preallocated (%u)\n", + irq_count, FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS); + } - error = fsl_mc_populate_irq_pool(mc_bus, - FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS); - if (error < 0) - return error; + error = fsl_mc_populate_irq_pool(mc_bus, + FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS); + if (error < 0) + return error; + } } - if (total_irq_count) *total_irq_count = irq_count; dprc_remove_devices(mc_bus_dev, child_obj_desc_array, num_child_objects); - dprc_add_new_devices(mc_bus_dev, child_obj_desc_array, + dprc_add_new_devices(mc_bus_dev, driver_override, child_obj_desc_array, num_child_objects); if (child_obj_desc_array) @@ -344,7 +355,7 @@ static int dprc_scan_container(struct fsl_mc_device *mc_bus_dev) * Discover objects in the DPRC: */ mutex_lock(&mc_bus->scan_mutex); - error = dprc_scan_objects(mc_bus_dev, NULL); + error = dprc_scan_objects(mc_bus_dev, NULL, true, NULL); mutex_unlock(&mc_bus->scan_mutex); if (error < 0) { fsl_mc_cleanup_all_resource_pools(mc_bus_dev); @@ -354,6 +365,33 @@ static int dprc_scan_container(struct fsl_mc_device *mc_bus_dev) return 0; } +static ssize_t rescan_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct fsl_mc_device *root_mc_dev; + struct fsl_mc_bus *root_mc_bus; + unsigned long val; + + if (!fsl_mc_is_root_dprc(dev)) + return -EINVAL; + + root_mc_dev = to_fsl_mc_device(dev); + root_mc_bus = to_fsl_mc_bus(root_mc_dev); + + if (kstrtoul(buf, 0, &val) < 0) + return -EINVAL; + + if (val) { + mutex_lock(&root_mc_bus->scan_mutex); + dprc_scan_objects(root_mc_dev, NULL, true, NULL); + mutex_unlock(&root_mc_bus->scan_mutex); + } + + return count; +} +static DEVICE_ATTR_WO(rescan); + /** * dprc_irq0_handler - Regular ISR for DPRC interrupt 0 * @@ -415,7 +453,7 @@ static irqreturn_t dprc_irq0_handler_thread(int irq_num, void *arg) DPRC_IRQ_EVENT_OBJ_CREATED)) { unsigned int irq_count; - error = dprc_scan_objects(mc_dev, &irq_count); + error = dprc_scan_objects(mc_dev, NULL, true, &irq_count); if (error < 0) { /* * If the error is -ENXIO, we ignore it, as it indicates @@ -446,8 +484,9 @@ static irqreturn_t dprc_irq0_handler_thread(int irq_num, void *arg) /* * Disable and clear interrupt for a given DPRC object */ -static int disable_dprc_irq(struct fsl_mc_device *mc_dev) +int disable_dprc_irq(struct fsl_mc_device *mc_dev) { + struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev); int error; struct fsl_mc_io *mc_io = mc_dev->mc_io; @@ -484,9 +523,18 @@ static int disable_dprc_irq(struct fsl_mc_device *mc_dev) return error; } + mc_bus->irq_enabled = 0; + return 0; } +int get_dprc_irq_state(struct fsl_mc_device *mc_dev) +{ + struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev); + + return mc_bus->irq_enabled; +} + static int register_dprc_irq_handler(struct fsl_mc_device *mc_dev) { int error; @@ -513,8 +561,9 @@ static int register_dprc_irq_handler(struct fsl_mc_device *mc_dev) return 0; } -static int enable_dprc_irq(struct fsl_mc_device *mc_dev) +int enable_dprc_irq(struct fsl_mc_device *mc_dev) { + struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev); int error; /* @@ -542,6 +591,8 @@ static int enable_dprc_irq(struct fsl_mc_device *mc_dev) return error; } + mc_bus->irq_enabled = 1; + return 0; } @@ -647,6 +698,12 @@ static int dprc_probe(struct fsl_mc_device *mc_dev) } else { dev_set_msi_domain(&mc_dev->dev, mc_msi_domain); msi_domain_set = true; + + error = fsl_mc_uapi_create_device_file(mc_bus); + if (error < 0) { + error = -EPROBE_DEFER; + goto error_cleanup_msi_domain; + } } } @@ -654,7 +711,7 @@ static int dprc_probe(struct fsl_mc_device *mc_dev) &mc_dev->mc_handle); if (error < 0) { dev_err(&mc_dev->dev, "dprc_open() failed: %d\n", error); - goto error_cleanup_msi_domain; + goto error_cleanup_uapi; } error = dprc_get_attributes(mc_dev->mc_io, 0, mc_dev->mc_handle, @@ -686,6 +743,13 @@ static int dprc_probe(struct fsl_mc_device *mc_dev) mutex_init(&mc_bus->scan_mutex); + error = device_create_file(&mc_dev->dev, &dev_attr_rescan); + if (error < 0) { + dev_err(&mc_dev->dev, "device_create_file() failed: %d\n", + error); + goto error_cleanup_open; + } + /* * Discover MC objects in DPRC object: */ @@ -706,6 +770,10 @@ static int dprc_probe(struct fsl_mc_device *mc_dev) error_cleanup_open: (void)dprc_close(mc_dev->mc_io, 0, mc_dev->mc_handle); +error_cleanup_uapi: + if (fsl_mc_is_root_dprc(&mc_dev->dev)) + fsl_mc_uapi_remove_device_file(mc_bus); + error_cleanup_msi_domain: if (msi_domain_set) dev_set_msi_domain(&mc_dev->dev, NULL); @@ -774,8 +842,12 @@ static int dprc_remove(struct fsl_mc_device *mc_dev) if (!fsl_mc_is_root_dprc(&mc_dev->dev)) { fsl_destroy_mc_io(mc_dev->mc_io); mc_dev->mc_io = NULL; + } else { + fsl_mc_uapi_remove_device_file(mc_bus); } + device_remove_file(&mc_dev->dev, &dev_attr_rescan); + dev_info(&mc_dev->dev, "DPRC device unbound from driver"); return 0; } diff --git a/drivers/bus/fsl-mc/dprc.c b/drivers/bus/fsl-mc/dprc.c index 0fe3f52ae0de8f..413353b6473ba8 100644 --- a/drivers/bus/fsl-mc/dprc.c +++ b/drivers/bus/fsl-mc/dprc.c @@ -72,6 +72,47 @@ int dprc_close(struct fsl_mc_io *mc_io, } EXPORT_SYMBOL_GPL(dprc_close); +/** + * dprc_reset_container - Reset child container. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @child_container_id: ID of the container to reset + * + * In case a software context crashes or becomes non-responsive, the parent + * may wish to reset its resources container before the software context is + * restarted. + * + * This routine informs all objects assigned to the child container that the + * container is being reset, so they may perform any cleanup operations that are + * needed. All objects handles that were owned by the child container shall be + * closed. + * + * Note that such request may be submitted even if the child software context + * has not crashed, but the resulting object cleanup operations will not be + * aware of that. + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_reset_container(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + int child_container_id) +{ + struct fsl_mc_command cmd = { 0 }; + struct dprc_cmd_reset_container *cmd_params; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_RESET_CONT, + cmd_flags, token); + cmd_params = (struct dprc_cmd_reset_container *)cmd.params; + cmd_params->child_container_id = cpu_to_le32(child_container_id); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} +EXPORT_SYMBOL_GPL(dprc_reset_container); + /** * dprc_set_irq() - Set IRQ information for the DPRC to trigger an interrupt. * @mc_io: Pointer to MC portal's I/O object @@ -281,7 +322,7 @@ int dprc_get_attributes(struct fsl_mc_io *mc_io, /* retrieve response parameters */ rsp_params = (struct dprc_rsp_get_attributes *)cmd.params; attr->container_id = le32_to_cpu(rsp_params->container_id); - attr->icid = le16_to_cpu(rsp_params->icid); + attr->icid = le32_to_cpu(rsp_params->icid); attr->options = le32_to_cpu(rsp_params->options); attr->portal_id = le32_to_cpu(rsp_params->portal_id); @@ -483,6 +524,8 @@ int dprc_get_obj_region(struct fsl_mc_io *mc_io, rsp_params = (struct dprc_rsp_get_obj_region *)cmd.params; region_desc->base_offset = le64_to_cpu(rsp_params->base_offset); region_desc->size = le32_to_cpu(rsp_params->size); + region_desc->type = rsp_params->type; + region_desc->flags = le32_to_cpu(rsp_params->flags); if (major_ver > 6 || (major_ver == 6 && minor_ver >= 3)) region_desc->base_address = le64_to_cpu(rsp_params->base_addr); else diff --git a/drivers/bus/fsl-mc/fsl-mc-allocator.c b/drivers/bus/fsl-mc/fsl-mc-allocator.c index cc7bb900f52498..9e3400b4243f9c 100644 --- a/drivers/bus/fsl-mc/fsl-mc-allocator.c +++ b/drivers/bus/fsl-mc/fsl-mc-allocator.c @@ -547,6 +547,7 @@ void fsl_mc_init_all_resource_pools(struct fsl_mc_device *mc_bus_dev) mutex_init(&res_pool->mutex); } } +EXPORT_SYMBOL_GPL(fsl_mc_init_all_resource_pools); static void fsl_mc_cleanup_resource_pool(struct fsl_mc_device *mc_bus_dev, enum fsl_mc_pool_type pool_type) @@ -571,6 +572,7 @@ void fsl_mc_cleanup_all_resource_pools(struct fsl_mc_device *mc_bus_dev) for (pool_type = 0; pool_type < FSL_MC_NUM_POOL_TYPES; pool_type++) fsl_mc_cleanup_resource_pool(mc_bus_dev, pool_type); } +EXPORT_SYMBOL_GPL(fsl_mc_cleanup_all_resource_pools); /** * fsl_mc_allocator_probe - callback invoked when an allocatable device is diff --git a/drivers/bus/fsl-mc/fsl-mc-bus.c b/drivers/bus/fsl-mc/fsl-mc-bus.c index 5c9bf2e0655203..f483ac0dedea59 100644 --- a/drivers/bus/fsl-mc/fsl-mc-bus.c +++ b/drivers/bus/fsl-mc/fsl-mc-bus.c @@ -83,6 +83,12 @@ static int fsl_mc_bus_match(struct device *dev, struct device_driver *drv) struct fsl_mc_driver *mc_drv = to_fsl_mc_driver(drv); bool found = false; + /* When driver_override is set, only bind to the matching driver */ + if (mc_dev->driver_override) { + found = !strcmp(mc_dev->driver_override, mc_drv->driver.name); + goto out; + } + if (!mc_drv->match_id_table) goto out; @@ -134,7 +140,7 @@ static int fsl_mc_dma_configure(struct device *dev) while (dev_is_fsl_mc(dma_dev)) dma_dev = dma_dev->parent; - return of_dma_configure(dev, dma_dev->of_node, 0); + return of_dma_configure(dev, dma_dev->of_node, 1); } static ssize_t modalias_show(struct device *dev, struct device_attribute *attr, @@ -147,19 +153,159 @@ static ssize_t modalias_show(struct device *dev, struct device_attribute *attr, } static DEVICE_ATTR_RO(modalias); +static ssize_t driver_override_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); + const char *driver_override, *old = mc_dev->driver_override; + char *cp; + + if (WARN_ON(dev->bus != &fsl_mc_bus_type)) + return -EINVAL; + + if (count >= (PAGE_SIZE - 1)) + return -EINVAL; + + driver_override = kstrndup(buf, count, GFP_KERNEL); + if (!driver_override) + return -ENOMEM; + + cp = strchr(driver_override, '\n'); + if (cp) + *cp = '\0'; + + if (strlen(driver_override)) { + mc_dev->driver_override = driver_override; + } else { + kfree(driver_override); + mc_dev->driver_override = NULL; + } + + kfree(old); + + return count; +} + +static ssize_t driver_override_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); + + return snprintf(buf, PAGE_SIZE, "%s\n", mc_dev->driver_override); +} +static DEVICE_ATTR_RW(driver_override); + static struct attribute *fsl_mc_dev_attrs[] = { &dev_attr_modalias.attr, + &dev_attr_driver_override.attr, NULL, }; ATTRIBUTE_GROUPS(fsl_mc_dev); +static int scan_fsl_mc_bus(struct device *dev, void *data) +{ + struct fsl_mc_device *root_mc_dev; + struct fsl_mc_bus *root_mc_bus; + + if (!fsl_mc_is_root_dprc(dev)) + goto exit; + + root_mc_dev = to_fsl_mc_device(dev); + root_mc_bus = to_fsl_mc_bus(root_mc_dev); + mutex_lock(&root_mc_bus->scan_mutex); + dprc_scan_objects(root_mc_dev, NULL, true, NULL); + mutex_unlock(&root_mc_bus->scan_mutex); + +exit: + return 0; +} + +static ssize_t rescan_store(struct bus_type *bus, + const char *buf, size_t count) +{ + unsigned long val; + + if (kstrtoul(buf, 0, &val) < 0) + return -EINVAL; + + if (val) + bus_for_each_dev(bus, NULL, NULL, scan_fsl_mc_bus); + + return count; +} +static BUS_ATTR_WO(rescan); + +static int fsl_mc_bus_set_autorescan(struct device *dev, void *data) +{ + struct fsl_mc_device *root_mc_dev; + unsigned long val; + char *buf = data; + + if (!fsl_mc_is_root_dprc(dev)) + goto exit; + + root_mc_dev = to_fsl_mc_device(dev); + + if (kstrtoul(buf, 0, &val) < 0) + return -EINVAL; + + if (val) + enable_dprc_irq(root_mc_dev); + else + disable_dprc_irq(root_mc_dev); + +exit: + return 0; +} + +static int fsl_mc_bus_get_autorescan(struct device *dev, void *data) +{ + struct fsl_mc_device *root_mc_dev; + char *buf = data; + + if (!fsl_mc_is_root_dprc(dev)) + goto exit; + + root_mc_dev = to_fsl_mc_device(dev); + + sprintf(buf, "%d\n", get_dprc_irq_state(root_mc_dev)); +exit: + return 0; +} + +static ssize_t autorescan_store(struct bus_type *bus, + const char *buf, size_t count) +{ + bus_for_each_dev(bus, NULL, (void *)buf, fsl_mc_bus_set_autorescan); + + return count; +} + +static ssize_t autorescan_show(struct bus_type *bus, char *buf) +{ + bus_for_each_dev(bus, NULL, (void *)buf, fsl_mc_bus_get_autorescan); + return strlen(buf); +} + +static BUS_ATTR_RW(autorescan); + +static struct attribute *fsl_mc_bus_attrs[] = { + &bus_attr_rescan.attr, + &bus_attr_autorescan.attr, + NULL, +}; + +ATTRIBUTE_GROUPS(fsl_mc_bus); + struct bus_type fsl_mc_bus_type = { .name = "fsl-mc", .match = fsl_mc_bus_match, .uevent = fsl_mc_bus_uevent, .dma_configure = fsl_mc_dma_configure, .dev_groups = fsl_mc_dev_groups, + .bus_groups = fsl_mc_bus_groups, }; EXPORT_SYMBOL_GPL(fsl_mc_bus_type); @@ -179,6 +325,10 @@ struct device_type fsl_mc_bus_dpsw_type = { .name = "fsl_mc_bus_dpsw" }; +struct device_type fsl_mc_bus_dpdmux_type = { + .name = "fsl_mc_bus_dpdmux" +}; + struct device_type fsl_mc_bus_dpbp_type = { .name = "fsl_mc_bus_dpbp" }; @@ -203,6 +353,26 @@ struct device_type fsl_mc_bus_dpseci_type = { .name = "fsl_mc_bus_dpseci" }; +struct device_type fsl_mc_bus_dpdcei_type = { + .name = "fsl_mc_bus_dpdcei" +}; + +struct device_type fsl_mc_bus_dpaiop_type = { + .name = "fsl_mc_bus_dpaiop" +}; + +struct device_type fsl_mc_bus_dpci_type = { + .name = "fsl_mc_bus_dpci" +}; + +struct device_type fsl_mc_bus_dpdmai_type = { + .name = "fsl_mc_bus_dpdmai" +}; + +struct device_type fsl_mc_bus_dpdbg_type = { + .name = "fsl_mc_bus_dpdbg" +}; + static struct device_type *fsl_mc_get_device_type(const char *type) { static const struct { @@ -213,12 +383,18 @@ static struct device_type *fsl_mc_get_device_type(const char *type) { &fsl_mc_bus_dpni_type, "dpni" }, { &fsl_mc_bus_dpio_type, "dpio" }, { &fsl_mc_bus_dpsw_type, "dpsw" }, + { &fsl_mc_bus_dpdmux_type, "dpdmux" }, { &fsl_mc_bus_dpbp_type, "dpbp" }, { &fsl_mc_bus_dpcon_type, "dpcon" }, { &fsl_mc_bus_dpmcp_type, "dpmcp" }, { &fsl_mc_bus_dpmac_type, "dpmac" }, { &fsl_mc_bus_dprtc_type, "dprtc" }, { &fsl_mc_bus_dpseci_type, "dpseci" }, + { &fsl_mc_bus_dpdcei_type, "dpdcei" }, + { &fsl_mc_bus_dpaiop_type, "dpaiop" }, + { &fsl_mc_bus_dpci_type, "dpci" }, + { &fsl_mc_bus_dpdmai_type, "dpdmai" }, + { &fsl_mc_bus_dpdbg_type, "dpdbg" }, { NULL, NULL } }; int i; @@ -356,8 +532,8 @@ static int mc_get_version(struct fsl_mc_io *mc_io, /** * fsl_mc_get_root_dprc - function to traverse to the root dprc */ -static void fsl_mc_get_root_dprc(struct device *dev, - struct device **root_dprc_dev) +void fsl_mc_get_root_dprc(struct device *dev, + struct device **root_dprc_dev) { if (!dev) { *root_dprc_dev = NULL; @@ -369,6 +545,7 @@ static void fsl_mc_get_root_dprc(struct device *dev, *root_dprc_dev = (*root_dprc_dev)->parent; } } +EXPORT_SYMBOL_GPL(fsl_mc_get_root_dprc); static int get_dprc_attr(struct fsl_mc_io *mc_io, int container_id, struct dprc_attributes *attr) @@ -398,7 +575,7 @@ static int get_dprc_attr(struct fsl_mc_io *mc_io, } static int get_dprc_icid(struct fsl_mc_io *mc_io, - int container_id, u16 *icid) + int container_id, u32 *icid) { struct dprc_attributes attr; int error; @@ -510,11 +687,8 @@ static int fsl_mc_device_get_mmio_regions(struct fsl_mc_device *mc_dev, regions[i].end = regions[i].start + region_desc.size - 1; regions[i].name = "fsl-mc object MMIO region"; - regions[i].flags = IORESOURCE_IO; - if (region_desc.flags & DPRC_REGION_CACHEABLE) - regions[i].flags |= IORESOURCE_CACHEABLE; - if (region_desc.flags & DPRC_REGION_SHAREABLE) - regions[i].flags |= IORESOURCE_MEM; + regions[i].flags = region_desc.flags & IORESOURCE_BITS; + regions[i].flags |= IORESOURCE_MEM; } mc_dev->regions = regions; @@ -556,6 +730,7 @@ static void fsl_mc_device_release(struct device *dev) int fsl_mc_device_add(struct fsl_mc_obj_desc *obj_desc, struct fsl_mc_io *mc_io, struct device *parent_dev, + const char *driver_override, struct fsl_mc_device **new_mc_dev) { int error; @@ -588,6 +763,19 @@ int fsl_mc_device_add(struct fsl_mc_obj_desc *obj_desc, mc_dev->obj_desc = *obj_desc; mc_dev->mc_io = mc_io; + + if (driver_override) { + /* + * We trust driver_override, so we don't need to use + * kstrndup() here + */ + mc_dev->driver_override = kstrdup(driver_override, GFP_KERNEL); + if (!mc_dev->driver_override) { + error = -ENOMEM; + goto error_cleanup_dev; + } + } + device_initialize(&mc_dev->dev); mc_dev->dev.parent = parent_dev; mc_dev->dev.bus = &fsl_mc_bus_type; @@ -694,6 +882,9 @@ EXPORT_SYMBOL_GPL(fsl_mc_device_add); */ void fsl_mc_device_remove(struct fsl_mc_device *mc_dev) { + kfree(mc_dev->driver_override); + mc_dev->driver_override = NULL; + /* * The device-specific remove callback will get invoked by device_del() */ @@ -883,7 +1074,8 @@ static int fsl_mc_bus_probe(struct platform_device *pdev) obj_desc.irq_count = 1; obj_desc.region_count = 0; - error = fsl_mc_device_add(&obj_desc, mc_io, &pdev->dev, &mc_bus_dev); + error = fsl_mc_device_add(&obj_desc, mc_io, &pdev->dev, NULL, + &mc_bus_dev); if (error < 0) goto error_cleanup_mc_io; diff --git a/drivers/bus/fsl-mc/fsl-mc-private.h b/drivers/bus/fsl-mc/fsl-mc-private.h index 020fcc04ec8bcb..28c1c1c1953e3a 100644 --- a/drivers/bus/fsl-mc/fsl-mc-private.h +++ b/drivers/bus/fsl-mc/fsl-mc-private.h @@ -69,329 +69,6 @@ int dpmcp_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); -/* - * Data Path Resource Container (DPRC) API - */ - -/* Minimal supported DPRC Version */ -#define DPRC_MIN_VER_MAJOR 6 -#define DPRC_MIN_VER_MINOR 0 - -/* DPRC command versioning */ -#define DPRC_CMD_BASE_VERSION 1 -#define DPRC_CMD_2ND_VERSION 2 -#define DPRC_CMD_ID_OFFSET 4 - -#define DPRC_CMD(id) (((id) << DPRC_CMD_ID_OFFSET) | DPRC_CMD_BASE_VERSION) -#define DPRC_CMD_V2(id) (((id) << DPRC_CMD_ID_OFFSET) | DPRC_CMD_2ND_VERSION) - -/* DPRC command IDs */ -#define DPRC_CMDID_CLOSE DPRC_CMD(0x800) -#define DPRC_CMDID_OPEN DPRC_CMD(0x805) -#define DPRC_CMDID_GET_API_VERSION DPRC_CMD(0xa05) - -#define DPRC_CMDID_GET_ATTR DPRC_CMD(0x004) - -#define DPRC_CMDID_SET_IRQ DPRC_CMD(0x010) -#define DPRC_CMDID_SET_IRQ_ENABLE DPRC_CMD(0x012) -#define DPRC_CMDID_SET_IRQ_MASK DPRC_CMD(0x014) -#define DPRC_CMDID_GET_IRQ_STATUS DPRC_CMD(0x016) -#define DPRC_CMDID_CLEAR_IRQ_STATUS DPRC_CMD(0x017) - -#define DPRC_CMDID_GET_CONT_ID DPRC_CMD(0x830) -#define DPRC_CMDID_GET_OBJ_COUNT DPRC_CMD(0x159) -#define DPRC_CMDID_GET_OBJ DPRC_CMD(0x15A) -#define DPRC_CMDID_GET_OBJ_REG DPRC_CMD(0x15E) -#define DPRC_CMDID_GET_OBJ_REG_V2 DPRC_CMD_V2(0x15E) -#define DPRC_CMDID_SET_OBJ_IRQ DPRC_CMD(0x15F) - -struct dprc_cmd_open { - __le32 container_id; -}; - -struct dprc_cmd_set_irq { - /* cmd word 0 */ - __le32 irq_val; - u8 irq_index; - u8 pad[3]; - /* cmd word 1 */ - __le64 irq_addr; - /* cmd word 2 */ - __le32 irq_num; -}; - -#define DPRC_ENABLE 0x1 - -struct dprc_cmd_set_irq_enable { - u8 enable; - u8 pad[3]; - u8 irq_index; -}; - -struct dprc_cmd_set_irq_mask { - __le32 mask; - u8 irq_index; -}; - -struct dprc_cmd_get_irq_status { - __le32 status; - u8 irq_index; -}; - -struct dprc_rsp_get_irq_status { - __le32 status; -}; - -struct dprc_cmd_clear_irq_status { - __le32 status; - u8 irq_index; -}; - -struct dprc_rsp_get_attributes { - /* response word 0 */ - __le32 container_id; - __le16 icid; - __le16 pad; - /* response word 1 */ - __le32 options; - __le32 portal_id; -}; - -struct dprc_rsp_get_obj_count { - __le32 pad; - __le32 obj_count; -}; - -struct dprc_cmd_get_obj { - __le32 obj_index; -}; - -struct dprc_rsp_get_obj { - /* response word 0 */ - __le32 pad0; - __le32 id; - /* response word 1 */ - __le16 vendor; - u8 irq_count; - u8 region_count; - __le32 state; - /* response word 2 */ - __le16 version_major; - __le16 version_minor; - __le16 flags; - __le16 pad1; - /* response word 3-4 */ - u8 type[16]; - /* response word 5-6 */ - u8 label[16]; -}; - -struct dprc_cmd_get_obj_region { - /* cmd word 0 */ - __le32 obj_id; - __le16 pad0; - u8 region_index; - u8 pad1; - /* cmd word 1-2 */ - __le64 pad2[2]; - /* cmd word 3-4 */ - u8 obj_type[16]; -}; - -struct dprc_rsp_get_obj_region { - /* response word 0 */ - __le64 pad; - /* response word 1 */ - __le64 base_offset; - /* response word 2 */ - __le32 size; - __le32 pad2; - /* response word 3 */ - __le32 flags; - __le32 pad3; - /* response word 4 */ - /* base_addr may be zero if older MC firmware is used */ - __le64 base_addr; -}; - -struct dprc_cmd_set_obj_irq { - /* cmd word 0 */ - __le32 irq_val; - u8 irq_index; - u8 pad[3]; - /* cmd word 1 */ - __le64 irq_addr; - /* cmd word 2 */ - __le32 irq_num; - __le32 obj_id; - /* cmd word 3-4 */ - u8 obj_type[16]; -}; - -/* - * DPRC API for managing and querying DPAA resources - */ -int dprc_open(struct fsl_mc_io *mc_io, - u32 cmd_flags, - int container_id, - u16 *token); - -int dprc_close(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token); - -/* DPRC IRQ events */ - -/* IRQ event - Indicates that a new object added to the container */ -#define DPRC_IRQ_EVENT_OBJ_ADDED 0x00000001 -/* IRQ event - Indicates that an object was removed from the container */ -#define DPRC_IRQ_EVENT_OBJ_REMOVED 0x00000002 -/* - * IRQ event - Indicates that one of the descendant containers that opened by - * this container is destroyed - */ -#define DPRC_IRQ_EVENT_CONTAINER_DESTROYED 0x00000010 - -/* - * IRQ event - Indicates that on one of the container's opened object is - * destroyed - */ -#define DPRC_IRQ_EVENT_OBJ_DESTROYED 0x00000020 - -/* Irq event - Indicates that object is created at the container */ -#define DPRC_IRQ_EVENT_OBJ_CREATED 0x00000040 - -/** - * struct dprc_irq_cfg - IRQ configuration - * @paddr: Address that must be written to signal a message-based interrupt - * @val: Value to write into irq_addr address - * @irq_num: A user defined number associated with this IRQ - */ -struct dprc_irq_cfg { - phys_addr_t paddr; - u32 val; - int irq_num; -}; - -int dprc_set_irq(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - u8 irq_index, - struct dprc_irq_cfg *irq_cfg); - -int dprc_set_irq_enable(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - u8 irq_index, - u8 en); - -int dprc_set_irq_mask(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - u8 irq_index, - u32 mask); - -int dprc_get_irq_status(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - u8 irq_index, - u32 *status); - -int dprc_clear_irq_status(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - u8 irq_index, - u32 status); - -/** - * struct dprc_attributes - Container attributes - * @container_id: Container's ID - * @icid: Container's ICID - * @portal_id: Container's portal ID - * @options: Container's options as set at container's creation - */ -struct dprc_attributes { - int container_id; - u16 icid; - int portal_id; - u64 options; -}; - -int dprc_get_attributes(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - struct dprc_attributes *attributes); - -int dprc_get_obj_count(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - int *obj_count); - -int dprc_get_obj(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - int obj_index, - struct fsl_mc_obj_desc *obj_desc); - -int dprc_set_obj_irq(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - char *obj_type, - int obj_id, - u8 irq_index, - struct dprc_irq_cfg *irq_cfg); - -/* Region flags */ -/* Cacheable - Indicates that region should be mapped as cacheable */ -#define DPRC_REGION_CACHEABLE 0x00000001 -#define DPRC_REGION_SHAREABLE 0x00000002 - -/** - * enum dprc_region_type - Region type - * @DPRC_REGION_TYPE_MC_PORTAL: MC portal region - * @DPRC_REGION_TYPE_QBMAN_PORTAL: Qbman portal region - */ -enum dprc_region_type { - DPRC_REGION_TYPE_MC_PORTAL, - DPRC_REGION_TYPE_QBMAN_PORTAL, - DPRC_REGION_TYPE_QBMAN_MEM_BACKED_PORTAL -}; - -/** - * struct dprc_region_desc - Mappable region descriptor - * @base_offset: Region offset from region's base address. - * For DPMCP and DPRC objects, region base is offset from SoC MC portals - * base address; For DPIO, region base is offset from SoC QMan portals - * base address - * @size: Region size (in bytes) - * @flags: Region attributes - * @type: Portal region type - */ -struct dprc_region_desc { - u32 base_offset; - u32 size; - u32 flags; - enum dprc_region_type type; - u64 base_address; -}; - -int dprc_get_obj_region(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - char *obj_type, - int obj_id, - u8 region_index, - struct dprc_region_desc *region_desc); - -int dprc_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver); - -int dprc_get_container_id(struct fsl_mc_io *mc_io, - u32 cmd_flags, - int *container_id); - /* * Data Path Buffer Pool (DPBP) API */ @@ -479,59 +156,12 @@ struct dpcon_cmd_set_notification { __le64 user_ctx; }; -/** - * Maximum number of total IRQs that can be pre-allocated for an MC bus' - * IRQ pool - */ -#define FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS 256 - -/** - * struct fsl_mc_resource_pool - Pool of MC resources of a given - * type - * @type: type of resources in the pool - * @max_count: maximum number of resources in the pool - * @free_count: number of free resources in the pool - * @mutex: mutex to serialize access to the pool's free list - * @free_list: anchor node of list of free resources in the pool - * @mc_bus: pointer to the MC bus that owns this resource pool - */ -struct fsl_mc_resource_pool { - enum fsl_mc_pool_type type; - int max_count; - int free_count; - struct mutex mutex; /* serializes access to free_list */ - struct list_head free_list; - struct fsl_mc_bus *mc_bus; -}; - -/** - * struct fsl_mc_bus - logical bus that corresponds to a physical DPRC - * @mc_dev: fsl-mc device for the bus device itself. - * @resource_pools: array of resource pools (one pool per resource type) - * for this MC bus. These resources represent allocatable entities - * from the physical DPRC. - * @irq_resources: Pointer to array of IRQ objects for the IRQ pool - * @scan_mutex: Serializes bus scanning - * @dprc_attr: DPRC attributes - */ -struct fsl_mc_bus { - struct fsl_mc_device mc_dev; - struct fsl_mc_resource_pool resource_pools[FSL_MC_NUM_POOL_TYPES]; - struct fsl_mc_device_irq *irq_resources; - struct mutex scan_mutex; /* serializes bus scanning */ - struct dprc_attributes dprc_attr; -}; - -#define to_fsl_mc_bus(_mc_dev) \ - container_of(_mc_dev, struct fsl_mc_bus, mc_dev) - int __must_check fsl_mc_device_add(struct fsl_mc_obj_desc *obj_desc, struct fsl_mc_io *mc_io, struct device *parent_dev, + const char *driver_override, struct fsl_mc_device **new_mc_dev); -void fsl_mc_device_remove(struct fsl_mc_device *mc_dev); - int __init dprc_driver_init(void); void dprc_driver_exit(void); @@ -540,10 +170,6 @@ int __init fsl_mc_allocator_driver_init(void); void fsl_mc_allocator_driver_exit(void); -void fsl_mc_init_all_resource_pools(struct fsl_mc_device *mc_bus_dev); - -void fsl_mc_cleanup_all_resource_pools(struct fsl_mc_device *mc_bus_dev); - int __must_check fsl_mc_resource_allocate(struct fsl_mc_bus *mc_bus, enum fsl_mc_pool_type pool_type, struct fsl_mc_resource @@ -556,22 +182,29 @@ int fsl_mc_msi_domain_alloc_irqs(struct device *dev, void fsl_mc_msi_domain_free_irqs(struct device *dev); -int fsl_mc_find_msi_domain(struct device *mc_platform_dev, - struct irq_domain **mc_msi_domain); +bool fsl_mc_is_root_dprc(struct device *dev); -int fsl_mc_populate_irq_pool(struct fsl_mc_bus *mc_bus, - unsigned int irq_count); +#ifdef CONFIG_FSL_MC_UAPI_SUPPORT -void fsl_mc_cleanup_irq_pool(struct fsl_mc_bus *mc_bus); +int fsl_mc_uapi_create_device_file(struct fsl_mc_bus *mc_bus); -int __must_check fsl_create_mc_io(struct device *dev, - phys_addr_t mc_portal_phys_addr, - u32 mc_portal_size, - struct fsl_mc_device *dpmcp_dev, - u32 flags, struct fsl_mc_io **new_mc_io); +void fsl_mc_uapi_remove_device_file(struct fsl_mc_bus *mc_bus); -void fsl_destroy_mc_io(struct fsl_mc_io *mc_io); +#else -bool fsl_mc_is_root_dprc(struct device *dev); +static inline int fsl_mc_uapi_create_device_file(struct fsl_mc_bus *mc_bus) +{ + return 0; +} + +static inline void fsl_mc_uapi_remove_device_file(struct fsl_mc_bus *mc_bus) +{ +} + +#endif + +int disable_dprc_irq(struct fsl_mc_device *mc_dev); +int enable_dprc_irq(struct fsl_mc_device *mc_dev); +int get_dprc_irq_state(struct fsl_mc_device *mc_dev); #endif /* _FSL_MC_PRIVATE_H_ */ diff --git a/drivers/bus/fsl-mc/fsl-mc-uapi.c b/drivers/bus/fsl-mc/fsl-mc-uapi.c new file mode 100644 index 00000000000000..71ff2014f67491 --- /dev/null +++ b/drivers/bus/fsl-mc/fsl-mc-uapi.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Management Complex (MC) userspace support + * + * Copyright 2018 NXP + * + */ + +#include +#include +#include +#include + +#include "fsl-mc-private.h" + +struct uapi_priv_data { + struct fsl_mc_uapi *uapi; + struct fsl_mc_io *mc_io; +}; + +static int fsl_mc_uapi_send_command(unsigned long arg, + struct fsl_mc_io *mc_io) +{ + struct fsl_mc_command mc_cmd; + int error; + + error = copy_from_user(&mc_cmd, (void __user *)arg, sizeof(mc_cmd)); + if (error) + return -EFAULT; + + error = mc_send_command(mc_io, &mc_cmd); + if (error) + return error; + + error = copy_to_user((void __user *)arg, &mc_cmd, sizeof(mc_cmd)); + if (error) + return -EFAULT; + + return 0; +} + +static int fsl_mc_uapi_dev_open(struct inode *inode, struct file *filep) +{ + struct fsl_mc_device *root_mc_device; + struct uapi_priv_data *priv_data; + struct fsl_mc_io *dynamic_mc_io; + struct fsl_mc_uapi *mc_uapi; + struct fsl_mc_bus *mc_bus; + int error; + + priv_data = kzalloc(sizeof(*priv_data), GFP_KERNEL); + if (!priv_data) + return -ENOMEM; + + mc_uapi = container_of(filep->private_data, struct fsl_mc_uapi, misc); + mc_bus = container_of(mc_uapi, struct fsl_mc_bus, uapi_misc); + root_mc_device = &mc_bus->mc_dev; + + mutex_lock(&mc_uapi->mutex); + + if (!mc_uapi->local_instance_in_use) { + priv_data->mc_io = mc_uapi->static_mc_io; + mc_uapi->local_instance_in_use = 1; + } else { + error = fsl_mc_portal_allocate(root_mc_device, 0, + &dynamic_mc_io); + if (error) { + dev_dbg(&root_mc_device->dev, + "Could not allocate MC portal\n"); + goto error_portal_allocate; + } + + priv_data->mc_io = dynamic_mc_io; + } + priv_data->uapi = mc_uapi; + filep->private_data = priv_data; + + mutex_unlock(&mc_uapi->mutex); + + return 0; + +error_portal_allocate: + mutex_unlock(&mc_uapi->mutex); + + return error; +} + +static int fsl_mc_uapi_dev_release(struct inode *inode, struct file *filep) +{ + struct uapi_priv_data *priv_data; + struct fsl_mc_uapi *mc_uapi; + struct fsl_mc_io *mc_io; + + priv_data = filep->private_data; + mc_uapi = priv_data->uapi; + mc_io = priv_data->mc_io; + + mutex_lock(&mc_uapi->mutex); + + if (mc_io == mc_uapi->static_mc_io) + mc_uapi->local_instance_in_use = 0; + else + fsl_mc_portal_free(mc_io); + + kfree(filep->private_data); + filep->private_data = NULL; + + mutex_unlock(&mc_uapi->mutex); + + return 0; +} + +static long fsl_mc_uapi_dev_ioctl(struct file *file, + unsigned int cmd, + unsigned long arg) +{ + struct uapi_priv_data *priv_data = file->private_data; + struct fsl_mc_device *root_mc_device; + struct fsl_mc_bus *mc_bus; + int error; + + mc_bus = container_of(priv_data->uapi, struct fsl_mc_bus, uapi_misc); + root_mc_device = &mc_bus->mc_dev; + + switch (cmd) { + case FSL_MC_SEND_MC_COMMAND: + error = fsl_mc_uapi_send_command(arg, priv_data->mc_io); + break; + default: + dev_dbg(&root_mc_device->dev, "unexpected ioctl call number\n"); + error = -EINVAL; + } + + return error; +} + +static const struct file_operations fsl_mc_uapi_dev_fops = { + .owner = THIS_MODULE, + .open = fsl_mc_uapi_dev_open, + .release = fsl_mc_uapi_dev_release, + .unlocked_ioctl = fsl_mc_uapi_dev_ioctl, +}; + +int fsl_mc_uapi_create_device_file(struct fsl_mc_bus *mc_bus) +{ + struct fsl_mc_device *mc_dev = &mc_bus->mc_dev; + struct fsl_mc_uapi *mc_uapi = &mc_bus->uapi_misc; + int error; + + mc_uapi->misc.minor = MISC_DYNAMIC_MINOR; + mc_uapi->misc.name = dev_name(&mc_dev->dev); + mc_uapi->misc.fops = &fsl_mc_uapi_dev_fops; + + error = misc_register(&mc_uapi->misc); + if (error) + return error; + + mc_uapi->static_mc_io = mc_bus->mc_dev.mc_io; + + mutex_init(&mc_uapi->mutex); + + return 0; +} + +void fsl_mc_uapi_remove_device_file(struct fsl_mc_bus *mc_bus) +{ + misc_deregister(&mc_bus->uapi_misc.misc); +} diff --git a/drivers/bus/fsl-mc/mc-io.c b/drivers/bus/fsl-mc/mc-io.c index d9629fc13a1553..04d08df4ce3284 100644 --- a/drivers/bus/fsl-mc/mc-io.c +++ b/drivers/bus/fsl-mc/mc-io.c @@ -82,7 +82,7 @@ int __must_check fsl_create_mc_io(struct device *dev, mc_io->portal_phys_addr = mc_portal_phys_addr; mc_io->portal_size = mc_portal_size; if (flags & FSL_MC_IO_ATOMIC_CONTEXT_PORTAL) - spin_lock_init(&mc_io->spinlock); + raw_spin_lock_init(&mc_io->spinlock); else mutex_init(&mc_io->mutex); @@ -169,14 +169,16 @@ int __must_check fsl_mc_portal_allocate(struct fsl_mc_device *mc_dev, int error = -EINVAL; struct fsl_mc_resource *resource = NULL; struct fsl_mc_io *mc_io = NULL; + struct device *root_dprc_dev; - if (mc_dev->flags & FSL_MC_IS_DPRC) { + if (fsl_mc_is_root_dprc(&mc_dev->dev)) { mc_bus_dev = mc_dev; } else { - if (!dev_is_fsl_mc(mc_dev->dev.parent)) - return error; + fsl_mc_get_root_dprc(&mc_dev->dev, &root_dprc_dev); + if (WARN_ON(!root_dprc_dev)) + return -EINVAL; - mc_bus_dev = to_fsl_mc_device(mc_dev->dev.parent); + mc_bus_dev = to_fsl_mc_device(root_dprc_dev); } mc_bus = to_fsl_mc_bus(mc_bus_dev); diff --git a/drivers/bus/fsl-mc/mc-sys.c b/drivers/bus/fsl-mc/mc-sys.c index 3221a7fbaf0ad2..14d77dc618cc11 100644 --- a/drivers/bus/fsl-mc/mc-sys.c +++ b/drivers/bus/fsl-mc/mc-sys.c @@ -19,7 +19,7 @@ /** * Timeout in milliseconds to wait for the completion of an MC command */ -#define MC_CMD_COMPLETION_TIMEOUT_MS 500 +#define MC_CMD_COMPLETION_TIMEOUT_MS 15000 /* * usleep_range() min and max values used to throttle down polling @@ -251,7 +251,7 @@ int mc_send_command(struct fsl_mc_io *mc_io, struct fsl_mc_command *cmd) return -EINVAL; if (mc_io->flags & FSL_MC_IO_ATOMIC_CONTEXT_PORTAL) - spin_lock_irqsave(&mc_io->spinlock, irq_flags); + raw_spin_lock_irqsave(&mc_io->spinlock, irq_flags); else mutex_lock(&mc_io->mutex); @@ -287,7 +287,7 @@ int mc_send_command(struct fsl_mc_io *mc_io, struct fsl_mc_command *cmd) error = 0; common_exit: if (mc_io->flags & FSL_MC_IO_ATOMIC_CONTEXT_PORTAL) - spin_unlock_irqrestore(&mc_io->spinlock, irq_flags); + raw_spin_unlock_irqrestore(&mc_io->spinlock, irq_flags); else mutex_unlock(&mc_io->mutex); diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig index df0fc997dc3e30..b2b84096f2a74f 100644 --- a/drivers/char/Kconfig +++ b/drivers/char/Kconfig @@ -535,6 +535,7 @@ config ADI and SSM (Silicon Secured Memory). Intended consumers of this driver include crash and makedumpfile. +source "drivers/char/imx_amp/Kconfig" endmenu config RANDOM_TRUST_CPU diff --git a/drivers/char/Makefile b/drivers/char/Makefile index 7c5ea6f9df1455..acbe489829c954 100644 --- a/drivers/char/Makefile +++ b/drivers/char/Makefile @@ -52,3 +52,4 @@ js-rtc-y = rtc.o obj-$(CONFIG_XILLYBUS) += xillybus/ obj-$(CONFIG_POWERNV_OP_PANEL) += powernv-op-panel.o obj-$(CONFIG_ADI) += adi.o +obj-$(CONFIG_HAVE_IMX_AMP) += imx_amp/ diff --git a/drivers/char/imx_amp/Kconfig b/drivers/char/imx_amp/Kconfig new file mode 100644 index 00000000000000..1f892f8daccbcd --- /dev/null +++ b/drivers/char/imx_amp/Kconfig @@ -0,0 +1,9 @@ +# +# imx mcc +# + +config IMX_SEMA4 + bool "IMX SEMA4 driver" + depends on SOC_IMX6SX + help + Support for IMX SEMA4 driver, most people should say N here. diff --git a/drivers/char/imx_amp/Makefile b/drivers/char/imx_amp/Makefile new file mode 100644 index 00000000000000..4e7a91691b3903 --- /dev/null +++ b/drivers/char/imx_amp/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for imx mcc +# +# +obj-$(CONFIG_IMX_SEMA4) += imx_sema4.o diff --git a/drivers/char/imx_amp/imx_sema4.c b/drivers/char/imx_amp/imx_sema4.c new file mode 100644 index 00000000000000..46a178de41f52b --- /dev/null +++ b/drivers/char/imx_amp/imx_sema4.c @@ -0,0 +1,412 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct imx_sema4_mutex_device *imx6_sema4; +static unsigned long sema4_flags; + + +/*! + * \brief mutex create function. + * + * This function allocates imx_sema4_mutex structure and returns a handle + * to it. The mutex to be created is identified by SEMA4 device number and mutex + * (gate) number. The handle is used to reference the created mutex in calls to + * other imx_sema4_mutex API functions. This function is to be called only + * once for each mutex. + * + * \param[in] dev_num SEMA4 device (module) number. + * \param[in] mutex_num Mutex (gate) number. + * + * \return NULL (Failure.) + * \return imx_sema4_mutex (Success.) + */ +struct imx_sema4_mutex * +imx_sema4_mutex_create(u32 dev_num, u32 mutex_num) +{ + struct imx_sema4_mutex *mutex_ptr = NULL; + + if (mutex_num >= SEMA4_NUM_GATES || dev_num >= SEMA4_NUM_DEVICES) + goto out; + + if (imx6_sema4->cpine_val & (1 < mutex_num)) { + pr_err("Error: requiring a allocated sema4.\n"); + pr_err("mutex_num %d cpine_val 0x%08x.\n", + mutex_num, imx6_sema4->cpine_val); + } + mutex_ptr = kzalloc(sizeof(*mutex_ptr), GFP_KERNEL); + if (!mutex_ptr) + goto out; + imx6_sema4->mutex_ptr[mutex_num] = mutex_ptr; + imx6_sema4->alloced |= 1 < mutex_num; + imx6_sema4->cpine_val |= idx_sema4[mutex_num]; + writew(imx6_sema4->cpine_val, imx6_sema4->ioaddr + SEMA4_CP0INE); + + mutex_ptr->valid = CORE_MUTEX_VALID; + mutex_ptr->gate_num = mutex_num; + init_waitqueue_head(&mutex_ptr->wait_q); + +out: + return mutex_ptr; +} +EXPORT_SYMBOL(imx_sema4_mutex_create); + +/*! + * \brief mutex destroy function. + * + * This function destroys a mutex. + * + * \param[in] mutex_ptr Pointer to mutex structure. + * + * \return MQX_COMPONENT_DOES_NOT_EXIST (mutex component not installed.) + * \return MQX_INVALID_PARAMETER (Wrong input parameter.) + * \return COREMUTEX_OK (Success.) + * + */ +int imx_sema4_mutex_destroy(struct imx_sema4_mutex *mutex_ptr) +{ + u32 mutex_num; + + if ((mutex_ptr == NULL) || (mutex_ptr->valid != CORE_MUTEX_VALID)) + return -EINVAL; + + mutex_num = mutex_ptr->gate_num; + if ((imx6_sema4->cpine_val & idx_sema4[mutex_num]) == 0) { + pr_err("Error: trying to destroy a un-allocated sema4.\n"); + pr_err("mutex_num %d cpine_val 0x%08x.\n", + mutex_num, imx6_sema4->cpine_val); + } + imx6_sema4->mutex_ptr[mutex_num] = NULL; + imx6_sema4->alloced &= ~(1 << mutex_num); + imx6_sema4->cpine_val &= ~(idx_sema4[mutex_num]); + writew(imx6_sema4->cpine_val, imx6_sema4->ioaddr + SEMA4_CP0INE); + + kfree(mutex_ptr); + + return 0; +} +EXPORT_SYMBOL(imx_sema4_mutex_destroy); + +/*! + * \brief Lock the mutex, shouldn't be interruted by INT. + * + * This function attempts to lock a mutex. If the mutex is already locked + * by another task the function return -EBUSY, and tell invoker wait until + * it is possible to lock the mutex. + * + * \param[in] mutex_ptr Pointer to mutex structure. + * + * \return MQX_INVALID_POINTER (Wrong pointer to the mutex structure provided.) + * \return COREMUTEX_OK (mutex successfully locked.) + * + * \see imx_sema4_mutex_unlock + */ +int _imx_sema4_mutex_lock(struct imx_sema4_mutex *mutex_ptr) +{ + int ret = 0, i = 0; + + if ((mutex_ptr == NULL) || (mutex_ptr->valid != CORE_MUTEX_VALID)) + return -EINVAL; + + i = mutex_ptr->gate_num; + mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= SEMA4_GATE_MASK; + /* Check to see if this core already own it */ + if (mutex_ptr->gate_val == SEMA4_A9_LOCK) { + /* return -EBUSY, invoker should be in sleep, and re-lock ag */ + pr_err("%s -> %s %d already locked, wait! num %d val %d.\n", + __FILE__, __func__, __LINE__, + i, mutex_ptr->gate_val); + ret = -EBUSY; + goto out; + } else { + /* try to lock the mutex */ + mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= (~SEMA4_GATE_MASK); + mutex_ptr->gate_val |= SEMA4_A9_LOCK; + writeb(mutex_ptr->gate_val, imx6_sema4->ioaddr + i); + mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= SEMA4_GATE_MASK; + /* double check the mutex is locked, otherwise, return -EBUSY */ + if (mutex_ptr->gate_val != SEMA4_A9_LOCK) { + pr_debug("wait-locked num %d val %d.\n", + i, mutex_ptr->gate_val); + ret = -EBUSY; + } + } +out: + return ret; +} + +/* ! + * \brief Try to lock the core mutex. + * + * This function attempts to lock a mutex. If the mutex is successfully locked + * for the calling task, SEMA4_A9_LOCK is returned. If the mutex is already + * locked by another task, the function does not block but rather returns + * negative immediately. + * + * \param[in] mutex_ptr Pointer to core_mutex structure. + * + * \return SEMA4_A9_LOCK (mutex successfully locked.) + * \return negative (mutex not locked.) + * + */ +int imx_sema4_mutex_trylock(struct imx_sema4_mutex *mutex_ptr) +{ + int ret = 0; + + ret = _imx_sema4_mutex_lock(mutex_ptr); + if (ret == 0) + return SEMA4_A9_LOCK; + else + return ret; +} +EXPORT_SYMBOL(imx_sema4_mutex_trylock); + +/*! + * \brief Invoke _imx_sema4_mutex_lock to lock the mutex. + * + * This function attempts to lock a mutex. If the mutex is already locked + * by another task the function, sleep itself and schedule out. + * Wait until it is possible to lock the mutex. + * + * Invoker should add its own wait queue into the wait queue header of the + * required semaphore, set TASK_INTERRUPTIBLE and sleep on itself by + * schedule() when the lock is failed. Re-try to lock the semaphore when + * it is woke up by the sema4 isr. + * + * \param[in] mutex_ptr Pointer to mutex structure. + * + * \return SEMA4_A9_LOCK (mutex successfully locked.) + * + * \see imx_sema4_mutex_unlock + */ +int imx_sema4_mutex_lock(struct imx_sema4_mutex *mutex_ptr) +{ + int ret = 0; + + spin_lock_irqsave(&imx6_sema4->lock, sema4_flags); + ret = _imx_sema4_mutex_lock(mutex_ptr); + while (-EBUSY == ret) { + ret = _imx_sema4_mutex_lock(mutex_ptr); + if (ret == 0) + break; + } + + return ret; +} +EXPORT_SYMBOL(imx_sema4_mutex_lock); + +/*! + * \brief Unlock the mutex. + * + * This function unlocks the specified mutex. + * + * \param[in] mutex_ptr Pointer to mutex structure. + * + * \return -EINVAL (Wrong pointer to the mutex structure provided.) + * \return -EINVAL (This mutex has not been locked by this core.) + * \return 0 (mutex successfully unlocked.) + * + * \see imx_sema4_mutex_lock + */ +int imx_sema4_mutex_unlock(struct imx_sema4_mutex *mutex_ptr) +{ + int ret = 0, i = 0; + + if ((mutex_ptr == NULL) || (mutex_ptr->valid != CORE_MUTEX_VALID)) + return -EINVAL; + + i = mutex_ptr->gate_num; + mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= SEMA4_GATE_MASK; + /* make sure it is locked by this core */ + if (mutex_ptr->gate_val != SEMA4_A9_LOCK) { + pr_err("%d Trying to unlock an unlock mutex.\n", __LINE__); + ret = -EINVAL; + goto out; + } + /* unlock it */ + mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= (~SEMA4_GATE_MASK); + writeb(mutex_ptr->gate_val | SEMA4_UNLOCK, imx6_sema4->ioaddr + i); + mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= SEMA4_GATE_MASK; + /* make sure it is locked by this core */ + if (mutex_ptr->gate_val == SEMA4_A9_LOCK) + pr_err("%d ERROR, failed to unlock the mutex.\n", __LINE__); + + spin_unlock_irqrestore(&imx6_sema4->lock, sema4_flags); +out: + return ret; +} +EXPORT_SYMBOL(imx_sema4_mutex_unlock); + +/* + * isr used by SEMA4, wake up the sleep tasks if there are the tasks waiting + * for locking semaphore. + * FIXME the bits order of the gatn, cpnie, cpnntf are not exact identified yet! + */ +static irqreturn_t imx_sema4_isr(int irq, void *dev_id) +{ + int i; + struct imx_sema4_mutex *mutex_ptr; + unsigned int mask; + struct imx_sema4_mutex_device *imx6_sema4 = dev_id; + + imx6_sema4->cpntf_val = readw(imx6_sema4->ioaddr + SEMA4_CP0NTF); + for (i = 0; i < SEMA4_NUM_GATES; i++) { + mask = idx_sema4[i]; + if ((imx6_sema4->cpntf_val) & mask) { + mutex_ptr = imx6_sema4->mutex_ptr[i]; + /* + * An interrupt is pending on this mutex, the only way + * to clear it is to lock it (either by this core or + * another). + */ + mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= (~SEMA4_GATE_MASK); + mutex_ptr->gate_val |= SEMA4_A9_LOCK; + writeb(mutex_ptr->gate_val, imx6_sema4->ioaddr + i); + mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= SEMA4_GATE_MASK; + if (mutex_ptr->gate_val == SEMA4_A9_LOCK) { + /* + * wake up the wait queue, whatever there + * are wait task or not. + * NOTE: check gate is locted or not in + * sema4_lock func by wait task. + */ + mutex_ptr->gate_val = + readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= (~SEMA4_GATE_MASK); + mutex_ptr->gate_val |= SEMA4_UNLOCK; + + writeb(mutex_ptr->gate_val, + imx6_sema4->ioaddr + i); + wake_up(&mutex_ptr->wait_q); + } else { + pr_debug("can't lock gate%d %s retry!\n", i, + mutex_ptr->gate_val ? + "locked by m4" : ""); + } + } + } + + return IRQ_HANDLED; +} + +static const struct of_device_id imx_sema4_dt_ids[] = { + { .compatible = "fsl,imx6sx-sema4", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx_sema4_dt_ids); + +static int imx_sema4_probe(struct platform_device *pdev) +{ + struct resource *res; + int ret; + + imx6_sema4 = devm_kzalloc(&pdev->dev, sizeof(*imx6_sema4), GFP_KERNEL); + if (!imx6_sema4) + return -ENOMEM; + + imx6_sema4->dev = &pdev->dev; + imx6_sema4->cpine_val = 0; + spin_lock_init(&imx6_sema4->lock); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (IS_ERR(res)) { + dev_err(&pdev->dev, "unable to get imx sema4 resource 0\n"); + ret = -ENODEV; + goto err; + } + + imx6_sema4->ioaddr = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(imx6_sema4->ioaddr)) { + ret = PTR_ERR(imx6_sema4->ioaddr); + goto err; + } + + imx6_sema4->irq = platform_get_irq(pdev, 0); + if (!imx6_sema4->irq) { + dev_err(&pdev->dev, "failed to get irq\n"); + ret = -ENODEV; + goto err; + } + + ret = devm_request_irq(&pdev->dev, imx6_sema4->irq, imx_sema4_isr, + IRQF_SHARED, "imx6sx-sema4", imx6_sema4); + if (ret) { + dev_err(&pdev->dev, "failed to request imx sema4 irq\n"); + ret = -ENODEV; + goto err; + } + + platform_set_drvdata(pdev, imx6_sema4); + +err: + return ret; +} + +static int imx_sema4_remove(struct platform_device *pdev) +{ + return 0; +} + +static struct platform_driver imx_sema4_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "imx-sema4", + .of_match_table = imx_sema4_dt_ids, + }, + .probe = imx_sema4_probe, + .remove = imx_sema4_remove, +}; + +static int __init imx_sema4_init(void) +{ + int ret; + + ret = platform_driver_register(&imx_sema4_driver); + if (ret) + pr_err("Unable to initialize sema4 driver\n"); + else + pr_info("imx sema4 driver is registered.\n"); + + return ret; +} + +static void __exit imx_sema4_exit(void) +{ + pr_info("imx sema4 driver is unregistered.\n"); + platform_driver_unregister(&imx_sema4_driver); +} + +module_exit(imx_sema4_exit); +module_init(imx_sema4_init); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("IMX SEMA4 driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c44247d0b83e8a..2e67d597ab12d2 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -218,6 +218,16 @@ config CLK_QORIQ This adds the clock driver support for Freescale QorIQ platforms using common clock framework. +config CLK_LS1028A_PLLDIG + tristate "Clock driver for LS1028A Display output" + depends on ARCH_LAYERSCAPE || COMPILE_TEST + default ARCH_LAYERSCAPE + help + This driver support the Display output interfaces(LCD, DPHY) pixel clocks + of the QorIQ Layerscape LS1028A, as implemented TSMC CLN28HPM PLL. Not all + features of the PLL are currently supported by the driver. By default, + configured bypass mode with this PLL. + config COMMON_CLK_XGENE bool "Clock driver for APM XGene SoC" default ARCH_XGENE @@ -318,6 +328,7 @@ source "drivers/clk/meson/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/qcom/Kconfig" source "drivers/clk/renesas/Kconfig" +source "drivers/clk/s32/Kconfig" source "drivers/clk/samsung/Kconfig" source "drivers/clk/sifive/Kconfig" source "drivers/clk/sprd/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 0138fb14e6f883..15488d4d358bdc 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_ARCH_NPCM7XX) += clk-npcm7xx.o obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o obj-$(CONFIG_COMMON_CLK_OXNAS) += clk-oxnas.o obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o +obj-$(CONFIG_CLK_LS1028A_PLLDIG) += clk-plldig.o obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o @@ -97,6 +98,7 @@ obj-$(CONFIG_COMMON_CLK_PXA) += pxa/ obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/ obj-y += renesas/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ +obj-$(CONFIG_ARCH_S32) += s32/ obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ obj-$(CONFIG_CLK_SIFIVE) += sifive/ obj-$(CONFIG_ARCH_SIRF) += sirf/ diff --git a/drivers/clk/clk-plldig.c b/drivers/clk/clk-plldig.c new file mode 100644 index 00000000000000..365edd30da8c4d --- /dev/null +++ b/drivers/clk/clk-plldig.c @@ -0,0 +1,301 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP + * + * Clock driver for LS1028A Display output interfaces(LCD, DPHY). + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* PLLDIG register offsets and bit masks */ +#define PLLDIG_REG_PLLSR 0x24 +#define PLLDIG_LOCK_MASK BIT(2) +#define PLLDIG_REG_PLLDV 0x28 +#define PLLDIG_MFD_MASK GENMASK(7, 0) +#define PLLDIG_RFDPHI1_MASK GENMASK(30, 25) +#define PLLDIG_REG_PLLFM 0x2c +#define PLLDIG_SSCGBYP_ENABLE BIT(30) +#define PLLDIG_REG_PLLFD 0x30 +#define PLLDIG_FDEN BIT(30) +#define PLLDIG_FRAC_MASK GENMASK(15, 0) +#define PLLDIG_DTH_MASK GENMASK(17, 16) +#define PLLDIG_DTH_DISABLE 3 +#define PLLDIG_REG_PLLCAL1 0x38 +#define PLLDIG_REG_PLLCAL2 0x3c + +/* Range of the VCO frequencies, in Hz */ +#define PLLDIG_MIN_VCO_FREQ 650000000 +#define PLLDIG_MAX_VCO_FREQ 1300000000 + +/* Range of the output frequencies, in Hz */ +#define PHI1_MIN_FREQ 27000000 +#define PHI1_MAX_FREQ 600000000 + +/* Maximum value of the reduced frequency divider */ +#define MAX_RFDPHI1 63UL + +/* Best value of multiplication factor divider */ +#define PLLDIG_DEFAULT_MFD 44 + +/* + * Denominator part of the fractional part of the + * loop multiplication factor. + */ +#define MFDEN 20480 + +static const struct clk_parent_data parent_data[] = { + {.index = 0}, +}; + +struct clk_plldig { + struct clk_hw hw; + void __iomem *regs; + unsigned int vco_freq; +}; + +#define to_clk_plldig(_hw) container_of(_hw, struct clk_plldig, hw) + +static int plldig_enable(struct clk_hw *hw) +{ + struct clk_plldig *data = to_clk_plldig(hw); + u32 val; + + val = readl(data->regs + PLLDIG_REG_PLLFM); + /* + * Use Bypass mode with PLL off by default, the frequency overshoot + * detector output was disable. SSCG Bypass mode should be enable. + */ + val |= PLLDIG_SSCGBYP_ENABLE; + writel(val, data->regs + PLLDIG_REG_PLLFM); + + return 0; +} + +static void plldig_disable(struct clk_hw *hw) +{ + struct clk_plldig *data = to_clk_plldig(hw); + u32 val; + + val = readl(data->regs + PLLDIG_REG_PLLFM); + + val &= ~PLLDIG_SSCGBYP_ENABLE; + val |= FIELD_PREP(PLLDIG_SSCGBYP_ENABLE, 0x0); + + writel(val, data->regs + PLLDIG_REG_PLLFM); +} + +static int plldig_is_enabled(struct clk_hw *hw) +{ + struct clk_plldig *data = to_clk_plldig(hw); + + return (readl(data->regs + PLLDIG_REG_PLLFM) & + PLLDIG_SSCGBYP_ENABLE); +} + +static unsigned long plldig_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_plldig *data = to_clk_plldig(hw); + u32 val, rfdphi1; + + val = readl(data->regs + PLLDIG_REG_PLLDV); + + /* Check if PLL is bypassed */ + if (val & PLLDIG_SSCGBYP_ENABLE) + return parent_rate; + + rfdphi1 = FIELD_GET(PLLDIG_RFDPHI1_MASK, val); + + /* + * If RFDPHI1 has a value of 1 the VCO frequency is also divided by + * one. + */ + if (!rfdphi1) + rfdphi1 = 1; + + return DIV_ROUND_UP(data->vco_freq, rfdphi1); +} + +static unsigned long plldig_calc_target_div(unsigned long vco_freq, + unsigned long target_rate) +{ + unsigned long div; + + div = DIV_ROUND_CLOSEST(vco_freq, target_rate); + div = max(1UL, div); + div = min(div, MAX_RFDPHI1); + + return div; +} + +static int plldig_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_plldig *data = to_clk_plldig(hw); + unsigned int div; + + if (req->rate < PHI1_MIN_FREQ) + req->rate = PHI1_MIN_FREQ; + if (req->rate > PHI1_MAX_FREQ) + req->rate = PHI1_MAX_FREQ; + + div = plldig_calc_target_div(data->vco_freq, req->rate); + req->rate = DIV_ROUND_UP(data->vco_freq, div); + + return 0; +} + +static int plldig_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_plldig *data = to_clk_plldig(hw); + unsigned int val, cond; + unsigned int rfdphi1; + + if (rate < PHI1_MIN_FREQ) + rate = PHI1_MIN_FREQ; + if (rate > PHI1_MAX_FREQ) + rate = PHI1_MAX_FREQ; + + rfdphi1 = plldig_calc_target_div(data->vco_freq, rate); + + /* update the divider value */ + val = readl(data->regs + PLLDIG_REG_PLLDV); + val &= ~PLLDIG_RFDPHI1_MASK; + val |= FIELD_PREP(PLLDIG_RFDPHI1_MASK, rfdphi1); + writel(val, data->regs + PLLDIG_REG_PLLDV); + + /* delay 200us make sure that old lock state is cleared */ + udelay(200); + + /* Wait until PLL is locked or timeout (maximum 1000 usecs) */ + return readl_poll_timeout_atomic(data->regs + PLLDIG_REG_PLLSR, cond, + cond & PLLDIG_LOCK_MASK, 0, + USEC_PER_MSEC); +} + +static const struct clk_ops plldig_clk_ops = { + .enable = plldig_enable, + .disable = plldig_disable, + .is_enabled = plldig_is_enabled, + .recalc_rate = plldig_recalc_rate, + .determine_rate = plldig_determine_rate, + .set_rate = plldig_set_rate, +}; + +static int plldig_init(struct clk_hw *hw) +{ + struct clk_plldig *data = to_clk_plldig(hw); + struct clk_hw *parent = clk_hw_get_parent(hw); + unsigned long parent_rate = clk_hw_get_rate(parent); + unsigned long val; + unsigned long long lltmp; + unsigned int mfd, fracdiv = 0; + + if (!parent) + return -EINVAL; + + if (data->vco_freq) { + mfd = data->vco_freq / parent_rate; + lltmp = data->vco_freq % parent_rate; + lltmp *= MFDEN; + do_div(lltmp, parent_rate); + fracdiv = lltmp; + } else { + mfd = PLLDIG_DEFAULT_MFD; + data->vco_freq = parent_rate * mfd; + } + + val = FIELD_PREP(PLLDIG_MFD_MASK, mfd); + writel(val, data->regs + PLLDIG_REG_PLLDV); + + if (fracdiv) { + val = FIELD_PREP(PLLDIG_FRAC_MASK, fracdiv); + /* Enable fractional divider */ + val |= PLLDIG_FDEN; + /* Disable dither */ + val |= FIELD_PREP(PLLDIG_DTH_MASK, PLLDIG_DTH_DISABLE); + writel(val, data->regs + PLLDIG_REG_PLLFD); + } + + return 0; +} + +static int plldig_clk_probe(struct platform_device *pdev) +{ + struct clk_plldig *data; + struct resource *mem; + struct device *dev = &pdev->dev; + int ret; + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + data->regs = devm_ioremap_resource(dev, mem); + if (IS_ERR(data->regs)) + return PTR_ERR(data->regs); + + data->hw.init = CLK_HW_INIT_PARENTS_DATA("dpclk", + parent_data, + &plldig_clk_ops, + 0); + + ret = devm_clk_hw_register(dev, &data->hw); + if (ret) { + dev_err(dev, "failed to register %s clock\n", + dev->of_node->name); + return ret; + } + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, + &data->hw); + if (ret) { + dev_err(dev, "unable to add clk provider\n"); + return ret; + } + + /* + * The frequency of the VCO cannot be changed during runtime. + * Therefore, let the user specify a desired frequency. + */ + if (!of_property_read_u32(dev->of_node, "vco-frequency", + &data->vco_freq)) { + if (data->vco_freq < PLLDIG_MIN_VCO_FREQ || + data->vco_freq > PLLDIG_MAX_VCO_FREQ) + return -EINVAL; + } + + return plldig_init(&data->hw); +} + +static const struct of_device_id plldig_clk_id[] = { + { .compatible = "fsl,ls1028a-plldig"}, + { } +}; +MODULE_DEVICE_TABLE(of, plldig_clk_id); + +static struct platform_driver plldig_clk_driver = { + .driver = { + .name = "plldig-clock", + .of_match_table = plldig_clk_id, + }, + .probe = plldig_clk_probe, +}; +module_platform_driver(plldig_clk_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Wen He "); +MODULE_DESCRIPTION("LS1028A Display output interface pixel clock driver"); diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 36e9f38a38824d..b6355e2c0b2c9f 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -2469,7 +2469,8 @@ static int clk_core_set_parent_nolock(struct clk_core *core, if (!core) return 0; - if (core->parent == parent) + if ((core->parent == parent) && + !(core->flags & CLK_SET_PARENT_NOCACHE)) return 0; /* verify ops for multi-parent clks */ diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig index 1ac0c7990392d7..01eadee88d6615 100644 --- a/drivers/clk/imx/Kconfig +++ b/drivers/clk/imx/Kconfig @@ -20,6 +20,12 @@ config CLK_IMX8MN help Build the driver for i.MX8MN CCM Clock Driver +config CLK_IMX8MP + bool "IMX8MP CCM Clock Driver" + depends on ARCH_MXC && ARM64 + help + Build the driver for i.MX8MP CCM Clock Driver + config CLK_IMX8MQ bool "IMX8MQ CCM Clock Driver" depends on ARCH_MXC && ARM64 diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 77a3d714f1d599..764236881a9bca 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -27,9 +27,11 @@ obj-$(CONFIG_MXC_CLK_SCU) += \ obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o +obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-audiomix.o clk-hdmimix.o clk-gate-shared.o obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o -obj-$(CONFIG_CLK_IMX8QXP) += clk-imx8qxp.o clk-imx8qxp-lpcg.o - +obj-$(CONFIG_CLK_IMX8QXP) += clk-imx8qxp.o clk-imx8qxp-lpcg.o clk-imx8qxp-acm.o \ + clk-imx8qxp-rsrc.o clk-imx8qm-rsrc.o clk-imx8qm-acm.o \ + clk-imx8dxl-rsrc.o clk-imx8dxl-acm.o clk-imx-acm-utils.o obj-$(CONFIG_SOC_IMX1) += clk-imx1.o obj-$(CONFIG_SOC_IMX21) += clk-imx21.o obj-$(CONFIG_SOC_IMX25) += clk-imx25.o diff --git a/drivers/clk/imx/clk-audiomix.c b/drivers/clk/imx/clk-audiomix.c new file mode 100644 index 00000000000000..a79622ab4dbf5c --- /dev/null +++ b/drivers/clk/imx/clk-audiomix.c @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +static int shared_count_pdm; +static struct clk *clks[IMX8MP_CLK_AUDIOMIX_END]; +static struct clk_onecell_data clk_data; +static uint32_t audiomix_clk_saved_regs[14]; +static struct clk *clk_audio_root; + +/* descending order */ +static const struct imx_pll14xx_rate_table imx_audiomix_sai_pll_tbl[] = { + PLL_1443X_RATE(245760000U, 328, 4, 3, 0xae15), + PLL_1443X_RATE(225792000U, 226, 3, 3, 0xcac1), + PLL_1443X_RATE(122880000U, 328, 4, 4, 0xae15), + PLL_1443X_RATE(112896000U, 226, 3, 4, 0xcac1), + PLL_1443X_RATE(61440000U, 328, 4, 5, 0xae15), + PLL_1443X_RATE(56448000U, 226, 3, 5, 0xcac1), + PLL_1443X_RATE(49152000U, 393, 3, 6, 0x374c), + PLL_1443X_RATE(45158400U, 241, 2, 6, 0xd845), + PLL_1443X_RATE(40960000U, 109, 1, 6, 0x3a07), +}; + +static const struct imx_pll14xx_clk imx_audiomix_sai_pll = { + .type = PLL_1443X, + .rate_table = imx_audiomix_sai_pll_tbl, + .rate_count = ARRAY_SIZE(imx_audiomix_sai_pll_tbl), +}; + +static const char *imx_sai_mclk2_sels[] = {"sai1", "sai2", "sai3", "dummy", + "sai5", "sai6", "sai7", "dummy", + "dummy", "dummy", "dummy", + "dummy", "dummy", "dummy", "dummy"}; +static const char *imx_sai1_mclk1_sels[] = {"sai1", "dummy", }; +static const char *imx_sai2_mclk1_sels[] = {"sai2", "dummy", }; +static const char *imx_sai3_mclk1_sels[] = {"sai3", "dummy", }; +static const char *imx_sai5_mclk1_sels[] = {"sai5", "dummy", }; +static const char *imx_sai6_mclk1_sels[] = {"sai6", "dummy", }; +static const char *imx_sai7_mclk1_sels[] = {"sai7", "dummy", }; +static const char *imx_pdm_sels[] = {"pdm", "sai_pll_div2", "dummy", "dummy" }; +static const char *imx_sai_pll_ref_sels[] = {"osc_24m", "dummy", "dummy", "dummy", }; +static const char *imx_sai_pll_bypass_sels[] = {"sai_pll", "sai_pll_ref_sel", }; + +static int imx_audiomix_clk_runtime_suspend(struct device *dev) +{ + void __iomem *base; + + base = dev_get_drvdata(dev->parent); + + audiomix_clk_saved_regs[0] = readl(base); + audiomix_clk_saved_regs[1] = readl(base + 0x4); + + audiomix_clk_saved_regs[2] = readl(base + 0x300); + audiomix_clk_saved_regs[3] = readl(base + 0x304); + audiomix_clk_saved_regs[4] = readl(base + 0x308); + audiomix_clk_saved_regs[5] = readl(base + 0x30C); + audiomix_clk_saved_regs[6] = readl(base + 0x310); + audiomix_clk_saved_regs[7] = readl(base + 0x314); + audiomix_clk_saved_regs[8] = readl(base + 0x318); + + audiomix_clk_saved_regs[9] = readl(base + 0x400); + audiomix_clk_saved_regs[10] = readl(base + 0x404); + audiomix_clk_saved_regs[11] = readl(base + 0x408); + audiomix_clk_saved_regs[12] = readl(base + 0x40C); + audiomix_clk_saved_regs[13] = readl(base + 0x410); + + clk_disable_unprepare(clk_audio_root); + + return 0; +} + +static int imx_audiomix_clk_runtime_resume(struct device *dev) +{ + void __iomem *base; + + base = dev_get_drvdata(dev->parent); + + clk_prepare_enable(clk_audio_root); + + /* + * Ignore bit26, which are clock gate for sdma clock root. + * We need to keep it on as reset state for hardware issue + * that sdma3' event logic depends on sdma2's clock gate. + * keep it enabled can workaround the issue. + */ + writel(audiomix_clk_saved_regs[0] | 0x4000000, base); + writel(audiomix_clk_saved_regs[1], base + 0x4); + + writel(audiomix_clk_saved_regs[2], base + 0x300); + writel(audiomix_clk_saved_regs[3], base + 0x304); + writel(audiomix_clk_saved_regs[4], base + 0x308); + writel(audiomix_clk_saved_regs[5], base + 0x30C); + writel(audiomix_clk_saved_regs[6], base + 0x310); + writel(audiomix_clk_saved_regs[7], base + 0x314); + writel(audiomix_clk_saved_regs[8], base + 0x318); + + writel(audiomix_clk_saved_regs[9], base + 0x400); + writel(audiomix_clk_saved_regs[10], base + 0x404); + writel(audiomix_clk_saved_regs[11], base + 0x408); + writel(audiomix_clk_saved_regs[12], base + 0x40C); + writel(audiomix_clk_saved_regs[13], base + 0x410); + + return 0; +} + +static int imx_audiomix_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + void __iomem *base; + int ret; + + clk_audio_root = of_clk_get_by_name(np, "audio_root"); + if (IS_ERR(clk_audio_root)) + return PTR_ERR(clk_audio_root); + + base = dev_get_drvdata(dev->parent); + if (IS_ERR(base)) + return PTR_ERR(base); + + pm_runtime_enable(dev); + pm_runtime_get_sync(dev); + + clks[IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL] = imx_dev_clk_mux(dev, "sai_pll_ref_sel", base + 0x400, 0, 2, imx_sai_pll_ref_sels, ARRAY_SIZE(imx_sai_pll_ref_sels)); + clks[IMX8MP_CLK_AUDIOMIX_SAI_PLL] = imx_dev_clk_pll14xx(dev, "sai_pll", "sai_pll_ref_sel", base + 0x400, &imx_audiomix_sai_pll); + + clks[IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS] = imx_dev_clk_mux_flags(dev, "sai_pll_bypass", base + 0x400, 4, 1, imx_sai_pll_bypass_sels, ARRAY_SIZE(imx_sai_pll_bypass_sels), CLK_SET_RATE_PARENT); + + clks[IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT] = imx_dev_clk_gate(dev, "sai_pll_out", "sai_pll_bypass", base + 0x400, 13); + + clks[IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL] = imx_dev_clk_mux_flags(dev, "sai1_mclk1_sel", base + 0x300, 0, 1, imx_sai1_mclk1_sels, ARRAY_SIZE(imx_sai1_mclk1_sels), CLK_SET_RATE_PARENT); + clks[IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL] = imx_dev_clk_mux(dev, "sai1_mclk2_sel", base + 0x300, 1, 4, imx_sai_mclk2_sels, ARRAY_SIZE(imx_sai_mclk2_sels)); + clks[IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL] = imx_dev_clk_mux_flags(dev, "sai2_mclk1_sel", base + 0x304, 0, 1, imx_sai2_mclk1_sels, ARRAY_SIZE(imx_sai2_mclk1_sels), CLK_SET_RATE_PARENT); + clks[IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2_SEL] = imx_dev_clk_mux(dev, "sai2_mclk2_sel", base + 0x304, 1, 4, imx_sai_mclk2_sels, ARRAY_SIZE(imx_sai_mclk2_sels)); + clks[IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1_SEL] = imx_dev_clk_mux_flags(dev, "sai3_mclk1_sel", base + 0x308, 0, 1, imx_sai3_mclk1_sels, ARRAY_SIZE(imx_sai3_mclk1_sels), CLK_SET_RATE_PARENT); + clks[IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2_SEL] = imx_dev_clk_mux(dev, "sai3_mclk2_sel", base + 0x308, 1, 4, imx_sai_mclk2_sels, ARRAY_SIZE(imx_sai_mclk2_sels)); + clks[IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1_SEL] = imx_dev_clk_mux(dev, "sai5_mclk1_sel", base + 0x30C, 0, 1, imx_sai5_mclk1_sels, ARRAY_SIZE(imx_sai5_mclk1_sels)); + clks[IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2_SEL] = imx_dev_clk_mux(dev, "sai5_mclk2_sel", base + 0x30C, 1, 4, imx_sai_mclk2_sels, ARRAY_SIZE(imx_sai_mclk2_sels)); + clks[IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1_SEL] = imx_dev_clk_mux(dev, "sai6_mclk1_sel", base + 0x310, 0, 1, imx_sai6_mclk1_sels, ARRAY_SIZE(imx_sai6_mclk1_sels)); + clks[IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2_SEL] = imx_dev_clk_mux(dev, "sai6_mclk2_sel", base + 0x310, 1, 4, imx_sai_mclk2_sels, ARRAY_SIZE(imx_sai_mclk2_sels)); + clks[IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1_SEL] = imx_dev_clk_mux(dev, "sai7_mclk1_sel", base + 0x314, 0, 1, imx_sai7_mclk1_sels, ARRAY_SIZE(imx_sai7_mclk1_sels)); + clks[IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2_SEL] = imx_dev_clk_mux(dev, "sai7_mclk2_sel", base + 0x314, 1, 4, imx_sai_mclk2_sels, ARRAY_SIZE(imx_sai_mclk2_sels)); + + clks[IMX8MP_CLK_AUDIOMIX_SAI1_IPG] = imx_dev_clk_gate(dev, "sai1_ipg_clk", "ipg_audio_root", base, 0); + clks[IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1] = imx_dev_clk_gate(dev, "sai1_mclk1_clk", "sai1_mclk1_sel", base, 1); + clks[IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2] = imx_dev_clk_gate(dev, "sai1_mclk2_clk", "sai1_mclk2_sel", base, 2); + clks[IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3] = imx_dev_clk_gate(dev, "sai1_mclk3_clk", "sai_pll_out", base, 3); + clks[IMX8MP_CLK_AUDIOMIX_SAI2_IPG] = imx_dev_clk_gate(dev, "sai2_ipg_clk", "ipg_audio_root", base, 4); + clks[IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1] = imx_dev_clk_gate(dev, "sai2_mclk1_clk", "sai2_mclk1_sel", base, 5); + clks[IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2] = imx_dev_clk_gate(dev, "sai2_mclk2_clk", "sai2_mclk2_sel", base, 6); + clks[IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3] = imx_dev_clk_gate(dev, "sai2_mclk3_clk", "sai_pll_out", base, 7); + clks[IMX8MP_CLK_AUDIOMIX_SAI3_IPG] = imx_dev_clk_gate(dev, "sai3_ipg_clk", "ipg_audio_root", base, 8); + clks[IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1] = imx_dev_clk_gate(dev, "sai3_mclk1_clk", "sai3_mclk1_sel", base, 9); + clks[IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2] = imx_dev_clk_gate(dev, "sai3_mclk2_clk", "sai3_mclk2_sel", base, 10); + clks[IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3] = imx_dev_clk_gate(dev, "sai3_mclk3_clk", "sai_pll_out", base, 11); + clks[IMX8MP_CLK_AUDIOMIX_SAI5_IPG] = imx_dev_clk_gate(dev, "sai5_ipg_clk", "ipg_audio_root", base, 12); + clks[IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1] = imx_dev_clk_gate(dev, "sai5_mclk1_clk", "sai5_mclk1_sel", base, 13); + clks[IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2] = imx_dev_clk_gate(dev, "sai5_mclk2_clk", "sai5_mclk2_sel", base, 14); + clks[IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3] = imx_dev_clk_gate(dev, "sai5_mclk3_clk", "sai_pll_out", base, 15); + clks[IMX8MP_CLK_AUDIOMIX_SAI6_IPG] = imx_dev_clk_gate(dev, "sai6_ipg_clk", "ipg_audio_root", base, 16); + clks[IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1] = imx_dev_clk_gate(dev, "sai6_mclk1_clk", "sai6_mclk1_sel", base, 17); + clks[IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2] = imx_dev_clk_gate(dev, "sai6_mclk2_clk", "sai6_mclk2_sel", base, 18); + clks[IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3] = imx_dev_clk_gate(dev, "sai6_mclk3_clk", "sai_pll_out", base, 19); + clks[IMX8MP_CLK_AUDIOMIX_SAI7_IPG] = imx_dev_clk_gate(dev, "sai7_ipg_clk", "ipg_audio_root", base, 20); + clks[IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1] = imx_dev_clk_gate(dev, "sai7_mclk1_clk", "sai7_mclk1_sel", base, 21); + clks[IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2] = imx_dev_clk_gate(dev, "sai7_mclk2_clk", "sai7_mclk2_sel", base, 22); + clks[IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3] = imx_dev_clk_gate(dev, "sai7_mclk3_clk", "sai_pll_out", base, 23); + clks[IMX8MP_CLK_AUDIOMIX_ASRC_IPG] = imx_dev_clk_gate(dev, "asrc_ipg_clk", "ipg_audio_root", base, 24); + clks[IMX8MP_CLK_AUDIOMIX_PDM_IPG] = imx_dev_clk_gate_shared(dev, "pdm_ipg_clk", "ipg_audio_root", base, 25, &shared_count_pdm); + clks[IMX8MP_CLK_AUDIOMIX_PDM_ROOT] = imx_dev_clk_gate_shared(dev, "pdm_root_clk", "pdm", base, 25, &shared_count_pdm); + + clks[IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT] = imx_dev_clk_gate(dev, "sdma3_root_clk", "ipg_audio_root", base, 27); + clks[IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT] = imx_dev_clk_gate(dev, "spba2_root_clk", "ipg_audio_root", base, 28); + clks[IMX8MP_CLK_AUDIOMIX_DSP_ROOT] = imx_dev_clk_gate(dev, "dsp_root_clk", "ipg_audio_root", base, 29); + clks[IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT] = imx_dev_clk_gate(dev, "dsp_dbg_clk", "ipg_audio_root", base, 30); + clks[IMX8MP_CLK_AUDIOMIX_EARC_IPG] = imx_dev_clk_gate(dev, "earc_ipg_clk", "ipg_audio_root", base, 31); + + clks[IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG] = imx_dev_clk_gate(dev, "ocram_a_ipg_clk", "ipg_audio_root", base + 4, 0); + clks[IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG] = imx_dev_clk_gate(dev, "aud2htx_ipg_clk", "ipg_audio_root", base + 4, 1); + clks[IMX8MP_CLK_AUDIOMIX_EDMA_ROOT] = imx_dev_clk_gate(dev, "edma_root_clk", "ipg_audio_root", base + 4, 2); + clks[IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT] = imx_dev_clk_gate(dev, "aud_pll_clk", "ipg_audio_root", base + 4, 3); + clks[IMX8MP_CLK_AUDIOMIX_MU2_ROOT] = imx_dev_clk_gate(dev, "mu2_root_clk", "ipg_audio_root", base + 4, 4); + clks[IMX8MP_CLK_AUDIOMIX_MU3_ROOT] = imx_dev_clk_gate(dev, "mu3_root_clk", "ipg_audio_root", base + 4, 5); + clks[IMX8MP_CLK_AUDIOMIX_EARC_PHY] = imx_dev_clk_gate(dev, "earc_phy_clk", "sai_pll_out", base + 4, 6); + + clks[IMX8MP_CLK_AUDIOMIX_PDM_SEL] = imx_dev_clk_mux(dev, "pdm_sel", base + 0x318, 1, 4, imx_pdm_sels, ARRAY_SIZE(imx_pdm_sels)); + + /* unbypass the pll */ + clk_set_parent(clks[IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS], clks[IMX8MP_CLK_AUDIOMIX_SAI_PLL]); + + imx_check_clocks(clks, ARRAY_SIZE(clks)); + + clk_data.clks = clks; + clk_data.clk_num = ARRAY_SIZE(clks); + ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + if (ret < 0) { + pr_err("failed to register clks for i.MX8MP\n"); + return -EINVAL; + } + + pm_runtime_put_sync(dev); + + return 0; +} + +static const struct dev_pm_ops imx_audiomix_clk_pm_ops = { + SET_RUNTIME_PM_OPS(imx_audiomix_clk_runtime_suspend, + imx_audiomix_clk_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + +static const struct of_device_id imx_audiomix_clk_of_match[] = { + { .compatible = "fsl,imx8mp-audiomix-clk" }, + { /* Sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, imx_audiomix_clk_of_match); + + +static struct platform_driver imx_audiomix_clk_driver = { + .probe = imx_audiomix_clk_probe, + .driver = { + .name = "imx-audiomix-clk", + .of_match_table = of_match_ptr(imx_audiomix_clk_of_match), + .pm = &imx_audiomix_clk_pm_ops, + }, +}; +module_platform_driver(imx_audiomix_clk_driver); diff --git a/drivers/clk/imx/clk-composite-7ulp.c b/drivers/clk/imx/clk-composite-7ulp.c index 060f8600ea0dd3..82eabd33e067b5 100644 --- a/drivers/clk/imx/clk-composite-7ulp.c +++ b/drivers/clk/imx/clk-composite-7ulp.c @@ -7,6 +7,7 @@ #include #include +#include #include #include "clk.h" @@ -32,6 +33,7 @@ struct clk_hw *imx7ulp_clk_composite(const char *name, struct clk_gate *gate = NULL; struct clk_mux *mux = NULL; struct clk_hw *hw; + u32 val; if (mux_present) { mux = kzalloc(sizeof(*mux), GFP_KERNEL); @@ -70,6 +72,18 @@ struct clk_hw *imx7ulp_clk_composite(const char *name, gate_hw = &gate->hw; gate->reg = reg; gate->bit_idx = PCG_CGC_SHIFT; + /* + * make sure clock is gated during clock tree initialization, + * the HW ONLY allow clock parent/rate changed with clock gated, + * during clock tree initialization, clocks could be enabled + * by bootloader, so the HW status will mismatch with clock tree + * prepare count, then clock core driver will allow parent/rate + * change since the prepare count is zero, but HW actually + * prevent the parent/rate change due to the clock is enabled. + */ + val = readl_relaxed(reg); + val &= ~(1 << PCG_CGC_SHIFT); + writel_relaxed(val, reg); } hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index d3486ee79ab54e..a47c2c05d03409 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -155,14 +155,19 @@ struct clk *imx8m_clk_composite_flags(const char *name, div->lock = &imx_ccm_lock; div->flags = CLK_DIVIDER_ROUND_CLOSEST; - gate = kzalloc(sizeof(*gate), GFP_KERNEL); - if (!gate) - goto fail; - - gate_hw = &gate->hw; - gate->reg = reg; - gate->bit_idx = PCG_CGC_SHIFT; - gate->lock = &imx_ccm_lock; + /* skip registering the gate ops if M4 is enabled */ + if (imx_src_is_m4_enabled()) { + gate_hw = NULL; + } else { + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + goto fail; + + gate_hw = &gate->hw; + gate->reg = reg; + gate->bit_idx = PCG_CGC_SHIFT; + gate->lock = &imx_ccm_lock; + } hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, mux_hw, &clk_mux_ops, div_hw, diff --git a/drivers/clk/imx/clk-gate-shared.c b/drivers/clk/imx/clk-gate-shared.c new file mode 100644 index 00000000000000..cefc681c281304 --- /dev/null +++ b/drivers/clk/imx/clk-gate-shared.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP. + */ + +#include +#include +#include +#include +#include "clk.h" + +/** + * struct clk_gate_shared - i.MX specific gate clock having the gate flag + * shared with other gate clocks + */ +struct clk_gate_shared { + struct clk_gate gate; + spinlock_t *lock; + unsigned int *share_count; +}; + +static int clk_gate_shared_enable(struct clk_hw *hw) +{ + struct clk_gate *gate = to_clk_gate(hw); + struct clk_gate_shared *shgate = container_of(gate, + struct clk_gate_shared, gate); + unsigned long flags = 0; + int ret = 0; + + spin_lock_irqsave(shgate->lock, flags); + + if (shgate->share_count && (*shgate->share_count)++ > 0) + goto out; + + ret = clk_gate_ops.enable(hw); +out: + spin_unlock_irqrestore(shgate->lock, flags); + + return ret; +} + +static void clk_gate_shared_disable(struct clk_hw *hw) +{ + struct clk_gate *gate = to_clk_gate(hw); + struct clk_gate_shared *shgate = container_of(gate, + struct clk_gate_shared, gate); + unsigned long flags = 0; + + spin_lock_irqsave(shgate->lock, flags); + + if (shgate->share_count) { + if (WARN_ON(*shgate->share_count == 0)) + goto out; + else if (--(*shgate->share_count) > 0) + goto out; + } + + clk_gate_ops.disable(hw); +out: + spin_unlock_irqrestore(shgate->lock, flags); +} + +static int clk_gate_shared_is_enabled(struct clk_hw *hw) +{ + return clk_gate_ops.is_enabled(hw); +} + +static const struct clk_ops clk_gate_shared_ops = { + .enable = clk_gate_shared_enable, + .disable = clk_gate_shared_disable, + .is_enabled = clk_gate_shared_is_enabled, +}; + +struct clk *imx_dev_clk_gate_shared(struct device *dev, const char *name, + const char *parent, void __iomem *reg, + u8 shift, unsigned int *share_count) +{ + struct clk_gate_shared *shgate; + struct clk_gate *gate; + struct clk *clk; + struct clk_init_data init; + + shgate = kzalloc(sizeof(*shgate), GFP_KERNEL); + if (!shgate) + return ERR_PTR(-ENOMEM); + gate = &shgate->gate; + + init.name = name; + init.ops = &clk_gate_shared_ops; + init.flags = CLK_OPS_PARENT_ENABLE; + init.parent_names = parent ? &parent : NULL; + init.num_parents = parent ? 1 : 0; + + gate->reg = reg; + gate->bit_idx = shift; + gate->lock = NULL; + gate->hw.init = &init; + shgate->lock = &imx_ccm_lock; + shgate->share_count = share_count; + + clk = clk_register(dev, &gate->hw); + if (IS_ERR(clk)) + kfree(shgate); + + return clk; +} diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c index 7d44ce81480639..d9a4487dd384ef 100644 --- a/drivers/clk/imx/clk-gate2.c +++ b/drivers/clk/imx/clk-gate2.c @@ -7,11 +7,13 @@ */ #include +#include #include #include #include #include #include +#include #include "clk.h" /** @@ -35,11 +37,56 @@ struct clk_gate2 { }; #define to_clk_gate2(_hw) container_of(_hw, struct clk_gate2, hw) +#define CCM_CCGR_FULL_ENABLE 0x3 + +static void clk_gate2_do_hardware(struct clk_gate2 *gate, bool enable) +{ + u32 reg; + + reg = readl(gate->reg); + if (enable) + reg |= CCM_CCGR_FULL_ENABLE << gate->bit_idx; + else + reg &= ~(CCM_CCGR_FULL_ENABLE << gate->bit_idx); + writel(reg, gate->reg); +} + +static void clk_gate2_do_shared_clks(struct clk_hw *hw, bool enable) +{ + struct clk_gate2 *gate = to_clk_gate2(hw); + + if (imx_src_is_m4_enabled() && clk_on_imx6sx()) { +#ifdef CONFIG_SOC_IMX6SX + if (!amp_power_mutex || !shared_mem) { + if (enable) + clk_gate2_do_hardware(gate, enable); + return; + } + + imx_sema4_mutex_lock(amp_power_mutex); + if (shared_mem->ca9_valid != SHARED_MEM_MAGIC_NUMBER || + shared_mem->cm4_valid != SHARED_MEM_MAGIC_NUMBER) { + imx_sema4_mutex_unlock(amp_power_mutex); + return; + } + + if (!imx_update_shared_mem(hw, enable)) { + imx_sema4_mutex_unlock(amp_power_mutex); + return; + } + + clk_gate2_do_hardware(gate, enable); + + imx_sema4_mutex_unlock(amp_power_mutex); +#endif + } else { + clk_gate2_do_hardware(gate, enable); + } +} static int clk_gate2_enable(struct clk_hw *hw) { struct clk_gate2 *gate = to_clk_gate2(hw); - u32 reg; unsigned long flags = 0; spin_lock_irqsave(gate->lock, flags); @@ -47,11 +94,7 @@ static int clk_gate2_enable(struct clk_hw *hw) if (gate->share_count && (*gate->share_count)++ > 0) goto out; - reg = readl(gate->reg); - reg &= ~(3 << gate->bit_idx); - reg |= gate->cgr_val << gate->bit_idx; - writel(reg, gate->reg); - + clk_gate2_do_shared_clks(hw, true); out: spin_unlock_irqrestore(gate->lock, flags); @@ -61,7 +104,6 @@ static int clk_gate2_enable(struct clk_hw *hw) static void clk_gate2_disable(struct clk_hw *hw) { struct clk_gate2 *gate = to_clk_gate2(hw); - u32 reg; unsigned long flags = 0; spin_lock_irqsave(gate->lock, flags); @@ -73,10 +115,7 @@ static void clk_gate2_disable(struct clk_hw *hw) goto out; } - reg = readl(gate->reg); - reg &= ~(3 << gate->bit_idx); - writel(reg, gate->reg); - + clk_gate2_do_shared_clks(hw, false); out: spin_unlock_irqrestore(gate->lock, flags); } @@ -102,15 +141,11 @@ static void clk_gate2_disable_unused(struct clk_hw *hw) { struct clk_gate2 *gate = to_clk_gate2(hw); unsigned long flags = 0; - u32 reg; spin_lock_irqsave(gate->lock, flags); - if (!gate->share_count || *gate->share_count == 0) { - reg = readl(gate->reg); - reg &= ~(3 << gate->bit_idx); - writel(reg, gate->reg); - } + if (!gate->share_count || *gate->share_count == 0) + clk_gate2_do_shared_clks(hw, false); spin_unlock_irqrestore(gate->lock, flags); } diff --git a/drivers/clk/imx/clk-hdmimix.c b/drivers/clk/imx/clk-hdmimix.c new file mode 100644 index 00000000000000..92fbe789ce011f --- /dev/null +++ b/drivers/clk/imx/clk-hdmimix.c @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +static struct clk *clks[IMX8MP_CLK_HDMIMIX_END]; +static struct clk_onecell_data clk_data; +static uint32_t hdmimix_clk_saved_regs[2]; + +static const char *imx_hdmi_phy_clks_sels[] = { "hdmi_glb_24m", "dummy",}; +static const char *imx_lcdif_clks_sels[] = { "dummy", "hdmi_glb_pix", }; +static const char *imx_hdmi_pipe_clks_sels[] = {"dummy","hdmi_glb_pix", }; + +static int imx_hdmimix_clk_suspend(struct device *dev) +{ + void __iomem *base; + + base = dev_get_drvdata(dev->parent); + + hdmimix_clk_saved_regs[0] = readl(base + 0x40); + hdmimix_clk_saved_regs[1] = readl(base + 0x50); + + return 0; +} + +static int imx_hdmimix_clk_resume(struct device *dev) +{ + void __iomem *base; + + base = dev_get_drvdata(dev->parent); + + writel(hdmimix_clk_saved_regs[0], base + 0x40); + writel(hdmimix_clk_saved_regs[1], base + 0x50); + + return 0; +} + +static int imx_hdmimix_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + void __iomem *base; + struct clk *clk_dummy; + int ret; + + pm_runtime_enable(dev); + pm_runtime_get_sync(dev); + + /* Defer until CCM driver is probed */ + clk_dummy = of_clk_get_by_name(np, "dummy"); + if (IS_ERR(clk_dummy)) + return PTR_ERR(clk_dummy); + + base = dev_get_drvdata(dev->parent); + if (IS_ERR(base)) + return PTR_ERR(base); + + clks[IMX8MP_CLK_HDMIMIX_GLOBAL_APB_CLK] = imx_dev_clk_gate(dev, "hdmi_glb_apb", "hdmi_apb", base + 0x40, 0); + clks[IMX8MP_CLK_HDMIMIX_GLOBAL_B_CLK] = imx_dev_clk_gate(dev, "hdmi_glb_b", "hdmi_axi", base + 0x40, 1); + clks[IMX8MP_CLK_HDMIMIX_GLOBAL_REF266M_CLK]= imx_dev_clk_gate(dev, "hdmi_glb_ref_266m","hdmi_ref_266m", base + 0x40, 2); + clks[IMX8MP_CLK_HDMIMIX_GLOBAL_XTAL24M_CLK]= imx_dev_clk_gate(dev, "hdmi_glb_24m", "hdmi_24m", base + 0x40, 4); + clks[IMX8MP_CLK_HDMIMIX_GLOBAL_XTAL32K_CLK]= imx_dev_clk_gate(dev, "hdmi_glb_32k", "osc_32k", base + 0x40, 5); + clks[IMX8MP_CLK_HDMIMIX_GLOBAL_TX_PIX_CLK] = imx_dev_clk_gate(dev, "hdmi_glb_pix", "hdmi_phy", base + 0x40, 7); + clks[IMX8MP_CLK_HDMIMIX_IRQS_STEER_CLK] = imx_dev_clk_gate(dev, "hdmi_irq_steer", "hdmi_glb_apb", base + 0x40, 9); + clks[IMX8MP_CLK_HDMIMIX_NOC_HDMI_CLK] = imx_dev_clk_gate(dev, "hdmi_noc", "hdmi_glb_apb", base + 0x40, 10); + clks[IMX8MP_CLK_HDMIMIX_NOC_HDCP_CLK] = imx_dev_clk_gate(dev, "hdcp_noc", "hdmi_glb_apb", base + 0x40, 11); + clks[IMX8MP_CLK_HDMIMIX_LCDIF_APB_CLK] = imx_dev_clk_gate(dev, "lcdif3_apb", "hdmi_glb_apb", base + 0x40, 16); + clks[IMX8MP_CLK_HDMIMIX_LCDIF_B_CLK] = imx_dev_clk_gate(dev, "lcdif3_b", "hdmi_glb_b", base + 0x40, 17); + clks[IMX8MP_CLK_HDMIMIX_LCDIF_PDI_CLK] = imx_dev_clk_gate(dev, "lcdif3_pdi", "hdmi_glb_apb", base + 0x40, 18); + clks[IMX8MP_CLK_HDMIMIX_LCDIF_PIX_CLK] = imx_dev_clk_gate(dev, "lcdif3_pxl", "hdmi_glb_pix", base + 0x40, 19); + clks[IMX8MP_CLK_HDMIMIX_LCDIF_SPU_CLK] = imx_dev_clk_gate(dev, "lcdif3_spu", "hdmi_glb_apb", base + 0x40, 20); + + clks[IMX8MP_CLK_HDMIMIX_FDCC_REF_CLK] = imx_dev_clk_gate(dev, "hdmi_fdcc_ref", "hdmi_fdcc_tst", base + 0x50, 2); + clks[IMX8MP_CLK_HDMIMIX_HRV_MWR_APB_CLK] = imx_dev_clk_gate(dev, "hrv_mwr_apb", "hdmi_glb_apb", base + 0x50, 3); + clks[IMX8MP_CLK_HDMIMIX_HRV_MWR_B_CLK] = imx_dev_clk_gate(dev, "hrv_mwr_b", "hdmi_glb_axi", base + 0x50, 4); + clks[IMX8MP_CLK_HDMIMIX_HRV_MWR_CEA_CLK] = imx_dev_clk_gate(dev, "hrv_mwr_cea", "hdmi_glb_apb", base + 0x50, 5); + clks[IMX8MP_CLK_HDMIMIX_VSFD_CEA_CLK] = imx_dev_clk_gate(dev, "vsfd_cea", "hdmi_glb_apb", base + 0x50, 6); + clks[IMX8MP_CLK_HDMIMIX_TX_HPI_CLK] = imx_dev_clk_gate(dev, "hdmi_tx_hpi", "hdmi_glb_apb", base + 0x50, 13); + clks[IMX8MP_CLK_HDMIMIX_TX_APB_CLK] = imx_dev_clk_gate(dev, "hdmi_tx_apb", "hdmi_glb_apb", base + 0x50, 14); + clks[IMX8MP_CLK_HDMIMIX_TX_CEC_CLK] = imx_dev_clk_gate(dev, "hdmi_cec", "hdmi_glb_32k", base + 0x50, 15); + clks[IMX8MP_CLK_HDMIMIX_TX_ESM_CLK] = imx_dev_clk_gate(dev, "hdmi_esm", "hdmi_glb_ref_266m", base + 0x50, 16); + clks[IMX8MP_CLK_HDMIMIX_TX_GPA_CLK] = imx_dev_clk_gate(dev, "hdmi_tx_gpa", "hdmi_glb_apb", base + 0x50, 17); + clks[IMX8MP_CLK_HDMIMIX_TX_PIXEL_CLK] = imx_dev_clk_gate(dev, "hdmi_tx_pix", "hdmi_glb_pix", base + 0x50, 18); + clks[IMX8MP_CLK_HDMIMIX_TX_SFR_CLK] = imx_dev_clk_gate(dev, "hdmi_tx_sfr", "hdmi_glb_apb", base + 0x50, 19); + clks[IMX8MP_CLK_HDMIMIX_TX_SKP_CLK] = imx_dev_clk_gate(dev, "hdmi_tx_skp", "hdmi_glb_apb", base + 0x50, 20); + clks[IMX8MP_CLK_HDMIMIX_TX_PREP_CLK] = imx_dev_clk_gate(dev, "hdmi_tx_prep", "hdmi_glb_apb", base + 0x50, 21); + clks[IMX8MP_CLK_HDMIMIX_TX_PHY_APB_CLK] = imx_dev_clk_gate(dev, "hdmi_phy_apb", "hdmi_glb_apb", base + 0x50, 22); + clks[IMX8MP_CLK_HDMIMIX_TX_PHY_INT_CLK] = imx_dev_clk_gate(dev, "hdmi_phy_int", "hdmi_glb_apb", base + 0x50, 24); + clks[IMX8MP_CLK_HDMIMIX_TX_SEC_MEM_CLK] = imx_dev_clk_gate(dev, "hdmi_sec_mem", "hdmi_glb_ref_266m", base + 0x50, 25); + clks[IMX8MP_CLK_HDMIMIX_TX_TRNG_SKP_CLK] = imx_dev_clk_gate(dev, "hdmi_trng_skp", "hdmi_glb_apb", base + 0x50, 27); + clks[IMX8MP_CLK_HDMIMIX_TX_VID_LINK_PIX_CLK]= imx_dev_clk_gate(dev, "hdmi_vid_pix", "hdmi_glb_pix", base + 0x50, 28); + clks[IMX8MP_CLK_HDMIMIX_TX_TRNG_APB_CLK] = imx_dev_clk_gate(dev, "hdmi_trng_apb", "hdmi_glb_apb", base + 0x50, 30); + + clks[IMX8MP_CLK_HDMIMIX_HTXPHY_CLK_SEL] = imx_dev_clk_mux(dev, "hdmi_phy_sel", base + 0x50, 10, 1, imx_hdmi_phy_clks_sels, ARRAY_SIZE(imx_hdmi_phy_clks_sels)); + clks[IMX8MP_CLK_HDMIMIX_LCDIF_CLK_SEL] = imx_dev_clk_mux(dev, "lcdif_clk_sel", base + 0x50, 11, 1, imx_lcdif_clks_sels, ARRAY_SIZE(imx_hdmi_phy_clks_sels)); + clks[IMX8MP_CLK_HDMIMIX_TX_PIPE_CLK_SEL] = imx_dev_clk_mux(dev, "hdmi_pipe_sel", base + 0x50, 12, 1, imx_hdmi_pipe_clks_sels, ARRAY_SIZE(imx_hdmi_pipe_clks_sels)); + + /* hdmi/lcdif pixel clock parent to hdmi phy */ + clk_set_parent(clks[IMX8MP_CLK_HDMIMIX_TX_PIPE_CLK_SEL], clks[IMX8MP_CLK_HDMIMIX_GLOBAL_TX_PIX_CLK]); + clk_set_parent(clks[IMX8MP_CLK_HDMIMIX_LCDIF_CLK_SEL], clks[IMX8MP_CLK_HDMIMIX_GLOBAL_TX_PIX_CLK]); + /* hdmi ref clock from 24MHz */ + clk_set_parent(clks[IMX8MP_CLK_HDMIMIX_HTXPHY_CLK_SEL], clks[IMX8MP_CLK_HDMIMIX_GLOBAL_XTAL24M_CLK]); + + imx_check_clocks(clks, ARRAY_SIZE(clks)); + + clk_data.clks = clks; + clk_data.clk_num = ARRAY_SIZE(clks); + ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + if (ret < 0) { + pr_err("failed to register clks for i.MX8MP\n"); + return -EINVAL; + } + + pm_runtime_put(dev); + + return 0; +} + +UNIVERSAL_DEV_PM_OPS(imx_hdmimix_clk_pm_ops, imx_hdmimix_clk_suspend, + imx_hdmimix_clk_resume, NULL); + +static const struct of_device_id imx_hdmimix_clk_of_match[] = { + { .compatible = "fsl,imx8mp-hdmimix-clk" }, + { /* Sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, imx_hdmimix_clk_of_match); + + +static struct platform_driver imx_hdmimix_clk_driver = { + .probe = imx_hdmimix_clk_probe, + .driver = { + .name = "imx-hdmimix-clk", + .of_match_table = of_match_ptr(imx_hdmimix_clk_of_match), + .pm = &imx_hdmimix_clk_pm_ops, + }, +}; +module_platform_driver(imx_hdmimix_clk_driver); diff --git a/drivers/clk/imx/clk-imx-acm-utils.c b/drivers/clk/imx/clk-imx-acm-utils.c new file mode 100644 index 00000000000000..b923e117dd1a98 --- /dev/null +++ b/drivers/clk/imx/clk-imx-acm-utils.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright 2020 NXP + +#include +#include +#include "clk-imx-acm-utils.h" + +/** + * clk_imx_acm_attach_pm_domains + */ +int clk_imx_acm_attach_pm_domains(struct device *dev, + struct clk_imx_acm_pm_domains *dev_pm) +{ + int ret; + int i; + + dev_pm->num_domains = of_count_phandle_with_args(dev->of_node, "power-domains", + "#power-domain-cells"); + if (dev_pm->num_domains <= 1) + return 0; + + dev_pm->pd_dev = devm_kmalloc_array(dev, dev_pm->num_domains, + sizeof(*dev_pm->pd_dev), + GFP_KERNEL); + if (!dev_pm->pd_dev) + return -ENOMEM; + + dev_pm->pd_dev_link = devm_kmalloc_array(dev, + dev_pm->num_domains, + sizeof(*dev_pm->pd_dev_link), + GFP_KERNEL); + if (!dev_pm->pd_dev_link) + return -ENOMEM; + + for (i = 0; i < dev_pm->num_domains; i++) { + dev_pm->pd_dev[i] = dev_pm_domain_attach_by_id(dev, i); + if (IS_ERR(dev_pm->pd_dev[i])) + return PTR_ERR(dev_pm->pd_dev[i]); + + dev_pm->pd_dev_link[i] = device_link_add(dev, + dev_pm->pd_dev[i], + DL_FLAG_STATELESS | + DL_FLAG_PM_RUNTIME | + DL_FLAG_RPM_ACTIVE); + if (IS_ERR(dev_pm->pd_dev_link[i])) { + dev_pm_domain_detach(dev_pm->pd_dev[i], false); + ret = PTR_ERR(dev_pm->pd_dev_link[i]); + goto detach_pm; + } + } + return 0; + +detach_pm: + while (--i >= 0) { + device_link_del(dev_pm->pd_dev_link[i]); + dev_pm_domain_detach(dev_pm->pd_dev[i], false); + } + return ret; +} + +/** + * fsl_dev_detach_pm_domains + */ +int clk_imx_acm_detach_pm_domains(struct device *dev, + struct clk_imx_acm_pm_domains *dev_pm) +{ + int i; + + if (dev_pm->num_domains <= 1) + return 0; + + for (i = 0; i < dev_pm->num_domains; i++) { + device_link_del(dev_pm->pd_dev_link[i]); + dev_pm_domain_detach(dev_pm->pd_dev[i], false); + } + + return 0; +} diff --git a/drivers/clk/imx/clk-imx-acm-utils.h b/drivers/clk/imx/clk-imx-acm-utils.h new file mode 100644 index 00000000000000..662e0d123a1e98 --- /dev/null +++ b/drivers/clk/imx/clk-imx-acm-utils.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright 2020 NXP */ + +#ifndef _CLK_IMX_ACM_UTILS_H +#define _CLK_IMX_ACM_UTILS_H + +#include + +struct clk_imx_acm_pm_domains { + struct device **pd_dev; + struct device_link **pd_dev_link; + int num_domains; +}; + +int clk_imx_acm_attach_pm_domains(struct device *dev, + struct clk_imx_acm_pm_domains *dev_pm); +int clk_imx_acm_detach_pm_domains(struct device *dev, + struct clk_imx_acm_pm_domains *dev_pm); +#endif /* _CLK_IMX_ACM_UTILS_H */ diff --git a/drivers/clk/imx/clk-imx25.c b/drivers/clk/imx/clk-imx25.c index a66cabfbf94f10..cc013b343e62a9 100644 --- a/drivers/clk/imx/clk-imx25.c +++ b/drivers/clk/imx/clk-imx25.c @@ -73,16 +73,6 @@ enum mx25_clks { static struct clk *clk[clk_max]; -static struct clk ** const uart_clks[] __initconst = { - &clk[uart_ipg_per], - &clk[uart1_ipg], - &clk[uart2_ipg], - &clk[uart3_ipg], - &clk[uart4_ipg], - &clk[uart5_ipg], - NULL -}; - static int __init __mx25_clocks_init(void __iomem *ccm_base) { BUG_ON(!ccm_base); @@ -228,7 +218,7 @@ static int __init __mx25_clocks_init(void __iomem *ccm_base) */ clk_set_parent(clk[cko_sel], clk[ipg]); - imx_register_uart_clocks(uart_clks); + imx_register_uart_clocks(); return 0; } diff --git a/drivers/clk/imx/clk-imx27.c b/drivers/clk/imx/clk-imx27.c index a3753067fc120d..ee9ef5079e40b1 100644 --- a/drivers/clk/imx/clk-imx27.c +++ b/drivers/clk/imx/clk-imx27.c @@ -49,17 +49,6 @@ static const char *ssi_sel_clks[] = { "spll_gate", "mpll", }; static struct clk *clk[IMX27_CLK_MAX]; static struct clk_onecell_data clk_data; -static struct clk ** const uart_clks[] __initconst = { - &clk[IMX27_CLK_PER1_GATE], - &clk[IMX27_CLK_UART1_IPG_GATE], - &clk[IMX27_CLK_UART2_IPG_GATE], - &clk[IMX27_CLK_UART3_IPG_GATE], - &clk[IMX27_CLK_UART4_IPG_GATE], - &clk[IMX27_CLK_UART5_IPG_GATE], - &clk[IMX27_CLK_UART6_IPG_GATE], - NULL -}; - static void __init _mx27_clocks_init(unsigned long fref) { BUG_ON(!ccm); @@ -176,7 +165,7 @@ static void __init _mx27_clocks_init(unsigned long fref) clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]); - imx_register_uart_clocks(uart_clks); + imx_register_uart_clocks(); imx_print_silicon_rev("i.MX27", mx27_revision()); } diff --git a/drivers/clk/imx/clk-imx31.c b/drivers/clk/imx/clk-imx31.c index 4bb05e440cdd64..ae9ff78d45bf8a 100644 --- a/drivers/clk/imx/clk-imx31.c +++ b/drivers/clk/imx/clk-imx31.c @@ -51,16 +51,6 @@ enum mx31_clks { static struct clk *clk[clk_max]; static struct clk_onecell_data clk_data; -static struct clk ** const uart_clks[] __initconst = { - &clk[ipg], - &clk[uart1_gate], - &clk[uart2_gate], - &clk[uart3_gate], - &clk[uart4_gate], - &clk[uart5_gate], - NULL -}; - static void __init _mx31_clocks_init(void __iomem *base, unsigned long fref) { clk[dummy] = imx_clk_fixed("dummy", 0); @@ -197,7 +187,7 @@ int __init mx31_clocks_init(unsigned long fref) clk_register_clkdev(clk[iim_gate], "iim", NULL); - imx_register_uart_clocks(uart_clks); + imx_register_uart_clocks(); mxc_timer_init(MX31_GPT1_BASE_ADDR, MX31_INT_GPT, GPT_TYPE_IMX31); return 0; diff --git a/drivers/clk/imx/clk-imx35.c b/drivers/clk/imx/clk-imx35.c index e595f559907fbf..c97511360e0911 100644 --- a/drivers/clk/imx/clk-imx35.c +++ b/drivers/clk/imx/clk-imx35.c @@ -82,14 +82,6 @@ enum mx35_clks { static struct clk *clk[clk_max]; -static struct clk ** const uart_clks[] __initconst = { - &clk[ipg], - &clk[uart1_gate], - &clk[uart2_gate], - &clk[uart3_gate], - NULL -}; - static void __init _mx35_clocks_init(void) { void __iomem *base; @@ -243,7 +235,7 @@ static void __init _mx35_clocks_init(void) */ clk_prepare_enable(clk[scc_gate]); - imx_register_uart_clocks(uart_clks); + imx_register_uart_clocks(); imx_print_silicon_rev("i.MX35", mx35_revision()); } diff --git a/drivers/clk/imx/clk-imx5.c b/drivers/clk/imx/clk-imx5.c index 01e079b8102617..b8204491160316 100644 --- a/drivers/clk/imx/clk-imx5.c +++ b/drivers/clk/imx/clk-imx5.c @@ -128,30 +128,6 @@ static const char *ieee1588_sels[] = { "pll3_sw", "pll4_sw", "dummy" /* usbphy2_ static struct clk *clk[IMX5_CLK_END]; static struct clk_onecell_data clk_data; -static struct clk ** const uart_clks_mx51[] __initconst = { - &clk[IMX5_CLK_UART1_IPG_GATE], - &clk[IMX5_CLK_UART1_PER_GATE], - &clk[IMX5_CLK_UART2_IPG_GATE], - &clk[IMX5_CLK_UART2_PER_GATE], - &clk[IMX5_CLK_UART3_IPG_GATE], - &clk[IMX5_CLK_UART3_PER_GATE], - NULL -}; - -static struct clk ** const uart_clks_mx50_mx53[] __initconst = { - &clk[IMX5_CLK_UART1_IPG_GATE], - &clk[IMX5_CLK_UART1_PER_GATE], - &clk[IMX5_CLK_UART2_IPG_GATE], - &clk[IMX5_CLK_UART2_PER_GATE], - &clk[IMX5_CLK_UART3_IPG_GATE], - &clk[IMX5_CLK_UART3_PER_GATE], - &clk[IMX5_CLK_UART4_IPG_GATE], - &clk[IMX5_CLK_UART4_PER_GATE], - &clk[IMX5_CLK_UART5_IPG_GATE], - &clk[IMX5_CLK_UART5_PER_GATE], - NULL -}; - static void __init mx5_clocks_common_init(void __iomem *ccm_base) { clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0); @@ -382,7 +358,7 @@ static void __init mx50_clocks_init(struct device_node *np) r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); - imx_register_uart_clocks(uart_clks_mx50_mx53); + imx_register_uart_clocks(); } CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init); @@ -488,7 +464,7 @@ static void __init mx51_clocks_init(struct device_node *np) val |= 1 << 23; writel(val, MXC_CCM_CLPCR); - imx_register_uart_clocks(uart_clks_mx51); + imx_register_uart_clocks(); } CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init); @@ -633,6 +609,6 @@ static void __init mx53_clocks_init(struct device_node *np) r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); - imx_register_uart_clocks(uart_clks_mx50_mx53); + imx_register_uart_clocks(); } CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init); diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index 60f2de851f39fc..f32c57d39d96f3 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -26,7 +26,8 @@ static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; -static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", }; +static const char *axi_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_540m", }; +static const char *axi_sels[] = { "periph", "axi_alt_sel", }; static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; static const char *gpu_axi_sels[] = { "axi", "ahb", }; static const char *pre_axi_sels[] = { "axi", "ahb", }; @@ -36,15 +37,17 @@ static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_p static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", }; static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", }; +static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", }; +static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", }; static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", }; static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; -static const char *ipu1_di0_sels_2[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; -static const char *ipu1_di1_sels_2[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; -static const char *ipu2_di0_sels_2[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; -static const char *ipu2_di1_sels_2[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; +static const char *ipu1_di0_sels_2[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0_div_sel", "ldb_di1_div_sel", }; +static const char *ipu1_di1_sels_2[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0_div_sel", "ldb_di1_div_sel", }; +static const char *ipu2_di0_sels_2[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0_div_sel", "ldb_di1_div_sel", }; +static const char *ipu2_di1_sels_2[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0_div_sel", "ldb_di1_div_sel", }; static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", }; static const char *pcie_axi_sels[] = { "axi", "ahb", }; static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", }; @@ -90,6 +93,7 @@ static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; static struct clk_hw **hws; static struct clk_hw_onecell_data *clk_hw_data; +static void __iomem *ccm_base; static struct clk_div_table clk_enet_ref_table[] = { { .val = 0, .div = 20, }, @@ -139,13 +143,6 @@ static inline int clk_on_imx6dl(void) return of_machine_is_compatible("fsl,imx6dl"); } -static const int uart_clk_ids[] __initconst = { - IMX6QDL_CLK_UART_IPG, - IMX6QDL_CLK_UART_SERIAL, -}; - -static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata; - static int ldb_di_sel_by_clock_id(int clock_id) { switch (clock_id) { @@ -258,6 +255,11 @@ static bool pll6_bypassed(struct device_node *node) #define CCM_CCSR 0x0c #define CCM_CS2CDR 0x2c +#define CCM_CSCDR3 0x3c +#define CCM_CCGR0 0x68 +#define CCM_CCGR3 0x74 + +#define ANATOP_PLL3_PFD 0xf0 #define CCSR_PLL3_SW_CLK_SEL BIT(0) @@ -394,6 +396,62 @@ static void init_ldb_clks(struct device_node *np, void __iomem *ccm_base) #define PFD2_CLKGATE BIT(23) #define PFD3_CLKGATE BIT(31) +/* + * workaround for ERR010579, when switching the clock source of IPU clock + * root in CCM. even setting CCGR3[CG0]=0x0 to gate off clock before + * switching, IPU may hang due to no IPU clock from CCM. + */ +static void __init init_ipu_clk(void __iomem *anatop_base) +{ + u32 val, origin_podf; + + /* gate off the IPU1_IPU clock */ + val = readl_relaxed(ccm_base + CCM_CCGR3); + val &= ~0x3; + writel_relaxed(val, ccm_base + CCM_CCGR3); + + /* gate off IPU DCIC1/2 clocks */ + val = readl_relaxed(ccm_base + CCM_CCGR0); + val &= ~(0xf << 24); + writel_relaxed(val, ccm_base + CCM_CCGR0); + + /* set IPU_PODF to 3'b000 */ + val = readl_relaxed(ccm_base + CCM_CSCDR3); + origin_podf = val & (0x7 << 11); + val &= ~(0x7 << 11); + writel_relaxed(val, ccm_base + CCM_CSCDR3); + + /* disable PLL3_PFD1 */ + val = readl_relaxed(anatop_base + ANATOP_PLL3_PFD); + val &= ~(0x1 << 15); + writel_relaxed(val, anatop_base + ANATOP_PLL3_PFD); + + /* switch IPU_SEL clock to PLL3_PFD1 */ + val = readl_relaxed(ccm_base + CCM_CSCDR3); + val |= (0x3 << 9); + writel_relaxed(val, ccm_base + CCM_CSCDR3); + + /* restore the IPU PODF*/ + val = readl_relaxed(ccm_base + CCM_CSCDR3); + val |= origin_podf; + writel_relaxed(val, ccm_base + CCM_CSCDR3); + + /* enable PLL3_PFD1 */ + val = readl_relaxed(anatop_base + ANATOP_PLL3_PFD); + val |= (0x1 << 15); + writel_relaxed(val, anatop_base + ANATOP_PLL3_PFD); + + /* enable IPU1_IPU clock */ + val = readl_relaxed(ccm_base + CCM_CCGR3); + val |= 0x3; + writel_relaxed(val, ccm_base + CCM_CCGR3); + + /* enable IPU DCIC1/2 clock */ + val = readl_relaxed(ccm_base + CCM_CCGR0); + val |= (0xf << 24); + writel_relaxed(val, ccm_base + CCM_CCGR0); +} + static void disable_anatop_clocks(void __iomem *anatop_base) { unsigned int reg; @@ -439,7 +497,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) struct device_node *np; void __iomem *anatop_base, *base; int ret; - int i; clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, IMX6QDL_CLK_END), GFP_KERNEL); @@ -604,6 +661,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) np = ccm_node; base = of_iomap(np, 0); + ccm_base = base; WARN_ON(!base); /* name reg shift width parent_names num_parents */ @@ -613,7 +671,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) hws[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_hw_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); hws[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_hw_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_hw_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); - hws[IMX6QDL_CLK_AXI_SEL] = imx_clk_hw_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); + hws[IMX6QDL_CLK_AXI_ALT_SEL] = imx_clk_hw_mux("axi_alt_sel", base + 0x14, 7, 1, axi_alt_sels, ARRAY_SIZE(axi_alt_sels)); + hws[IMX6QDL_CLK_AXI_SEL] = imx_clk_hw_mux("axi_sel", base + 0x14, 6, 1, axi_sels, ARRAY_SIZE(axi_sels)); hws[IMX6QDL_CLK_ESAI_SEL] = imx_clk_hw_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); hws[IMX6QDL_CLK_ASRC_SEL] = imx_clk_hw_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); hws[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_hw_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); @@ -659,6 +718,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) hws[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_hw_mux_ldb("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); } + hws[IMX6QDL_CLK_LDB_DI0_DIV_SEL] = imx_clk_hw_mux_flags("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels), CLK_SET_RATE_PARENT); + hws[IMX6QDL_CLK_LDB_DI1_DIV_SEL] = imx_clk_hw_mux_flags("ldb_di1_div_sel", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels), CLK_SET_RATE_PARENT); hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_hw_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_hw_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_hw_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); @@ -727,6 +788,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) hws[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_hw_divider("uart_serial_podf", "uart_sel", base + 0x24, 0, 6); hws[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di0_div_3_5", "ldb_di0", 2, 7); hws[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di1_div_3_5", "ldb_di1", 2, 7); + hws[IMX6QDL_CLK_LDB_DI0_DIV_7] = imx_clk_hw_fixed_factor("ldb_di0_div_7", "ldb_di0", 1, 7); + hws[IMX6QDL_CLK_LDB_DI1_DIV_7] = imx_clk_hw_fixed_factor("ldb_di1_div_7", "ldb_di1", 1, 7); } else { hws[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_hw_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); hws[IMX6QDL_CLK_CAN_ROOT] = imx_clk_hw_divider("can_root", "pll3_60m", base + 0x20, 2, 6); @@ -734,6 +797,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) hws[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_hw_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6); hws[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); hws[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); + hws[IMX6QDL_CLK_LDB_DI0_DIV_7] = imx_clk_hw_fixed_factor("ldb_di0_div_7", "ldb_di0_sel", 1, 7); + hws[IMX6QDL_CLK_LDB_DI1_DIV_7] = imx_clk_hw_fixed_factor("ldb_di1_div_7", "ldb_di1_sel", 1, 7); } if (clk_on_imx6dl()) @@ -919,8 +984,19 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk_hw_register_clkdev(hws[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL); clk_set_rate(hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk, 540000000); - if (clk_on_imx6dl()) + if (clk_on_imx6dl()) { + init_ipu_clk(anatop_base); clk_set_parent(hws[IMX6QDL_CLK_IPU1_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk); + clk_set_parent(hws[IMX6QDL_CLK_AXI_ALT_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk); + clk_set_parent(hws[IMX6QDL_CLK_AXI_SEL]->clk, hws[IMX6QDL_CLK_AXI_ALT_SEL]->clk); + /* set epdc/pxp axi clock to 200Mhz */ + clk_set_parent(hws[IMX6QDL_CLK_IPU2_SEL]->clk, hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk); + clk_set_rate(hws[IMX6QDL_CLK_IPU2]->clk, 200000000); + } else { + clk_set_parent(hws[IMX6QDL_CLK_IPU1_SEL]->clk, hws[IMX6QDL_CLK_MMDC_CH0_AXI]->clk); + + clk_set_parent(hws[IMX6QDL_CLK_IPU2_SEL]->clk, hws[IMX6QDL_CLK_MMDC_CH0_AXI]->clk); + } clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); @@ -978,12 +1054,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk); } - for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) { - int index = uart_clk_ids[i]; - - uart_clks[i] = &hws[index]->clk; - } - - imx_register_uart_clocks(uart_clks); + imx_register_uart_clocks(); } CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init); diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c index 4bd44d89eaaa8b..f264359607842c 100644 --- a/drivers/clk/imx/clk-imx6sl.c +++ b/drivers/clk/imx/clk-imx6sl.c @@ -177,19 +177,11 @@ void imx6sl_set_wait_clk(bool enter) imx6sl_enable_pll_arm(false); } -static const int uart_clk_ids[] __initconst = { - IMX6SL_CLK_UART, - IMX6SL_CLK_UART_SERIAL, -}; - -static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata; - static void __init imx6sl_clocks_init(struct device_node *ccm_node) { struct device_node *np; void __iomem *base; int ret; - int i; clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, IMX6SL_CLK_END), GFP_KERNEL); @@ -438,19 +430,23 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) /* Audio-related clocks configuration */ clk_set_parent(hws[IMX6SL_CLK_SPDIF0_SEL]->clk, hws[IMX6SL_CLK_PLL3_PFD3]->clk); + /* Initialize Video PLLs to valid frequency (650MHz). */ + clk_set_rate(hws[IMX6SL_CLK_PLL5_VIDEO_DIV]->clk, 650000000); + /* set PLL5 video as lcdif pix parent clock */ clk_set_parent(hws[IMX6SL_CLK_LCDIF_PIX_SEL]->clk, hws[IMX6SL_CLK_PLL5_VIDEO_DIV]->clk); + /* Configure EPDC clocks */ + clk_set_parent(hws[IMX6SL_CLK_EPDC_PIX_SEL]->clk, + hws[IMX6SL_CLK_PLL5_VIDEO_DIV]->clk); + clk_set_parent(hws[IMX6SL_CLK_EPDC_AXI_SEL]->clk, + hws[IMX6SL_CLK_PLL2_PFD2]->clk); + clk_set_rate(hws[IMX6SL_CLK_EPDC_AXI]->clk, 200000000); + clk_set_parent(hws[IMX6SL_CLK_LCDIF_AXI_SEL]->clk, hws[IMX6SL_CLK_PLL2_PFD2]->clk); - for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) { - int index = uart_clk_ids[i]; - - uart_clks[i] = &hws[index]->clk; - } - - imx_register_uart_clocks(uart_clks); + imx_register_uart_clocks(); } CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init); diff --git a/drivers/clk/imx/clk-imx6sll.c b/drivers/clk/imx/clk-imx6sll.c index 5f3e92c09a5e6b..1035ef0e55a3e9 100644 --- a/drivers/clk/imx/clk-imx6sll.c +++ b/drivers/clk/imx/clk-imx6sll.c @@ -76,26 +76,10 @@ static u32 share_count_ssi1; static u32 share_count_ssi2; static u32 share_count_ssi3; -static const int uart_clk_ids[] __initconst = { - IMX6SLL_CLK_UART1_IPG, - IMX6SLL_CLK_UART1_SERIAL, - IMX6SLL_CLK_UART2_IPG, - IMX6SLL_CLK_UART2_SERIAL, - IMX6SLL_CLK_UART3_IPG, - IMX6SLL_CLK_UART3_SERIAL, - IMX6SLL_CLK_UART4_IPG, - IMX6SLL_CLK_UART4_SERIAL, - IMX6SLL_CLK_UART5_IPG, - IMX6SLL_CLK_UART5_SERIAL, -}; - -static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata; - static void __init imx6sll_clocks_init(struct device_node *ccm_node) { struct device_node *np; void __iomem *base; - int i; clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, IMX6SLL_CLK_END), GFP_KERNEL); @@ -356,13 +340,12 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node) of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); - for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) { - int index = uart_clk_ids[i]; - - uart_clks[i] = &hws[index]->clk; - } - - imx_register_uart_clocks(uart_clks); + /* Set the UART parent if needed */ + if (uart_from_osc) + clk_set_parent(hws[IMX6SLL_CLK_UART_SEL]->clk, hws[IMX6SLL_CLK_OSC]->clk); + else + clk_set_parent(hws[IMX6SLL_CLK_UART_SEL]->clk, hws[IMX6SLL_CLK_PLL3_80M]->clk); + imx_register_uart_clocks(); /* Lower the AHB clock rate before changing the clock source. */ clk_set_rate(hws[IMX6SLL_CLK_AHB]->clk, 99000000); @@ -372,6 +355,10 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node) clk_set_parent(hws[IMX6SLL_CLK_PERIPH]->clk, hws[IMX6SLL_CLK_PERIPH_CLK2]->clk); clk_set_parent(hws[IMX6SLL_CLK_PERIPH_PRE]->clk, hws[IMX6SLL_CLK_PLL2_BUS]->clk); clk_set_parent(hws[IMX6SLL_CLK_PERIPH]->clk, hws[IMX6SLL_CLK_PERIPH_PRE]->clk); + /* Configure EPDC clocks */ + clk_set_rate(hws[IMX6SLL_CLK_PLL3_PFD2]->clk, 320000000); + clk_set_parent(hws[IMX6SLL_CLK_EPDC_PRE_SEL]->clk, + hws[IMX6SLL_CLK_PLL3_PFD2]->clk); clk_set_rate(hws[IMX6SLL_CLK_AHB]->clk, 132000000); } diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c index c4685c01929a4a..274c31cf61a214 100644 --- a/drivers/clk/imx/clk-imx6sx.c +++ b/drivers/clk/imx/clk-imx6sx.c @@ -10,13 +10,18 @@ #include #include #include +#include #include #include #include #include +#include +#include #include "clk.h" +#define CCM_CCGR_OFFSET(index) (index * 2) + static const char *step_sels[] = { "osc", "pll2_pfd2_396m", }; static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; @@ -83,6 +88,12 @@ static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; static struct clk_hw **hws; static struct clk_hw_onecell_data *clk_hw_data; +struct imx_sema4_mutex *amp_power_mutex; + +static int clks_shared[MAX_SHARED_CLK_NUMBER]; + +struct imx_shared_mem *shared_mem; +static unsigned int shared_mem_paddr, shared_mem_size; static const struct clk_div_table clk_enet_ref_table[] = { { .val = 0, .div = 20, }, @@ -116,18 +127,43 @@ static u32 share_count_ssi3; static u32 share_count_sai1; static u32 share_count_sai2; -static const int uart_clk_ids[] __initconst = { - IMX6SX_CLK_UART_IPG, - IMX6SX_CLK_UART_SERIAL, -}; +/* + * As IMX6SX_CLK_M4_PRE_SEL is NOT a glitchless MUX, so when + * M4 is trying to change its clk parent, need to ask A9 to + * help do it, and M4 must be hold in wfi. To avoid glitch + * occur, need to gate M4 clk first before switching its parent. + */ +void imx6sx_set_m4_highfreq(bool high_freq) +{ + static struct clk *m4_high_freq_sel; + + imx_gpc_hold_m4_in_sleep(); + + clk_disable_unprepare(hws[IMX6SX_CLK_M4]->clk); + clk_set_parent(hws[IMX6SX_CLK_M4_SEL]->clk, + hws[IMX6SX_CLK_LDB_DI0]->clk); + + if (high_freq) { + /* FIXME: m4_high_freq_sel possible used without intialization? */ + clk_set_parent(hws[IMX6SX_CLK_M4_PRE_SEL]->clk, + m4_high_freq_sel); + } else { + m4_high_freq_sel = clk_get_parent(hws[IMX6SX_CLK_M4_PRE_SEL]->clk); + clk_set_parent(hws[IMX6SX_CLK_M4_PRE_SEL]->clk, + hws[IMX6SX_CLK_OSC]->clk); + } + + clk_set_parent(hws[IMX6SX_CLK_M4_SEL]->clk, + hws[IMX6SX_CLK_M4_PRE_SEL]->clk); + clk_prepare_enable(hws[IMX6SX_CLK_M4]->clk); -static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata; + imx_gpc_release_m4_in_sleep(); +} static void __init imx6sx_clocks_init(struct device_node *ccm_node) { struct device_node *np; void __iomem *base; - int i; clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, IMX6SX_CLK_CLK_END), GFP_KERNEL); @@ -189,7 +225,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clk_set_parent(hws[IMX6SX_PLL6_BYPASS]->clk, hws[IMX6SX_CLK_PLL6]->clk); clk_set_parent(hws[IMX6SX_PLL7_BYPASS]->clk, hws[IMX6SX_CLK_PLL7]->clk); - hws[IMX6SX_CLK_PLL1_SYS] = imx_clk_hw_gate("pll1_sys", "pll1_bypass", base + 0x00, 13); + hws[IMX6SX_CLK_PLL1_SYS] = imx_clk_hw_fixed_factor("pll1_sys", "pll1_bypass", 1, 1); hws[IMX6SX_CLK_PLL2_BUS] = imx_clk_hw_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); hws[IMX6SX_CLK_PLL3_USB_OTG] = imx_clk_hw_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); hws[IMX6SX_CLK_PLL4_AUDIO] = imx_clk_hw_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); @@ -405,7 +441,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) hws[IMX6SX_CLK_GPT_BUS] = imx_clk_hw_gate2("gpt_bus", "perclk", base + 0x6c, 20); hws[IMX6SX_CLK_GPT_SERIAL] = imx_clk_hw_gate2("gpt_serial", "perclk", base + 0x6c, 22); hws[IMX6SX_CLK_GPU] = imx_clk_hw_gate2("gpu", "gpu_core_podf", base + 0x6c, 26); - hws[IMX6SX_CLK_OCRAM_S] = imx_clk_hw_gate2("ocram_s", "ahb", base + 0x6c, 28); + hws[IMX6SX_CLK_OCRAM_S] = imx_clk_hw_gate2_flags("ocram_s", "ahb", base + 0x6c, 28, CLK_IS_CRITICAL); hws[IMX6SX_CLK_CANFD] = imx_clk_hw_gate2("canfd", "can_podf", base + 0x6c, 30); /* CCGR2 */ @@ -489,13 +525,59 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) hws[IMX6SX_CLK_CKO1] = imx_clk_hw_gate("cko1", "cko1_podf", base + 0x60, 7); hws[IMX6SX_CLK_CKO2] = imx_clk_hw_gate("cko2", "cko2_podf", base + 0x60, 24); + /* get those shared clk nodes if M4 is active */ + if (imx_src_is_m4_enabled()) { + u32 num; + + of_property_read_u32(np, "fsl,shared-clks-number", &num); + if (num > MAX_SHARED_CLK_NUMBER) + pr_err("clk: shared clk nodes exceed the max number!\n"); + of_property_read_u32_array(np, "fsl,shared-clks-index", + clks_shared, num); + if (of_property_read_u32(np, "fsl,shared-mem-addr", + &shared_mem_paddr)) + pr_err("clk: fsl,shared-mem-addr NOT found!\n"); + if (of_property_read_u32(np, "fsl,shared-mem-size", + &shared_mem_size)) + pr_err("clk: fsl,shared-mem-size NOT found!\n"); + } + /* mask handshake of mmdc */ imx_mmdc_mask_handshake(base, 0); imx_check_clk_hws(hws, IMX6SX_CLK_CLK_END); + /* + * QSPI2/GPMI_IO share the same clock source but with the + * different gate, need explicitely gate the QSPI2 & GPMI_IO + * during the clock init phase according to the SOC design. + */ + if (!imx_src_is_m4_enabled()) { + writel_relaxed(readl_relaxed(base + 0x78) & + ~(3 << CCM_CCGR_OFFSET(5)), base + 0x78); + writel_relaxed(readl_relaxed(base + 0x78) & + ~(3 << CCM_CCGR_OFFSET(14)), base + 0x78); + } + + of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); + /* + * As some of the modules need to access ocotp in MSL, + * need to make sure ocotp clk(CCM_CCGR2_CG6) is enabled + * during MSL, as on i.MX6SX, accessing OCOTP registers + * needs its clk on, it will be disabled by clk late + * init and managed by ocotp driver. + */ + writel_relaxed(readl_relaxed(base + 0x70) | 1 << 12, base + 0x70); + + /* maintain M4 usecount */ + if (imx_src_is_m4_enabled()) + clk_prepare_enable(hws[IMX6SX_CLK_M4]->clk); + + /* set perclk to from OSC */ + clk_set_parent(hws[IMX6SX_CLK_PERCLK_SEL]->clk, hws[IMX6SX_CLK_OSC]->clk); + if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { clk_prepare_enable(hws[IMX6SX_CLK_USBPHY1_GATE]->clk); clk_prepare_enable(hws[IMX6SX_CLK_USBPHY2_GATE]->clk); @@ -527,7 +609,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clk_set_rate(hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk, 393216000); clk_set_parent(hws[IMX6SX_CLK_SPDIF_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk); - clk_set_rate(hws[IMX6SX_CLK_SPDIF_PODF]->clk, 98304000); + clk_set_rate(hws[IMX6SX_CLK_SPDIF_PODF]->clk, 24576000); clk_set_parent(hws[IMX6SX_CLK_AUDIO_SEL]->clk, hws[IMX6SX_CLK_PLL3_USB_OTG]->clk); clk_set_rate(hws[IMX6SX_CLK_AUDIO_PODF]->clk, 24000000); @@ -542,6 +624,12 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clk_set_parent(hws[IMX6SX_CLK_ESAI_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk); clk_set_rate(hws[IMX6SX_CLK_ESAI_PODF]->clk, 24576000); + /* Set the UART parent if needed. */ + if (uart_from_osc) + clk_set_parent(hws[IMX6SX_CLK_UART_SEL]->clk, hws[IMX6SX_CLK_OSC]->clk); + else + clk_set_parent(hws[IMX6SX_CLK_UART_SEL]->clk, hws[IMX6SX_CLK_PLL3_80M]->clk); + /* Set parent clock for vadc */ clk_set_parent(hws[IMX6SX_CLK_VID_SEL]->clk, hws[IMX6SX_CLK_PLL3_USB_OTG]->clk); @@ -551,16 +639,74 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) /* Update gpu clock from default 528M to 720M */ clk_set_parent(hws[IMX6SX_CLK_GPU_CORE_SEL]->clk, hws[IMX6SX_CLK_PLL3_PFD0]->clk); clk_set_parent(hws[IMX6SX_CLK_GPU_AXI_SEL]->clk, hws[IMX6SX_CLK_PLL3_PFD0]->clk); + if (!imx_src_is_m4_enabled()) + /* default parent of can_sel clock is invalid, manually set it here */ + clk_set_parent(hws[IMX6SX_CLK_CAN_SEL]->clk, hws[IMX6SX_CLK_PLL3_60M]->clk); clk_set_parent(hws[IMX6SX_CLK_QSPI1_SEL]->clk, hws[IMX6SX_CLK_PLL2_BUS]->clk); clk_set_parent(hws[IMX6SX_CLK_QSPI2_SEL]->clk, hws[IMX6SX_CLK_PLL2_BUS]->clk); - for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) { - int index = uart_clk_ids[i]; + imx_register_uart_clocks(); +} +CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init); + +int imx_update_shared_mem(struct clk_hw *hw, bool enable) +{ + int i; - uart_clks[i] = &hws[index]->clk; + for (i = 0; i < ARRAY_SIZE(clks_shared); i++) { + if (shared_mem->imx_clk[i].self == hw->clk) + break; } - imx_register_uart_clocks(uart_clks); + if (i >= ARRAY_SIZE(clks_shared)) + return 1; + + /* update ca9 clk status in shared memory */ + if (enable) + shared_mem->imx_clk[i].ca9_enabled = 1; + else + shared_mem->imx_clk[i].ca9_enabled = 0; + + if (shared_mem->imx_clk[i].cm4_enabled == 0) + return 1; + + return 0; } -CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init); + +static int __init imx_amp_power_init(void) +{ + int i; + void __iomem *shared_mem_base; + + if (!(imx_src_is_m4_enabled() && clk_on_imx6sx())) + return 0; + + amp_power_mutex = imx_sema4_mutex_create(0, MCC_POWER_SHMEM_NUMBER); + + shared_mem_base = ioremap_nocache(shared_mem_paddr, shared_mem_size); + + if (!amp_power_mutex) { + pr_err("Failed to create sema4 mutex!\n"); + return 0; + } + + shared_mem = (struct imx_shared_mem *)shared_mem_base; + + for (i = 0; i < ARRAY_SIZE(clks_shared); i++) { + shared_mem->imx_clk[i].self = hws[clks_shared[i]]->clk; + shared_mem->imx_clk[i].ca9_enabled = 1; + pr_debug("%d: name %s, addr 0x%x\n", i, + __clk_get_name(shared_mem->imx_clk[i].self), + (u32)&(shared_mem->imx_clk[i])); + } + /* enable amp power management */ + shared_mem->ca9_valid = SHARED_MEM_MAGIC_NUMBER; + + pr_info("A9-M4 sema4 num %d, A9-M4 magic number 0x%x - 0x%x.\n", + amp_power_mutex->gate_num, shared_mem->ca9_valid, + shared_mem->cm4_valid); + + return 0; +} +late_initcall(imx_amp_power_init); diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c index bc931988fe7b24..6c0a8e0a7ef479 100644 --- a/drivers/clk/imx/clk-imx6ul.c +++ b/drivers/clk/imx/clk-imx6ul.c @@ -495,6 +495,12 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clk_set_rate(hws[IMX6UL_CLK_ENET2_REF]->clk, 50000000); clk_set_rate(hws[IMX6UL_CLK_CSI]->clk, 24000000); + /* Set the UART parent if needed */ + if (uart_from_osc) + clk_set_parent(hws[IMX6UL_CLK_UART_SEL]->clk, hws[IMX6UL_CLK_OSC]->clk); + else + clk_set_parent(hws[IMX6UL_CLK_UART_SEL]->clk, hws[IMX6UL_CLK_PLL3_80M]->clk); + if (clk_on_imx6ull()) clk_prepare_enable(hws[IMX6UL_CLK_AIPSTZ3]->clk); diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index fbea774ef6877b..ed70a57e2e6dcc 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -14,6 +14,7 @@ #include #include #include +#include #include "clk.h" @@ -23,6 +24,7 @@ static u32 share_count_sai3; static u32 share_count_nand; static u32 share_count_enet1; static u32 share_count_enet2; +static u32 share_count_pxp; static const struct clk_div_table test_div_table[] = { { .val = 3, .div = 1, }, @@ -376,23 +378,10 @@ static const char *pll_video_bypass_sel[] = { "pll_video_main", "pll_video_main_ static struct clk_hw **hws; static struct clk_hw_onecell_data *clk_hw_data; -static const int uart_clk_ids[] __initconst = { - IMX7D_UART1_ROOT_CLK, - IMX7D_UART2_ROOT_CLK, - IMX7D_UART3_ROOT_CLK, - IMX7D_UART4_ROOT_CLK, - IMX7D_UART5_ROOT_CLK, - IMX7D_UART6_ROOT_CLK, - IMX7D_UART7_ROOT_CLK, -}; - -static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata; - static void __init imx7d_clocks_init(struct device_node *ccm_node) { struct device_node *np; void __iomem *base; - int i; clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, IMX7D_CLK_END), GFP_KERNEL); @@ -865,6 +854,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) hws[IMX7D_USB_PHY1_CLK] = imx_clk_hw_gate4("usb_phy1_clk", "pll_usb1_main_clk", base + 0x46a0, 0); hws[IMX7D_USB_PHY2_CLK] = imx_clk_hw_gate4("usb_phy2_clk", "pll_usb_main_clk", base + 0x46b0, 0); hws[IMX7D_ADC_ROOT_CLK] = imx_clk_hw_gate4("adc_root_clk", "ipg_root_clk", base + 0x4200, 0); + hws[IMX7D_PXP_IPG_CLK] = imx_clk_hw_gate2_shared2("pxp_ipg_clk", "ipg_root_clk", base + 0x44c0, 0, &share_count_pxp); + hws[IMX7D_PXP_AXI_CLK] = imx_clk_hw_gate2_shared2("pxp_axi_clk", "main_axi_root_clk", base + 0x44c0, 0, &share_count_pxp); hws[IMX7D_GPT_3M_CLK] = imx_clk_hw_fixed_factor("gpt_3m", "osc", 1, 8); @@ -887,6 +878,12 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clk_set_parent(hws[IMX7D_MIPI_CSI_ROOT_SRC]->clk, hws[IMX7D_PLL_SYS_PFD3_CLK]->clk); + if (imx_src_is_m4_enabled()) { + clk_set_parent(hws[IMX7D_ARM_M4_ROOT_SRC]->clk, hws[IMX7D_PLL_SYS_MAIN_240M_CLK]->clk); + clk_prepare_enable(hws[IMX7D_ARM_M4_ROOT_CLK]->clk); + clk_prepare_enable(hws[IMX7D_UART2_ROOT_CLK]->clk); + } + /* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */ clk_set_parent(hws[IMX7D_GPT1_ROOT_SRC]->clk, hws[IMX7D_OSC_24M_CLK]->clk); @@ -894,14 +891,10 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) hws[IMX7D_USB1_MAIN_480M_CLK] = imx_clk_hw_fixed_factor("pll_usb1_main_clk", "osc", 20, 1); hws[IMX7D_USB_MAIN_480M_CLK] = imx_clk_hw_fixed_factor("pll_usb_main_clk", "osc", 20, 1); - for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) { - int index = uart_clk_ids[i]; - - uart_clks[i] = &hws[index]->clk; - } - + /* set parent of EPDC pixel clock */ + clk_set_parent(hws[IMX7D_EPDC_PIXEL_ROOT_SRC]->clk, hws[IMX7D_PLL_SYS_MAIN_CLK]->clk); - imx_register_uart_clocks(uart_clks); + imx_register_uart_clocks(); } CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init); diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c index 04a3ae979281cc..490b628a755e24 100644 --- a/drivers/clk/imx/clk-imx7ulp.c +++ b/drivers/clk/imx/clk-imx7ulp.c @@ -28,7 +28,7 @@ static const char * const scs_sels[] = { "dummy", "sosc", "sirc", "firc", "dumm static const char * const ddr_sels[] = { "apll_pfd_sel", "dummy", "dummy", "dummy", }; static const char * const nic_sels[] = { "firc", "ddr_clk", }; static const char * const periph_plat_sels[] = { "dummy", "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", }; -static const char * const periph_bus_sels[] = { "dummy", "sosc_bus_clk", "mpll", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", }; +static const char * const periph_bus_sels[] = { "dummy", "sosc_bus_clk", "dummy", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", }; static const char * const arm_sels[] = { "divcore", "dummy", "dummy", "hsrun_divcore", }; /* used by sosc/sirc/firc/ddr/spll/apll dividers */ @@ -48,14 +48,6 @@ static const int pcc2_uart_clk_ids[] __initconst = { IMX7ULP_CLK_LPUART5, }; -static const int pcc3_uart_clk_ids[] __initconst = { - IMX7ULP_CLK_LPUART6, - IMX7ULP_CLK_LPUART7, -}; - -static struct clk **pcc2_uart_clks[ARRAY_SIZE(pcc2_uart_clk_ids) + 1] __initdata; -static struct clk **pcc3_uart_clks[ARRAY_SIZE(pcc3_uart_clk_ids) + 1] __initdata; - static void __init imx7ulp_clk_scg1_init(struct device_node *np) { struct clk_hw_onecell_data *clk_data; @@ -76,7 +68,6 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np) clks[IMX7ULP_CLK_SOSC] = imx_obtain_fixed_clk_hw(np, "sosc"); clks[IMX7ULP_CLK_SIRC] = imx_obtain_fixed_clk_hw(np, "sirc"); clks[IMX7ULP_CLK_FIRC] = imx_obtain_fixed_clk_hw(np, "firc"); - clks[IMX7ULP_CLK_MIPI_PLL] = imx_obtain_fixed_clk_hw(np, "mpll"); clks[IMX7ULP_CLK_UPLL] = imx_obtain_fixed_clk_hw(np, "upll"); /* SCG1 */ @@ -149,7 +140,6 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np) struct clk_hw_onecell_data *clk_data; struct clk_hw **clks; void __iomem *base; - int i; clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC2_END), GFP_KERNEL); @@ -188,14 +178,6 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np) imx_check_clk_hws(clks, clk_data->num); of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); - - for (i = 0; i < ARRAY_SIZE(pcc2_uart_clk_ids); i++) { - int index = pcc2_uart_clk_ids[i]; - - pcc2_uart_clks[i] = &clks[index]->clk; - } - - imx_register_uart_clocks(pcc2_uart_clks); } CLK_OF_DECLARE(imx7ulp_clk_pcc2, "fsl,imx7ulp-pcc2", imx7ulp_clk_pcc2_init); @@ -204,7 +186,6 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np) struct clk_hw_onecell_data *clk_data; struct clk_hw **clks; void __iomem *base; - int i; clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC3_END), GFP_KERNEL); @@ -243,13 +224,7 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np) of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); - for (i = 0; i < ARRAY_SIZE(pcc3_uart_clk_ids); i++) { - int index = pcc3_uart_clk_ids[i]; - - pcc3_uart_clks[i] = &clks[index]->clk; - } - - imx_register_uart_clocks(pcc3_uart_clks); + imx_register_uart_clocks(); } CLK_OF_DECLARE(imx7ulp_clk_pcc3, "fsl,imx7ulp-pcc3", imx7ulp_clk_pcc3_init); diff --git a/drivers/clk/imx/clk-imx8dxl-acm.c b/drivers/clk/imx/clk-imx8dxl-acm.c new file mode 100644 index 00000000000000..fa993af90926e9 --- /dev/null +++ b/drivers/clk/imx/clk-imx8dxl-acm.c @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" +#include "clk-scu.h" +#include "clk-imx-acm-utils.h" + +#include + +struct imx8dxl_acm_priv { + struct clk_imx_acm_pm_domains dev_pm; + void __iomem *reg; + u32 regs[0x20]; +}; + +static const char *aud_clk_sels[] = { + "aud_rec_clk0_lpcg_clk", + "aud_rec_clk1_lpcg_clk", + "ext_aud_mclk0", + "ext_aud_mclk1", + "dummy", + "dummy", + "dummy", + "dummy", + "spdif0_rx", + "sai0_rx_bclk", + "sai0_tx_bclk", + "sai1_rx_bclk", + "sai1_tx_bclk", + "sai2_rx_bclk", + "sai3_rx_bclk", +}; + +static const char *mclk_out_sels[] = { + "aud_rec_clk0_lpcg_clk", + "aud_rec_clk1_lpcg_clk", + "dummy", + "dummy", + "spdif0_rx", + "dummy", + "dummy", + "dummy", +}; + +static const char *sai_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static const char *spdif_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static const char *mqs_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static int imx8dxl_acm_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct clk_onecell_data *clk_data; + struct imx8dxl_acm_priv *priv; + struct resource *res; + struct clk **clks; + void __iomem *base; + int ret; + int i; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap(dev, res->start, resource_size(res)); + if (!base) + return -ENOMEM; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->reg = base; + + platform_set_drvdata(pdev, priv); + + clk_data = devm_kzalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + clk_data->clks = devm_kcalloc(&pdev->dev, IMX_ADMA_ACM_CLK_END, + sizeof(*clk_data->clks), GFP_KERNEL); + if (!clk_data->clks) + return -ENOMEM; + + clk_data->clk_num = IMX_ADMA_ACM_CLK_END; + + clks = clk_data->clks; + + ret = clk_imx_acm_attach_pm_domains(&pdev->dev, &priv->dev_pm); + if (ret) + return ret; + + pm_runtime_enable(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + + clks[IMX_ADMA_EXT_AUD_MCLK0] = imx_clk_fixed("ext_aud_mclk0", 0); + clks[IMX_ADMA_EXT_AUD_MCLK1] = imx_clk_fixed("ext_aud_mclk1", 0); + clks[IMX_ADMA_SPDIF0_RX] = imx_clk_fixed("spdif0_rx", 0); + clks[IMX_ADMA_SAI0_RX_BCLK] = imx_clk_fixed("sai0_rx_bclk", 0); + clks[IMX_ADMA_SAI0_TX_BCLK] = imx_clk_fixed("sai0_tx_bclk", 0); + clks[IMX_ADMA_SAI1_RX_BCLK] = imx_clk_fixed("sai1_rx_bclk", 0); + clks[IMX_ADMA_SAI1_TX_BCLK] = imx_clk_fixed("sai1_tx_bclk", 0); + clks[IMX_ADMA_SAI2_RX_BCLK] = imx_clk_fixed("sai2_rx_bclk", 0); + clks[IMX_ADMA_SAI3_RX_BCLK] = imx_clk_fixed("sai3_rx_bclk", 0); + + clks[IMX_ADMA_ACM_AUD_CLK0_SEL] = imx_dev_clk_mux(dev, "acm_aud_clk0_sel", base+0x000000, 0, 5, aud_clk_sels, ARRAY_SIZE(aud_clk_sels)); + clks[IMX_ADMA_ACM_AUD_CLK1_CLK] = imx_dev_clk_mux(dev, "acm_aud_clk1_sel", base+0x010000, 0, 5, aud_clk_sels, ARRAY_SIZE(aud_clk_sels)); + + clks[IMX_ADMA_ACM_MCLKOUT0_SEL] = imx_dev_clk_mux(dev, "acm_mclkout0_sel", base+0x020000, 0, 3, mclk_out_sels, ARRAY_SIZE(mclk_out_sels)); + clks[IMX_ADMA_ACM_MCLKOUT1_SEL] = imx_dev_clk_mux(dev, "acm_mclkout1_sel", base+0x030000, 0, 3, mclk_out_sels, ARRAY_SIZE(mclk_out_sels)); + + clks[IMX_ADMA_ACM_SAI0_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai0_mclk_sel", base+0x0E0000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI1_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai1_mclk_sel", base+0x0F0000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI2_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai2_mclk_sel", base+0x100000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI3_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai3_mclk_sel", base+0x110000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + + clks[IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL] = imx_dev_clk_mux(dev, "acm_spdif0_mclk_sel", base+0x1A0000, 0, 2, spdif_mclk_sels, ARRAY_SIZE(spdif_mclk_sels)); + clks[IMX_ADMA_ACM_MQS_TX_CLK_SEL] = imx_dev_clk_mux(dev, "acm_mqs_mclk_sel", base+0x1C0000, 0, 2, mqs_mclk_sels, ARRAY_SIZE(mqs_mclk_sels)); + + for (i = 0; i < clk_data->clk_num; i++) { + if (IS_ERR(clks[i])) + pr_warn("i.MX clk %u: register failed with %ld\n", + i, PTR_ERR(clks[i])); + } + + ret = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); + + pm_runtime_put_sync(&pdev->dev); + + return ret; +} + +static int imx8dxl_acm_clk_remove(struct platform_device *pdev) +{ + struct imx8dxl_acm_priv *priv = dev_get_drvdata(&pdev->dev); + + pm_runtime_disable(&pdev->dev); + + clk_imx_acm_detach_pm_domains(&pdev->dev, &priv->dev_pm); + + return 0; +} + +static const struct of_device_id imx8dxl_acm_match[] = { + { .compatible = "nxp,imx8dxl-acm", }, + { /* sentinel */ } +}; + +static int __maybe_unused imx8dxl_acm_runtime_suspend(struct device *dev) +{ + struct imx8dxl_acm_priv *priv = dev_get_drvdata(dev); + + priv->regs[0] = readl_relaxed(priv->reg + 0x000000); + priv->regs[1] = readl_relaxed(priv->reg + 0x010000); + priv->regs[2] = readl_relaxed(priv->reg + 0x020000); + priv->regs[3] = readl_relaxed(priv->reg + 0x030000); + priv->regs[14] = readl_relaxed(priv->reg + 0x0E0000); + priv->regs[15] = readl_relaxed(priv->reg + 0x0F0000); + priv->regs[16] = readl_relaxed(priv->reg + 0x100000); + priv->regs[17] = readl_relaxed(priv->reg + 0x110000); + priv->regs[26] = readl_relaxed(priv->reg + 0x1A0000); + priv->regs[28] = readl_relaxed(priv->reg + 0x1C0000); + + return 0; +} + +static int __maybe_unused imx8dxl_acm_runtime_resume(struct device *dev) +{ + struct imx8dxl_acm_priv *priv = dev_get_drvdata(dev); + + writel_relaxed(priv->regs[0], priv->reg + 0x000000); + writel_relaxed(priv->regs[1], priv->reg + 0x010000); + writel_relaxed(priv->regs[2], priv->reg + 0x020000); + writel_relaxed(priv->regs[3], priv->reg + 0x030000); + writel_relaxed(priv->regs[14], priv->reg + 0x0E0000); + writel_relaxed(priv->regs[15], priv->reg + 0x0F0000); + writel_relaxed(priv->regs[16], priv->reg + 0x100000); + writel_relaxed(priv->regs[17], priv->reg + 0x110000); + writel_relaxed(priv->regs[26], priv->reg + 0x1A0000); + writel_relaxed(priv->regs[28], priv->reg + 0x1C0000); + + return 0; +} + +const struct dev_pm_ops imx8dxl_acm_pm_ops = { + SET_RUNTIME_PM_OPS(imx8dxl_acm_runtime_suspend, + imx8dxl_acm_runtime_resume, NULL) + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + +static struct platform_driver imx8dxl_acm_clk_driver = { + .driver = { + .name = "imx8dxl-acm", + .of_match_table = imx8dxl_acm_match, + .pm = &imx8dxl_acm_pm_ops, + .suppress_bind_attrs = true, + }, + .probe = imx8dxl_acm_clk_probe, + .remove = imx8dxl_acm_clk_remove, +}; + +static int __init imx8dxl_acm_init(void) +{ + return platform_driver_register(&imx8dxl_acm_clk_driver); +} +fs_initcall(imx8dxl_acm_init); diff --git a/drivers/clk/imx/clk-imx8dxl-rsrc.c b/drivers/clk/imx/clk-imx8dxl-rsrc.c new file mode 100644 index 00000000000000..8bd3c326cca56d --- /dev/null +++ b/drivers/clk/imx/clk-imx8dxl-rsrc.c @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020 NXP + */ + +#include + +#include "clk-scu.h" + +/* Keep sorted in the ascending order */ +static u32 imx8dxl_clk_scu_rsrc_table[] = { + IMX_SC_R_SPI_0, + IMX_SC_R_SPI_1, + IMX_SC_R_SPI_2, + IMX_SC_R_SPI_3, + IMX_SC_R_UART_0, + IMX_SC_R_UART_1, + IMX_SC_R_UART_2, + IMX_SC_R_UART_3, + IMX_SC_R_I2C_0, + IMX_SC_R_I2C_1, + IMX_SC_R_I2C_2, + IMX_SC_R_I2C_3, + IMX_SC_R_ADC_0, + IMX_SC_R_FTM_0, + IMX_SC_R_FTM_1, + IMX_SC_R_CAN_0, + IMX_SC_R_LCD_0, + IMX_SC_R_LCD_0_PWM_0, + IMX_SC_R_PWM_0, + IMX_SC_R_PWM_1, + IMX_SC_R_PWM_2, + IMX_SC_R_PWM_3, + IMX_SC_R_PWM_4, + IMX_SC_R_PWM_5, + IMX_SC_R_PWM_6, + IMX_SC_R_PWM_7, + IMX_SC_R_GPT_0, + IMX_SC_R_GPT_1, + IMX_SC_R_GPT_2, + IMX_SC_R_GPT_3, + IMX_SC_R_GPT_4, + IMX_SC_R_FSPI_0, + IMX_SC_R_FSPI_1, + IMX_SC_R_SDHC_0, + IMX_SC_R_SDHC_1, + IMX_SC_R_SDHC_2, + IMX_SC_R_ENET_0, + IMX_SC_R_ENET_1, + IMX_SC_R_MLB_0, + IMX_SC_R_USB_1, + IMX_SC_R_NAND, + IMX_SC_R_M4_0_I2C, + IMX_SC_R_ELCDIF_PLL, + IMX_SC_R_AUDIO_PLL_0, + IMX_SC_R_AUDIO_PLL_1, + IMX_SC_R_AUDIO_CLK_0, + IMX_SC_R_AUDIO_CLK_1, + IMX_SC_R_A35 +}; + +const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8dxl = { + .rsrc = imx8dxl_clk_scu_rsrc_table, + .num = ARRAY_SIZE(imx8dxl_clk_scu_rsrc_table), +}; diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 172589e94f60e1..7dee2f76cc37c7 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -12,7 +13,9 @@ #include #include #include +#include #include +#include #include "clk.h" @@ -67,6 +70,7 @@ static struct imx_pll14xx_clk imx8mm_dram_pll = { .type = PLL_1443X, .rate_table = imx8mm_drampll_tbl, .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl), + .flags = CLK_GET_RATE_NOCACHE, }; static struct imx_pll14xx_clk imx8mm_arm_pll = { @@ -109,6 +113,8 @@ static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; static const char *imx8mm_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; +static const char *imx8mm_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", }; + static const char *imx8mm_m4_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", "sys_pll1_266m", "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", }; @@ -357,13 +363,31 @@ static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m", static struct clk *clks[IMX8MM_CLK_END]; static struct clk_onecell_data clk_data; -static struct clk ** const uart_clks[] = { - &clks[IMX8MM_CLK_UART1_ROOT], - &clks[IMX8MM_CLK_UART2_ROOT], - &clks[IMX8MM_CLK_UART3_ROOT], - &clks[IMX8MM_CLK_UART4_ROOT], - NULL -}; +static int __init imx_clk_init_on(struct device_node *np, + struct clk * const clks[]) +{ + u32 *array; + int i, ret, elems; + + elems = of_property_count_u32_elems(np, "init-on-array"); + if (elems < 0) + return elems; + array = kcalloc(elems, sizeof(elems), GFP_KERNEL); + if (IS_ERR_OR_NULL(array)) + return PTR_ERR(array); + + ret = of_property_read_u32_array(np, "init-on-array", array, elems); + if (ret) + return ret; + + for (i = 0; i < elems; i++) { + ret = clk_prepare_enable(clks[array[i]]); + if (ret) + pr_err("clk_prepare_enable failed %d\n", array[i]); + } + + return 0; +} static int imx8mm_clocks_probe(struct platform_device *pdev) { @@ -372,6 +396,8 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) void __iomem *base; int ret; + check_m4_enabled(); + clks[IMX8MM_CLK_DUMMY] = imx_clk_fixed("dummy", 0); clks[IMX8MM_CLK_24M] = of_clk_get_by_name(np, "osc_24m"); clks[IMX8MM_CLK_32K] = of_clk_get_by_name(np, "osc_32k"); @@ -474,10 +500,13 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) clks[IMX8MM_CLK_GPU3D_DIV] = imx_clk_divider2("gpu3d_div", "gpu3d_cg", base + 0x8180, 0, 3); clks[IMX8MM_CLK_GPU2D_DIV] = imx_clk_divider2("gpu2d_div", "gpu2d_cg", base + 0x8200, 0, 3); + /* CORE SEL */ + clks[IMX8MM_CLK_A53_CORE] = imx_clk_mux2_flags("arm_a53_core", base + 0x9880, 24, 1, imx8mm_a53_core_sels, ARRAY_SIZE(imx8mm_a53_core_sels), CLK_IS_CRITICAL); + /* BUS */ clks[IMX8MM_CLK_MAIN_AXI] = imx8m_clk_composite_critical("main_axi", imx8mm_main_axi_sels, base + 0x8800); clks[IMX8MM_CLK_ENET_AXI] = imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels, base + 0x8880); - clks[IMX8MM_CLK_NAND_USDHC_BUS] = imx8m_clk_composite_critical("nand_usdhc_bus", imx8mm_nand_usdhc_sels, base + 0x8900); + clks[IMX8MM_CLK_NAND_USDHC_BUS] = imx8m_clk_composite("nand_usdhc_bus", imx8mm_nand_usdhc_sels, base + 0x8900); clks[IMX8MM_CLK_VPU_BUS] = imx8m_clk_composite("vpu_bus", imx8mm_vpu_bus_sels, base + 0x8980); clks[IMX8MM_CLK_DISP_AXI] = imx8m_clk_composite("disp_axi", imx8mm_disp_axi_sels, base + 0x8a00); clks[IMX8MM_CLK_DISP_APB] = imx8m_clk_composite("disp_apb", imx8mm_disp_apb_sels, base + 0x8a80); @@ -634,11 +663,14 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) clks[IMX8MM_CLK_DRAM_ALT_ROOT] = imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4); clks[IMX8MM_CLK_DRAM_CORE] = imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mm_dram_core_sels, ARRAY_SIZE(imx8mm_dram_core_sels), CLK_IS_CRITICAL); - clks[IMX8MM_CLK_ARM] = imx_clk_cpu("arm", "arm_a53_div", - clks[IMX8MM_CLK_A53_DIV], - clks[IMX8MM_CLK_A53_SRC], + clk_set_parent(clks[IMX8MM_CLK_A53_SRC], clks[IMX8MM_SYS_PLL1_800M]); + clk_set_parent(clks[IMX8MM_CLK_A53_CORE], clks[IMX8MM_ARM_PLL_OUT]); + + clks[IMX8MM_CLK_ARM] = imx_clk_cpu("arm", "arm_a53_core", + clks[IMX8MM_CLK_A53_CORE], + clks[IMX8MM_CLK_A53_CORE], clks[IMX8MM_ARM_PLL_OUT], - clks[IMX8MM_SYS_PLL1_800M]); + clks[IMX8MM_CLK_A53_DIV]); imx_check_clocks(clks, ARRAY_SIZE(clks)); @@ -650,7 +682,16 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) goto unregister_clks; } - imx_register_uart_clocks(uart_clks); + imx_clk_init_on(np, clks); + + clk_set_parent(clks[IMX8MM_CLK_PCIE1_CTRL], clks[IMX8MM_SYS_PLL2_250M]); + clk_set_parent(clks[IMX8MM_CLK_PCIE1_PHY], clks[IMX8MM_SYS_PLL2_100M]); + + clk_set_parent(clks[IMX8MM_CLK_CSI1_CORE], clks[IMX8MM_SYS_PLL2_1000M]); + clk_set_parent(clks[IMX8MM_CLK_CSI1_PHY_REF], clks[IMX8MM_SYS_PLL2_1000M]); + clk_set_parent(clks[IMX8MM_CLK_CSI1_ESC], clks[IMX8MM_SYS_PLL1_800M]); + + imx_register_uart_clocks(); return 0; @@ -674,3 +715,81 @@ static struct platform_driver imx8mm_clk_driver = { }, }; module_platform_driver(imx8mm_clk_driver); + +/* + * Debugfs interface for audio PLL K divider change dynamically. + * Monitor control for the Audio PLL K-Divider + */ +#ifdef CONFIG_DEBUG_FS + +#define KDIV_MASK GENMASK(15, 0) +#define MDIV_SHIFT 12 +#define MDIV_MASK GENMASK(21, 12) +#define PDIV_SHIFT 4 +#define PDIV_MASK GENMASK(9, 4) +#define SDIV_SHIFT 0 +#define SDIV_MASK GENMASK(2, 0) + +static int pll_delta_k_set(void *data, u64 val) +{ + struct clk_hw *hw; + short int delta_k; + + hw = __clk_get_hw(data); + delta_k = (short int) (val & KDIV_MASK); + + clk_set_delta_k(hw, val); + + pr_debug("the delta k is %d\n", delta_k); + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(delta_k_fops, NULL, pll_delta_k_set, "%lld\n"); + +static int pll_setting_show(struct seq_file *s, void *data) +{ + struct clk *pll_clk; + struct clk_hw *hw; + u32 pll_div_ctrl0, pll_div_ctrl1; + u32 mdiv, pdiv, sdiv, kdiv; + + pll_clk = s->private; + + hw = __clk_get_hw(pll_clk); + + clk_get_pll_setting(hw, &pll_div_ctrl0, &pll_div_ctrl1); + mdiv = (pll_div_ctrl0 & MDIV_MASK) >> MDIV_SHIFT; + pdiv = (pll_div_ctrl0 & PDIV_MASK) >> PDIV_SHIFT; + sdiv = (pll_div_ctrl0 & SDIV_MASK) >> SDIV_SHIFT; + kdiv = (pll_div_ctrl1 & KDIV_MASK); + + seq_printf(s, "Mdiv: 0x%x; Pdiv: 0x%x; Sdiv: 0x%x; Kdiv: 0x%x\n", + mdiv, pdiv, sdiv, kdiv); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(pll_setting); + +static int __init pll_debug_init(void) +{ + struct dentry *root, *audio_pll1, *audio_pll2; + + if (of_machine_is_compatible("fsl,imx8mm")) { + /* create a root dir for audio pll monitor */ + root = debugfs_create_dir("audio_pll_monitor", NULL); + audio_pll1 = debugfs_create_dir("audio_pll1", root); + audio_pll2 = debugfs_create_dir("audio_pll2", root); + + debugfs_create_file_unsafe("delta_k", 0444, audio_pll1, + clks[IMX8MM_AUDIO_PLL1], &delta_k_fops); + debugfs_create_file("pll_parameter", 0x444, audio_pll1, + clks[IMX8MM_AUDIO_PLL1], &pll_setting_fops); + debugfs_create_file_unsafe("delta_k", 0444, audio_pll2, + clks[IMX8MM_AUDIO_PLL2], &delta_k_fops); + debugfs_create_file("pll_parameter", 0x444, audio_pll2, + clks[IMX8MM_AUDIO_PLL2], &pll_setting_fops); + } + + return 0; +} +late_initcall(pll_debug_init); +#endif /* CONFIG_DEBUG_FS */ diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 58b5acee383069..681ad342a7590f 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -12,7 +12,9 @@ #include #include #include +#include #include +#include #include "clk.h" @@ -82,6 +84,7 @@ static struct imx_pll14xx_clk imx8mn_dram_pll = { .type = PLL_1443X, .rate_table = imx8mn_drampll_tbl, .rate_count = ARRAY_SIZE(imx8mn_drampll_tbl), + .flags = CLK_GET_RATE_NOCACHE, }; static struct imx_pll14xx_clk imx8mn_arm_pll = { @@ -124,6 +127,8 @@ static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pl "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; +static const char *imx8mn_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", }; + static const char * const imx8mn_gpu_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; @@ -368,13 +373,31 @@ static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sy static struct clk *clks[IMX8MN_CLK_END]; static struct clk_onecell_data clk_data; -static struct clk ** const uart_clks[] = { - &clks[IMX8MN_CLK_UART1_ROOT], - &clks[IMX8MN_CLK_UART2_ROOT], - &clks[IMX8MN_CLK_UART3_ROOT], - &clks[IMX8MN_CLK_UART4_ROOT], - NULL -}; +static int __init imx_clk_init_on(struct device_node *np, + struct clk * const clks[]) +{ + u32 *array; + int i, ret, elems; + + elems = of_property_count_u32_elems(np, "init-on-array"); + if (elems < 0) + return elems; + array = kcalloc(elems, sizeof(elems), GFP_KERNEL); + if (IS_ERR_OR_NULL(array)) + return PTR_ERR(array); + + ret = of_property_read_u32_array(np, "init-on-array", array, elems); + if (ret) + return ret; + + for (i = 0; i < elems; i++) { + ret = clk_prepare_enable(clks[array[i]]); + if (ret) + pr_err("clk_prepare_enable failed %d\n", array[i]); + } + + return 0; +} static int imx8mn_clocks_probe(struct platform_device *pdev) { @@ -383,6 +406,8 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) void __iomem *base; int ret; + check_m4_enabled(); + clks[IMX8MN_CLK_DUMMY] = imx_clk_fixed("dummy", 0); clks[IMX8MN_CLK_24M] = of_clk_get_by_name(np, "osc_24m"); clks[IMX8MN_CLK_32K] = of_clk_get_by_name(np, "osc_32k"); @@ -484,6 +509,9 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) clks[IMX8MN_CLK_GPU_CORE_DIV] = imx_clk_divider2("gpu_core_div", "gpu_core_cg", base + 0x8180, 0, 3); clks[IMX8MN_CLK_GPU_SHADER_DIV] = imx_clk_divider2("gpu_shader_div", "gpu_shader_cg", base + 0x8200, 0, 3); + /* CORE SEL */ + clks[IMX8MN_CLK_A53_CORE] = imx_clk_mux2_flags("arm_a53_core", base + 0x9880, 24, 1, imx8mn_a53_core_sels, ARRAY_SIZE(imx8mn_a53_core_sels), CLK_IS_CRITICAL); + /* BUS */ clks[IMX8MN_CLK_MAIN_AXI] = imx8m_clk_composite_critical("main_axi", imx8mn_main_axi_sels, base + 0x8800); clks[IMX8MN_CLK_ENET_AXI] = imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels, base + 0x8880); @@ -578,11 +606,12 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) clks[IMX8MN_CLK_SAI5_IPG] = imx_clk_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5); clks[IMX8MN_CLK_SAI6_ROOT] = imx_clk_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6); clks[IMX8MN_CLK_SAI6_IPG] = imx_clk_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6); + clks[IMX8MN_CLK_SNVS_ROOT] = imx_clk_gate4("snvs_root_clk", "ipg_root", base + 0x4470, 0); clks[IMX8MN_CLK_UART1_ROOT] = imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0); clks[IMX8MN_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0); clks[IMX8MN_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0); clks[IMX8MN_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0); - clks[IMX8MN_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_core_ref", base + 0x44d0, 0); + clks[IMX8MN_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0); clks[IMX8MN_CLK_GPU_CORE_ROOT] = imx_clk_gate4("gpu_core_root_clk", "gpu_core_div", base + 0x44f0, 0); clks[IMX8MN_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0); clks[IMX8MN_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0); @@ -606,11 +635,14 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) clks[IMX8MN_CLK_DRAM_ALT_ROOT] = imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4); - clks[IMX8MN_CLK_ARM] = imx_clk_cpu("arm", "arm_a53_div", - clks[IMX8MN_CLK_A53_DIV], - clks[IMX8MN_CLK_A53_SRC], + clk_set_parent(clks[IMX8MN_CLK_A53_SRC], clks[IMX8MN_SYS_PLL1_800M]); + clk_set_parent(clks[IMX8MN_CLK_A53_CORE], clks[IMX8MN_ARM_PLL_OUT]); + + clks[IMX8MN_CLK_ARM] = imx_clk_cpu("arm", "arm_a53_core", + clks[IMX8MN_CLK_A53_CORE], + clks[IMX8MN_CLK_A53_CORE], clks[IMX8MN_ARM_PLL_OUT], - clks[IMX8MN_SYS_PLL1_800M]); + clks[IMX8MN_CLK_A53_DIV]); imx_check_clocks(clks, ARRAY_SIZE(clks)); @@ -622,7 +654,13 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) goto unregister_clks; } - imx_register_uart_clocks(uart_clks); + imx_clk_init_on(np, clks); + + clk_set_parent(clks[IMX8MN_CLK_AUDIO_AHB], clks[IMX8MN_SYS_PLL1_800M]); + clk_set_rate(clks[IMX8MN_CLK_AUDIO_AHB], 400000000); + clk_set_rate(clks[IMX8MN_CLK_IPG_AUDIO_ROOT], 400000000); + + imx_register_uart_clocks(); return 0; diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c new file mode 100644 index 00000000000000..b640d2aad9a710 --- /dev/null +++ b/drivers/clk/imx/clk-imx8mp.c @@ -0,0 +1,889 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +static u32 share_count_nand; +static u32 share_count_media; + +#define PLL_1416X_RATE(_rate, _m, _p, _s) \ + { \ + .rate = (_rate), \ + .mdiv = (_m), \ + .pdiv = (_p), \ + .sdiv = (_s), \ + } + +#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \ + { \ + .rate = (_rate), \ + .mdiv = (_m), \ + .pdiv = (_p), \ + .sdiv = (_s), \ + .kdiv = (_k), \ + } + +static const struct imx_pll14xx_rate_table imx8mp_pll1416x_tbl[] = { + PLL_1416X_RATE(1800000000U, 225, 3, 0), + PLL_1416X_RATE(1600000000U, 200, 3, 0), + PLL_1416X_RATE(1200000000U, 300, 3, 1), + PLL_1416X_RATE(1000000000U, 250, 3, 1), + PLL_1416X_RATE(800000000U, 200, 3, 1), + PLL_1416X_RATE(750000000U, 250, 2, 2), + PLL_1416X_RATE(700000000U, 350, 3, 2), + PLL_1416X_RATE(600000000U, 300, 3, 2), +}; + +static const struct imx_pll14xx_rate_table imx8mp_audiopll_tbl[] = { + PLL_1443X_RATE(393216000U, 262, 2, 3, 9437), + PLL_1443X_RATE(361267200U, 361, 3, 3, 17511), +}; + +static const struct imx_pll14xx_rate_table imx8mp_videopll_tbl[] = { + PLL_1443X_RATE(2079000000U, 173, 1, 1, 16384), + PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384), + PLL_1443X_RATE(650000000U, 325, 3, 2, 0), + PLL_1443X_RATE(594000000U, 198, 2, 2, 0), + PLL_1443X_RATE(519750000U, 173, 2, 2, 16384), +}; + +static const struct imx_pll14xx_rate_table imx8mp_drampll_tbl[] = { + PLL_1443X_RATE(650000000U, 325, 3, 2, 0), +}; + +static struct imx_pll14xx_clk imx8mp_audio_pll = { + .type = PLL_1443X, + .rate_table = imx8mp_audiopll_tbl, + .rate_count = ARRAY_SIZE(imx8mp_audiopll_tbl), +}; + +static struct imx_pll14xx_clk imx8mp_video_pll = { + .type = PLL_1443X, + .rate_table = imx8mp_videopll_tbl, + .rate_count = ARRAY_SIZE(imx8mp_videopll_tbl), +}; + +static struct imx_pll14xx_clk imx8mp_dram_pll = { + .type = PLL_1443X, + .rate_table = imx8mp_drampll_tbl, +}; + +static struct imx_pll14xx_clk imx8mp_arm_pll = { + .type = PLL_1416X, + .rate_table = imx8mp_pll1416x_tbl, + .rate_count = ARRAY_SIZE(imx8mp_pll1416x_tbl), +}; + +static struct imx_pll14xx_clk imx8mp_gpu_pll = { + .type = PLL_1416X, + .rate_table = imx8mp_pll1416x_tbl, +}; + +static struct imx_pll14xx_clk imx8mp_vpu_pll = { + .type = PLL_1416X, + .rate_table = imx8mp_pll1416x_tbl, +}; + +static struct imx_pll14xx_clk imx8mp_sys_pll = { + .type = PLL_1416X, + .rate_table = imx8mp_pll1416x_tbl, +}; + +static const char *pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; +static const char *audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; +static const char *audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", }; +static const char *video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", }; +static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; +static const char *gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; +static const char *vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", }; +static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; +static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", }; +static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", }; +static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; + +/* CCM ROOT */ +static const char *imx8mp_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m", + "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", + "sys_pll3_out", }; + +static const char *imx8mp_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", }; + +static const char *imx8mp_m7_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", "vpu_pll_out", + "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", }; + +static const char *imx8mp_ml_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", }; + +static const char *imx8mp_gpu3d_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", }; + +static const char *imx8mp_gpu3d_shader_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", }; + +static const char *imx8mp_gpu2d_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", }; + +static const char *imx8mp_audio_axi_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", }; + +static const char *imx8mp_hsio_axi_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_100m", + "sys_pll2_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", }; + +static const char *imx8mp_media_isp_sels[] = {"osc_24m", "sys_pll2_1000m", "sys_pll1_800m", + "sys_pll3_out", "sys_pll1_400m", "audio_pll2_out", + "clk_ext1", "sys_pll2_500m", }; + +static const char *imx8mp_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m", + "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "sys_pll1_100m",}; + +static const char *imx8mp_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", + "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", + "video_pll1_out", "sys_pll3_out", }; + +static const char *imx8mp_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", + "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll1_out", }; + +static const char *imx8mp_vpu_bus_sels[] = {"osc_24m", "sys_pll1_800m", "vpu_pll_out", + "audio_pll2_out", "sys_pll3_out", "sys_pll2_1000m", + "sys_pll2_200m", "sys_pll1_100m", }; + +static const char *imx8mp_media_axi_sels[] = {"osc_24m", "sys_pll2_1000m", "sys_pll1_800m", + "sys_pll3_out", "sys_pll1_40m", "audio_pll2_out", + "clk_ext1", "sys_pll2_500m", }; + +static const char *imx8mp_media_apb_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll1_800m", + "sys_pll3_out", "sys_pll1_40m", "audio_pll2_out", + "clk_ext1", "sys_pll1_133m", }; + +static const char *imx8mp_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", + "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mp_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", + "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mp_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mp_noc_io_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mp_ml_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", + "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mp_ml_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", + "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mp_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", + "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", + "audio_pll1_out", "video_pll1_out", }; + +static const char *imx8mp_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", + "sys_pll2_1000m", "sys_pll2_166m", "sys_pll3_out", + "audio_pll1_out", "video_pll1_out", }; + +static const char *imx8mp_mipi_dsi_esc_rx_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m", + "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", + "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mp_media_disp2_pix_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out", + "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m", + "sys_pll3_out", "clk_ext4", }; + +static const char *imx8mp_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m", + "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out", + "audio_pll1_out", "sys_pll1_266m", }; + +static const char *imx8mp_dram_apb_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; + +static const char *imx8mp_vpu_g1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", + "sys_pll2_1000m", "sys_pll1_100m", "sys_pll2_125m", + "sys_pll3_out", "audio_pll1_out", }; + +static const char *imx8mp_vpu_g2_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", + "sys_pll2_1000m", "sys_pll1_100m", "sys_pll2_125m", + "sys_pll3_out", "audio_pll1_out", }; + +static const char *imx8mp_can1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; + +static const char *imx8mp_can2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; + +static const char *imx8mp_pcie_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll2_500m", + "clk_ext1", "clk_ext2", "clk_ext3", + "clk_ext4", "sys_pll1_400m", }; + +static const char *imx8mp_pcie_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m", + "sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m", + "sys_pll1_160m", "sys_pll1_200m", }; + +static const char *imx8mp_i2c5_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; + +static const char *imx8mp_i2c6_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; + +static const char *imx8mp_sai1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", + "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "clk_ext1", "clk_ext2", }; + +static const char *imx8mp_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", + "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "clk_ext2", "clk_ext3", }; + +static const char *imx8mp_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", + "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "clk_ext3", "clk_ext4", }; + +static const char *imx8mp_sai4_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", + "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "clk_ext1", "clk_ext2", }; + +static const char *imx8mp_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", + "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "clk_ext2", "clk_ext3", }; + +static const char *imx8mp_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", + "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "clk_ext3", "clk_ext4", }; + +static const char *imx8mp_enet_qos_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", + "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", + "video_pll1_out", "clk_ext4", }; + +static const char *imx8mp_enet_qos_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", + "clk_ext1", "clk_ext2", "clk_ext3", + "clk_ext4", "video_pll1_out", }; + +static const char *imx8mp_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", + "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", + "video_pll1_out", "clk_ext4", }; + +static const char *imx8mp_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", + "clk_ext1", "clk_ext2", "clk_ext3", + "clk_ext4", "video_pll1_out", }; + +static const char *imx8mp_enet_phy_ref_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m", + "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mp_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out", + "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out", + "sys_pll2_250m", "video_pll1_out", }; + +static const char *imx8mp_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m", + "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", + "sys_pll3_out", "sys_pll1_100m", }; + +static const char *imx8mp_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", + "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", + "audio_pll2_out", "sys_pll1_100m", }; + +static const char *imx8mp_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", + "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", + "audio_pll2_out", "sys_pll1_100m", }; + +static const char *imx8mp_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; + +static const char *imx8mp_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; + +static const char *imx8mp_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; + +static const char *imx8mp_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; + +static const char *imx8mp_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext4", "audio_pll2_out", }; + +static const char *imx8mp_uart2_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mp_uart3_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext4", "audio_pll2_out", }; + +static const char *imx8mp_uart4_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mp_usb_core_ref_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", + "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mp_usb_phy_ref_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", + "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mp_gic_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll2_100m", "sys_pll1_800m", + "sys_pll2_500m", "clk_ext4", "audio_pll2_out" }; + +static const char *imx8mp_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; + +static const char *imx8mp_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; + +static const char *imx8mp_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext1", + "sys_pll1_80m", "video_pll1_out", }; + +static const char *imx8mp_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext1", + "sys_pll1_80m", "video_pll1_out", }; + +static const char *imx8mp_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext2", + "sys_pll1_80m", "video_pll1_out", }; + +static const char *imx8mp_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext2", + "sys_pll1_80m", "video_pll1_out", }; + +static const char *imx8mp_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", + "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "audio_pll1_out", "clk_ext1" }; + +static const char *imx8mp_gpt2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", + "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "audio_pll1_out", "clk_ext2" }; + +static const char *imx8mp_gpt3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", + "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "audio_pll1_out", "clk_ext3" }; + +static const char *imx8mp_gpt4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", + "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "audio_pll1_out", "clk_ext1" }; + +static const char *imx8mp_gpt5_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", + "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "audio_pll1_out", "clk_ext2" }; + +static const char *imx8mp_gpt6_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", + "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "audio_pll1_out", "clk_ext3" }; + +static const char *imx8mp_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", + "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out", + "sys_pll1_80m", "sys_pll2_166m" }; + +static const char *imx8mp_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "vpu_pll_out", + "sys_pll3_out", "sys_pll2_200m", "sys_pll1_266m", + "sys_pll2_500m", "sys_pll1_100m" }; + +static const char *imx8mp_ipp_do_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_133m", + "sys_pll1_200m", "audio_pll2_out", "sys_pll2_500m", + "vpu_pll_out", "sys_pll1_80m" }; + +static const char *imx8mp_ipp_do_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", + "sys_pll1_166m", "sys_pll3_out", "audio_pll1_out", + "video_pll1_out", "osc_32k" }; + +static const char *imx8mp_hdmi_fdcc_tst_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", + "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", + "audio_pll2_out", "video_pll1_out", }; + +static const char *imx8mp_hdmi_24m_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; + +static const char *imx8mp_hdmi_ref_266m_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll3_out", + "sys_pll2_333m", "sys_pll1_266m", "sys_pll2_200m", + "audio_pll1_out", "video_pll1_out", }; + +static const char *imx8mp_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", + "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", + "audio_pll2_out", "sys_pll1_100m", }; + +static const char *imx8mp_media_cam1_pix_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", + "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", + "audio_pll2_out", "video_pll1_out", }; + +static const char *imx8mp_media_mipi_phy1_ref_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", + "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2", + "audio_pll2_out", "video_pll1_out", }; + +static const char *imx8mp_media_disp1_pix_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out", + "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m", + "sys_pll3_out", "clk_ext4", }; + +static const char *imx8mp_media_cam2_pix_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", + "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", + "audio_pll2_out", "video_pll1_out", }; + +static const char *imx8mp_media_ldb_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", + "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2", + "audio_pll2_out", "video_pll1_out", }; + +static const char *imx8mp_memrepair_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m", + "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", + "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mp_pcie2_ctrl_sels[] = {"osc_24m", "sys_pll2_250m", "sys_pll2_200m", + "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_500m", + "sys_pll2_333m", "sys_pll3_out", }; + +static const char *imx8mp_pcie2_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll2_500m", + "clk_ext1", "clk_ext2", "clk_ext3", + "clk_ext4", "sys_pll1_400m", }; + +static const char *imx8mp_media_mipi_test_byte_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m", + "sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m", + "sys_pll1_160m", "sys_pll1_200m", }; + +static const char *imx8mp_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; + +static const char *imx8mp_pdm_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", + "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", + "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mp_vpu_vc8000e_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", + "sys_pll2_1000m", "audio_pll2_out", "sys_pll2_125m", + "sys_pll3_out", "audio_pll1_out", }; + +static const char *imx8mp_sai7_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", + "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "clk_ext3", "clk_ext4", }; + +static const char *imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }; + +static struct clk *clks[IMX8MP_CLK_END]; +static struct clk_onecell_data clk_data; + +static int __init imx_clk_init_on(struct device_node *np, + struct clk * const clks[]) +{ + u32 *array; + int i, ret, elems; + + elems = of_property_count_u32_elems(np, "init-on-array"); + if (elems < 0) + return elems; + array = kcalloc(elems, sizeof(elems), GFP_KERNEL); + if (IS_ERR_OR_NULL(array)) + return PTR_ERR(array); + + ret = of_property_read_u32_array(np, "init-on-array", array, elems); + if (ret) + return ret; + + for (i = 0; i < elems; i++) { + ret = clk_prepare_enable(clks[array[i]]); + if (ret) + pr_err("clk_prepare_enable failed %d\n", array[i]); + } + + return 0; +} + +static int imx8mp_clocks_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct resource *res; + void __iomem *base; + int ret; + + check_m4_enabled(); + + clks[IMX8MP_CLK_DUMMY] = imx_clk_fixed("dummy", 0); + clks[IMX8MP_CLK_24M] = of_clk_get_by_name(np, "osc_24m"); + clks[IMX8MP_CLK_32K] = of_clk_get_by_name(np, "osc_32k"); + clks[IMX8MP_CLK_EXT1] = of_clk_get_by_name(np, "clk_ext1"); + clks[IMX8MP_CLK_EXT2] = of_clk_get_by_name(np, "clk_ext2"); + clks[IMX8MP_CLK_EXT3] = of_clk_get_by_name(np, "clk_ext3"); + clks[IMX8MP_CLK_EXT4] = of_clk_get_by_name(np, "clk_ext4"); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop"); + base = of_iomap(np, 0); + if (WARN_ON(!base)) + return -ENOMEM; + + clks[IMX8MP_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MP_AUDIO_PLL2_REF_SEL] = imx_clk_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MP_VIDEO_PLL1_REF_SEL] = imx_clk_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MP_DRAM_PLL_REF_SEL] = imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MP_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MP_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MP_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MP_SYS_PLL1_REF_SEL] = imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MP_SYS_PLL2_REF_SEL] = imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MP_SYS_PLL3_REF_SEL] = imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + + clks[IMX8MP_AUDIO_PLL1] = imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx8mp_audio_pll); + clks[IMX8MP_AUDIO_PLL2] = imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx8mp_audio_pll); + clks[IMX8MP_VIDEO_PLL1] = imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx8mp_video_pll); + clks[IMX8MP_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx8mp_dram_pll); + clks[IMX8MP_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx8mp_gpu_pll); + clks[IMX8MP_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx8mp_vpu_pll); + clks[IMX8MP_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx8mp_arm_pll); + clks[IMX8MP_SYS_PLL1] = imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94, &imx8mp_sys_pll); + clks[IMX8MP_SYS_PLL2] = imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104, &imx8mp_sys_pll); + clks[IMX8MP_SYS_PLL3] = imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mp_sys_pll); + + /* PLL bypass out */ + clks[IMX8MP_AUDIO_PLL1_BYPASS] = imx_clk_mux_flags("audio_pll1_bypass", base, 4, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX8MP_AUDIO_PLL2_BYPASS] = imx_clk_mux_flags("audio_pll2_bypass", base + 0x14, 4, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX8MP_VIDEO_PLL1_BYPASS] = imx_clk_mux_flags("video_pll1_bypass", base + 0x28, 4, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX8MP_DRAM_PLL_BYPASS] = imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX8MP_GPU_PLL_BYPASS] = imx_clk_mux_flags("gpu_pll_bypass", base + 0x64, 4, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX8MP_VPU_PLL_BYPASS] = imx_clk_mux_flags("vpu_pll_bypass", base + 0x74, 4, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX8MP_ARM_PLL_BYPASS] = imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX8MP_SYS_PLL1_BYPASS] = imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX8MP_SYS_PLL2_BYPASS] = imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX8MP_SYS_PLL3_BYPASS] = imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT); + + /* unbypass all the plls */ + clk_set_parent(clks[IMX8MP_AUDIO_PLL1_BYPASS], clks[IMX8MP_AUDIO_PLL1]); + clk_set_parent(clks[IMX8MP_AUDIO_PLL2_BYPASS], clks[IMX8MP_AUDIO_PLL2]); + clk_set_parent(clks[IMX8MP_VIDEO_PLL1_BYPASS], clks[IMX8MP_VIDEO_PLL1]); + clk_set_parent(clks[IMX8MP_DRAM_PLL_BYPASS], clks[IMX8MP_DRAM_PLL]); + clk_set_parent(clks[IMX8MP_GPU_PLL_BYPASS], clks[IMX8MP_GPU_PLL]); + clk_set_parent(clks[IMX8MP_VPU_PLL_BYPASS], clks[IMX8MP_VPU_PLL]); + clk_set_parent(clks[IMX8MP_ARM_PLL_BYPASS], clks[IMX8MP_ARM_PLL]); + clk_set_parent(clks[IMX8MP_SYS_PLL1_BYPASS], clks[IMX8MP_SYS_PLL1]); + clk_set_parent(clks[IMX8MP_SYS_PLL2_BYPASS], clks[IMX8MP_SYS_PLL2]); + clk_set_parent(clks[IMX8MP_SYS_PLL3_BYPASS], clks[IMX8MP_SYS_PLL3]); + + /* PLL out gate */ + clks[IMX8MP_AUDIO_PLL1_OUT] = imx_clk_gate("audio_pll1_out", "audio_pll1_bypass", base, 13); + clks[IMX8MP_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13); + clks[IMX8MP_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13); + clks[IMX8MP_DRAM_PLL_OUT] = imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13); + clks[IMX8MP_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11); + clks[IMX8MP_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11); + clks[IMX8MP_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11); + clks[IMX8MP_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11); + clks[IMX8MP_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11); + clks[IMX8MP_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11); + + /* SYS PLL fixed output */ + clks[IMX8MP_SYS_PLL1_40M] = imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); + clks[IMX8MP_SYS_PLL1_80M] = imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10); + clks[IMX8MP_SYS_PLL1_100M] = imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8); + clks[IMX8MP_SYS_PLL1_133M] = imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6); + clks[IMX8MP_SYS_PLL1_160M] = imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5); + clks[IMX8MP_SYS_PLL1_200M] = imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4); + clks[IMX8MP_SYS_PLL1_266M] = imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3); + clks[IMX8MP_SYS_PLL1_400M] = imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2); + clks[IMX8MP_SYS_PLL1_800M] = imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1); + + clks[IMX8MP_SYS_PLL2_50M] = imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); + clks[IMX8MP_SYS_PLL2_100M] = imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); + clks[IMX8MP_SYS_PLL2_125M] = imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); + clks[IMX8MP_SYS_PLL2_166M] = imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6); + clks[IMX8MP_SYS_PLL2_200M] = imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5); + clks[IMX8MP_SYS_PLL2_250M] = imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4); + clks[IMX8MP_SYS_PLL2_333M] = imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); + clks[IMX8MP_SYS_PLL2_500M] = imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); + clks[IMX8MP_SYS_PLL2_1000M] = imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); + + np = dev->of_node; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, res); + if (WARN_ON(IS_ERR(base))) + return PTR_ERR(base); + + /* Core Slice */ + clks[IMX8MP_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels)); + clks[IMX8MP_CLK_M7_SRC] = imx_clk_mux2("arm_m7_src", base + 0x8080, 24, 3, imx8mp_m7_sels, ARRAY_SIZE(imx8mp_m7_sels)); + clks[IMX8MP_CLK_ML_SRC] = imx_clk_mux2("ml_src", base + 0x8100, 24, 3, imx8mp_ml_sels, ARRAY_SIZE(imx8mp_ml_sels)); + clks[IMX8MP_CLK_GPU3D_CORE_SRC] = imx_clk_mux2("gpu3d_core_src", base + 0x8180, 24, 3, imx8mp_gpu3d_core_sels, ARRAY_SIZE(imx8mp_gpu3d_core_sels)); + clks[IMX8MP_CLK_GPU3D_SHADER_SRC] = imx_clk_mux2("gpu3d_shader_src", base + 0x8200, 24, 3, imx8mp_gpu3d_shader_sels, ARRAY_SIZE(imx8mp_gpu3d_shader_sels)); + clks[IMX8MP_CLK_GPU2D_SRC] = imx_clk_mux2("gpu2d_src", base + 0x8280, 24, 3, imx8mp_gpu2d_sels, ARRAY_SIZE(imx8mp_gpu2d_sels)); + clks[IMX8MP_CLK_AUDIO_AXI_SRC] = imx_clk_mux2("audio_axi_src", base + 0x8300, 24, 3, imx8mp_audio_axi_sels, ARRAY_SIZE(imx8mp_audio_axi_sels)); + clks[IMX8MP_CLK_HSIO_AXI_SRC] = imx_clk_mux2("hsio_axi_src", base + 0x8380, 24, 3, imx8mp_hsio_axi_sels, ARRAY_SIZE(imx8mp_hsio_axi_sels)); + clks[IMX8MP_CLK_MEDIA_ISP_SRC] = imx_clk_mux2("media_isp_src", base + 0x8400, 24, 3, imx8mp_media_isp_sels, ARRAY_SIZE(imx8mp_media_isp_sels)); + clks[IMX8MP_CLK_A53_CG] = imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28); + clks[IMX8MP_CLK_M4_CG] = imx_clk_gate3("arm_m7_cg", "arm_m7_src", base + 0x8080, 28); + clks[IMX8MP_CLK_ML_CG] = imx_clk_gate3("ml_cg", "ml_src", base + 0x8100, 28); + clks[IMX8MP_CLK_GPU3D_CORE_CG] = imx_clk_gate3("gpu3d_core_cg", "gpu3d_core_src", base + 0x8180, 28); + clks[IMX8MP_CLK_GPU3D_SHADER_CG] = imx_clk_gate3("gpu3d_shader_cg", "gpu3d_shader_src", base + 0x8200, 28); + clks[IMX8MP_CLK_GPU2D_CG] = imx_clk_gate3("gpu2d_cg", "gpu2d_src", base + 0x8280, 28); + clks[IMX8MP_CLK_AUDIO_AXI_CG] = imx_clk_gate3("audio_axi_cg", "audio_axi_src", base + 0x8300, 28); + clks[IMX8MP_CLK_HSIO_AXI_CG] = imx_clk_gate3("hsio_axi_cg", "hsio_axi_src", base + 0x8380, 28); + clks[IMX8MP_CLK_MEDIA_ISP_CG] = imx_clk_gate3("media_isp_cg", "media_isp_src", base + 0x8400, 28); + clks[IMX8MP_CLK_A53_DIV] = imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3); + clks[IMX8MP_CLK_M7_DIV] = imx_clk_divider2("arm_m7_div", "arm_m7_cg", base + 0x8080, 0, 3); + clks[IMX8MP_CLK_ML_DIV] = imx_clk_divider2("ml_div", "ml_cg", base + 0x8100, 0, 3); + clks[IMX8MP_CLK_GPU3D_CORE_DIV] = imx_clk_divider2("gpu3d_core_div", "gpu3d_core_cg", base + 0x8180, 0, 3); + clks[IMX8MP_CLK_GPU3D_SHADER_DIV] = imx_clk_divider2("gpu3d_shader_div", "gpu3d_shader_cg", base + 0x8200, 0, 3); + clks[IMX8MP_CLK_GPU2D_DIV] = imx_clk_divider2("gpu2d_div", "gpu2d_cg", base + 0x8280, 0, 3); + clks[IMX8MP_CLK_AUDIO_AXI_DIV] = imx_clk_divider2("audio_axi_div", "audio_axi_cg", base + 0x8300, 0, 3); + clks[IMX8MP_CLK_HSIO_AXI_DIV] = imx_clk_divider2("hsio_axi_div", "hsio_axi_cg", base + 0x8380, 0, 3); + clks[IMX8MP_CLK_MEDIA_ISP_DIV] = imx_clk_divider2("media_isp_div", "media_isp_cg", base + 0x8400, 0, 3); + + /* CORE SEL */ + clks[IMX8MP_CLK_A53_CORE] = imx_clk_mux2_flags("arm_a53_core", base + 0x9880, 24, 1, imx8mp_a53_core_sels, ARRAY_SIZE(imx8mp_a53_core_sels), CLK_IS_CRITICAL); + + /* BUS */ + clks[IMX8MP_CLK_MAIN_AXI] = imx8m_clk_composite_critical("main_axi", imx8mp_main_axi_sels, base + 0x8800); + clks[IMX8MP_CLK_ENET_AXI] = imx8m_clk_composite("enet_axi", imx8mp_enet_axi_sels, base + 0x8880); + clks[IMX8MP_CLK_NAND_USDHC_BUS] = imx8m_clk_composite("nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 0x8900); + clks[IMX8MP_CLK_VPU_BUS] = imx8m_clk_composite("vpu_bus", imx8mp_vpu_bus_sels, base + 0x8980); + clks[IMX8MP_CLK_MEDIA_AXI] = imx8m_clk_composite("media_axi", imx8mp_media_axi_sels, base + 0x8a00); + clks[IMX8MP_CLK_MEDIA_APB] = imx8m_clk_composite("media_apb", imx8mp_media_apb_sels, base + 0x8a80); + clks[IMX8MP_CLK_HDMI_APB] = imx8m_clk_composite("hdmi_apb", imx8mp_media_apb_sels, base + 0x8b00); + clks[IMX8MP_CLK_HDMI_AXI] = imx8m_clk_composite("hdmi_axi", imx8mp_media_axi_sels, base + 0x8b80); + clks[IMX8MP_CLK_GPU_AXI] = imx8m_clk_composite("gpu_axi", imx8mp_gpu_axi_sels, base + 0x8c00); + clks[IMX8MP_CLK_GPU_AHB] = imx8m_clk_composite("gpu_ahb", imx8mp_gpu_ahb_sels, base + 0x8c80); + clks[IMX8MP_CLK_NOC] = imx8m_clk_composite_critical("noc", imx8mp_noc_sels, base + 0x8d00); + clks[IMX8MP_CLK_NOC_IO] = imx8m_clk_composite_critical("noc_io", imx8mp_noc_io_sels, base + 0x8d80); + clks[IMX8MP_CLK_ML_AXI] = imx8m_clk_composite("ml_axi", imx8mp_ml_axi_sels, base + 0x8e00); + clks[IMX8MP_CLK_ML_AHB] = imx8m_clk_composite("ml_ahb", imx8mp_ml_ahb_sels, base + 0x8e80); + + /* AHB */ + clks[IMX8MP_CLK_AHB] = imx8m_clk_composite_critical("ahb_root", imx8mp_ahb_sels, base + 0x9000); + clks[IMX8MP_CLK_AUDIO_AHB] = imx8m_clk_composite("audio_ahb", imx8mp_audio_ahb_sels, base + 0x9100); + clks[IMX8MP_CLK_MIPI_DSI_ESC_RX] = imx8m_clk_composite("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, base + 0x9200); + clks[IMX8MP_CLK_MEDIA_DISP2_PIX] = imx8m_clk_composite("media_disp2_pix", imx8mp_media_disp2_pix_sels, base + 0x9300); + + /* IPG */ + clks[IMX8MP_CLK_IPG_ROOT] = imx_clk_divider2("ipg_root", "ahb_root", base + 0x9080, 0, 1); + clks[IMX8MP_CLK_IPG_AUDIO_ROOT] = imx_clk_divider2("ipg_audio_root", "audio_ahb", base + 0x9180, 0, 1); + + /* IP */ + clks[IMX8MP_CLK_DRAM_ALT] = imx8m_clk_composite("dram_alt", imx8mp_dram_alt_sels, base + 0xa000); + clks[IMX8MP_CLK_DRAM_APB] = imx8m_clk_composite_critical("dram_apb", imx8mp_dram_apb_sels, base + 0xa080); + clks[IMX8MP_CLK_VPU_G1] = imx8m_clk_composite("vpu_g1", imx8mp_vpu_g1_sels, base + 0xa100); + clks[IMX8MP_CLK_VPU_G2] = imx8m_clk_composite("vpu_g2", imx8mp_vpu_g2_sels, base + 0xa180); + clks[IMX8MP_CLK_CAN1] = imx8m_clk_composite("can1", imx8mp_can1_sels, base + 0xa200); + clks[IMX8MP_CLK_CAN2] = imx8m_clk_composite("can2", imx8mp_can2_sels, base + 0xa280); + clks[IMX8MP_CLK_PCIE_PHY] = imx8m_clk_composite("pcie_phy", imx8mp_pcie_phy_sels, base + 0xa380); + clks[IMX8MP_CLK_PCIE_AUX] = imx8m_clk_composite("pcie_aux", imx8mp_pcie_aux_sels, base + 0xa400); + clks[IMX8MP_CLK_I2C5] = imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, base + 0xa480); + clks[IMX8MP_CLK_I2C6] = imx8m_clk_composite("i2c6", imx8mp_i2c6_sels, base + 0xa500); + clks[IMX8MP_CLK_SAI1] = imx8m_clk_composite("sai1", imx8mp_sai1_sels, base + 0xa580); + clks[IMX8MP_CLK_SAI2] = imx8m_clk_composite("sai2", imx8mp_sai2_sels, base + 0xa600); + clks[IMX8MP_CLK_SAI3] = imx8m_clk_composite("sai3", imx8mp_sai3_sels, base + 0xa680); + clks[IMX8MP_CLK_SAI4] = imx8m_clk_composite("sai4", imx8mp_sai4_sels, base + 0xa700); + clks[IMX8MP_CLK_SAI5] = imx8m_clk_composite("sai5", imx8mp_sai5_sels, base + 0xa780); + clks[IMX8MP_CLK_SAI6] = imx8m_clk_composite("sai6", imx8mp_sai6_sels, base + 0xa800); + clks[IMX8MP_CLK_ENET_QOS] = imx8m_clk_composite("enet_qos", imx8mp_enet_qos_sels, base + 0xa880); + clks[IMX8MP_CLK_ENET_QOS_TIMER] = imx8m_clk_composite("enet_qos_timer", imx8mp_enet_qos_timer_sels, base + 0xa900); + clks[IMX8MP_CLK_ENET_REF] = imx8m_clk_composite("enet_ref", imx8mp_enet_ref_sels, base + 0xa980); + clks[IMX8MP_CLK_ENET_TIMER] = imx8m_clk_composite("enet_timer", imx8mp_enet_timer_sels, base + 0xaa00); + clks[IMX8MP_CLK_ENET_PHY_REF] = imx8m_clk_composite("enet_phy_ref", imx8mp_enet_phy_ref_sels, base + 0xaa80); + clks[IMX8MP_CLK_NAND] = imx8m_clk_composite("nand", imx8mp_nand_sels, base + 0xab00); + clks[IMX8MP_CLK_QSPI] = imx8m_clk_composite("qspi", imx8mp_qspi_sels, base + 0xab80); + clks[IMX8MP_CLK_USDHC1] = imx8m_clk_composite("usdhc1", imx8mp_usdhc1_sels, base + 0xac00); + clks[IMX8MP_CLK_USDHC2] = imx8m_clk_composite("usdhc2", imx8mp_usdhc2_sels, base + 0xac80); + clks[IMX8MP_CLK_I2C1] = imx8m_clk_composite("i2c1", imx8mp_i2c1_sels, base + 0xad00); + clks[IMX8MP_CLK_I2C2] = imx8m_clk_composite("i2c2", imx8mp_i2c2_sels, base + 0xad80); + clks[IMX8MP_CLK_I2C3] = imx8m_clk_composite("i2c3", imx8mp_i2c3_sels, base + 0xae00); + clks[IMX8MP_CLK_I2C4] = imx8m_clk_composite("i2c4", imx8mp_i2c4_sels, base + 0xae80); + + clks[IMX8MP_CLK_UART1] = imx8m_clk_composite("uart1", imx8mp_uart1_sels, base + 0xaf00); + clks[IMX8MP_CLK_UART2] = imx8m_clk_composite("uart2", imx8mp_uart2_sels, base + 0xaf80); + clks[IMX8MP_CLK_UART3] = imx8m_clk_composite("uart3", imx8mp_uart3_sels, base + 0xb000); + clks[IMX8MP_CLK_UART4] = imx8m_clk_composite("uart4", imx8mp_uart4_sels, base + 0xb080); + clks[IMX8MP_CLK_USB_CORE_REF] = imx8m_clk_composite("usb_core_ref", imx8mp_usb_core_ref_sels, base + 0xb100); + clks[IMX8MP_CLK_USB_PHY_REF] = imx8m_clk_composite("usb_phy_ref", imx8mp_usb_phy_ref_sels, base + 0xb180); + clks[IMX8MP_CLK_GIC] = imx8m_clk_composite_critical("gic", imx8mp_gic_sels, base + 0xb200); + clks[IMX8MP_CLK_ECSPI1] = imx8m_clk_composite("ecspi1", imx8mp_ecspi1_sels, base + 0xb280); + clks[IMX8MP_CLK_ECSPI2] = imx8m_clk_composite("ecspi2", imx8mp_ecspi2_sels, base + 0xb300); + clks[IMX8MP_CLK_PWM1] = imx8m_clk_composite("pwm1", imx8mp_pwm1_sels, base + 0xb380); + clks[IMX8MP_CLK_PWM2] = imx8m_clk_composite("pwm2", imx8mp_pwm2_sels, base + 0xb400); + clks[IMX8MP_CLK_PWM3] = imx8m_clk_composite("pwm3", imx8mp_pwm3_sels, base + 0xb480); + clks[IMX8MP_CLK_PWM4] = imx8m_clk_composite("pwm4", imx8mp_pwm4_sels, base + 0xb500); + + clks[IMX8MP_CLK_GPT1] = imx8m_clk_composite("gpt1", imx8mp_gpt1_sels, base + 0xb580); + clks[IMX8MP_CLK_GPT2] = imx8m_clk_composite("gpt2", imx8mp_gpt2_sels, base + 0xb600); + clks[IMX8MP_CLK_GPT3] = imx8m_clk_composite("gpt3", imx8mp_gpt3_sels, base + 0xb680); + clks[IMX8MP_CLK_GPT4] = imx8m_clk_composite("gpt4", imx8mp_gpt4_sels, base + 0xb700); + clks[IMX8MP_CLK_GPT5] = imx8m_clk_composite("gpt5", imx8mp_gpt5_sels, base + 0xb780); + clks[IMX8MP_CLK_GPT6] = imx8m_clk_composite("gpt6", imx8mp_gpt6_sels, base + 0xb800); + clks[IMX8MP_CLK_WDOG] = imx8m_clk_composite("wdog", imx8mp_wdog_sels, base + 0xb900); + clks[IMX8MP_CLK_WRCLK] = imx8m_clk_composite("wrclk", imx8mp_wrclk_sels, base + 0xb980); + clks[IMX8MP_CLK_IPP_DO_CLKO1] = imx8m_clk_composite("ipp_do_clko1", imx8mp_ipp_do_clko1_sels, base + 0xba00); + clks[IMX8MP_CLK_IPP_DO_CLKO2] = imx8m_clk_composite("ipp_do_clko2", imx8mp_ipp_do_clko2_sels, base + 0xba80); + clks[IMX8MP_CLK_HDMI_FDCC_TST] = imx8m_clk_composite("hdmi_fdcc_tst", imx8mp_hdmi_fdcc_tst_sels, base + 0xbb00); + clks[IMX8MP_CLK_HDMI_24M] = imx8m_clk_composite("hdmi_24m", imx8mp_hdmi_24m_sels, base + 0xbb80); + clks[IMX8MP_CLK_HDMI_REF_266M] = imx8m_clk_composite("hdmi_ref_266m", imx8mp_hdmi_ref_266m_sels, base + 0xbc00); + clks[IMX8MP_CLK_USDHC3] = imx8m_clk_composite("usdhc3", imx8mp_usdhc3_sels, base + 0xbc80); + clks[IMX8MP_CLK_MEDIA_CAM1_PIX] = imx8m_clk_composite("media_cam1_pix", imx8mp_media_cam1_pix_sels, base + 0xbd00); + clks[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF] = imx8m_clk_composite("media_mipi_phy1_ref", imx8mp_media_mipi_phy1_ref_sels, base + 0xbd80); + clks[IMX8MP_CLK_MEDIA_DISP1_PIX] = imx8m_clk_composite("media_disp1_pix", imx8mp_media_disp1_pix_sels, base + 0xbe00); + clks[IMX8MP_CLK_MEDIA_CAM2_PIX] = imx8m_clk_composite("media_cam2_pix", imx8mp_media_cam2_pix_sels, base + 0xbe80); + clks[IMX8MP_CLK_MEDIA_LDB] = imx8m_clk_composite("media_ldb", imx8mp_media_ldb_sels, base + 0xbf00); + clks[IMX8MP_CLK_MEMREPAIR] = imx8m_clk_composite_critical("mem_repair", imx8mp_memrepair_sels, base + 0xbf80); + clks[IMX8MP_CLK_PCIE2_CTRL] = imx8m_clk_composite("pcie2_ctrl", imx8mp_pcie2_ctrl_sels, base + 0xc000); + clks[IMX8MP_CLK_PCIE2_PHY] = imx8m_clk_composite("pcie2_phy", imx8mp_pcie2_phy_sels, base + 0xc080); + clks[IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE] = imx8m_clk_composite("media_mipi_test_byte", imx8mp_media_mipi_test_byte_sels, base + 0xc100); + clks[IMX8MP_CLK_ECSPI3] = imx8m_clk_composite("ecspi3", imx8mp_ecspi3_sels, base + 0xc180); + clks[IMX8MP_CLK_PDM] = imx8m_clk_composite("pdm", imx8mp_pdm_sels, base + 0xc200); + clks[IMX8MP_CLK_VPU_VC8000E] = imx8m_clk_composite("vpu_vc8000e", imx8mp_vpu_vc8000e_sels, base + 0xc280); + clks[IMX8MP_CLK_SAI7] = imx8m_clk_composite("sai7", imx8mp_sai7_sels, base + 0xc300); + + clks[IMX8MP_CLK_DRAM_ALT_ROOT] = imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4); + clks[IMX8MP_CLK_DRAM_CORE] = imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL); + + /* CCGR */ + clks[IMX8MP_CLK_DRAM1_ROOT] = imx_clk_gate4_flags("dram1_root_clk", "dram_core_clk", base + 0x4050, 0, CLK_IS_CRITICAL); + clks[IMX8MP_CLK_ECSPI1_ROOT] = imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0); + clks[IMX8MP_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0); + clks[IMX8MP_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0); + clks[IMX8MP_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0); + clks[IMX8MP_CLK_GPIO1_ROOT] = imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0); + clks[IMX8MP_CLK_GPIO2_ROOT] = imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0); + clks[IMX8MP_CLK_GPIO3_ROOT] = imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0); + clks[IMX8MP_CLK_GPIO4_ROOT] = imx_clk_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0); + clks[IMX8MP_CLK_GPIO5_ROOT] = imx_clk_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0); + clks[IMX8MP_CLK_GPT1_ROOT] = imx_clk_gate4("gpt1_root_clk", "gpt1", base + 0x4100, 0); + clks[IMX8MP_CLK_GPT2_ROOT] = imx_clk_gate4("gpt2_root_clk", "gpt2", base + 0x4110, 0); + clks[IMX8MP_CLK_GPT3_ROOT] = imx_clk_gate4("gpt3_root_clk", "gpt3", base + 0x4120, 0); + clks[IMX8MP_CLK_GPT4_ROOT] = imx_clk_gate4("gpt4_root_clk", "gpt4", base + 0x4130, 0); + clks[IMX8MP_CLK_GPT5_ROOT] = imx_clk_gate4("gpt5_root_clk", "gpt5", base + 0x4140, 0); + clks[IMX8MP_CLK_GPT6_ROOT] = imx_clk_gate4("gpt6_root_clk", "gpt6", base + 0x4150, 0); + clks[IMX8MP_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0); + clks[IMX8MP_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0); + clks[IMX8MP_CLK_I2C3_ROOT] = imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0); + clks[IMX8MP_CLK_I2C4_ROOT] = imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0); + clks[IMX8MP_CLK_MU_ROOT] = imx_clk_gate4("mu_root_clk", "ipg_root", base + 0x4210, 0); + clks[IMX8MP_CLK_OCOTP_ROOT] = imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0); + clks[IMX8MP_CLK_PCIE_ROOT] = imx_clk_gate4("pcie_root_clk", "pcie_aux", base + 0x4250, 0); + clks[IMX8MP_CLK_PWM1_ROOT] = imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0); + clks[IMX8MP_CLK_PWM2_ROOT] = imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0); + clks[IMX8MP_CLK_PWM3_ROOT] = imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0); + clks[IMX8MP_CLK_PWM4_ROOT] = imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0); + clks[IMX8MP_CLK_QOS_ROOT] = imx_clk_gate4("qos_root_clk", "ipg_root", base + 0x42c0, 0); + clks[IMX8MP_CLK_QOS_ENET_ROOT] = imx_clk_gate4("qos_enet_root_clk", "ipg_root", base + 0x42e0, 0); + clks[IMX8MP_CLK_QSPI_ROOT] = imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0); + clks[IMX8MP_CLK_NAND_ROOT] = imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand); + clks[IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0, &share_count_nand); + clks[IMX8MP_CLK_I2C5_ROOT] = imx_clk_gate2("i2c5_root_clk", "i2c5", base + 0x4330, 0); + clks[IMX8MP_CLK_I2C6_ROOT] = imx_clk_gate2("i2c6_root_clk", "i2c6", base + 0x4340, 0); + clks[IMX8MP_CLK_CAN1_ROOT] = imx_clk_gate2("can1_root_clk", "can1", base + 0x4350, 0); + clks[IMX8MP_CLK_CAN2_ROOT] = imx_clk_gate2("can2_root_clk", "can2", base + 0x4360, 0); + clks[IMX8MP_CLK_SDMA1_ROOT] = imx_clk_gate4("sdma1_root_clk", "ipg_root", base + 0x43a0, 0); + clks[IMX8MP_CLK_SIM_ENET_ROOT] = imx_clk_gate4("sim_enet_root_clk", "enet_axi", base + 0x4400, 0); + clks[IMX8MP_CLK_ENET_QOS_ROOT] = imx_clk_gate4("enet_qos_root_clk", "sim_enet_root_clk", base + 0x43b0, 0); + clks[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_gate4("gpu2d_root_clk", "gpu2d_div", base + 0x4450, 0); + clks[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_gate4("gpu3d_root_clk", "gpu3d_core_div", base + 0x4460, 0); + clks[IMX8MP_CLK_SNVS_ROOT] = imx_clk_gate4("snvs_root_clk", "ipg_root", base + 0x4470, 0); + clks[IMX8MP_CLK_UART1_ROOT] = imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0); + clks[IMX8MP_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0); + clks[IMX8MP_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0); + clks[IMX8MP_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0); + clks[IMX8MP_CLK_USB_ROOT] = imx_clk_gate4("usb_root_clk", "osc_32k", base + 0x44d0, 0); + clks[IMX8MP_CLK_USB_PHY_ROOT] = imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0); + clks[IMX8MP_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0); + clks[IMX8MP_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0); + clks[IMX8MP_CLK_WDOG1_ROOT] = imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0); + clks[IMX8MP_CLK_WDOG2_ROOT] = imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0); + clks[IMX8MP_CLK_WDOG3_ROOT] = imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0); + clks[IMX8MP_CLK_VPU_G1_ROOT] = imx_clk_gate4("vpu_g1_root_clk", "vpu_g1", base + 0x4560, 0); + clks[IMX8MP_CLK_GPU_ROOT] = imx_clk_gate4("gpu_root_clk", "gpu_axi", base + 0x4570, 0); + clks[IMX8MP_CLK_VPU_VC8KE_ROOT] = imx_clk_gate4("vpu_vc8ke_root_clk", "vpu_vc8000e", base + 0x4590, 0); + clks[IMX8MP_CLK_VPU_G2_ROOT] = imx_clk_gate4("vpu_g2_root_clk", "vpu_g2", base + 0x45a0, 0); + clks[IMX8MP_CLK_NPU_ROOT] = imx_clk_gate4("npu_root_clk", "ml_div", base + 0x45b0, 0); + clks[IMX8MP_CLK_HSIO_ROOT] = imx_clk_gate4("hsio_root_clk", "ipg_root", base + 0x45c0, 0); + clks[IMX8MP_CLK_MEDIA_APB_ROOT] = imx_clk_gate2_shared2("media_apb_root_clk", "media_apb", base + 0x45d0, 0, &share_count_media); + clks[IMX8MP_CLK_MEDIA_AXI_ROOT] = imx_clk_gate2_shared2("media_axi_root_clk", "media_axi", base + 0x45d0, 0, &share_count_media); + clks[IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT] = imx_clk_gate2_shared2("media_cam1_pix_root_clk", "media_cam1_pix", base + 0x45d0, 0, &share_count_media); + clks[IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT] = imx_clk_gate2_shared2("media_cam2_pix_root_clk", "media_cam2_pix", base + 0x45d0, 0, &share_count_media); + clks[IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT] = imx_clk_gate2_shared2("media_disp1_pix_root_clk", "media_disp1_pix", base + 0x45d0, 0, &share_count_media); + clks[IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT] = imx_clk_gate2_shared2("media_disp2_pix_root_clk", "media_disp2_pix", base + 0x45d0, 0, &share_count_media); + clks[IMX8MP_CLK_MEDIA_LDB_ROOT] = imx_clk_gate2_shared2("media_ldb_root_clk", "media_ldb", base + 0x45d0, 0, &share_count_media); + clks[IMX8MP_CLK_MEDIA_ISP_ROOT] = imx_clk_gate2_shared2("media_isp_root_clk", "media_isp_div", base + 0x45d0, 0, &share_count_media); + + clks[IMX8MP_CLK_USDHC3_ROOT] = imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0); + clks[IMX8MP_CLK_HDMI_ROOT] = imx_clk_gate4("hdmi_root_clk", "hdmi_axi", base + 0x45f0, 0); + clks[IMX8MP_CLK_TSENSOR_ROOT] = imx_clk_gate4("tsensor_root_clk", "ipg_root", base + 0x4620, 0); + clks[IMX8MP_CLK_VPU_ROOT] = imx_clk_gate4("vpu_root_clk", "vpu_bus", base + 0x4630, 0); + clks[IMX8MP_CLK_AUDIO_ROOT] = imx_clk_gate4("audio_root_clk", "ipg_audio_root", base + 0x4650, 0); + + clk_set_parent(clks[IMX8MP_CLK_A53_SRC], clks[IMX8MP_SYS_PLL1_800M]); + clk_set_parent(clks[IMX8MP_CLK_A53_CORE], clks[IMX8MP_ARM_PLL_OUT]); + + clks[IMX8MP_CLK_ARM] = imx_clk_cpu("arm", "arm_a53_core", + clks[IMX8MP_CLK_A53_CORE], + clks[IMX8MP_CLK_A53_CORE], + clks[IMX8MP_ARM_PLL_OUT], + clks[IMX8MP_CLK_A53_DIV]); + + imx_check_clocks(clks, ARRAY_SIZE(clks)); + + clk_data.clks = clks; + clk_data.clk_num = ARRAY_SIZE(clks); + ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + if (ret < 0) { + pr_err("failed to register clks for i.MX8MP\n"); + return -ENOMEM; + } + + imx_clk_init_on(np, clks); + + clk_prepare_enable(clks[IMX8MP_CLK_QOS_ENET_ROOT]); + clk_prepare_enable(clks[IMX8MP_CLK_ENET_QOS_ROOT]); + + imx_register_uart_clocks(); + + pr_info("i.MX8MP clock driver probe done\n"); + + return 0; +} + +static const struct of_device_id imx8mp_clk_of_match[] = { + { .compatible = "fsl,imx8mp-ccm" }, + { /* Sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, imx8mp_clk_of_match); + + +static struct platform_driver imx8mp_clk_driver = { + .probe = imx8mp_clocks_probe, + .driver = { + .name = "imx8mp-ccm", + .of_match_table = of_match_ptr(imx8mp_clk_of_match), + }, +}; +module_platform_driver(imx8mp_clk_driver); diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index 41fc9c63356ea9..74b23a46c1c0da 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include #include "clk.h" @@ -26,7 +28,7 @@ static u32 share_count_nand; static struct clk *clks[IMX8MQ_CLK_END]; -static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy", "dummy", }; +static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "phy_27m", "dummy", }; static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", }; @@ -38,11 +40,14 @@ static const char * const sys1_pll_out_sels[] = {"sys1_pll1_ref_sel", }; static const char * const sys2_pll_out_sels[] = {"sys1_pll1_ref_sel", "sys2_pll1_ref_sel", }; static const char * const sys3_pll_out_sels[] = {"sys3_pll1_ref_sel", "sys2_pll1_ref_sel", }; static const char * const dram_pll_out_sels[] = {"dram_pll1_ref_sel", }; +static const char *video2_pll_out_sels[] = {"video2_pll1_ref_sel", }; /* CCM ROOT */ static const char * const imx8mq_a53_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m", "sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "sys3_pll_out", }; +static const char *imx8mq_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", }; + static const char * const imx8mq_arm_m4_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_250m", "sys1_pll_266m", "sys1_pll_800m", "audio_pll1_out", "video_pll1_out", "sys3_pll_out", }; @@ -272,13 +277,31 @@ static const char * const imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sy static struct clk_onecell_data clk_data; -static struct clk ** const uart_clks[] = { - &clks[IMX8MQ_CLK_UART1_ROOT], - &clks[IMX8MQ_CLK_UART2_ROOT], - &clks[IMX8MQ_CLK_UART3_ROOT], - &clks[IMX8MQ_CLK_UART4_ROOT], - NULL -}; +static int __init imx_clk_init_on(struct device_node *np, + struct clk * const clks[]) +{ + u32 *array; + int i, ret, elems; + + elems = of_property_count_u32_elems(np, "init-on-array"); + if (elems < 0) + return elems; + array = kzalloc(elems * sizeof(elems), GFP_KERNEL); + if (IS_ERR_OR_NULL(array)) + return PTR_ERR(array); + + ret = of_property_read_u32_array(np, "init-on-array", array, elems); + if (ret) + return ret; + + for (i = 0; i < elems; i++) { + ret = clk_prepare_enable(clks[array[i]]); + if (ret) + pr_err("clk_prepare_enable failed %d\n", array[i]); + } + + return 0; +} static int imx8mq_clocks_probe(struct platform_device *pdev) { @@ -287,6 +310,8 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) void __iomem *base; int err; + check_m4_enabled(); + clks[IMX8MQ_CLK_DUMMY] = imx_clk_fixed("dummy", 0); clks[IMX8MQ_CLK_32K] = of_clk_get_by_name(np, "ckil"); clks[IMX8MQ_CLK_25M] = of_clk_get_by_name(np, "osc_25m"); @@ -295,6 +320,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) clks[IMX8MQ_CLK_EXT2] = of_clk_get_by_name(np, "clk_ext2"); clks[IMX8MQ_CLK_EXT3] = of_clk_get_by_name(np, "clk_ext3"); clks[IMX8MQ_CLK_EXT4] = of_clk_get_by_name(np, "clk_ext4"); + clks[IMX8MQ_CLK_PHY_27MHZ] = imx_clk_fixed("phy_27m", 27000000); np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop"); base = of_iomap(np, 0); @@ -311,6 +337,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) clks[IMX8MQ_SYS2_PLL1_REF_SEL] = imx_clk_mux("sys2_pll1_ref_sel", base + 0x3c, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); clks[IMX8MQ_SYS3_PLL1_REF_SEL] = imx_clk_mux("sys3_pll1_ref_sel", base + 0x48, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); clks[IMX8MQ_DRAM_PLL1_REF_SEL] = imx_clk_mux("dram_pll1_ref_sel", base + 0x60, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MQ_VIDEO2_PLL1_REF_SEL] = imx_clk_mux("video2_pll1_ref_sel", base + 0x54, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); clks[IMX8MQ_ARM_PLL_REF_DIV] = imx_clk_divider("arm_pll_ref_div", "arm_pll_ref_sel", base + 0x28, 5, 6); clks[IMX8MQ_GPU_PLL_REF_DIV] = imx_clk_divider("gpu_pll_ref_div", "gpu_pll_ref_sel", base + 0x18, 5, 6); @@ -334,6 +361,13 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) clks[IMX8MQ_AUDIO_PLL2_BYPASS] = imx_clk_mux("audio_pll2_bypass", base + 0x8, 14, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels)); clks[IMX8MQ_VIDEO_PLL1_BYPASS] = imx_clk_mux("video_pll1_bypass", base + 0x10, 14, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels)); + /* unbypass all the plls */ + clk_set_parent(clks[IMX8MQ_GPU_PLL_BYPASS], clks[IMX8MQ_GPU_PLL]); + clk_set_parent(clks[IMX8MQ_VPU_PLL_BYPASS], clks[IMX8MQ_VPU_PLL]); + clk_set_parent(clks[IMX8MQ_AUDIO_PLL1_BYPASS], clks[IMX8MQ_AUDIO_PLL1]); + clk_set_parent(clks[IMX8MQ_AUDIO_PLL2_BYPASS], clks[IMX8MQ_AUDIO_PLL2]); + clk_set_parent(clks[IMX8MQ_VIDEO_PLL1_BYPASS], clks[IMX8MQ_VIDEO_PLL1]); + /* PLL OUT GATE */ clks[IMX8MQ_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x28, 21); clks[IMX8MQ_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x18, 21); @@ -346,6 +380,8 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_sccg_pll("sys2_pll_out", sys2_pll_out_sels, ARRAY_SIZE(sys2_pll_out_sels), 0, 0, 1, base + 0x3c, CLK_IS_CRITICAL); clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_sccg_pll("sys3_pll_out", sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 1, base + 0x48, CLK_IS_CRITICAL); clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_sccg_pll("dram_pll_out", dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60, CLK_IS_CRITICAL); + clks[IMX8MQ_VIDEO2_PLL_OUT] = imx_clk_sccg_pll("video2_pll_out", video2_pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, base + 0x54, 0); + /* SYS PLL fixed output */ clks[IMX8MQ_SYS1_PLL_40M] = imx_clk_fixed_factor("sys1_pll_40m", "sys1_pll_out", 1, 20); clks[IMX8MQ_SYS1_PLL_80M] = imx_clk_fixed_factor("sys1_pll_80m", "sys1_pll_out", 1, 10); @@ -391,6 +427,9 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) clks[IMX8MQ_CLK_GPU_CORE_DIV] = imx_clk_divider2("gpu_core_div", "gpu_core_cg", base + 0x8180, 0, 3); clks[IMX8MQ_CLK_GPU_SHADER_DIV] = imx_clk_divider2("gpu_shader_div", "gpu_shader_cg", base + 0x8200, 0, 3); + /* CORE SEL */ + clks[IMX8MQ_CLK_A53_CORE] = imx_clk_mux2_flags("arm_a53_core", base + 0x9880, 24, 1, imx8mq_a53_core_sels, ARRAY_SIZE(imx8mq_a53_core_sels), CLK_IS_CRITICAL); + /* BUS */ clks[IMX8MQ_CLK_MAIN_AXI] = imx8m_clk_composite_critical("main_axi", imx8mq_main_axi_sels, base + 0x8800); clks[IMX8MQ_CLK_ENET_AXI] = imx8m_clk_composite("enet_axi", imx8mq_enet_axi_sels, base + 0x8880); @@ -550,11 +589,14 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) clks[IMX8MQ_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc_25m", 1, 8); clks[IMX8MQ_CLK_DRAM_ALT_ROOT] = imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4); - clks[IMX8MQ_CLK_ARM] = imx_clk_cpu("arm", "arm_a53_div", - clks[IMX8MQ_CLK_A53_DIV], - clks[IMX8MQ_CLK_A53_SRC], + clk_set_parent(clks[IMX8MQ_CLK_A53_SRC], clks[IMX8MQ_SYS1_PLL_800M]); + clk_set_parent(clks[IMX8MQ_CLK_A53_CORE], clks[IMX8MQ_ARM_PLL_OUT]); + + clks[IMX8MQ_CLK_ARM] = imx_clk_cpu("arm", "arm_a53_core", + clks[IMX8MQ_CLK_A53_CORE], + clks[IMX8MQ_CLK_A53_CORE], clks[IMX8MQ_ARM_PLL_OUT], - clks[IMX8MQ_SYS1_PLL_800M]); + clks[IMX8MQ_CLK_A53_DIV]); imx_check_clocks(clks, ARRAY_SIZE(clks)); @@ -567,7 +609,17 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) goto unregister_clks; } - imx_register_uart_clocks(uart_clks); + /* enable all the clocks just for bringup */ + imx_clk_init_on(np, clks); + + clk_set_parent(clks[IMX8MQ_CLK_CSI1_CORE], clks[IMX8MQ_SYS1_PLL_266M]); + clk_set_parent(clks[IMX8MQ_CLK_CSI1_PHY_REF], clks[IMX8MQ_SYS2_PLL_1000M]); + clk_set_parent(clks[IMX8MQ_CLK_CSI1_ESC], clks[IMX8MQ_SYS1_PLL_800M]); + clk_set_parent(clks[IMX8MQ_CLK_CSI2_CORE], clks[IMX8MQ_SYS1_PLL_266M]); + clk_set_parent(clks[IMX8MQ_CLK_CSI2_PHY_REF], clks[IMX8MQ_SYS2_PLL_1000M]); + clk_set_parent(clks[IMX8MQ_CLK_CSI2_ESC], clks[IMX8MQ_SYS1_PLL_800M]); + + imx_register_uart_clocks(); return 0; diff --git a/drivers/clk/imx/clk-imx8qm-acm.c b/drivers/clk/imx/clk-imx8qm-acm.c new file mode 100644 index 00000000000000..068909d688d8be --- /dev/null +++ b/drivers/clk/imx/clk-imx8qm-acm.c @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" +#include "clk-scu.h" +#include "clk-imx-acm-utils.h" + +#include + +struct imx8qm_acm_priv { + struct clk_imx_acm_pm_domains dev_pm; + void __iomem *reg; + u32 regs[32]; +}; + +static const char *aud_clk_sels[] = { + "aud_rec_clk0_lpcg_clk", + "aud_rec_clk1_lpcg_clk", + "mlb_clk", + "hdmi_rx_mclk", + "ext_aud_mclk0", + "ext_aud_mclk1", + "esai0_rx_clk", + "esai0_rx_hf_clk", + "esai0_tx_clk", + "esai0_tx_hf_clk", + "esai1_rx_clk", + "esai1_rx_hf_clk", + "esai1_tx_clk", + "esai1_tx_hf_clk", + "spdif0_rx", + "spdif1_rx", + "sai0_rx_bclk", + "sai0_tx_bclk", + "sai1_rx_bclk", + "sai1_tx_bclk", + "sai2_rx_bclk", + "sai3_rx_bclk", + "sai4_rx_bclk", +}; + +static const char *mclk_out_sels[] = { + "aud_rec_clk0_lpcg_clk", + "aud_rec_clk1_lpcg_clk", + "mlb_clk", + "hdmi_rx_mclk", + "spdif0_rx", + "spdif1_rx", + "sai4_rx_bclk", + "sai6_rx_bclk", +}; + +static const char *sai_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static const char *asrc_mux_clk_sels[] = { + "sai4_rx_bclk", + "sai5_tx_bclk", + "dummy", + "mlb_clk", +}; + +static const char *esai_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static const char *spdif_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static const char *mqs_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static int imx8qm_acm_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct clk_onecell_data *clk_data; + struct imx8qm_acm_priv *priv; + struct resource *res; + struct clk **clks; + void __iomem *base; + int ret; + int i; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap(dev, res->start, resource_size(res)); + if (!base) + return -ENOMEM; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->reg = base; + + platform_set_drvdata(pdev, priv); + + clk_data = devm_kzalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + clk_data->clks = devm_kcalloc(&pdev->dev, IMX_ADMA_ACM_CLK_END, + sizeof(*clk_data->clks), GFP_KERNEL); + if (!clk_data->clks) + return -ENOMEM; + + clk_data->clk_num = IMX_ADMA_ACM_CLK_END; + + clks = clk_data->clks; + + ret = clk_imx_acm_attach_pm_domains(&pdev->dev, &priv->dev_pm); + if (ret) + return ret; + + pm_runtime_enable(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + + clks[IMX_ADMA_EXT_AUD_MCLK0] = imx_clk_fixed("ext_aud_mclk0", 0); + clks[IMX_ADMA_EXT_AUD_MCLK1] = imx_clk_fixed("ext_aud_mclk1", 0); + clks[IMX_ADMA_ESAI0_RX_CLK] = imx_clk_fixed("esai0_rx_clk", 0); + clks[IMX_ADMA_ESAI0_RX_HF_CLK] = imx_clk_fixed("esai0_rx_hf_clk", 0); + clks[IMX_ADMA_ESAI0_TX_CLK] = imx_clk_fixed("esai0_tx_clk", 0); + clks[IMX_ADMA_ESAI0_TX_HF_CLK] = imx_clk_fixed("esai0_tx_hf_clk", 0); + clks[IMX_ADMA_ESAI1_RX_CLK] = imx_clk_fixed("esai1_rx_clk", 0); + clks[IMX_ADMA_ESAI1_RX_HF_CLK] = imx_clk_fixed("esai1_rx_hf_clk", 0); + clks[IMX_ADMA_ESAI1_TX_CLK] = imx_clk_fixed("esai1_tx_clk", 0); + clks[IMX_ADMA_ESAI1_TX_HF_CLK] = imx_clk_fixed("esai1_tx_hf_clk", 0); + clks[IMX_ADMA_SPDIF0_RX] = imx_clk_fixed("spdif0_rx", 0); + clks[IMX_ADMA_SPDIF1_RX] = imx_clk_fixed("spdif1_rx", 0); + clks[IMX_ADMA_SAI0_RX_BCLK] = imx_clk_fixed("sai0_rx_bclk", 0); + clks[IMX_ADMA_SAI0_TX_BCLK] = imx_clk_fixed("sai0_tx_bclk", 0); + clks[IMX_ADMA_SAI1_RX_BCLK] = imx_clk_fixed("sai1_rx_bclk", 0); + clks[IMX_ADMA_SAI1_TX_BCLK] = imx_clk_fixed("sai1_tx_bclk", 0); + clks[IMX_ADMA_SAI2_RX_BCLK] = imx_clk_fixed("sai2_rx_bclk", 0); + clks[IMX_ADMA_SAI3_RX_BCLK] = imx_clk_fixed("sai3_rx_bclk", 0); + clks[IMX_ADMA_SAI4_RX_BCLK] = imx_clk_fixed("sai4_rx_bclk", 0); + clks[IMX_ADMA_SAI5_TX_BCLK] = imx_clk_fixed("sai5_tx_bclk", 0); + clks[IMX_ADMA_SAI6_RX_BCLK] = imx_clk_fixed("sai6_rx_bclk", 0); + clks[IMX_ADMA_HDMI_RX_MCLK] = imx_clk_fixed("hdmi_rx_mclk", 0); + clks[IMX_ADMA_MLB_CLK] = imx_clk_fixed("mlb_clk", 0); + + + clks[IMX_ADMA_ACM_AUD_CLK0_SEL] = imx_dev_clk_mux(dev, "acm_aud_clk0_sel", base+0x000000, 0, 5, aud_clk_sels, ARRAY_SIZE(aud_clk_sels)); + clks[IMX_ADMA_ACM_AUD_CLK1_CLK] = imx_dev_clk_mux(dev, "acm_aud_clk1_sel", base+0x010000, 0, 5, aud_clk_sels, ARRAY_SIZE(aud_clk_sels)); + + clks[IMX_ADMA_ACM_MCLKOUT0_SEL] = imx_dev_clk_mux(dev, "acm_mclkout0_sel", base+0x020000, 0, 3, mclk_out_sels, ARRAY_SIZE(mclk_out_sels)); + clks[IMX_ADMA_ACM_MCLKOUT1_SEL] = imx_dev_clk_mux(dev, "acm_mclkout1_sel", base+0x030000, 0, 3, mclk_out_sels, ARRAY_SIZE(mclk_out_sels)); + + clks[IMX_ADMA_ACM_ASRC0_MUX_CLK_SEL] = imx_dev_clk_mux(dev, "acm_asrc0_mclk_sel", base+0x040000, 0, 2, asrc_mux_clk_sels, ARRAY_SIZE(asrc_mux_clk_sels)); + + clks[IMX_ADMA_ACM_ESAI0_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_esai0_mclk_sel", base+0x060000, 0, 2, esai_mclk_sels, ARRAY_SIZE(esai_mclk_sels)); + clks[IMX_ADMA_ACM_ESAI1_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_esai1_mclk_sel", base+0x070000, 0, 2, esai_mclk_sels, ARRAY_SIZE(esai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI0_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai0_mclk_sel", base+0x0E0000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI1_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai1_mclk_sel", base+0x0F0000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI2_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai2_mclk_sel", base+0x100000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI3_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai3_mclk_sel", base+0x110000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI4_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai4_mclk_sel", base+0x120000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI5_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai5_mclk_sel", base+0x130000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI6_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai6_mclk_sel", base+0x140000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI7_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai7_mclk_sel", base+0x150000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + + clks[IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL] = imx_dev_clk_mux(dev, "acm_spdif0_mclk_sel", base+0x1A0000, 0, 2, spdif_mclk_sels, ARRAY_SIZE(spdif_mclk_sels)); + clks[IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL] = imx_dev_clk_mux(dev, "acm_spdif1_mclk_sel", base+0x1B0000, 0, 2, spdif_mclk_sels, ARRAY_SIZE(spdif_mclk_sels)); + clks[IMX_ADMA_ACM_MQS_TX_CLK_SEL] = imx_dev_clk_mux(dev, "acm_mqs_mclk_sel", base+0x1C0000, 0, 2, mqs_mclk_sels, ARRAY_SIZE(mqs_mclk_sels)); + + for (i = 0; i < clk_data->clk_num; i++) { + if (IS_ERR(clks[i])) + pr_warn("i.MX clk %u: register failed with %ld\n", + i, PTR_ERR(clks[i])); + } + + ret = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); + + pm_runtime_put_sync(&pdev->dev); + + return ret; +} + +static int imx8qm_acm_clk_remove(struct platform_device *pdev) +{ + struct imx8qm_acm_priv *priv = dev_get_drvdata(&pdev->dev); + + pm_runtime_disable(&pdev->dev); + + clk_imx_acm_detach_pm_domains(&pdev->dev, &priv->dev_pm); + + return 0; +} + +static const struct of_device_id imx8qm_acm_match[] = { + { .compatible = "nxp,imx8qm-acm", }, + { /* sentinel */ } +}; + +static int __maybe_unused imx8qm_acm_runtime_suspend(struct device *dev) +{ + struct imx8qm_acm_priv *priv = dev_get_drvdata(dev); + + priv->regs[0] = readl_relaxed(priv->reg + 0x000000); + priv->regs[1] = readl_relaxed(priv->reg + 0x010000); + priv->regs[2] = readl_relaxed(priv->reg + 0x020000); + priv->regs[3] = readl_relaxed(priv->reg + 0x030000); + priv->regs[4] = readl_relaxed(priv->reg + 0x040000); + priv->regs[6] = readl_relaxed(priv->reg + 0x060000); + priv->regs[7] = readl_relaxed(priv->reg + 0x070000); + priv->regs[14] = readl_relaxed(priv->reg + 0x0E0000); + priv->regs[15] = readl_relaxed(priv->reg + 0x0F0000); + priv->regs[16] = readl_relaxed(priv->reg + 0x100000); + priv->regs[17] = readl_relaxed(priv->reg + 0x110000); + priv->regs[18] = readl_relaxed(priv->reg + 0x120000); + priv->regs[19] = readl_relaxed(priv->reg + 0x130000); + priv->regs[20] = readl_relaxed(priv->reg + 0x140000); + priv->regs[21] = readl_relaxed(priv->reg + 0x150000); + priv->regs[26] = readl_relaxed(priv->reg + 0x1A0000); + priv->regs[27] = readl_relaxed(priv->reg + 0x1B0000); + priv->regs[28] = readl_relaxed(priv->reg + 0x1C0000); + + return 0; +} + +static int __maybe_unused imx8qm_acm_runtime_resume(struct device *dev) +{ + struct imx8qm_acm_priv *priv = dev_get_drvdata(dev); + + writel_relaxed(priv->regs[0], priv->reg + 0x000000); + writel_relaxed(priv->regs[1], priv->reg + 0x010000); + writel_relaxed(priv->regs[2], priv->reg + 0x020000); + writel_relaxed(priv->regs[3], priv->reg + 0x030000); + writel_relaxed(priv->regs[4], priv->reg + 0x040000); + writel_relaxed(priv->regs[6], priv->reg + 0x060000); + writel_relaxed(priv->regs[7], priv->reg + 0x070000); + writel_relaxed(priv->regs[14], priv->reg + 0x0E0000); + writel_relaxed(priv->regs[15], priv->reg + 0x0F0000); + writel_relaxed(priv->regs[16], priv->reg + 0x100000); + writel_relaxed(priv->regs[17], priv->reg + 0x110000); + writel_relaxed(priv->regs[18], priv->reg + 0x120000); + writel_relaxed(priv->regs[19], priv->reg + 0x130000); + writel_relaxed(priv->regs[20], priv->reg + 0x140000); + writel_relaxed(priv->regs[21], priv->reg + 0x150000); + writel_relaxed(priv->regs[26], priv->reg + 0x1A0000); + writel_relaxed(priv->regs[27], priv->reg + 0x1B0000); + writel_relaxed(priv->regs[28], priv->reg + 0x1C0000); + + return 0; +} + +static const struct dev_pm_ops imx8qm_acm_pm_ops = { + SET_RUNTIME_PM_OPS(imx8qm_acm_runtime_suspend, + imx8qm_acm_runtime_resume, NULL) + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + +static struct platform_driver imx8qm_acm_clk_driver = { + .driver = { + .name = "imx8qm-acm", + .of_match_table = imx8qm_acm_match, + .pm = &imx8qm_acm_pm_ops, + .suppress_bind_attrs = true, + }, + .probe = imx8qm_acm_clk_probe, + .remove = imx8qm_acm_clk_remove, +}; + +static int __init imx8qm_acm_init(void) +{ + return platform_driver_register(&imx8qm_acm_clk_driver); +} +fs_initcall(imx8qm_acm_init); diff --git a/drivers/clk/imx/clk-imx8qm-rsrc.c b/drivers/clk/imx/clk-imx8qm-rsrc.c new file mode 100644 index 00000000000000..3f683f765e1316 --- /dev/null +++ b/drivers/clk/imx/clk-imx8qm-rsrc.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +#include + +#include "clk-scu.h" + +/* Keep sorted in the ascending order */ +static u32 imx8qm_clk_scu_rsrc_table[] = { + IMX_SC_R_A53, + IMX_SC_R_A72, + IMX_SC_R_DC_0_VIDEO0, + IMX_SC_R_DC_0_VIDEO1, + IMX_SC_R_DC_0, + IMX_SC_R_DC_0_PLL_0, + IMX_SC_R_DC_0_PLL_1, + IMX_SC_R_DC_1_VIDEO0, + IMX_SC_R_DC_1_VIDEO1, + IMX_SC_R_DC_1, + IMX_SC_R_DC_1_PLL_0, + IMX_SC_R_DC_1_PLL_1, + IMX_SC_R_SPI_0, + IMX_SC_R_SPI_1, + IMX_SC_R_SPI_2, + IMX_SC_R_SPI_3, + IMX_SC_R_UART_0, + IMX_SC_R_UART_1, + IMX_SC_R_UART_2, + IMX_SC_R_UART_3, + IMX_SC_R_UART_4, + IMX_SC_R_EMVSIM_0, + IMX_SC_R_EMVSIM_1, + IMX_SC_R_I2C_0, + IMX_SC_R_I2C_1, + IMX_SC_R_I2C_2, + IMX_SC_R_I2C_3, + IMX_SC_R_I2C_4, + IMX_SC_R_ADC_0, + IMX_SC_R_ADC_1, + IMX_SC_R_FTM_0, + IMX_SC_R_FTM_1, + IMX_SC_R_CAN_0, + IMX_SC_R_CAN_1, + IMX_SC_R_CAN_2, + IMX_SC_R_GPU_0_PID0, + IMX_SC_R_GPU_1_PID0, + IMX_SC_R_PWM_0, + IMX_SC_R_PWM_1, + IMX_SC_R_PWM_2, + IMX_SC_R_PWM_3, + IMX_SC_R_PWM_4, + IMX_SC_R_PWM_5, + IMX_SC_R_PWM_6, + IMX_SC_R_PWM_7, + IMX_SC_R_GPT_0, + IMX_SC_R_GPT_1, + IMX_SC_R_GPT_2, + IMX_SC_R_GPT_3, + IMX_SC_R_GPT_4, + IMX_SC_R_FSPI_0, + IMX_SC_R_FSPI_1, + IMX_SC_R_SDHC_0, + IMX_SC_R_SDHC_1, + IMX_SC_R_SDHC_2, + IMX_SC_R_ENET_0, + IMX_SC_R_ENET_1, + IMX_SC_R_MLB_0, + IMX_SC_R_USB_2, + IMX_SC_R_NAND, + IMX_SC_R_LVDS_0, + IMX_SC_R_LVDS_0_PWM_0, + IMX_SC_R_LVDS_0_I2C_0, + IMX_SC_R_LVDS_0_I2C_1, + IMX_SC_R_LVDS_1, + IMX_SC_R_LVDS_1_PWM_0, + IMX_SC_R_LVDS_1_I2C_0, + IMX_SC_R_LVDS_1_I2C_1, + IMX_SC_R_M4_0_I2C, + IMX_SC_R_M4_1_I2C, + IMX_SC_R_AUDIO_PLL_0, + IMX_SC_R_VPU_UART, + IMX_SC_R_VPUCORE, + IMX_SC_R_MIPI_0, + IMX_SC_R_MIPI_0_PWM_0, + IMX_SC_R_MIPI_0_I2C_0, + IMX_SC_R_MIPI_0_I2C_1, + IMX_SC_R_MIPI_1, + IMX_SC_R_MIPI_1_PWM_0, + IMX_SC_R_MIPI_1_I2C_0, + IMX_SC_R_MIPI_1_I2C_1, + IMX_SC_R_CSI_0, + IMX_SC_R_CSI_0_PWM_0, + IMX_SC_R_CSI_0_I2C_0, + IMX_SC_R_CSI_1, + IMX_SC_R_CSI_1_PWM_0, + IMX_SC_R_CSI_1_I2C_0, + IMX_SC_R_HDMI, + IMX_SC_R_HDMI_I2S, + IMX_SC_R_HDMI_I2C_0, + IMX_SC_R_HDMI_PLL_0, + IMX_SC_R_HDMI_RX, + IMX_SC_R_HDMI_RX_BYPASS, + IMX_SC_R_HDMI_RX_I2C_0, + IMX_SC_R_AUDIO_PLL_1, + IMX_SC_R_AUDIO_CLK_0, + IMX_SC_R_AUDIO_CLK_1, + IMX_SC_R_HDMI_RX_PWM_0, + IMX_SC_R_HDMI_PLL_1, + IMX_SC_R_VPU, +}; + +const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm = { + .rsrc = imx8qm_clk_scu_rsrc_table, + .num = ARRAY_SIZE(imx8qm_clk_scu_rsrc_table), +}; diff --git a/drivers/clk/imx/clk-imx8qxp-acm.c b/drivers/clk/imx/clk-imx8qxp-acm.c new file mode 100644 index 00000000000000..2e94e419a129f3 --- /dev/null +++ b/drivers/clk/imx/clk-imx8qxp-acm.c @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" +#include "clk-scu.h" +#include "clk-imx-acm-utils.h" + +#include + +struct imx8qxp_acm_priv { + struct clk_imx_acm_pm_domains dev_pm; + void __iomem *reg; + u32 regs[0x20]; +}; + +static const char *aud_clk_sels[] = { + "aud_rec_clk0_lpcg_clk", + "aud_rec_clk1_lpcg_clk", + "ext_aud_mclk0", + "ext_aud_mclk1", + "esai0_rx_clk", + "esai0_rx_hf_clk", + "esai0_tx_clk", + "esai0_tx_hf_clk", + "spdif0_rx", + "sai0_rx_bclk", + "sai0_tx_bclk", + "sai1_rx_bclk", + "sai1_tx_bclk", + "sai2_rx_bclk", + "sai3_rx_bclk", +}; + +static const char *mclk_out_sels[] = { + "aud_rec_clk0_lpcg_clk", + "aud_rec_clk1_lpcg_clk", + "dummy", + "dummy", + "spdif0_rx", + "dummy", + "dummy", + "sai4_rx_bclk", +}; + +static const char *sai_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static const char *esai_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static const char *spdif_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static const char *mqs_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static int imx8qxp_acm_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct clk_onecell_data *clk_data; + struct imx8qxp_acm_priv *priv; + struct resource *res; + struct clk **clks; + void __iomem *base; + int ret; + int i; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap(dev, res->start, resource_size(res)); + if (!base) + return -ENOMEM; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->reg = base; + + platform_set_drvdata(pdev, priv); + + clk_data = devm_kzalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + clk_data->clks = devm_kcalloc(&pdev->dev, IMX_ADMA_ACM_CLK_END, + sizeof(*clk_data->clks), GFP_KERNEL); + if (!clk_data->clks) + return -ENOMEM; + + clk_data->clk_num = IMX_ADMA_ACM_CLK_END; + + clks = clk_data->clks; + + ret = clk_imx_acm_attach_pm_domains(&pdev->dev, &priv->dev_pm); + if (ret) + return ret; + + pm_runtime_enable(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + + clks[IMX_ADMA_EXT_AUD_MCLK0] = imx_clk_fixed("ext_aud_mclk0", 0); + clks[IMX_ADMA_EXT_AUD_MCLK1] = imx_clk_fixed("ext_aud_mclk1", 0); + clks[IMX_ADMA_ESAI0_RX_CLK] = imx_clk_fixed("esai0_rx_clk", 0); + clks[IMX_ADMA_ESAI0_RX_HF_CLK] = imx_clk_fixed("esai0_rx_hf_clk", 0); + clks[IMX_ADMA_ESAI0_TX_CLK] = imx_clk_fixed("esai0_tx_clk", 0); + clks[IMX_ADMA_ESAI0_TX_HF_CLK] = imx_clk_fixed("esai0_tx_hf_clk", 0); + clks[IMX_ADMA_SPDIF0_RX] = imx_clk_fixed("spdif0_rx", 0); + clks[IMX_ADMA_SAI0_RX_BCLK] = imx_clk_fixed("sai0_rx_bclk", 0); + clks[IMX_ADMA_SAI0_TX_BCLK] = imx_clk_fixed("sai0_tx_bclk", 0); + clks[IMX_ADMA_SAI1_RX_BCLK] = imx_clk_fixed("sai1_rx_bclk", 0); + clks[IMX_ADMA_SAI1_TX_BCLK] = imx_clk_fixed("sai1_tx_bclk", 0); + clks[IMX_ADMA_SAI2_RX_BCLK] = imx_clk_fixed("sai2_rx_bclk", 0); + clks[IMX_ADMA_SAI3_RX_BCLK] = imx_clk_fixed("sai3_rx_bclk", 0); + clks[IMX_ADMA_SAI4_RX_BCLK] = imx_clk_fixed("sai4_rx_bclk", 0); + + + clks[IMX_ADMA_ACM_AUD_CLK0_SEL] = imx_dev_clk_mux(dev, "acm_aud_clk0_sel", base+0x000000, 0, 5, aud_clk_sels, ARRAY_SIZE(aud_clk_sels)); + clks[IMX_ADMA_ACM_AUD_CLK1_CLK] = imx_dev_clk_mux(dev, "acm_aud_clk1_sel", base+0x010000, 0, 5, aud_clk_sels, ARRAY_SIZE(aud_clk_sels)); + + clks[IMX_ADMA_ACM_MCLKOUT0_SEL] = imx_dev_clk_mux(dev, "acm_mclkout0_sel", base+0x020000, 0, 3, mclk_out_sels, ARRAY_SIZE(mclk_out_sels)); + clks[IMX_ADMA_ACM_MCLKOUT1_SEL] = imx_dev_clk_mux(dev, "acm_mclkout1_sel", base+0x030000, 0, 3, mclk_out_sels, ARRAY_SIZE(mclk_out_sels)); + + clks[IMX_ADMA_ACM_ESAI0_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_esai0_mclk_sel", base+0x060000, 0, 2, esai_mclk_sels, ARRAY_SIZE(esai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI0_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai0_mclk_sel", base+0x0E0000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI1_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai1_mclk_sel", base+0x0F0000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI2_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai2_mclk_sel", base+0x100000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI3_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai3_mclk_sel", base+0x110000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI4_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai4_mclk_sel", base+0x140000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI5_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai5_mclk_sel", base+0x150000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + + clks[IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL] = imx_dev_clk_mux(dev, "acm_spdif0_mclk_sel", base+0x1A0000, 0, 2, spdif_mclk_sels, ARRAY_SIZE(spdif_mclk_sels)); + clks[IMX_ADMA_ACM_MQS_TX_CLK_SEL] = imx_dev_clk_mux(dev, "acm_mqs_mclk_sel", base+0x1C0000, 0, 2, mqs_mclk_sels, ARRAY_SIZE(mqs_mclk_sels)); + + for (i = 0; i < clk_data->clk_num; i++) { + if (IS_ERR(clks[i])) + pr_warn("i.MX clk %u: register failed with %ld\n", + i, PTR_ERR(clks[i])); + } + + ret = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); + + pm_runtime_put_sync(&pdev->dev); + + return ret; +} + +static int imx8qxp_acm_clk_remove(struct platform_device *pdev) +{ + struct imx8qxp_acm_priv *priv = dev_get_drvdata(&pdev->dev); + + pm_runtime_disable(&pdev->dev); + + clk_imx_acm_detach_pm_domains(&pdev->dev, &priv->dev_pm); + + return 0; +} + +static const struct of_device_id imx8qxp_acm_match[] = { + { .compatible = "nxp,imx8qxp-acm", }, + { /* sentinel */ } +}; + +static int __maybe_unused imx8qxp_acm_runtime_suspend(struct device *dev) +{ + struct imx8qxp_acm_priv *priv = dev_get_drvdata(dev); + + priv->regs[0] = readl_relaxed(priv->reg + 0x000000); + priv->regs[1] = readl_relaxed(priv->reg + 0x010000); + priv->regs[2] = readl_relaxed(priv->reg + 0x020000); + priv->regs[3] = readl_relaxed(priv->reg + 0x030000); + priv->regs[6] = readl_relaxed(priv->reg + 0x060000); + priv->regs[14] = readl_relaxed(priv->reg + 0x0E0000); + priv->regs[15] = readl_relaxed(priv->reg + 0x0F0000); + priv->regs[16] = readl_relaxed(priv->reg + 0x100000); + priv->regs[17] = readl_relaxed(priv->reg + 0x110000); + priv->regs[20] = readl_relaxed(priv->reg + 0x140000); + priv->regs[21] = readl_relaxed(priv->reg + 0x150000); + priv->regs[26] = readl_relaxed(priv->reg + 0x1A0000); + priv->regs[28] = readl_relaxed(priv->reg + 0x1C0000); + + return 0; +} + +static int __maybe_unused imx8qxp_acm_runtime_resume(struct device *dev) +{ + struct imx8qxp_acm_priv *priv = dev_get_drvdata(dev); + + writel_relaxed(priv->regs[0], priv->reg + 0x000000); + writel_relaxed(priv->regs[1], priv->reg + 0x010000); + writel_relaxed(priv->regs[2], priv->reg + 0x020000); + writel_relaxed(priv->regs[3], priv->reg + 0x030000); + writel_relaxed(priv->regs[6], priv->reg + 0x060000); + writel_relaxed(priv->regs[14], priv->reg + 0x0E0000); + writel_relaxed(priv->regs[15], priv->reg + 0x0F0000); + writel_relaxed(priv->regs[16], priv->reg + 0x100000); + writel_relaxed(priv->regs[17], priv->reg + 0x110000); + writel_relaxed(priv->regs[20], priv->reg + 0x140000); + writel_relaxed(priv->regs[21], priv->reg + 0x150000); + writel_relaxed(priv->regs[26], priv->reg + 0x1A0000); + writel_relaxed(priv->regs[28], priv->reg + 0x1C0000); + + return 0; +} + +const struct dev_pm_ops imx8qxp_acm_pm_ops = { + SET_RUNTIME_PM_OPS(imx8qxp_acm_runtime_suspend, + imx8qxp_acm_runtime_resume, NULL) + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + +static struct platform_driver imx8qxp_acm_clk_driver = { + .driver = { + .name = "imx8qxp-acm", + .of_match_table = imx8qxp_acm_match, + .pm = &imx8qxp_acm_pm_ops, + .suppress_bind_attrs = true, + }, + .probe = imx8qxp_acm_clk_probe, + .remove = imx8qxp_acm_clk_remove, +}; + +static int __init imx8qxp_acm_init(void) +{ + return platform_driver_register(&imx8qxp_acm_clk_driver); +} +fs_initcall(imx8qxp_acm_init); diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c b/drivers/clk/imx/clk-imx8qxp-lpcg.c index c0aff7ca6374c9..741b73e4c6091a 100644 --- a/drivers/clk/imx/clk-imx8qxp-lpcg.c +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c @@ -9,205 +9,106 @@ #include #include #include +#include #include #include +#include #include #include "clk-scu.h" -#include "clk-imx8qxp-lpcg.h" -#include - -/* - * struct imx8qxp_lpcg_data - Description of one LPCG clock - * @id: clock ID - * @name: clock name - * @parent: parent clock name - * @flags: common clock flags - * @offset: offset of this LPCG clock - * @bit_idx: bit index of this LPCG clock - * @hw_gate: whether supports HW autogate - * - * This structure describes one LPCG clock - */ -struct imx8qxp_lpcg_data { - int id; - char *name; - char *parent; - unsigned long flags; - u32 offset; - u8 bit_idx; - bool hw_gate; -}; - -/* - * struct imx8qxp_ss_lpcg - Description of one subsystem LPCG clocks - * @lpcg: LPCG clocks array of one subsystem - * @num_lpcg: the number of LPCG clocks - * @num_max: the maximum number of LPCG clocks - * - * This structure describes each subsystem LPCG clocks information - * which then will be used to create respective LPCGs clocks - */ -struct imx8qxp_ss_lpcg { - const struct imx8qxp_lpcg_data *lpcg; - u8 num_lpcg; - u8 num_max; -}; - -static const struct imx8qxp_lpcg_data imx8qxp_lpcg_adma[] = { - { IMX_ADMA_LPCG_UART0_IPG_CLK, "uart0_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_0_LPCG, 16, 0, }, - { IMX_ADMA_LPCG_UART0_BAUD_CLK, "uart0_lpcg_baud_clk", "uart0_clk", 0, ADMA_LPUART_0_LPCG, 0, 0, }, - { IMX_ADMA_LPCG_UART1_IPG_CLK, "uart1_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_1_LPCG, 16, 0, }, - { IMX_ADMA_LPCG_UART1_BAUD_CLK, "uart1_lpcg_baud_clk", "uart1_clk", 0, ADMA_LPUART_1_LPCG, 0, 0, }, - { IMX_ADMA_LPCG_UART2_IPG_CLK, "uart2_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_2_LPCG, 16, 0, }, - { IMX_ADMA_LPCG_UART2_BAUD_CLK, "uart2_lpcg_baud_clk", "uart2_clk", 0, ADMA_LPUART_2_LPCG, 0, 0, }, - { IMX_ADMA_LPCG_UART3_IPG_CLK, "uart3_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_3_LPCG, 16, 0, }, - { IMX_ADMA_LPCG_UART3_BAUD_CLK, "uart3_lpcg_baud_clk", "uart3_clk", 0, ADMA_LPUART_3_LPCG, 0, 0, }, - { IMX_ADMA_LPCG_I2C0_IPG_CLK, "i2c0_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_0_LPCG, 16, 0, }, - { IMX_ADMA_LPCG_I2C0_CLK, "i2c0_lpcg_clk", "i2c0_clk", 0, ADMA_LPI2C_0_LPCG, 0, 0, }, - { IMX_ADMA_LPCG_I2C1_IPG_CLK, "i2c1_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_1_LPCG, 16, 0, }, - { IMX_ADMA_LPCG_I2C1_CLK, "i2c1_lpcg_clk", "i2c1_clk", 0, ADMA_LPI2C_1_LPCG, 0, 0, }, - { IMX_ADMA_LPCG_I2C2_IPG_CLK, "i2c2_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_2_LPCG, 16, 0, }, - { IMX_ADMA_LPCG_I2C2_CLK, "i2c2_lpcg_clk", "i2c2_clk", 0, ADMA_LPI2C_2_LPCG, 0, 0, }, - { IMX_ADMA_LPCG_I2C3_IPG_CLK, "i2c3_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_3_LPCG, 16, 0, }, - { IMX_ADMA_LPCG_I2C3_CLK, "i2c3_lpcg_clk", "i2c3_clk", 0, ADMA_LPI2C_3_LPCG, 0, 0, }, - - { IMX_ADMA_LPCG_DSP_CORE_CLK, "dsp_lpcg_core_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 28, 0, }, - { IMX_ADMA_LPCG_DSP_IPG_CLK, "dsp_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 20, 0, }, - { IMX_ADMA_LPCG_DSP_ADB_CLK, "dsp_lpcg_adb_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 16, 0, }, - { IMX_ADMA_LPCG_OCRAM_IPG_CLK, "ocram_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_OCRAM_LPCG, 16, 0, }, -}; - -static const struct imx8qxp_ss_lpcg imx8qxp_ss_adma = { - .lpcg = imx8qxp_lpcg_adma, - .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_adma), - .num_max = IMX_ADMA_LPCG_CLK_END, -}; - -static const struct imx8qxp_lpcg_data imx8qxp_lpcg_conn[] = { - { IMX_CONN_LPCG_SDHC0_PER_CLK, "sdhc0_lpcg_per_clk", "sdhc0_clk", 0, CONN_USDHC_0_LPCG, 0, 0, }, - { IMX_CONN_LPCG_SDHC0_IPG_CLK, "sdhc0_lpcg_ipg_clk", "conn_ipg_clk_root", 0, CONN_USDHC_0_LPCG, 16, 0, }, - { IMX_CONN_LPCG_SDHC0_HCLK, "sdhc0_lpcg_ahb_clk", "conn_axi_clk_root", 0, CONN_USDHC_0_LPCG, 20, 0, }, - { IMX_CONN_LPCG_SDHC1_PER_CLK, "sdhc1_lpcg_per_clk", "sdhc1_clk", 0, CONN_USDHC_1_LPCG, 0, 0, }, - { IMX_CONN_LPCG_SDHC1_IPG_CLK, "sdhc1_lpcg_ipg_clk", "conn_ipg_clk_root", 0, CONN_USDHC_1_LPCG, 16, 0, }, - { IMX_CONN_LPCG_SDHC1_HCLK, "sdhc1_lpcg_ahb_clk", "conn_axi_clk_root", 0, CONN_USDHC_1_LPCG, 20, 0, }, - { IMX_CONN_LPCG_SDHC2_PER_CLK, "sdhc2_lpcg_per_clk", "sdhc2_clk", 0, CONN_USDHC_2_LPCG, 0, 0, }, - { IMX_CONN_LPCG_SDHC2_IPG_CLK, "sdhc2_lpcg_ipg_clk", "conn_ipg_clk_root", 0, CONN_USDHC_2_LPCG, 16, 0, }, - { IMX_CONN_LPCG_SDHC2_HCLK, "sdhc2_lpcg_ahb_clk", "conn_axi_clk_root", 0, CONN_USDHC_2_LPCG, 20, 0, }, - { IMX_CONN_LPCG_ENET0_ROOT_CLK, "enet0_ipg_root_clk", "enet0_clk", 0, CONN_ENET_0_LPCG, 0, 0, }, - { IMX_CONN_LPCG_ENET0_TX_CLK, "enet0_tx_clk", "enet0_clk", 0, CONN_ENET_0_LPCG, 4, 0, }, - { IMX_CONN_LPCG_ENET0_AHB_CLK, "enet0_ahb_clk", "conn_axi_clk_root", 0, CONN_ENET_0_LPCG, 8, 0, }, - { IMX_CONN_LPCG_ENET0_IPG_S_CLK, "enet0_ipg_s_clk", "conn_ipg_clk_root", 0, CONN_ENET_0_LPCG, 20, 0, }, - { IMX_CONN_LPCG_ENET0_IPG_CLK, "enet0_ipg_clk", "enet0_ipg_s_clk", 0, CONN_ENET_0_LPCG, 16, 0, }, - { IMX_CONN_LPCG_ENET1_ROOT_CLK, "enet1_ipg_root_clk", "enet1_clk", 0, CONN_ENET_1_LPCG, 0, 0, }, - { IMX_CONN_LPCG_ENET1_TX_CLK, "enet1_tx_clk", "enet1_clk", 0, CONN_ENET_1_LPCG, 4, 0, }, - { IMX_CONN_LPCG_ENET1_AHB_CLK, "enet1_ahb_clk", "conn_axi_clk_root", 0, CONN_ENET_1_LPCG, 8, 0, }, - { IMX_CONN_LPCG_ENET1_IPG_S_CLK, "enet1_ipg_s_clk", "conn_ipg_clk_root", 0, CONN_ENET_1_LPCG, 20, 0, }, - { IMX_CONN_LPCG_ENET1_IPG_CLK, "enet1_ipg_clk", "enet0_ipg_s_clk", 0, CONN_ENET_1_LPCG, 16, 0, }, -}; - -static const struct imx8qxp_ss_lpcg imx8qxp_ss_conn = { - .lpcg = imx8qxp_lpcg_conn, - .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_conn), - .num_max = IMX_CONN_LPCG_CLK_END, -}; - -static const struct imx8qxp_lpcg_data imx8qxp_lpcg_lsio[] = { - { IMX_LSIO_LPCG_PWM0_IPG_CLK, "pwm0_lpcg_ipg_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 0, 0, }, - { IMX_LSIO_LPCG_PWM0_IPG_HF_CLK, "pwm0_lpcg_ipg_hf_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 4, 0, }, - { IMX_LSIO_LPCG_PWM0_IPG_S_CLK, "pwm0_lpcg_ipg_s_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 16, 0, }, - { IMX_LSIO_LPCG_PWM0_IPG_SLV_CLK, "pwm0_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_0_LPCG, 20, 0, }, - { IMX_LSIO_LPCG_PWM0_IPG_MSTR_CLK, "pwm0_lpcg_ipg_mstr_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 24, 0, }, - { IMX_LSIO_LPCG_PWM1_IPG_CLK, "pwm1_lpcg_ipg_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 0, 0, }, - { IMX_LSIO_LPCG_PWM1_IPG_HF_CLK, "pwm1_lpcg_ipg_hf_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 4, 0, }, - { IMX_LSIO_LPCG_PWM1_IPG_S_CLK, "pwm1_lpcg_ipg_s_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 16, 0, }, - { IMX_LSIO_LPCG_PWM1_IPG_SLV_CLK, "pwm1_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_1_LPCG, 20, 0, }, - { IMX_LSIO_LPCG_PWM1_IPG_MSTR_CLK, "pwm1_lpcg_ipg_mstr_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 24, 0, }, - { IMX_LSIO_LPCG_PWM2_IPG_CLK, "pwm2_lpcg_ipg_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 0, 0, }, - { IMX_LSIO_LPCG_PWM2_IPG_HF_CLK, "pwm2_lpcg_ipg_hf_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 4, 0, }, - { IMX_LSIO_LPCG_PWM2_IPG_S_CLK, "pwm2_lpcg_ipg_s_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 16, 0, }, - { IMX_LSIO_LPCG_PWM2_IPG_SLV_CLK, "pwm2_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_2_LPCG, 20, 0, }, - { IMX_LSIO_LPCG_PWM2_IPG_MSTR_CLK, "pwm2_lpcg_ipg_mstr_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 24, 0, }, - { IMX_LSIO_LPCG_PWM3_IPG_CLK, "pwm3_lpcg_ipg_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 0, 0, }, - { IMX_LSIO_LPCG_PWM3_IPG_HF_CLK, "pwm3_lpcg_ipg_hf_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 4, 0, }, - { IMX_LSIO_LPCG_PWM3_IPG_S_CLK, "pwm3_lpcg_ipg_s_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 16, 0, }, - { IMX_LSIO_LPCG_PWM3_IPG_SLV_CLK, "pwm3_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_3_LPCG, 20, 0, }, - { IMX_LSIO_LPCG_PWM3_IPG_MSTR_CLK, "pwm3_lpcg_ipg_mstr_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 24, 0, }, - { IMX_LSIO_LPCG_PWM4_IPG_CLK, "pwm4_lpcg_ipg_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 0, 0, }, - { IMX_LSIO_LPCG_PWM4_IPG_HF_CLK, "pwm4_lpcg_ipg_hf_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 4, 0, }, - { IMX_LSIO_LPCG_PWM4_IPG_S_CLK, "pwm4_lpcg_ipg_s_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 16, 0, }, - { IMX_LSIO_LPCG_PWM4_IPG_SLV_CLK, "pwm4_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_4_LPCG, 20, 0, }, - { IMX_LSIO_LPCG_PWM4_IPG_MSTR_CLK, "pwm4_lpcg_ipg_mstr_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 24, 0, }, - { IMX_LSIO_LPCG_PWM5_IPG_CLK, "pwm5_lpcg_ipg_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 0, 0, }, - { IMX_LSIO_LPCG_PWM5_IPG_HF_CLK, "pwm5_lpcg_ipg_hf_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 4, 0, }, - { IMX_LSIO_LPCG_PWM5_IPG_S_CLK, "pwm5_lpcg_ipg_s_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 16, 0, }, - { IMX_LSIO_LPCG_PWM5_IPG_SLV_CLK, "pwm5_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_5_LPCG, 20, 0, }, - { IMX_LSIO_LPCG_PWM5_IPG_MSTR_CLK, "pwm5_lpcg_ipg_mstr_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 24, 0, }, - { IMX_LSIO_LPCG_PWM6_IPG_CLK, "pwm6_lpcg_ipg_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 0, 0, }, - { IMX_LSIO_LPCG_PWM6_IPG_HF_CLK, "pwm6_lpcg_ipg_hf_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 4, 0, }, - { IMX_LSIO_LPCG_PWM6_IPG_S_CLK, "pwm6_lpcg_ipg_s_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 16, 0, }, - { IMX_LSIO_LPCG_PWM6_IPG_SLV_CLK, "pwm6_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_6_LPCG, 20, 0, }, - { IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK, "pwm6_lpcg_ipg_mstr_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 24, 0, }, -}; - -static const struct imx8qxp_ss_lpcg imx8qxp_ss_lsio = { - .lpcg = imx8qxp_lpcg_lsio, - .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_lsio), - .num_max = IMX_LSIO_LPCG_CLK_END, -}; +#define IMX_LPCG_MAX_CLKS 8 static int imx8qxp_lpcg_clk_probe(struct platform_device *pdev) { - struct device *dev = &pdev->dev; - struct device_node *np = dev->of_node; + struct device_node *np = pdev->dev.of_node; + const char *output_names[IMX_LPCG_MAX_CLKS]; + const char *parent_names[IMX_LPCG_MAX_CLKS]; + unsigned int bit_offset[IMX_LPCG_MAX_CLKS]; struct clk_hw_onecell_data *clk_data; - const struct imx8qxp_ss_lpcg *ss_lpcg; - const struct imx8qxp_lpcg_data *lpcg; + struct clk_hw **clk_hws; struct resource *res; - struct clk_hw **clks; void __iomem *base; + bool autogate; + int count; + int ret; int i; - ss_lpcg = of_device_get_match_data(dev); - if (!ss_lpcg) - return -ENODEV; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + count = of_property_count_u32_elems(np, "bit-offset"); + if (count < 0) { + dev_err(&pdev->dev, "failed to count clocks\n"); return -EINVAL; - base = devm_ioremap(dev, res->start, resource_size(res)); - if (!base) - return -ENOMEM; + } - clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws, - ss_lpcg->num_max), GFP_KERNEL); + clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws, count), + GFP_KERNEL); if (!clk_data) return -ENOMEM; - clk_data->num = ss_lpcg->num_max; - clks = clk_data->hws; + clk_data->num = count; + clk_hws = clk_data->hws; - for (i = 0; i < ss_lpcg->num_lpcg; i++) { - lpcg = ss_lpcg->lpcg + i; - clks[lpcg->id] = imx_clk_lpcg_scu(lpcg->name, lpcg->parent, - lpcg->flags, base + lpcg->offset, - lpcg->bit_idx, lpcg->hw_gate); + ret = of_property_read_u32_array(np, "bit-offset", bit_offset, + clk_data->num); + if (ret < 0) { + dev_err(&pdev->dev, "failed to read clocks bit-offset\n"); + return -EINVAL; } + ret = of_clk_parent_fill(np, parent_names, clk_data->num); + if (ret != clk_data->num) { + dev_err(&pdev->dev, "failed to get clock parent names\n"); + return -EINVAL; + } + + ret = of_property_read_string_array(np, "clock-output-names", + output_names, clk_data->num); + if (ret != clk_data->num) { + dev_err(&pdev->dev, "failed to read clock-output-names\n"); + return -EINVAL; + } + + autogate = of_property_read_bool(np, "hw-autogate"); + + pm_runtime_get_noresume(&pdev->dev); + pm_runtime_set_active(&pdev->dev); + pm_runtime_set_autosuspend_delay(&pdev->dev, 500); + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_enable(&pdev->dev); + for (i = 0; i < clk_data->num; i++) { - if (IS_ERR(clks[i])) - pr_warn("i.MX clk %u: register failed with %ld\n", - i, PTR_ERR(clks[i])); + if (bit_offset[i] > 31) { + dev_warn(&pdev->dev, "invalid bit offset of clock %d\n", + i); + return -EINVAL; + } + + clk_hws[i] = imx_clk_lpcg_scu_dev(&pdev->dev, output_names[i], + parent_names[i], 0, base, + bit_offset[i], autogate); + if (IS_ERR(clk_hws[i])) { + dev_warn(&pdev->dev, "failed to register clock %d\n", + i); + return -EINVAL; + } } - return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); + ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, + clk_data); + + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_put_autosuspend(&pdev->dev); + + return ret; } static const struct of_device_id imx8qxp_lpcg_match[] = { - { .compatible = "fsl,imx8qxp-lpcg-adma", &imx8qxp_ss_adma, }, - { .compatible = "fsl,imx8qxp-lpcg-conn", &imx8qxp_ss_conn, }, - { .compatible = "fsl,imx8qxp-lpcg-lsio", &imx8qxp_ss_lsio, }, + { .compatible = "fsl,imx8qxp-lpcg", NULL }, { /* sentinel */ } }; @@ -215,6 +116,7 @@ static struct platform_driver imx8qxp_lpcg_clk_driver = { .driver = { .name = "imx8qxp-lpcg-clk", .of_match_table = imx8qxp_lpcg_match, + .pm = &imx_clk_lpcg_scu_pm_ops, .suppress_bind_attrs = true, }, .probe = imx8qxp_lpcg_clk_probe, diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.h b/drivers/clk/imx/clk-imx8qxp-lpcg.h index 2a37ce57c50083..d435cd5c5713b6 100644 --- a/drivers/clk/imx/clk-imx8qxp-lpcg.h +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.h @@ -99,4 +99,49 @@ #define ADMA_FLEXCAN_1_LPCG 0x1ce0000 #define ADMA_FLEXCAN_2_LPCG 0x1cf0000 +/* CM40 SS */ +#define CM40_I2C_LPCG 0x60000 + +/* HSIO SS */ +#define HSIO_PCIEA_LPCG 0x00000 +#define HSIO_PCIEB_LPCG 0x10000 +#define HSIO_SATA0_LPCG 0x20000 +#define HSIO_PHYX2_LPCG 0x30000 +#define HSIO_PHYX1_LPCG 0x40000 +#define HSIO_CRR_0_LPCG 0x50000 +#define HSIO_CRR_1_LPCG 0x60000 +#define HSIO_CRR_2_LPCG 0x70000 +#define HSIO_CRR_3_LPCG 0x80000 +#define HSIO_CRR_4_LPCG 0x90000 +#define HSIO_CRR_5_LPCG 0xa0000 +#define HSIO_GPIO_LPCG 0xb0000 + +/* IMG SS */ +#define IMG_PDMA0_LPCG 0x00000 +#define IMG_PDMA1_LPCG 0x10000 +#define IMG_PDMA2_LPCG 0x20000 +#define IMG_PDMA3_LPCG 0x30000 +#define IMG_PDMA4_LPCG 0x40000 +#define IMG_PDMA5_LPCG 0x50000 +#define IMG_PDMA6_LPCG 0x60000 +#define IMG_PDMA7_LPCG 0x70000 +#define IMG_MIPI_CSI0_LPCG 0x80000 +#define IMG_MIPI_CSI1_LPCG 0x90000 + +/* CSI SS */ +#define CSI_CSI0_CORE_LPCG 0x18 +#define CSI_CSI0_ESC_LPCG 0x1C +#define CSI_CSI0_I2C0_LPCG 0x14 +#define CSI_CSI1_CORE_LPCG 0x18 +#define CSI_CSI1_ESC_LPCG 0x1C +#define CSI_CSI1_I2C0_LPCG 0x14 + +/* Parallel Interface SS */ +#define PI_PI0_PIXEL_LPCG 0x18 +#define PI_PI0_IPG_LPCG 0x04 +#define PI_PI0_MISC_LPCG 0x1C + +/* DC0 SS */ +/* TODO: ADD DC LPCGs */ + #endif /* _IMX8QXP_LPCG_H */ diff --git a/drivers/clk/imx/clk-imx8qxp-rsrc.c b/drivers/clk/imx/clk-imx8qxp-rsrc.c new file mode 100644 index 00000000000000..cad85be3f87f13 --- /dev/null +++ b/drivers/clk/imx/clk-imx8qxp-rsrc.c @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +#include + +#include "clk-scu.h" + +/* Keep sorted in the ascending order */ +static u32 imx8qxp_clk_scu_rsrc_table[] = { + IMX_SC_R_DC_0_VIDEO0, + IMX_SC_R_DC_0_VIDEO1, + IMX_SC_R_DC_0, + IMX_SC_R_DC_0_PLL_0, + IMX_SC_R_DC_0_PLL_1, + IMX_SC_R_SPI_0, + IMX_SC_R_SPI_1, + IMX_SC_R_SPI_2, + IMX_SC_R_SPI_3, + IMX_SC_R_UART_0, + IMX_SC_R_UART_1, + IMX_SC_R_UART_2, + IMX_SC_R_UART_3, + IMX_SC_R_I2C_0, + IMX_SC_R_I2C_1, + IMX_SC_R_I2C_2, + IMX_SC_R_I2C_3, + IMX_SC_R_ADC_0, + IMX_SC_R_FTM_0, + IMX_SC_R_FTM_1, + IMX_SC_R_CAN_0, + IMX_SC_R_GPU_0_PID0, + IMX_SC_R_LCD_0, + IMX_SC_R_LCD_0_PWM_0, + IMX_SC_R_PWM_0, + IMX_SC_R_PWM_1, + IMX_SC_R_PWM_2, + IMX_SC_R_PWM_3, + IMX_SC_R_PWM_4, + IMX_SC_R_PWM_5, + IMX_SC_R_PWM_6, + IMX_SC_R_PWM_7, + IMX_SC_R_GPT_0, + IMX_SC_R_GPT_1, + IMX_SC_R_GPT_2, + IMX_SC_R_GPT_3, + IMX_SC_R_GPT_4, + IMX_SC_R_FSPI_0, + IMX_SC_R_FSPI_1, + IMX_SC_R_SDHC_0, + IMX_SC_R_SDHC_1, + IMX_SC_R_SDHC_2, + IMX_SC_R_ENET_0, + IMX_SC_R_ENET_1, + IMX_SC_R_MLB_0, + IMX_SC_R_USB_2, + IMX_SC_R_NAND, + IMX_SC_R_LVDS_0, + IMX_SC_R_LVDS_1, + IMX_SC_R_M4_0_I2C, + IMX_SC_R_ELCDIF_PLL, + IMX_SC_R_AUDIO_PLL_0, + IMX_SC_R_PI_0, + IMX_SC_R_PI_0_PWM_0, + IMX_SC_R_PI_0_I2C_0, + IMX_SC_R_PI_0_PLL, + IMX_SC_R_MIPI_0, + IMX_SC_R_MIPI_0_PWM_0, + IMX_SC_R_MIPI_0_I2C_0, + IMX_SC_R_MIPI_0_I2C_1, + IMX_SC_R_MIPI_1, + IMX_SC_R_MIPI_1_PWM_0, + IMX_SC_R_MIPI_1_I2C_0, + IMX_SC_R_MIPI_1_I2C_1, + IMX_SC_R_CSI_0, + IMX_SC_R_CSI_0_PWM_0, + IMX_SC_R_CSI_0_I2C_0, + IMX_SC_R_AUDIO_PLL_1, + IMX_SC_R_AUDIO_CLK_0, + IMX_SC_R_AUDIO_CLK_1, + IMX_SC_R_A35, + IMX_SC_R_VPU_DEC_0, + IMX_SC_R_VPU_ENC_0, +}; + +const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp = { + .rsrc = imx8qxp_clk_scu_rsrc_table, + .num = ARRAY_SIZE(imx8qxp_clk_scu_rsrc_table), +}; diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index 5e2903efc4881c..6e8afaa9d22904 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -9,139 +9,263 @@ #include #include #include +#include #include #include +#include + #include "clk-scu.h" -#include -#include +static const char *pll0_sels[] = { + "clk_dummy", + "pi_dpll_clk", + "clk_dummy", + "clk_dummy", + "clk_dummy", +}; + +static const char *enet0_rgmii_txc_sels[] = { + "enet0_ref_div", + "clk_dummy", +}; + +static const char *enet1_rgmii_txc_sels[] __maybe_unused = { + "enet1_ref_div", + "clk_dummy", +}; + +static const char *dc0_sels[] = { + "clk_dummy", + "clk_dummy", + "dc0_pll0_clk", + "dc0_pll1_clk", + "dc0_bypass0_clk", +}; + +static const char *dc1_sels[] = { + "clk_dummy", + "clk_dummy", + "dc1_pll0_clk", + "dc1_pll1_clk", + "dc1_bypass0_clk", +}; + +static const char *hdmi_sels[] = { + "clk_dummy", + "hdmi_dig_pll_clk", + "clk_dummy", + "clk_dummy", + "hdmi_av_pll_clk", +}; + +static const char *lcd_pxl_sels[] = { + "dummy", + "dummy", + "dummy", + "dummy", + "lcd_pxl_bypass_div_clk", +}; + +static const char *mipi_sels[] = { + "clk_dummy", + "clk_dummy", + "mipi_pll_div2_clk", + "clk_dummy", + "clk_dummy", +}; + +static const struct of_device_id imx8qxp_match[] = { + { .compatible = "fsl,scu-clk", }, + { .compatible = "fsl,imx8qxp-clk", &imx_clk_scu_rsrc_imx8qxp, }, + { .compatible = "fsl,imx8qm-clk", &imx_clk_scu_rsrc_imx8qm, }, + { .compatible = "fsl,imx8dxl-clk", &imx_clk_scu_rsrc_imx8dxl, }, + { /* sentinel */ } +}; static int imx8qxp_clk_probe(struct platform_device *pdev) { + const struct of_device_id *of_id = + of_match_device(imx8qxp_match, &pdev->dev); struct device_node *ccm_node = pdev->dev.of_node; - struct clk_hw_onecell_data *clk_data; - struct clk_hw **clks; - int ret, i; + int ret; - ret = imx_clk_scu_init(); + ret = imx_clk_scu_init(ccm_node, of_id->data); if (ret) return ret; - clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws, - IMX_SCU_CLK_END), GFP_KERNEL); - if (!clk_data) - return -ENOMEM; - - clk_data->num = IMX_SCU_CLK_END; - clks = clk_data->hws; - - /* Fixed clocks */ - clks[IMX_CLK_DUMMY] = clk_hw_register_fixed_rate(NULL, "dummy", NULL, 0, 0); - clks[IMX_ADMA_IPG_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "dma_ipg_clk_root", NULL, 0, 120000000); - clks[IMX_CONN_AXI_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "conn_axi_clk_root", NULL, 0, 333333333); - clks[IMX_CONN_AHB_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "conn_ahb_clk_root", NULL, 0, 166666666); - clks[IMX_CONN_IPG_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "conn_ipg_clk_root", NULL, 0, 83333333); - clks[IMX_DC_AXI_EXT_CLK] = clk_hw_register_fixed_rate(NULL, "dc_axi_ext_clk_root", NULL, 0, 800000000); - clks[IMX_DC_AXI_INT_CLK] = clk_hw_register_fixed_rate(NULL, "dc_axi_int_clk_root", NULL, 0, 400000000); - clks[IMX_DC_CFG_CLK] = clk_hw_register_fixed_rate(NULL, "dc_cfg_clk_root", NULL, 0, 100000000); - clks[IMX_MIPI_IPG_CLK] = clk_hw_register_fixed_rate(NULL, "mipi_ipg_clk_root", NULL, 0, 120000000); - clks[IMX_IMG_AXI_CLK] = clk_hw_register_fixed_rate(NULL, "img_axi_clk_root", NULL, 0, 400000000); - clks[IMX_IMG_IPG_CLK] = clk_hw_register_fixed_rate(NULL, "img_ipg_clk_root", NULL, 0, 200000000); - clks[IMX_IMG_PXL_CLK] = clk_hw_register_fixed_rate(NULL, "img_pxl_clk_root", NULL, 0, 600000000); - clks[IMX_HSIO_AXI_CLK] = clk_hw_register_fixed_rate(NULL, "hsio_axi_clk_root", NULL, 0, 400000000); - clks[IMX_HSIO_PER_CLK] = clk_hw_register_fixed_rate(NULL, "hsio_per_clk_root", NULL, 0, 133333333); - clks[IMX_LSIO_MEM_CLK] = clk_hw_register_fixed_rate(NULL, "lsio_mem_clk_root", NULL, 0, 200000000); - clks[IMX_LSIO_BUS_CLK] = clk_hw_register_fixed_rate(NULL, "lsio_bus_clk_root", NULL, 0, 100000000); - /* ARM core */ - clks[IMX_A35_CLK] = imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU); + imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU); + imx_clk_scu("a53_clk", IMX_SC_R_A53, IMX_SC_PM_CLK_CPU); + imx_clk_scu("a72_clk", IMX_SC_R_A72, IMX_SC_PM_CLK_CPU); /* LSIO SS */ - clks[IMX_LSIO_PWM0_CLK] = imx_clk_scu("pwm0_clk", IMX_SC_R_PWM_0, IMX_SC_PM_CLK_PER); - clks[IMX_LSIO_PWM1_CLK] = imx_clk_scu("pwm1_clk", IMX_SC_R_PWM_1, IMX_SC_PM_CLK_PER); - clks[IMX_LSIO_PWM2_CLK] = imx_clk_scu("pwm2_clk", IMX_SC_R_PWM_2, IMX_SC_PM_CLK_PER); - clks[IMX_LSIO_PWM3_CLK] = imx_clk_scu("pwm3_clk", IMX_SC_R_PWM_3, IMX_SC_PM_CLK_PER); - clks[IMX_LSIO_PWM4_CLK] = imx_clk_scu("pwm4_clk", IMX_SC_R_PWM_4, IMX_SC_PM_CLK_PER); - clks[IMX_LSIO_PWM5_CLK] = imx_clk_scu("pwm5_clk", IMX_SC_R_PWM_5, IMX_SC_PM_CLK_PER); - clks[IMX_LSIO_PWM6_CLK] = imx_clk_scu("pwm6_clk", IMX_SC_R_PWM_6, IMX_SC_PM_CLK_PER); - clks[IMX_LSIO_PWM7_CLK] = imx_clk_scu("pwm7_clk", IMX_SC_R_PWM_7, IMX_SC_PM_CLK_PER); - clks[IMX_LSIO_GPT0_CLK] = imx_clk_scu("gpt0_clk", IMX_SC_R_GPT_0, IMX_SC_PM_CLK_PER); - clks[IMX_LSIO_GPT1_CLK] = imx_clk_scu("gpt1_clk", IMX_SC_R_GPT_1, IMX_SC_PM_CLK_PER); - clks[IMX_LSIO_GPT2_CLK] = imx_clk_scu("gpt2_clk", IMX_SC_R_GPT_2, IMX_SC_PM_CLK_PER); - clks[IMX_LSIO_GPT3_CLK] = imx_clk_scu("gpt3_clk", IMX_SC_R_GPT_3, IMX_SC_PM_CLK_PER); - clks[IMX_LSIO_GPT4_CLK] = imx_clk_scu("gpt4_clk", IMX_SC_R_GPT_4, IMX_SC_PM_CLK_PER); - clks[IMX_LSIO_FSPI0_CLK] = imx_clk_scu("fspi0_clk", IMX_SC_R_FSPI_0, IMX_SC_PM_CLK_PER); - clks[IMX_LSIO_FSPI1_CLK] = imx_clk_scu("fspi1_clk", IMX_SC_R_FSPI_1, IMX_SC_PM_CLK_PER); - - /* ADMA SS */ - clks[IMX_ADMA_UART0_CLK] = imx_clk_scu("uart0_clk", IMX_SC_R_UART_0, IMX_SC_PM_CLK_PER); - clks[IMX_ADMA_UART1_CLK] = imx_clk_scu("uart1_clk", IMX_SC_R_UART_1, IMX_SC_PM_CLK_PER); - clks[IMX_ADMA_UART2_CLK] = imx_clk_scu("uart2_clk", IMX_SC_R_UART_2, IMX_SC_PM_CLK_PER); - clks[IMX_ADMA_UART3_CLK] = imx_clk_scu("uart3_clk", IMX_SC_R_UART_3, IMX_SC_PM_CLK_PER); - clks[IMX_ADMA_SPI0_CLK] = imx_clk_scu("spi0_clk", IMX_SC_R_SPI_0, IMX_SC_PM_CLK_PER); - clks[IMX_ADMA_SPI1_CLK] = imx_clk_scu("spi1_clk", IMX_SC_R_SPI_1, IMX_SC_PM_CLK_PER); - clks[IMX_ADMA_SPI2_CLK] = imx_clk_scu("spi2_clk", IMX_SC_R_SPI_2, IMX_SC_PM_CLK_PER); - clks[IMX_ADMA_SPI3_CLK] = imx_clk_scu("spi3_clk", IMX_SC_R_SPI_3, IMX_SC_PM_CLK_PER); - clks[IMX_ADMA_CAN0_CLK] = imx_clk_scu("can0_clk", IMX_SC_R_CAN_0, IMX_SC_PM_CLK_PER); - clks[IMX_ADMA_I2C0_CLK] = imx_clk_scu("i2c0_clk", IMX_SC_R_I2C_0, IMX_SC_PM_CLK_PER); - clks[IMX_ADMA_I2C1_CLK] = imx_clk_scu("i2c1_clk", IMX_SC_R_I2C_1, IMX_SC_PM_CLK_PER); - clks[IMX_ADMA_I2C2_CLK] = imx_clk_scu("i2c2_clk", IMX_SC_R_I2C_2, IMX_SC_PM_CLK_PER); - clks[IMX_ADMA_I2C3_CLK] = imx_clk_scu("i2c3_clk", IMX_SC_R_I2C_3, IMX_SC_PM_CLK_PER); - clks[IMX_ADMA_FTM0_CLK] = imx_clk_scu("ftm0_clk", IMX_SC_R_FTM_0, IMX_SC_PM_CLK_PER); - clks[IMX_ADMA_FTM1_CLK] = imx_clk_scu("ftm1_clk", IMX_SC_R_FTM_1, IMX_SC_PM_CLK_PER); - clks[IMX_ADMA_ADC0_CLK] = imx_clk_scu("adc0_clk", IMX_SC_R_ADC_0, IMX_SC_PM_CLK_PER); - clks[IMX_ADMA_PWM_CLK] = imx_clk_scu("pwm_clk", IMX_SC_R_LCD_0_PWM_0, IMX_SC_PM_CLK_PER); - clks[IMX_ADMA_LCD_CLK] = imx_clk_scu("lcd_clk", IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("pwm0_clk", IMX_SC_R_PWM_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("pwm1_clk", IMX_SC_R_PWM_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("pwm2_clk", IMX_SC_R_PWM_2, IMX_SC_PM_CLK_PER); + imx_clk_scu("pwm3_clk", IMX_SC_R_PWM_3, IMX_SC_PM_CLK_PER); + imx_clk_scu("pwm4_clk", IMX_SC_R_PWM_4, IMX_SC_PM_CLK_PER); + imx_clk_scu("pwm5_clk", IMX_SC_R_PWM_5, IMX_SC_PM_CLK_PER); + imx_clk_scu("pwm6_clk", IMX_SC_R_PWM_6, IMX_SC_PM_CLK_PER); + imx_clk_scu("pwm7_clk", IMX_SC_R_PWM_7, IMX_SC_PM_CLK_PER); + imx_clk_scu("gpt1_clk", IMX_SC_R_GPT_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("gpt2_clk", IMX_SC_R_GPT_2, IMX_SC_PM_CLK_PER); + imx_clk_scu("gpt3_clk", IMX_SC_R_GPT_3, IMX_SC_PM_CLK_PER); + imx_clk_scu("gpt4_clk", IMX_SC_R_GPT_4, IMX_SC_PM_CLK_PER); + imx_clk_scu("fspi0_clk", IMX_SC_R_FSPI_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("fspi1_clk", IMX_SC_R_FSPI_1, IMX_SC_PM_CLK_PER); + + /* DMA SS */ + imx_clk_scu("uart0_clk", IMX_SC_R_UART_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("uart1_clk", IMX_SC_R_UART_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("uart2_clk", IMX_SC_R_UART_2, IMX_SC_PM_CLK_PER); + imx_clk_scu("uart3_clk", IMX_SC_R_UART_3, IMX_SC_PM_CLK_PER); + imx_clk_scu("uart4_clk", IMX_SC_R_UART_4, IMX_SC_PM_CLK_PER); + imx_clk_scu("sim0_clk", IMX_SC_R_EMVSIM_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("spi0_clk", IMX_SC_R_SPI_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("spi1_clk", IMX_SC_R_SPI_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("spi2_clk", IMX_SC_R_SPI_2, IMX_SC_PM_CLK_PER); + imx_clk_scu("spi3_clk", IMX_SC_R_SPI_3, IMX_SC_PM_CLK_PER); + imx_clk_scu("can0_clk", IMX_SC_R_CAN_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("can1_clk", IMX_SC_R_CAN_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("can2_clk", IMX_SC_R_CAN_2, IMX_SC_PM_CLK_PER); + imx_clk_scu("i2c0_clk", IMX_SC_R_I2C_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("i2c1_clk", IMX_SC_R_I2C_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("i2c2_clk", IMX_SC_R_I2C_2, IMX_SC_PM_CLK_PER); + imx_clk_scu("i2c3_clk", IMX_SC_R_I2C_3, IMX_SC_PM_CLK_PER); + imx_clk_scu("ftm0_clk", IMX_SC_R_FTM_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("ftm1_clk", IMX_SC_R_FTM_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("adc0_clk", IMX_SC_R_ADC_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("pwm_clk", IMX_SC_R_LCD_0_PWM_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("lcd_clk", IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER); + imx_clk_scu2("lcd_pxl_clk", lcd_pxl_sels, ARRAY_SIZE(lcd_pxl_sels), IMX_SC_R_LCD_0, IMX_SC_PM_CLK_MISC0); + imx_clk_scu("lcd_pxl_bypass_div_clk", IMX_SC_R_LCD_0, IMX_SC_PM_CLK_BYPASS); + + /* Audio SS */ + imx_clk_scu("audio_pll0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_PLL); + imx_clk_scu("audio_pll1_clk", IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_PLL); + imx_clk_scu("audio_pll_div_clk0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_MISC0); + imx_clk_scu("audio_pll_div_clk1_clk", IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_MISC0); + imx_clk_scu("audio_rec_clk0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_MISC1); + imx_clk_scu("audio_rec_clk1_clk", IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_MISC1); /* Connectivity */ - clks[IMX_CONN_SDHC0_CLK] = imx_clk_scu("sdhc0_clk", IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER); - clks[IMX_CONN_SDHC1_CLK] = imx_clk_scu("sdhc1_clk", IMX_SC_R_SDHC_1, IMX_SC_PM_CLK_PER); - clks[IMX_CONN_SDHC2_CLK] = imx_clk_scu("sdhc2_clk", IMX_SC_R_SDHC_2, IMX_SC_PM_CLK_PER); - clks[IMX_CONN_ENET0_ROOT_CLK] = imx_clk_scu("enet0_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER); - clks[IMX_CONN_ENET0_BYPASS_CLK] = imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS); - clks[IMX_CONN_ENET0_RGMII_CLK] = imx_clk_scu("enet0_rgmii_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0); - clks[IMX_CONN_ENET1_ROOT_CLK] = imx_clk_scu("enet1_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER); - clks[IMX_CONN_ENET1_BYPASS_CLK] = imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS); - clks[IMX_CONN_ENET1_RGMII_CLK] = imx_clk_scu("enet1_rgmii_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0); - clks[IMX_CONN_GPMI_BCH_IO_CLK] = imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS); - clks[IMX_CONN_GPMI_BCH_CLK] = imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER); - clks[IMX_CONN_USB2_ACLK] = imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER); - clks[IMX_CONN_USB2_BUS_CLK] = imx_clk_scu("usb3_bus_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MST_BUS); - clks[IMX_CONN_USB2_LPM_CLK] = imx_clk_scu("usb3_lpm_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC); + imx_clk_scu("sdhc0_clk", IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("sdhc1_clk", IMX_SC_R_SDHC_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("sdhc2_clk", IMX_SC_R_SDHC_2, IMX_SC_PM_CLK_PER); + if (of_id->data == &imx_clk_scu_rsrc_imx8dxl) { + imx_clk_divider_gpr_scu("enet0_ref_div", "conn_enet0_root_clk", IMX_SC_R_ENET_0, IMX_SC_C_CLKDIV); + } else { + imx_clk_scu("enet0_root_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER); + imx_clk_divider_gpr_scu("enet0_ref_div", "enet0_root_clk", IMX_SC_R_ENET_0, IMX_SC_C_CLKDIV); + } + imx_clk_mux_gpr_scu("enet0_rgmii_txc_sel", enet0_rgmii_txc_sels, ARRAY_SIZE(enet0_rgmii_txc_sels), IMX_SC_R_ENET_0, IMX_SC_C_TXCLK); + imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS); + imx_clk_gate_gpr_scu("enet0_ref_50_clk", "clk_dummy", IMX_SC_R_ENET_0, IMX_SC_C_DISABLE_50, true); + imx_clk_scu("enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER); + + if (of_id->data != &imx_clk_scu_rsrc_imx8dxl) { + imx_clk_scu("enet0_rgmii_rx_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0); + imx_clk_scu("enet1_rgmii_rx_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0); + imx_clk_divider_gpr_scu("enet1_ref_div", "enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_C_CLKDIV); + imx_clk_mux_gpr_scu("enet1_rgmii_txc_sel", enet1_rgmii_txc_sels, ARRAY_SIZE(enet1_rgmii_txc_sels), IMX_SC_R_ENET_1, IMX_SC_C_TXCLK); + } + imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS); + imx_clk_gate_gpr_scu("enet1_ref_50_clk", "clk_dummy", IMX_SC_R_ENET_1, IMX_SC_C_DISABLE_50, true); + imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS); + imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER); + imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER); + imx_clk_scu("usb3_bus_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MST_BUS); + imx_clk_scu("usb3_lpm_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC); /* Display controller SS */ - clks[IMX_DC0_DISP0_CLK] = imx_clk_scu("dc0_disp0_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0); - clks[IMX_DC0_DISP1_CLK] = imx_clk_scu("dc0_disp1_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1); + imx_clk_scu2("dc0_disp0_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0); + imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1); + imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL); + imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL); + imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS); + + imx_clk_scu2("dc1_disp0_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC0); + imx_clk_scu2("dc1_disp1_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC1); + imx_clk_scu("dc1_pll0_clk", IMX_SC_R_DC_1_PLL_0, IMX_SC_PM_CLK_PLL); + imx_clk_scu("dc1_pll1_clk", IMX_SC_R_DC_1_PLL_1, IMX_SC_PM_CLK_PLL); + imx_clk_scu("dc1_bypass0_clk", IMX_SC_R_DC_1_VIDEO0, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu("dc1_bypass1_clk", IMX_SC_R_DC_1_VIDEO1, IMX_SC_PM_CLK_BYPASS); /* MIPI-LVDS SS */ - clks[IMX_MIPI0_I2C0_CLK] = imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2); - clks[IMX_MIPI0_I2C1_CLK] = imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2); + imx_clk_scu("mipi0_bypass_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu("mipi0_pixel_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("lvds0_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2); + imx_clk_scu("lvds0_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu("lvds0_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3); + imx_clk_scu2("mipi0_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_MST_BUS); + imx_clk_scu2("mipi0_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_SLV_BUS); + imx_clk_scu2("mipi0_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PHY); + imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2); + imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2); + imx_clk_scu("mipi0_pwm_clk", IMX_SC_R_MIPI_0_PWM_0, IMX_SC_PM_CLK_PER); + + imx_clk_scu("mipi1_bypass_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu("mipi1_pixel_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("lvds1_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2); + imx_clk_scu("lvds1_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu("lvds1_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3); + imx_clk_scu2("mipi1_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_MST_BUS); + imx_clk_scu2("mipi1_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_SLV_BUS); + imx_clk_scu2("mipi1_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PHY); + imx_clk_scu("mipi1_i2c0_clk", IMX_SC_R_MIPI_1_I2C_0, IMX_SC_PM_CLK_MISC2); + imx_clk_scu("mipi1_i2c1_clk", IMX_SC_R_MIPI_1_I2C_1, IMX_SC_PM_CLK_MISC2); + imx_clk_scu("mipi1_pwm_clk", IMX_SC_R_MIPI_1_PWM_0, IMX_SC_PM_CLK_PER); + + imx_clk_scu("lvds0_i2c0_clk", IMX_SC_R_LVDS_0_I2C_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("lvds0_pwm0_clk", IMX_SC_R_LVDS_0_PWM_0, IMX_SC_PM_CLK_PER); + + imx_clk_scu("lvds1_i2c0_clk", IMX_SC_R_LVDS_1_I2C_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("lvds1_pwm0_clk", IMX_SC_R_LVDS_1_PWM_0, IMX_SC_PM_CLK_PER); /* MIPI CSI SS */ - clks[IMX_CSI0_CORE_CLK] = imx_clk_scu("mipi_csi0_core_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_PER); - clks[IMX_CSI0_ESC_CLK] = imx_clk_scu("mipi_csi0_esc_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_MISC); - clks[IMX_CSI0_I2C0_CLK] = imx_clk_scu("mipi_csi0_i2c0_clk", IMX_SC_R_CSI_0_I2C_0, IMX_SC_PM_CLK_PER); - clks[IMX_CSI0_PWM0_CLK] = imx_clk_scu("mipi_csi0_pwm0_clk", IMX_SC_R_CSI_0_PWM_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("mipi_csi0_core_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("mipi_csi0_esc_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_MISC); + imx_clk_scu("mipi_csi0_i2c0_clk", IMX_SC_R_CSI_0_I2C_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("mipi_csi0_pwm0_clk", IMX_SC_R_CSI_0_PWM_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("mipi_csi1_core_clk", IMX_SC_R_CSI_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("mipi_csi1_esc_clk", IMX_SC_R_CSI_1, IMX_SC_PM_CLK_MISC); + imx_clk_scu("mipi_csi1_i2c0_clk", IMX_SC_R_CSI_1_I2C_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("mipi_csi1_pwm0_clk", IMX_SC_R_CSI_1_PWM_0, IMX_SC_PM_CLK_PER); + + /* Parallel Interface SS */ + imx_clk_scu("pi_dpll_clk", IMX_SC_R_PI_0_PLL, IMX_SC_PM_CLK_PLL); + imx_clk_scu2("pi_per_div_clk", pll0_sels, ARRAY_SIZE(pll0_sels), IMX_SC_R_PI_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("pi_mclk_div_clk", IMX_SC_R_PI_0, IMX_SC_PM_CLK_MISC0); + imx_clk_scu("pi_i2c0_div_clk", IMX_SC_R_PI_0_I2C_0, IMX_SC_PM_CLK_PER); /* GPU SS */ - clks[IMX_GPU0_CORE_CLK] = imx_clk_scu("gpu_core0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER); - clks[IMX_GPU0_SHADER_CLK] = imx_clk_scu("gpu_shader0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC); + imx_clk_scu("gpu_core0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER); + imx_clk_scu("gpu_shader0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC); - for (i = 0; i < clk_data->num; i++) { - if (IS_ERR(clks[i])) - pr_warn("i.MX clk %u: register failed with %ld\n", - i, PTR_ERR(clks[i])); - } + imx_clk_scu("gpu_core1_clk", IMX_SC_R_GPU_1_PID0, IMX_SC_PM_CLK_PER); + imx_clk_scu("gpu_shader1_clk", IMX_SC_R_GPU_1_PID0, IMX_SC_PM_CLK_MISC); + /* CM40 SS */ + imx_clk_scu("cm40_i2c_div", IMX_SC_R_M4_0_I2C, IMX_SC_PM_CLK_PER); - return of_clk_add_hw_provider(ccm_node, of_clk_hw_onecell_get, clk_data); -} + /* CM41 SS */ + imx_clk_scu("cm41_i2c_div", IMX_SC_R_M4_1_I2C, IMX_SC_PM_CLK_PER); -static const struct of_device_id imx8qxp_match[] = { - { .compatible = "fsl,scu-clk", }, - { .compatible = "fsl,imx8qxp-clk", }, - { /* sentinel */ } -}; + /* HDMI TX SS */ + imx_clk_scu("hdmi_dig_pll_clk", IMX_SC_R_HDMI_PLL_0, IMX_SC_PM_CLK_PLL); + imx_clk_scu("hdmi_av_pll_clk", IMX_SC_R_HDMI_PLL_1, IMX_SC_PM_CLK_PLL); + imx_clk_scu2("hdmi_pixel_mux_clk", hdmi_sels, ARRAY_SIZE(hdmi_sels), IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC0); + imx_clk_scu2("hdmi_pixel_link_clk", hdmi_sels, ARRAY_SIZE(hdmi_sels), IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC1); + imx_clk_scu("hdmi_ipg_clk", IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC4); + imx_clk_scu("hdmi_i2c0_clk", IMX_SC_R_HDMI_I2C_0, IMX_SC_PM_CLK_MISC2); + imx_clk_scu("hdmi_hdp_core_clk", IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC2); + imx_clk_scu2("hdmi_pxl_clk", hdmi_sels, ARRAY_SIZE(hdmi_sels), IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC3); + imx_clk_scu("hdmi_i2s_bypass_clk", IMX_SC_R_HDMI_I2S, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu("hdmi_i2s_clk", IMX_SC_R_HDMI_I2S, IMX_SC_PM_CLK_MISC0); + + return of_clk_add_hw_provider(ccm_node, imx_scu_of_clk_src_get, imx_scu_clks); +} static struct platform_driver imx8qxp_clk_driver = { .driver = { @@ -151,4 +275,8 @@ static struct platform_driver imx8qxp_clk_driver = { }, .probe = imx8qxp_clk_probe, }; -builtin_platform_driver(imx8qxp_clk_driver); +static int __init imx8qxp_clk_driver_init(void) +{ + return platform_driver_register(&imx8qxp_clk_driver); +} +subsys_initcall_sync(imx8qxp_clk_driver_init); diff --git a/drivers/clk/imx/clk-lpcg-scu.c b/drivers/clk/imx/clk-lpcg-scu.c index a73a799fb777d7..17b278487e1a86 100644 --- a/drivers/clk/imx/clk-lpcg-scu.c +++ b/drivers/clk/imx/clk-lpcg-scu.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -33,10 +34,38 @@ struct clk_lpcg_scu { void __iomem *reg; u8 bit_idx; bool hw_gate; + + /* for state save&restore */ + u32 state; }; #define to_clk_lpcg_scu(_hw) container_of(_hw, struct clk_lpcg_scu, hw) +/* e10858 -LPCG clock gating register synchronization errata */ +static void do_lpcg_workaround(u32 rate, void __iomem *reg, u32 val) +{ + writel(val, reg); + + if (rate >= 24000000 || rate == 0) { + u32 reg1; + + /* + * The time taken to access the LPCG registers from the AP core + * through the interconnect is longer than the minimum delay + * of 4 clock cycles required by the errata. + * Adding a readl will provide sufficient delay to prevent + * back-to-back writes. + */ + reg1 = readl(reg); + } else { + /* + * For clocks running below 24MHz, wait a minimum of + * 4 clock cycles. + */ + ndelay(4 * (DIV_ROUND_UP(1000000000, rate))); + } +} + static int clk_lpcg_scu_enable(struct clk_hw *hw) { struct clk_lpcg_scu *clk = to_clk_lpcg_scu(hw); @@ -53,7 +82,8 @@ static int clk_lpcg_scu_enable(struct clk_hw *hw) val |= CLK_GATE_SCU_LPCG_HW_SEL; reg |= val << clk->bit_idx; - writel(reg, clk->reg); + + do_lpcg_workaround(clk_hw_get_rate(hw), clk->reg, reg); spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags); @@ -70,7 +100,7 @@ static void clk_lpcg_scu_disable(struct clk_hw *hw) reg = readl_relaxed(clk->reg); reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); - writel(reg, clk->reg); + do_lpcg_workaround(clk_hw_get_rate(hw), clk->reg, reg); spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags); } @@ -80,9 +110,9 @@ static const struct clk_ops clk_lpcg_scu_ops = { .disable = clk_lpcg_scu_disable, }; -struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *parent_name, - unsigned long flags, void __iomem *reg, - u8 bit_idx, bool hw_gate) +struct clk_hw *__imx_clk_lpcg_scu(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 bit_idx, bool hw_gate) { struct clk_lpcg_scu *clk; struct clk_init_data init; @@ -106,11 +136,47 @@ struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *parent_name, clk->hw.init = &init; hw = &clk->hw; - ret = clk_hw_register(NULL, hw); + ret = clk_hw_register(dev, hw); if (ret) { kfree(clk); hw = ERR_PTR(ret); } + if (dev) + dev_set_drvdata(dev, clk); + return hw; } + +int __maybe_unused imx_clk_lpcg_scu_suspend(struct device *dev) +{ + struct clk_lpcg_scu *clk = dev_get_drvdata(dev); + + if (!strncmp("hdmi_lpcg", clk_hw_get_name(&clk->hw), strlen("hdmi_lpcg"))) + return 0; + + clk->state = readl_relaxed(clk->reg); + dev_dbg(dev, "save lpcg state 0x%x\n", clk->state); + + return 0; +} + +int __maybe_unused imx_clk_lpcg_scu_resume(struct device *dev) +{ + struct clk_lpcg_scu *clk = dev_get_drvdata(dev); + + if (!strncmp("hdmi_lpcg", clk_hw_get_name(&clk->hw), strlen("hdmi_lpcg"))) + return 0; + + /* FIXME: double write in case a failure */ + writel(clk->state, clk->reg); + do_lpcg_workaround(0, clk->reg, clk->state); + dev_dbg(dev, "restore lpcg state 0x%x\n", clk->state); + + return 0; +} + +const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_clk_lpcg_scu_suspend, + imx_clk_lpcg_scu_resume) +}; diff --git a/drivers/clk/imx/clk-pfd.c b/drivers/clk/imx/clk-pfd.c index 50b7c30296f735..fc2e0fe03bdd3e 100644 --- a/drivers/clk/imx/clk-pfd.c +++ b/drivers/clk/imx/clk-pfd.c @@ -5,9 +5,11 @@ */ #include +#include #include #include #include +#include #include "clk.h" /** @@ -32,20 +34,57 @@ struct clk_pfd { #define CLR 0x8 #define OTG 0xc -static int clk_pfd_enable(struct clk_hw *hw) +static void clk_pfd_do_hardware(struct clk_pfd *pfd, bool enable) +{ + if (enable) + writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR); + else + writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET); +} + +static void clk_pfd_do_shared_clks(struct clk_hw *hw, bool enable) { struct clk_pfd *pfd = to_clk_pfd(hw); - writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR); + if (imx_src_is_m4_enabled() && clk_on_imx6sx()) { +#ifdef CONFIG_SOC_IMX6SX + if (!amp_power_mutex || !shared_mem) { + if (enable) + clk_pfd_do_hardware(pfd, enable); + return; + } + + imx_sema4_mutex_lock(amp_power_mutex); + if (shared_mem->ca9_valid != SHARED_MEM_MAGIC_NUMBER || + shared_mem->cm4_valid != SHARED_MEM_MAGIC_NUMBER) { + imx_sema4_mutex_unlock(amp_power_mutex); + return; + } + + if (!imx_update_shared_mem(hw, enable)) { + imx_sema4_mutex_unlock(amp_power_mutex); + return; + } + + clk_pfd_do_hardware(pfd, enable); + + imx_sema4_mutex_unlock(amp_power_mutex); +#endif + } else { + clk_pfd_do_hardware(pfd, enable); + } +} + +static int clk_pfd_enable(struct clk_hw *hw) +{ + clk_pfd_do_shared_clks(hw, true); return 0; } static void clk_pfd_disable(struct clk_hw *hw) { - struct clk_pfd *pfd = to_clk_pfd(hw); - - writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET); + clk_pfd_do_shared_clks(hw, false); } static unsigned long clk_pfd_recalc_rate(struct clk_hw *hw, diff --git a/drivers/clk/imx/clk-pfdv2.c b/drivers/clk/imx/clk-pfdv2.c index a03bbed662c6bc..2a46b9b61b4661 100644 --- a/drivers/clk/imx/clk-pfdv2.c +++ b/drivers/clk/imx/clk-pfdv2.c @@ -139,6 +139,12 @@ static int clk_pfdv2_set_rate(struct clk_hw *hw, unsigned long rate, u32 val; u8 frac; + if (!rate) + return -EINVAL; + + /* PFD can NOT change rate without gating */ + WARN_ON(clk_pfdv2_is_enabled(hw)); + tmp = tmp * 18 + rate / 2; do_div(tmp, rate); frac = tmp; diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 047f1d8fe323f3..8863d9a5cdd9b2 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -92,9 +92,12 @@ static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_pll14xx *pll = to_clk_pll14xx(hw); + const struct imx_pll14xx_rate_table *rate_table = pll->rate_table; u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1; short int kdiv; u64 fvco = parent_rate; + long rate = 0; + int i; pll_div_ctl0 = readl_relaxed(pll->base + 4); pll_div_ctl1 = readl_relaxed(pll->base + 8); @@ -103,13 +106,25 @@ static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw, sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; kdiv = pll_div_ctl1 & KDIV_MASK; + /* + * Sometimes, the recalculated rate has deviation due to + * the frac part. So find the accurate pll rate from the table + * first, if no match rate in the table, use the rate calculated + * from the equation below. + */ + for (i = 0; i < pll->rate_count; i++) { + if (rate_table[i].pdiv == pdiv && rate_table[i].mdiv == mdiv && + rate_table[i].sdiv == sdiv && rate_table[i].kdiv == kdiv) + rate = rate_table[i].rate; + } + /* fvco = (m * 65536 + k) * Fin / (p * 65536) */ fvco *= (mdiv * 65536 + kdiv); pdiv *= 65536; do_div(fvco, pdiv << sdiv); - return fvco; + return rate ? (unsigned long) rate : (unsigned long)fvco; } static inline bool clk_pll14xx_mp_change(const struct imx_pll14xx_rate_table *rate, @@ -315,6 +330,26 @@ static void clk_pll14xx_unprepare(struct clk_hw *hw) writel_relaxed(val, pll->base + GNRL_CTL); } +void clk_set_delta_k(struct clk_hw *hw, short int delta_k) +{ + struct clk_pll14xx *pll = to_clk_pll14xx(hw); + short int k; + u32 val; + + val = readl_relaxed(pll->base + 8); + k = (val & KDIV_MASK) + delta_k; + writel_relaxed(k << KDIV_SHIFT, pll->base + 8); +} + +void clk_get_pll_setting(struct clk_hw *hw, u32 *pll_div_ctrl0, + u32 *pll_div_ctrl1) +{ + struct clk_pll14xx *pll = to_clk_pll14xx(hw); + + *pll_div_ctrl0 = readl_relaxed(pll->base + 4); + *pll_div_ctrl1 = readl_relaxed(pll->base + 8); +} + static const struct clk_ops clk_pll1416x_ops = { .prepare = clk_pll14xx_prepare, .unprepare = clk_pll14xx_unprepare, @@ -337,8 +372,8 @@ static const struct clk_ops clk_pll1443x_ops = { .set_rate = clk_pll1443x_set_rate, }; -struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, - void __iomem *base, +struct clk *imx_dev_clk_pll14xx(struct device *dev, const char *name, + const char *parent_name, void __iomem *base, const struct imx_pll14xx_clk *pll_clk) { struct clk_pll14xx *pll; @@ -380,7 +415,7 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, val &= ~BYPASS_MASK; writel_relaxed(val, pll->base + GNRL_CTL); - clk = clk_register(NULL, &pll->hw); + clk = clk_register(dev, &pll->hw); if (IS_ERR(clk)) { pr_err("%s: failed to register pll %s %lu\n", __func__, name, PTR_ERR(clk)); diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index df91a8244fb4d9..fd4d4d809d61e4 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -7,9 +7,11 @@ #include #include #include +#include #include #include #include +#include #include "clk.h" #define PLL_NUM_OFFSET 0x10 @@ -66,38 +68,82 @@ static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) break; if (time_after(jiffies, timeout)) break; - usleep_range(50, 500); + /* Do not usleep if m4 enabled on i.mx6sx */ + if (!(imx_src_is_m4_enabled() && clk_on_imx6sx())) + usleep_range(50, 500); } while (1); return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT; } -static int clk_pllv3_prepare(struct clk_hw *hw) +static int clk_pllv3_do_hardware(struct clk_hw *hw, bool enable) { struct clk_pllv3 *pll = to_clk_pllv3(hw); + int ret; u32 val; val = readl_relaxed(pll->base); - if (pll->powerup_set) - val |= pll->power_bit; - else - val &= ~pll->power_bit; - writel_relaxed(val, pll->base); + if (enable) { + if (pll->powerup_set) + val |= pll->power_bit; + else + val &= ~pll->power_bit; + writel_relaxed(val, pll->base); + + ret = clk_pllv3_wait_lock(pll); + if (ret) + return ret; + } else { + if (pll->powerup_set) + val &= ~pll->power_bit; + else + val |= pll->power_bit; + writel_relaxed(val, pll->base); + } - return clk_pllv3_wait_lock(pll); + return 0; } -static void clk_pllv3_unprepare(struct clk_hw *hw) +static void clk_pllv3_do_shared_clks(struct clk_hw *hw, bool enable) { - struct clk_pllv3 *pll = to_clk_pllv3(hw); - u32 val; + if (imx_src_is_m4_enabled() && clk_on_imx6sx()) { +#ifdef CONFIG_SOC_IMX6SX + if (!amp_power_mutex || !shared_mem) { + if (enable) + clk_pllv3_do_hardware(hw, enable); + return; + } + + imx_sema4_mutex_lock(amp_power_mutex); + if (shared_mem->ca9_valid != SHARED_MEM_MAGIC_NUMBER || + shared_mem->cm4_valid != SHARED_MEM_MAGIC_NUMBER) { + imx_sema4_mutex_unlock(amp_power_mutex); + return; + } + + if (!imx_update_shared_mem(hw, enable)) { + imx_sema4_mutex_unlock(amp_power_mutex); + return; + } + clk_pllv3_do_hardware(hw, enable); + + imx_sema4_mutex_unlock(amp_power_mutex); +#endif + } else { + clk_pllv3_do_hardware(hw, enable); + } +} - val = readl_relaxed(pll->base); - if (pll->powerup_set) - val &= ~pll->power_bit; - else - val |= pll->power_bit; - writel_relaxed(val, pll->base); +static int clk_pllv3_prepare(struct clk_hw *hw) +{ + clk_pllv3_do_shared_clks(hw, true); + + return 0; +} + +static void clk_pllv3_unprepare(struct clk_hw *hw) +{ + clk_pllv3_do_shared_clks(hw, false); } static int clk_pllv3_is_prepared(struct clk_hw *hw) diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c index b8b2072742a560..6a64aa0d39134a 100644 --- a/drivers/clk/imx/clk-scu.c +++ b/drivers/clk/imx/clk-scu.c @@ -6,16 +6,42 @@ #include #include +#include #include #include +#include +#include +#include +#include +#include #include +#include +#include #include "clk-scu.h" #define IMX_SIP_CPUFREQ 0xC2000001 #define IMX_SIP_SET_CPUFREQ 0x00 +#define MAX_CLUSTER_NUM 2 static struct imx_sc_ipc *ccm_ipc_handle; +static const struct imx_clk_scu_rsrc_table *rsrc_table; +static struct delayed_work cpufreq_governor_daemon; +struct device_node *pd_np; +u32 clock_cells; + +struct imx_scu_clk_node { + const char *name; + u32 rsrc; + u8 clk_type; + const char * const *parents; + int num_parents; + + struct clk_hw *hw; + struct list_head node; +}; + +struct list_head imx_scu_clks[IMX_SC_R_LAST]; /* * struct clk_scu - Description of one SCU clock @@ -27,6 +53,26 @@ struct clk_scu { struct clk_hw hw; u16 rsrc_id; u8 clk_type; + + /* for state save&restore */ + struct clk_hw *parent; + u8 parent_index; + bool is_enabled; + u32 rate; +}; + +/* + * struct clk_gpr_scu - Description of one gate SCU clock + * @hw: the common clk_hw + * @rsrc_id: resource ID of this SCU clock + * @gpr_id: GPR ID index to control the divider + */ +struct clk_gpr_scu { + struct clk_hw hw; + u16 rsrc_id; + u8 gpr_id; + u8 flags; + bool gate_invert; }; /* @@ -54,6 +100,9 @@ struct resp_get_clock_rate { __le32 rate; }; +#define to_clk_mux_gpr_scu(_hw) container_of(_hw, struct clk_mux_gpr_scu, hw) +#define to_clk_gpr_scu(_hw) container_of(_hw, struct clk_gpr_scu, hw) + /* * struct imx_sc_msg_get_clock_rate - clock get rate protocol * @hdr: SCU protocol header @@ -128,9 +177,48 @@ static inline struct clk_scu *to_clk_scu(struct clk_hw *hw) return container_of(hw, struct clk_scu, hw); } -int imx_clk_scu_init(void) +static int imx_scu_clk_search_cmp(const void *rsrc, const void *rsrc_p) { - return imx_scu_get_handle(&ccm_ipc_handle); + return *(u32 *)rsrc - *(u32 *)rsrc_p; +} + +bool imx_scu_clk_is_valid(u32 rsrc_id) +{ + void *p; + + if (!rsrc_table) + return true; + + p = bsearch(&rsrc_id, rsrc_table->rsrc, rsrc_table->num, + sizeof(rsrc_table->rsrc[0]), imx_scu_clk_search_cmp); + return p != NULL; +} + +int imx_clk_scu_init(struct device_node *np, const void *data) +{ + struct platform_device *pd_dev; + int ret, i; + + ret = imx_scu_get_handle(&ccm_ipc_handle); + if (ret) + return ret; + + if (of_property_read_u32(np, "#clock-cells", &clock_cells)) + return -EINVAL; + + if (clock_cells == 2) { + for (i = 0; i < IMX_SC_R_LAST; i++) + INIT_LIST_HEAD(&imx_scu_clks[i]); + + pd_np = of_find_compatible_node(NULL, NULL, "fsl,scu-pd"); + pd_dev = of_find_device_by_node(pd_np); + if (!pd_dev || !device_is_bound(&pd_dev->dev)) + return -EPROBE_DEFER; + + rsrc_table = data; + } + + return 0; } /* @@ -192,8 +280,10 @@ static int clk_scu_atf_set_cpu_rate(struct clk_hw *hw, unsigned long rate, struct arm_smccc_res res; unsigned long cluster_id; - if (clk->rsrc_id == IMX_SC_R_A35) + if (clk->rsrc_id == IMX_SC_R_A35 || clk->rsrc_id == IMX_SC_R_A53) cluster_id = 0; + else if (clk->rsrc_id == IMX_SC_R_A72) + cluster_id = 1; else return -EINVAL; @@ -254,6 +344,8 @@ static u8 clk_scu_get_parent(struct clk_hw *hw) return 0; } + clk->parent_index = msg.data.resp.parent; + return msg.data.resp.parent; } @@ -262,6 +354,7 @@ static int clk_scu_set_parent(struct clk_hw *hw, u8 index) struct clk_scu *clk = to_clk_scu(hw); struct imx_sc_msg_set_clock_parent msg; struct imx_sc_rpc_msg *hdr = &msg.hdr; + int ret; hdr->ver = IMX_SC_RPC_VERSION; hdr->svc = IMX_SC_RPC_SVC_PM; @@ -272,7 +365,16 @@ static int clk_scu_set_parent(struct clk_hw *hw, u8 index) msg.clk = clk->clk_type; msg.parent = index; - return imx_scu_call_rpc(ccm_ipc_handle, &msg, true); + ret = imx_scu_call_rpc(ccm_ipc_handle, &msg, true); + if (ret) { + pr_err("%s: failed to set clock parent %d\n", + clk_hw_get_name(hw), ret); + return ret; + } + + clk->parent_index = index; + + return 0; } static int sc_pm_clock_enable(struct imx_sc_ipc *ipc, u16 resource, @@ -344,8 +446,15 @@ static const struct clk_ops clk_scu_cpu_ops = { .unprepare = clk_scu_unprepare, }; -struct clk_hw *__imx_clk_scu(const char *name, const char * const *parents, - int num_parents, u32 rsrc_id, u8 clk_type) +static const struct clk_ops clk_scu_pi_ops = { + .recalc_rate = clk_scu_recalc_rate, + .round_rate = clk_scu_round_rate, + .set_rate = clk_scu_set_rate, +}; + +struct clk_hw *__imx_clk_scu(struct device *dev, const char *name, + const char * const *parents, int num_parents, + u32 rsrc_id, u8 clk_type) { struct clk_init_data init; struct clk_scu *clk; @@ -361,8 +470,10 @@ struct clk_hw *__imx_clk_scu(const char *name, const char * const *parents, init.name = name; init.ops = &clk_scu_ops; - if (rsrc_id == IMX_SC_R_A35) + if (rsrc_id == IMX_SC_R_A35 || rsrc_id == IMX_SC_R_A53 || rsrc_id == IMX_SC_R_A72) init.ops = &clk_scu_cpu_ops; + else if (rsrc_id == IMX_SC_R_PI_0_PLL) + init.ops = &clk_scu_pi_ops; else init.ops = &clk_scu_ops; init.parent_names = parents; @@ -375,15 +486,474 @@ struct clk_hw *__imx_clk_scu(const char *name, const char * const *parents, * clock status from HW instead of using the possible invalid * cached rate. */ - init.flags = CLK_GET_RATE_NOCACHE; + init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_PARENT_NOCACHE; + clk->hw.init = &init; + + hw = &clk->hw; + ret = clk_hw_register(dev, hw); + if (ret) { + kfree(clk); + hw = ERR_PTR(ret); + } + + if (dev) + dev_set_drvdata(dev, clk); + + return hw; +} + +struct clk_hw *imx_scu_of_clk_src_get(struct of_phandle_args *clkspec, + void *data) +{ + unsigned int rsrc = clkspec->args[0]; + unsigned int idx = clkspec->args[1]; + struct list_head *scu_clks = data; + struct imx_scu_clk_node *clk; + + list_for_each_entry(clk, &scu_clks[rsrc], node) { + if (clk->clk_type == idx) + return clk->hw; + } + + return ERR_PTR(-ENODEV); +} + +static int imx_clk_scu_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct imx_scu_clk_node *clk = dev_get_platdata(dev); + struct clk_hw *hw; + int ret; + + pm_runtime_set_suspended(dev); + pm_runtime_set_autosuspend_delay(dev, 50); + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_enable(dev); + + ret = pm_runtime_get_sync(dev); + if (ret) { + pm_genpd_remove_device(dev); + pm_runtime_disable(dev); + return ret; + } + + hw = __imx_clk_scu(dev, clk->name, clk->parents, clk->num_parents, + clk->rsrc, clk->clk_type); + if (IS_ERR(hw)) { + pm_runtime_disable(dev); + return PTR_ERR(hw); + } + + clk->hw = hw; + list_add_tail(&clk->node, &imx_scu_clks[clk->rsrc]); + + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_put_autosuspend(&pdev->dev); + + dev_dbg(dev, "register SCU clock rsrc:%d type:%d\n", clk->rsrc, + clk->clk_type); + + return 0; +} + +int __maybe_unused imx_clk_scu_suspend(struct device *dev) +{ + struct clk_scu *clk = dev_get_drvdata(dev); + u32 rsrc_id = clk->rsrc_id; + + if ((rsrc_id == IMX_SC_R_A35) || (rsrc_id == IMX_SC_R_A53) || + (rsrc_id == IMX_SC_R_A72)) + return 0; + + clk->parent = clk_hw_get_parent(&clk->hw); + + /* DC SS needs to handle bypass clock using non-cached clock rate */ + if (clk->rsrc_id == IMX_SC_R_DC_0_VIDEO0 || + clk->rsrc_id == IMX_SC_R_DC_0_VIDEO1 || + clk->rsrc_id == IMX_SC_R_DC_1_VIDEO0 || + clk->rsrc_id == IMX_SC_R_DC_1_VIDEO1) + clk->rate = clk_scu_recalc_rate(&clk->hw, 0); + else + clk->rate = clk_hw_get_rate(&clk->hw); + + clk->is_enabled = clk_hw_is_enabled(&clk->hw); + + if (clk->parent) + dev_dbg(dev, "save parent %s idx %u\n", clk_hw_get_name(clk->parent), + clk->parent_index); + + if (clk->rate) + dev_dbg(dev, "save rate %d\n", clk->rate); + + if (clk->is_enabled) + dev_dbg(dev, "save enabled state\n"); + + return 0; +} + +int __maybe_unused imx_clk_scu_resume(struct device *dev) +{ + struct clk_scu *clk = dev_get_drvdata(dev); + u32 rsrc_id = clk->rsrc_id; + int ret = 0; + + if ((rsrc_id == IMX_SC_R_A35) || (rsrc_id == IMX_SC_R_A53) || + (rsrc_id == IMX_SC_R_A72)) + return 0; + + if (clk->parent) { + ret = clk_scu_set_parent(&clk->hw, clk->parent_index); + dev_dbg(dev, "restore parent %s idx %u %s\n", + clk_hw_get_name(clk->parent), + clk->parent_index, !ret ? "success" : "failed"); + } + + if (clk->rate) { + ret = clk_scu_set_rate(&clk->hw, clk->rate, 0); + dev_dbg(dev, "restore rate %d %s\n", clk->rate, + !ret ? "success" : "failed"); + } + + if (clk->is_enabled && rsrc_id != IMX_SC_R_PI_0_PLL) { + ret = clk_scu_prepare(&clk->hw); + dev_dbg(dev, "restore enabled state %s\n", + !ret ? "success" : "failed"); + } + + return ret; +} + +const struct dev_pm_ops imx_clk_scu_pm_ops = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_clk_scu_suspend, + imx_clk_scu_resume) +}; + +static struct platform_driver imx_clk_scu_driver = { + .driver = { + .name = "imx-scu-clk", + .suppress_bind_attrs = true, + .pm = &imx_clk_scu_pm_ops, + }, + .probe = imx_clk_scu_probe, +}; + +static int __init imx_clk_scu_driver_init(void) +{ + return platform_driver_register(&imx_clk_scu_driver); +} +subsys_initcall_sync(imx_clk_scu_driver_init); + +static int imx_clk_scu_attach_pd(struct device *dev, u32 rsrc_id) +{ + struct of_phandle_args genpdspec = { + .np = pd_np, + .args_count = 1, + .args[0] = rsrc_id, + }; + + if ((rsrc_id == IMX_SC_R_A35) || (rsrc_id == IMX_SC_R_A53) || + (rsrc_id == IMX_SC_R_A72)) + return 0; + + /* + * Temp fix to avoid the uart clk attached pd power off uart_0 + */ + if (rsrc_id == IMX_SC_R_UART_0 && xen_initial_domain()) + return 0; + + return of_genpd_add_device(&genpdspec, dev); +} + +static bool imx_clk_is_resource_owned(u32 rsrc) +{ + /* + * A-core resources are special. SCFW reports they are not "owned" by + * current partition but linux can still adjust them for cpufreq. + * + * So force this to return false when running as a VM guest and always + * true otherwise. + */ + if (rsrc == IMX_SC_R_A53 || rsrc == IMX_SC_R_A72 || + rsrc == IMX_SC_R_A35) { + if (xen_domain() && !xen_initial_domain()) + return false; + return true; + } + + return imx_sc_rm_is_resource_owned(ccm_ipc_handle, rsrc); +} + +struct clk_hw *imx_clk_scu_alloc_dev(const char *name, + const char * const *parents, + int num_parents, u32 rsrc_id, u8 clk_type) +{ + struct imx_scu_clk_node clk = { + .name = name, + .rsrc = rsrc_id, + .clk_type = clk_type, + .parents = parents, + .num_parents = num_parents, + }; + struct platform_device *pdev; + int ret; + + if (!imx_scu_clk_is_valid(rsrc_id)) + return NULL; + + if (!imx_clk_is_resource_owned(rsrc_id)) + return NULL; + + pdev = platform_device_alloc(name, PLATFORM_DEVID_NONE); + if (!pdev) { + pr_err("%s: failed to allocate scu clk dev rsrc %d type %d\n", + name, rsrc_id, clk_type); + return ERR_PTR(-ENOMEM); + } + + ret = platform_device_add_data(pdev, &clk, sizeof(clk)); + if (ret) { + platform_device_put(pdev); + return ERR_PTR(-ENOMEM); + } + + pdev->driver_override = "imx-scu-clk"; + + ret = imx_clk_scu_attach_pd(&pdev->dev, rsrc_id); + if (ret) + pr_warn("%s: failed to attached the power domain %d\n", + name, ret); + + platform_device_add(pdev); + + /* For API backwards compatiblilty, simply return NULL for success */ + return NULL; +} + +static unsigned long clk_gpr_div_scu_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_gpr_scu *clk = to_clk_gpr_scu(hw); + unsigned long rate = 0; + u32 val; + int err; + + err = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id, + clk->gpr_id, &val); + + rate = val ? parent_rate / 2 : parent_rate; + + return err ? 0 : rate; +} + +static long clk_gpr_div_scu_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + if (rate < *prate) + rate = *prate / 2; + else + rate = *prate; + + return rate; +} + +static int clk_gpr_div_scu_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_gpr_scu *clk = to_clk_gpr_scu(hw); + uint32_t val; + int err; + + val = (rate < parent_rate) ? 1 : 0; + err = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id, + clk->gpr_id, val); + + return err ? -EINVAL : 0; +} + +static const struct clk_ops clk_gpr_div_scu_ops = { + .recalc_rate = clk_gpr_div_scu_recalc_rate, + .round_rate = clk_gpr_div_scu_round_rate, + .set_rate = clk_gpr_div_scu_set_rate, +}; + +static u8 clk_gpr_mux_scu_get_parent(struct clk_hw *hw) +{ + struct clk_gpr_scu *clk= to_clk_gpr_scu(hw); + u32 val = 0; + + imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id, + clk->gpr_id, &val); + + return (u8)val; +} + +static int clk_gpr_mux_scu_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_gpr_scu *clk= to_clk_gpr_scu(hw); + + imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id, + clk->gpr_id, index); + + return 0; +} + +static const struct clk_ops clk_gpr_mux_scu_ops = { + .get_parent = clk_gpr_mux_scu_get_parent, + .set_parent = clk_gpr_mux_scu_set_parent, +}; + +static int clk_gpr_gate_scu_prepare(struct clk_hw *hw) +{ + struct clk_gpr_scu *clk = to_clk_gpr_scu(hw); + + return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id, + clk->gpr_id, !clk->gate_invert); +} + +static void clk_gpr_gate_scu_unprepare(struct clk_hw *hw) +{ + struct clk_gpr_scu *clk = to_clk_gpr_scu(hw); + int ret; + + ret = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id, + clk->gpr_id, clk->gate_invert); + if (ret) + pr_err("%s: clk unprepare failed %d\n", clk_hw_get_name(hw), + ret); +} + +static int clk_gpr_gate_scu_is_prepared(struct clk_hw *hw) +{ + struct clk_gpr_scu *clk= to_clk_gpr_scu(hw); + int ret; + u32 val; + + ret = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id, + clk->gpr_id, &val); + if (ret) + return ret; + + return clk->gate_invert ? !val : val; +} + +static struct clk_ops clk_gpr_gate_scu_ops = { + .prepare = clk_gpr_gate_scu_prepare, + .unprepare = clk_gpr_gate_scu_unprepare, + .is_prepared = clk_gpr_gate_scu_is_prepared, +}; + +struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name, + int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags, + bool invert) +{ + struct imx_scu_clk_node *clk_node; + struct clk_gpr_scu *clk; + struct clk_hw *hw; + struct clk_init_data init; + int ret; + + if (rsrc_id >= IMX_SC_R_LAST) + return NULL; + + if (gpr_id >= IMX_SC_C_LAST) + return NULL; + + if (!imx_scu_clk_is_valid(rsrc_id)) + return ERR_PTR(-EINVAL); + + clk = kzalloc(sizeof(*clk), GFP_KERNEL); + if (!clk) + return ERR_PTR(-ENOMEM); + + clk_node = kzalloc(sizeof(*clk_node), GFP_KERNEL); + if (!clk_node) { + kfree(clk); + return ERR_PTR(-ENOMEM); + }; + + /* struct clk_gate_scu assignments */ + clk->rsrc_id = rsrc_id; + clk->gpr_id = gpr_id; + clk->flags = flags; + clk->gate_invert = invert; + + if (flags & IMX_SCU_GPR_CLK_GATE) + init.ops = &clk_gpr_gate_scu_ops; + + if (flags & IMX_SCU_GPR_CLK_DIV) + init.ops = &clk_gpr_div_scu_ops; + + if (flags & IMX_SCU_GPR_CLK_MUX) + init.ops = &clk_gpr_mux_scu_ops; + + init.flags = 0; + init.name = name; + init.parent_names = parent_name; + init.num_parents = num_parents; + clk->hw.init = &init; hw = &clk->hw; ret = clk_hw_register(NULL, hw); if (ret) { kfree(clk); + kfree(clk_node); hw = ERR_PTR(ret); + } else { + clk_node->hw = hw; + clk_node->clk_type = gpr_id; + list_add_tail(&clk_node->node, &imx_scu_clks[rsrc_id]); } return hw; } + +static void cpufreq_governor_daemon_handler(struct work_struct *work) +{ + int fd, i; + unsigned char cluster_governor[MAX_CLUSTER_NUM][54] = { + "/sys/devices/system/cpu/cpu0/cpufreq/scaling_governor", + "", + }; + + /* generate second cluster's cpufreq governor path */ + sprintf(cluster_governor[MAX_CLUSTER_NUM - 1], + "%s%d%s", "/sys/devices/system/cpu/cpu", num_online_cpus() - 1, + "/cpufreq/scaling_governor"); + + for (i = 0; i < MAX_CLUSTER_NUM; i++) { + fd = ksys_open((const char __user __force *)cluster_governor[i], + O_RDWR, 0700); + if (fd >= 0) { + ksys_write(fd, "schedutil", strlen("schedutil")); + ksys_close(fd); + pr_info("switch cluster %d cpu-freq governor to schedutil\n", + i); + } else { + /* re-schedule if sys write is NOT ready */ + schedule_delayed_work(&cpufreq_governor_daemon, + msecs_to_jiffies(3000)); + break; + } + } +} + +static int __init imx_scu_switch_cpufreq_governor(void) +{ + int i; + + INIT_DELAYED_WORK(&cpufreq_governor_daemon, + cpufreq_governor_daemon_handler); + + for (i = 1; i < num_online_cpus(); i++) { + if (topology_physical_package_id(i) == topology_physical_package_id(0)) + continue; + + schedule_delayed_work(&cpufreq_governor_daemon, + msecs_to_jiffies(3000)); + break; + } + + return 0; +} +late_initcall(imx_scu_switch_cpufreq_governor); diff --git a/drivers/clk/imx/clk-scu.h b/drivers/clk/imx/clk-scu.h index 2bcfaf06a4586c..50f88319924d67 100644 --- a/drivers/clk/imx/clk-scu.h +++ b/drivers/clk/imx/clk-scu.h @@ -8,25 +8,95 @@ #define __IMX_CLK_SCU_H #include +#include -int imx_clk_scu_init(void); +#define IMX_SCU_GPR_CLK_GATE BIT(0) +#define IMX_SCU_GPR_CLK_DIV BIT(1) +#define IMX_SCU_GPR_CLK_MUX BIT(2) -struct clk_hw *__imx_clk_scu(const char *name, const char * const *parents, - int num_parents, u32 rsrc_id, u8 clk_type); +struct imx_clk_scu_rsrc_table { + const u32 *rsrc; + u8 num; +}; + +extern u32 clock_cells; +extern struct list_head imx_scu_clks[]; +extern const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops; +extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp; +extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm; +extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8dxl; + +int imx_clk_scu_init(struct device_node *np, const void *data); +struct clk_hw *imx_scu_of_clk_src_get(struct of_phandle_args *clkspec, + void *data); +struct clk_hw *imx_clk_scu_alloc_dev(const char *name, + const char * const *parents, + int num_parents, u32 rsrc_id, u8 clk_type); + +struct clk_hw *__imx_clk_scu(struct device *dev, const char *name, + const char * const *parents, int num_parents, + u32 rsrc_id, u8 clk_type); + +struct clk_hw *__imx_clk_lpcg_scu(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 bit_idx, bool hw_gate); + +struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name, + int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags, + bool invert); static inline struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id, u8 clk_type) { - return __imx_clk_scu(name, NULL, 0, rsrc_id, clk_type); + if (clock_cells == 2) + return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type); + else + return __imx_clk_scu(NULL, name, NULL, 0, rsrc_id, clk_type); } static inline struct clk_hw *imx_clk_scu2(const char *name, const char * const *parents, int num_parents, u32 rsrc_id, u8 clk_type) { - return __imx_clk_scu(name, parents, num_parents, rsrc_id, clk_type); + if (clock_cells == 2) + return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type); + else + return __imx_clk_scu(NULL, name, parents, num_parents, rsrc_id, clk_type); } -struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *parent_name, - unsigned long flags, void __iomem *reg, - u8 bit_idx, bool hw_gate); +static inline struct clk_hw *imx_clk_lpcg_scu_dev(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 bit_idx, bool hw_gate) +{ + return __imx_clk_lpcg_scu(dev, name, parent_name, flags, reg, + bit_idx, hw_gate); +} + +static inline struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *parent_name, + unsigned long flags, void __iomem *reg, + u8 bit_idx, bool hw_gate) +{ + return __imx_clk_lpcg_scu(NULL, name, parent_name, flags, reg, + bit_idx, hw_gate); +} + +static inline struct clk_hw *imx_clk_gate_gpr_scu(const char *name, const char *parent_name, + u32 rsrc_id, u8 gpr_id, bool invert) +{ + return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id, + IMX_SCU_GPR_CLK_GATE, invert); +} + +static inline struct clk_hw *imx_clk_divider_gpr_scu(const char *name, const char *parent_name, + u32 rsrc_id, u8 gpr_id) +{ + return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id, + IMX_SCU_GPR_CLK_DIV, 0); +} + +static inline struct clk_hw *imx_clk_mux_gpr_scu(const char *name, const char * const *parent_names, + int num_parents, u32 rsrc_id, u8 gpr_id) +{ + return __imx_clk_gpr_scu(name, parent_names, num_parents, rsrc_id, + gpr_id, IMX_SCU_GPR_CLK_MUX, 0); +} #endif diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c index cfc05e43c3430d..6c0029950d389a 100644 --- a/drivers/clk/imx/clk.c +++ b/drivers/clk/imx/clk.c @@ -14,6 +14,8 @@ DEFINE_SPINLOCK(imx_ccm_lock); +bool uart_from_osc; + void imx_unregister_clocks(struct clk *clks[], unsigned int count) { unsigned int i; @@ -133,7 +135,7 @@ void imx_cscmr1_fixup(u32 *val) } static int imx_keep_uart_clocks; -static struct clk ** const *imx_uart_clocks; +static bool imx_uart_clks_on; static int __init imx_keep_uart_clocks_param(char *str) { @@ -146,26 +148,49 @@ __setup_param("earlycon", imx_keep_uart_earlycon, __setup_param("earlyprintk", imx_keep_uart_earlyprintk, imx_keep_uart_clocks_param, 0); -void imx_register_uart_clocks(struct clk ** const clks[]) +static void imx_earlycon_uart_clks_onoff(bool is_on) { - if (imx_keep_uart_clocks) { - int i; + struct clk *uart_clk; + int i = 0; - imx_uart_clocks = clks; - for (i = 0; imx_uart_clocks[i]; i++) - clk_prepare_enable(*imx_uart_clocks[i]); - } + if (!imx_keep_uart_clocks || (!is_on && !imx_uart_clks_on)) + return; + + /* only support dt */ + if (!of_stdout) + return; + + do { + uart_clk = of_clk_get(of_stdout, i++); + if (IS_ERR(uart_clk)) + break; + + if (is_on) + clk_prepare_enable(uart_clk); + else + clk_disable_unprepare(uart_clk); + } while (true); + + if (is_on) + imx_uart_clks_on = true; } -static int __init imx_clk_disable_uart(void) +void imx_register_uart_clocks(void) { - if (imx_keep_uart_clocks && imx_uart_clocks) { - int i; + imx_earlycon_uart_clks_onoff(true); +} - for (i = 0; imx_uart_clocks[i]; i++) - clk_disable_unprepare(*imx_uart_clocks[i]); - } +static int __init imx_clk_disable_uart(void) +{ + imx_earlycon_uart_clks_onoff(false); return 0; } late_initcall_sync(imx_clk_disable_uart); + +static int __init setup_uart_clk(char *uart_rate) +{ + uart_from_osc = true; + return 1; +} +__setup("uart_from_osc", setup_uart_clk); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 6fe64ff8ffa125..b940f68c978c8c 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -4,16 +4,20 @@ #include #include +#include extern spinlock_t imx_ccm_lock; void imx_check_clocks(struct clk *clks[], unsigned int count); void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count); -void imx_register_uart_clocks(struct clk ** const clks[]); +void imx_register_uart_clocks(void); void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn); void imx_unregister_clocks(struct clk *clks[], unsigned int count); extern void imx_cscmr1_fixup(u32 *val); +extern struct imx_sema4_mutex *amp_power_mutex; +extern struct imx_shared_mem *shared_mem; +extern bool uart_from_osc; enum imx_pllv1_type { IMX_PLLV1_IMX1, @@ -94,8 +98,9 @@ struct imx_pll14xx_clk { #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \ to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents)) -struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, - void __iomem *base, const struct imx_pll14xx_clk *pll_clk); +struct clk *imx_dev_clk_pll14xx(struct device *dev, const char *name, + const char *parent_name, void __iomem *base, + const struct imx_pll14xx_clk *pll_clk); struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name, const char *parent, void __iomem *base); @@ -126,6 +131,25 @@ enum imx_pllv3_type { IMX_PLLV3_AV_IMX7, }; +#define MAX_SHARED_CLK_NUMBER 100 +#define SHARED_MEM_MAGIC_NUMBER 0x12345678 +#define MCC_POWER_SHMEM_NUMBER (6) + +struct imx_shared_clk { + struct clk *self; + struct clk *parent; + void *m4_clk; + void *m4_clk_parent; + u8 ca9_enabled; + u8 cm4_enabled; +}; + +struct imx_shared_mem { + u32 ca9_valid; + u32 cm4_valid; + struct imx_shared_clk imx_clk[MAX_SHARED_CLK_NUMBER]; +}; + struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, u32 div_mask); @@ -181,6 +205,13 @@ struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift u8 width, void __iomem *busy_reg, u8 busy_shift, const char * const *parent_names, int num_parents); +int imx_update_shared_mem(struct clk_hw *hw, bool enable); + +static inline int clk_on_imx6sx(void) +{ + return of_machine_is_compatible("fsl,imx6sx"); +} + struct clk_hw *imx7ulp_clk_composite(const char *name, const char * const *parent_names, int num_parents, bool mux_present, @@ -285,6 +316,25 @@ static inline struct clk *imx_clk_gate(const char *name, const char *parent, shift, 0, &imx_ccm_lock); } +static inline struct clk *imx_dev_clk_gate(struct device *dev, + const char *name, const char *parent, + void __iomem *reg, u8 shift) +{ + return clk_register_gate(dev, name, parent, CLK_SET_RATE_PARENT, reg, + shift, 0, &imx_ccm_lock); +} + +struct clk *imx_dev_clk_gate_shared(struct device *dev, const char *name, + const char *parent, void __iomem *reg, + u8 shift, unsigned int *share_count); + +static inline struct clk *imx_clk_gate_shared(const char *name, + const char *parent, void __iomem *reg, u8 shift, + unsigned int *share_count) +{ + return imx_dev_clk_gate_shared(NULL, name, parent, reg, shift, share_count); +} + static inline struct clk_hw *imx_clk_hw_gate_flags(const char *name, const char *parent, void __iomem *reg, u8 shift, unsigned long flags) { @@ -354,7 +404,17 @@ static inline struct clk *imx_clk_gate2_cgr(const char *name, static inline struct clk_hw *imx_clk_hw_gate3(const char *name, const char *parent, void __iomem *reg, u8 shift) { - return clk_hw_register_gate(NULL, name, parent, + /* + * per design team's suggestion, clk root is NOT consuming + * much power, and clk root enable/disable does NOT have domain + * control, so they suggest to leave clk root always on when + * M4 is enabled. + */ + if (imx_src_is_m4_enabled()) + return clk_hw_register_fixed_factor(NULL, name, parent, + CLK_SET_RATE_PARENT, 1, 1); + else + return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, reg, shift, 0, &imx_ccm_lock); } @@ -394,6 +454,15 @@ static inline struct clk_hw *imx_clk_hw_mux(const char *name, void __iomem *reg, width, 0, &imx_ccm_lock); } +static inline struct clk *imx_dev_clk_mux(struct device *dev, const char *name, + void __iomem *reg, u8 shift, u8 width, + const char * const *parents, int num_parents) +{ + return clk_register_mux(dev, name, parents, num_parents, + CLK_SET_RATE_NO_REPARENT | CLK_SET_PARENT_GATE, + reg, shift, width, 0, &imx_ccm_lock); +} + static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents) @@ -424,6 +493,16 @@ static inline struct clk *imx_clk_mux_flags(const char *name, &imx_ccm_lock); } +static inline struct clk *imx_dev_clk_mux_flags(struct device *dev, + const char *name, void __iomem *reg, u8 shift, + u8 width, const char * const *parents, int num_parents, + unsigned long flags) +{ + return clk_register_mux(dev, name, parents, num_parents, + flags | CLK_SET_RATE_NO_REPARENT | CLK_SET_PARENT_GATE, + reg, shift, width, 0, &imx_ccm_lock); +} + static inline struct clk *imx_clk_mux2_flags(const char *name, void __iomem *reg, u8 shift, u8 width, const char * const *parents, @@ -446,6 +525,14 @@ static inline struct clk_hw *imx_clk_hw_mux_flags(const char *name, reg, shift, width, 0, &imx_ccm_lock); } +static inline struct clk *imx_clk_pll14xx(const char *name, + const char *parent_name, + void __iomem *base, + const struct imx_pll14xx_clk *pll_clk) +{ + return imx_dev_clk_pll14xx(NULL, name, parent_name, base, pll_clk); +} + struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name, struct clk *div, struct clk *mux, struct clk *pll, struct clk *step); @@ -470,4 +557,7 @@ struct clk_hw *imx_clk_divider_gate(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock); + +void clk_set_delta_k(struct clk_hw *hw, short int delta_k); +void clk_get_pll_setting(struct clk_hw *hw, u32 *pll_div_ctrl0, u32 *pll_div_ctrl1); #endif diff --git a/drivers/clk/s32/Kconfig b/drivers/clk/s32/Kconfig new file mode 100644 index 00000000000000..c28bdbbfaa3aff --- /dev/null +++ b/drivers/clk/s32/Kconfig @@ -0,0 +1,4 @@ +config ARCH_S32_CLK + bool "Enable S32 CLK Framework" + help + Support for the Clock Framework on S32 SoCs. diff --git a/drivers/clk/s32/Makefile b/drivers/clk/s32/Makefile new file mode 100644 index 00000000000000..169b8b5900f9bd --- /dev/null +++ b/drivers/clk/s32/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_ARCH_S32_CLK) += clk-core.o +obj-$(CONFIG_ARCH_S32_CLK) += s32v234/ diff --git a/drivers/clk/s32/clk-core.c b/drivers/clk/s32/clk-core.c new file mode 100644 index 00000000000000..a8cca66f7959c8 --- /dev/null +++ b/drivers/clk/s32/clk-core.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ + +#include +#include +#include +#include +#include +#include "clk.h" + +void __init s32_check_clocks(struct clk *clks[], unsigned int count) +{ + unsigned int i; + + for (i = 0; i < count; i++) + if (IS_ERR(clks[i])) + pr_err("S32 clk %u: register failed with %ld\n", + i, PTR_ERR(clks[i])); +} + +static struct clk * __init s32_obtain_fixed_clock_from_dt(const char *name) +{ + struct of_phandle_args phandle; + struct clk *clk = ERR_PTR(-ENODEV); + char *path; + + path = kasprintf(GFP_KERNEL, "/clocks/%s", name); + if (!path) + return ERR_PTR(-ENOMEM); + + phandle.np = of_find_node_by_path(path); + kfree(path); + + if (phandle.np) { + clk = of_clk_get_from_provider(&phandle); + of_node_put(phandle.np); + } + return clk; +} + +struct clk * __init s32_obtain_fixed_clock( + const char *name, unsigned long rate) +{ + struct clk *clk; + + clk = s32_obtain_fixed_clock_from_dt(name); + if (IS_ERR(clk)) + clk = s32_clk_fixed(name, rate); + return clk; +} diff --git a/drivers/clk/s32/clk.h b/drivers/clk/s32/clk.h new file mode 100644 index 00000000000000..83100641158f4c --- /dev/null +++ b/drivers/clk/s32/clk.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + */ + +#ifndef __MACH_S32_CLK_H +#define __MACH_S32_CLK_H + +#include +#include + +#define PNAME(x) \ + static const char *x[] __initconst + +void s32_check_clocks(struct clk *clks[], unsigned int count); + +struct clk *s32_obtain_fixed_clock( + const char *name, unsigned long rate); + +static inline struct clk *s32_clk_fixed(const char *name, unsigned long rate) +{ + return clk_register_fixed_rate(NULL, name, NULL, 0, rate); +} + +static inline struct clk *s32_clk_divider(const char *name, const char *parent, + void __iomem *reg, u8 shift, u8 width, + spinlock_t *lock) +{ + struct clk *tmp_clk = clk_register_divider(NULL, name, parent, + CLK_SET_RATE_PARENT, + reg, shift, width, 0, lock); + + return tmp_clk; +} + +static inline struct clk *s32_clk_mux(const char *name, void __iomem *reg, + u8 shift, u8 width, const char **parents, + u8 num_parents, spinlock_t *lock) +{ + return clk_register_mux(NULL, name, parents, num_parents, + CLK_SET_RATE_NO_REPARENT, reg, shift, + width, 0, lock); +} + +static inline struct clk *s32_clk_fixed_factor(const char *name, + const char *parent, + unsigned int mult, + unsigned int div) +{ + return clk_register_fixed_factor(NULL, name, parent, + CLK_SET_RATE_PARENT, mult, div); +} + +#endif diff --git a/drivers/clk/s32/s32v234/Makefile b/drivers/clk/s32/s32v234/Makefile new file mode 100644 index 00000000000000..7ddf9f4b5d8183 --- /dev/null +++ b/drivers/clk/s32/s32v234/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_ARCH_S32_CLK) += clk.o clk-plldig.o clk-dfs.o diff --git a/drivers/clk/s32/s32v234/clk-dfs.c b/drivers/clk/s32/s32v234/clk-dfs.c new file mode 100644 index 00000000000000..2bd569e13a184b --- /dev/null +++ b/drivers/clk/s32/s32v234/clk-dfs.c @@ -0,0 +1,236 @@ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include "clk.h" + +/** + * struct clk_dfs - S32 DFS clock + * @clk_hw: clock source + * @reg: DFS register address + * @idx: the index of DFS encoded in the register + * + * DFS clock found on S32 series. Each register for DFS has 4 clk_dfs + * data encoded, and member idx is used to specify the one. + * Only ARMPLL(3 DFS), ENETPLL(4 DFS) and DDRPLL(3 DFS) has DFS outputs. + */ +struct clk_dfs { + struct clk_hw hw; + void __iomem *reg; + enum s32v234_plldig_type plltype; + u8 idx; + u32 mfn; +}; + +#define to_clk_dfs(_hw) container_of(_hw, struct clk_dfs, hw) + +static int get_pllx_dfs_nr(enum s32v234_plldig_type plltype) +{ + switch (plltype) { + case S32_PLLDIG_ARM: + return ARMPLL_DFS_NR; + case S32_PLLDIG_ENET: + return ENETPLL_DFS_NR; + case S32_PLLDIG_DDR: + return DDRPLL_DFS_NR; + case S32_PLLDIG_PERIPH: + case S32_PLLDIG_VIDEO: + pr_warn("Current selected PLL has no DFS\n"); + break; + } + + return -EINVAL; +} +static unsigned long get_pllx_dfsy_max_rate(enum s32v234_plldig_type plltype, + int dfsno) +{ + switch (plltype) { + case S32_PLLDIG_ARM: + switch (dfsno) { + case 0: + return ARMPLL_DFS0_MAX_RATE; + case 1: + return ARMPLL_DFS1_MAX_RATE; + case 2: + return ARMPLL_DFS2_MAX_RATE; + } + break; + case S32_PLLDIG_ENET: + switch (dfsno) { + case 0: + return ENETPLL_DFS0_MAX_RATE; + case 1: + return ENETPLL_DFS1_MAX_RATE; + case 2: + return ENETPLL_DFS2_MAX_RATE; + case 3: + return ENETPLL_DFS3_MAX_RATE; + } + break; + case S32_PLLDIG_DDR: + switch (dfsno) { + case 0: + return DDRPLL_DFS0_MAX_RATE; + case 1: + return DDRPLL_DFS1_MAX_RATE; + case 2: + return DDRPLL_DFS2_MAX_RATE; + } + break; + case S32_PLLDIG_PERIPH: + case S32_PLLDIG_VIDEO: + pr_warn("Current selected PLL has no DFS."); + break; + default: + pr_warn("Unsupported PLL. Use %d or %d\n", + S32_PLLDIG_ARM, S32_PLLDIG_VIDEO); + break; + } + + return -EINVAL; +} +static int clk_dfs_enable(struct clk_hw *hw) +{ + /* + * TODO: When SOC is available, this function + * should be tested and implemented for DFS + * if it is possible + */ + return 0; +} + +static void clk_dfs_disable(struct clk_hw *hw) +{ + /* + * TODO: When SOC is available, this function + * should be tested and implemented for DFS + * if it is possible + */ +} + +static unsigned long clk_dfs_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_dfs *dfs = to_clk_dfs(hw); + u32 mfn, mfi, rate; + u32 dvport = readl_relaxed(DFS_DVPORTn(dfs->reg, dfs->idx)); + + mfn = (dvport & DFS_DVPORTn_MFN_MASK) >> DFS_DVPORTn_MFN_OFFSET; + mfi = (dvport & DFS_DVPORTn_MFI_MASK) >> DFS_DVPORTn_MFI_OFFSET; + mfi <<= 8; + rate = parent_rate / (mfi + mfn); + rate <<= 8; + + return rate; +} + +static long clk_dfs_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_dfs *dfs = to_clk_dfs(hw); + unsigned long max_allowed_rate; + + max_allowed_rate = get_pllx_dfsy_max_rate(dfs->plltype, dfs->idx); + + if (rate > max_allowed_rate) + rate = max_allowed_rate; + + return rate; +} + +static int clk_dfs_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_dfs *dfs = to_clk_dfs(hw); + u32 mfi; + u32 portreset = readl_relaxed(DFS_PORTRESET(dfs->reg)); + + writel_relaxed(DFS_CTRL_DLL_RESET, DFS_CTRL(dfs->reg)); + writel_relaxed(portreset | ~DFS_PORTRESET_PORTRESET_SET(dfs->idx), + DFS_PORTRESET(dfs->reg)); + + mfi = parent_rate/rate; + writel_relaxed(DFS_DVPORTn_MFI_SET(mfi) | + DFS_DVPORTn_MFN_SET(dfs->mfn), + DFS_DVPORTn(dfs->reg, dfs->idx)); + + writel_relaxed(~DFS_CTRL_DLL_RESET, DFS_CTRL(dfs->reg)); + + while (readl_relaxed(DFS_PORTSR(dfs->reg)) & (1 << (dfs->idx))) + ; + + return 0; +} + +static int clk_dfs_is_enabled(struct clk_hw *hw) +{ + struct clk_dfs *dfs = to_clk_dfs(hw); + + /* Check if current DFS output port is locked */ + if (readl_relaxed(DFS_PORTSR(dfs->reg)) & (1 << (dfs->idx))) + return 0; + + return 1; +} + +static const struct clk_ops clk_dfs_ops = { + .enable = clk_dfs_enable, + .disable = clk_dfs_disable, + .recalc_rate = clk_dfs_recalc_rate, + .round_rate = clk_dfs_round_rate, + .set_rate = clk_dfs_set_rate, + .is_enabled = clk_dfs_is_enabled, +}; + +struct clk *s32v234_clk_dfs(enum s32v234_plldig_type type, const char *name, + const char *parent_name, void __iomem *reg, + u8 idx, u32 mfn) +{ + struct clk_dfs *dfs; + struct clk *clk; + struct clk_init_data init; + + /* PERIPH and VIDEO PLL do not have DFS */ + if (type == S32_PLLDIG_PERIPH || type == S32_PLLDIG_VIDEO) + return ERR_PTR(-EINVAL); + + /* check if DFS index is valid for current pll */ + if (idx >= get_pllx_dfs_nr(type)) + return ERR_PTR(-EINVAL); + + dfs = kzalloc(sizeof(*dfs), GFP_KERNEL); + if (!dfs) + return ERR_PTR(-ENOMEM); + + dfs->reg = reg; + dfs->idx = idx; + dfs->mfn = mfn; + dfs->plltype = type; + + init.name = name; + init.ops = &clk_dfs_ops; + init.flags = 0; + init.parent_names = &parent_name; + init.num_parents = 1; + + dfs->hw.init = &init; + + clk = clk_register(NULL, &dfs->hw); + if (IS_ERR(clk)) + kfree(dfs); + + return clk; +} diff --git a/drivers/clk/s32/s32v234/clk-plldig.c b/drivers/clk/s32/s32v234/clk-plldig.c new file mode 100644 index 00000000000000..6ed23974ee6361 --- /dev/null +++ b/drivers/clk/s32/s32v234/clk-plldig.c @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include "clk.h" + +/* + * struct clk_plldig - S32 PLLDIG clock + * @clk_hw: clock source + * @base: base address of PLL registers + * @plldv_mfd: multiplication loop factor divider + * @plldv_rfdphi: PHI reduced frequency divider + * @plldv_rfdphi1: PHI reduced frequency divider + * + * PLLDIG clock version 1, found on S32 series. + */ +struct clk_plldig { + struct clk_hw hw; + void __iomem *base; + enum s32v234_plldig_type type; + u32 plldv_mfd; + u32 pllfd_mfn; + u32 plldv_rfdphi; + u32 plldv_rfdphi1; +}; + +#define to_clk_plldig(_hw) container_of(_hw, struct clk_plldig, hw) + +static unsigned long get_pllx_max_vco_rate(enum s32v234_plldig_type plltype) +{ + switch (plltype) { + case S32_PLLDIG_PERIPH: + return PERIPHPLL_MAX_VCO_RATE; + default: + pr_warn("Unsupported PLL.\n"); + return -EINVAL; + } +} + +static unsigned long get_pllx_phiy_max_rate(enum s32v234_plldig_type plltype, + unsigned int phino) +{ + switch (plltype) { + case S32_PLLDIG_PERIPH: + switch (phino) { + case 0: + return PERIPHPLL_MAX_PHI0_MAX_RATE; + case 1: + return PERIPHPLL_MAX_PHI1_MAX_RATE; + default: + break; + } + break; + default: + pr_warn("Unsupported PLL.\n"); + break; + } + return -EINVAL; +} + +static int clk_plldig_prepare(struct clk_hw *hw) +{ + return 0; +} + +static void clk_plldig_unprepare(struct clk_hw *hw) +{ +} + +static unsigned long clk_plldig_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_plldig *pll = to_clk_plldig(hw); + u32 plldv = readl_relaxed(PLLDIG_PLLDV(pll->base)); + u32 pllfd = readl_relaxed(PLLDIG_PLLFD(pll->base)); + u32 prediv, mfd, mfn, vco; + + prediv = (plldv & PLLDIG_PLLDV_PREDIV_MASK) + >> PLLDIG_PLLDV_PREDIV_OFFSET; + mfd = (plldv & PLLDIG_PLLDV_MFD_MASK); + + mfn = (pllfd & PLLDIG_PLLFD_MFN_MASK); + + if (prediv == 0) + prediv = 1; + + /* + * This formula is from platform reference manual + * (Rev. 1, 6/2015), PLLDIG chapter. + */ + vco = (parent_rate / prediv) * (mfd + mfn / 20480); + + return vco; +} + +static long clk_plldig_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_plldig *pll = to_clk_plldig(hw); + unsigned long max_allowed_rate = get_pllx_max_vco_rate(pll->type); + + if (rate > max_allowed_rate) + rate = max_allowed_rate; + else if (rate < MIN_VCO_RATE) + rate = MIN_VCO_RATE; + + return rate; +} + +static int clk_plldig_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_plldig *pll = to_clk_plldig(hw); + u32 pllfd, prediv; + + unsigned long max_allowed_rate = get_pllx_max_vco_rate(pll->type); + unsigned long phi0_max_rate = get_pllx_phiy_max_rate(pll->type, 0); + unsigned long phi1_max_rate = get_pllx_phiy_max_rate(pll->type, 1); + + if (rate < MIN_VCO_RATE || rate > max_allowed_rate) + return -EINVAL; + + if (((rate / pll->plldv_rfdphi) > phi0_max_rate) || + ((rate / pll->plldv_rfdphi) > phi1_max_rate)) + return -EINVAL; + + pllfd = readl_relaxed(PLLDIG_PLLFD(pll->base)); + prediv = (parent_rate / rate) * + (pll->plldv_mfd + pll->pllfd_mfn / 20480); + + writel_relaxed(PLLDIG_PLLDV_RFDPHI1_SET(pll->plldv_rfdphi1) | + PLLDIG_PLLDV_RFDPHI_SET(pll->plldv_rfdphi) | + PLLDIG_PLLDV_PREDIV_SET(prediv) | + PLLDIG_PLLDV_MFD_SET(pll->plldv_mfd), + PLLDIG_PLLDV(pll->base)); + + writel_relaxed(pllfd | PLLDIG_PLLFD_MFN_SET(pll->pllfd_mfn), + PLLDIG_PLLFD(pll->base)); + + /* + * To be implemented the wait_lock or an equivalent state + * return clk_plldig_wait_lock(pll); + */ + return 0; +} + +static const struct clk_ops clk_plldig_ops = { + .prepare = clk_plldig_prepare, + .unprepare = clk_plldig_unprepare, + .recalc_rate = clk_plldig_recalc_rate, + .round_rate = clk_plldig_round_rate, + .set_rate = clk_plldig_set_rate, +}; + +struct clk *s32v234_clk_plldig_phi(enum s32v234_plldig_type type, + const char *name, const char *parent, + void __iomem *base, u32 phi) +{ + u32 plldv, rfd_phi; + + if (!base) + return ERR_PTR(-ENOMEM); + + plldv = readl_relaxed(PLLDIG_PLLDV(base)); + + switch (phi) { + /* PHI0 */ + case 0: + rfd_phi = (plldv & PLLDIG_PLLDV_RFDPHI_MASK) + >> PLLDIG_PLLDV_RFDPHI_OFFSET; + break; + /* PHI1 */ + case 1: + rfd_phi = (plldv & PLLDIG_PLLDV_RFDPHI1_MASK) + >> PLLDIG_PLLDV_RFDPHI1_OFFSET; + + if (rfd_phi == 0) + rfd_phi = 1; + + break; + default: + return ERR_PTR(-EINVAL); + } + + return clk_register_fixed_factor(NULL, name, parent, + CLK_SET_RATE_PARENT, 1, rfd_phi); +} + +struct clk *s32v234_clk_plldig(enum s32v234_plldig_type type, const char *name, + const char *parent_name, void __iomem *base, + u32 plldv_mfd, u32 pllfd_mfn, + u32 plldv_rfdphi, u32 plldv_rfdphi1) +{ + struct clk_plldig *pll; + const struct clk_ops *ops; + struct clk *clk; + struct clk_init_data init; + + if (plldv_rfdphi > PLLDIG_PLLDV_RFDPHI_MAXVALUE) + return ERR_PTR(-EINVAL); + + if (plldv_rfdphi1 > PLLDIG_PLLDV_RFDPHI1_MAXVALUE) + return ERR_PTR(-EINVAL); + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + ops = &clk_plldig_ops; + + pll->base = base; + pll->type = type; + pll->plldv_mfd = plldv_mfd; + pll->pllfd_mfn = pllfd_mfn; + pll->plldv_rfdphi = plldv_rfdphi; + pll->plldv_rfdphi1 = plldv_rfdphi1; + + init.name = name; + init.ops = ops; + init.flags = 0; + init.parent_names = &parent_name; + init.num_parents = 1; + + pll->hw.init = &init; + + clk = clk_register(NULL, &pll->hw); + if (IS_ERR(clk)) + kfree(pll); + + return clk; +} diff --git a/drivers/clk/s32/s32v234/clk.c b/drivers/clk/s32/s32v234/clk.c new file mode 100644 index 00000000000000..ad88c6b45c6b7f --- /dev/null +++ b/drivers/clk/s32/s32v234/clk.c @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + */ + +#include +#include +#include + +#include "clk.h" + +static void __iomem *mc_cgm0_base; +static void __iomem *mc_cgm1_base; +static void __iomem *mc_cgm2_base; +static void __iomem *mc_cgm3_base; +static void __iomem *mc_me_base; +static void __iomem *src_base; + +DEFINE_SPINLOCK(s32v234_lock); + +/* sources for multiplexer clocks, this is used multiple times */ +PNAME(osc_sels) = {"firc", "fxosc", }; + +PNAME(sys_sels) = {"firc", "fxosc", "armpll_dfs0", }; + +PNAME(can_sels) = {"firc", "fxosc", "dummy", + "periphpll_phi0_div5", }; + +PNAME(lin_sels) = {"firc", "fxosc", "dummy", + "periphpll_phi0_div3", "dummy", "dummy", + "dummy", "dummy", "sys6",}; + +PNAME(sdhc_sels) = {"firc", "fxosc", "dummy", "dummy", + "enetpll_dfs3",}; + +PNAME(enet_sels) = {"firc", "fxosc", "dummy", + "dummy", "enetpll_phi0",}; + +PNAME(enet_time_sels) = {"firc", "fxosc", "dummy", + "dummy", "enetpll_phi0",}; + +static struct clk *clk[S32V234_CLK_END]; +static struct clk_onecell_data clk_data; + +static void __init s32v234_clocks_init(struct device_node *mc_cgm0_node) +{ + struct device_node *np; + + clk[S32V234_CLK_DUMMY] = s32_clk_fixed("dummy", 0); + clk[S32V234_CLK_FXOSC] = s32_obtain_fixed_clock("fxosc", 0); + clk[S32V234_CLK_FIRC] = s32_obtain_fixed_clock("firc", 0); + + np = of_find_compatible_node(NULL, NULL, "fsl,s32v234-mc_me"); + mc_me_base = of_iomap(np, 0); + if (WARN_ON(!mc_me_base)) + return; + + np = of_find_compatible_node(NULL, NULL, "fsl,s32v234-src"); + src_base = of_iomap(np, 0); + if (WARN_ON(!src_base)) + return; + + np = of_find_compatible_node(NULL, NULL, "fsl,s32v234-mc_cgm1"); + mc_cgm1_base = of_iomap(np, 0); + if (WARN_ON(!mc_cgm1_base)) + return; + + np = of_find_compatible_node(NULL, NULL, "fsl,s32v234-mc_cgm2"); + mc_cgm2_base = of_iomap(np, 0); + if (WARN_ON(!mc_cgm2_base)) + return; + + np = of_find_compatible_node(NULL, NULL, "fsl,s32v234-mc_cgm3"); + mc_cgm3_base = of_iomap(np, 0); + if (WARN_ON(!mc_cgm3_base)) + return; + + np = mc_cgm0_node; + mc_cgm0_base = of_iomap(np, 0); + if (WARN_ON(!mc_cgm0_base)) + return; + + enable_cpumodes_onperipheralconfig(mc_me_base, MC_ME_RUN_PCn_DRUN | + MC_ME_RUN_PCn_RUN0 | + MC_ME_RUN_PCn_RUN1 | + MC_ME_RUN_PCn_RUN2 | + MC_ME_RUN_PCn_RUN3, + 0); + + /* turn on XOSC and FIRC */ + enable_clocks_sources(MC_ME_MODE_MC_MVRON, MC_ME_MODE_MC_XOSCON | + MC_ME_MODE_MC_FIRCON, + MC_ME_RUNn_MC(mc_me_base, 0)); + + /* transition the core to RUN0 mode */ + entry_to_target_mode(mc_me_base, MC_ME_MCTL_RUN0); + + clk[S32V234_CLK_ARMPLL_SRC_SEL] = s32_clk_mux("armpll_sel", + SRC_GPR1, SRC_GPR1_ARMPLL_SRC_SEL_OFFSET, + SRC_GPR1_XPLL_SRC_SEL_SIZE, + osc_sels, ARRAY_SIZE(osc_sels), &s32v234_lock); + + clk[S32V234_CLK_PERIPHPLL_SRC_SEL] = s32_clk_mux("periphpll_sel", + SRC_GPR1, SRC_GPR1_PERIPHPLL_SRC_SEL_OFFSET, + SRC_GPR1_XPLL_SRC_SEL_SIZE, + osc_sels, ARRAY_SIZE(osc_sels), &s32v234_lock); + + clk[S32V234_CLK_ENETPLL_SRC_SEL] = s32_clk_mux("enetpll_sel", + SRC_GPR1, SRC_GPR1_ENETPLL_SRC_SEL_OFFSET, + SRC_GPR1_XPLL_SRC_SEL_SIZE, + osc_sels, ARRAY_SIZE(osc_sels), &s32v234_lock); + + /* ARM_PLL */ + clk[S32V234_CLK_ARMPLL_VCO] = s32v234_clk_plldig(S32_PLLDIG_ARM, + "armpll_vco", "armpll_sel", ARMPLL_PLLDIG(mc_cgm0_base), + ARMPLL_PLLDIG_PLLDV_MFD, ARMPLL_PLLDIG_PLLDV_MFN, + ARMPLL_PLLDIG_PLLDV_RFDPHI0, ARMPLL_PLLDIG_PLLDV_RFDPHI1); + + clk[S32V234_CLK_ARMPLL_PHI0] = s32v234_clk_plldig_phi(S32_PLLDIG_ARM, + "armpll_phi0", "armpll_vco", + ARMPLL_PLLDIG(mc_cgm0_base), 0); + + clk[S32V234_CLK_ARMPLL_PHI1] = s32v234_clk_plldig_phi(S32_PLLDIG_ARM, + "armpll_phi1", "armpll_vco", + ARMPLL_PLLDIG(mc_cgm0_base), 1); + + clk[S32V234_CLK_ARMPLL_DFS0] = s32v234_clk_dfs(S32_PLLDIG_ARM, + "armpll_dfs0", "armpll_phi1", + ARMPLL_PLLDIG_DFS(mc_cgm0_base), 0, + ARMPLL_PLLDIG_DFS0_MFN); + + clk[S32V234_CLK_ARMPLL_DFS1] = s32v234_clk_dfs(S32_PLLDIG_ARM, + "armpll_dfs1", "armpll_phi1", + ARMPLL_PLLDIG_DFS(mc_cgm0_base), 1, + ARMPLL_PLLDIG_DFS1_MFN); + + clk[S32V234_CLK_ARMPLL_DFS2] = s32v234_clk_dfs(S32_PLLDIG_ARM, + "armpll_dfs2", "armpll_phi1", + ARMPLL_PLLDIG_DFS(mc_cgm0_base), 2, + ARMPLL_PLLDIG_DFS2_MFN); + + clk[S32V234_CLK_SYS_SEL] = s32_clk_mux("sys_sel", + MC_ME_RUNn_MC(mc_me_base, 0), + MC_ME_MODE_MC_SYSCLK_OFFSET, + MC_ME_MODE_MC_SYSCLK_SIZE, + sys_sels, ARRAY_SIZE(sys_sels), &s32v234_lock); + + clk[S32V234_CLK_SYS3] = s32_clk_divider("sys3", "sys_sel", + CGM_SC_DCn(mc_cgm0_base, 0), MC_CGM_SC_DCn_PREDIV_OFFSET, + MC_CGM_SC_DCn_PREDIV_SIZE, &s32v234_lock); + + clk[S32V234_CLK_SYS6] = s32_clk_divider("sys6", "sys_sel", + CGM_SC_DCn(mc_cgm0_base, 1), MC_CGM_SC_DCn_PREDIV_OFFSET, + MC_CGM_SC_DCn_PREDIV_SIZE, &s32v234_lock); + + clk[S32V234_CLK_SYS6_DIV2] = s32_clk_divider("sys6_div2", "sys_sel", + CGM_SC_DCn(mc_cgm0_base, 2), MC_CGM_SC_DCn_PREDIV_OFFSET, + MC_CGM_SC_DCn_PREDIV_SIZE, &s32v234_lock); + + /* PERIPH_PLL */ + clk[S32V234_CLK_PERIPHPLL_VCO] = s32v234_clk_plldig(S32_PLLDIG_PERIPH, + "periphpll_vco", "periphpll_sel", + PERIPHPLL_PLLDIG(mc_cgm0_base), + PERIPHPLL_PLLDIG_PLLDV_MFD, PERIPHPLL_PLLDIG_PLLDV_MFN, + PERIPHPLL_PLLDIG_PLLDV_RFDPHI0, + PERIPHPLL_PLLDIG_PLLDV_RFDPHI1); + + clk[S32V234_CLK_PERIPHPLL_PHI0] = + s32v234_clk_plldig_phi(S32_PLLDIG_PERIPH, + "periphpll_phi0", "periphpll_vco", + PERIPHPLL_PLLDIG(mc_cgm0_base), 0); + + clk[S32V234_CLK_PERIPHPLL_PHI1] = + s32v234_clk_plldig_phi(S32_PLLDIG_PERIPH, + "periphpll_phi1", "periphpll_vco", + PERIPHPLL_PLLDIG(mc_cgm0_base), 1); + + clk[S32V234_CLK_PERIPHPLL_PHI0_DIV3] = s32_clk_fixed_factor( + "periphpll_phi0_div3", "periphpll_phi0", 1, 3); + + clk[S32V234_CLK_PERIPHPLL_PHI0_DIV5] = s32_clk_fixed_factor( + "periphpll_phi0_div5", "periphpll_phi0", 1, 5); + + clk[S32V234_CLK_CAN_SEL] = s32_clk_mux("can_sel", + CGM_ACn_SC(mc_cgm0_base, 6), + MC_CGM_ACn_SEL_OFFSET, + MC_CGM_ACn_SEL_SIZE, + can_sels, ARRAY_SIZE(can_sels), &s32v234_lock); + + /* CAN Clock */ + clk[S32V234_CLK_CAN] = s32_clk_divider("can", "can_sel", + CGM_ACn_DCm(mc_cgm0_base, 6, 0), + MC_CGM_ACn_DCm_PREDIV_OFFSET, + MC_CGM_ACn_DCm_PREDIV_SIZE, &s32v234_lock); + + /* Lin Clock */ + clk[S32V234_CLK_LIN_SEL] = s32_clk_mux("lin_sel", + CGM_ACn_SC(mc_cgm0_base, 3), + MC_CGM_ACn_SEL_OFFSET, + MC_CGM_ACn_SEL_SIZE, + lin_sels, ARRAY_SIZE(lin_sels), &s32v234_lock); + + clk[S32V234_CLK_LIN] = s32_clk_divider("lin", "lin_sel", + CGM_ACn_DCm(mc_cgm0_base, 3, 0), + MC_CGM_ACn_DCm_PREDIV_OFFSET, + MC_CGM_ACn_DCm_PREDIV_SIZE, &s32v234_lock); + + clk[S32V234_CLK_LIN_IPG] = s32_clk_fixed_factor("lin_ipg", + "lin", 1, 2); + + /* enable PERIPHPLL */ + enable_clocks_sources(0, MC_ME_MODE_MC_PERIPHPLL, + MC_ME_RUNn_MC(mc_me_base, 0)); + + /* ENET_PLL */ + clk[S32V234_CLK_ENETPLL_VCO] = s32v234_clk_plldig(S32_PLLDIG_ENET, + "enetpll_vco", "enetpll_sel", ENETPLL_PLLDIG(mc_cgm0_base), + ENETPLL_PLLDIG_PLLDV_MFD, ENETPLL_PLLDIG_PLLDV_MFN, + ENETPLL_PLLDIG_PLLDV_RFDPHI0, ENETPLL_PLLDIG_PLLDV_RFDPHI1); + + clk[S32V234_CLK_ENETPLL_PHI0] = s32v234_clk_plldig_phi(S32_PLLDIG_ENET, + "enetpll_phi0", "enetpll_vco", + ENETPLL_PLLDIG(mc_cgm0_base), 0); + + clk[S32V234_CLK_ENETPLL_PHI1] = s32v234_clk_plldig_phi(S32_PLLDIG_ENET, + "enetpll_phi1", "enetpll_vco", + ENETPLL_PLLDIG(mc_cgm0_base), 1); + + clk[S32V234_CLK_ENETPLL_DFS0] = s32v234_clk_dfs(S32_PLLDIG_ENET, + "enetpll_dfs0", "enetpll_phi1", + ENETPLL_PLLDIG_DFS(mc_cgm0_base), 0, + ENETPLL_PLLDIG_DFS0_MFN); + + clk[S32V234_CLK_ENETPLL_DFS1] = s32v234_clk_dfs(S32_PLLDIG_ENET, + "enetpll_dfs1", "enetpll_phi1", + ENETPLL_PLLDIG_DFS(mc_cgm0_base), 1, + ENETPLL_PLLDIG_DFS1_MFN); + + clk[S32V234_CLK_ENETPLL_DFS2] = s32v234_clk_dfs(S32_PLLDIG_ENET, + "enetpll_dfs2", "enetpll_phi1", + ENETPLL_PLLDIG_DFS(mc_cgm0_base), 2, + ENETPLL_PLLDIG_DFS2_MFN); + + clk[S32V234_CLK_ENETPLL_DFS3] = s32v234_clk_dfs(S32_PLLDIG_ENET, + "enetpll_dfs3", "enetpll_phi1", + ENETPLL_PLLDIG_DFS(mc_cgm0_base), 3, + ENETPLL_PLLDIG_DFS3_MFN); + + /* ENET Clock */ + clk[S32V234_CLK_ENET_SEL] = s32_clk_mux("enet_sel", + CGM_ACn_SC(mc_cgm2_base, 2), + MC_CGM_ACn_SEL_OFFSET, + MC_CGM_ACn_SEL_SIZE, + enet_sels, ARRAY_SIZE(enet_sels), &s32v234_lock); + + clk[S32V234_CLK_ENET_TIME_SEL] = s32_clk_mux("enet_time_sel", + CGM_ACn_SC(mc_cgm0_base, 7), + MC_CGM_ACn_SEL_OFFSET, + MC_CGM_ACn_SEL_SIZE, + enet_time_sels, ARRAY_SIZE(enet_time_sels), &s32v234_lock); + + clk[S32V234_CLK_ENET] = s32_clk_divider("enet", "enet_sel", + CGM_ACn_DCm(mc_cgm2_base, 2, 0), + MC_CGM_ACn_DCm_PREDIV_OFFSET, + MC_CGM_ACn_DCm_PREDIV_SIZE, &s32v234_lock); + + clk[S32V234_CLK_ENET_TIME] = s32_clk_divider("enet_time", + "enet_time_sel", + CGM_ACn_DCm(mc_cgm0_base, 7, 1), + MC_CGM_ACn_DCm_PREDIV_OFFSET, + MC_CGM_ACn_DCm_PREDIV_SIZE, &s32v234_lock); + + /* SDHC Clock */ + clk[S32V234_CLK_SDHC_SEL] = s32_clk_mux("sdhc_sel", + CGM_ACn_SC(mc_cgm0_base, 15), + MC_CGM_ACn_SEL_OFFSET, + MC_CGM_ACn_SEL_SIZE, + sdhc_sels, ARRAY_SIZE(sdhc_sels), &s32v234_lock); + + clk[S32V234_CLK_SDHC] = s32_clk_divider("sdhc", "sdhc_sel", + CGM_ACn_DCm(mc_cgm0_base, 15, 0), + MC_CGM_ACn_DCm_PREDIV_OFFSET, + MC_CGM_ACn_DCm_PREDIV_SIZE, &s32v234_lock); + + /* set the system clock */ + enable_sysclock(MC_ME_MODE_MC_SYSCLK(0x2), + MC_ME_RUNn_MC(mc_me_base, 0)); + + /* transition the core to RUN0 mode */ + entry_to_target_mode(mc_me_base, MC_ME_MCTL_RUN0); + + /* Add the clocks to provider list */ + clk_data.clks = clk; + clk_data.clk_num = ARRAY_SIZE(clk); + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); +} + +CLK_OF_DECLARE(S32V234, "fsl,s32v234-mc_cgm0", s32v234_clocks_init); diff --git a/drivers/clk/s32/s32v234/clk.h b/drivers/clk/s32/s32v234/clk.h new file mode 100644 index 00000000000000..82a2224833940a --- /dev/null +++ b/drivers/clk/s32/s32v234/clk.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + */ + +#ifndef __MACH_S32V234_CLK_H +#define __MACH_S32V234_CLK_H + +#include +#include +#include "mc_cgm.h" +#include "mc_me.h" +#include "pll.h" +#include "src.h" +#include "dfs.h" +#include "../clk.h" + +struct clk *s32v234_clk_plldig(enum s32v234_plldig_type type, const char *name, + const char *parent_name, void __iomem *base, + u32 plldv_mfd, u32 plldv_mfn, + u32 plldv_rfdphi, u32 plldv_rfdphi1); + +struct clk *s32v234_clk_plldig_phi(enum s32v234_plldig_type type, + const char *name, const char *parent, + void __iomem *base, u32 phi); + +struct clk *s32v234_clk_dfs(enum s32v234_plldig_type type, const char *name, + const char *parent_name, + void __iomem *reg, u8 idx, u32 mfn); +#endif diff --git a/drivers/clk/s32/s32v234/dfs.h b/drivers/clk/s32/s32v234/dfs.h new file mode 100644 index 00000000000000..be3104f7ae51fe --- /dev/null +++ b/drivers/clk/s32/s32v234/dfs.h @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#ifndef _DFS_S32V234_H +#define _DFS_S32V234_H + +/* DFS Control Register (DFS_CTRL) */ +#define DFS_CTRL(base) ((base) + 0x00000018) +#define DFS_CTRL_DLL_LOLIE (1 << 0) +#define DFS_CTRL_DLL_RESET (1 << 1) + +/* DFS Port Status (DFS_PORTSR) */ +#define DFS_PORTSR(base) ((base) + 0x0000000C) +#define DFS_PORTSR_MASK (0x0000000F) +#define DFS_PORTSR_OFFSET (28) + +/* DFS Port Reset Register (DFS_PORTRESET) */ +#define DFS_PORTRESET(base) ((base) + 0x00000014) +#define DFS_PORTRESET_PORTRESET_SET(val) \ + (DFS_PORTRESET_PORTRESET_MASK | \ + (((val) & DFS_PORTRESET_PORTRESET_MAXVAL) \ + << DFS_PORTRESET_PORTRESET_OFFSET)) +#define DFS_PORTRESET_PORTRESET_MAXVAL (0xF) +#define DFS_PORTRESET_PORTRESET_MASK (0x0000000F) +#define DFS_PORTRESET_PORTRESET_OFFSET (28) + +/* DFS Divide Register Portn (DFS_DVPORTn) */ +#define DFS_DVPORTn(base, n) ((base) + (0x0000001C + \ + ((n) * sizeof(u32)))) +#define DFS_DVPORTn_MFI_SET(val) (DFS_DVPORTn_MFI_MASK & \ + (((val) & DFS_DVPORTn_MFI_MAXVAL) \ + << DFS_DVPORTn_MFI_OFFSET)) +#define DFS_DVPORTn_MFN_SET(val) (DFS_DVPORTn_MFN_MASK & \ + (((val) & DFS_DVPORTn_MFN_MAXVAL) \ + << DFS_DVPORTn_MFN_OFFSET)) +#define DFS_DVPORTn_MFI_MASK (0x0000FF00) +#define DFS_DVPORTn_MFN_MASK (0x000000FF) +#define DFS_DVPORTn_MFI_MAXVAL (0xFF) +#define DFS_DVPORTn_MFN_MAXVAL (0xFF) +#define DFS_DVPORTn_MFI_OFFSET (8) +#define DFS_DVPORTn_MFN_OFFSET (0) +#define DFS_MAXNUMBER (4) + +/* + * Naming convention for PLL: + * ARMPLL - PLL0 + * PERIPHPLL - PLL1 + * ENETPLL - PLL2 + * DDRPLL - PLL3 + * VIDEOPLL - PLL4 + */ + +/* The max values for PLL DFS is in Hz */ +/* ARMPLL */ +#define ARMPLL_DFS0_MAX_RATE (266000000) +#define ARMPLL_DFS1_MAX_RATE (600000000) +#define ARMPLL_DFS2_MAX_RATE (600000000) +/* ENETPLL */ +#define ENETPLL_DFS0_MAX_RATE (350000000) +#define ENETPLL_DFS1_MAX_RATE (350000000) +#define ENETPLL_DFS2_MAX_RATE (416000000) +#define ENETPLL_DFS3_MAX_RATE (104000000) +/* DDRPLL */ +#define DDRPLL_DFS0_MAX_RATE (500000000) +#define DDRPLL_DFS1_MAX_RATE (500000000) +#define DDRPLL_DFS2_MAX_RATE (350000000) + +#define ARMPLL_DFS_NR (3) +#define ENETPLL_DFS_NR (4) +#define DDRPLL_DFS_NR (3) + +#endif diff --git a/drivers/clk/s32/s32v234/mc_cgm.h b/drivers/clk/s32/s32v234/mc_cgm.h new file mode 100644 index 00000000000000..aeac6877189071 --- /dev/null +++ b/drivers/clk/s32/s32v234/mc_cgm.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright (C) 2017 NXP + */ +#ifndef _MC_CGM_H +#define _MC_CGM_H + +#define ARMPLL_PLLDIG(mc_cgm) (mc_cgm) +#define ARMPLL_PLLDIG_DFS(mc_cgm) ((mc_cgm) + 0x40) +#define ARMPLL_PLLDIG_PLLDV_MFD (50) +#define ARMPLL_PLLDIG_PLLDV_MFN (0) +#define ARMPLL_PLLDIG_PLLDV_RFDPHI0 (1) +#define ARMPLL_PLLDIG_PLLDV_RFDPHI1 (1) +#define ARMPLL_PLLDIG_DFS0_MFN (195) +#define ARMPLL_PLLDIG_DFS1_MFN (171) +#define ARMPLL_PLLDIG_DFS2_MFN (171) + +#define PERIPHPLL_PLLDIG(mc_cgm) ((mc_cgm) + 0x80) +#define PERIPHPLL_PLLDIG_PLLDV_MFD (30) +#define PERIPHPLL_PLLDIG_PLLDV_MFN (0) +#define PERIPHPLL_PLLDIG_PLLDV_RFDPHI0 (0x1) +#define PERIPHPLL_PLLDIG_PLLDV_RFDPHI1 (0x1) + +#define ENETPLL_PLLDIG(mc_cgm) ((mc_cgm) + 0x100) +#define ENETPLL_PLLDIG_DFS(mc_cgm) ((mc_cgm) + 0x100 + 0x40) +#define ENETPLL_PLLDIG_PLLDV_MFD (50) +#define ENETPLL_PLLDIG_PLLDV_MFN (0) +#define ENETPLL_PLLDIG_PLLDV_RFDPHI0 (0x1) +#define ENETPLL_PLLDIG_PLLDV_RFDPHI1 (0x1) +#define ENETPLL_PLLDIG_DFS0_MFN (220) +#define ENETPLL_PLLDIG_DFS1_MFN (220) +#define ENETPLL_PLLDIG_DFS2_MFN (33) +#define ENETPLL_PLLDIG_DFS3_MFN (1) + +/* MC_CGM_SC_SS */ +#define CGM_SC_SS(mc_cgm) (((mc_cgm) + 0x7E4)) + +/* MC_CGM_SC_DCn */ +#define CGM_SC_DCn(mc_cgm, dc) (((mc_cgm) + 0x7E8) + ((dc) * 0x4)) + +#define MC_CGM_SC_DCn_PREDIV_OFFSET (16) +#define MC_CGM_SC_DCn_PREDIV_SIZE (3) +#define MC_CGM_SC_DCn_DE (1 << 31) +#define MC_CGM_SC_SEL_OFFSET (24) +#define MC_CGM_SC_SEL_SIZE (4) + +/* MC_CGM_ACn_DCm */ +#define CGM_ACn_DCm(mc_cgm, ac, dc) (((mc_cgm) + 0x808) + ((ac) * 0x20)\ + + ((dc) * 0x4)) + +#define MC_CGM_ACn_DCm_PREDIV(val) (MC_CGM_ACn_DCm_PREDIV_MASK & \ + ((val) \ + << MC_CGM_ACn_DCm_PREDIV_OFFSET)) +#define MC_CGM_ACn_DCm_PREDIV_MASK (0x001F0000) +#define MC_CGM_ACn_DCm_PREDIV_OFFSET (16) +#define MC_CGM_ACn_DCm_PREDIV_SIZE (5) +#define MC_CGM_ACn_DCm_DE (1 << 31) + +/* MC_CGM_ACn_SC/MC_CGM_ACn_SS */ +#define CGM_ACn_SC(mc_cgm, ac) (((mc_cgm) + 0x800) + ((ac) * 0x20)) +#define CGM_ACn_SS(mc_cgm, ac) (((mc_cgm) + 0x804) + ((ac) * 0x24)) +#define MC_CGM_ACn_SEL_MASK (0x07000000) +#define MC_CGM_ACn_SEL_SET(source) (MC_CGM_ACn_SEL_MASK & \ + (((source) & 0x7) \ + << MC_CGM_ACn_SEL_OFFSET)) +#define MC_CGM_ACn_SEL_OFFSET (24) +#define MC_CGM_ACn_SEL_SIZE (4) + +#endif diff --git a/drivers/clk/s32/s32v234/mc_me.h b/drivers/clk/s32/s32v234/mc_me.h new file mode 100644 index 00000000000000..718f1d1a0c30cb --- /dev/null +++ b/drivers/clk/s32/s32v234/mc_me.h @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright (C) 2017 NXP + */ + +#ifndef _MC_ME_H +#define _MC_ME_H + +/* MC_ME registers definitions */ +/* MC_ME_GS */ + #define MC_ME_GS(mc_me) ((mc_me) + 0x00000000) + +/* MC_ME_MCTL */ +#define MC_ME_MCTL(mc_me) ((mc_me) + 0x00000004) +#define MC_ME_MCTL_RESET (0x0 << 28) +#define MC_ME_MCTL_TEST (0x1 << 28) +#define MC_ME_MCTL_DRUN (0x3 << 28) +#define MC_ME_MCTL_RUN0 (0x4 << 28) +#define MC_ME_MCTL_RUN1 (0x5 << 28) +#define MC_ME_MCTL_RUN2 (0x6 << 28) +#define MC_ME_MCTL_RUN3 (0x7 << 28) + +#define MC_ME_GS_S_MTRANS (1 << 27) + +#define MC_ME_MCTL_KEY (0x00005AF0) +#define MC_ME_MCTL_INVERTEDKEY (0x0000A50F) + +/* + * MC_ME_RESET_MC/MC_ME_TEST_MC + * MC_ME_DRUN_MC + * MC_ME_RUNn_MC + */ +#define MC_ME_RESET_MC(mc_me) ((mc_me) + 0x00000020) +#define MC_ME_TEST_MC(mc_me) ((mc_me) + 0x00000024) +#define MC_ME_DRUN_MC(mc_me) ((mc_me) + 0x0000002C) +#define MC_ME_RUNn_MC(mc_me, n) ((mc_me) + 0x00000030 + 0x4 * (n)) +#define MC_ME_MODE_MC_SYSCLK_OFFSET (0) +#define MC_ME_MODE_MC_SYSCLK_SIZE (0x3) +#define MC_ME_MODE_MC_SYSCLK(val) (MC_ME_MODE_MC_SYSCLK_MASK & (val)) +#define MC_ME_MODE_MC_SYSCLK_MASK (0x0000000F) +#define MC_ME_MODE_MC_FIRCON (1 << 4) +#define MC_ME_MODE_MC_XOSCON (1 << 5) +#define MC_ME_MODE_MC_ARMPLL (1 << 6) +#define MC_ME_MODE_MC_PERIPHPLL (1 << 7) +#define MC_ME_MODE_MC_ENETPLL (1 << 8) +#define MC_ME_MODE_MC_DDRPLL (1 << 9) +#define MC_ME_MODE_MC_VIDEOPLL (1 << 10) +#define MC_ME_MODE_MC_MVRON (1 << 20) + +/* MC_ME_DRUN_SEC_CC_I */ +#define MC_ME_DRUN_SEC_CC_I(mc_me) ((mc_me) + 0x260) +/* MC_ME_RUNn_SEC_CC_I */ +#define MC_ME_RUNn_SEC_CC_I(mc_me, n) ((mc_me) + 0x270 + (n) * 0x10) +#define MC_ME_MODE_SEC_CC_I_SYSCLK1_OFFSET (4) +#define MC_ME_MODE_SEC_CC_I_SYSCLK2_OFFSET (8) +#define MC_ME_MODE_SEC_CC_I_SYSCLK3_OFFSET (12) +/* Consider only the defined clocks */ +#define MC_ME_MODE_SEC_CC_I_SYSCLK1_SIZE (0x3) +#define MC_ME_MODE_SEC_CC_I_SYSCLK2_SIZE (0x3) +#define MC_ME_MODE_SEC_CC_I_SYSCLK3_SIZE (0x3) + +/* MC_ME_RUN_PCn */ +#define MC_ME_RUN_PCn(mc_me, n) (mc_me + 0x00000080 + 0x4 * (n)) + +#define MC_ME_RUN_PCn_MAX_IDX (7) +#define MC_ME_RUN_PCn_RESET (1 << 0) +#define MC_ME_RUN_PCn_TEST (1 << 1) +#define MC_ME_RUN_PCn_DRUN (1 << 3) +#define MC_ME_RUN_PCn_RUN0 (1 << 4) +#define MC_ME_RUN_PCn_RUN1 (1 << 5) +#define MC_ME_RUN_PCn_RUN2 (1 << 6) +#define MC_ME_RUN_PCn_RUN3 (1 << 7) + +#define MC_ME_PCTLn(mc_me, n) (mc_me + 0xC0 + 4 * (n >> 2) + \ + (3 - (n) % 4)) + +static inline void entry_to_target_mode(void __iomem *mc_me, u32 mode) +{ + writel_relaxed(mode | MC_ME_MCTL_KEY, MC_ME_MCTL(mc_me)); + writel_relaxed(mode | MC_ME_MCTL_INVERTEDKEY, MC_ME_MCTL(mc_me)); + while ((readl_relaxed(MC_ME_GS(mc_me)) & + MC_ME_GS_S_MTRANS) != 0x00000000) + ; +} + +static inline void enable_cpumodes_onperipheralconfig(void __iomem *mc_me, + u32 modes, u32 run_pc_idx) +{ + WARN_ON(run_pc_idx > MC_ME_RUN_PCn_MAX_IDX); + if (run_pc_idx > MC_ME_RUN_PCn_MAX_IDX) + return; + + writel_relaxed(modes, MC_ME_RUN_PCn(mc_me, run_pc_idx)); +} + +static inline void enable_clocks_sources(u32 flags, u32 clks, + void __iomem *xrun_mc_addr) +{ + writel_relaxed(readl_relaxed(xrun_mc_addr) | flags | clks, + xrun_mc_addr); +} + +static inline void enable_sysclock(u32 clk, void __iomem *xrun_mc_addr) +{ + writel_relaxed(readl_relaxed(xrun_mc_addr) & clk, + xrun_mc_addr); +} + +#endif diff --git a/drivers/clk/s32/s32v234/pll.h b/drivers/clk/s32/s32v234/pll.h new file mode 100644 index 00000000000000..b7bcc50f0a2268 --- /dev/null +++ b/drivers/clk/s32/s32v234/pll.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright (C) 2017-2018 NXP + */ +#ifndef _PLL_S32V234_H +#define _PLL_S32V234_H + +/* PLLDIG PLL Divider Register (PLLDIG_PLLDV) */ +#define PLLDIG_PLLDV(base) ((base) + 0x00000028) +#define PLLDIG_PLLDV_MFD_SET(val) (PLLDIG_PLLDV_MFD_MASK & (val)) +#define PLLDIG_PLLDV_MFD_MASK (0x000000FF) + +#define PLLDIG_PLLDV_RFDPHI_SET(val) (PLLDIG_PLLDV_RFDPHI_MASK & \ + (((val) & \ + PLLDIG_PLLDV_RFDPHI_MAXVALUE) \ + << PLLDIG_PLLDV_RFDPHI_OFFSET)) +#define PLLDIG_PLLDV_RFDPHI_MASK (0x003F0000) +#define PLLDIG_PLLDV_RFDPHI_MAXVALUE (0x3F) + +#define PLLDIG_PLLDV_RFDPHI_OFFSET (16) + +#define PLLDIG_PLLDV_RFDPHI1_SET(val) (PLLDIG_PLLDV_RFDPHI1_MASK & \ + (((val) & \ + PLLDIG_PLLDV_RFDPHI1_MAXVALUE) \ + << PLLDIG_PLLDV_RFDPHI1_OFFSET)) +#define PLLDIG_PLLDV_RFDPHI1_MASK (0x7E000000) +#define PLLDIG_PLLDV_RFDPHI1_MAXVALUE (0x3F) +#define PLLDIG_PLLDV_RFDPHI1_OFFSET (25) + +#define PLLDIG_PLLDV_PREDIV_SET(val) (PLLDIG_PLLDV_PREDIV_MASK & \ + (((val) & \ + PLLDIG_PLLDV_PREDIV_MAXVALUE) \ + << PLLDIG_PLLDV_PREDIV_OFFSET)) +#define PLLDIG_PLLDV_PREDIV_MASK (0x00007000) +#define PLLDIG_PLLDV_PREDIV_MAXVALUE (0x7) +#define PLLDIG_PLLDV_PREDIV_OFFSET (12) + +/* PLLDIG PLL Fractional Divide Register (PLLDIG_PLLFD) */ +#define PLLDIG_PLLFD(base) ((base) + 0x00000030) +#define PLLDIG_PLLFD_MFN_SET(val) (PLLDIG_PLLFD_MFN_MASK & (val)) +#define PLLDIG_PLLFD_MFN_MASK (0x00007FFF) + +/* PLL Calibration Register 1 (PLLDIG_PLLCAL1) */ +#define PLLDIG_PLLCAL1(base) ((base) + 0x00000038) +#define PLLDIG_PLLCAL1_NDAC1_SET(val) (PLLDIG_PLLCAL1_NDAC1_MASK & \ + ((val) \ + << PLLDIG_PLLCAL1_NDAC1_OFFSET)) +#define PLLDIG_PLLCAL1_NDAC1_OFFSET (24) +#define PLLDIG_PLLCAL1_NDAC1_MASK (0x7F000000) + +/* Naming convention for PLL: + * ARMPLL - PLL0 + * PERIPHPLL - PLL1 + * ENETPLL - PLL2 + * DDRPLL - PLL3 + * VIDEOPLL - PLL4 + */ +/* The min,max values for PLL VCO (Hz) */ +#define PERIPHPLL_MAX_VCO_RATE (1200000000) + +/* The min,max values for PLL PHI0 and PHI1 outputs (Hz) */ +#define PERIPHPLL_MAX_PHI0_MAX_RATE (400000000) +#define PERIPHPLL_MAX_PHI1_MAX_RATE (100000000) + +/* The maximum value for PLL VCO according to data sheet */ +#define MAX_VCO_RATE (1300000000) +#define MIN_VCO_RATE (650000000) + +enum s32v234_plldig_type { + S32_PLLDIG_ARM, + S32_PLLDIG_PERIPH, + S32_PLLDIG_ENET, + S32_PLLDIG_DDR, + S32_PLLDIG_VIDEO, +}; + +#endif diff --git a/drivers/clk/s32/s32v234/src.h b/drivers/clk/s32/s32v234/src.h new file mode 100644 index 00000000000000..39fa973b7c3cd6 --- /dev/null +++ b/drivers/clk/s32/s32v234/src.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ +#ifndef _SRC_H +#define _SRC_H + +/* Source Reset Control: General Purpose Register 1 */ +#define SRC_GPR1 (src_base + 0x100) +#define SRC_GPR1_ARMPLL_SRC_SEL_OFFSET (27) +#define SRC_GPR1_ENETPLL_SRC_SEL_OFFSET (28) +#define SRC_GPR1_DDRPLL_SRC_SEL_OFFSET (29) +#define SRC_GPR1_PERIPHPLL_SRC_SEL_OFFSET (30) +#define SRC_GPR1_VIDEOPLL_SRC_SEL_OFFSET (31) +#define SRC_GPR1_XPLL_SRC_SEL_SIZE (1) + +#endif diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 25f11e9ec35878..18f8d6a5fd3706 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -115,6 +115,14 @@ config ARM_IMX_CPUFREQ_DT If in doubt, say N. +config ARM_IMX7ULP_CPUFREQ + tristate "NXP i.MX7ULP cpufreq support" + depends on ARCH_MXC + help + This adds cpufreq driver support for NXP i.MX7ULP series SoCs. + + If in doubt, say N. + config ARM_KIRKWOOD_CPUFREQ def_bool MACH_KIRKWOOD help diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index 9a9f5ccd13d981..f6fdc4e4014c9e 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -57,6 +57,7 @@ obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o obj-$(CONFIG_ARM_IMX_CPUFREQ_DT) += imx-cpufreq-dt.o +obj-$(CONFIG_ARM_IMX7ULP_CPUFREQ) += imx7ulp-cpufreq.o obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o obj-$(CONFIG_ARM_MEDIATEK_CPUFREQ) += mediatek-cpufreq.o obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index bca8d1f47fd2c0..fbf52fbebd9b12 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -110,6 +110,7 @@ static const struct of_device_id blacklist[] __initconst = { { .compatible = "fsl,imx8mq", }, { .compatible = "fsl,imx8mm", }, { .compatible = "fsl,imx8mn", }, + { .compatible = "fsl,imx8mp", }, { .compatible = "marvell,armadaxp", }, diff --git a/drivers/cpufreq/imx-cpufreq-dt.c b/drivers/cpufreq/imx-cpufreq-dt.c index 85a6efd6b68f9a..22c11415276417 100644 --- a/drivers/cpufreq/imx-cpufreq-dt.c +++ b/drivers/cpufreq/imx-cpufreq-dt.c @@ -19,6 +19,8 @@ #define IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK (0xf << 8) #define OCOTP_CFG3_MKT_SEGMENT_SHIFT 6 #define OCOTP_CFG3_MKT_SEGMENT_MASK (0x3 << 6) +#define IMX8MP_OCOTP_CFG3_MKT_SEGMENT_SHIFT 5 +#define IMX8MP_OCOTP_CFG3_MKT_SEGMENT_MASK (0x3 << 5) /* cpufreq-dt device registered by imx-cpufreq-dt */ static struct platform_device *cpufreq_dt_pdev; @@ -35,13 +37,18 @@ static int imx_cpufreq_dt_probe(struct platform_device *pdev) if (ret) return ret; - if (of_machine_is_compatible("fsl,imx8mn")) + if (of_machine_is_compatible("fsl,imx8mn") || of_machine_is_compatible("fsl,imx8mp")) speed_grade = (cell_value & IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK) >> OCOTP_CFG3_SPEED_GRADE_SHIFT; else speed_grade = (cell_value & OCOTP_CFG3_SPEED_GRADE_MASK) >> OCOTP_CFG3_SPEED_GRADE_SHIFT; - mkt_segment = (cell_value & OCOTP_CFG3_MKT_SEGMENT_MASK) >> OCOTP_CFG3_MKT_SEGMENT_SHIFT; + if (of_machine_is_compatible("fsl,imx8mp")) + mkt_segment = (cell_value & IMX8MP_OCOTP_CFG3_MKT_SEGMENT_MASK) + >> IMX8MP_OCOTP_CFG3_MKT_SEGMENT_SHIFT; + else + mkt_segment = (cell_value & OCOTP_CFG3_MKT_SEGMENT_MASK) + >> OCOTP_CFG3_MKT_SEGMENT_SHIFT; /* * Early samples without fuses written report "0 0" which may NOT @@ -54,7 +61,8 @@ static int imx_cpufreq_dt_probe(struct platform_device *pdev) if (of_machine_is_compatible("fsl,imx8mm") || of_machine_is_compatible("fsl,imx8mq")) speed_grade = 1; - if (of_machine_is_compatible("fsl,imx8mn")) + if (of_machine_is_compatible("fsl,imx8mn") || + of_machine_is_compatible("fsl,imx8mp")) speed_grade = 0xb; } diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c index edef3399c97945..515b83b596dfe3 100644 --- a/drivers/cpufreq/imx6q-cpufreq.c +++ b/drivers/cpufreq/imx6q-cpufreq.c @@ -3,6 +3,7 @@ * Copyright (C) 2013 Freescale Semiconductor, Inc. */ +#include #include #include #include @@ -14,14 +15,27 @@ #include #include #include +#include #define PU_SOC_VOLTAGE_NORMAL 1250000 #define PU_SOC_VOLTAGE_HIGH 1275000 #define FREQ_1P2_GHZ 1200000000 +#define FREQ_396_MHZ 396000 -static struct regulator *arm_reg; -static struct regulator *pu_reg; -static struct regulator *soc_reg; +#define PU_SOC_VOLTAGE_NORMAL 1250000 +#define PU_SOC_VOLTAGE_HIGH 1275000 +#define DC_VOLTAGE_MIN 1300000 +#define DC_VOLTAGE_MAX 1400000 +#define FREQ_1P2_GHZ 1200000000 +#define FREQ_396_MHZ 396000 +#define FREQ_528_MHZ 528000 +#define FREQ_198_MHZ 198000 +#define FREQ_24_MHZ 24000 + +struct regulator *arm_reg; +struct regulator *pu_reg; +struct regulator *soc_reg; +struct regulator *dc_reg; enum IMX6_CPUFREQ_CLKS { ARM, @@ -29,12 +43,15 @@ enum IMX6_CPUFREQ_CLKS { STEP, PLL1_SW, PLL2_PFD2_396M, + PLL1, + PLL1_BYPASS, + PLL1_BYPASS_SRC, /* MX6UL requires two more clks */ PLL2_BUS, SECONDARY_SEL, }; -#define IMX6Q_CPUFREQ_CLK_NUM 5 -#define IMX6UL_CPUFREQ_CLK_NUM 7 +#define IMX6Q_CPUFREQ_CLK_NUM 8 +#define IMX6UL_CPUFREQ_CLK_NUM 10 static int num_clks; static struct clk_bulk_data clks[] = { @@ -43,6 +60,9 @@ static struct clk_bulk_data clks[] = { { .id = "step" }, { .id = "pll1_sw" }, { .id = "pll2_pfd2_396m" }, + { .id = "pll1" }, + { .id = "pll1_bypass" }, + { .id = "pll1_bypass_src" }, { .id = "pll2_bus" }, { .id = "secondary_sel" }, }; @@ -56,6 +76,9 @@ static unsigned int transition_latency; static u32 *imx6_soc_volt; static u32 soc_opp_count; +static bool ignore_dc_reg; +static bool low_power_run_support; + static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) { struct dev_pm_opp *opp; @@ -66,7 +89,16 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) new_freq = freq_table[index].frequency; freq_hz = new_freq * 1000; - old_freq = clk_get_rate(clks[ARM].clk) / 1000; + old_freq = policy->cur; + + /* + * ON i.MX6ULL, the 24MHz setpoint is not seen by cpufreq + * so we neet to prevent the cpufreq change frequency + * from 24MHz to 198Mhz directly. busfreq will handle this + * when exit from low bus mode. + */ + if (old_freq == FREQ_24_MHZ && new_freq == FREQ_198_MHZ) + return 0; opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); if (IS_ERR(opp)) { @@ -83,6 +115,13 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) old_freq / 1000, volt_old / 1000, new_freq / 1000, volt / 1000); + if (low_power_run_support) { + if (old_freq == freq_table[0].frequency) + request_bus_freq(BUS_FREQ_HIGH); + } else if (old_freq <= FREQ_396_MHZ && new_freq > FREQ_396_MHZ) { + request_bus_freq(BUS_FREQ_HIGH); + } + /* scaling up? scale voltage before frequency */ if (new_freq > old_freq) { if (!IS_ERR(pu_reg)) { @@ -143,11 +182,18 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk); clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) { + /* Ensure that pll1_bypass is set back to + * pll1. We have to do this first so that the + * change rate done to pll1_sys_clk done below + * can propagate up to pll1. + */ + clk_set_parent(clks[PLL1_BYPASS].clk, clks[PLL1].clk); clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000); clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); } else { /* pll1_sys needs to be enabled for divider rate change to work. */ pll1_sys_temp_enabled = true; + clk_set_parent(clks[PLL1_BYPASS].clk, clks[PLL1_BYPASS_SRC].clk); clk_prepare_enable(clks[PLL1_SYS].clk); } } @@ -185,16 +231,34 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) } } + /* + * If CPU is dropped to the lowest level, release the need + * for a high bus frequency. + */ + if (low_power_run_support) { + if (new_freq == freq_table[0].frequency) + release_bus_freq(BUS_FREQ_HIGH); + } else if (old_freq > FREQ_396_MHZ && new_freq <= FREQ_396_MHZ) { + release_bus_freq(BUS_FREQ_HIGH); + } + return 0; } static int imx6q_cpufreq_init(struct cpufreq_policy *policy) { policy->clk = clks[ARM].clk; + policy->cur = clk_get_rate(policy->clk) / 1000; cpufreq_generic_init(policy, freq_table, transition_latency); policy->suspend_freq = max_freq; dev_pm_opp_of_register_em(policy->cpus); + if (low_power_run_support && policy->cur > freq_table[0].frequency) { + request_bus_freq(BUS_FREQ_HIGH); + } else if (policy->cur > FREQ_396_MHZ) { + request_bus_freq(BUS_FREQ_HIGH); + } + return 0; } @@ -327,6 +391,43 @@ static int imx6ul_opp_check_speed_grading(struct device *dev) return ret; } +static int imx6_cpufreq_pm_notify(struct notifier_block *nb, + unsigned long event, void *dummy) +{ + int ret; + + switch (event) { + case PM_SUSPEND_PREPARE: + if (!IS_ERR(dc_reg) && !ignore_dc_reg) { + ret = regulator_set_voltage_tol(dc_reg, DC_VOLTAGE_MAX, 0); + if (ret) { + dev_err(cpu_dev, + "failed to scale dc_reg to max: %d\n", ret); + return ret; + } + } + break; + case PM_POST_SUSPEND: + if (!IS_ERR(dc_reg) && !ignore_dc_reg) { + ret = regulator_set_voltage_tol(dc_reg, DC_VOLTAGE_MIN, 0); + if (ret) { + dev_err(cpu_dev, + "failed to scale dc_reg to min: %d\n", ret); + return ret; + } + } + break; + default: + break; + } + + return NOTIFY_OK; +} + +static struct notifier_block imx6_cpufreq_pm_notifier = { + .notifier_call = imx6_cpufreq_pm_notify, +}; + static int imx6q_cpufreq_probe(struct platform_device *pdev) { struct device_node *np; @@ -375,6 +476,11 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) goto put_reg; } + dc_reg = devm_regulator_get_optional(cpu_dev, "dc"); + + /* On i.MX6ULL, check the 24MHz low power run mode support */ + low_power_run_support = of_property_read_bool(np, "fsl,low-power-run"); + ret = dev_pm_opp_of_add_table(cpu_dev); if (ret < 0) { dev_err(cpu_dev, "failed to init OPP table: %d\n", ret); @@ -388,8 +494,10 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) of_machine_is_compatible("fsl,imx6ull")) { ret = imx6ul_opp_check_speed_grading(cpu_dev); if (ret) { - if (ret == -EPROBE_DEFER) + if (ret == -EPROBE_DEFER) { + dev_err(cpu_dev, "defer the cpufreq\n\n"); goto out_free_opp; + } dev_err(cpu_dev, "failed to read ocotp: %d\n", ret); @@ -412,6 +520,21 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) goto out_free_opp; } + /* + * On i.MX6UL/ULL EVK board, if the SOC is run in overide frequency, + * the dc_regulator voltage should not be touched. + */ + if (freq_table[num - 1].frequency > FREQ_528_MHZ) + ignore_dc_reg = true; + if (!IS_ERR(dc_reg) && !ignore_dc_reg) { + ret = regulator_set_voltage_tol(dc_reg, DC_VOLTAGE_MIN, 0); + if (ret) { + dev_err(cpu_dev, + "failed to scale dc_reg to min: %d\n", ret); + return ret; + } + } + /* Make imx6_soc_volt array's size same as arm opp number */ imx6_soc_volt = devm_kcalloc(cpu_dev, num, sizeof(*imx6_soc_volt), GFP_KERNEL); @@ -494,6 +617,8 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) goto free_freq_table; } + register_pm_notifier(&imx6_cpufreq_pm_notifier); + of_node_put(np); return 0; diff --git a/drivers/cpufreq/imx7ulp-cpufreq.c b/drivers/cpufreq/imx7ulp-cpufreq.c new file mode 100644 index 00000000000000..04b0a27c49bf75 --- /dev/null +++ b/drivers/cpufreq/imx7ulp-cpufreq.c @@ -0,0 +1,261 @@ + /* + * Copyright 2017 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_RUN_FREQ 528000 + +static struct clk *arm_clk; +static struct clk *core_div; +static struct clk *sys_sel; +static struct clk *hsrun_sys_sel; +static struct clk *hsrun_core; +static struct clk *spll_pfd0; +static struct clk *spll_sel; +static struct clk *firc_clk; +static struct clk *spll; + +static struct pm_qos_request pm_qos_hsrun; +static struct regulator *arm_reg; +static struct device *cpu_dev; +static struct cpufreq_frequency_table *freq_table; +static unsigned int transition_latency; + +static int imx7ulp_set_target(struct cpufreq_policy *policy, unsigned int index) +{ + struct dev_pm_opp *opp; + unsigned long freq_hz, volt, volt_old; + unsigned int old_freq, new_freq; + int ret; + + new_freq = freq_table[index].frequency; + freq_hz = new_freq * 1000; + old_freq = clk_get_rate(arm_clk) / 1000; + if (new_freq == 0 || old_freq == 0) + return -EINVAL; + + opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); + if (IS_ERR(opp)) { + dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz); + return PTR_ERR(opp); + } + volt = dev_pm_opp_get_voltage(opp); + dev_pm_opp_put(opp); + + volt_old = regulator_get_voltage(arm_reg); + + dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", + old_freq / 1000, volt_old / 1000, + new_freq / 1000, volt / 1000); + + /* Scaling up? scale voltage before frequency */ + if (new_freq > old_freq) { + ret = regulator_set_voltage_tol(arm_reg, volt, 0); + if (ret) { + dev_err(cpu_dev, "failed to scale vddarm up: %d\n", ret); + return ret; + } + } + + /* before changing pll_arm rate, change the arm_src's soure + * to firc clk first. + */ + if (new_freq > MAX_RUN_FREQ) { + pm_qos_add_request(&pm_qos_hsrun, PM_QOS_CPU_DMA_LATENCY, 0); + /* change the RUN clock to firc */ + clk_set_parent(sys_sel, firc_clk); + /* change the clock rate in HSRUN */ + clk_set_rate(spll, 480000000); + clk_set_rate(spll_pfd0, new_freq * 1000); + clk_set_parent(hsrun_sys_sel, spll_sel); + clk_set_parent(arm_clk, hsrun_core); + } else { + /* change the HSRUN clock to firc */ + clk_set_parent(hsrun_sys_sel, firc_clk); + /* change the clock rate in RUN */ + clk_set_rate(spll, 528000000); + clk_set_rate(spll_pfd0, new_freq * 1000); + clk_set_parent(sys_sel, spll_sel); + clk_set_parent(arm_clk, core_div); + if (old_freq > MAX_RUN_FREQ) + pm_qos_remove_request(&pm_qos_hsrun); + } + + /* scaling down? scaling voltage after frequency */ + if (new_freq < old_freq) { + ret = regulator_set_voltage_tol(arm_reg, volt, 0); + if (ret) { + dev_warn(cpu_dev, "failed to scale vddarm down: %d\n", ret); + ret = 0; + } + } + + return 0; +} + +static int imx7ulp_cpufreq_init(struct cpufreq_policy *policy) +{ + policy->clk = arm_clk; + policy->cur = clk_get_rate(arm_clk) / 1000; + policy->suspend_freq = freq_table[0].frequency; + + cpufreq_generic_init(policy, freq_table, transition_latency); + + return 0; +} + +static struct cpufreq_driver imx7ulp_cpufreq_driver = { + .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, + .verify = cpufreq_generic_frequency_table_verify, + .target_index = imx7ulp_set_target, + .get = cpufreq_generic_get, + .init = imx7ulp_cpufreq_init, + .name = "imx7ulp-cpufreq", + .attr = cpufreq_generic_attr, +#ifdef CONFIG_PM + .suspend = cpufreq_generic_suspend, +#endif +}; + +static int imx7ulp_cpufreq_probe(struct platform_device *pdev) +{ + struct device_node *np; + int ret; + + cpu_dev = get_cpu_device(0); + if (!cpu_dev) { + pr_err("failed to get cpu0 device\n"); + return -ENOENT; + } + + np = of_node_get(cpu_dev->of_node); + if (!np) { + dev_err(cpu_dev, "failed to find the cpu0 node\n"); + return -ENOENT; + } + + arm_clk = clk_get(cpu_dev, "arm"); + sys_sel = clk_get(cpu_dev, "sys_sel"); + core_div = clk_get(cpu_dev, "core_div"); + hsrun_sys_sel = clk_get(cpu_dev, "hsrun_sys_sel"); + hsrun_core = clk_get(cpu_dev, "hsrun_core"); + spll_pfd0 = clk_get(cpu_dev, "spll_pfd0"); + spll_sel = clk_get(cpu_dev, "spll_sel"); + firc_clk = clk_get(cpu_dev, "firc"); + spll = clk_get(cpu_dev, "spll"); + + if (IS_ERR(arm_clk) || IS_ERR(sys_sel) || IS_ERR(spll_sel) || + IS_ERR(spll_sel) || IS_ERR(firc_clk) || IS_ERR(hsrun_sys_sel) || + IS_ERR(hsrun_core) || IS_ERR(spll)) { + dev_err(cpu_dev, "failed to get cpu clock\n"); + ret = -ENOENT; + goto put_clk; + } + + arm_reg = regulator_get(cpu_dev, "arm"); + if (IS_ERR(arm_reg)) { + if (PTR_ERR(arm_reg) != -EPROBE_DEFER) + dev_err(cpu_dev, "failed to get regulator\n"); + ret = PTR_ERR(arm_reg); + goto put_clk; + } + + ret = dev_pm_opp_of_add_table(cpu_dev); + if (ret < 0) { + dev_err(cpu_dev, "failed to init OPP table: %d\n", ret); + goto put_reg; + } + + ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); + if (ret) { + dev_err(cpu_dev, "failed to init cpufreq table\n"); + goto put_reg; + } + + if (of_property_read_u32(np, "clock-latency", &transition_latency)) + transition_latency = CPUFREQ_ETERNAL; + + ret = cpufreq_register_driver(&imx7ulp_cpufreq_driver); + if (ret) { + dev_err(cpu_dev, "failed to register driver\n"); + goto free_opp_table; + } + + return 0; + +free_opp_table: + dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); +put_reg: + regulator_put(arm_reg); +put_clk: + if (!IS_ERR(arm_clk)) + clk_put(arm_clk); + if (!IS_ERR(sys_sel)) + clk_put(sys_sel); + if (!IS_ERR(core_div)) + clk_put(core_div); + if (!IS_ERR(hsrun_sys_sel)) + clk_put(hsrun_sys_sel); + if (!IS_ERR(hsrun_core)) + clk_put(hsrun_core); + if (!IS_ERR(spll_pfd0)) + clk_put(spll_pfd0); + if (!IS_ERR(spll_sel)) + clk_put(spll_sel); + if (!IS_ERR(firc_clk)) + clk_put(firc_clk); + if (!IS_ERR(spll)) + clk_put(spll); + + return ret; +} + +static int imx7ulp_cpufreq_remove(struct platform_device *pdev) +{ + cpufreq_unregister_driver(&imx7ulp_cpufreq_driver); + dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); + + regulator_put(arm_reg); + clk_put(arm_clk); + clk_put(sys_sel); + clk_put(core_div); + clk_put(hsrun_sys_sel); + clk_put(hsrun_core); + clk_put(spll_pfd0); + clk_put(spll_sel); + clk_put(firc_clk); + clk_put(spll); + + return 0; +} + +static struct platform_driver imx7ulp_cpufreq_platdrv = { + .driver = { + .name = "imx7ulp-cpufreq", + .owner = THIS_MODULE, + }, + .probe = imx7ulp_cpufreq_probe, + .remove = imx7ulp_cpufreq_remove, +}; + +module_platform_driver(imx7ulp_cpufreq_platdrv); + +MODULE_DESCRIPTION("NXP i.MX7ULP cpufreq driver"); +MODULE_LICENSE("GPL v2"); + diff --git a/drivers/crypto/caam/Kconfig b/drivers/crypto/caam/Kconfig index 137ed3df0c74d5..f38af9c3ddb8f2 100644 --- a/drivers/crypto/caam/Kconfig +++ b/drivers/crypto/caam/Kconfig @@ -8,6 +8,14 @@ config CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC config CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC tristate +config CRYPTO_DEV_FSL_CAAM_SECVIO + tristate "CAAM/SNVS Security Violation Handler (EXPERIMENTAL)" + depends on ARCH_MXC + help + Enables installation of an interrupt handler with registrable + handler functions which can be specified to act on the consequences + of a security violation. + config CRYPTO_DEV_FSL_CAAM tristate "Freescale CAAM-Multicore platform driver backend" depends on FSL_SOC || ARCH_MXC || ARCH_LAYERSCAPE @@ -33,6 +41,7 @@ config CRYPTO_DEV_FSL_CAAM_DEBUG menuconfig CRYPTO_DEV_FSL_CAAM_JR tristate "Freescale CAAM Job Ring driver backend" + select CRYPTO_ENGINE default y help Enables the driver module for Job Rings which are part of @@ -106,7 +115,7 @@ config CRYPTO_DEV_FSL_CAAM_CRYPTO_API config CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI bool "Queue Interface as Crypto API backend" - depends on FSL_DPAA && NET + depends on FSL_SDK_DPA && NET default y select CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC select CRYPTO_AUTHENC @@ -147,6 +156,66 @@ config CRYPTO_DEV_FSL_CAAM_RNG_API Selecting this will register the SEC4 hardware rng to the hw_random API for suppying the kernel entropy pool. +config CRYPTO_DEV_FSL_CAAM_TK_API + bool "Register tagged key cryptography implementations with Crypto API" + depends on CRYPTO_DEV_FSL_CAAM_CRYPTO_API + help + Selecting this will register algorithms supporting tagged + key. + + Tagged key are keys that contains metadata indicating what + they are and how to handle them. + +config CRYPTO_DEV_FSL_CAAM_RNG_TEST + bool "Test caam rng" + depends on CRYPTO_DEV_FSL_CAAM_RNG_API + help + Selecting this will enable a self-test to run for the + caam RNG. This test is several minutes long and executes + just before the RNG is registered with the hw_random API. + +config CRYPTO_DEV_FSL_CAAM_SM + bool "CAAM Secure Memory / Keystore API (EXPERIMENTAL)" + help + Enables use of a prototype kernel-level Keystore API with CAAM + Secure Memory for insertion/extraction of bus-protected secrets. + +config CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE + int "Size of each keystore slot in Secure Memory" + depends on CRYPTO_DEV_FSL_CAAM_SM + range 5 9 + default 7 + help + Select size of allocation units to divide Secure Memory pages into + (the size of a "slot" as referenced inside the API code). + Established as powers of two. + Examples: + 5 => 32 bytes + 6 => 64 bytes + 7 => 128 bytes + 8 => 256 bytes + 9 => 512 bytes + +config CRYPTO_DEV_FSL_CAAM_SM_TEST + tristate "CAAM Secure Memory - Keystore Test/Example (EXPERIMENTAL)" + depends on CRYPTO_DEV_FSL_CAAM_SM + depends on m + help + Example thread to exercise the Keystore API and to verify that + stored and recovered secrets can be used for general purpose + encryption/decryption. + +config CRYPTO_DEV_FSL_CAAM_JR_UIO + tristate "Freescale Job Ring UIO support" + depends on UIO + default y + help + Selecting this will allow job ring UIO support for + Userspace drivers + + To compile this as a module, choose M here: the module + will be called fsl_jr_uio. + endif # CRYPTO_DEV_FSL_CAAM_JR endif # CRYPTO_DEV_FSL_CAAM diff --git a/drivers/crypto/caam/Makefile b/drivers/crypto/caam/Makefile index 68d5cc0f28e295..60891ecee8988a 100644 --- a/drivers/crypto/caam/Makefile +++ b/drivers/crypto/caam/Makefile @@ -13,14 +13,20 @@ obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += caam.o obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_JR) += caam_jr.o obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC) += caamalg_desc.o obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC) += caamhash_desc.o +obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_JR_UIO) += fsl_jr_uio.o caam-y := ctrl.o +caam-$(CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API) += tag_object.o caam_jr-y := jr.o key_gen.o caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API) += caamalg.o caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI) += caamalg_qi.o caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API) += caamhash.o caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API) += caamrng.o caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API) += caampkc.o pkc_desc.o +caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_SM) += sm_store.o +obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST) += sm_test.o +obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO) += secvio.o +#caam-jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API) += tag_object.o caam-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI) += qi.o ifneq ($(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI),) diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c index fdd994ee55e22c..06140fd96fc276 100644 --- a/drivers/crypto/caam/caamalg.c +++ b/drivers/crypto/caam/caamalg.c @@ -56,6 +56,11 @@ #include "sg_sw_sec4.h" #include "key_gen.h" #include "caamalg_desc.h" +#include + +#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API +#include "tag_object.h" +#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API */ /* * crypto alg @@ -83,6 +88,7 @@ struct caam_alg_entry { bool rfc3686; bool geniv; bool nodkp; + bool support_tagged_key; }; struct caam_aead_alg { @@ -101,6 +107,7 @@ struct caam_skcipher_alg { * per-session context */ struct caam_ctx { + struct crypto_engine_ctx enginectx; u32 sh_desc_enc[DESC_MAX_USED_LEN]; u32 sh_desc_dec[DESC_MAX_USED_LEN]; u8 key[CAAM_MAX_KEY_SIZE]; @@ -114,6 +121,14 @@ struct caam_ctx { unsigned int authsize; }; +struct caam_skcipher_req_ctx { + struct skcipher_edesc *edesc; +}; + +struct caam_aead_req_ctx { + struct aead_edesc *edesc; +}; + static int aead_null_set_sh_desc(struct crypto_aead *aead) { struct caam_ctx *ctx = crypto_aead_ctx(aead); @@ -739,6 +754,44 @@ static int skcipher_setkey(struct crypto_skcipher *skcipher, const u8 *key, ctx->cdata.key_virt = key; ctx->cdata.key_inline = true; +#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API + /* + * Check if the key is not in plaintext format + */ + if (alg->caam.support_tagged_key) { + struct tag_object_conf *tagged_key_conf; + int ret; + + /* Get the configuration */ + ret = get_tag_object_conf(ctx->cdata.key_virt, + ctx->cdata.keylen, &tagged_key_conf); + if (ret) { + dev_err(jrdev, + "caam algorithms can't process tagged key\n"); + return ret; + } + + /* Only support black key */ + if (!is_bk_conf(tagged_key_conf)) { + dev_err(jrdev, + "The tagged key provided is not a black key\n"); + return -EINVAL; + } + + get_blackey_conf(&tagged_key_conf->conf.bk_conf, + &ctx->cdata.key_real_len, + &ctx->cdata.key_cmd_opt); + + ret = get_tagged_data(ctx->cdata.key_virt, ctx->cdata.keylen, + &ctx->cdata.key_virt, &ctx->cdata.keylen); + if (ret) { + dev_err(jrdev, + "caam algorithms wrong data from tagged key\n"); + return ret; + } + } +#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API */ + /* skcipher_encrypt shared descriptor */ desc = ctx->sh_desc_enc; cnstr_shdsc_skcipher_encap(desc, &ctx->cdata, ivsize, is_rfc3686, @@ -818,6 +871,20 @@ static int ctr_skcipher_setkey(struct crypto_skcipher *skcipher, return skcipher_setkey(skcipher, key, keylen, ctx1_iv_off); } +static int arc4_skcipher_setkey(struct crypto_skcipher *skcipher, + const u8 *key, unsigned int keylen) +{ + return skcipher_setkey(skcipher, key, keylen, 0); +} + +#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API +static int tk_skcipher_setkey(struct crypto_skcipher *skcipher, + const u8 *key, unsigned int keylen) +{ + return skcipher_setkey(skcipher, key, keylen, 0); +} +#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API */ + static int des_skcipher_setkey(struct crypto_skcipher *skcipher, const u8 *key, unsigned int keylen) { @@ -871,6 +938,7 @@ static int xts_skcipher_setkey(struct crypto_skcipher *skcipher, const u8 *key, * @mapped_src_nents: number of segments in input h/w link table * @mapped_dst_nents: number of segments in output h/w link table * @sec4_sg_bytes: length of dma mapped sec4_sg space + * @bklog: stored to determine if the request needs backlog * @sec4_sg_dma: bus physical mapped address of h/w link table * @sec4_sg: pointer to h/w link table * @hw_desc: the h/w job descriptor followed by any referenced link tables @@ -881,6 +949,7 @@ struct aead_edesc { int mapped_src_nents; int mapped_dst_nents; int sec4_sg_bytes; + bool bklog; dma_addr_t sec4_sg_dma; struct sec4_sg_entry *sec4_sg; u32 hw_desc[]; @@ -894,6 +963,7 @@ struct aead_edesc { * @mapped_dst_nents: number of segments in output h/w link table * @iv_dma: dma address of iv for checking continuity and link table * @sec4_sg_bytes: length of dma mapped sec4_sg space + * @bklog: stored to determine if the request needs backlog * @sec4_sg_dma: bus physical mapped address of h/w link table * @sec4_sg: pointer to h/w link table * @hw_desc: the h/w job descriptor followed by any referenced link tables @@ -906,6 +976,7 @@ struct skcipher_edesc { int mapped_dst_nents; dma_addr_t iv_dma; int sec4_sg_bytes; + bool bklog; dma_addr_t sec4_sg_dma; struct sec4_sg_entry *sec4_sg; u32 hw_desc[0]; @@ -954,16 +1025,20 @@ static void skcipher_unmap(struct device *dev, struct skcipher_edesc *edesc, edesc->sec4_sg_dma, edesc->sec4_sg_bytes); } -static void aead_encrypt_done(struct device *jrdev, u32 *desc, u32 err, - void *context) +static void aead_crypt_done(struct device *jrdev, u32 *desc, u32 err, + void *context) { struct aead_request *req = context; + struct caam_aead_req_ctx *rctx = aead_request_ctx(req); + struct caam_drv_private_jr *jrp = dev_get_drvdata(jrdev); struct aead_edesc *edesc; int ecode = 0; + bool has_bklog; dev_dbg(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err); - edesc = container_of(desc, struct aead_edesc, hw_desc[0]); + edesc = rctx->edesc; + has_bklog = edesc->bklog; if (err) ecode = caam_jr_strstatus(jrdev, err); @@ -972,82 +1047,32 @@ static void aead_encrypt_done(struct device *jrdev, u32 *desc, u32 err, kfree(edesc); - aead_request_complete(req, ecode); -} - -static void aead_decrypt_done(struct device *jrdev, u32 *desc, u32 err, - void *context) -{ - struct aead_request *req = context; - struct aead_edesc *edesc; - int ecode = 0; - - dev_dbg(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err); - - edesc = container_of(desc, struct aead_edesc, hw_desc[0]); - - if (err) - ecode = caam_jr_strstatus(jrdev, err); - - aead_unmap(jrdev, edesc, req); - - kfree(edesc); - - aead_request_complete(req, ecode); -} - -static void skcipher_encrypt_done(struct device *jrdev, u32 *desc, u32 err, - void *context) -{ - struct skcipher_request *req = context; - struct skcipher_edesc *edesc; - struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req); - int ivsize = crypto_skcipher_ivsize(skcipher); - int ecode = 0; - - dev_dbg(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err); - - edesc = container_of(desc, struct skcipher_edesc, hw_desc[0]); - - if (err) - ecode = caam_jr_strstatus(jrdev, err); - - skcipher_unmap(jrdev, edesc, req); - /* - * The crypto API expects us to set the IV (req->iv) to the last - * ciphertext block (CBC mode) or last counter (CTR mode). - * This is used e.g. by the CTS mode. + * If no backlog flag, the completion of the request is done + * by CAAM, not crypto engine. */ - if (ivsize && !ecode) { - memcpy(req->iv, (u8 *)edesc->sec4_sg + edesc->sec4_sg_bytes, - ivsize); - print_hex_dump_debug("dstiv @"__stringify(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, req->iv, - edesc->src_nents > 1 ? 100 : ivsize, 1); - } - - caam_dump_sg("dst @" __stringify(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, req->dst, - edesc->dst_nents > 1 ? 100 : req->cryptlen, 1); - - kfree(edesc); - - skcipher_request_complete(req, ecode); + if (!has_bklog) + aead_request_complete(req, ecode); + else + crypto_finalize_aead_request(jrp->engine, req, ecode); } -static void skcipher_decrypt_done(struct device *jrdev, u32 *desc, u32 err, - void *context) +static void skcipher_crypt_done(struct device *jrdev, u32 *desc, u32 err, + void *context) { struct skcipher_request *req = context; struct skcipher_edesc *edesc; + struct caam_skcipher_req_ctx *rctx = skcipher_request_ctx(req); struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req); + struct caam_drv_private_jr *jrp = dev_get_drvdata(jrdev); int ivsize = crypto_skcipher_ivsize(skcipher); int ecode = 0; + bool has_bklog; dev_dbg(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err); - edesc = container_of(desc, struct skcipher_edesc, hw_desc[0]); + edesc = rctx->edesc; + has_bklog = edesc->bklog; if (err) ecode = caam_jr_strstatus(jrdev, err); @@ -1073,7 +1098,14 @@ static void skcipher_decrypt_done(struct device *jrdev, u32 *desc, u32 err, kfree(edesc); - skcipher_request_complete(req, ecode); + /* + * If no backlog flag, the completion of the request is done + * by CAAM, not crypto engine. + */ + if (!has_bklog) + skcipher_request_complete(req, ecode); + else + crypto_finalize_skcipher_request(jrp->engine, req, ecode); } /* @@ -1319,6 +1351,7 @@ static struct aead_edesc *aead_edesc_alloc(struct aead_request *req, struct crypto_aead *aead = crypto_aead_reqtfm(req); struct caam_ctx *ctx = crypto_aead_ctx(aead); struct device *jrdev = ctx->jrdev; + struct caam_aead_req_ctx *rctx = aead_request_ctx(req); gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? GFP_KERNEL : GFP_ATOMIC; int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0; @@ -1419,6 +1452,9 @@ static struct aead_edesc *aead_edesc_alloc(struct aead_request *req, edesc->mapped_dst_nents = mapped_dst_nents; edesc->sec4_sg = (void *)edesc + sizeof(struct aead_edesc) + desc_bytes; + + rctx->edesc = edesc; + *all_contig_ptr = !(mapped_src_nents > 1); sec4_sg_index = 0; @@ -1449,41 +1485,34 @@ static struct aead_edesc *aead_edesc_alloc(struct aead_request *req, return edesc; } -static int gcm_encrypt(struct aead_request *req) +static int aead_enqueue_req(struct device *jrdev, struct aead_request *req) { - struct aead_edesc *edesc; - struct crypto_aead *aead = crypto_aead_reqtfm(req); - struct caam_ctx *ctx = crypto_aead_ctx(aead); - struct device *jrdev = ctx->jrdev; - bool all_contig; - u32 *desc; - int ret = 0; - - /* allocate extended descriptor */ - edesc = aead_edesc_alloc(req, GCM_DESC_JOB_IO_LEN, &all_contig, true); - if (IS_ERR(edesc)) - return PTR_ERR(edesc); - - /* Create and submit job descriptor */ - init_gcm_job(req, edesc, all_contig, true); + struct caam_drv_private_jr *jrpriv = dev_get_drvdata(jrdev); + struct caam_aead_req_ctx *rctx = aead_request_ctx(req); + struct aead_edesc *edesc = rctx->edesc; + u32 *desc = edesc->hw_desc; + int ret; - print_hex_dump_debug("aead jobdesc@"__stringify(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc, - desc_bytes(edesc->hw_desc), 1); + /* + * Only the backlog request are sent to crypto-engine since the others + * can be handled by CAAM, if free, especially since JR has up to 1024 + * entries (more than the 10 entries from crypto-engine). + */ + if (req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG) + ret = crypto_transfer_aead_request_to_engine(jrpriv->engine, + req); + else + ret = caam_jr_enqueue(jrdev, desc, aead_crypt_done, req); - desc = edesc->hw_desc; - ret = caam_jr_enqueue(jrdev, desc, aead_encrypt_done, req); - if (!ret) { - ret = -EINPROGRESS; - } else { + if ((ret != -EINPROGRESS) && (ret != -EBUSY)) { aead_unmap(jrdev, edesc, req); - kfree(edesc); + kfree(rctx->edesc); } return ret; } -static int chachapoly_encrypt(struct aead_request *req) +static inline int chachapoly_crypt(struct aead_request *req, bool encrypt) { struct aead_edesc *edesc; struct crypto_aead *aead = crypto_aead_reqtfm(req); @@ -1491,180 +1520,130 @@ static int chachapoly_encrypt(struct aead_request *req) struct device *jrdev = ctx->jrdev; bool all_contig; u32 *desc; - int ret; edesc = aead_edesc_alloc(req, CHACHAPOLY_DESC_JOB_IO_LEN, &all_contig, - true); + encrypt); if (IS_ERR(edesc)) return PTR_ERR(edesc); desc = edesc->hw_desc; - init_chachapoly_job(req, edesc, all_contig, true); + init_chachapoly_job(req, edesc, all_contig, encrypt); print_hex_dump_debug("chachapoly jobdesc@" __stringify(__LINE__)": ", DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); - ret = caam_jr_enqueue(jrdev, desc, aead_encrypt_done, req); - if (!ret) { - ret = -EINPROGRESS; - } else { - aead_unmap(jrdev, edesc, req); - kfree(edesc); - } - - return ret; + return aead_enqueue_req(jrdev, req); } -static int chachapoly_decrypt(struct aead_request *req) +static int chachapoly_encrypt(struct aead_request *req) { - struct aead_edesc *edesc; - struct crypto_aead *aead = crypto_aead_reqtfm(req); - struct caam_ctx *ctx = crypto_aead_ctx(aead); - struct device *jrdev = ctx->jrdev; - bool all_contig; - u32 *desc; - int ret; - - edesc = aead_edesc_alloc(req, CHACHAPOLY_DESC_JOB_IO_LEN, &all_contig, - false); - if (IS_ERR(edesc)) - return PTR_ERR(edesc); - - desc = edesc->hw_desc; - - init_chachapoly_job(req, edesc, all_contig, false); - print_hex_dump_debug("chachapoly jobdesc@" __stringify(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), - 1); - - ret = caam_jr_enqueue(jrdev, desc, aead_decrypt_done, req); - if (!ret) { - ret = -EINPROGRESS; - } else { - aead_unmap(jrdev, edesc, req); - kfree(edesc); - } - - return ret; + return chachapoly_crypt(req, true); } -static int ipsec_gcm_encrypt(struct aead_request *req) +static int chachapoly_decrypt(struct aead_request *req) { - return crypto_ipsec_check_assoclen(req->assoclen) ? : gcm_encrypt(req); + return chachapoly_crypt(req, false); } -static int aead_encrypt(struct aead_request *req) +static inline int aead_crypt(struct aead_request *req, bool encrypt) { struct aead_edesc *edesc; struct crypto_aead *aead = crypto_aead_reqtfm(req); struct caam_ctx *ctx = crypto_aead_ctx(aead); struct device *jrdev = ctx->jrdev; bool all_contig; - u32 *desc; - int ret = 0; /* allocate extended descriptor */ edesc = aead_edesc_alloc(req, AUTHENC_DESC_JOB_IO_LEN, - &all_contig, true); + &all_contig, encrypt); if (IS_ERR(edesc)) return PTR_ERR(edesc); /* Create and submit job descriptor */ - init_authenc_job(req, edesc, all_contig, true); + init_authenc_job(req, edesc, all_contig, encrypt); print_hex_dump_debug("aead jobdesc@"__stringify(__LINE__)": ", DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc, desc_bytes(edesc->hw_desc), 1); - desc = edesc->hw_desc; - ret = caam_jr_enqueue(jrdev, desc, aead_encrypt_done, req); - if (!ret) { - ret = -EINPROGRESS; - } else { - aead_unmap(jrdev, edesc, req); - kfree(edesc); - } + return aead_enqueue_req(jrdev, req); +} - return ret; +static int aead_encrypt(struct aead_request *req) +{ + return aead_crypt(req, true); } -static int gcm_decrypt(struct aead_request *req) +static int aead_decrypt(struct aead_request *req) { - struct aead_edesc *edesc; - struct crypto_aead *aead = crypto_aead_reqtfm(req); - struct caam_ctx *ctx = crypto_aead_ctx(aead); - struct device *jrdev = ctx->jrdev; - bool all_contig; - u32 *desc; - int ret = 0; + return aead_crypt(req, false); +} - /* allocate extended descriptor */ - edesc = aead_edesc_alloc(req, GCM_DESC_JOB_IO_LEN, &all_contig, false); - if (IS_ERR(edesc)) - return PTR_ERR(edesc); +static int aead_do_one_req(struct crypto_engine *engine, void *areq) +{ + struct aead_request *req = aead_request_cast(areq); + struct caam_ctx *ctx = crypto_aead_ctx(crypto_aead_reqtfm(req)); + struct caam_aead_req_ctx *rctx = aead_request_ctx(req); + u32 *desc = rctx->edesc->hw_desc; + int ret; - /* Create and submit job descriptor*/ - init_gcm_job(req, edesc, all_contig, false); + rctx->edesc->bklog = true; - print_hex_dump_debug("aead jobdesc@"__stringify(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc, - desc_bytes(edesc->hw_desc), 1); + ret = caam_jr_enqueue(ctx->jrdev, desc, aead_crypt_done, req); - desc = edesc->hw_desc; - ret = caam_jr_enqueue(jrdev, desc, aead_decrypt_done, req); - if (!ret) { - ret = -EINPROGRESS; + if (ret != -EINPROGRESS) { + aead_unmap(ctx->jrdev, rctx->edesc, req); + kfree(rctx->edesc); } else { - aead_unmap(jrdev, edesc, req); - kfree(edesc); + ret = 0; } return ret; } -static int ipsec_gcm_decrypt(struct aead_request *req) -{ - return crypto_ipsec_check_assoclen(req->assoclen) ? : gcm_decrypt(req); -} - -static int aead_decrypt(struct aead_request *req) +static inline int gcm_crypt(struct aead_request *req, bool encrypt) { struct aead_edesc *edesc; struct crypto_aead *aead = crypto_aead_reqtfm(req); struct caam_ctx *ctx = crypto_aead_ctx(aead); struct device *jrdev = ctx->jrdev; bool all_contig; - u32 *desc; - int ret = 0; - - caam_dump_sg("dec src@" __stringify(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, req->src, - req->assoclen + req->cryptlen, 1); /* allocate extended descriptor */ - edesc = aead_edesc_alloc(req, AUTHENC_DESC_JOB_IO_LEN, - &all_contig, false); + edesc = aead_edesc_alloc(req, GCM_DESC_JOB_IO_LEN, &all_contig, + encrypt); if (IS_ERR(edesc)) return PTR_ERR(edesc); - /* Create and submit job descriptor*/ - init_authenc_job(req, edesc, all_contig, false); + /* Create and submit job descriptor */ + init_gcm_job(req, edesc, all_contig, encrypt); print_hex_dump_debug("aead jobdesc@"__stringify(__LINE__)": ", DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc, desc_bytes(edesc->hw_desc), 1); - desc = edesc->hw_desc; - ret = caam_jr_enqueue(jrdev, desc, aead_decrypt_done, req); - if (!ret) { - ret = -EINPROGRESS; - } else { - aead_unmap(jrdev, edesc, req); - kfree(edesc); - } + return aead_enqueue_req(jrdev, req); +} - return ret; +static int gcm_encrypt(struct aead_request *req) +{ + return gcm_crypt(req, true); +} + +static int gcm_decrypt(struct aead_request *req) +{ + return gcm_crypt(req, false); +} + +static int ipsec_gcm_encrypt(struct aead_request *req) +{ + return crypto_ipsec_check_assoclen(req->assoclen) ? : gcm_encrypt(req); +} + +static int ipsec_gcm_decrypt(struct aead_request *req) +{ + return crypto_ipsec_check_assoclen(req->assoclen) ? : gcm_decrypt(req); } /* @@ -1675,6 +1654,7 @@ static struct skcipher_edesc *skcipher_edesc_alloc(struct skcipher_request *req, { struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req); struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher); + struct caam_skcipher_req_ctx *rctx = skcipher_request_ctx(req); struct device *jrdev = ctx->jrdev; gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? GFP_KERNEL : GFP_ATOMIC; @@ -1773,6 +1753,7 @@ static struct skcipher_edesc *skcipher_edesc_alloc(struct skcipher_request *req, edesc->sec4_sg_bytes = sec4_sg_bytes; edesc->sec4_sg = (struct sec4_sg_entry *)((u8 *)edesc->hw_desc + desc_bytes); + rctx->edesc = edesc; /* Make sure IV is located in a DMAable area */ if (ivsize) { @@ -1828,49 +1809,35 @@ static struct skcipher_edesc *skcipher_edesc_alloc(struct skcipher_request *req, return edesc; } -static int skcipher_encrypt(struct skcipher_request *req) +static int skcipher_do_one_req(struct crypto_engine *engine, void *areq) { - struct skcipher_edesc *edesc; - struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req); - struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher); - struct device *jrdev = ctx->jrdev; - u32 *desc; - int ret = 0; - - if (!req->cryptlen) - return 0; - - /* allocate extended descriptor */ - edesc = skcipher_edesc_alloc(req, DESC_JOB_IO_LEN * CAAM_CMD_SZ); - if (IS_ERR(edesc)) - return PTR_ERR(edesc); + struct skcipher_request *req = skcipher_request_cast(areq); + struct caam_ctx *ctx = crypto_skcipher_ctx(crypto_skcipher_reqtfm(req)); + struct caam_skcipher_req_ctx *rctx = skcipher_request_ctx(req); + u32 *desc = rctx->edesc->hw_desc; + int ret; - /* Create and submit job descriptor*/ - init_skcipher_job(req, edesc, true); + rctx->edesc->bklog = true; - print_hex_dump_debug("skcipher jobdesc@" __stringify(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc, - desc_bytes(edesc->hw_desc), 1); - - desc = edesc->hw_desc; - ret = caam_jr_enqueue(jrdev, desc, skcipher_encrypt_done, req); + ret = caam_jr_enqueue(ctx->jrdev, desc, skcipher_crypt_done, req); - if (!ret) { - ret = -EINPROGRESS; + if (ret != -EINPROGRESS) { + skcipher_unmap(ctx->jrdev, rctx->edesc, req); + kfree(rctx->edesc); } else { - skcipher_unmap(jrdev, edesc, req); - kfree(edesc); + ret = 0; } return ret; } -static int skcipher_decrypt(struct skcipher_request *req) +static inline int skcipher_crypt(struct skcipher_request *req, bool encrypt) { struct skcipher_edesc *edesc; struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req); struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher); struct device *jrdev = ctx->jrdev; + struct caam_drv_private_jr *jrpriv = dev_get_drvdata(jrdev); u32 *desc; int ret = 0; @@ -1883,17 +1850,25 @@ static int skcipher_decrypt(struct skcipher_request *req) return PTR_ERR(edesc); /* Create and submit job descriptor*/ - init_skcipher_job(req, edesc, false); - desc = edesc->hw_desc; + init_skcipher_job(req, edesc, encrypt); print_hex_dump_debug("skcipher jobdesc@" __stringify(__LINE__)": ", DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc, desc_bytes(edesc->hw_desc), 1); - ret = caam_jr_enqueue(jrdev, desc, skcipher_decrypt_done, req); - if (!ret) { - ret = -EINPROGRESS; - } else { + desc = edesc->hw_desc; + /* + * Only the backlog request are sent to crypto-engine since the others + * can be handled by CAAM, if free, especially since JR has up to 1024 + * entries (more than the 10 entries from crypto-engine). + */ + if (req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG) + ret = crypto_transfer_skcipher_request_to_engine(jrpriv->engine, + req); + else + ret = caam_jr_enqueue(jrdev, desc, skcipher_crypt_done, req); + + if ((ret != -EINPROGRESS) && (ret != -EBUSY)) { skcipher_unmap(jrdev, edesc, req); kfree(edesc); } @@ -1901,6 +1876,16 @@ static int skcipher_decrypt(struct skcipher_request *req) return ret; } +static int skcipher_encrypt(struct skcipher_request *req) +{ + return skcipher_crypt(req, true); +} + +static int skcipher_decrypt(struct skcipher_request *req) +{ + return skcipher_crypt(req, false); +} + static struct caam_skcipher_alg driver_algs[] = { { .skcipher = { @@ -1918,6 +1903,25 @@ static struct caam_skcipher_alg driver_algs[] = { }, .caam.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, }, +#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API + { + .skcipher = { + .base = { + .cra_name = "tk(cbc(aes))", + .cra_driver_name = "tk-cbc-aes-caam", + .cra_blocksize = AES_BLOCK_SIZE, + }, + .setkey = tk_skcipher_setkey, + .encrypt = skcipher_encrypt, + .decrypt = skcipher_decrypt, + .min_keysize = TAG_MIN_SIZE, + .max_keysize = CAAM_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + }, + .caam.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, + .caam.support_tagged_key = true, + }, +#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API */ { .skcipher = { .base = { @@ -1934,6 +1938,21 @@ static struct caam_skcipher_alg driver_algs[] = { }, .caam.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC, }, + { + .skcipher = { + .base = { + .cra_name = "ecb(arc4)", + .cra_driver_name = "ecb-arc4-caam", + .cra_blocksize = ARC4_BLOCK_SIZE, + }, + .setkey = arc4_skcipher_setkey, + .encrypt = skcipher_encrypt, + .decrypt = skcipher_decrypt, + .min_keysize = ARC4_MIN_KEY_SIZE, + .max_keysize = ARC4_MAX_KEY_SIZE, + }, + .caam.class1_alg_type = OP_ALG_ALGSEL_ARC4 | OP_ALG_AAI_ECB, + }, { .skcipher = { .base = { @@ -2037,6 +2056,24 @@ static struct caam_skcipher_alg driver_algs[] = { }, .caam.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_ECB, }, +#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API + { + .skcipher = { + .base = { + .cra_name = "tk(ecb(aes))", + .cra_driver_name = "tk-ecb-aes-caam", + .cra_blocksize = AES_BLOCK_SIZE, + }, + .setkey = tk_skcipher_setkey, + .encrypt = skcipher_encrypt, + .decrypt = skcipher_decrypt, + .min_keysize = TAG_MIN_SIZE, + .max_keysize = CAAM_MAX_KEY_SIZE, + }, + .caam.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_ECB, + .caam.support_tagged_key = true, + }, +#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API */ { .skcipher = { .base = { @@ -3389,6 +3426,8 @@ static int caam_init_common(struct caam_ctx *ctx, struct caam_alg_entry *caam, { dma_addr_t dma_addr; struct caam_drv_private *priv; + const size_t sh_desc_enc_offset = offsetof(struct caam_ctx, + sh_desc_enc); ctx->jrdev = caam_jr_alloc(); if (IS_ERR(ctx->jrdev)) { @@ -3404,7 +3443,8 @@ static int caam_init_common(struct caam_ctx *ctx, struct caam_alg_entry *caam, dma_addr = dma_map_single_attrs(ctx->jrdev, ctx->sh_desc_enc, offsetof(struct caam_ctx, - sh_desc_enc_dma), + sh_desc_enc_dma) - + sh_desc_enc_offset, ctx->dir, DMA_ATTR_SKIP_CPU_SYNC); if (dma_mapping_error(ctx->jrdev, dma_addr)) { dev_err(ctx->jrdev, "unable to map key, shared descriptors\n"); @@ -3414,8 +3454,10 @@ static int caam_init_common(struct caam_ctx *ctx, struct caam_alg_entry *caam, ctx->sh_desc_enc_dma = dma_addr; ctx->sh_desc_dec_dma = dma_addr + offsetof(struct caam_ctx, - sh_desc_dec); - ctx->key_dma = dma_addr + offsetof(struct caam_ctx, key); + sh_desc_dec) - + sh_desc_enc_offset; + ctx->key_dma = dma_addr + offsetof(struct caam_ctx, key) - + sh_desc_enc_offset; /* copy descriptor header template value */ ctx->cdata.algtype = OP_TYPE_CLASS1_ALG | caam->class1_alg_type; @@ -3429,6 +3471,11 @@ static int caam_cra_init(struct crypto_skcipher *tfm) struct skcipher_alg *alg = crypto_skcipher_alg(tfm); struct caam_skcipher_alg *caam_alg = container_of(alg, typeof(*caam_alg), skcipher); + struct caam_ctx *ctx = crypto_skcipher_ctx(tfm); + + crypto_skcipher_set_reqsize(tfm, sizeof(struct caam_skcipher_req_ctx)); + + ctx->enginectx.op.do_one_request = skcipher_do_one_req; return caam_init_common(crypto_skcipher_ctx(tfm), &caam_alg->caam, false); @@ -3441,13 +3488,18 @@ static int caam_aead_init(struct crypto_aead *tfm) container_of(alg, struct caam_aead_alg, aead); struct caam_ctx *ctx = crypto_aead_ctx(tfm); + crypto_aead_set_reqsize(tfm, sizeof(struct caam_aead_req_ctx)); + + ctx->enginectx.op.do_one_request = aead_do_one_req; + return caam_init_common(ctx, &caam_alg->caam, !caam_alg->caam.nodkp); } static void caam_exit_common(struct caam_ctx *ctx) { dma_unmap_single_attrs(ctx->jrdev, ctx->sh_desc_enc_dma, - offsetof(struct caam_ctx, sh_desc_enc_dma), + offsetof(struct caam_ctx, sh_desc_enc_dma) - + offsetof(struct caam_ctx, sh_desc_enc), ctx->dir, DMA_ATTR_SKIP_CPU_SYNC); caam_jr_free(ctx->jrdev); } @@ -3486,7 +3538,8 @@ static void caam_skcipher_alg_init(struct caam_skcipher_alg *t_alg) struct skcipher_alg *alg = &t_alg->skcipher; alg->base.cra_module = THIS_MODULE; - alg->base.cra_priority = CAAM_CRA_PRIORITY; + alg->base.cra_priority = + t_alg->caam.support_tagged_key ? 1 : CAAM_CRA_PRIORITY; alg->base.cra_ctxsize = sizeof(struct caam_ctx); alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY; @@ -3512,6 +3565,7 @@ int caam_algapi_init(struct device *ctrldev) struct caam_drv_private *priv = dev_get_drvdata(ctrldev); int i = 0, err = 0; u32 aes_vid, aes_inst, des_inst, md_vid, md_inst, ccha_inst, ptha_inst; + u32 arc4_inst; unsigned int md_limit = SHA512_DIGEST_SIZE; bool registered = false, gcm_support; @@ -3520,37 +3574,41 @@ int caam_algapi_init(struct device *ctrldev) * First, detect presence and attributes of DES, AES, and MD blocks. */ if (priv->era < 10) { + struct caam_perfmon __iomem *perfmon = &priv->jr[0]->perfmon; u32 cha_vid, cha_inst, aes_rn; - cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls); + cha_vid = rd_reg32(&perfmon->cha_id_ls); aes_vid = cha_vid & CHA_ID_LS_AES_MASK; md_vid = (cha_vid & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT; - cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls); + cha_inst = rd_reg32(&perfmon->cha_num_ls); des_inst = (cha_inst & CHA_ID_LS_DES_MASK) >> CHA_ID_LS_DES_SHIFT; aes_inst = cha_inst & CHA_ID_LS_AES_MASK; md_inst = (cha_inst & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT; + arc4_inst = (cha_inst & CHA_ID_LS_ARC4_MASK) >> + CHA_ID_LS_ARC4_SHIFT; ccha_inst = 0; ptha_inst = 0; - aes_rn = rd_reg32(&priv->ctrl->perfmon.cha_rev_ls) & - CHA_ID_LS_AES_MASK; + aes_rn = rd_reg32(&perfmon->cha_rev_ls) & CHA_ID_LS_AES_MASK; gcm_support = !(aes_vid == CHA_VER_VID_AES_LP && aes_rn < 8); } else { + struct version_regs __iomem *vreg = &priv->jr[0]->vreg; u32 aesa, mdha; - aesa = rd_reg32(&priv->ctrl->vreg.aesa); - mdha = rd_reg32(&priv->ctrl->vreg.mdha); + aesa = rd_reg32(&vreg->aesa); + mdha = rd_reg32(&vreg->mdha); aes_vid = (aesa & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT; md_vid = (mdha & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT; - des_inst = rd_reg32(&priv->ctrl->vreg.desa) & CHA_VER_NUM_MASK; + des_inst = rd_reg32(&vreg->desa) & CHA_VER_NUM_MASK; aes_inst = aesa & CHA_VER_NUM_MASK; md_inst = mdha & CHA_VER_NUM_MASK; - ccha_inst = rd_reg32(&priv->ctrl->vreg.ccha) & CHA_VER_NUM_MASK; - ptha_inst = rd_reg32(&priv->ctrl->vreg.ptha) & CHA_VER_NUM_MASK; + ccha_inst = rd_reg32(&vreg->ccha) & CHA_VER_NUM_MASK; + ptha_inst = rd_reg32(&vreg->ptha) & CHA_VER_NUM_MASK; + arc4_inst = rd_reg32(&vreg->afha) & CHA_VER_NUM_MASK; gcm_support = aesa & CHA_VER_MISC_AES_GCM; } @@ -3573,6 +3631,10 @@ int caam_algapi_init(struct device *ctrldev) if (!aes_inst && (alg_sel == OP_ALG_ALGSEL_AES)) continue; + /* Skip ARC4 algorithms if not supported by device */ + if (!arc4_inst && alg_sel == OP_ALG_ALGSEL_ARC4) + continue; + /* * Check support for AES modes not available * on LP devices. diff --git a/drivers/crypto/caam/caamalg_desc.c b/drivers/crypto/caam/caamalg_desc.c index d6c58184bb57cf..00a726d38b9953 100644 --- a/drivers/crypto/caam/caamalg_desc.c +++ b/drivers/crypto/caam/caamalg_desc.c @@ -621,6 +621,420 @@ void cnstr_shdsc_aead_givencap(u32 * const desc, struct alginfo *cdata, } EXPORT_SYMBOL(cnstr_shdsc_aead_givencap); +/** + * cnstr_shdsc_tls_encap - tls encapsulation shared descriptor + * @desc: pointer to buffer used for descriptor construction + * @cdata: pointer to block cipher transform definitions + * Valid algorithm values - one of OP_ALG_ALGSEL_AES ANDed + * with OP_ALG_AAI_CBC + * @adata: pointer to authentication transform definitions. + * A split key is required for SEC Era < 6; the size of the split key + * is specified in this case. Valid algorithm values OP_ALG_ALGSEL_SHA1 + * ANDed with OP_ALG_AAI_HMAC_PRECOMP. + * @assoclen: associated data length + * @ivsize: initialization vector size + * @authsize: authentication data size + * @blocksize: block cipher size + * @era: SEC Era + */ +void cnstr_shdsc_tls_encap(u32 * const desc, struct alginfo *cdata, + struct alginfo *adata, unsigned int assoclen, + unsigned int ivsize, unsigned int authsize, + unsigned int blocksize, int era) +{ + u32 *key_jump_cmd, *zero_payload_jump_cmd; + u32 genpad, idx_ld_datasz, idx_ld_pad, stidx; + + /* + * Compute the index (in bytes) for the LOAD with destination of + * Class 1 Data Size Register and for the LOAD that generates padding + */ + if (adata->key_inline) { + idx_ld_datasz = DESC_TLS10_ENC_LEN + adata->keylen_pad + + cdata->keylen - 4 * CAAM_CMD_SZ; + idx_ld_pad = DESC_TLS10_ENC_LEN + adata->keylen_pad + + cdata->keylen - 2 * CAAM_CMD_SZ; + } else { + idx_ld_datasz = DESC_TLS10_ENC_LEN + 2 * CAAM_PTR_SZ - + 4 * CAAM_CMD_SZ; + idx_ld_pad = DESC_TLS10_ENC_LEN + 2 * CAAM_PTR_SZ - + 2 * CAAM_CMD_SZ; + } + + stidx = 1 << HDR_START_IDX_SHIFT; + init_sh_desc(desc, HDR_SHARE_SERIAL | stidx); + + /* skip key loading if they are loaded due to sharing */ + key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | + JUMP_COND_SHRD); + + if (era < 6) { + if (adata->key_inline) + append_key_as_imm(desc, adata->key_virt, + adata->keylen_pad, adata->keylen, + CLASS_2 | KEY_DEST_MDHA_SPLIT | + KEY_ENC); + else + append_key(desc, adata->key_dma, adata->keylen, + CLASS_2 | KEY_DEST_MDHA_SPLIT | KEY_ENC); + } else { + append_proto_dkp(desc, adata); + } + + if (cdata->key_inline) + append_key_as_imm(desc, cdata->key_virt, cdata->keylen, + cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG); + else + append_key(desc, cdata->key_dma, cdata->keylen, CLASS_1 | + KEY_DEST_CLASS_REG); + + set_jump_tgt_here(desc, key_jump_cmd); + + /* class 2 operation */ + append_operation(desc, adata->algtype | OP_ALG_AS_INITFINAL | + OP_ALG_ENCRYPT); + /* class 1 operation */ + append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL | + OP_ALG_ENCRYPT); + + /* payloadlen = input data length - (assoclen + ivlen) */ + append_math_sub_imm_u32(desc, REG0, SEQINLEN, IMM, assoclen + ivsize); + + /* math1 = payloadlen + icvlen */ + append_math_add_imm_u32(desc, REG1, REG0, IMM, authsize); + + /* padlen = block_size - math1 % block_size */ + append_math_and_imm_u32(desc, REG3, REG1, IMM, blocksize - 1); + append_math_sub_imm_u32(desc, REG2, IMM, REG3, blocksize); + + /* cryptlen = payloadlen + icvlen + padlen */ + append_math_add(desc, VARSEQOUTLEN, REG1, REG2, 4); + + /* + * update immediate data with the padding length value + * for the LOAD in the class 1 data size register. + */ + append_move(desc, MOVE_SRC_DESCBUF | MOVE_DEST_MATH2 | + (idx_ld_datasz << MOVE_OFFSET_SHIFT) | 7); + append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH2 | MOVE_DEST_DESCBUF | + (idx_ld_datasz << MOVE_OFFSET_SHIFT) | 8); + + /* overwrite PL field for the padding iNFO FIFO entry */ + append_move(desc, MOVE_SRC_DESCBUF | MOVE_DEST_MATH2 | + (idx_ld_pad << MOVE_OFFSET_SHIFT) | 7); + append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH2 | MOVE_DEST_DESCBUF | + (idx_ld_pad << MOVE_OFFSET_SHIFT) | 8); + + /* store encrypted payload, icv and padding */ + append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | LDST_VLF); + + /* if payload length is zero, jump to zero-payload commands */ + append_math_add(desc, VARSEQINLEN, ZERO, REG0, 4); + zero_payload_jump_cmd = append_jump(desc, JUMP_TEST_ALL | + JUMP_COND_MATH_Z); + + /* load iv in context1 */ + append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_WORD_CLASS_CTX | + LDST_CLASS_1_CCB | ivsize); + + /* read assoc for authentication */ + append_seq_fifo_load(desc, assoclen, FIFOLD_CLASS_CLASS2 | + FIFOLD_TYPE_MSG); + /* insnoop payload */ + append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH | FIFOLD_TYPE_MSG | + FIFOLD_TYPE_LAST2 | FIFOLDST_VLF); + + /* jump the zero-payload commands */ + append_jump(desc, JUMP_TEST_ALL | 3); + + /* zero-payload commands */ + set_jump_tgt_here(desc, zero_payload_jump_cmd); + + /* load iv in context1 */ + append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_WORD_CLASS_CTX | + LDST_CLASS_1_CCB | ivsize); + + /* assoc data is the only data for authentication */ + append_seq_fifo_load(desc, assoclen, FIFOLD_CLASS_CLASS2 | + FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST2); + + /* send icv to encryption */ + append_move(desc, MOVE_SRC_CLASS2CTX | MOVE_DEST_CLASS1INFIFO | + authsize); + + /* update class 1 data size register with padding length */ + append_load_imm_u32(desc, 0, LDST_CLASS_1_CCB | + LDST_SRCDST_WORD_DATASZ_REG | LDST_IMM); + + /* generate padding and send it to encryption */ + genpad = NFIFOENTRY_DEST_CLASS1 | NFIFOENTRY_LC1 | NFIFOENTRY_FC1 | + NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DTYPE_MSG | NFIFOENTRY_PTYPE_N; + append_load_imm_u32(desc, genpad, LDST_CLASS_IND_CCB | + LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM); + +#ifdef DEBUG + print_hex_dump(KERN_ERR, "tls enc shdesc@" __stringify(__LINE__) ": ", + DUMP_PREFIX_ADDRESS, 16, 4, desc, + desc_bytes(desc), 1); +#endif +} +EXPORT_SYMBOL(cnstr_shdsc_tls_encap); + +/** + * cnstr_shdsc_tls_decap - tls decapsulation shared descriptor + * @desc: pointer to buffer used for descriptor construction + * @cdata: pointer to block cipher transform definitions + * Valid algorithm values - one of OP_ALG_ALGSEL_AES ANDed + * with OP_ALG_AAI_CBC + * @adata: pointer to authentication transform definitions. + * A split key is required for SEC Era < 6; the size of the split key + * is specified in this case. Valid algorithm values OP_ALG_ALGSEL_SHA1 + * ANDed with OP_ALG_AAI_HMAC_PRECOMP. + * @assoclen: associated data length + * @ivsize: initialization vector size + * @authsize: authentication data size + * @blocksize: block cipher size + * @era: SEC Era + */ +void cnstr_shdsc_tls_decap(u32 * const desc, struct alginfo *cdata, + struct alginfo *adata, unsigned int assoclen, + unsigned int ivsize, unsigned int authsize, + unsigned int blocksize, int era) +{ + u32 stidx, jumpback; + u32 *key_jump_cmd, *zero_payload_jump_cmd, *skip_zero_jump_cmd; + /* + * Pointer Size bool determines the size of address pointers. + * false - Pointers fit in one 32-bit word. + * true - Pointers fit in two 32-bit words. + */ + bool ps = (CAAM_PTR_SZ != CAAM_CMD_SZ); + + stidx = 1 << HDR_START_IDX_SHIFT; + init_sh_desc(desc, HDR_SHARE_SERIAL | stidx); + + /* skip key loading if they are loaded due to sharing */ + key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | + JUMP_COND_SHRD); + + if (era < 6) + append_key(desc, adata->key_dma, adata->keylen, CLASS_2 | + KEY_DEST_MDHA_SPLIT | KEY_ENC); + else + append_proto_dkp(desc, adata); + + append_key(desc, cdata->key_dma, cdata->keylen, CLASS_1 | + KEY_DEST_CLASS_REG); + + set_jump_tgt_here(desc, key_jump_cmd); + + /* class 2 operation */ + append_operation(desc, adata->algtype | OP_ALG_AS_INITFINAL | + OP_ALG_DECRYPT | OP_ALG_ICV_ON); + /* class 1 operation */ + append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL | + OP_ALG_DECRYPT); + + /* VSIL = input data length - 2 * block_size */ + append_math_sub_imm_u32(desc, VARSEQINLEN, SEQINLEN, IMM, 2 * + blocksize); + + /* + * payloadlen + icvlen + padlen = input data length - (assoclen + + * ivsize) + */ + append_math_sub_imm_u32(desc, REG3, SEQINLEN, IMM, assoclen + ivsize); + + /* skip data to the last but one cipher block */ + append_seq_fifo_load(desc, 0, FIFOLD_CLASS_SKIP | LDST_VLF); + + /* load iv for the last cipher block */ + append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_WORD_CLASS_CTX | + LDST_CLASS_1_CCB | ivsize); + + /* read last cipher block */ + append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_MSG | + FIFOLD_TYPE_LAST1 | blocksize); + + /* move decrypted block into math0 and math1 */ + append_move(desc, MOVE_WAITCOMP | MOVE_SRC_OUTFIFO | MOVE_DEST_MATH0 | + blocksize); + + /* reset AES CHA */ + append_load_imm_u32(desc, CCTRL_RESET_CHA_AESA, LDST_CLASS_IND_CCB | + LDST_SRCDST_WORD_CHACTRL | LDST_IMM); + + /* rewind input sequence */ + append_seq_in_ptr_intlen(desc, 0, 65535, SQIN_RTO); + + /* key1 is in decryption form */ + append_operation(desc, cdata->algtype | OP_ALG_AAI_DK | + OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT); + + /* load iv in context1 */ + append_cmd(desc, CMD_SEQ_LOAD | LDST_CLASS_1_CCB | + LDST_SRCDST_WORD_CLASS_CTX | ivsize); + + /* read sequence number */ + append_seq_fifo_load(desc, 8, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG); + /* load Type, Version and Len fields in math0 */ + append_cmd(desc, CMD_SEQ_LOAD | LDST_CLASS_DECO | + LDST_SRCDST_WORD_DECO_MATH0 | (3 << LDST_OFFSET_SHIFT) | 5); + + /* compute (padlen - 1) */ + append_math_and_imm_u64(desc, REG1, REG1, IMM, 255); + + /* math2 = icvlen + (padlen - 1) + 1 */ + append_math_add_imm_u32(desc, REG2, REG1, IMM, authsize + 1); + + append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 1); + + /* VSOL = payloadlen + icvlen + padlen */ + append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, 4); + + if (caam_little_end) + append_moveb(desc, MOVE_WAITCOMP | + MOVE_SRC_MATH0 | MOVE_DEST_MATH0 | 8); + + /* update Len field */ + append_math_sub(desc, REG0, REG0, REG2, 8); + + /* store decrypted payload, icv and padding */ + append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | LDST_VLF); + + /* VSIL = (payloadlen + icvlen + padlen) - (icvlen + padlen)*/ + append_math_sub(desc, VARSEQINLEN, REG3, REG2, 4); + + zero_payload_jump_cmd = append_jump(desc, JUMP_TEST_ALL | + JUMP_COND_MATH_Z); + + /* send Type, Version and Len(pre ICV) fields to authentication */ + append_move(desc, MOVE_WAITCOMP | + MOVE_SRC_MATH0 | MOVE_DEST_CLASS2INFIFO | + (3 << MOVE_OFFSET_SHIFT) | 5); + + /* outsnooping payload */ + append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH | + FIFOLD_TYPE_MSG1OUT2 | FIFOLD_TYPE_LAST2 | + FIFOLDST_VLF); + skip_zero_jump_cmd = append_jump(desc, JUMP_TEST_ALL | 2); + + set_jump_tgt_here(desc, zero_payload_jump_cmd); + /* send Type, Version and Len(pre ICV) fields to authentication */ + append_move(desc, MOVE_WAITCOMP | MOVE_AUX_LS | + MOVE_SRC_MATH0 | MOVE_DEST_CLASS2INFIFO | + (3 << MOVE_OFFSET_SHIFT) | 5); + + set_jump_tgt_here(desc, skip_zero_jump_cmd); + append_math_add(desc, VARSEQINLEN, ZERO, REG2, 4); + + /* load icvlen and padlen */ + append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_MSG | + FIFOLD_TYPE_LAST1 | FIFOLDST_VLF); + + /* VSIL = (payloadlen + icvlen + padlen) - icvlen + padlen */ + append_math_sub(desc, VARSEQINLEN, REG3, REG2, 4); + + /* + * Start a new input sequence using the SEQ OUT PTR command options, + * pointer and length used when the current output sequence was defined. + */ + if (ps) { + /* + * Move the lower 32 bits of Shared Descriptor address, the + * SEQ OUT PTR command, Output Pointer (2 words) and + * Output Length into math registers. + */ + if (caam_little_end) + append_move(desc, MOVE_WAITCOMP | MOVE_SRC_DESCBUF | + MOVE_DEST_MATH0 | + (55 * 4 << MOVE_OFFSET_SHIFT) | 20); + else + append_move(desc, MOVE_WAITCOMP | MOVE_SRC_DESCBUF | + MOVE_DEST_MATH0 | + (54 * 4 << MOVE_OFFSET_SHIFT) | 20); + + /* Transform SEQ OUT PTR command in SEQ IN PTR command */ + append_math_and_imm_u32(desc, REG0, REG0, IMM, + ~(CMD_SEQ_IN_PTR ^ CMD_SEQ_OUT_PTR)); + /* Append a JUMP command after the copied fields */ + jumpback = CMD_JUMP | (char)-9; + append_load_imm_u32(desc, jumpback, LDST_CLASS_DECO | LDST_IMM | + LDST_SRCDST_WORD_DECO_MATH2 | + (4 << LDST_OFFSET_SHIFT)); + append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 1); + /* Move the updated fields back to the Job Descriptor */ + if (caam_little_end) + append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH0 | + MOVE_DEST_DESCBUF | + (55 * 4 << MOVE_OFFSET_SHIFT) | 24); + else + append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH0 | + MOVE_DEST_DESCBUF | + (54 * 4 << MOVE_OFFSET_SHIFT) | 24); + + /* + * Read the new SEQ IN PTR command, Input Pointer, Input Length + * and then jump back to the next command from the + * Shared Descriptor. + */ + append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 6); + } else { + /* + * Move the SEQ OUT PTR command, Output Pointer (1 word) and + * Output Length into math registers. + */ + if (caam_little_end) + append_move(desc, MOVE_WAITCOMP | MOVE_SRC_DESCBUF | + MOVE_DEST_MATH0 | + (54 * 4 << MOVE_OFFSET_SHIFT) | 12); + else + append_move(desc, MOVE_WAITCOMP | MOVE_SRC_DESCBUF | + MOVE_DEST_MATH0 | + (53 * 4 << MOVE_OFFSET_SHIFT) | 12); + + /* Transform SEQ OUT PTR command in SEQ IN PTR command */ + append_math_and_imm_u64(desc, REG0, REG0, IMM, + ~(((u64)(CMD_SEQ_IN_PTR ^ + CMD_SEQ_OUT_PTR)) << 32)); + /* Append a JUMP command after the copied fields */ + jumpback = CMD_JUMP | (char)-7; + append_load_imm_u32(desc, jumpback, LDST_CLASS_DECO | LDST_IMM | + LDST_SRCDST_WORD_DECO_MATH1 | + (4 << LDST_OFFSET_SHIFT)); + append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 1); + /* Move the updated fields back to the Job Descriptor */ + if (caam_little_end) + append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH0 | + MOVE_DEST_DESCBUF | + (54 * 4 << MOVE_OFFSET_SHIFT) | 16); + else + append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH0 | + MOVE_DEST_DESCBUF | + (53 * 4 << MOVE_OFFSET_SHIFT) | 16); + + /* + * Read the new SEQ IN PTR command, Input Pointer, Input Length + * and then jump back to the next command from the + * Shared Descriptor. + */ + append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 5); + } + + /* skip payload */ + append_seq_fifo_load(desc, 0, FIFOLD_CLASS_SKIP | FIFOLDST_VLF); + /* check icv */ + append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_ICV | + FIFOLD_TYPE_LAST2 | authsize); + +#ifdef DEBUG + print_hex_dump(KERN_ERR, "tls dec shdesc@" __stringify(__LINE__) ": ", + DUMP_PREFIX_ADDRESS, 16, 4, desc, + desc_bytes(desc), 1); +#endif +} +EXPORT_SYMBOL(cnstr_shdsc_tls_decap); + /** * cnstr_shdsc_gcm_encap - gcm encapsulation shared descriptor * @desc: pointer to buffer used for descriptor construction @@ -1389,8 +1803,14 @@ void cnstr_shdsc_skcipher_encap(u32 * const desc, struct alginfo *cdata, JUMP_COND_SHRD); /* Load class1 key only */ - append_key_as_imm(desc, cdata->key_virt, cdata->keylen, - cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG); + if (IS_ENABLED(CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API) && + cdata->key_cmd_opt) + append_key_as_imm(desc, cdata->key_virt, cdata->keylen, + cdata->key_real_len, CLASS_1 | + KEY_DEST_CLASS_REG | cdata->key_cmd_opt); + else + append_key_as_imm(desc, cdata->key_virt, cdata->keylen, + cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG); /* Load nonce into CONTEXT1 reg */ if (is_rfc3686) { @@ -1464,8 +1884,14 @@ void cnstr_shdsc_skcipher_decap(u32 * const desc, struct alginfo *cdata, JUMP_COND_SHRD); /* Load class1 key only */ - append_key_as_imm(desc, cdata->key_virt, cdata->keylen, - cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG); + if (IS_ENABLED(CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API) && + cdata->key_cmd_opt) + append_key_as_imm(desc, cdata->key_virt, cdata->keylen, + cdata->key_real_len, CLASS_1 | + KEY_DEST_CLASS_REG | cdata->key_cmd_opt); + else + append_key_as_imm(desc, cdata->key_virt, cdata->keylen, + cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG); /* Load nonce into CONTEXT1 reg */ if (is_rfc3686) { diff --git a/drivers/crypto/caam/caamalg_desc.h b/drivers/crypto/caam/caamalg_desc.h index f2893393ba5e77..99f0d1471d9c68 100644 --- a/drivers/crypto/caam/caamalg_desc.h +++ b/drivers/crypto/caam/caamalg_desc.h @@ -17,6 +17,9 @@ #define DESC_QI_AEAD_DEC_LEN (DESC_AEAD_DEC_LEN + 3 * CAAM_CMD_SZ) #define DESC_QI_AEAD_GIVENC_LEN (DESC_AEAD_GIVENC_LEN + 3 * CAAM_CMD_SZ) +#define DESC_TLS_BASE (4 * CAAM_CMD_SZ) +#define DESC_TLS10_ENC_LEN (DESC_TLS_BASE + 29 * CAAM_CMD_SZ) + /* Note: Nonce is counted in cdata.keylen */ #define DESC_AEAD_CTR_RFC3686_LEN (4 * CAAM_CMD_SZ) @@ -72,6 +75,16 @@ void cnstr_shdsc_aead_givencap(u32 * const desc, struct alginfo *cdata, u32 *nonce, const u32 ctx1_iv_off, const bool is_qi, int era); +void cnstr_shdsc_tls_encap(u32 *const desc, struct alginfo *cdata, + struct alginfo *adata, unsigned int assoclen, + unsigned int ivsize, unsigned int authsize, + unsigned int blocksize, int era); + +void cnstr_shdsc_tls_decap(u32 *const desc, struct alginfo *cdata, + struct alginfo *adata, unsigned int assoclen, + unsigned int ivsize, unsigned int authsize, + unsigned int blocksize, int era); + void cnstr_shdsc_gcm_encap(u32 * const desc, struct alginfo *cdata, unsigned int ivsize, unsigned int icvsize, const bool is_qi); diff --git a/drivers/crypto/caam/caamalg_qi.c b/drivers/crypto/caam/caamalg_qi.c index 8e3449670d2f05..fceeef15586340 100644 --- a/drivers/crypto/caam/caamalg_qi.c +++ b/drivers/crypto/caam/caamalg_qi.c @@ -290,6 +290,167 @@ static int des3_aead_setkey(struct crypto_aead *aead, const u8 *key, return err; } +static int tls_set_sh_desc(struct crypto_aead *tls) +{ + struct caam_ctx *ctx = crypto_aead_ctx(tls); + unsigned int ivsize = crypto_aead_ivsize(tls); + unsigned int blocksize = crypto_aead_blocksize(tls); + unsigned int assoclen = 13; /* always 13 bytes for TLS */ + unsigned int data_len[2]; + u32 inl_mask; + struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctx->jrdev->parent); + + if (!ctx->cdata.keylen || !ctx->authsize) + return 0; + + /* + * TLS 1.0 encrypt shared descriptor + * Job Descriptor and Shared Descriptor + * must fit into the 64-word Descriptor h/w Buffer + */ + data_len[0] = ctx->adata.keylen_pad; + data_len[1] = ctx->cdata.keylen; + + if (desc_inline_query(DESC_TLS10_ENC_LEN, DESC_JOB_IO_LEN, data_len, + &inl_mask, ARRAY_SIZE(data_len)) < 0) + return -EINVAL; + + if (inl_mask & 1) + ctx->adata.key_virt = ctx->key; + else + ctx->adata.key_dma = ctx->key_dma; + + if (inl_mask & 2) + ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad; + else + ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad; + + ctx->adata.key_inline = !!(inl_mask & 1); + ctx->cdata.key_inline = !!(inl_mask & 2); + + cnstr_shdsc_tls_encap(ctx->sh_desc_enc, &ctx->cdata, &ctx->adata, + assoclen, ivsize, ctx->authsize, blocksize, + ctrlpriv->era); + + /* + * TLS 1.0 decrypt shared descriptor + * Keys do not fit inline, regardless of algorithms used + */ + ctx->adata.key_inline = false; + ctx->adata.key_dma = ctx->key_dma; + ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad; + + cnstr_shdsc_tls_decap(ctx->sh_desc_dec, &ctx->cdata, &ctx->adata, + assoclen, ivsize, ctx->authsize, blocksize, + ctrlpriv->era); + + return 0; +} + +static int tls_setauthsize(struct crypto_aead *tls, unsigned int authsize) +{ + struct caam_ctx *ctx = crypto_aead_ctx(tls); + + ctx->authsize = authsize; + tls_set_sh_desc(tls); + + return 0; +} + +static int tls_setkey(struct crypto_aead *tls, const u8 *key, + unsigned int keylen) +{ + struct caam_ctx *ctx = crypto_aead_ctx(tls); + struct device *jrdev = ctx->jrdev; + struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent); + struct crypto_authenc_keys keys; + int ret = 0; + + if (crypto_authenc_extractkeys(&keys, key, keylen) != 0) + goto badkey; + +#ifdef DEBUG + dev_err(jrdev, "keylen %d enckeylen %d authkeylen %d\n", + keys.authkeylen + keys.enckeylen, keys.enckeylen, + keys.authkeylen); + print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); +#endif + + /* + * If DKP is supported, use it in the shared descriptor to generate + * the split key. + */ + if (ctrlpriv->era >= 6) { + ctx->adata.keylen = keys.authkeylen; + ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype & + OP_ALG_ALGSEL_MASK); + + if (ctx->adata.keylen_pad + keys.enckeylen > CAAM_MAX_KEY_SIZE) + goto badkey; + + memcpy(ctx->key, keys.authkey, keys.authkeylen); + memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, + keys.enckeylen); + dma_sync_single_for_device(jrdev, ctx->key_dma, + ctx->adata.keylen_pad + + keys.enckeylen, ctx->dir); + goto skip_split_key; + } + + ret = gen_split_key(jrdev, ctx->key, &ctx->adata, keys.authkey, + keys.authkeylen, CAAM_MAX_KEY_SIZE - + keys.enckeylen); + if (ret) + goto badkey; + + /* postpend encryption key to auth split key */ + memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, keys.enckeylen); + dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->adata.keylen_pad + + keys.enckeylen, ctx->dir); + +#ifdef DEBUG + dev_err(jrdev, "split keylen %d split keylen padded %d\n", + ctx->adata.keylen, ctx->adata.keylen_pad); + print_hex_dump(KERN_ERR, "ctx.key@" __stringify(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, ctx->key, + ctx->adata.keylen_pad + keys.enckeylen, 1); +#endif + +skip_split_key: + ctx->cdata.keylen = keys.enckeylen; + + ret = tls_set_sh_desc(tls); + if (ret) + goto badkey; + + /* Now update the driver contexts with the new shared descriptor */ + if (ctx->drv_ctx[ENCRYPT]) { + ret = caam_drv_ctx_update(ctx->drv_ctx[ENCRYPT], + ctx->sh_desc_enc); + if (ret) { + dev_err(jrdev, "driver enc context update failed\n"); + goto badkey; + } + } + + if (ctx->drv_ctx[DECRYPT]) { + ret = caam_drv_ctx_update(ctx->drv_ctx[DECRYPT], + ctx->sh_desc_dec); + if (ret) { + dev_err(jrdev, "driver dec context update failed\n"); + goto badkey; + } + } + + memzero_explicit(&keys, sizeof(keys)); + return ret; +badkey: + crypto_aead_set_flags(tls, CRYPTO_TFM_RES_BAD_KEY_LEN); + memzero_explicit(&keys, sizeof(keys)); + return -EINVAL; +} + static int gcm_set_sh_desc(struct crypto_aead *aead) { struct caam_ctx *ctx = crypto_aead_ctx(aead); @@ -808,6 +969,29 @@ struct aead_edesc { struct qm_sg_entry sgt[0]; }; +/* + * tls_edesc - s/w-extended tls descriptor + * @src_nents: number of segments in input scatterlist + * @dst_nents: number of segments in output scatterlist + * @iv_dma: dma address of iv for checking continuity and link table + * @qm_sg_bytes: length of dma mapped h/w link table + * @tmp: array of scatterlists used by 'scatterwalk_ffwd' + * @qm_sg_dma: bus physical mapped address of h/w link table + * @drv_req: driver-specific request structure + * @sgt: the h/w link table, followed by IV + */ +struct tls_edesc { + int src_nents; + int dst_nents; + dma_addr_t iv_dma; + int qm_sg_bytes; + dma_addr_t qm_sg_dma; + struct scatterlist tmp[2]; + struct scatterlist *dst; + struct caam_drv_req drv_req; + struct qm_sg_entry sgt[0]; +}; + /* * skcipher_edesc - s/w-extended skcipher descriptor * @src_nents: number of segments in input scatterlist @@ -900,6 +1084,18 @@ static void aead_unmap(struct device *dev, dma_unmap_single(dev, edesc->assoclen_dma, 4, DMA_TO_DEVICE); } +static void tls_unmap(struct device *dev, + struct tls_edesc *edesc, + struct aead_request *req) +{ + struct crypto_aead *aead = crypto_aead_reqtfm(req); + int ivsize = crypto_aead_ivsize(aead); + + caam_unmap(dev, req->src, edesc->dst, edesc->src_nents, + edesc->dst_nents, edesc->iv_dma, ivsize, DMA_TO_DEVICE, + edesc->qm_sg_dma, edesc->qm_sg_bytes); +} + static void skcipher_unmap(struct device *dev, struct skcipher_edesc *edesc, struct skcipher_request *req) { @@ -1192,6 +1388,243 @@ static int aead_decrypt(struct aead_request *req) return aead_crypt(req, false); } +static void tls_done(struct caam_drv_req *drv_req, u32 status) +{ + struct device *qidev; + struct tls_edesc *edesc; + struct aead_request *aead_req = drv_req->app_ctx; + struct crypto_aead *aead = crypto_aead_reqtfm(aead_req); + struct caam_ctx *caam_ctx = crypto_aead_ctx(aead); + int ecode = 0; + + qidev = caam_ctx->qidev; + + if (unlikely(status)) { + caam_jr_strstatus(qidev, status); + ecode = -EIO; + } + + edesc = container_of(drv_req, typeof(*edesc), drv_req); + tls_unmap(qidev, edesc, aead_req); + + aead_request_complete(aead_req, ecode); + qi_cache_free(edesc); +} + +/* + * allocate and map the tls extended descriptor + */ +static struct tls_edesc *tls_edesc_alloc(struct aead_request *req, bool encrypt) +{ + struct crypto_aead *aead = crypto_aead_reqtfm(req); + struct caam_ctx *ctx = crypto_aead_ctx(aead); + unsigned int blocksize = crypto_aead_blocksize(aead); + unsigned int padsize, authsize; + struct caam_aead_alg *alg = container_of(crypto_aead_alg(aead), + typeof(*alg), aead); + struct device *qidev = ctx->qidev; + gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? + GFP_KERNEL : GFP_ATOMIC; + int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0; + struct tls_edesc *edesc; + dma_addr_t qm_sg_dma, iv_dma = 0; + int ivsize = 0; + u8 *iv; + int qm_sg_index, qm_sg_ents = 0, qm_sg_bytes; + int in_len, out_len; + struct qm_sg_entry *sg_table, *fd_sgt; + struct caam_drv_ctx *drv_ctx; + struct scatterlist *dst; + + if (encrypt) { + padsize = blocksize - ((req->cryptlen + ctx->authsize) % + blocksize); + authsize = ctx->authsize + padsize; + } else { + authsize = ctx->authsize; + } + + drv_ctx = get_drv_ctx(ctx, encrypt ? ENCRYPT : DECRYPT); + if (unlikely(IS_ERR_OR_NULL(drv_ctx))) + return (struct tls_edesc *)drv_ctx; + + /* allocate space for base edesc, link tables and IV */ + edesc = qi_cache_alloc(GFP_DMA | flags); + if (unlikely(!edesc)) { + dev_err(qidev, "could not allocate extended descriptor\n"); + return ERR_PTR(-ENOMEM); + } + + if (likely(req->src == req->dst)) { + src_nents = sg_nents_for_len(req->src, req->assoclen + + req->cryptlen + + (encrypt ? authsize : 0)); + if (unlikely(src_nents < 0)) { + dev_err(qidev, "Insufficient bytes (%d) in src S/G\n", + req->assoclen + req->cryptlen + + (encrypt ? authsize : 0)); + qi_cache_free(edesc); + return ERR_PTR(src_nents); + } + + mapped_src_nents = dma_map_sg(qidev, req->src, src_nents, + DMA_BIDIRECTIONAL); + if (unlikely(!mapped_src_nents)) { + dev_err(qidev, "unable to map source\n"); + qi_cache_free(edesc); + return ERR_PTR(-ENOMEM); + } + dst = req->dst; + } else { + src_nents = sg_nents_for_len(req->src, req->assoclen + + req->cryptlen); + if (unlikely(src_nents < 0)) { + dev_err(qidev, "Insufficient bytes (%d) in src S/G\n", + req->assoclen + req->cryptlen); + qi_cache_free(edesc); + return ERR_PTR(src_nents); + } + + dst = scatterwalk_ffwd(edesc->tmp, req->dst, req->assoclen); + dst_nents = sg_nents_for_len(dst, req->cryptlen + + (encrypt ? authsize : 0)); + if (unlikely(dst_nents < 0)) { + dev_err(qidev, "Insufficient bytes (%d) in dst S/G\n", + req->cryptlen + + (encrypt ? authsize : 0)); + qi_cache_free(edesc); + return ERR_PTR(dst_nents); + } + + if (src_nents) { + mapped_src_nents = dma_map_sg(qidev, req->src, + src_nents, DMA_TO_DEVICE); + if (unlikely(!mapped_src_nents)) { + dev_err(qidev, "unable to map source\n"); + qi_cache_free(edesc); + return ERR_PTR(-ENOMEM); + } + } else { + mapped_src_nents = 0; + } + + mapped_dst_nents = dma_map_sg(qidev, dst, dst_nents, + DMA_FROM_DEVICE); + if (unlikely(!mapped_dst_nents)) { + dev_err(qidev, "unable to map destination\n"); + dma_unmap_sg(qidev, req->src, src_nents, DMA_TO_DEVICE); + qi_cache_free(edesc); + return ERR_PTR(-ENOMEM); + } + } + + /* + * Create S/G table: IV, src, dst. + * Input is not contiguous. + */ + qm_sg_ents = 1 + mapped_src_nents + + (mapped_dst_nents > 1 ? mapped_dst_nents : 0); + sg_table = &edesc->sgt[0]; + qm_sg_bytes = qm_sg_ents * sizeof(*sg_table); + + ivsize = crypto_aead_ivsize(aead); + iv = (u8 *)(sg_table + qm_sg_ents); + /* Make sure IV is located in a DMAable area */ + memcpy(iv, req->iv, ivsize); + iv_dma = dma_map_single(qidev, iv, ivsize, DMA_TO_DEVICE); + if (dma_mapping_error(qidev, iv_dma)) { + dev_err(qidev, "unable to map IV\n"); + caam_unmap(qidev, req->src, dst, src_nents, dst_nents, 0, 0, + DMA_NONE, 0, 0); + qi_cache_free(edesc); + return ERR_PTR(-ENOMEM); + } + + edesc->src_nents = src_nents; + edesc->dst_nents = dst_nents; + edesc->dst = dst; + edesc->iv_dma = iv_dma; + edesc->drv_req.app_ctx = req; + edesc->drv_req.cbk = tls_done; + edesc->drv_req.drv_ctx = drv_ctx; + + dma_to_qm_sg_one(sg_table, iv_dma, ivsize, 0); + qm_sg_index = 1; + + sg_to_qm_sg_last(req->src, mapped_src_nents, sg_table + qm_sg_index, 0); + qm_sg_index += mapped_src_nents; + + if (mapped_dst_nents > 1) + sg_to_qm_sg_last(dst, mapped_dst_nents, sg_table + + qm_sg_index, 0); + + qm_sg_dma = dma_map_single(qidev, sg_table, qm_sg_bytes, DMA_TO_DEVICE); + if (dma_mapping_error(qidev, qm_sg_dma)) { + dev_err(qidev, "unable to map S/G table\n"); + caam_unmap(qidev, req->src, dst, src_nents, dst_nents, iv_dma, + ivsize, DMA_TO_DEVICE, 0, 0); + qi_cache_free(edesc); + return ERR_PTR(-ENOMEM); + } + + edesc->qm_sg_dma = qm_sg_dma; + edesc->qm_sg_bytes = qm_sg_bytes; + + out_len = req->cryptlen + (encrypt ? authsize : 0); + in_len = ivsize + req->assoclen + req->cryptlen; + + fd_sgt = &edesc->drv_req.fd_sgt[0]; + + dma_to_qm_sg_one_last_ext(&fd_sgt[1], qm_sg_dma, in_len, 0); + + if (req->dst == req->src) + dma_to_qm_sg_one_ext(&fd_sgt[0], qm_sg_dma + + (sg_nents_for_len(req->src, req->assoclen) + + 1) * sizeof(*sg_table), out_len, 0); + else if (mapped_dst_nents == 1) + dma_to_qm_sg_one(&fd_sgt[0], sg_dma_address(dst), out_len, 0); + else + dma_to_qm_sg_one_ext(&fd_sgt[0], qm_sg_dma + sizeof(*sg_table) * + qm_sg_index, out_len, 0); + + return edesc; +} + +static int tls_crypt(struct aead_request *req, bool encrypt) +{ + struct tls_edesc *edesc; + struct crypto_aead *aead = crypto_aead_reqtfm(req); + struct caam_ctx *ctx = crypto_aead_ctx(aead); + int ret; + + if (unlikely(caam_congested)) + return -EAGAIN; + + edesc = tls_edesc_alloc(req, encrypt); + if (IS_ERR_OR_NULL(edesc)) + return PTR_ERR(edesc); + + ret = caam_qi_enqueue(ctx->qidev, &edesc->drv_req); + if (!ret) { + ret = -EINPROGRESS; + } else { + tls_unmap(ctx->qidev, edesc, req); + qi_cache_free(edesc); + } + + return ret; +} + +static int tls_encrypt(struct aead_request *req) +{ + return tls_crypt(req, true); +} + +static int tls_decrypt(struct aead_request *req) +{ + return tls_crypt(req, false); +} + static int ipsec_gcm_encrypt(struct aead_request *req) { return crypto_ipsec_check_assoclen(req->assoclen) ? : aead_crypt(req, @@ -2411,6 +2844,26 @@ static struct caam_aead_alg driver_aeads[] = { .geniv = true, } }, + { + .aead = { + .base = { + .cra_name = "tls10(hmac(sha1),cbc(aes))", + .cra_driver_name = "tls10-hmac-sha1-cbc-aes-caam-qi", + .cra_blocksize = AES_BLOCK_SIZE, + }, + .setkey = tls_setkey, + .setauthsize = tls_setauthsize, + .encrypt = tls_encrypt, + .decrypt = tls_decrypt, + .ivsize = AES_BLOCK_SIZE, + .maxauthsize = SHA1_DIGEST_SIZE, + }, + .caam = { + .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, + .class2_alg_type = OP_ALG_ALGSEL_SHA1 | + OP_ALG_AAI_HMAC_PRECOMP, + } + } }; static int caam_init_common(struct caam_ctx *ctx, struct caam_alg_entry *caam, @@ -2418,6 +2871,16 @@ static int caam_init_common(struct caam_ctx *ctx, struct caam_alg_entry *caam, { struct caam_drv_private *priv; struct device *dev; + /* Digest sizes for MD5, SHA1, SHA-224, SHA-256, SHA-384, SHA-512 */ + static const u8 digest_size[] = { + MD5_DIGEST_SIZE, + SHA1_DIGEST_SIZE, + SHA224_DIGEST_SIZE, + SHA256_DIGEST_SIZE, + SHA384_DIGEST_SIZE, + SHA512_DIGEST_SIZE + }; + u8 op_id; /* * distribute tfms across job rings to ensure in-order @@ -2449,6 +2912,21 @@ static int caam_init_common(struct caam_ctx *ctx, struct caam_alg_entry *caam, ctx->adata.algtype = OP_TYPE_CLASS2_ALG | caam->class2_alg_type; ctx->qidev = dev; + if (ctx->adata.algtype) { + op_id = (ctx->adata.algtype & OP_ALG_ALGSEL_SUBMASK) + >> OP_ALG_ALGSEL_SHIFT; + if (op_id < ARRAY_SIZE(digest_size)) { + ctx->authsize = digest_size[op_id]; + } else { + dev_err(ctx->jrdev, + "incorrect op_id %d; must be less than %zu\n", + op_id, ARRAY_SIZE(digest_size)); + caam_jr_free(ctx->jrdev); + return -EINVAL; + } + } else { + ctx->authsize = 0; + } spin_lock_init(&ctx->lock); ctx->drv_ctx[ENCRYPT] = NULL; diff --git a/drivers/crypto/caam/caamalg_qi2.c b/drivers/crypto/caam/caamalg_qi2.c index 6863d70976746d..5fd86bac5cf630 100644 --- a/drivers/crypto/caam/caamalg_qi2.c +++ b/drivers/crypto/caam/caamalg_qi2.c @@ -583,6 +583,257 @@ static struct aead_edesc *aead_edesc_alloc(struct aead_request *req, return edesc; } +static struct tls_edesc *tls_edesc_alloc(struct aead_request *req, + bool encrypt) +{ + struct crypto_aead *tls = crypto_aead_reqtfm(req); + unsigned int blocksize = crypto_aead_blocksize(tls); + unsigned int padsize, authsize; + struct caam_request *req_ctx = aead_request_ctx(req); + struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1]; + struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0]; + struct caam_ctx *ctx = crypto_aead_ctx(tls); + struct caam_aead_alg *alg = container_of(crypto_aead_alg(tls), + typeof(*alg), aead); + struct device *dev = ctx->dev; + gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? + GFP_KERNEL : GFP_ATOMIC; + int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0; + struct tls_edesc *edesc; + dma_addr_t qm_sg_dma, iv_dma = 0; + int ivsize = 0; + u8 *iv; + int qm_sg_index, qm_sg_ents = 0, qm_sg_bytes; + int in_len, out_len; + struct dpaa2_sg_entry *sg_table; + struct scatterlist *dst; + + if (encrypt) { + padsize = blocksize - ((req->cryptlen + ctx->authsize) % + blocksize); + authsize = ctx->authsize + padsize; + } else { + authsize = ctx->authsize; + } + + /* allocate space for base edesc, link tables and IV */ + edesc = qi_cache_zalloc(GFP_DMA | flags); + if (unlikely(!edesc)) { + dev_err(dev, "could not allocate extended descriptor\n"); + return ERR_PTR(-ENOMEM); + } + + if (likely(req->src == req->dst)) { + src_nents = sg_nents_for_len(req->src, req->assoclen + + req->cryptlen + + (encrypt ? authsize : 0)); + if (unlikely(src_nents < 0)) { + dev_err(dev, "Insufficient bytes (%d) in src S/G\n", + req->assoclen + req->cryptlen + + (encrypt ? authsize : 0)); + qi_cache_free(edesc); + return ERR_PTR(src_nents); + } + + mapped_src_nents = dma_map_sg(dev, req->src, src_nents, + DMA_BIDIRECTIONAL); + if (unlikely(!mapped_src_nents)) { + dev_err(dev, "unable to map source\n"); + qi_cache_free(edesc); + return ERR_PTR(-ENOMEM); + } + dst = req->dst; + } else { + src_nents = sg_nents_for_len(req->src, req->assoclen + + req->cryptlen); + if (unlikely(src_nents < 0)) { + dev_err(dev, "Insufficient bytes (%d) in src S/G\n", + req->assoclen + req->cryptlen); + qi_cache_free(edesc); + return ERR_PTR(src_nents); + } + + dst = scatterwalk_ffwd(edesc->tmp, req->dst, req->assoclen); + dst_nents = sg_nents_for_len(dst, req->cryptlen + + (encrypt ? authsize : 0)); + if (unlikely(dst_nents < 0)) { + dev_err(dev, "Insufficient bytes (%d) in dst S/G\n", + req->cryptlen + + (encrypt ? authsize : 0)); + qi_cache_free(edesc); + return ERR_PTR(dst_nents); + } + + if (src_nents) { + mapped_src_nents = dma_map_sg(dev, req->src, + src_nents, DMA_TO_DEVICE); + if (unlikely(!mapped_src_nents)) { + dev_err(dev, "unable to map source\n"); + qi_cache_free(edesc); + return ERR_PTR(-ENOMEM); + } + } else { + mapped_src_nents = 0; + } + + mapped_dst_nents = dma_map_sg(dev, dst, dst_nents, + DMA_FROM_DEVICE); + if (unlikely(!mapped_dst_nents)) { + dev_err(dev, "unable to map destination\n"); + dma_unmap_sg(dev, req->src, src_nents, DMA_TO_DEVICE); + qi_cache_free(edesc); + return ERR_PTR(-ENOMEM); + } + } + + /* + * Create S/G table: IV, src, dst. + * Input is not contiguous. + */ + qm_sg_ents = 1 + mapped_src_nents + + (mapped_dst_nents > 1 ? mapped_dst_nents : 0); + sg_table = &edesc->sgt[0]; + qm_sg_bytes = qm_sg_ents * sizeof(*sg_table); + + ivsize = crypto_aead_ivsize(tls); + iv = (u8 *)(sg_table + qm_sg_ents); + /* Make sure IV is located in a DMAable area */ + memcpy(iv, req->iv, ivsize); + iv_dma = dma_map_single(dev, iv, ivsize, DMA_TO_DEVICE); + if (dma_mapping_error(dev, iv_dma)) { + dev_err(dev, "unable to map IV\n"); + caam_unmap(dev, req->src, dst, src_nents, dst_nents, 0, 0, + DMA_NONE, 0, 0); + qi_cache_free(edesc); + return ERR_PTR(-ENOMEM); + } + + edesc->src_nents = src_nents; + edesc->dst_nents = dst_nents; + edesc->dst = dst; + edesc->iv_dma = iv_dma; + + dma_to_qm_sg_one(sg_table, iv_dma, ivsize, 0); + qm_sg_index = 1; + + sg_to_qm_sg_last(req->src, mapped_src_nents, sg_table + qm_sg_index, 0); + qm_sg_index += mapped_src_nents; + + if (mapped_dst_nents > 1) + sg_to_qm_sg_last(dst, mapped_dst_nents, sg_table + + qm_sg_index, 0); + + qm_sg_dma = dma_map_single(dev, sg_table, qm_sg_bytes, DMA_TO_DEVICE); + if (dma_mapping_error(dev, qm_sg_dma)) { + dev_err(dev, "unable to map S/G table\n"); + caam_unmap(dev, req->src, dst, src_nents, dst_nents, iv_dma, + ivsize, DMA_TO_DEVICE, 0, 0); + qi_cache_free(edesc); + return ERR_PTR(-ENOMEM); + } + + edesc->qm_sg_dma = qm_sg_dma; + edesc->qm_sg_bytes = qm_sg_bytes; + + out_len = req->cryptlen + (encrypt ? authsize : 0); + in_len = ivsize + req->assoclen + req->cryptlen; + + memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt)); + dpaa2_fl_set_final(in_fle, true); + dpaa2_fl_set_format(in_fle, dpaa2_fl_sg); + dpaa2_fl_set_addr(in_fle, qm_sg_dma); + dpaa2_fl_set_len(in_fle, in_len); + + if (req->dst == req->src) { + dpaa2_fl_set_format(out_fle, dpaa2_fl_sg); + dpaa2_fl_set_addr(out_fle, qm_sg_dma + + (sg_nents_for_len(req->src, req->assoclen) + + 1) * sizeof(*sg_table)); + } else if (mapped_dst_nents == 1) { + dpaa2_fl_set_format(out_fle, dpaa2_fl_single); + dpaa2_fl_set_addr(out_fle, sg_dma_address(dst)); + } else { + dpaa2_fl_set_format(out_fle, dpaa2_fl_sg); + dpaa2_fl_set_addr(out_fle, qm_sg_dma + qm_sg_index * + sizeof(*sg_table)); + } + + dpaa2_fl_set_len(out_fle, out_len); + + return edesc; +} + +static int tls_set_sh_desc(struct crypto_aead *tls) +{ + struct caam_ctx *ctx = crypto_aead_ctx(tls); + unsigned int ivsize = crypto_aead_ivsize(tls); + unsigned int blocksize = crypto_aead_blocksize(tls); + struct device *dev = ctx->dev; + struct dpaa2_caam_priv *priv = dev_get_drvdata(dev); + struct caam_flc *flc; + u32 *desc; + unsigned int assoclen = 13; /* always 13 bytes for TLS */ + unsigned int data_len[2]; + u32 inl_mask; + + if (!ctx->cdata.keylen || !ctx->authsize) + return 0; + + /* + * TLS 1.0 encrypt shared descriptor + * Job Descriptor and Shared Descriptor + * must fit into the 64-word Descriptor h/w Buffer + */ + data_len[0] = ctx->adata.keylen_pad; + data_len[1] = ctx->cdata.keylen; + + if (desc_inline_query(DESC_TLS10_ENC_LEN, DESC_JOB_IO_LEN, data_len, + &inl_mask, ARRAY_SIZE(data_len)) < 0) + return -EINVAL; + + if (inl_mask & 1) + ctx->adata.key_virt = ctx->key; + else + ctx->adata.key_dma = ctx->key_dma; + + if (inl_mask & 2) + ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad; + else + ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad; + + ctx->adata.key_inline = !!(inl_mask & 1); + ctx->cdata.key_inline = !!(inl_mask & 2); + + flc = &ctx->flc[ENCRYPT]; + desc = flc->sh_desc; + cnstr_shdsc_tls_encap(desc, &ctx->cdata, &ctx->adata, + assoclen, ivsize, ctx->authsize, blocksize, + priv->sec_attr.era); + flc->flc[1] = cpu_to_caam32(desc_len(desc)); + dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT], + sizeof(flc->flc) + desc_bytes(desc), + ctx->dir); + + /* + * TLS 1.0 decrypt shared descriptor + * Keys do not fit inline, regardless of algorithms used + */ + ctx->adata.key_inline = false; + ctx->adata.key_dma = ctx->key_dma; + ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad; + + flc = &ctx->flc[DECRYPT]; + desc = flc->sh_desc; + cnstr_shdsc_tls_decap(desc, &ctx->cdata, &ctx->adata, assoclen, ivsize, + ctx->authsize, blocksize, priv->sec_attr.era); + flc->flc[1] = cpu_to_caam32(desc_len(desc)); + dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT], + sizeof(flc->flc) + desc_bytes(desc), + ctx->dir); + + return 0; +} + static int chachapoly_set_sh_desc(struct crypto_aead *aead) { struct caam_ctx *ctx = crypto_aead_ctx(aead); @@ -627,6 +878,61 @@ static int chachapoly_setauthsize(struct crypto_aead *aead, return chachapoly_set_sh_desc(aead); } +static int tls_setkey(struct crypto_aead *tls, const u8 *key, + unsigned int keylen) +{ + struct caam_ctx *ctx = crypto_aead_ctx(tls); + struct device *dev = ctx->dev; + struct crypto_authenc_keys keys; + + if (crypto_authenc_extractkeys(&keys, key, keylen) != 0) + goto badkey; + +#ifdef DEBUG + dev_err(dev, "keylen %d enckeylen %d authkeylen %d\n", + keys.authkeylen + keys.enckeylen, keys.enckeylen, + keys.authkeylen); + print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); +#endif + + ctx->adata.keylen = keys.authkeylen; + ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype & + OP_ALG_ALGSEL_MASK); + + if (ctx->adata.keylen_pad + keys.enckeylen > CAAM_MAX_KEY_SIZE) + goto badkey; + + memcpy(ctx->key, keys.authkey, keys.authkeylen); + memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, keys.enckeylen); + dma_sync_single_for_device(dev, ctx->key_dma, ctx->adata.keylen_pad + + keys.enckeylen, ctx->dir); +#ifdef DEBUG + print_hex_dump(KERN_ERR, "ctx.key@" __stringify(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, ctx->key, + ctx->adata.keylen_pad + keys.enckeylen, 1); +#endif + + ctx->cdata.keylen = keys.enckeylen; + + memzero_explicit(&keys, sizeof(keys)); + return tls_set_sh_desc(tls); +badkey: + crypto_aead_set_flags(tls, CRYPTO_TFM_RES_BAD_KEY_LEN); + memzero_explicit(&keys, sizeof(keys)); + return -EINVAL; +} + +static int tls_setauthsize(struct crypto_aead *tls, unsigned int authsize) +{ + struct caam_ctx *ctx = crypto_aead_ctx(tls); + + ctx->authsize = authsize; + tls_set_sh_desc(tls); + + return 0; +} + static int chachapoly_setkey(struct crypto_aead *aead, const u8 *key, unsigned int keylen) { @@ -1274,6 +1580,17 @@ static void aead_unmap(struct device *dev, struct aead_edesc *edesc, dma_unmap_single(dev, edesc->assoclen_dma, 4, DMA_TO_DEVICE); } +static void tls_unmap(struct device *dev, struct tls_edesc *edesc, + struct aead_request *req) +{ + struct crypto_aead *tls = crypto_aead_reqtfm(req); + int ivsize = crypto_aead_ivsize(tls); + + caam_unmap(dev, req->src, edesc->dst, edesc->src_nents, + edesc->dst_nents, edesc->iv_dma, ivsize, DMA_TO_DEVICE, + edesc->qm_sg_dma, edesc->qm_sg_bytes); +} + static void skcipher_unmap(struct device *dev, struct skcipher_edesc *edesc, struct skcipher_request *req) { @@ -1383,6 +1700,119 @@ static int aead_decrypt(struct aead_request *req) return ret; } +static void tls_encrypt_done(void *cbk_ctx, u32 status) +{ + struct crypto_async_request *areq = cbk_ctx; + struct aead_request *req = container_of(areq, struct aead_request, + base); + struct caam_request *req_ctx = to_caam_req(areq); + struct tls_edesc *edesc = req_ctx->edesc; + struct crypto_aead *tls = crypto_aead_reqtfm(req); + struct caam_ctx *ctx = crypto_aead_ctx(tls); + int ecode = 0; + +#ifdef DEBUG + dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status); +#endif + + if (unlikely(status)) { + caam_qi2_strstatus(ctx->dev, status); + ecode = -EIO; + } + + tls_unmap(ctx->dev, edesc, req); + qi_cache_free(edesc); + aead_request_complete(req, ecode); +} + +static void tls_decrypt_done(void *cbk_ctx, u32 status) +{ + struct crypto_async_request *areq = cbk_ctx; + struct aead_request *req = container_of(areq, struct aead_request, + base); + struct caam_request *req_ctx = to_caam_req(areq); + struct tls_edesc *edesc = req_ctx->edesc; + struct crypto_aead *tls = crypto_aead_reqtfm(req); + struct caam_ctx *ctx = crypto_aead_ctx(tls); + int ecode = 0; + +#ifdef DEBUG + dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status); +#endif + + if (unlikely(status)) { + caam_qi2_strstatus(ctx->dev, status); + /* + * verify hw auth check passed else return -EBADMSG + */ + if ((status & JRSTA_CCBERR_ERRID_MASK) == + JRSTA_CCBERR_ERRID_ICVCHK) + ecode = -EBADMSG; + else + ecode = -EIO; + } + + tls_unmap(ctx->dev, edesc, req); + qi_cache_free(edesc); + aead_request_complete(req, ecode); +} + +static int tls_encrypt(struct aead_request *req) +{ + struct tls_edesc *edesc; + struct crypto_aead *tls = crypto_aead_reqtfm(req); + struct caam_ctx *ctx = crypto_aead_ctx(tls); + struct caam_request *caam_req = aead_request_ctx(req); + int ret; + + /* allocate extended descriptor */ + edesc = tls_edesc_alloc(req, true); + if (IS_ERR(edesc)) + return PTR_ERR(edesc); + + caam_req->flc = &ctx->flc[ENCRYPT]; + caam_req->flc_dma = ctx->flc_dma[ENCRYPT]; + caam_req->cbk = tls_encrypt_done; + caam_req->ctx = &req->base; + caam_req->edesc = edesc; + ret = dpaa2_caam_enqueue(ctx->dev, caam_req); + if (ret != -EINPROGRESS && + !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) { + tls_unmap(ctx->dev, edesc, req); + qi_cache_free(edesc); + } + + return ret; +} + +static int tls_decrypt(struct aead_request *req) +{ + struct tls_edesc *edesc; + struct crypto_aead *tls = crypto_aead_reqtfm(req); + struct caam_ctx *ctx = crypto_aead_ctx(tls); + struct caam_request *caam_req = aead_request_ctx(req); + int ret; + + /* allocate extended descriptor */ + edesc = tls_edesc_alloc(req, false); + if (IS_ERR(edesc)) + return PTR_ERR(edesc); + + caam_req->flc = &ctx->flc[DECRYPT]; + caam_req->flc_dma = ctx->flc_dma[DECRYPT]; + caam_req->cbk = tls_decrypt_done; + caam_req->ctx = &req->base; + caam_req->edesc = edesc; + ret = dpaa2_caam_enqueue(ctx->dev, caam_req); + if (ret != -EINPROGRESS && + !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) { + tls_unmap(ctx->dev, edesc, req); + qi_cache_free(edesc); + } + + return ret; +} + static int ipsec_gcm_encrypt(struct aead_request *req) { return crypto_ipsec_check_assoclen(req->assoclen) ? : aead_encrypt(req); @@ -2929,6 +3359,26 @@ static struct caam_aead_alg driver_aeads[] = { .geniv = true, }, }, + { + .aead = { + .base = { + .cra_name = "tls10(hmac(sha1),cbc(aes))", + .cra_driver_name = "tls10-hmac-sha1-cbc-aes-caam-qi2", + .cra_blocksize = AES_BLOCK_SIZE, + }, + .setkey = tls_setkey, + .setauthsize = tls_setauthsize, + .encrypt = tls_encrypt, + .decrypt = tls_decrypt, + .ivsize = AES_BLOCK_SIZE, + .maxauthsize = SHA1_DIGEST_SIZE, + }, + .caam = { + .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, + .class2_alg_type = OP_ALG_ALGSEL_SHA1 | + OP_ALG_AAI_HMAC_PRECOMP, + }, + }, }; static void caam_skcipher_alg_init(struct caam_skcipher_alg *t_alg) diff --git a/drivers/crypto/caam/caamalg_qi2.h b/drivers/crypto/caam/caamalg_qi2.h index 706736776b47ac..de9504f91fa90c 100644 --- a/drivers/crypto/caam/caamalg_qi2.h +++ b/drivers/crypto/caam/caamalg_qi2.h @@ -117,6 +117,28 @@ struct aead_edesc { struct dpaa2_sg_entry sgt[0]; }; +/* + * tls_edesc - s/w-extended tls descriptor + * @src_nents: number of segments in input scatterlist + * @dst_nents: number of segments in output scatterlist + * @iv_dma: dma address of iv for checking continuity and link table + * @qm_sg_bytes: length of dma mapped h/w link table + * @qm_sg_dma: bus physical mapped address of h/w link table + * @tmp: array of scatterlists used by 'scatterwalk_ffwd' + * @dst: pointer to output scatterlist, usefull for unmapping + * @sgt: the h/w link table, followed by IV + */ +struct tls_edesc { + int src_nents; + int dst_nents; + dma_addr_t iv_dma; + int qm_sg_bytes; + dma_addr_t qm_sg_dma; + struct scatterlist tmp[2]; + struct scatterlist *dst; + struct dpaa2_sg_entry sgt[0]; +}; + /* * skcipher_edesc - s/w-extended skcipher descriptor * @src_nents: number of segments in input scatterlist diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c index 65399cb2a77057..1d7e8fe7a533cf 100644 --- a/drivers/crypto/caam/caamhash.c +++ b/drivers/crypto/caam/caamhash.c @@ -65,6 +65,7 @@ #include "sg_sw_sec4.h" #include "key_gen.h" #include "caamhash_desc.h" +#include #define CAAM_CRA_PRIORITY 3000 @@ -86,6 +87,7 @@ static struct list_head hash_list; /* ahash per-session context */ struct caam_hash_ctx { + struct crypto_engine_ctx enginectx; u32 sh_desc_update[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned; u32 sh_desc_update_first[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned; u32 sh_desc_fin[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned; @@ -112,10 +114,13 @@ struct caam_hash_state { u8 buf_1[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned; int buflen_1; u8 caam_ctx[MAX_CTX_LEN] ____cacheline_aligned; - int (*update)(struct ahash_request *req); + int (*update)(struct ahash_request *req) ____cacheline_aligned; int (*final)(struct ahash_request *req); int (*finup)(struct ahash_request *req); int current_buf; + struct ahash_edesc *edesc; + void (*ahash_op_done)(struct device *jrdev, u32 *desc, u32 err, + void *context); }; struct caam_export_state { @@ -422,7 +427,7 @@ static int hash_digest_key(struct caam_hash_ctx *ctx, u32 *keylen, u8 *key, init_completion(&result.completion); ret = caam_jr_enqueue(jrdev, desc, split_key_done, &result); - if (!ret) { + if (ret == -EINPROGRESS) { /* in progress */ wait_for_completion(&result.completion); ret = result.err; @@ -553,6 +558,7 @@ static int acmac_setkey(struct crypto_ahash *ahash, const u8 *key, * @sec4_sg_dma: physical mapped address of h/w link table * @src_nents: number of segments in input scatterlist * @sec4_sg_bytes: length of dma mapped sec4_sg space + * @bklog: stored to determine if the request needs backlog * @hw_desc: the h/w job descriptor followed by any referenced link tables * @sec4_sg: h/w link table */ @@ -560,6 +566,7 @@ struct ahash_edesc { dma_addr_t sec4_sg_dma; int src_nents; int sec4_sg_bytes; + bool bklog; u32 hw_desc[DESC_JOB_IO_LEN_MAX / sizeof(u32)] ____cacheline_aligned; struct sec4_sg_entry sec4_sg[0]; }; @@ -597,24 +604,28 @@ static inline void ahash_unmap_ctx(struct device *dev, ahash_unmap(dev, edesc, req, dst_len); } -static void ahash_done(struct device *jrdev, u32 *desc, u32 err, - void *context) +static inline void ahash_done_cpy(struct device *jrdev, u32 *desc, u32 err, + void *context, enum dma_data_direction dir) { struct ahash_request *req = context; + struct caam_drv_private_jr *jrp = dev_get_drvdata(jrdev); struct ahash_edesc *edesc; struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); int digestsize = crypto_ahash_digestsize(ahash); struct caam_hash_state *state = ahash_request_ctx(req); struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); int ecode = 0; + bool has_bklog; dev_dbg(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err); - edesc = container_of(desc, struct ahash_edesc, hw_desc[0]); + edesc = state->edesc; + has_bklog = edesc->bklog; + if (err) ecode = caam_jr_strstatus(jrdev, err); - ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_FROM_DEVICE); + ahash_unmap_ctx(jrdev, edesc, req, digestsize, dir); memcpy(req->result, state->caam_ctx, digestsize); kfree(edesc); @@ -622,87 +633,49 @@ static void ahash_done(struct device *jrdev, u32 *desc, u32 err, DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx, ctx->ctx_len, 1); - req->base.complete(&req->base, ecode); + /* + * If no backlog flag, the completion of the request is done + * by CAAM, not crypto engine. + */ + if (!has_bklog) + req->base.complete(&req->base, ecode); + else + crypto_finalize_hash_request(jrp->engine, req, ecode); } -static void ahash_done_bi(struct device *jrdev, u32 *desc, u32 err, - void *context) +static void ahash_done(struct device *jrdev, u32 *desc, u32 err, + void *context) { - struct ahash_request *req = context; - struct ahash_edesc *edesc; - struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); - struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); - struct caam_hash_state *state = ahash_request_ctx(req); - int digestsize = crypto_ahash_digestsize(ahash); - int ecode = 0; - - dev_dbg(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err); - - edesc = container_of(desc, struct ahash_edesc, hw_desc[0]); - if (err) - ecode = caam_jr_strstatus(jrdev, err); - - ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_BIDIRECTIONAL); - switch_buf(state); - kfree(edesc); - - print_hex_dump_debug("ctx@"__stringify(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx, - ctx->ctx_len, 1); - if (req->result) - print_hex_dump_debug("result@"__stringify(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, req->result, - digestsize, 1); - - req->base.complete(&req->base, ecode); + ahash_done_cpy(jrdev, desc, err, context, DMA_FROM_DEVICE); } static void ahash_done_ctx_src(struct device *jrdev, u32 *desc, u32 err, void *context) { - struct ahash_request *req = context; - struct ahash_edesc *edesc; - struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); - int digestsize = crypto_ahash_digestsize(ahash); - struct caam_hash_state *state = ahash_request_ctx(req); - struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); - int ecode = 0; - - dev_dbg(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err); - - edesc = container_of(desc, struct ahash_edesc, hw_desc[0]); - if (err) - ecode = caam_jr_strstatus(jrdev, err); - - ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_BIDIRECTIONAL); - memcpy(req->result, state->caam_ctx, digestsize); - kfree(edesc); - - print_hex_dump_debug("ctx@"__stringify(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx, - ctx->ctx_len, 1); - - req->base.complete(&req->base, ecode); + ahash_done_cpy(jrdev, desc, err, context, DMA_BIDIRECTIONAL); } -static void ahash_done_ctx_dst(struct device *jrdev, u32 *desc, u32 err, - void *context) +static inline void ahash_done_switch(struct device *jrdev, u32 *desc, u32 err, + void *context, enum dma_data_direction dir) { struct ahash_request *req = context; + struct caam_drv_private_jr *jrp = dev_get_drvdata(jrdev); struct ahash_edesc *edesc; struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); struct caam_hash_state *state = ahash_request_ctx(req); int digestsize = crypto_ahash_digestsize(ahash); int ecode = 0; + bool has_bklog; dev_dbg(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err); - edesc = container_of(desc, struct ahash_edesc, hw_desc[0]); + edesc = state->edesc; + has_bklog = edesc->bklog; if (err) ecode = caam_jr_strstatus(jrdev, err); - ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_FROM_DEVICE); + ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, dir); switch_buf(state); kfree(edesc); @@ -714,18 +687,42 @@ static void ahash_done_ctx_dst(struct device *jrdev, u32 *desc, u32 err, DUMP_PREFIX_ADDRESS, 16, 4, req->result, digestsize, 1); - req->base.complete(&req->base, ecode); + /* + * If no backlog flag, the completion of the request is done + * by CAAM, not crypto engine. + */ + if (!has_bklog) + req->base.complete(&req->base, ecode); + else + crypto_finalize_hash_request(jrp->engine, req, ecode); + +} + +static void ahash_done_bi(struct device *jrdev, u32 *desc, u32 err, + void *context) +{ + ahash_done_switch(jrdev, desc, err, context, DMA_BIDIRECTIONAL); +} + +static void ahash_done_ctx_dst(struct device *jrdev, u32 *desc, u32 err, + void *context) +{ + ahash_done_switch(jrdev, desc, err, context, DMA_FROM_DEVICE); } /* * Allocate an enhanced descriptor, which contains the hardware descriptor * and space for hardware scatter table containing sg_num entries. */ -static struct ahash_edesc *ahash_edesc_alloc(struct caam_hash_ctx *ctx, +static struct ahash_edesc *ahash_edesc_alloc(struct ahash_request *req, int sg_num, u32 *sh_desc, - dma_addr_t sh_desc_dma, - gfp_t flags) + dma_addr_t sh_desc_dma) { + struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); + struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); + struct caam_hash_state *state = ahash_request_ctx(req); + gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? + GFP_KERNEL : GFP_ATOMIC; struct ahash_edesc *edesc; unsigned int sg_size = sg_num * sizeof(struct sec4_sg_entry); @@ -735,6 +732,8 @@ static struct ahash_edesc *ahash_edesc_alloc(struct caam_hash_ctx *ctx, return NULL; } + state->edesc = edesc; + init_job_desc_shared(edesc->hw_desc, sh_desc_dma, desc_len(sh_desc), HDR_SHARE_DEFER | HDR_REVERSE); @@ -777,6 +776,62 @@ static int ahash_edesc_add_src(struct caam_hash_ctx *ctx, return 0; } +static int ahash_do_one_req(struct crypto_engine *engine, void *areq) +{ + struct ahash_request *req = ahash_request_cast(areq); + struct caam_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); + struct caam_hash_state *state = ahash_request_ctx(req); + struct device *jrdev = ctx->jrdev; + u32 *desc = state->edesc->hw_desc; + int ret; + + state->edesc->bklog = true; + + ret = caam_jr_enqueue(jrdev, desc, state->ahash_op_done, req); + + if (ret != -EINPROGRESS) { + ahash_unmap(jrdev, state->edesc, req, 0); + kfree(state->edesc); + } else { + ret = 0; + } + + return ret; +} + +static int ahash_enqueue_req(struct device *jrdev, + void (*cbk)(struct device *jrdev, u32 *desc, + u32 err, void *context), + struct ahash_request *req, + int dst_len, enum dma_data_direction dir) +{ + struct caam_drv_private_jr *jrpriv = dev_get_drvdata(jrdev); + struct caam_hash_state *state = ahash_request_ctx(req); + struct ahash_edesc *edesc = state->edesc; + u32 *desc = edesc->hw_desc; + int ret; + + state->ahash_op_done = cbk; + + /* + * Only the backlog request are sent to crypto-engine since the others + * can be handled by CAAM, if free, especially since JR has up to 1024 + * entries (more than the 10 entries from crypto-engine). + */ + if (req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG) + ret = crypto_transfer_hash_request_to_engine(jrpriv->engine, + req); + else + ret = caam_jr_enqueue(jrdev, desc, cbk, req); + + if ((ret != -EINPROGRESS) && (ret != -EBUSY)) { + ahash_unmap_ctx(jrdev, edesc, req, dst_len, dir); + kfree(edesc); + } + + return ret; +} + /* submit update job descriptor */ static int ahash_update_ctx(struct ahash_request *req) { @@ -784,8 +839,6 @@ static int ahash_update_ctx(struct ahash_request *req) struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); struct caam_hash_state *state = ahash_request_ctx(req); struct device *jrdev = ctx->jrdev; - gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? - GFP_KERNEL : GFP_ATOMIC; u8 *buf = current_buf(state); int *buflen = current_buflen(state); u8 *next_buf = alt_buf(state); @@ -841,8 +894,8 @@ static int ahash_update_ctx(struct ahash_request *req) * allocate space for base edesc and hw desc commands, * link tables */ - edesc = ahash_edesc_alloc(ctx, pad_nents, ctx->sh_desc_update, - ctx->sh_desc_update_dma, flags); + edesc = ahash_edesc_alloc(req, pad_nents, ctx->sh_desc_update, + ctx->sh_desc_update_dma); if (!edesc) { dma_unmap_sg(jrdev, req->src, src_nents, DMA_TO_DEVICE); return -ENOMEM; @@ -892,11 +945,8 @@ static int ahash_update_ctx(struct ahash_request *req) DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); - ret = caam_jr_enqueue(jrdev, desc, ahash_done_bi, req); - if (ret) - goto unmap_ctx; - - ret = -EINPROGRESS; + ret = ahash_enqueue_req(jrdev, ahash_done_bi, req, + ctx->ctx_len, DMA_BIDIRECTIONAL); } else if (*next_buflen) { scatterwalk_map_and_copy(buf + *buflen, req->src, 0, req->nbytes, 0); @@ -923,8 +973,6 @@ static int ahash_final_ctx(struct ahash_request *req) struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); struct caam_hash_state *state = ahash_request_ctx(req); struct device *jrdev = ctx->jrdev; - gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? - GFP_KERNEL : GFP_ATOMIC; int buflen = *current_buflen(state); u32 *desc; int sec4_sg_bytes; @@ -936,8 +984,8 @@ static int ahash_final_ctx(struct ahash_request *req) sizeof(struct sec4_sg_entry); /* allocate space for base edesc and hw desc commands, link tables */ - edesc = ahash_edesc_alloc(ctx, 4, ctx->sh_desc_fin, - ctx->sh_desc_fin_dma, flags); + edesc = ahash_edesc_alloc(req, 4, ctx->sh_desc_fin, + ctx->sh_desc_fin_dma); if (!edesc) return -ENOMEM; @@ -972,11 +1020,8 @@ static int ahash_final_ctx(struct ahash_request *req) DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); - ret = caam_jr_enqueue(jrdev, desc, ahash_done_ctx_src, req); - if (ret) - goto unmap_ctx; - - return -EINPROGRESS; + return ahash_enqueue_req(jrdev, ahash_done_ctx_src, req, + digestsize, DMA_BIDIRECTIONAL); unmap_ctx: ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_BIDIRECTIONAL); kfree(edesc); @@ -989,8 +1034,6 @@ static int ahash_finup_ctx(struct ahash_request *req) struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); struct caam_hash_state *state = ahash_request_ctx(req); struct device *jrdev = ctx->jrdev; - gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? - GFP_KERNEL : GFP_ATOMIC; int buflen = *current_buflen(state); u32 *desc; int sec4_sg_src_index; @@ -1019,9 +1062,8 @@ static int ahash_finup_ctx(struct ahash_request *req) sec4_sg_src_index = 1 + (buflen ? 1 : 0); /* allocate space for base edesc and hw desc commands, link tables */ - edesc = ahash_edesc_alloc(ctx, sec4_sg_src_index + mapped_nents, - ctx->sh_desc_fin, ctx->sh_desc_fin_dma, - flags); + edesc = ahash_edesc_alloc(req, sec4_sg_src_index + mapped_nents, + ctx->sh_desc_fin, ctx->sh_desc_fin_dma); if (!edesc) { dma_unmap_sg(jrdev, req->src, src_nents, DMA_TO_DEVICE); return -ENOMEM; @@ -1052,11 +1094,8 @@ static int ahash_finup_ctx(struct ahash_request *req) DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); - ret = caam_jr_enqueue(jrdev, desc, ahash_done_ctx_src, req); - if (ret) - goto unmap_ctx; - - return -EINPROGRESS; + return ahash_enqueue_req(jrdev, ahash_done_ctx_src, req, + digestsize, DMA_BIDIRECTIONAL); unmap_ctx: ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_BIDIRECTIONAL); kfree(edesc); @@ -1069,8 +1108,6 @@ static int ahash_digest(struct ahash_request *req) struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); struct caam_hash_state *state = ahash_request_ctx(req); struct device *jrdev = ctx->jrdev; - gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? - GFP_KERNEL : GFP_ATOMIC; u32 *desc; int digestsize = crypto_ahash_digestsize(ahash); int src_nents, mapped_nents; @@ -1097,9 +1134,8 @@ static int ahash_digest(struct ahash_request *req) } /* allocate space for base edesc and hw desc commands, link tables */ - edesc = ahash_edesc_alloc(ctx, mapped_nents > 1 ? mapped_nents : 0, - ctx->sh_desc_digest, ctx->sh_desc_digest_dma, - flags); + edesc = ahash_edesc_alloc(req, mapped_nents > 1 ? mapped_nents : 0, + ctx->sh_desc_digest, ctx->sh_desc_digest_dma); if (!edesc) { dma_unmap_sg(jrdev, req->src, src_nents, DMA_TO_DEVICE); return -ENOMEM; @@ -1128,15 +1164,8 @@ static int ahash_digest(struct ahash_request *req) DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); - ret = caam_jr_enqueue(jrdev, desc, ahash_done, req); - if (!ret) { - ret = -EINPROGRESS; - } else { - ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_FROM_DEVICE); - kfree(edesc); - } - - return ret; + return ahash_enqueue_req(jrdev, ahash_done, req, digestsize, + DMA_FROM_DEVICE); } /* submit ahash final if it the first job descriptor */ @@ -1146,8 +1175,6 @@ static int ahash_final_no_ctx(struct ahash_request *req) struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); struct caam_hash_state *state = ahash_request_ctx(req); struct device *jrdev = ctx->jrdev; - gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? - GFP_KERNEL : GFP_ATOMIC; u8 *buf = current_buf(state); int buflen = *current_buflen(state); u32 *desc; @@ -1156,8 +1183,8 @@ static int ahash_final_no_ctx(struct ahash_request *req) int ret; /* allocate space for base edesc and hw desc commands, link tables */ - edesc = ahash_edesc_alloc(ctx, 0, ctx->sh_desc_digest, - ctx->sh_desc_digest_dma, flags); + edesc = ahash_edesc_alloc(req, 0, ctx->sh_desc_digest, + ctx->sh_desc_digest_dma); if (!edesc) return -ENOMEM; @@ -1182,20 +1209,12 @@ static int ahash_final_no_ctx(struct ahash_request *req) DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); - ret = caam_jr_enqueue(jrdev, desc, ahash_done, req); - if (!ret) { - ret = -EINPROGRESS; - } else { - ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_FROM_DEVICE); - kfree(edesc); - } - - return ret; + return ahash_enqueue_req(jrdev, ahash_done, req, + digestsize, DMA_FROM_DEVICE); unmap: ahash_unmap(jrdev, edesc, req, digestsize); kfree(edesc); return -ENOMEM; - } /* submit ahash update if it the first job descriptor after update */ @@ -1205,8 +1224,6 @@ static int ahash_update_no_ctx(struct ahash_request *req) struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); struct caam_hash_state *state = ahash_request_ctx(req); struct device *jrdev = ctx->jrdev; - gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? - GFP_KERNEL : GFP_ATOMIC; u8 *buf = current_buf(state); int *buflen = current_buflen(state); int blocksize = crypto_ahash_blocksize(ahash); @@ -1260,10 +1277,9 @@ static int ahash_update_no_ctx(struct ahash_request *req) * allocate space for base edesc and hw desc commands, * link tables */ - edesc = ahash_edesc_alloc(ctx, pad_nents, + edesc = ahash_edesc_alloc(req, pad_nents, ctx->sh_desc_update_first, - ctx->sh_desc_update_first_dma, - flags); + ctx->sh_desc_update_first_dma); if (!edesc) { dma_unmap_sg(jrdev, req->src, src_nents, DMA_TO_DEVICE); return -ENOMEM; @@ -1305,11 +1321,10 @@ static int ahash_update_no_ctx(struct ahash_request *req) DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); - ret = caam_jr_enqueue(jrdev, desc, ahash_done_ctx_dst, req); - if (ret) - goto unmap_ctx; - - ret = -EINPROGRESS; + ret = ahash_enqueue_req(jrdev, ahash_done_ctx_dst, req, + ctx->ctx_len, DMA_TO_DEVICE); + if ((ret != -EINPROGRESS) && (ret != -EBUSY)) + return ret; state->update = ahash_update_ctx; state->finup = ahash_finup_ctx; state->final = ahash_final_ctx; @@ -1340,8 +1355,6 @@ static int ahash_finup_no_ctx(struct ahash_request *req) struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); struct caam_hash_state *state = ahash_request_ctx(req); struct device *jrdev = ctx->jrdev; - gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? - GFP_KERNEL : GFP_ATOMIC; int buflen = *current_buflen(state); u32 *desc; int sec4_sg_bytes, sec4_sg_src_index, src_nents, mapped_nents; @@ -1371,9 +1384,8 @@ static int ahash_finup_no_ctx(struct ahash_request *req) sizeof(struct sec4_sg_entry); /* allocate space for base edesc and hw desc commands, link tables */ - edesc = ahash_edesc_alloc(ctx, sec4_sg_src_index + mapped_nents, - ctx->sh_desc_digest, ctx->sh_desc_digest_dma, - flags); + edesc = ahash_edesc_alloc(req, sec4_sg_src_index + mapped_nents, + ctx->sh_desc_digest, ctx->sh_desc_digest_dma); if (!edesc) { dma_unmap_sg(jrdev, req->src, src_nents, DMA_TO_DEVICE); return -ENOMEM; @@ -1403,15 +1415,8 @@ static int ahash_finup_no_ctx(struct ahash_request *req) DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); - ret = caam_jr_enqueue(jrdev, desc, ahash_done, req); - if (!ret) { - ret = -EINPROGRESS; - } else { - ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_FROM_DEVICE); - kfree(edesc); - } - - return ret; + return ahash_enqueue_req(jrdev, ahash_done, req, + digestsize, DMA_FROM_DEVICE); unmap: ahash_unmap(jrdev, edesc, req, digestsize); kfree(edesc); @@ -1426,8 +1431,6 @@ static int ahash_update_first(struct ahash_request *req) struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); struct caam_hash_state *state = ahash_request_ctx(req); struct device *jrdev = ctx->jrdev; - gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? - GFP_KERNEL : GFP_ATOMIC; u8 *next_buf = alt_buf(state); int *next_buflen = alt_buflen(state); int to_hash; @@ -1474,11 +1477,10 @@ static int ahash_update_first(struct ahash_request *req) * allocate space for base edesc and hw desc commands, * link tables */ - edesc = ahash_edesc_alloc(ctx, mapped_nents > 1 ? + edesc = ahash_edesc_alloc(req, mapped_nents > 1 ? mapped_nents : 0, ctx->sh_desc_update_first, - ctx->sh_desc_update_first_dma, - flags); + ctx->sh_desc_update_first_dma); if (!edesc) { dma_unmap_sg(jrdev, req->src, src_nents, DMA_TO_DEVICE); return -ENOMEM; @@ -1505,11 +1507,10 @@ static int ahash_update_first(struct ahash_request *req) DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); - ret = caam_jr_enqueue(jrdev, desc, ahash_done_ctx_dst, req); - if (ret) - goto unmap_ctx; - - ret = -EINPROGRESS; + ret = ahash_enqueue_req(jrdev, ahash_done_ctx_dst, req, + ctx->ctx_len, DMA_TO_DEVICE); + if ((ret != -EINPROGRESS) && (ret != -EBUSY)) + return ret; state->update = ahash_update_ctx; state->finup = ahash_finup_ctx; state->final = ahash_final_ctx; @@ -1821,6 +1822,8 @@ static int caam_hash_cra_init(struct crypto_tfm *tfm) HASH_MSG_LEN + SHA256_DIGEST_SIZE, HASH_MSG_LEN + 64, HASH_MSG_LEN + SHA512_DIGEST_SIZE }; + const size_t sh_desc_update_offset = offsetof(struct caam_hash_ctx, + sh_desc_update); dma_addr_t dma_addr; struct caam_drv_private *priv; @@ -1873,7 +1876,8 @@ static int caam_hash_cra_init(struct crypto_tfm *tfm) } dma_addr = dma_map_single_attrs(ctx->jrdev, ctx->sh_desc_update, - offsetof(struct caam_hash_ctx, key), + offsetof(struct caam_hash_ctx, key) - + sh_desc_update_offset, ctx->dir, DMA_ATTR_SKIP_CPU_SYNC); if (dma_mapping_error(ctx->jrdev, dma_addr)) { dev_err(ctx->jrdev, "unable to map shared descriptors\n"); @@ -1891,11 +1895,16 @@ static int caam_hash_cra_init(struct crypto_tfm *tfm) ctx->sh_desc_update_dma = dma_addr; ctx->sh_desc_update_first_dma = dma_addr + offsetof(struct caam_hash_ctx, - sh_desc_update_first); + sh_desc_update_first) - + sh_desc_update_offset; ctx->sh_desc_fin_dma = dma_addr + offsetof(struct caam_hash_ctx, - sh_desc_fin); + sh_desc_fin) - + sh_desc_update_offset; ctx->sh_desc_digest_dma = dma_addr + offsetof(struct caam_hash_ctx, - sh_desc_digest); + sh_desc_digest) - + sh_desc_update_offset; + + ctx->enginectx.op.do_one_request = ahash_do_one_req; crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), sizeof(struct caam_hash_state)); @@ -1912,7 +1921,8 @@ static void caam_hash_cra_exit(struct crypto_tfm *tfm) struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm); dma_unmap_single_attrs(ctx->jrdev, ctx->sh_desc_update_dma, - offsetof(struct caam_hash_ctx, key), + offsetof(struct caam_hash_ctx, key) - + offsetof(struct caam_hash_ctx, sh_desc_update), ctx->dir, DMA_ATTR_SKIP_CPU_SYNC); if (ctx->key_dir != DMA_NONE) dma_unmap_single_attrs(ctx->jrdev, ctx->adata.key_dma, @@ -1991,12 +2001,14 @@ int caam_algapi_hash_init(struct device *ctrldev) * presence and attributes of MD block. */ if (priv->era < 10) { - md_vid = (rd_reg32(&priv->ctrl->perfmon.cha_id_ls) & + struct caam_perfmon __iomem *perfmon = &priv->jr[0]->perfmon; + + md_vid = (rd_reg32(&perfmon->cha_id_ls) & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT; - md_inst = (rd_reg32(&priv->ctrl->perfmon.cha_num_ls) & + md_inst = (rd_reg32(&perfmon->cha_num_ls) & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT; } else { - u32 mdha = rd_reg32(&priv->ctrl->vreg.mdha); + u32 mdha = rd_reg32(&priv->jr[0]->vreg.mdha); md_vid = (mdha & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT; md_inst = mdha & CHA_VER_NUM_MASK; diff --git a/drivers/crypto/caam/caampkc.c b/drivers/crypto/caam/caampkc.c index 83f96d4f86e036..bfbb8d3e5716f2 100644 --- a/drivers/crypto/caam/caampkc.c +++ b/drivers/crypto/caam/caampkc.c @@ -117,76 +117,73 @@ static void rsa_priv_f3_unmap(struct device *dev, struct rsa_edesc *edesc, static void rsa_pub_done(struct device *dev, u32 *desc, u32 err, void *context) { struct akcipher_request *req = context; + struct caam_rsa_req_ctx *req_ctx = akcipher_request_ctx(req); + struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); struct rsa_edesc *edesc; int ecode = 0; + bool has_bklog; if (err) ecode = caam_jr_strstatus(dev, err); - edesc = container_of(desc, struct rsa_edesc, hw_desc[0]); + edesc = req_ctx->edesc; + has_bklog = edesc->bklog; rsa_pub_unmap(dev, edesc, req); rsa_io_unmap(dev, edesc, req); kfree(edesc); - akcipher_request_complete(req, ecode); -} - -static void rsa_priv_f1_done(struct device *dev, u32 *desc, u32 err, - void *context) -{ - struct akcipher_request *req = context; - struct rsa_edesc *edesc; - int ecode = 0; - - if (err) - ecode = caam_jr_strstatus(dev, err); - - edesc = container_of(desc, struct rsa_edesc, hw_desc[0]); - - rsa_priv_f1_unmap(dev, edesc, req); - rsa_io_unmap(dev, edesc, req); - kfree(edesc); - - akcipher_request_complete(req, ecode); -} - -static void rsa_priv_f2_done(struct device *dev, u32 *desc, u32 err, - void *context) -{ - struct akcipher_request *req = context; - struct rsa_edesc *edesc; - int ecode = 0; - - if (err) - ecode = caam_jr_strstatus(dev, err); - - edesc = container_of(desc, struct rsa_edesc, hw_desc[0]); - - rsa_priv_f2_unmap(dev, edesc, req); - rsa_io_unmap(dev, edesc, req); - kfree(edesc); - - akcipher_request_complete(req, ecode); + /* + * If no backlog flag, the completion of the request is done + * by CAAM, not crypto engine. + */ + if (!has_bklog) + akcipher_request_complete(req, ecode); + else + crypto_finalize_akcipher_request(jrp->engine, req, ecode); } -static void rsa_priv_f3_done(struct device *dev, u32 *desc, u32 err, - void *context) +static void rsa_priv_f_done(struct device *dev, u32 *desc, u32 err, + void *context) { struct akcipher_request *req = context; + struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req); + struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); + struct caam_rsa_ctx *ctx = akcipher_tfm_ctx(tfm); + struct caam_rsa_key *key = &ctx->key; + struct caam_rsa_req_ctx *req_ctx = akcipher_request_ctx(req); struct rsa_edesc *edesc; int ecode = 0; + bool has_bklog; if (err) ecode = caam_jr_strstatus(dev, err); - edesc = container_of(desc, struct rsa_edesc, hw_desc[0]); + edesc = req_ctx->edesc; + has_bklog = edesc->bklog; + + switch (key->priv_form) { + case FORM1: + rsa_priv_f1_unmap(dev, edesc, req); + break; + case FORM2: + rsa_priv_f2_unmap(dev, edesc, req); + break; + case FORM3: + rsa_priv_f3_unmap(dev, edesc, req); + } - rsa_priv_f3_unmap(dev, edesc, req); rsa_io_unmap(dev, edesc, req); kfree(edesc); - akcipher_request_complete(req, ecode); + /* + * If no backlog flag, the completion of the request is done + * by CAAM, not crypto engine. + */ + if (!has_bklog) + akcipher_request_complete(req, ecode); + else + crypto_finalize_akcipher_request(jrp->engine, req, ecode); } /** @@ -252,9 +249,9 @@ static struct rsa_edesc *rsa_edesc_alloc(struct akcipher_request *req, gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? GFP_KERNEL : GFP_ATOMIC; int sg_flags = (flags == GFP_ATOMIC) ? SG_MITER_ATOMIC : 0; - int sgc; int sec4_sg_index, sec4_sg_len = 0, sec4_sg_bytes; int src_nents, dst_nents; + int mapped_src_nents, mapped_dst_nents; unsigned int diff_size = 0; int lzeros; @@ -285,13 +282,27 @@ static struct rsa_edesc *rsa_edesc_alloc(struct akcipher_request *req, req_ctx->fixup_src_len); dst_nents = sg_nents_for_len(req->dst, req->dst_len); - if (!diff_size && src_nents == 1) + mapped_src_nents = dma_map_sg(dev, req_ctx->fixup_src, src_nents, + DMA_TO_DEVICE); + if (unlikely(!mapped_src_nents)) { + dev_err(dev, "unable to map source\n"); + return ERR_PTR(-ENOMEM); + } + mapped_dst_nents = dma_map_sg(dev, req->dst, dst_nents, + DMA_FROM_DEVICE); + if (unlikely(!mapped_dst_nents)) { + dev_err(dev, "unable to map destination\n"); + goto src_fail; + } + + if (!diff_size && mapped_src_nents == 1) sec4_sg_len = 0; /* no need for an input hw s/g table */ else - sec4_sg_len = src_nents + !!diff_size; + sec4_sg_len = mapped_src_nents + !!diff_size; sec4_sg_index = sec4_sg_len; - if (dst_nents > 1) - sec4_sg_len += pad_sg_nents(dst_nents); + + if (mapped_dst_nents > 1) + sec4_sg_len += pad_sg_nents(mapped_dst_nents); else sec4_sg_len = pad_sg_nents(sec4_sg_len); @@ -301,19 +312,7 @@ static struct rsa_edesc *rsa_edesc_alloc(struct akcipher_request *req, edesc = kzalloc(sizeof(*edesc) + desclen + sec4_sg_bytes, GFP_DMA | flags); if (!edesc) - return ERR_PTR(-ENOMEM); - - sgc = dma_map_sg(dev, req_ctx->fixup_src, src_nents, DMA_TO_DEVICE); - if (unlikely(!sgc)) { - dev_err(dev, "unable to map source\n"); - goto src_fail; - } - - sgc = dma_map_sg(dev, req->dst, dst_nents, DMA_FROM_DEVICE); - if (unlikely(!sgc)) { - dev_err(dev, "unable to map destination\n"); goto dst_fail; - } edesc->sec4_sg = (void *)edesc + sizeof(*edesc) + desclen; if (diff_size) @@ -324,7 +323,7 @@ static struct rsa_edesc *rsa_edesc_alloc(struct akcipher_request *req, sg_to_sec4_sg_last(req_ctx->fixup_src, req_ctx->fixup_src_len, edesc->sec4_sg + !!diff_size, 0); - if (dst_nents > 1) + if (mapped_dst_nents > 1) sg_to_sec4_sg_last(req->dst, req->dst_len, edesc->sec4_sg + sec4_sg_index, 0); @@ -332,9 +331,14 @@ static struct rsa_edesc *rsa_edesc_alloc(struct akcipher_request *req, edesc->src_nents = src_nents; edesc->dst_nents = dst_nents; + req_ctx->edesc = edesc; + if (!sec4_sg_bytes) return edesc; + edesc->mapped_src_nents = mapped_src_nents; + edesc->mapped_dst_nents = mapped_dst_nents; + edesc->sec4_sg_dma = dma_map_single(dev, edesc->sec4_sg, sec4_sg_bytes, DMA_TO_DEVICE); if (dma_mapping_error(dev, edesc->sec4_sg_dma)) { @@ -351,14 +355,41 @@ static struct rsa_edesc *rsa_edesc_alloc(struct akcipher_request *req, return edesc; sec4_sg_fail: - dma_unmap_sg(dev, req->dst, dst_nents, DMA_FROM_DEVICE); + kfree(edesc); dst_fail: - dma_unmap_sg(dev, req_ctx->fixup_src, src_nents, DMA_TO_DEVICE); + dma_unmap_sg(dev, req->dst, dst_nents, DMA_FROM_DEVICE); src_fail: - kfree(edesc); + dma_unmap_sg(dev, req_ctx->fixup_src, src_nents, DMA_TO_DEVICE); return ERR_PTR(-ENOMEM); } +static int akcipher_do_one_req(struct crypto_engine *engine, void *areq) +{ + struct akcipher_request *req = container_of(areq, + struct akcipher_request, + base); + struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req); + struct caam_rsa_req_ctx *req_ctx = akcipher_request_ctx(req); + struct caam_rsa_ctx *ctx = akcipher_tfm_ctx(tfm); + struct device *jrdev = ctx->dev; + u32 *desc = req_ctx->edesc->hw_desc; + int ret; + + req_ctx->edesc->bklog = true; + + ret = caam_jr_enqueue(jrdev, desc, req_ctx->akcipher_op_done, req); + + if (ret != -EINPROGRESS) { + rsa_pub_unmap(jrdev, req_ctx->edesc, req); + rsa_io_unmap(jrdev, req_ctx->edesc, req); + kfree(req_ctx->edesc); + } else { + ret = 0; + } + + return ret; +} + static int set_rsa_pub_pdb(struct akcipher_request *req, struct rsa_edesc *edesc) { @@ -383,15 +414,15 @@ static int set_rsa_pub_pdb(struct akcipher_request *req, return -ENOMEM; } - if (edesc->src_nents > 1) { + if (edesc->mapped_src_nents > 1) { pdb->sgf |= RSA_PDB_SGF_F; pdb->f_dma = edesc->sec4_sg_dma; - sec4_sg_index += edesc->src_nents; + sec4_sg_index += edesc->mapped_src_nents; } else { pdb->f_dma = sg_dma_address(req_ctx->fixup_src); } - if (edesc->dst_nents > 1) { + if (edesc->mapped_dst_nents > 1) { pdb->sgf |= RSA_PDB_SGF_G; pdb->g_dma = edesc->sec4_sg_dma + sec4_sg_index * sizeof(struct sec4_sg_entry); @@ -428,17 +459,18 @@ static int set_rsa_priv_f1_pdb(struct akcipher_request *req, return -ENOMEM; } - if (edesc->src_nents > 1) { + if (edesc->mapped_src_nents > 1) { pdb->sgf |= RSA_PRIV_PDB_SGF_G; pdb->g_dma = edesc->sec4_sg_dma; - sec4_sg_index += edesc->src_nents; + sec4_sg_index += edesc->mapped_src_nents; + } else { struct caam_rsa_req_ctx *req_ctx = akcipher_request_ctx(req); pdb->g_dma = sg_dma_address(req_ctx->fixup_src); } - if (edesc->dst_nents > 1) { + if (edesc->mapped_dst_nents > 1) { pdb->sgf |= RSA_PRIV_PDB_SGF_F; pdb->f_dma = edesc->sec4_sg_dma + sec4_sg_index * sizeof(struct sec4_sg_entry); @@ -493,17 +525,17 @@ static int set_rsa_priv_f2_pdb(struct akcipher_request *req, goto unmap_tmp1; } - if (edesc->src_nents > 1) { + if (edesc->mapped_src_nents > 1) { pdb->sgf |= RSA_PRIV_PDB_SGF_G; pdb->g_dma = edesc->sec4_sg_dma; - sec4_sg_index += edesc->src_nents; + sec4_sg_index += edesc->mapped_src_nents; } else { struct caam_rsa_req_ctx *req_ctx = akcipher_request_ctx(req); pdb->g_dma = sg_dma_address(req_ctx->fixup_src); } - if (edesc->dst_nents > 1) { + if (edesc->mapped_dst_nents > 1) { pdb->sgf |= RSA_PRIV_PDB_SGF_F; pdb->f_dma = edesc->sec4_sg_dma + sec4_sg_index * sizeof(struct sec4_sg_entry); @@ -582,17 +614,17 @@ static int set_rsa_priv_f3_pdb(struct akcipher_request *req, goto unmap_tmp1; } - if (edesc->src_nents > 1) { + if (edesc->mapped_src_nents > 1) { pdb->sgf |= RSA_PRIV_PDB_SGF_G; pdb->g_dma = edesc->sec4_sg_dma; - sec4_sg_index += edesc->src_nents; + sec4_sg_index += edesc->mapped_src_nents; } else { struct caam_rsa_req_ctx *req_ctx = akcipher_request_ctx(req); pdb->g_dma = sg_dma_address(req_ctx->fixup_src); } - if (edesc->dst_nents > 1) { + if (edesc->mapped_dst_nents > 1) { pdb->sgf |= RSA_PRIV_PDB_SGF_F; pdb->f_dma = edesc->sec4_sg_dma + sec4_sg_index * sizeof(struct sec4_sg_entry); @@ -621,6 +653,53 @@ static int set_rsa_priv_f3_pdb(struct akcipher_request *req, return -ENOMEM; } +static int akcipher_enqueue_req(struct device *jrdev, + void (*cbk)(struct device *jrdev, u32 *desc, + u32 err, void *context), + struct akcipher_request *req) +{ + struct caam_drv_private_jr *jrpriv = dev_get_drvdata(jrdev); + struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req); + struct caam_rsa_ctx *ctx = akcipher_tfm_ctx(tfm); + struct caam_rsa_key *key = &ctx->key; + struct caam_rsa_req_ctx *req_ctx = akcipher_request_ctx(req); + struct rsa_edesc *edesc = req_ctx->edesc; + u32 *desc = edesc->hw_desc; + int ret; + + req_ctx->akcipher_op_done = cbk; + /* + * Only the backlog request are sent to crypto-engine since the others + * can be handled by CAAM, if free, especially since JR has up to 1024 + * entries (more than the 10 entries from crypto-engine). + */ + if (req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG) + ret = crypto_transfer_akcipher_request_to_engine(jrpriv->engine, + req); + else + ret = caam_jr_enqueue(jrdev, desc, cbk, req); + + if ((ret != -EINPROGRESS) && (ret != -EBUSY)) { + switch (key->priv_form) { + case FORM1: + rsa_priv_f1_unmap(jrdev, edesc, req); + break; + case FORM2: + rsa_priv_f2_unmap(jrdev, edesc, req); + break; + case FORM3: + rsa_priv_f3_unmap(jrdev, edesc, req); + break; + default: + rsa_pub_unmap(jrdev, edesc, req); + } + rsa_io_unmap(jrdev, edesc, req); + kfree(edesc); + } + + return ret; +} + static int caam_rsa_enc(struct akcipher_request *req) { struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req); @@ -652,11 +731,7 @@ static int caam_rsa_enc(struct akcipher_request *req) /* Initialize Job Descriptor */ init_rsa_pub_desc(edesc->hw_desc, &edesc->pdb.pub); - ret = caam_jr_enqueue(jrdev, edesc->hw_desc, rsa_pub_done, req); - if (!ret) - return -EINPROGRESS; - - rsa_pub_unmap(jrdev, edesc, req); + return akcipher_enqueue_req(jrdev, rsa_pub_done, req); init_fail: rsa_io_unmap(jrdev, edesc, req); @@ -685,11 +760,7 @@ static int caam_rsa_dec_priv_f1(struct akcipher_request *req) /* Initialize Job Descriptor */ init_rsa_priv_f1_desc(edesc->hw_desc, &edesc->pdb.priv_f1); - ret = caam_jr_enqueue(jrdev, edesc->hw_desc, rsa_priv_f1_done, req); - if (!ret) - return -EINPROGRESS; - - rsa_priv_f1_unmap(jrdev, edesc, req); + return akcipher_enqueue_req(jrdev, rsa_priv_f_done, req); init_fail: rsa_io_unmap(jrdev, edesc, req); @@ -718,11 +789,7 @@ static int caam_rsa_dec_priv_f2(struct akcipher_request *req) /* Initialize Job Descriptor */ init_rsa_priv_f2_desc(edesc->hw_desc, &edesc->pdb.priv_f2); - ret = caam_jr_enqueue(jrdev, edesc->hw_desc, rsa_priv_f2_done, req); - if (!ret) - return -EINPROGRESS; - - rsa_priv_f2_unmap(jrdev, edesc, req); + return akcipher_enqueue_req(jrdev, rsa_priv_f_done, req); init_fail: rsa_io_unmap(jrdev, edesc, req); @@ -751,11 +818,7 @@ static int caam_rsa_dec_priv_f3(struct akcipher_request *req) /* Initialize Job Descriptor */ init_rsa_priv_f3_desc(edesc->hw_desc, &edesc->pdb.priv_f3); - ret = caam_jr_enqueue(jrdev, edesc->hw_desc, rsa_priv_f3_done, req); - if (!ret) - return -EINPROGRESS; - - rsa_priv_f3_unmap(jrdev, edesc, req); + return akcipher_enqueue_req(jrdev, rsa_priv_f_done, req); init_fail: rsa_io_unmap(jrdev, edesc, req); @@ -1048,6 +1111,8 @@ static int caam_rsa_init_tfm(struct crypto_akcipher *tfm) return -ENOMEM; } + ctx->enginectx.op.do_one_request = akcipher_do_one_req; + return 0; } @@ -1093,10 +1158,10 @@ int caam_pkc_init(struct device *ctrldev) /* Determine public key hardware accelerator presence. */ if (priv->era < 10) - pk_inst = (rd_reg32(&priv->ctrl->perfmon.cha_num_ls) & + pk_inst = (rd_reg32(&priv->jr[0]->perfmon.cha_num_ls) & CHA_ID_LS_PK_MASK) >> CHA_ID_LS_PK_SHIFT; else - pk_inst = rd_reg32(&priv->ctrl->vreg.pkha) & CHA_VER_NUM_MASK; + pk_inst = rd_reg32(&priv->jr[0]->vreg.pkha) & CHA_VER_NUM_MASK; /* Do not register algorithms if PKHA is not present. */ if (!pk_inst) diff --git a/drivers/crypto/caam/caampkc.h b/drivers/crypto/caam/caampkc.h index 2c488c9a38128e..cc889a525e2fe5 100644 --- a/drivers/crypto/caam/caampkc.h +++ b/drivers/crypto/caam/caampkc.h @@ -12,6 +12,7 @@ #define _PKC_DESC_H_ #include "compat.h" #include "pdb.h" +#include /** * caam_priv_key_form - CAAM RSA private key representation @@ -87,11 +88,13 @@ struct caam_rsa_key { /** * caam_rsa_ctx - per session context. + * @enginectx : crypto engine context * @key : RSA key in DMA zone * @dev : device structure * @padding_dma : dma address of padding, for adding it to the input */ struct caam_rsa_ctx { + struct crypto_engine_ctx enginectx; struct caam_rsa_key key; struct device *dev; dma_addr_t padding_dma; @@ -103,18 +106,26 @@ struct caam_rsa_ctx { * @src : input scatterlist (stripped of leading zeros) * @fixup_src : input scatterlist (that might be stripped of leading zeros) * @fixup_src_len : length of the fixup_src input scatterlist + * @edesc : s/w-extended rsa descriptor + * @akcipher_op_done : callback used when operation is done */ struct caam_rsa_req_ctx { struct scatterlist src[2]; struct scatterlist *fixup_src; unsigned int fixup_src_len; + struct rsa_edesc *edesc; + void (*akcipher_op_done)(struct device *jrdev, u32 *desc, u32 err, + void *context); }; /** * rsa_edesc - s/w-extended rsa descriptor - * @src_nents : number of segments in input scatterlist - * @dst_nents : number of segments in output scatterlist + * @src_nents : number of segments in input s/w scatterlist + * @dst_nents : number of segments in output s/w scatterlist + * @mapped_src_nents: number of segments in input h/w link table + * @mapped_dst_nents: number of segments in output h/w link table * @sec4_sg_bytes : length of h/w link table + * @bklog : stored to determine if the request needs backlog * @sec4_sg_dma : dma address of h/w link table * @sec4_sg : pointer to h/w link table * @pdb : specific RSA Protocol Data Block (PDB) @@ -123,7 +134,10 @@ struct caam_rsa_req_ctx { struct rsa_edesc { int src_nents; int dst_nents; + int mapped_src_nents; + int mapped_dst_nents; int sec4_sg_bytes; + bool bklog; dma_addr_t sec4_sg_dma; struct sec4_sg_entry *sec4_sg; union { diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c index e8baacaabe07fb..bfbc62f9185baa 100644 --- a/drivers/crypto/caam/caamrng.c +++ b/drivers/crypto/caam/caamrng.c @@ -133,7 +133,7 @@ static inline int submit_job(struct caam_rng_ctx *ctx, int to_current) dev_dbg(jrdev, "submitting job %d\n", !(to_current ^ ctx->current_buf)); init_completion(&bd->filled); err = caam_jr_enqueue(jrdev, desc, rng_done, ctx); - if (err) + if (err != -EINPROGRESS) complete(&bd->filled); /* don't wait on failed job*/ else atomic_inc(&bd->empty); /* note if pending */ @@ -153,7 +153,7 @@ static int caam_read(struct hwrng *rng, void *data, size_t max, bool wait) if (atomic_read(&bd->empty) == BUF_EMPTY) { err = submit_job(ctx, 1); /* if can't submit job, can't even wait */ - if (err) + if (err != -EINPROGRESS) return 0; } /* no immediate data, so exit if not waiting */ @@ -258,6 +258,49 @@ static void caam_cleanup(struct hwrng *rng) rng_unmap_ctx(rng_ctx); } +#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST +static inline void test_len(struct hwrng *rng, size_t len, bool wait) +{ + u8 *buf; + int real_len; + + buf = kzalloc(sizeof(u8) * len, GFP_KERNEL); + real_len = rng->read(rng, buf, len, wait); + if (real_len == 0 && wait) + pr_err("WAITING FAILED\n"); + pr_info("wanted %zu bytes, got %d\n", len, real_len); + print_hex_dump(KERN_INFO, "random bytes@: ", DUMP_PREFIX_ADDRESS, + 16, 4, buf, real_len, 1); + kfree(buf); +} + +static inline void test_mode_once(struct hwrng *rng, bool wait) +{ +#define TEST_CHUNK (RN_BUF_SIZE / 4) + + test_len(rng, TEST_CHUNK, wait); + test_len(rng, RN_BUF_SIZE * 2, wait); + test_len(rng, RN_BUF_SIZE * 2 - TEST_CHUNK, wait); +} + +static inline void test_mode(struct hwrng *rng, bool wait) +{ +#define TEST_PASS 1 + int i; + + for (i = 0; i < TEST_PASS; i++) + test_mode_once(rng, wait); +} + +static void self_test(struct hwrng *rng) +{ + pr_info("testing without waiting\n"); + test_mode(rng, false); + pr_info("testing with waiting\n"); + test_mode(rng, true); +} +#endif + static int caam_init_buf(struct caam_rng_ctx *ctx, int buf_id) { struct buf_data *bd = &ctx->bufs[buf_id]; @@ -320,10 +363,10 @@ int caam_rng_init(struct device *ctrldev) /* Check for an instantiated RNG before registration */ if (priv->era < 10) - rng_inst = (rd_reg32(&priv->ctrl->perfmon.cha_num_ls) & + rng_inst = (rd_reg32(&priv->jr[0]->perfmon.cha_num_ls) & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT; else - rng_inst = rd_reg32(&priv->ctrl->vreg.rng) & CHA_VER_NUM_MASK; + rng_inst = rd_reg32(&priv->jr[0]->vreg.rng) & CHA_VER_NUM_MASK; if (!rng_inst) return 0; @@ -342,6 +385,10 @@ int caam_rng_init(struct device *ctrldev) if (err) goto free_rng_ctx; +#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST + self_test(&caam_rng); +#endif + dev_info(dev, "registering rng-caam\n"); err = hwrng_register(&caam_rng); diff --git a/drivers/crypto/caam/compat.h b/drivers/crypto/caam/compat.h index c3c22a8de4c00a..60e2a54c19f112 100644 --- a/drivers/crypto/caam/compat.h +++ b/drivers/crypto/caam/compat.h @@ -43,6 +43,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c index 62930351ccd934..eb7d7419c26539 100644 --- a/drivers/crypto/caam/ctrl.c +++ b/drivers/crypto/caam/ctrl.c @@ -17,6 +17,7 @@ #include "jr.h" #include "desc_constr.h" #include "ctrl.h" +#include "sm.h" bool caam_dpaa2; EXPORT_SYMBOL(caam_dpaa2); @@ -99,10 +100,13 @@ static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc, if (ctrlpriv->virt_en == 1 || /* - * Apparently on i.MX8MQ it doesn't matter if virt_en == 1 + * Apparently on i.MX8M{Q,M,N,P} it doesn't matter if virt_en == 1 * and the following steps should be performed regardless */ - of_machine_is_compatible("fsl,imx8mq")) { + of_machine_is_compatible("fsl,imx8mq") || + of_machine_is_compatible("fsl,imx8mm") || + of_machine_is_compatible("fsl,imx8mn") || + of_machine_is_compatible("fsl,imx8mp")) { clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0); while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) && @@ -175,6 +179,73 @@ static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc, return 0; } +/* + * deinstantiate_rng - builds and executes a descriptor on DECO0, + * which deinitializes the RNG block. + * @ctrldev - pointer to device + * @state_handle_mask - bitmask containing the instantiation status + * for the RNG4 state handles which exist in + * the RNG4 block: 1 if it's been instantiated + * + * Return: - 0 if no error occurred + * - -ENOMEM if there isn't enough memory to allocate the descriptor + * - -ENODEV if DECO0 couldn't be acquired + * - -EAGAIN if an error occurred when executing the descriptor + */ +static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask) +{ + u32 *desc, status; + int sh_idx, ret = 0; + + desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL); + if (!desc) + return -ENOMEM; + + for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) { + /* + * If the corresponding bit is set, then it means the state + * handle was initialized by us, and thus it needs to be + * deinitialized as well + */ + if ((1 << sh_idx) & state_handle_mask) { + /* + * Create the descriptor for deinstantating this state + * handle + */ + build_deinstantiation_desc(desc, sh_idx); + + /* Try to run it through DECO0 */ + ret = run_descriptor_deco0(ctrldev, desc, &status); + + if (ret || + (status && status != JRSTA_SSRC_JUMP_HALT_CC)) { + dev_err(ctrldev, + "Failed to deinstantiate RNG4 SH%d\n", + sh_idx); + break; + } + dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx); + } + } + + kfree(desc); + + return ret; +} + +static void devm_deinstantiate_rng(void *data) +{ + struct device *ctrldev = data; + struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); + + /* + * De-initialize RNG state handles initialized by this driver. + * In case of SoCs with Management Complex, RNG is managed by MC f/w. + */ + if (ctrlpriv->rng4_sh_init) + deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init); +} + /* * instantiate_rng - builds and executes a descriptor on DECO0, * which initializes the RNG block. @@ -247,109 +318,22 @@ static int instantiate_rng(struct device *ctrldev, int state_handle_mask, kfree(desc); - return ret; -} - -/* - * deinstantiate_rng - builds and executes a descriptor on DECO0, - * which deinitializes the RNG block. - * @ctrldev - pointer to device - * @state_handle_mask - bitmask containing the instantiation status - * for the RNG4 state handles which exist in - * the RNG4 block: 1 if it's been instantiated - * - * Return: - 0 if no error occurred - * - -ENOMEM if there isn't enough memory to allocate the descriptor - * - -ENODEV if DECO0 couldn't be acquired - * - -EAGAIN if an error occurred when executing the descriptor - */ -static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask) -{ - u32 *desc, status; - int sh_idx, ret = 0; - - desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL); - if (!desc) - return -ENOMEM; - - for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) { - /* - * If the corresponding bit is set, then it means the state - * handle was initialized by us, and thus it needs to be - * deinitialized as well - */ - if ((1 << sh_idx) & state_handle_mask) { - /* - * Create the descriptor for deinstantating this state - * handle - */ - build_deinstantiation_desc(desc, sh_idx); - - /* Try to run it through DECO0 */ - ret = run_descriptor_deco0(ctrldev, desc, &status); - - if (ret || - (status && status != JRSTA_SSRC_JUMP_HALT_CC)) { - dev_err(ctrldev, - "Failed to deinstantiate RNG4 SH%d\n", - sh_idx); - break; - } - dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx); - } - } - - kfree(desc); + if (!ret) + ret = devm_add_action_or_reset(ctrldev, devm_deinstantiate_rng, + ctrldev); return ret; } -static int caam_remove(struct platform_device *pdev) -{ - struct device *ctrldev; - struct caam_drv_private *ctrlpriv; - struct caam_ctrl __iomem *ctrl; - - ctrldev = &pdev->dev; - ctrlpriv = dev_get_drvdata(ctrldev); - ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; - - /* Remove platform devices under the crypto node */ - of_platform_depopulate(ctrldev); - -#ifdef CONFIG_CAAM_QI - if (ctrlpriv->qi_init) - caam_qi_shutdown(ctrldev); -#endif - - /* - * De-initialize RNG state handles initialized by this driver. - * In case of SoCs with Management Complex, RNG is managed by MC f/w. - */ - if (!ctrlpriv->mc_en && ctrlpriv->rng4_sh_init) - deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init); - - /* Shut down debug views */ -#ifdef CONFIG_DEBUG_FS - debugfs_remove_recursive(ctrlpriv->dfs_root); -#endif - - /* Unmap controller region */ - iounmap(ctrl); - - return 0; -} - /* * kick_trng - sets the various parameters for enabling the initialization * of the RNG4 block in CAAM - * @pdev - pointer to the platform device + * @dev - pointer to the controller device * @ent_delay - Defines the length (in system clocks) of each entropy sample. */ -static void kick_trng(struct platform_device *pdev, int ent_delay) +static void kick_trng(struct device *dev, int ent_delay) { - struct device *ctrldev = &pdev->dev; - struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); + struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev); struct caam_ctrl __iomem *ctrl; struct rng4tst __iomem *r4tst; u32 val; @@ -358,7 +342,11 @@ static void kick_trng(struct platform_device *pdev, int ent_delay) r4tst = &ctrl->r4tst[0]; /* put RNG4 into program mode */ - clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM); + /* Setting both RTMCTL:PRGM and RTMCTL:TRNG_ACC causes TRNG to + * properly invalidate the entropy in the entropy register and + * force re-generation. + */ + clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM | RTMCTL_ACC); /* * Performance-wise, it does not make sense to @@ -379,8 +367,8 @@ static void kick_trng(struct platform_device *pdev, int ent_delay) wr_reg32(&r4tst->rtsdctl, val); /* min. freq. count, equal to 1/4 of the entropy sample length */ wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2); - /* disable maximum frequency count */ - wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE); + /* max. freq. count, equal to 16 times the entropy sample length */ + wr_reg32(&r4tst->rtfrqmax, ent_delay << 4); /* read the control register */ val = rd_reg32(&r4tst->rtmctl); start_rng: @@ -388,10 +376,11 @@ static void kick_trng(struct platform_device *pdev, int ent_delay) * select raw sampling in both entropy shifter * and statistical checker; ; put RNG4 into run mode */ - clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, RTMCTL_SAMP_MODE_RAW_ES_SC); + clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM | RTMCTL_ACC, + RTMCTL_SAMP_MODE_RAW_ES_SC); } -static int caam_get_era_from_hw(struct caam_ctrl __iomem *ctrl) +static int caam_get_era_from_hw(struct caam_perfmon __iomem *perfmon) { static const struct { u16 ip_id; @@ -417,12 +406,12 @@ static int caam_get_era_from_hw(struct caam_ctrl __iomem *ctrl) u16 ip_id; int i; - ccbvid = rd_reg32(&ctrl->perfmon.ccb_id); + ccbvid = rd_reg32(&perfmon->ccb_id); era = (ccbvid & CCBVID_ERA_MASK) >> CCBVID_ERA_SHIFT; if (era) /* This is '0' prior to CAAM ERA-6 */ return era; - id_ms = rd_reg32(&ctrl->perfmon.caam_id_ms); + id_ms = rd_reg32(&perfmon->caam_id_ms); ip_id = (id_ms & SECVID_MS_IPID_MASK) >> SECVID_MS_IPID_SHIFT; maj_rev = (id_ms & SECVID_MS_MAJ_REV_MASK) >> SECVID_MS_MAJ_REV_SHIFT; @@ -440,7 +429,7 @@ static int caam_get_era_from_hw(struct caam_ctrl __iomem *ctrl) * In case this property is not passed an attempt to retrieve the CAAM * era via register reads will be made. **/ -static int caam_get_era(struct caam_ctrl __iomem *ctrl) +static int caam_get_era(struct caam_perfmon __iomem *perfmon) { struct device_node *caam_node; int ret; @@ -453,7 +442,7 @@ static int caam_get_era(struct caam_ctrl __iomem *ctrl) if (!ret) return prop; else - return caam_get_era_from_hw(ctrl); + return caam_get_era_from_hw(perfmon); } /* @@ -527,7 +516,7 @@ static const struct soc_device_attribute caam_imx_soc_table[] = { { .soc_id = "i.MX6UL", .data = &caam_imx6ul_data }, { .soc_id = "i.MX6*", .data = &caam_imx6_data }, { .soc_id = "i.MX7*", .data = &caam_imx7_data }, - { .soc_id = "i.MX8MQ", .data = &caam_imx7_data }, + { .soc_id = "i.MX8M*", .data = &caam_imx7_data }, { .family = "Freescale i.MX" }, { /* sentinel */ } }; @@ -568,23 +557,246 @@ static int init_clocks(struct device *dev, const struct caam_imx_data *data) return devm_add_action_or_reset(dev, disable_clocks, ctrlpriv); } +#ifdef CONFIG_DEBUG_FS +static void caam_remove_debugfs(void *root) +{ + debugfs_remove_recursive(root); +} +#endif + +static void caam_dma_dev_unregister(void *data) +{ + platform_device_unregister(data); +} + +static int caam_ctrl_rng_init(struct device *dev) +{ + struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev); + struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl; + int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN; + u8 rng_vid; + + if (ctrlpriv->era < 10) { + struct caam_perfmon __iomem *perfmon; + + perfmon = ctrlpriv->total_jobrs ? + (struct caam_perfmon *)&ctrlpriv->jr[0]->perfmon : + (struct caam_perfmon *)&ctrl->perfmon; + + rng_vid = (rd_reg32(&perfmon->cha_id_ls) & + CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT; + } else { + struct version_regs __iomem *vreg; + + vreg = ctrlpriv->total_jobrs ? + (struct version_regs *)&ctrlpriv->jr[0]->vreg : + (struct version_regs *)&ctrl->vreg; + + rng_vid = (rd_reg32(&vreg->rng) & CHA_VER_VID_MASK) >> + CHA_VER_VID_SHIFT; + } + + /* + * If SEC has RNG version >= 4 and RNG state handle has not been + * already instantiated, do RNG instantiation + * In case of SoCs with Management Complex, RNG is managed by MC f/w. + */ + if (!ctrlpriv->mc_en && rng_vid >= 4) { + ctrlpriv->rng4_sh_init = + rd_reg32(&ctrl->r4tst[0].rdsta); + /* + * If the secure keys (TDKEK, JDKEK, TDSK), were already + * generated, signal this to the function that is instantiating + * the state handles. An error would occur if RNG4 attempts + * to regenerate these keys before the next POR. + */ + gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1; + ctrlpriv->rng4_sh_init &= RDSTA_IFMASK; + do { + int inst_handles = + rd_reg32(&ctrl->r4tst[0].rdsta) & + RDSTA_IFMASK; + /* + * If either SH were instantiated by somebody else + * (e.g. u-boot) then it is assumed that the entropy + * parameters are properly set and thus the function + * setting these (kick_trng(...)) is skipped. + * Also, if a handle was instantiated, do not change + * the TRNG parameters. + */ + if (!(ctrlpriv->rng4_sh_init || inst_handles)) { + dev_info(dev, + "Entropy delay = %u\n", + ent_delay); + kick_trng(dev, ent_delay); + ent_delay += 400; + } + /* + * if instantiate_rng(...) fails, the loop will rerun + * and the kick_trng(...) function will modify the + * upper and lower limits of the entropy sampling + * interval, leading to a sucessful initialization of + * the RNG. + */ + ret = instantiate_rng(dev, inst_handles, + gen_sk); + if (ret == -EAGAIN) + /* + * if here, the loop will rerun, + * so don't hog the CPU + */ + cpu_relax(); + } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); + if (ret) { + dev_err(dev, "failed to instantiate RNG"); + return ret; + } + /* + * Set handles init'ed by this module as the complement of the + * already initialized ones + */ + ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK; + + /* Enable RDB bit so that RNG works faster */ + clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE); + } + + return 0; +} + +#ifdef CONFIG_PM_SLEEP + +/* Indicate if the internal state of the CAAM is lost during PM */ +static int caam_off_during_pm(void) +{ + bool not_off_during_pm = of_machine_is_compatible("fsl,imx6q") || + of_machine_is_compatible("fsl,imx6qp") || + of_machine_is_compatible("fsl,imx6dl"); + + return not_off_during_pm ? 0 : 1; +} + +static void caam_state_save(struct device *dev) +{ + struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev); + struct caam_ctl_state *state = &ctrlpriv->state; + struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl; + u32 deco_inst, jr_inst; + int i; + + state->mcr = rd_reg32(&ctrl->mcr); + state->scfgr = rd_reg32(&ctrl->scfgr); + + deco_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) & + CHA_ID_MS_DECO_MASK) >> CHA_ID_MS_DECO_SHIFT; + for (i = 0; i < deco_inst; i++) { + state->deco_mid[i].liodn_ms = + rd_reg32(&ctrl->deco_mid[i].liodn_ms); + state->deco_mid[i].liodn_ls = + rd_reg32(&ctrl->deco_mid[i].liodn_ls); + } + + jr_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) & + CHA_ID_MS_JR_MASK) >> CHA_ID_MS_JR_SHIFT; + for (i = 0; i < jr_inst; i++) { + state->jr_mid[i].liodn_ms = + rd_reg32(&ctrl->jr_mid[i].liodn_ms); + state->jr_mid[i].liodn_ls = + rd_reg32(&ctrl->jr_mid[i].liodn_ls); + } +} + +static void caam_state_restore(const struct device *dev) +{ + const struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev); + const struct caam_ctl_state *state = &ctrlpriv->state; + struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl; + u32 deco_inst, jr_inst; + int i; + + wr_reg32(&ctrl->mcr, state->mcr); + wr_reg32(&ctrl->scfgr, state->scfgr); + + deco_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) & + CHA_ID_MS_DECO_MASK) >> CHA_ID_MS_DECO_SHIFT; + for (i = 0; i < deco_inst; i++) { + wr_reg32(&ctrl->deco_mid[i].liodn_ms, + state->deco_mid[i].liodn_ms); + wr_reg32(&ctrl->deco_mid[i].liodn_ls, + state->deco_mid[i].liodn_ls); + } + + jr_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) & + CHA_ID_MS_JR_MASK) >> CHA_ID_MS_JR_SHIFT; + for (i = 0; i < ctrlpriv->total_jobrs; i++) { + wr_reg32(&ctrl->jr_mid[i].liodn_ms, + state->jr_mid[i].liodn_ms); + wr_reg32(&ctrl->jr_mid[i].liodn_ls, + state->jr_mid[i].liodn_ls); + } + + if (ctrlpriv->virt_en == 1) + clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START | + JRSTART_JR1_START | JRSTART_JR2_START | + JRSTART_JR3_START); +} + +static int caam_ctrl_suspend(struct device *dev) +{ + const struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev); + + if (ctrlpriv->caam_off_during_pm && !ctrlpriv->scu_en && + !ctrlpriv->optee_en) + caam_state_save(dev); + + return 0; +} + +static int caam_ctrl_resume(struct device *dev) +{ + struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev); + int ret = 0; + + if (ctrlpriv->caam_off_during_pm && !ctrlpriv->scu_en && + !ctrlpriv->optee_en) { + caam_state_restore(dev); + + /* HW and rng will be reset so deinstantiation can be removed */ + devm_remove_action(dev, devm_deinstantiate_rng, dev); + ret = caam_ctrl_rng_init(dev); + } + + return ret; +} + +SIMPLE_DEV_PM_OPS(caam_ctrl_pm_ops, caam_ctrl_suspend, caam_ctrl_resume); + +#endif /* CONFIG_PM_SLEEP */ + /* Probe routine for CAAM top (controller) level */ static int caam_probe(struct platform_device *pdev) { - int ret, ring, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN; + int ret, ring; u64 caam_id; const struct soc_device_attribute *imx_soc_match; + static struct platform_device_info caam_dma_pdev_info = { + .name = "caam-dma", + .id = PLATFORM_DEVID_NONE + }; + static struct platform_device *caam_dma_dev; struct device *dev; struct device_node *nprop, *np; + struct resource res_regs; struct caam_ctrl __iomem *ctrl; struct caam_drv_private *ctrlpriv; + struct caam_perfmon __iomem *perfmon; #ifdef CONFIG_DEBUG_FS - struct caam_perfmon *perfmon; + struct dentry *dfs_root; #endif u32 scfgr, comp_params; - u8 rng_vid; int pg_size; int BLOCK_OFFSET = 0; + bool reg_access = true; ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL); if (!ctrlpriv) @@ -597,7 +809,35 @@ static int caam_probe(struct platform_device *pdev) imx_soc_match = soc_device_match(caam_imx_soc_table); caam_imx = (bool)imx_soc_match; +#ifdef CONFIG_PM_SLEEP + ctrlpriv->caam_off_during_pm = caam_imx && caam_off_during_pm(); +#endif + if (imx_soc_match) { + np = of_find_compatible_node(NULL, NULL, "fsl,imx-scu"); + ctrlpriv->scu_en = !!np; + of_node_put(np); + + reg_access = !ctrlpriv->scu_en; + + /* + * CAAM clocks cannot be controlled from kernel. + * They are automatically turned on by SCU f/w. + */ + if (ctrlpriv->scu_en) + goto iomap_ctrl; + + /* + * Until Layerscape and i.MX OP-TEE get in sync, + * only i.MX OP-TEE use cases disallow access to + * caam page 0 (controller) registers. + */ + np = of_find_compatible_node(NULL, NULL, "linaro,optee-tz"); + ctrlpriv->optee_en = !!np; + of_node_put(np); + + reg_access = reg_access && !ctrlpriv->optee_en; + if (!imx_soc_match->data) { dev_err(dev, "No clock data provided for i.MX SoC"); return -EINVAL; @@ -608,19 +848,48 @@ static int caam_probe(struct platform_device *pdev) return ret; } - +iomap_ctrl: /* Get configuration properties from device tree */ /* First, get register page */ - ctrl = of_iomap(nprop, 0); - if (!ctrl) { + ctrl = devm_of_iomap(dev, nprop, 0, NULL); + ret = PTR_ERR_OR_ZERO(ctrl); + if (ret) { dev_err(dev, "caam: of_iomap() failed\n"); - return -ENOMEM; + return ret; } - caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) & + ring = 0; + for_each_available_child_of_node(nprop, np) + if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || + of_device_is_compatible(np, "fsl,sec4.0-job-ring")) { + u32 reg; + + if (of_property_read_u32_index(np, "reg", 0, ®)) { + dev_err(dev, "%s read reg property error\n", + np->full_name); + continue; + } + + ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *) + ((__force uint8_t *)ctrl + reg); + + ctrlpriv->total_jobrs++; + ring++; + } + + /* + * Wherever possible, instead of accessing registers from the global page, + * use the alias registers in the first (cf. DT nodes order) + * job ring's page. + */ + perfmon = ring ? (struct caam_perfmon *)&ctrlpriv->jr[0]->perfmon : + (struct caam_perfmon *)&ctrl->perfmon; + + caam_little_end = !(bool)(rd_reg32(&perfmon->status) & (CSTA_PLEND | CSTA_ALT_PLEND)); - comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms); - if (comp_params & CTPR_MS_PS && rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR) + comp_params = rd_reg32(&perfmon->comp_parms_ms); + if (reg_access && comp_params & CTPR_MS_PS && + rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR) caam_ptr_sz = sizeof(u64); else caam_ptr_sz = sizeof(u32); @@ -632,22 +901,18 @@ static int caam_probe(struct platform_device *pdev) if (ctrlpriv->qi_present && !caam_dpaa2) { ret = qman_is_probed(); if (!ret) { - ret = -EPROBE_DEFER; - goto iounmap_ctrl; + return -EPROBE_DEFER; } else if (ret < 0) { dev_err(dev, "failing probe due to qman probe error\n"); - ret = -ENODEV; - goto iounmap_ctrl; + return -ENODEV; } ret = qman_portals_probed(); if (!ret) { - ret = -EPROBE_DEFER; - goto iounmap_ctrl; + return -EPROBE_DEFER; } else if (ret < 0) { dev_err(dev, "failing probe due to qman portals probe error\n"); - ret = -ENODEV; - goto iounmap_ctrl; + return -ENODEV; } } #endif @@ -671,9 +936,48 @@ static int caam_probe(struct platform_device *pdev) BLOCK_OFFSET * DECO_BLOCK_NUMBER ); - /* Get the IRQ of the controller (for security violations only) */ - ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0); + /* Only i.MX SoCs have sm */ + if (!imx_soc_match) + goto mc_fw; + + /* Get CAAM-SM node and of_iomap() and save */ + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-sm"); + if (!np) + return -ENODEV; + + /* Get CAAM SM registers base address from device tree */ + ret = of_address_to_resource(np, 0, &res_regs); + if (ret) { + dev_err(dev, "failed to retrieve registers base from device tree\n"); + of_node_put(np); + return -ENODEV; + } + + ctrlpriv->sm_phy = res_regs.start; + ctrlpriv->sm_base = devm_ioremap_resource(dev, &res_regs); + if (IS_ERR(ctrlpriv->sm_base)) { + of_node_put(np); + return PTR_ERR(ctrlpriv->sm_base); + } + if (!of_machine_is_compatible("fsl,imx8mp") && + !of_machine_is_compatible("fsl,imx8mn") && + !of_machine_is_compatible("fsl,imx8mm") && + !of_machine_is_compatible("fsl,imx8mq") && + !of_machine_is_compatible("fsl,imx8qm") && + !of_machine_is_compatible("fsl,imx8qxp") && + !of_machine_is_compatible("fsl,imx8dxl")) + ctrlpriv->sm_size = resource_size(&res_regs); + else + ctrlpriv->sm_size = PG_SIZE_64K; + + ctrlpriv->sm_present = 1; + of_node_put(np); + + if (!reg_access) + goto set_dma_mask; + +mc_fw: /* * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, * long pointers in master configuration register. @@ -717,13 +1021,14 @@ static int caam_probe(struct platform_device *pdev) JRSTART_JR1_START | JRSTART_JR2_START | JRSTART_JR3_START); +set_dma_mask: ret = dma_set_mask_and_coherent(dev, caam_get_dma_mask(dev)); if (ret) { dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret); - goto iounmap_ctrl; + return ret; } - ctrlpriv->era = caam_get_era(ctrl); + ctrlpriv->era = caam_get_era(perfmon); ctrlpriv->domain = iommu_get_domain_for_dev(dev); #ifdef CONFIG_DEBUG_FS @@ -732,10 +1037,12 @@ static int caam_probe(struct platform_device *pdev) * "caam" and nprop->full_name. The OF name isn't distinctive, * but does separate instances */ - perfmon = (struct caam_perfmon __force *)&ctrl->perfmon; + dfs_root = debugfs_create_dir(dev_name(dev), NULL); + ret = devm_add_action_or_reset(dev, caam_remove_debugfs, dfs_root); + if (ret) + return ret; - ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL); - ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root); + ctrlpriv->ctl = debugfs_create_dir("ctl", dfs_root); #endif /* Check to see if (DPAA 1.x) QI present. If so, enable */ @@ -755,108 +1062,34 @@ static int caam_probe(struct platform_device *pdev) #endif } - ret = of_platform_populate(nprop, caam_match, NULL, dev); - if (ret) { - dev_err(dev, "JR platform devices creation error\n"); - goto shutdown_qi; - } - - ring = 0; - for_each_available_child_of_node(nprop, np) - if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || - of_device_is_compatible(np, "fsl,sec4.0-job-ring")) { - ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *) - ((__force uint8_t *)ctrl + - (ring + JR_BLOCK_NUMBER) * - BLOCK_OFFSET - ); - ctrlpriv->total_jobrs++; - ring++; - } - /* If no QI and no rings specified, quit and go home */ if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) { dev_err(dev, "no queues configured, terminating\n"); - ret = -ENOMEM; - goto caam_remove; + return -ENOMEM; } - if (ctrlpriv->era < 10) - rng_vid = (rd_reg32(&ctrl->perfmon.cha_id_ls) & - CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT; - else - rng_vid = (rd_reg32(&ctrl->vreg.rng) & CHA_VER_VID_MASK) >> - CHA_VER_VID_SHIFT; - - /* - * If SEC has RNG version >= 4 and RNG state handle has not been - * already instantiated, do RNG instantiation - * In case of SoCs with Management Complex, RNG is managed by MC f/w. - */ - if (!ctrlpriv->mc_en && rng_vid >= 4) { - ctrlpriv->rng4_sh_init = - rd_reg32(&ctrl->r4tst[0].rdsta); - /* - * If the secure keys (TDKEK, JDKEK, TDSK), were already - * generated, signal this to the function that is instantiating - * the state handles. An error would occur if RNG4 attempts - * to regenerate these keys before the next POR. - */ - gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1; - ctrlpriv->rng4_sh_init &= RDSTA_IFMASK; - do { - int inst_handles = - rd_reg32(&ctrl->r4tst[0].rdsta) & - RDSTA_IFMASK; - /* - * If either SH were instantiated by somebody else - * (e.g. u-boot) then it is assumed that the entropy - * parameters are properly set and thus the function - * setting these (kick_trng(...)) is skipped. - * Also, if a handle was instantiated, do not change - * the TRNG parameters. - */ - if (!(ctrlpriv->rng4_sh_init || inst_handles)) { - dev_info(dev, - "Entropy delay = %u\n", - ent_delay); - kick_trng(pdev, ent_delay); - ent_delay += 400; - } - /* - * if instantiate_rng(...) fails, the loop will rerun - * and the kick_trng(...) function will modfiy the - * upper and lower limits of the entropy sampling - * interval, leading to a sucessful initialization of - * the RNG. - */ - ret = instantiate_rng(dev, inst_handles, - gen_sk); - if (ret == -EAGAIN) - /* - * if here, the loop will rerun, - * so don't hog the CPU - */ - cpu_relax(); - } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); - if (ret) { - dev_err(dev, "failed to instantiate RNG"); - goto caam_remove; - } - /* - * Set handles init'ed by this module as the complement of the - * already initialized ones - */ - ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK; - - /* Enable RDB bit so that RNG works faster */ - clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE); + caam_dma_pdev_info.parent = dev; + caam_dma_pdev_info.dma_mask = dma_get_mask(dev); + caam_dma_dev = platform_device_register_full(&caam_dma_pdev_info); + if (IS_ERR(caam_dma_dev)) { + dev_err(dev, "Unable to create and register caam-dma dev\n"); + return PTR_ERR(caam_dma_dev); + } else { + set_dma_ops(&caam_dma_dev->dev, get_dma_ops(dev)); + ret = devm_add_action_or_reset(dev, caam_dma_dev_unregister, + caam_dma_dev); + if (ret) + return ret; } - /* NOTE: RTIC detection ought to go here, around Si time */ + if (reg_access) { + ret = caam_ctrl_rng_init(dev); + if (ret) + return ret; + } - caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 | - (u64)rd_reg32(&ctrl->perfmon.caam_id_ls); + caam_id = (u64)rd_reg32(&perfmon->caam_id_ms) << 32 | + (u64)rd_reg32(&perfmon->caam_id_ls); /* Report "alive" for developer to see */ dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id, @@ -898,6 +1131,9 @@ static int caam_probe(struct platform_device *pdev) ctrlpriv->ctl, &perfmon->status, &caam_fops_u32_ro); + if (!reg_access) + goto probe_jrs; + /* Internal covering keys (useful in non-secure mode only) */ ctrlpriv->ctl_kek_wrap.data = (__force void *)&ctrlpriv->ctrl->kek[0]; ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32); @@ -914,19 +1150,12 @@ static int caam_probe(struct platform_device *pdev) debugfs_create_blob("tdsk", S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl, &ctrlpriv->ctl_tdsk_wrap); #endif - return 0; -caam_remove: - caam_remove(pdev); - return ret; +probe_jrs: + ret = devm_of_platform_populate(dev); + if (ret) + dev_err(dev, "JR platform devices creation error\n"); -shutdown_qi: -#ifdef CONFIG_CAAM_QI - if (ctrlpriv->qi_init) - caam_qi_shutdown(dev); -#endif -iounmap_ctrl: - iounmap(ctrl); return ret; } @@ -934,9 +1163,11 @@ static struct platform_driver caam_driver = { .driver = { .name = "caam", .of_match_table = caam_match, +#ifdef CONFIG_PM_SLEEP + .pm = &caam_ctrl_pm_ops, +#endif }, .probe = caam_probe, - .remove = caam_remove, }; module_platform_driver(caam_driver); diff --git a/drivers/crypto/caam/desc.h b/drivers/crypto/caam/desc.h index 4b6854bf896a74..30724be7a6a081 100644 --- a/drivers/crypto/caam/desc.h +++ b/drivers/crypto/caam/desc.h @@ -43,6 +43,7 @@ #define CMD_SEQ_LOAD (0x03 << CMD_SHIFT) #define CMD_FIFO_LOAD (0x04 << CMD_SHIFT) #define CMD_SEQ_FIFO_LOAD (0x05 << CMD_SHIFT) +#define CMD_MOVEB (0x07 << CMD_SHIFT) #define CMD_STORE (0x0a << CMD_SHIFT) #define CMD_SEQ_STORE (0x0b << CMD_SHIFT) #define CMD_FIFO_STORE (0x0c << CMD_SHIFT) @@ -363,6 +364,7 @@ #define FIFOLD_TYPE_PK_N (0x08 << FIFOLD_TYPE_SHIFT) #define FIFOLD_TYPE_PK_A (0x0c << FIFOLD_TYPE_SHIFT) #define FIFOLD_TYPE_PK_B (0x0d << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_IFIFO (0x0f << FIFOLD_TYPE_SHIFT) /* Other types. Need to OR in last/flush bits as desired */ #define FIFOLD_TYPE_MSG_MASK (0x38 << FIFOLD_TYPE_SHIFT) @@ -403,6 +405,10 @@ #define FIFOST_TYPE_PKHA_N (0x08 << FIFOST_TYPE_SHIFT) #define FIFOST_TYPE_PKHA_A (0x0c << FIFOST_TYPE_SHIFT) #define FIFOST_TYPE_PKHA_B (0x0d << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_AF_SBOX_CCM_JKEK (0x10 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_AF_SBOX_CCM_TKEK (0x11 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_KEY_CCM_JKEK (0x14 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_KEY_CCM_TKEK (0x15 << FIFOST_TYPE_SHIFT) #define FIFOST_TYPE_AF_SBOX_JKEK (0x20 << FIFOST_TYPE_SHIFT) #define FIFOST_TYPE_AF_SBOX_TKEK (0x21 << FIFOST_TYPE_SHIFT) #define FIFOST_TYPE_PKHA_E_JKEK (0x22 << FIFOST_TYPE_SHIFT) @@ -1136,6 +1142,23 @@ #define OP_PCL_PKPROT_ECC 0x0002 #define OP_PCL_PKPROT_F2M 0x0001 +/* Blob protocol protinfo bits */ +#define OP_PCL_BLOB_TK 0x0200 +#define OP_PCL_BLOB_EKT 0x0100 + +#define OP_PCL_BLOB_K2KR_MEM 0x0000 +#define OP_PCL_BLOB_K2KR_C1KR 0x0010 +#define OP_PCL_BLOB_K2KR_C2KR 0x0030 +#define OP_PCL_BLOB_K2KR_AFHAS 0x0050 +#define OP_PCL_BLOB_K2KR_C2KR_SPLIT 0x0070 + +#define OP_PCL_BLOB_PTXT_SECMEM 0x0008 +#define OP_PCL_BLOB_BLACK 0x0004 + +#define OP_PCL_BLOB_FMT_NORMAL 0x0000 +#define OP_PCL_BLOB_FMT_MSTR 0x0002 +#define OP_PCL_BLOB_FMT_TEST 0x0003 + /* For non-protocol/alg-only op commands */ #define OP_ALG_TYPE_SHIFT 24 #define OP_ALG_TYPE_MASK (0x7 << OP_ALG_TYPE_SHIFT) @@ -1500,6 +1523,7 @@ #define MATH_SRC1_INFIFO (0x0a << MATH_SRC1_SHIFT) #define MATH_SRC1_OUTFIFO (0x0b << MATH_SRC1_SHIFT) #define MATH_SRC1_ONE (0x0c << MATH_SRC1_SHIFT) +#define MATH_SRC1_ZERO (0x0f << MATH_SRC1_SHIFT) /* Destination selectors */ #define MATH_DEST_SHIFT 8 @@ -1682,4 +1706,31 @@ /* Frame Descriptor Command for Replacement Job Descriptor */ #define FD_CMD_REPLACE_JOB_DESC 0x20000000 +/* CHA Control Register bits */ +#define CCTRL_RESET_CHA_ALL 0x1 +#define CCTRL_RESET_CHA_AESA 0x2 +#define CCTRL_RESET_CHA_DESA 0x4 +#define CCTRL_RESET_CHA_AFHA 0x8 +#define CCTRL_RESET_CHA_KFHA 0x10 +#define CCTRL_RESET_CHA_SF8A 0x20 +#define CCTRL_RESET_CHA_PKHA 0x40 +#define CCTRL_RESET_CHA_MDHA 0x80 +#define CCTRL_RESET_CHA_CRCA 0x100 +#define CCTRL_RESET_CHA_RNG 0x200 +#define CCTRL_RESET_CHA_SF9A 0x400 +#define CCTRL_RESET_CHA_ZUCE 0x800 +#define CCTRL_RESET_CHA_ZUCA 0x1000 +#define CCTRL_UNLOAD_PK_A0 0x10000 +#define CCTRL_UNLOAD_PK_A1 0x20000 +#define CCTRL_UNLOAD_PK_A2 0x40000 +#define CCTRL_UNLOAD_PK_A3 0x80000 +#define CCTRL_UNLOAD_PK_B0 0x100000 +#define CCTRL_UNLOAD_PK_B1 0x200000 +#define CCTRL_UNLOAD_PK_B2 0x400000 +#define CCTRL_UNLOAD_PK_B3 0x800000 +#define CCTRL_UNLOAD_PK_N 0x1000000 +#define CCTRL_UNLOAD_PK_A 0x4000000 +#define CCTRL_UNLOAD_PK_B 0x8000000 +#define CCTRL_UNLOAD_SBOX 0x10000000 + #endif /* DESC_H */ diff --git a/drivers/crypto/caam/desc_constr.h b/drivers/crypto/caam/desc_constr.h index 62ce6421bb3fe7..f98dec8f25924d 100644 --- a/drivers/crypto/caam/desc_constr.h +++ b/drivers/crypto/caam/desc_constr.h @@ -240,6 +240,7 @@ static inline u32 *append_##cmd(u32 * const desc, u32 options) \ APPEND_CMD_RET(jump, JUMP) APPEND_CMD_RET(move, MOVE) APPEND_CMD_RET(move_len, MOVE_LEN) +APPEND_CMD_RET(moveb, MOVEB) static inline void set_jump_tgt_here(u32 * const desc, u32 *jump_cmd) { @@ -500,6 +501,8 @@ do { \ * @key_virt: virtual address where algorithm key resides * @key_inline: true - key can be inlined in the descriptor; false - key is * referenced by the descriptor + * @key_real_len: size of the key to be loaded by the CAAM + * @key_cmd_opt: optional parameters for KEY command */ struct alginfo { u32 algtype; @@ -508,6 +511,8 @@ struct alginfo { dma_addr_t key_dma; const void *key_virt; bool key_inline; + u32 key_real_len; + u32 key_cmd_opt; }; /** diff --git a/drivers/crypto/caam/dpseci.c b/drivers/crypto/caam/dpseci.c index 8a68531ded0b2c..65a131be92b433 100644 --- a/drivers/crypto/caam/dpseci.c +++ b/drivers/crypto/caam/dpseci.c @@ -5,6 +5,7 @@ */ #include +#include #include "dpseci.h" #include "dpseci_cmd.h" @@ -16,8 +17,8 @@ * @token: Returned token; use in subsequent API calls * * This function can be used to open a control session for an already created - * object; an object may have been declared statically in the DPL - * or created dynamically. + * object; an object may have been declared in the DPL or by calling the + * dpseci_create() function. * This function returns a unique authentication token, associated with the * specific object ID and the specific MC portal; this token must be used in all * subsequent commands for this specific object. @@ -66,6 +67,85 @@ int dpseci_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) return mc_send_command(mc_io, &cmd); } +/** + * dpseci_create() - Create the DPSECI object + * @mc_io: Pointer to MC portal's I/O object + * @dprc_token: Parent container token; '0' for default container + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @cfg: Configuration structure + * @obj_id: returned object id + * + * Create the DPSECI object, allocate required resources and perform required + * initialization. + * + * The object can be created either by declaring it in the DPL file, or by + * calling this function. + * + * The function accepts an authentication token of a parent container that this + * object should be assigned to. The token can be '0' so the object will be + * assigned to the default container. + * The newly created object can be opened with the returned object id and using + * the container's associated tokens and MC portals. + * + * Return: '0' on success, error code otherwise + */ +int dpseci_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + const struct dpseci_cfg *cfg, u32 *obj_id) +{ + struct fsl_mc_command cmd = { 0 }; + struct dpseci_cmd_create *cmd_params; + int i, err; + + cmd.header = mc_encode_cmd_header(DPSECI_CMDID_CREATE, + cmd_flags, + dprc_token); + cmd_params = (struct dpseci_cmd_create *)cmd.params; + for (i = 0; i < 8; i++) + cmd_params->priorities[i] = cfg->priorities[i]; + for (i = 0; i < 8; i++) + cmd_params->priorities2[i] = cfg->priorities[8 + i]; + cmd_params->num_tx_queues = cfg->num_tx_queues; + cmd_params->num_rx_queues = cfg->num_rx_queues; + cmd_params->options = cpu_to_le32(cfg->options); + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + *obj_id = mc_cmd_read_object_id(&cmd); + + return 0; +} + +/** + * dpseci_destroy() - Destroy the DPSECI object and release all its resources + * @mc_io: Pointer to MC portal's I/O object + * @dprc_token: Parent container token; '0' for default container + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @object_id: The object id; it must be a valid id within the container that + * created this object + * + * The function accepts the authentication token of the parent container that + * created the object (not the one that currently owns the object). The object + * is searched within parent using the provided 'object_id'. + * All tokens to the object must be closed before calling destroy. + * + * Return: '0' on success, error code otherwise + */ +int dpseci_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + u32 object_id) +{ + struct fsl_mc_command cmd = { 0 }; + struct dpseci_cmd_destroy *cmd_params; + + cmd.header = mc_encode_cmd_header(DPSECI_CMDID_DESTROY, + cmd_flags, + dprc_token); + cmd_params = (struct dpseci_cmd_destroy *)cmd.params; + cmd_params->object_id = cpu_to_le32(object_id); + + return mc_send_command(mc_io, &cmd); +} + /** * dpseci_enable() - Enable the DPSECI, allow sending and receiving frames * @mc_io: Pointer to MC portal's I/O object @@ -132,6 +212,217 @@ int dpseci_is_enabled(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, return 0; } +/** + * dpseci_reset() - Reset the DPSECI, returns the object to initial state. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSECI object + * + * Return: '0' on success, error code otherwise + */ +int dpseci_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) +{ + struct fsl_mc_command cmd = { 0 }; + + cmd.header = mc_encode_cmd_header(DPSECI_CMDID_RESET, + cmd_flags, + token); + + return mc_send_command(mc_io, &cmd); +} + +/** + * dpseci_get_irq_enable() - Get overall interrupt state + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSECI object + * @irq_index: The interrupt index to configure + * @en: Returned Interrupt state - enable = 1, disable = 0 + * + * Return: '0' on success, error code otherwise + */ +int dpseci_get_irq_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 irq_index, u8 *en) +{ + struct fsl_mc_command cmd = { 0 }; + struct dpseci_cmd_irq_enable *cmd_params; + struct dpseci_rsp_get_irq_enable *rsp_params; + int err; + + cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_IRQ_ENABLE, + cmd_flags, + token); + cmd_params = (struct dpseci_cmd_irq_enable *)cmd.params; + cmd_params->irq_index = irq_index; + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + rsp_params = (struct dpseci_rsp_get_irq_enable *)cmd.params; + *en = rsp_params->enable_state; + + return 0; +} + +/** + * dpseci_set_irq_enable() - Set overall interrupt state. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSECI object + * @irq_index: The interrupt index to configure + * @en: Interrupt state - enable = 1, disable = 0 + * + * Allows GPP software to control when interrupts are generated. + * Each interrupt can have up to 32 causes. The enable/disable control's the + * overall interrupt state. If the interrupt is disabled no causes will cause + * an interrupt. + * + * Return: '0' on success, error code otherwise + */ +int dpseci_set_irq_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 irq_index, u8 en) +{ + struct fsl_mc_command cmd = { 0 }; + struct dpseci_cmd_irq_enable *cmd_params; + + cmd.header = mc_encode_cmd_header(DPSECI_CMDID_SET_IRQ_ENABLE, + cmd_flags, + token); + cmd_params = (struct dpseci_cmd_irq_enable *)cmd.params; + cmd_params->irq_index = irq_index; + cmd_params->enable_state = en; + + return mc_send_command(mc_io, &cmd); +} + +/** + * dpseci_get_irq_mask() - Get interrupt mask. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSECI object + * @irq_index: The interrupt index to configure + * @mask: Returned event mask to trigger interrupt + * + * Every interrupt can have up to 32 causes and the interrupt model supports + * masking/unmasking each cause independently. + * + * Return: '0' on success, error code otherwise + */ +int dpseci_get_irq_mask(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 irq_index, u32 *mask) +{ + struct fsl_mc_command cmd = { 0 }; + struct dpseci_cmd_irq_mask *cmd_params; + int err; + + cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_IRQ_MASK, + cmd_flags, + token); + cmd_params = (struct dpseci_cmd_irq_mask *)cmd.params; + cmd_params->irq_index = irq_index; + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + *mask = le32_to_cpu(cmd_params->mask); + + return 0; +} + +/** + * dpseci_set_irq_mask() - Set interrupt mask. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSECI object + * @irq_index: The interrupt index to configure + * @mask: event mask to trigger interrupt; + * each bit: + * 0 = ignore event + * 1 = consider event for asserting IRQ + * + * Every interrupt can have up to 32 causes and the interrupt model supports + * masking/unmasking each cause independently + * + * Return: '0' on success, error code otherwise + */ +int dpseci_set_irq_mask(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 irq_index, u32 mask) +{ + struct fsl_mc_command cmd = { 0 }; + struct dpseci_cmd_irq_mask *cmd_params; + + cmd.header = mc_encode_cmd_header(DPSECI_CMDID_SET_IRQ_MASK, + cmd_flags, + token); + cmd_params = (struct dpseci_cmd_irq_mask *)cmd.params; + cmd_params->mask = cpu_to_le32(mask); + cmd_params->irq_index = irq_index; + + return mc_send_command(mc_io, &cmd); +} + +/** + * dpseci_get_irq_status() - Get the current status of any pending interrupts + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSECI object + * @irq_index: The interrupt index to configure + * @status: Returned interrupts status - one bit per cause: + * 0 = no interrupt pending + * 1 = interrupt pending + * + * Return: '0' on success, error code otherwise + */ +int dpseci_get_irq_status(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 irq_index, u32 *status) +{ + struct fsl_mc_command cmd = { 0 }; + struct dpseci_cmd_irq_status *cmd_params; + int err; + + cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_IRQ_STATUS, + cmd_flags, + token); + cmd_params = (struct dpseci_cmd_irq_status *)cmd.params; + cmd_params->status = cpu_to_le32(*status); + cmd_params->irq_index = irq_index; + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + *status = le32_to_cpu(cmd_params->status); + + return 0; +} + +/** + * dpseci_clear_irq_status() - Clear a pending interrupt's status + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSECI object + * @irq_index: The interrupt index to configure + * @status: bits to clear (W1C) - one bit per cause: + * 0 = don't change + * 1 = clear status bit + * + * Return: '0' on success, error code otherwise + */ +int dpseci_clear_irq_status(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 irq_index, u32 status) +{ + struct fsl_mc_command cmd = { 0 }; + struct dpseci_cmd_irq_status *cmd_params; + + cmd.header = mc_encode_cmd_header(DPSECI_CMDID_CLEAR_IRQ_STATUS, + cmd_flags, + token); + cmd_params = (struct dpseci_cmd_irq_status *)cmd.params; + cmd_params->status = cpu_to_le32(status); + cmd_params->irq_index = irq_index; + + return mc_send_command(mc_io, &cmd); +} + /** * dpseci_get_attributes() - Retrieve DPSECI attributes * @mc_io: Pointer to MC portal's I/O object @@ -321,6 +612,42 @@ int dpseci_get_sec_attr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, return 0; } +/** + * dpseci_get_sec_counters() - Retrieve SEC accelerator counters + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSECI object + * @counters: Returned SEC counters + * + * Return: '0' on success, error code otherwise + */ +int dpseci_get_sec_counters(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + struct dpseci_sec_counters *counters) +{ + struct fsl_mc_command cmd = { 0 }; + struct dpseci_rsp_get_sec_counters *rsp_params; + int err; + + cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_SEC_COUNTERS, + cmd_flags, + token); + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + rsp_params = (struct dpseci_rsp_get_sec_counters *)cmd.params; + counters->dequeued_requests = + le64_to_cpu(rsp_params->dequeued_requests); + counters->ob_enc_requests = le64_to_cpu(rsp_params->ob_enc_requests); + counters->ib_dec_requests = le64_to_cpu(rsp_params->ib_dec_requests); + counters->ob_enc_bytes = le64_to_cpu(rsp_params->ob_enc_bytes); + counters->ob_prot_bytes = le64_to_cpu(rsp_params->ob_prot_bytes); + counters->ib_dec_bytes = le64_to_cpu(rsp_params->ib_dec_bytes); + counters->ib_valid_bytes = le64_to_cpu(rsp_params->ib_valid_bytes); + + return 0; +} + /** * dpseci_get_api_version() - Get Data Path SEC Interface API version * @mc_io: Pointer to MC portal's I/O object @@ -350,6 +677,90 @@ int dpseci_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, return 0; } +/** + * dpseci_set_opr() - Set Order Restoration configuration + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSECI object + * @index: The queue index + * @options: Configuration mode options; can be OPR_OPT_CREATE or + * OPR_OPT_RETIRE + * @cfg: Configuration options for the OPR + * + * Return: '0' on success, error code otherwise + */ +int dpseci_set_opr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u8 index, + u8 options, struct opr_cfg *cfg) +{ + struct fsl_mc_command cmd = { 0 }; + struct dpseci_cmd_opr *cmd_params; + + cmd.header = mc_encode_cmd_header( + DPSECI_CMDID_SET_OPR, + cmd_flags, + token); + cmd_params = (struct dpseci_cmd_opr *)cmd.params; + cmd_params->index = index; + cmd_params->options = options; + cmd_params->oloe = cfg->oloe; + cmd_params->oeane = cfg->oeane; + cmd_params->olws = cfg->olws; + cmd_params->oa = cfg->oa; + cmd_params->oprrws = cfg->oprrws; + + return mc_send_command(mc_io, &cmd); +} + +/** + * dpseci_get_opr() - Retrieve Order Restoration config and query + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSECI object + * @index: The queue index + * @cfg: Returned OPR configuration + * @qry: Returned OPR query + * + * Return: '0' on success, error code otherwise + */ +int dpseci_get_opr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u8 index, + struct opr_cfg *cfg, struct opr_qry *qry) +{ + struct fsl_mc_command cmd = { 0 }; + struct dpseci_cmd_opr *cmd_params; + struct dpseci_rsp_get_opr *rsp_params; + int err; + + cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_OPR, + cmd_flags, + token); + cmd_params = (struct dpseci_cmd_opr *)cmd.params; + cmd_params->index = index; + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + rsp_params = (struct dpseci_rsp_get_opr *)cmd.params; + qry->rip = dpseci_get_field(rsp_params->flags, OPR_RIP); + qry->enable = dpseci_get_field(rsp_params->flags, OPR_ENABLE); + cfg->oloe = rsp_params->oloe; + cfg->oeane = rsp_params->oeane; + cfg->olws = rsp_params->olws; + cfg->oa = rsp_params->oa; + cfg->oprrws = rsp_params->oprrws; + qry->nesn = le16_to_cpu(rsp_params->nesn); + qry->ndsn = le16_to_cpu(rsp_params->ndsn); + qry->ea_tseq = le16_to_cpu(rsp_params->ea_tseq); + qry->tseq_nlis = dpseci_get_field(rsp_params->tseq_nlis, OPR_TSEQ_NLIS); + qry->ea_hseq = le16_to_cpu(rsp_params->ea_hseq); + qry->hseq_nlis = dpseci_get_field(rsp_params->hseq_nlis, OPR_HSEQ_NLIS); + qry->ea_hptr = le16_to_cpu(rsp_params->ea_hptr); + qry->ea_tptr = le16_to_cpu(rsp_params->ea_tptr); + qry->opr_vid = le16_to_cpu(rsp_params->opr_vid); + qry->opr_id = le16_to_cpu(rsp_params->opr_id); + + return 0; +} + /** * dpseci_set_congestion_notification() - Set congestion group * notification configuration diff --git a/drivers/crypto/caam/dpseci.h b/drivers/crypto/caam/dpseci.h index 4550e134d16666..aa0fd40e807222 100644 --- a/drivers/crypto/caam/dpseci.h +++ b/drivers/crypto/caam/dpseci.h @@ -12,6 +12,8 @@ */ struct fsl_mc_io; +struct opr_cfg; +struct opr_qry; /** * General DPSECI macros @@ -37,10 +39,22 @@ int dpseci_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); */ #define DPSECI_OPT_HAS_CG 0x000020 +/** + * Enable the Order Restoration support + */ +#define DPSECI_OPT_HAS_OPR 0x000040 + +/** + * Order Point Records are shared for the entire DPSECI + */ +#define DPSECI_OPT_OPR_SHARED 0x000080 + /** * struct dpseci_cfg - Structure representing DPSECI configuration - * @options: Any combination of the following flags: + * @options: Any combination of the following options: * DPSECI_OPT_HAS_CG + * DPSECI_OPT_HAS_OPR + * DPSECI_OPT_OPR_SHARED * @num_tx_queues: num of queues towards the SEC * @num_rx_queues: num of queues back from the SEC * @priorities: Priorities for the SEC hardware processing; @@ -55,6 +69,12 @@ struct dpseci_cfg { u8 priorities[DPSECI_MAX_QUEUE_NUM]; }; +int dpseci_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + const struct dpseci_cfg *cfg, u32 *obj_id); + +int dpseci_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + u32 object_id); + int dpseci_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); int dpseci_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); @@ -62,13 +82,35 @@ int dpseci_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); int dpseci_is_enabled(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, int *en); +int dpseci_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); + +int dpseci_get_irq_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 irq_index, u8 *en); + +int dpseci_set_irq_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 irq_index, u8 en); + +int dpseci_get_irq_mask(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 irq_index, u32 *mask); + +int dpseci_set_irq_mask(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 irq_index, u32 mask); + +int dpseci_get_irq_status(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 irq_index, u32 *status); + +int dpseci_clear_irq_status(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 irq_index, u32 status); + /** * struct dpseci_attr - Structure representing DPSECI attributes * @id: DPSECI object ID * @num_tx_queues: number of queues towards the SEC * @num_rx_queues: number of queues back from the SEC - * @options: any combination of the following flags: + * @options: any combination of the following options: * DPSECI_OPT_HAS_CG + * DPSECI_OPT_HAS_OPR + * DPSECI_OPT_OPR_SHARED */ struct dpseci_attr { int id; @@ -248,9 +290,39 @@ struct dpseci_sec_attr { int dpseci_get_sec_attr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, struct dpseci_sec_attr *attr); +/** + * struct dpseci_sec_counters - Structure representing global SEC counters and + * not per dpseci counters + * @dequeued_requests: Number of Requests Dequeued + * @ob_enc_requests: Number of Outbound Encrypt Requests + * @ib_dec_requests: Number of Inbound Decrypt Requests + * @ob_enc_bytes: Number of Outbound Bytes Encrypted + * @ob_prot_bytes: Number of Outbound Bytes Protected + * @ib_dec_bytes: Number of Inbound Bytes Decrypted + * @ib_valid_bytes: Number of Inbound Bytes Validated + */ +struct dpseci_sec_counters { + u64 dequeued_requests; + u64 ob_enc_requests; + u64 ib_dec_requests; + u64 ob_enc_bytes; + u64 ob_prot_bytes; + u64 ib_dec_bytes; + u64 ib_valid_bytes; +}; + +int dpseci_get_sec_counters(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + struct dpseci_sec_counters *counters); + int dpseci_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 *major_ver, u16 *minor_ver); +int dpseci_set_opr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u8 index, + u8 options, struct opr_cfg *cfg); + +int dpseci_get_opr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u8 index, + struct opr_cfg *cfg, struct opr_qry *qry); + /** * enum dpseci_congestion_unit - DPSECI congestion units * @DPSECI_CONGESTION_UNIT_BYTES: bytes units diff --git a/drivers/crypto/caam/dpseci_cmd.h b/drivers/crypto/caam/dpseci_cmd.h index 6ab77ead6e3dfb..9fec1c92ea82bf 100644 --- a/drivers/crypto/caam/dpseci_cmd.h +++ b/drivers/crypto/caam/dpseci_cmd.h @@ -17,6 +17,7 @@ /* Command versioning */ #define DPSECI_CMD_BASE_VERSION 1 #define DPSECI_CMD_BASE_VERSION_V2 2 +#define DPSECI_CMD_BASE_VERSION_V3 3 #define DPSECI_CMD_ID_OFFSET 4 #define DPSECI_CMD_V1(id) (((id) << DPSECI_CMD_ID_OFFSET) | \ @@ -25,20 +26,36 @@ #define DPSECI_CMD_V2(id) (((id) << DPSECI_CMD_ID_OFFSET) | \ DPSECI_CMD_BASE_VERSION_V2) +#define DPSECI_CMD_V3(id) (((id) << DPSECI_CMD_ID_OFFSET) | \ + DPSECI_CMD_BASE_VERSION_V3) + /* Command IDs */ #define DPSECI_CMDID_CLOSE DPSECI_CMD_V1(0x800) #define DPSECI_CMDID_OPEN DPSECI_CMD_V1(0x809) +#define DPSECI_CMDID_CREATE DPSECI_CMD_V3(0x909) +#define DPSECI_CMDID_DESTROY DPSECI_CMD_V1(0x989) #define DPSECI_CMDID_GET_API_VERSION DPSECI_CMD_V1(0xa09) #define DPSECI_CMDID_ENABLE DPSECI_CMD_V1(0x002) #define DPSECI_CMDID_DISABLE DPSECI_CMD_V1(0x003) #define DPSECI_CMDID_GET_ATTR DPSECI_CMD_V1(0x004) +#define DPSECI_CMDID_RESET DPSECI_CMD_V1(0x005) #define DPSECI_CMDID_IS_ENABLED DPSECI_CMD_V1(0x006) +#define DPSECI_CMDID_SET_IRQ_ENABLE DPSECI_CMD_V1(0x012) +#define DPSECI_CMDID_GET_IRQ_ENABLE DPSECI_CMD_V1(0x013) +#define DPSECI_CMDID_SET_IRQ_MASK DPSECI_CMD_V1(0x014) +#define DPSECI_CMDID_GET_IRQ_MASK DPSECI_CMD_V1(0x015) +#define DPSECI_CMDID_GET_IRQ_STATUS DPSECI_CMD_V1(0x016) +#define DPSECI_CMDID_CLEAR_IRQ_STATUS DPSECI_CMD_V1(0x017) + #define DPSECI_CMDID_SET_RX_QUEUE DPSECI_CMD_V1(0x194) #define DPSECI_CMDID_GET_RX_QUEUE DPSECI_CMD_V1(0x196) #define DPSECI_CMDID_GET_TX_QUEUE DPSECI_CMD_V1(0x197) #define DPSECI_CMDID_GET_SEC_ATTR DPSECI_CMD_V2(0x198) +#define DPSECI_CMDID_GET_SEC_COUNTERS DPSECI_CMD_V1(0x199) +#define DPSECI_CMDID_SET_OPR DPSECI_CMD_V1(0x19A) +#define DPSECI_CMDID_GET_OPR DPSECI_CMD_V1(0x19B) #define DPSECI_CMDID_SET_CONGESTION_NOTIFICATION DPSECI_CMD_V1(0x170) #define DPSECI_CMDID_GET_CONGESTION_NOTIFICATION DPSECI_CMD_V1(0x171) @@ -57,6 +74,20 @@ struct dpseci_cmd_open { __le32 dpseci_id; }; +struct dpseci_cmd_create { + u8 priorities[8]; + u8 num_tx_queues; + u8 num_rx_queues; + u8 pad0[6]; + __le32 options; + __le32 pad1; + u8 priorities2[8]; +}; + +struct dpseci_cmd_destroy { + __le32 object_id; +}; + #define DPSECI_ENABLE_SHIFT 0 #define DPSECI_ENABLE_SIZE 1 @@ -64,6 +95,26 @@ struct dpseci_rsp_is_enabled { u8 is_enabled; }; +struct dpseci_cmd_irq_enable { + u8 enable_state; + u8 pad[3]; + u8 irq_index; +}; + +struct dpseci_rsp_get_irq_enable { + u8 enable_state; +}; + +struct dpseci_cmd_irq_mask { + __le32 mask; + u8 irq_index; +}; + +struct dpseci_cmd_irq_status { + __le32 status; + u8 irq_index; +}; + struct dpseci_rsp_get_attributes { __le32 id; __le32 pad0; @@ -125,11 +176,70 @@ struct dpseci_rsp_get_sec_attr { u8 ptha_acc_num; }; +struct dpseci_rsp_get_sec_counters { + __le64 dequeued_requests; + __le64 ob_enc_requests; + __le64 ib_dec_requests; + __le64 ob_enc_bytes; + __le64 ob_prot_bytes; + __le64 ib_dec_bytes; + __le64 ib_valid_bytes; +}; + struct dpseci_rsp_get_api_version { __le16 major; __le16 minor; }; +struct dpseci_cmd_opr { + __le16 pad; + u8 index; + u8 options; + u8 pad1[7]; + u8 oloe; + u8 oeane; + u8 olws; + u8 oa; + u8 oprrws; +}; + +#define DPSECI_OPR_RIP_SHIFT 0 +#define DPSECI_OPR_RIP_SIZE 1 +#define DPSECI_OPR_ENABLE_SHIFT 1 +#define DPSECI_OPR_ENABLE_SIZE 1 +#define DPSECI_OPR_TSEQ_NLIS_SHIFT 0 +#define DPSECI_OPR_TSEQ_NLIS_SIZE 1 +#define DPSECI_OPR_HSEQ_NLIS_SHIFT 0 +#define DPSECI_OPR_HSEQ_NLIS_SIZE 1 + +struct dpseci_rsp_get_opr { + __le64 pad; + u8 flags; + u8 pad0[2]; + u8 oloe; + u8 oeane; + u8 olws; + u8 oa; + u8 oprrws; + __le16 nesn; + __le16 pad1; + __le16 ndsn; + __le16 pad2; + __le16 ea_tseq; + u8 tseq_nlis; + u8 pad3; + __le16 ea_hseq; + u8 hseq_nlis; + u8 pad4; + __le16 ea_hptr; + __le16 pad5; + __le16 ea_tptr; + __le16 pad6; + __le16 opr_vid; + __le16 pad7; + __le16 opr_id; +}; + #define DPSECI_CGN_DEST_TYPE_SHIFT 0 #define DPSECI_CGN_DEST_TYPE_SIZE 4 #define DPSECI_CGN_UNITS_SHIFT 4 diff --git a/drivers/crypto/caam/fsl_jr_uio.c b/drivers/crypto/caam/fsl_jr_uio.c new file mode 100644 index 00000000000000..1dff438e2de0d8 --- /dev/null +++ b/drivers/crypto/caam/fsl_jr_uio.c @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2018 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "regs.h" +#include "fsl_jr_uio.h" + +static const char jr_uio_version[] = "fsl JR UIO driver v1.0"; + +#define NAME_LENGTH 30 +#define JR_INDEX_OFFSET 12 + +static const char uio_device_name[] = "fsl-jr"; +static LIST_HEAD(jr_list); + +struct jr_uio_info { + atomic_t ref; /* exclusive, only one open() at a time */ + struct uio_info uio; + char name[NAME_LENGTH]; +}; + +struct jr_dev { + u32 revision; + u32 index; + u32 irq; + struct caam_job_ring __iomem *global_regs; + struct device *dev; + struct resource *res; + struct jr_uio_info info; + struct list_head node; + struct list_head jr_list; +}; + +static int jr_uio_open(struct uio_info *info, struct inode *inode) +{ + struct jr_uio_info *uio_info = container_of(info, + struct jr_uio_info, uio); + + if (!atomic_dec_and_test(&uio_info->ref)) { + pr_err("%s: failing non-exclusive open()\n", uio_info->name); + atomic_inc(&uio_info->ref); + return -EBUSY; + } + + return 0; +} + +static int jr_uio_release(struct uio_info *info, struct inode *inode) +{ + struct jr_uio_info *uio_info = container_of(info, + struct jr_uio_info, uio); + atomic_inc(&uio_info->ref); + + return 0; +} + +static irqreturn_t jr_uio_irq_handler(int irq, struct uio_info *dev_info) +{ + struct jr_dev *jrdev = dev_info->priv; + u32 irqstate; + + irqstate = rd_reg32(&jrdev->global_regs->jrintstatus); + + if (!irqstate) + return IRQ_NONE; + + if (irqstate & JRINT_JR_ERROR) + dev_info(jrdev->dev, "uio job ring error - irqstate: %08x\n", + irqstate); + + /*mask valid interrupts */ + clrsetbits_32(&jrdev->global_regs->rconfig_lo, 0, JRCFG_IMSK); + + /* Have valid interrupt at this point, just ACK and trigger */ + wr_reg32(&jrdev->global_regs->jrintstatus, irqstate); + + return IRQ_HANDLED; +} + +static int jr_uio_irqcontrol(struct uio_info *dev_info, int irqon) +{ + struct jr_dev *jrdev = dev_info->priv; + + switch (irqon) { + case SEC_UIO_SIMULATE_IRQ_CMD: + uio_event_notify(dev_info); + break; + case SEC_UIO_ENABLE_IRQ_CMD: + /* Enable Job Ring interrupt */ + clrsetbits_32(&jrdev->global_regs->rconfig_lo, JRCFG_IMSK, 0); + break; + case SEC_UIO_DISABLE_IRQ_CMD: + /* Disable Job Ring interrupt */ + clrsetbits_32(&jrdev->global_regs->rconfig_lo, 0, JRCFG_IMSK); + break; + default: + break; + } + return 0; +} + +static int __init jr_uio_init(struct jr_dev *uio_dev) +{ + int ret; + struct jr_uio_info *info; + + info = &uio_dev->info; + atomic_set(&info->ref, 1); + info->uio.version = jr_uio_version; + info->uio.name = uio_dev->info.name; + info->uio.mem[0].name = "JR config space"; + info->uio.mem[0].addr = uio_dev->res->start; + info->uio.mem[0].size = uio_dev->res->end - uio_dev->res->start + 1; + info->uio.mem[0].internal_addr = uio_dev->global_regs; + info->uio.mem[0].memtype = UIO_MEM_PHYS; + info->uio.irq = uio_dev->irq; + info->uio.irq_flags = IRQF_SHARED; + info->uio.handler = jr_uio_irq_handler; + info->uio.irqcontrol = jr_uio_irqcontrol; + info->uio.open = jr_uio_open; + info->uio.release = jr_uio_release; + info->uio.priv = uio_dev; + + ret = uio_register_device(uio_dev->dev, &info->uio); + if (ret) { + dev_err(uio_dev->dev, "jr_uio: UIO registration failed\n"); + return ret; + } + + return 0; +} + +static const struct of_device_id jr_ids[] = { + { .compatible = "fsl,sec-v4.0-job-ring", }, + { .compatible = "fsl,sec-v4.4-job-ring", }, + { .compatible = "fsl,sec-v5.0-job-ring", }, + { .compatible = "fsl,sec-v6.0-job-ring", }, + {}, +}; + +static int fsl_jr_probe(struct platform_device *dev) +{ + struct resource regs; + struct jr_dev *jr_dev; + struct device_node *jr_node; + int ret, count = 0; + struct list_head *p; + + jr_node = dev->dev.of_node; + if (!jr_node) { + dev_err(&dev->dev, "Device OF-Node is NULL\n"); + return -EFAULT; + } + + jr_dev = devm_kzalloc(&dev->dev, sizeof(*jr_dev), GFP_KERNEL); + if (!jr_dev) + return -ENOMEM; + + /* Creat name and index */ + list_for_each(p, &jr_list) { + count++; + } + jr_dev->index = count; + + snprintf(jr_dev->info.name, sizeof(jr_dev->info.name) - 1, + "%s%d", uio_device_name, jr_dev->index); + + jr_dev->dev = &dev->dev; + platform_set_drvdata(dev, jr_dev); + + /* Get the resource from dtb node */ + ret = of_address_to_resource(jr_node, 0, ®s); + if (unlikely(ret < 0)) { + dev_err(&dev->dev, "OF-Address-to-resource Failed\n"); + ret = -EFAULT; + goto abort; + } + + jr_dev->res = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (unlikely(!jr_dev->res)) { + dev_err(jr_dev->dev, "platform_get_resource() failed\n"); + ret = -ENOMEM; + goto abort; + } + + jr_dev->global_regs = + devm_ioremap(&dev->dev, jr_dev->res->start, + jr_dev->res->end - jr_dev->res->start + 1); + if (unlikely(jr_dev->global_regs == 0)) { + dev_err(jr_dev->dev, "devm_ioremap failed\n"); + ret = -EIO; + goto abort; + } + jr_dev->irq = irq_of_parse_and_map(jr_node, 0); + dev_dbg(jr_dev->dev, "errirq: %d\n", jr_dev->irq); + + /* Register UIO */ + ret = jr_uio_init(jr_dev); + if (ret) { + dev_err(&dev->dev, "UIO init Failed\n"); + goto abort; + } + + list_add_tail(&jr_dev->node, &jr_list); + + dev_info(jr_dev->dev, "UIO device full name %s initialized\n", + jr_dev->info.name); + + return 0; + +abort: + return ret; +} + +static int fsl_jr_remove(struct platform_device *dev) +{ + struct jr_dev *jr_dev = platform_get_drvdata(dev); + + if (!jr_dev) + return 0; + + list_del(&jr_dev->node); + uio_unregister_device(&jr_dev->info.uio); + + return 0; +} + +MODULE_DEVICE_TABLE(of, jr_ids); + +static struct platform_driver fsl_jr_driver = { + .driver = { + .name = "fsl-jr-uio", + .of_match_table = jr_ids, + }, + .probe = fsl_jr_probe, + .remove = fsl_jr_remove, +}; + +module_platform_driver(fsl_jr_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("NXP"); +MODULE_DESCRIPTION("FSL SEC UIO Driver"); diff --git a/drivers/crypto/caam/fsl_jr_uio.h b/drivers/crypto/caam/fsl_jr_uio.h new file mode 100644 index 00000000000000..2956645e12968e --- /dev/null +++ b/drivers/crypto/caam/fsl_jr_uio.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * CAAM Job RING UIO support header file + * + * Copyright 2013 Freescale Semiconductor, Inc + * Copyright 2018 NXP + */ + +#ifndef FSL_JR_UIO_H +#define FSL_JR_UIO_H + +/** UIO command used by user-space driver to request + * disabling IRQs on a certain job ring + */ +#define SEC_UIO_DISABLE_IRQ_CMD 0 +/** UIO command used by user-space driver to request + * enabling IRQs on a certain job ring + */ +#define SEC_UIO_ENABLE_IRQ_CMD 1 +/** UIO command used by user-space driver to request SEC kernel driver + * to simulate that an IRQ is generated on a certain job ring + */ +#define SEC_UIO_SIMULATE_IRQ_CMD 2 + +#endif diff --git a/drivers/crypto/caam/intern.h b/drivers/crypto/caam/intern.h index 731b06becd9c91..038a1cede82cdc 100644 --- a/drivers/crypto/caam/intern.h +++ b/drivers/crypto/caam/intern.h @@ -11,6 +11,7 @@ #define INTERN_H #include "ctrl.h" +#include /* Currently comes from Kconfig param as a ^2 (driver-required) */ #define JOBR_DEPTH (1 << CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE) @@ -38,6 +39,18 @@ struct caam_jrentry_info { u32 desc_size; /* Stored size for postprocessing, header derived */ }; +#ifdef CONFIG_PM_SLEEP +struct caam_jr_state { + dma_addr_t inpbusaddr; + dma_addr_t outbusaddr; +}; +#endif + +struct caam_jr_dequeue_params { + struct device *dev; + int enable_itr; +}; + /* Private sub-storage for a single JobR */ struct caam_drv_private_jr { struct list_head list_node; /* Job Ring device list */ @@ -45,6 +58,7 @@ struct caam_drv_private_jr { int ridx; struct caam_job_ring __iomem *rregs; /* JobR's register space */ struct tasklet_struct irqtask; + struct caam_jr_dequeue_params tasklet_params; int irq; /* One per queue */ /* Number of scatterlist crypt transforms active on the JobR */ @@ -60,18 +74,37 @@ struct caam_drv_private_jr { int out_ring_read_index; /* Output index "tail" */ int tail; /* entinfo (s/w ring) tail index */ void *outring; /* Base of output ring, DMA-safe */ + struct crypto_engine *engine; + +#ifdef CONFIG_PM_SLEEP + struct caam_jr_state state; /* State of the JR during PM */ +#endif }; +#ifdef CONFIG_PM_SLEEP +struct caam_ctl_state { + struct masterid deco_mid[16]; + struct masterid jr_mid[4]; + u32 mcr; + u32 scfgr; +}; +#endif + /* * Driver-private storage for a single CAAM block instance */ struct caam_drv_private { + struct device *smdev; + /* Physical-presence section */ struct caam_ctrl __iomem *ctrl; /* controller region */ struct caam_deco __iomem *deco; /* DECO/CCB views */ struct caam_assurance __iomem *assure; struct caam_queue_if __iomem *qi; /* QI control region */ struct caam_job_ring __iomem *jr[4]; /* JobR's register space */ + dma_addr_t __iomem *sm_base; /* Secure memory storage base */ + phys_addr_t sm_phy; /* Secure memory storage physical */ + u32 sm_size; struct iommu_domain *domain; @@ -81,11 +114,10 @@ struct caam_drv_private { */ u8 total_jobrs; /* Total Job Rings in device */ u8 qi_present; /* Nonzero if QI present in device */ -#ifdef CONFIG_CAAM_QI - u8 qi_init; /* Nonzero if QI has been initialized */ -#endif + u8 sm_present; /* Nonzero if Secure Memory is supported */ u8 mc_en; /* Nonzero if MC f/w is active */ - int secvio_irq; /* Security violation interrupt number */ + u8 scu_en; /* Nonzero if SCU f/w is active */ + u8 optee_en; /* Nonzero if OP-TEE f/w is active */ int virt_en; /* Virtualization enabled in CAAM */ int era; /* CAAM Era (internal HW revision) */ @@ -102,10 +134,14 @@ struct caam_drv_private { * variables at runtime. */ #ifdef CONFIG_DEBUG_FS - struct dentry *dfs_root; struct dentry *ctl; /* controller dir */ struct debugfs_blob_wrapper ctl_kek_wrap, ctl_tkek_wrap, ctl_tdsk_wrap; #endif + +#ifdef CONFIG_PM_SLEEP + int caam_off_during_pm; /* If the CAAM is reset after suspend */ + struct caam_ctl_state state; /* State of the CTL during PM */ +#endif }; #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API @@ -198,6 +234,24 @@ static inline void caam_qi_algapi_exit(void) #endif /* CONFIG_CAAM_QI */ +#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_SM + +int caam_sm_startup(struct device *dev); +void caam_sm_shutdown(struct device *dev); + +#else + +static inline int caam_sm_startup(struct device *dev) +{ + return 0; +} + +static inline void caam_sm_shutdown(struct device *dev) +{ +} + +#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_SM */ + #ifdef CONFIG_DEBUG_FS static int caam_debugfs_u64_get(void *data, u64 *val) { diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c index fc97cde2705950..31559e6ef7e86d 100644 --- a/drivers/crypto/caam/jr.c +++ b/drivers/crypto/caam/jr.c @@ -34,6 +34,7 @@ static void register_algs(struct device *dev) if (++active_devs != 1) goto algs_unlock; + caam_sm_startup(dev); caam_algapi_init(dev); caam_algapi_hash_init(dev); caam_pkc_init(dev); @@ -44,7 +45,7 @@ static void register_algs(struct device *dev) mutex_unlock(&algs_lock); } -static void unregister_algs(void) +static void unregister_algs(struct device *dev) { mutex_lock(&algs_lock); @@ -57,24 +58,50 @@ static void unregister_algs(void) caam_pkc_exit(); caam_algapi_hash_exit(); caam_algapi_exit(); + caam_sm_shutdown(dev); algs_unlock: mutex_unlock(&algs_lock); } -static int caam_reset_hw_jr(struct device *dev) +static int jr_driver_probed; + +int caam_jr_driver_probed(void) +{ + return jr_driver_probed; +} +EXPORT_SYMBOL(caam_jr_driver_probed); + +static void caam_jr_crypto_engine_exit(void *data) +{ + struct device *jrdev = data; + struct caam_drv_private_jr *jrpriv = dev_get_drvdata(jrdev); + + /* Free the resources of crypto-engine */ + crypto_engine_exit(jrpriv->engine); +} + +/* + * Put the CAAM in quiesce, ie stop + * + * Must be called with itr disabled + */ +static int caam_jr_stop_processing(struct device *dev, u32 jrcr_bits) { struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); unsigned int timeout = 100000; - /* - * mask interrupts since we are going to poll - * for reset completion status - */ - clrsetbits_32(&jrp->rregs->rconfig_lo, 0, JRCFG_IMSK); + /* Check the current status */ + if (rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_INPROGRESS) + goto wait_quiesce_completion; - /* initiate flush (required prior to reset) */ - wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET); + /* Reset the field */ + clrsetbits_32(&jrp->rregs->jrintstatus, JRINT_ERR_HALT_MASK, 0); + + /* initiate flush / park (required prior to reset) */ + wr_reg32(&jrp->rregs->jrcommand, jrcr_bits); + +wait_quiesce_completion: while (((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) == JRINT_ERR_HALT_INPROGRESS) && --timeout) cpu_relax(); @@ -85,8 +112,56 @@ static int caam_reset_hw_jr(struct device *dev) return -EIO; } + return 0; +} + +/* + * Flush the job ring, so the jobs running will be stopped, jobs queued will be + * invalidated and the CAAM will no longer fetch fron input ring. + * + * Must be called with itr disabled + */ +static int caam_jr_flush(struct device *dev) +{ + return caam_jr_stop_processing(dev, JRCR_RESET); +} + +#ifdef CONFIG_PM_SLEEP +/* The resume can be used after a park or a flush if CAAM has not been reset */ +static int caam_jr_restart_processing(struct device *dev) +{ + struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); + u32 halt_status = rd_reg32(&jrp->rregs->jrintstatus) & + JRINT_ERR_HALT_MASK; + + /* Check that the flush/park is completed */ + if (halt_status != JRINT_ERR_HALT_COMPLETE) + return -1; + + /* Resume processing of jobs */ + clrsetbits_32(&jrp->rregs->jrintstatus, 0, JRINT_ERR_HALT_COMPLETE); + + return 0; +} +#endif /* CONFIG_PM_SLEEP */ + +static int caam_reset_hw_jr(struct device *dev) +{ + struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); + unsigned int timeout = 100000; + int err; + + /* + * mask interrupts since we are going to poll + * for reset completion status + */ + clrsetbits_32(&jrp->rregs->rconfig_lo, 0, JRCFG_IMSK); + + err = caam_jr_flush(dev); + if (err) + return err; + /* initiate reset */ - timeout = 100000; wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET); while ((rd_reg32(&jrp->rregs->jrcommand) & JRCR_RESET) && --timeout) cpu_relax(); @@ -135,7 +210,7 @@ static int caam_jr_remove(struct platform_device *pdev) } /* Unregister JR-based RNG & crypto algorithms */ - unregister_algs(); + unregister_algs(jrdev->parent); /* Remove the node from Physical JobR list maintained by driver */ spin_lock(&driver_data.jr_alloc_lock); @@ -147,6 +222,8 @@ static int caam_jr_remove(struct platform_device *pdev) if (ret) dev_err(jrdev, "Failed to shut down job ring\n"); + jr_driver_probed--; + return ret; } @@ -192,7 +269,8 @@ static irqreturn_t caam_jr_interrupt(int irq, void *st_dev) static void caam_jr_dequeue(unsigned long devarg) { int hw_idx, sw_idx, i, head, tail; - struct device *dev = (struct device *)devarg; + struct caam_jr_dequeue_params *params = (void *)devarg; + struct device *dev = params->dev; struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); void (*usercall)(struct device *dev, u32 *desc, u32 status, void *arg); u32 *userdesc, userstatus; @@ -266,8 +344,9 @@ static void caam_jr_dequeue(unsigned long devarg) outring_used--; } - /* reenable / unmask IRQs */ - clrsetbits_32(&jrp->rregs->rconfig_lo, JRCFG_IMSK, 0); + if (params->enable_itr) + /* reenable / unmask IRQs */ + clrsetbits_32(&jrp->rregs->rconfig_lo, JRCFG_IMSK, 0); } /** @@ -310,6 +389,36 @@ struct device *caam_jr_alloc(void) } EXPORT_SYMBOL(caam_jr_alloc); +/** + * caam_jridx_alloc() - Alloc a specific job ring based on its index. + * + * returns : pointer to the newly allocated physical + * JobR dev can be written to if successful. + **/ +struct device *caam_jridx_alloc(int idx) +{ + struct caam_drv_private_jr *jrpriv; + struct device *dev = ERR_PTR(-ENODEV); + + spin_lock(&driver_data.jr_alloc_lock); + + if (list_empty(&driver_data.jr_list)) + goto end; + + list_for_each_entry(jrpriv, &driver_data.jr_list, list_node) { + if (jrpriv->ridx == idx) { + atomic_inc(&jrpriv->tfm_count); + dev = jrpriv->dev; + break; + } + } + +end: + spin_unlock(&driver_data.jr_alloc_lock); + return dev; +} +EXPORT_SYMBOL(caam_jridx_alloc); + /** * caam_jr_free() - Free the Job Ring * @rdev - points to the dev that identifies the Job ring to @@ -324,11 +433,10 @@ void caam_jr_free(struct device *rdev) EXPORT_SYMBOL(caam_jr_free); /** - * caam_jr_enqueue() - Enqueue a job descriptor head. Returns 0 if OK, - * -EBUSY if the queue is full, -EIO if it cannot map the caller's + * caam_jr_enqueue() - Enqueue a job descriptor head. Returns -EINPROGRESS + * if OK, -ENOSPC if the queue is full, -EIO if it cannot map the caller's * descriptor. - * @dev: device of the job ring to be used. This device should have - * been assigned prior by caam_jr_register(). + * @dev: struct device of the job ring to be used * @desc: points to a job descriptor that execute our request. All * descriptors (and all referenced data) must be in a DMAable * region, and all data references must be physical addresses @@ -377,7 +485,7 @@ int caam_jr_enqueue(struct device *dev, u32 *desc, CIRC_SPACE(head, tail, JOBR_DEPTH) <= 0) { spin_unlock_bh(&jrp->inplock); dma_unmap_single(dev, desc_dma, desc_size, DMA_TO_DEVICE); - return -EBUSY; + return -ENOSPC; } head_entry = &jrp->entinfo[head]; @@ -393,8 +501,16 @@ int caam_jr_enqueue(struct device *dev, u32 *desc, * Guarantee that the descriptor's DMA address has been written to * the next slot in the ring before the write index is updated, since * other cores may update this index independently. + * + * Under heavy DDR load, smp_wmb() or dma_wmb() fail to make the input + * ring be updated before the CAAM starts reading it. So, CAAM will + * process, again, an old descriptor address and will put it in the + * output ring. This will make caam_jr_dequeue() to fail, since this + * old descriptor is not in the software ring. + * To fix this, use wmb() which works on the full system instead of + * inner/outer shareable domains. */ - smp_wmb(); + wmb(); jrp->head = (head + 1) & (JOBR_DEPTH - 1); @@ -414,10 +530,33 @@ int caam_jr_enqueue(struct device *dev, u32 *desc, spin_unlock_bh(&jrp->inplock); - return 0; + return -EINPROGRESS; } EXPORT_SYMBOL(caam_jr_enqueue); +static void caam_jr_init_hw(struct device *dev, dma_addr_t inpbusaddr, + dma_addr_t outbusaddr) +{ + struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); + + wr_reg64(&jrp->rregs->inpring_base, inpbusaddr); + wr_reg64(&jrp->rregs->outring_base, outbusaddr); + wr_reg32(&jrp->rregs->inpring_size, JOBR_DEPTH); + wr_reg32(&jrp->rregs->outring_size, JOBR_DEPTH); + + /* Select interrupt coalescing parameters */ + clrsetbits_32(&jrp->rregs->rconfig_lo, 0, JOBR_INTC | + (JOBR_INTC_COUNT_THLD << JRCFG_ICDCT_SHIFT) | + (JOBR_INTC_TIME_THLD << JRCFG_ICTT_SHIFT)); +} + +static void caam_jr_reset_index(struct caam_drv_private_jr *jrp) +{ + jrp->out_ring_read_index = 0; + jrp->head = 0; + jrp->tail = 0; +} + /* * Init JobR independent of platform property detection */ @@ -454,25 +593,16 @@ static int caam_jr_init(struct device *dev) jrp->entinfo[i].desc_addr_dma = !0; /* Setup rings */ - jrp->out_ring_read_index = 0; - jrp->head = 0; - jrp->tail = 0; - - wr_reg64(&jrp->rregs->inpring_base, inpbusaddr); - wr_reg64(&jrp->rregs->outring_base, outbusaddr); - wr_reg32(&jrp->rregs->inpring_size, JOBR_DEPTH); - wr_reg32(&jrp->rregs->outring_size, JOBR_DEPTH); - + caam_jr_reset_index(jrp); jrp->inpring_avail = JOBR_DEPTH; + caam_jr_init_hw(dev, inpbusaddr, outbusaddr); spin_lock_init(&jrp->inplock); - /* Select interrupt coalescing parameters */ - clrsetbits_32(&jrp->rregs->rconfig_lo, 0, JOBR_INTC | - (JOBR_INTC_COUNT_THLD << JRCFG_ICDCT_SHIFT) | - (JOBR_INTC_TIME_THLD << JRCFG_ICTT_SHIFT)); - - tasklet_init(&jrp->irqtask, caam_jr_dequeue, (unsigned long)dev); + jrp->tasklet_params.dev = dev; + jrp->tasklet_params.enable_itr = 1; + tasklet_init(&jrp->irqtask, caam_jr_dequeue, + (unsigned long)&jrp->tasklet_params); /* Connect job ring interrupt handler. */ error = devm_request_irq(dev, jrp->irq, caam_jr_interrupt, IRQF_SHARED, @@ -538,6 +668,25 @@ static int caam_jr_probe(struct platform_device *pdev) return error; } + /* Initialize crypto engine */ + jrpriv->engine = crypto_engine_alloc_init(jrdev, false); + if (!jrpriv->engine) { + dev_err(jrdev, "Could not init crypto-engine\n"); + return -ENOMEM; + } + + error = devm_add_action_or_reset(jrdev, caam_jr_crypto_engine_exit, + jrdev); + if (error) + return error; + + /* Start crypto engine */ + error = crypto_engine_start(jrpriv->engine); + if (error) { + dev_err(jrdev, "Could not start crypto-engine\n"); + return error; + } + /* Identify the interrupt */ jrpriv->irq = irq_of_parse_and_map(nprop, 0); if (!jrpriv->irq) { @@ -562,11 +711,121 @@ static int caam_jr_probe(struct platform_device *pdev) atomic_set(&jrpriv->tfm_count, 0); + device_init_wakeup(&pdev->dev, 1); + device_set_wakeup_enable(&pdev->dev, false); + register_algs(jrdev->parent); + jr_driver_probed++; + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static void caam_jr_get_hw_state(struct device *dev) +{ + struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); + + jrp->state.inpbusaddr = rd_reg64(&jrp->rregs->inpring_base); + jrp->state.outbusaddr = rd_reg64(&jrp->rregs->outring_base); +} + +static int caam_jr_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct caam_drv_private_jr *jrpriv = platform_get_drvdata(pdev); + struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev->parent); + struct caam_jr_dequeue_params suspend_params = { + .dev = dev, + .enable_itr = 0, + }; + + if (ctrlpriv->caam_off_during_pm) { + int err; + + tasklet_disable(&jrpriv->irqtask); + + /* mask itr to call flush */ + clrsetbits_32(&jrpriv->rregs->rconfig_lo, 0, JRCFG_IMSK); + + /* Invalid job in process */ + err = caam_jr_flush(dev); + if (err) { + dev_err(dev, "Failed to flush\n"); + return err; + } + + /* Dequeing jobs flushed */ + caam_jr_dequeue((unsigned long)&suspend_params); + + /* Save state */ + caam_jr_get_hw_state(dev); + } else if (device_may_wakeup(&pdev->dev)) { + enable_irq_wake(jrpriv->irq); + } + + return 0; +} + +static int caam_jr_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct caam_drv_private_jr *jrpriv = platform_get_drvdata(pdev); + struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev->parent); + + if (ctrlpriv->caam_off_during_pm) { + u64 inp_addr; + int err; + + /* + * Check if the CAAM has been resetted checking the address of + * the input ring + */ + inp_addr = rd_reg64(&jrpriv->rregs->inpring_base); + if (inp_addr != 0) { + /* JR still has some configuration */ + if (inp_addr == jrpriv->state.inpbusaddr) { + /* JR has not been resetted */ + err = caam_jr_restart_processing(dev); + if (err) { + dev_err(dev, + "Restart processing failed\n"); + return err; + } + + tasklet_enable(&jrpriv->irqtask); + + clrsetbits_32(&jrpriv->rregs->rconfig_lo, + JRCFG_IMSK, 0); + + return 0; + } else if (ctrlpriv->optee_en) { + /* JR has been used by OPTEE, reset it */ + err = caam_reset_hw_jr(dev); + if (err) { + dev_err(dev, "Failed to reset JR\n"); + return err; + } + } else { + /* No explanation, return error */ + return -EIO; + } + } + + caam_jr_reset_index(jrpriv); + caam_jr_init_hw(dev, jrpriv->state.inpbusaddr, + jrpriv->state.outbusaddr); + + tasklet_enable(&jrpriv->irqtask); + } else if (device_may_wakeup(&pdev->dev)) { + disable_irq_wake(jrpriv->irq); + } return 0; } +SIMPLE_DEV_PM_OPS(caam_jr_pm_ops, caam_jr_suspend, caam_jr_resume); +#endif /* CONFIG_PM_SLEEP */ + static const struct of_device_id caam_jr_match[] = { { .compatible = "fsl,sec-v4.0-job-ring", @@ -582,6 +841,9 @@ static struct platform_driver caam_jr_driver = { .driver = { .name = "caam_jr", .of_match_table = caam_jr_match, +#ifdef CONFIG_PM_SLEEP + .pm = &caam_jr_pm_ops, +#endif }, .probe = caam_jr_probe, .remove = caam_jr_remove, diff --git a/drivers/crypto/caam/jr.h b/drivers/crypto/caam/jr.h index eab611530f3602..7183baa5652ff7 100644 --- a/drivers/crypto/caam/jr.h +++ b/drivers/crypto/caam/jr.h @@ -9,7 +9,9 @@ #define JR_H /* Prototypes for backend-level services exposed to APIs */ +int caam_jr_driver_probed(void); struct device *caam_jr_alloc(void); +struct device *caam_jridx_alloc(int idx); void caam_jr_free(struct device *rdev); int caam_jr_enqueue(struct device *dev, u32 *desc, void (*cbk)(struct device *dev, u32 *desc, u32 status, diff --git a/drivers/crypto/caam/key_gen.c b/drivers/crypto/caam/key_gen.c index 5a851ddc48fbed..b0e8a4939b4ff7 100644 --- a/drivers/crypto/caam/key_gen.c +++ b/drivers/crypto/caam/key_gen.c @@ -108,7 +108,7 @@ int gen_split_key(struct device *jrdev, u8 *key_out, init_completion(&result.completion); ret = caam_jr_enqueue(jrdev, desc, split_key_done, &result); - if (!ret) { + if (ret == -EINPROGRESS) { /* in progress */ wait_for_completion(&result.completion); ret = result.err; diff --git a/drivers/crypto/caam/qi.c b/drivers/crypto/caam/qi.c index 378f627e1d64f6..a0ed99ff813cba 100644 --- a/drivers/crypto/caam/qi.c +++ b/drivers/crypto/caam/qi.c @@ -9,7 +9,7 @@ #include #include -#include +#include #include "regs.h" #include "qi.h" @@ -107,23 +107,21 @@ static void *caam_iova_to_virt(struct iommu_domain *domain, int caam_qi_enqueue(struct device *qidev, struct caam_drv_req *req) { struct qm_fd fd; - dma_addr_t addr; int ret; int num_retries = 0; - qm_fd_clear_fd(&fd); - qm_fd_set_compound(&fd, qm_sg_entry_get_len(&req->fd_sgt[1])); - - addr = dma_map_single(qidev, req->fd_sgt, sizeof(req->fd_sgt), + fd.cmd = 0; + fd.format = qm_fd_compound; + fd.cong_weight = caam32_to_cpu(req->fd_sgt[1].length); + fd.addr = dma_map_single(qidev, req->fd_sgt, sizeof(req->fd_sgt), DMA_BIDIRECTIONAL); - if (dma_mapping_error(qidev, addr)) { + if (dma_mapping_error(qidev, fd.addr)) { dev_err(qidev, "DMA mapping error for QI enqueue request\n"); return -EIO; } - qm_fd_addr_set64(&fd, addr); do { - ret = qman_enqueue(req->drv_ctx->req_fq, &fd); + ret = qman_enqueue(req->drv_ctx->req_fq, &fd, 0); if (likely(!ret)) return 0; @@ -139,7 +137,7 @@ int caam_qi_enqueue(struct device *qidev, struct caam_drv_req *req) EXPORT_SYMBOL(caam_qi_enqueue); static void caam_fq_ern_cb(struct qman_portal *qm, struct qman_fq *fq, - const union qm_mr_entry *msg) + const struct qm_mr_entry *msg) { const struct qm_fd *fd; struct caam_drv_req *drv_req; @@ -148,7 +146,7 @@ static void caam_fq_ern_cb(struct qman_portal *qm, struct qman_fq *fq, fd = &msg->ern.fd; - if (qm_fd_get_format(fd) != qm_fd_compound) { + if (fd->format != qm_fd_compound) { dev_err(qidev, "Non-compound FD from CAAM\n"); return; } @@ -186,20 +184,22 @@ static struct qman_fq *create_caam_req_fq(struct device *qidev, req_fq->cb.fqs = NULL; ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID | - QMAN_FQ_FLAG_TO_DCPORTAL, req_fq); + QMAN_FQ_FLAG_TO_DCPORTAL | QMAN_FQ_FLAG_LOCKED, + req_fq); if (ret) { dev_err(qidev, "Failed to create session req FQ\n"); goto create_req_fq_fail; } - memset(&opts, 0, sizeof(opts)); - opts.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ | - QM_INITFQ_WE_CONTEXTB | - QM_INITFQ_WE_CONTEXTA | QM_INITFQ_WE_CGID); - opts.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_CPCSTASH | QM_FQCTRL_CGE); - qm_fqd_set_destwq(&opts.fqd, qm_channel_caam, 2); - opts.fqd.context_b = cpu_to_be32(qman_fq_fqid(rsp_fq)); - qm_fqd_context_a_set64(&opts.fqd, hwdesc); + opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ | + QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA | + QM_INITFQ_WE_CGID; + opts.fqd.fq_ctrl = QM_FQCTRL_CPCSTASH | QM_FQCTRL_CGE; + opts.fqd.dest.channel = qm_channel_caam; + opts.fqd.dest.wq = 2; + opts.fqd.context_b = qman_fq_fqid(rsp_fq); + opts.fqd.context_a.hi = upper_32_bits(hwdesc); + opts.fqd.context_a.lo = lower_32_bits(hwdesc); opts.fqd.cgid = qipriv.cgr.cgrid; ret = qman_init_fq(req_fq, fq_sched_flag, &opts); @@ -213,7 +213,7 @@ static struct qman_fq *create_caam_req_fq(struct device *qidev, return req_fq; init_req_fq_fail: - qman_destroy_fq(req_fq); + qman_destroy_fq(req_fq, 0); create_req_fq_fail: kfree(req_fq); return ERR_PTR(ret); @@ -281,7 +281,7 @@ static int kill_fq(struct device *qidev, struct qman_fq *fq) if (ret) dev_err(qidev, "OOS of FQID: %u failed\n", fq->fqid); - qman_destroy_fq(fq); + qman_destroy_fq(fq, 0); kfree(fq); return ret; @@ -298,7 +298,7 @@ static int empty_caam_fq(struct qman_fq *fq) if (ret) return ret; - if (!qm_mcr_np_get(&np, frm_cnt)) + if (!np.frm_cnt) break; msleep(20); @@ -500,9 +500,10 @@ void caam_drv_ctx_rel(struct caam_drv_ctx *drv_ctx) } EXPORT_SYMBOL(caam_drv_ctx_rel); -void caam_qi_shutdown(struct device *qidev) +static void caam_qi_shutdown(void *data) { int i; + struct device *qidev = data; struct caam_qi_priv *priv = &qipriv; const cpumask_t *cpus = qman_affine_cpus(); @@ -564,30 +565,28 @@ static enum qman_cb_dqrr_result caam_rsp_fq_dqrr_cb(struct qman_portal *p, const struct qm_fd *fd; struct device *qidev = &(raw_cpu_ptr(&pcpu_qipriv)->net_dev.dev); struct caam_drv_private *priv = dev_get_drvdata(qidev); - u32 status; if (caam_qi_napi_schedule(p, caam_napi)) return qman_cb_dqrr_stop; fd = &dqrr->fd; - status = be32_to_cpu(fd->status); - if (unlikely(status)) { - u32 ssrc = status & JRSTA_SSRC_MASK; - u8 err_id = status & JRSTA_CCBERR_ERRID_MASK; + if (unlikely(fd->status)) { + u32 ssrc = fd->status & JRSTA_SSRC_MASK; + u8 err_id = fd->status & JRSTA_CCBERR_ERRID_MASK; if (ssrc != JRSTA_SSRC_CCB_ERROR || err_id != JRSTA_CCBERR_ERRID_ICVCHK) dev_err_ratelimited(qidev, "Error: %#x in CAAM response FD\n", - status); + fd->status); } - if (unlikely(qm_fd_get_format(fd) != qm_fd_compound)) { + if (unlikely(fd->format != qm_fd_compound)) { dev_err(qidev, "Non-compound FD from CAAM\n"); return qman_cb_dqrr_consume; } - drv_req = caam_iova_to_virt(priv->domain, qm_fd_addr_get64(fd)); + drv_req = caam_iova_to_virt(priv->domain, fd->addr); if (unlikely(!drv_req)) { dev_err(qidev, "Can't find original request for caam response\n"); @@ -597,7 +596,7 @@ static enum qman_cb_dqrr_result caam_rsp_fq_dqrr_cb(struct qman_portal *p, dma_unmap_single(drv_req->drv_ctx->qidev, qm_fd_addr(fd), sizeof(drv_req->fd_sgt), DMA_BIDIRECTIONAL); - drv_req->cbk(drv_req, status); + drv_req->cbk(drv_req, fd->status); return qman_cb_dqrr_consume; } @@ -621,17 +620,18 @@ static int alloc_rsp_fq_cpu(struct device *qidev, unsigned int cpu) return -ENODEV; } - memset(&opts, 0, sizeof(opts)); - opts.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ | - QM_INITFQ_WE_CONTEXTB | - QM_INITFQ_WE_CONTEXTA | QM_INITFQ_WE_CGID); - opts.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_CTXASTASHING | - QM_FQCTRL_CPCSTASH | QM_FQCTRL_CGE); - qm_fqd_set_destwq(&opts.fqd, qman_affine_channel(cpu), 3); + opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ | + QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA | + QM_INITFQ_WE_CGID; + opts.fqd.fq_ctrl = QM_FQCTRL_CTXASTASHING | QM_FQCTRL_CPCSTASH | + QM_FQCTRL_CGE; + opts.fqd.dest.channel = qman_affine_channel(cpu); + opts.fqd.dest.wq = 3; opts.fqd.cgid = qipriv.cgr.cgrid; opts.fqd.context_a.stashing.exclusive = QM_STASHING_EXCL_CTX | QM_STASHING_EXCL_DATA; - qm_fqd_set_stashing(&opts.fqd, 0, 1, 1); + opts.fqd.context_a.stashing.data_cl = 1; + opts.fqd.context_a.stashing.context_cl = 1; ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts); if (ret) { @@ -661,8 +661,7 @@ static int init_cgr(struct device *qidev) qipriv.cgr.cb = cgr_cb; memset(&opts, 0, sizeof(opts)); - opts.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES | - QM_CGR_WE_MODE); + opts.we_mask = QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES | QM_CGR_WE_MODE; opts.cgr.cscn_en = QM_CGR_EN; opts.cgr.mode = QMAN_CGR_MODE_FRAME; qm_cgr_cs_thres_set64(&opts.cgr.cs_thres, val, 1); @@ -761,7 +760,10 @@ int caam_qi_init(struct platform_device *caam_pdev) ×_congested, &caam_fops_u64_ro); #endif - ctrlpriv->qi_init = 1; + err = devm_add_action_or_reset(qidev, caam_qi_shutdown, ctrlpriv); + if (err) + return err; + dev_info(qidev, "Linux CAAM Queue I/F driver initialised\n"); return 0; } diff --git a/drivers/crypto/caam/qi.h b/drivers/crypto/caam/qi.h index db0549549e3bd6..b9294a9d7ccc83 100644 --- a/drivers/crypto/caam/qi.h +++ b/drivers/crypto/caam/qi.h @@ -9,7 +9,7 @@ #ifndef __QI_H__ #define __QI_H__ -#include +#include #include "compat.h" #include "desc.h" #include "desc_constr.h" @@ -147,7 +147,6 @@ int caam_drv_ctx_update(struct caam_drv_ctx *drv_ctx, u32 *sh_desc); void caam_drv_ctx_rel(struct caam_drv_ctx *drv_ctx); int caam_qi_init(struct platform_device *pdev); -void caam_qi_shutdown(struct device *dev); /** * qi_cache_alloc - Allocate buffers from CAAM-QI cache diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h index 05127b70527d7f..6178ae3932ba76 100644 --- a/drivers/crypto/caam/regs.h +++ b/drivers/crypto/caam/regs.h @@ -173,9 +173,14 @@ static inline u64 rd_reg64(void __iomem *reg) static inline u64 cpu_to_caam_dma64(dma_addr_t value) { - if (caam_imx) - return (((u64)cpu_to_caam32(lower_32_bits(value)) << 32) | - (u64)cpu_to_caam32(upper_32_bits(value))); + if (caam_imx) { + u64 ret_val = (u64)cpu_to_caam32(lower_32_bits(value)) << 32; + + if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) + ret_val |= (u64)cpu_to_caam32(upper_32_bits(value)); + + return ret_val; + } return cpu_to_caam64(value); } @@ -377,6 +382,12 @@ struct version_regs { #define CHA_VER_VID_MD_LP512 0x1ull #define CHA_VER_VID_MD_HP 0x2ull +/* + * caam_perfmon - Performance Monitor/Secure Memory Status/ + * CAAM Global Status/Component Version IDs + * + * Spans f00-fff wherever instantiated + */ struct sec_vid { u16 ip_id; u8 maj_rev; @@ -407,17 +418,22 @@ struct caam_perfmon { #define CTPR_MS_PG_SZ_SHIFT 4 u32 comp_parms_ms; /* CTPR - Compile Parameters Register */ u32 comp_parms_ls; /* CTPR - Compile Parameters Register */ - u64 rsvd1[2]; + /* Secure Memory State Visibility */ + u32 rsvd1; + u32 smstatus; /* Secure memory status */ + u32 rsvd2; + u32 smpartown; /* Secure memory partition owner */ /* CAAM Global Status fc0-fdf */ u64 faultaddr; /* FAR - Fault Address */ u32 faultliodn; /* FALR - Fault Address LIODN */ u32 faultdetail; /* FADR - Fault Addr Detail */ - u32 rsvd2; #define CSTA_PLEND BIT(10) #define CSTA_ALT_PLEND BIT(18) + u32 rsvd3; u32 status; /* CSTA - CAAM Status */ - u64 rsvd3; + u32 smpart; /* Secure Memory Partition Parameters */ + u32 smvid; /* Secure Memory Version ID */ /* Component Instantiation Parameters fe0-fff */ u32 rtic_id; /* RVID - RTIC Version ID */ @@ -436,6 +452,62 @@ struct caam_perfmon { u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */ }; +#define SMSTATUS_PART_SHIFT 28 +#define SMSTATUS_PART_MASK (0xf << SMSTATUS_PART_SHIFT) +#define SMSTATUS_PAGE_SHIFT 16 +#define SMSTATUS_PAGE_MASK (0x7ff << SMSTATUS_PAGE_SHIFT) +#define SMSTATUS_MID_SHIFT 8 +#define SMSTATUS_MID_MASK (0x3f << SMSTATUS_MID_SHIFT) +#define SMSTATUS_ACCERR_SHIFT 4 +#define SMSTATUS_ACCERR_MASK (0xf << SMSTATUS_ACCERR_SHIFT) +#define SMSTATUS_ACCERR_NONE 0 +#define SMSTATUS_ACCERR_ALLOC 1 /* Page not allocated */ +#define SMSTATUS_ACCESS_ID 2 /* Not granted by ID */ +#define SMSTATUS_ACCESS_WRITE 3 /* Writes not allowed */ +#define SMSTATUS_ACCESS_READ 4 /* Reads not allowed */ +#define SMSTATUS_ACCESS_NONKEY 6 /* Non-key reads not allowed */ +#define SMSTATUS_ACCESS_BLOB 9 /* Blob access not allowed */ +#define SMSTATUS_ACCESS_DESCB 10 /* Descriptor Blob access spans pages */ +#define SMSTATUS_ACCESS_NON_SM 11 /* Outside Secure Memory range */ +#define SMSTATUS_ACCESS_XPAGE 12 /* Access crosses pages */ +#define SMSTATUS_ACCESS_INITPG 13 /* Page still initializing */ +#define SMSTATUS_STATE_SHIFT 0 +#define SMSTATUS_STATE_MASK (0xf << SMSTATUS_STATE_SHIFT) +#define SMSTATUS_STATE_RESET 0 +#define SMSTATUS_STATE_INIT 1 +#define SMSTATUS_STATE_NORMAL 2 +#define SMSTATUS_STATE_FAIL 3 + +/* up to 15 rings, 2 bits shifted by ring number */ +#define SMPARTOWN_RING_SHIFT 2 +#define SMPARTOWN_RING_MASK 3 +#define SMPARTOWN_AVAILABLE 0 +#define SMPARTOWN_NOEXIST 1 +#define SMPARTOWN_UNAVAILABLE 2 +#define SMPARTOWN_OURS 3 + +/* Maximum number of pages possible */ +#define SMPART_MAX_NUMPG_SHIFT 16 +#define SMPART_MAX_NUMPG_MASK (0x3f << SMPART_MAX_NUMPG_SHIFT) + +/* Maximum partition number */ +#define SMPART_MAX_PNUM_SHIFT 12 +#define SMPART_MAX_PNUM_MASK (0xf << SMPART_MAX_PNUM_SHIFT) + +/* Highest possible page number */ +#define SMPART_MAX_PG_SHIFT 0 +#define SMPART_MAX_PG_MASK (0x3f << SMPART_MAX_PG_SHIFT) + +/* Max size of a page */ +#define SMVID_PG_SIZE_SHIFT 16 +#define SMVID_PG_SIZE_MASK (0x7 << SMVID_PG_SIZE_SHIFT) + +/* Major/Minor Version ID */ +#define SMVID_MAJ_VERS_SHIFT 8 +#define SMVID_MAJ_VERS (0xf << SMVID_MAJ_VERS_SHIFT) +#define SMVID_MIN_VERS_SHIFT 0 +#define SMVID_MIN_VERS (0xf << SMVID_MIN_VERS_SHIFT) + /* LIODN programming for DMA configuration */ #define MSTRID_LOCK_LIODN 0x80000000 #define MSTRID_LOCK_MAKETRUSTED 0x00010000 /* only for JR masterid */ @@ -446,12 +518,6 @@ struct masterid { u32 liodn_ls; /* LIODN for non-sequence and seq access */ }; -/* Partition ID for DMA configuration */ -struct partid { - u32 rsvd1; - u32 pidr; /* partition ID, DECO */ -}; - /* RNGB test mode (replicated twice in some configurations) */ /* Padded out to 0x100 */ struct rngtst { @@ -487,7 +553,8 @@ struct rngtst { /* RNG4 TRNG test registers */ struct rng4tst { -#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */ +#define RTMCTL_ACC BIT(5) /* TRNG access mode */ +#define RTMCTL_PRGM BIT(16) /* 1 -> program mode, 0 -> run mode */ #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in both entropy shifter and statistical checker */ @@ -564,8 +631,7 @@ struct caam_ctrl { u32 deco_rsr; /* DECORSR - Deco Request Source */ u32 rsvd11; u32 deco_rq; /* DECORR - DECO Request */ - struct partid deco_mid[5]; /* DECOxLIODNR - 1 per DECO */ - u32 rsvd5[22]; + struct masterid deco_mid[16]; /* DECOxLIODNR - 1 per DECO */ /* DECO Availability/Reset Section 120-3ff */ u32 deco_avail; /* DAR - DECO availability */ @@ -639,6 +705,35 @@ struct caam_ctrl { #define JRSTART_JR2_START 0x00000004 /* Start Job ring 2 */ #define JRSTART_JR3_START 0x00000008 /* Start Job ring 3 */ +/* Secure Memory Configuration - if you have it */ +/* Secure Memory Register Offset from JR Base Reg*/ +#define SM_V1_OFFSET 0x0f4 +#define SM_V2_OFFSET 0xa00 + +/* Minimum SM Version ID requiring v2 SM register mapping */ +#define SMVID_V2 0x20105 + +struct caam_secure_mem_v1 { + u32 sm_cmd; /* SMCJRx - Secure memory command */ + u32 rsvd1; + u32 sm_status; /* SMCSJRx - Secure memory status */ + u32 rsvd2; + + u32 sm_perm; /* SMAPJRx - Secure memory access perms */ + u32 sm_group2; /* SMAP2JRx - Secure memory access group 2 */ + u32 sm_group1; /* SMAP1JRx - Secure memory access group 1 */ +}; + +struct caam_secure_mem_v2 { + u32 sm_perm; /* SMAPJRx - Secure memory access perms */ + u32 sm_group2; /* SMAP2JRx - Secure memory access group 2 */ + u32 sm_group1; /* SMAP1JRx - Secure memory access group 1 */ + u32 rsvd1[118]; + u32 sm_cmd; /* SMCJRx - Secure memory command */ + u32 rsvd2; + u32 sm_status; /* SMCSJRx - Secure memory status */ +}; + /* * caam_job_ring - direct job ring setup * 1-4 possible per instantiation, base + 1000/2000/3000/4000 @@ -809,6 +904,62 @@ struct caam_job_ring { #define JRCR_RESET 0x01 +/* secure memory command */ +#define SMC_PAGE_SHIFT 16 +#define SMC_PAGE_MASK (0xffff << SMC_PAGE_SHIFT) +#define SMC_PART_SHIFT 8 +#define SMC_PART_MASK (0x0f << SMC_PART_SHIFT) +#define SMC_CMD_SHIFT 0 +#define SMC_CMD_MASK (0x0f << SMC_CMD_SHIFT) + +#define SMC_CMD_ALLOC_PAGE 0x01 /* allocate page to this partition */ +#define SMC_CMD_DEALLOC_PAGE 0x02 /* deallocate page from partition */ +#define SMC_CMD_DEALLOC_PART 0x03 /* deallocate partition */ +#define SMC_CMD_PAGE_INQUIRY 0x05 /* find partition associate with page */ + +/* secure memory (command) status */ +#define SMCS_PAGE_SHIFT 16 +#define SMCS_PAGE_MASK (0x0fff << SMCS_PAGE_SHIFT) +#define SMCS_CMDERR_SHIFT 14 +#define SMCS_CMDERR_MASK (3 << SMCS_CMDERR_SHIFT) +#define SMCS_ALCERR_SHIFT 12 +#define SMCS_ALCERR_MASK (3 << SMCS_ALCERR_SHIFT) +#define SMCS_PGOWN_SHIFT 6 +#define SMCS_PGWON_MASK (3 << SMCS_PGOWN_SHIFT) +#define SMCS_PART_SHIFT 0 +#define SMCS_PART_MASK (0xf << SMCS_PART_SHIFT) + +#define SMCS_CMDERR_NONE 0 +#define SMCS_CMDERR_INCOMP 1 /* Command not yet complete */ +#define SMCS_CMDERR_SECFAIL 2 /* Security failure occurred */ +#define SMCS_CMDERR_OVERFLOW 3 /* Command overflow */ + +#define SMCS_ALCERR_NONE 0 +#define SMCS_ALCERR_PSPERR 1 /* Partion marked PSP (dealloc only) */ +#define SMCS_ALCERR_PAGEAVAIL 2 /* Page not available */ +#define SMCS_ALCERR_PARTOWN 3 /* Partition ownership error */ + +#define SMCS_PGOWN_AVAIL 0 /* Page is available */ +#define SMCS_PGOWN_NOEXIST 1 /* Page initializing or nonexistent */ +#define SMCS_PGOWN_NOOWN 2 /* Page owned by another processor */ +#define SMCS_PGOWN_OWNED 3 /* Page belongs to this processor */ + +/* secure memory access permissions */ +#define SMCS_PERM_KEYMOD_SHIFT 16 +#define SMCA_PERM_KEYMOD_MASK (0xff << SMCS_PERM_KEYMOD_SHIFT) +#define SMCA_PERM_CSP_ZERO 0x8000 /* Zero when deallocated or released */ +#define SMCA_PERM_PSP_LOCK 0x4000 /* Part./pages can't be deallocated */ +#define SMCA_PERM_PERM_LOCK 0x2000 /* Lock permissions */ +#define SMCA_PERM_GRP_LOCK 0x1000 /* Lock access groups */ +#define SMCA_PERM_RINGID_SHIFT 10 +#define SMCA_PERM_RINGID_MASK (3 << SMCA_PERM_RINGID_SHIFT) +#define SMCA_PERM_G2_BLOB 0x0080 /* Group 2 blob import/export */ +#define SMCA_PERM_G2_WRITE 0x0020 /* Group 2 write */ +#define SMCA_PERM_G2_READ 0x0010 /* Group 2 read */ +#define SMCA_PERM_G1_BLOB 0x0008 /* Group 1... */ +#define SMCA_PERM_G1_WRITE 0x0002 +#define SMCA_PERM_G1_READ 0x0001 + /* * caam_assurance - Assurance Controller View * base + 0x6000 padded out to 0x1000 diff --git a/drivers/crypto/caam/secvio.c b/drivers/crypto/caam/secvio.c new file mode 100644 index 00000000000000..237017ada21785 --- /dev/null +++ b/drivers/crypto/caam/secvio.c @@ -0,0 +1,342 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * SNVS Security Violation Handler + * + * Copyright 2012-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + */ + +#include "compat.h" +#include "secvio.h" +#include "regs.h" +#include "intern.h" +#include +#include +#include + +/* The driver is matched with node caam_snvs to get regmap + * It will then retrieve interruption and tamper alarm configuration from + * node caam-secvio searching for the compat string "fsl,imx6q-caam-secvio" + */ +#define DRIVER_NAME "caam-snvs" + +/* + * These names are associated with each violation handler. + * The source names were taken from MX6, and are based on recommendations + * for most common SoCs. + */ +static const u8 *violation_src_name[] = { + "CAAM Internal Security Violation", + "JTAG Alarm", + "Watchdog", + "(reserved)", + "External Boot", + "External Tamper Detect", +}; + +/* These names help describe security monitor state for the console */ +static const u8 *snvs_ssm_state_name[] = { + "init", + "hard fail", + "(undef:2)", + "soft fail", + "(undef:4)", + "(undef:5)", + "(undef:6)", + "(undef:7)", + "transition", + "check", + "(undef:10)", + "non-secure", + "(undef:12)", + "trusted", + "(undef:14)", + "secure", +}; + +/* Top-level security violation interrupt */ +static irqreturn_t snvs_secvio_interrupt(int irq, void *snvsdev) +{ + struct device *dev = snvsdev; + struct snvs_secvio_drv_private *svpriv = dev_get_drvdata(dev); + + clk_enable(svpriv->clk); + /* Check the HP secvio status register */ + svpriv->irqcause = rd_reg32(&svpriv->svregs->hp.secvio_status) & + HP_SECVIOST_SECVIOMASK; + + if (!svpriv->irqcause) { + clk_disable(svpriv->clk); + return IRQ_NONE; + } + + /* Now ACK cause */ + clrsetbits_32(&svpriv->svregs->hp.secvio_status, 0, svpriv->irqcause); + + /* And run deferred service */ + preempt_disable(); + tasklet_schedule(&svpriv->irqtask[smp_processor_id()]); + preempt_enable(); + + clk_disable(svpriv->clk); + + return IRQ_HANDLED; +} + +/* Deferred service handler. Tasklet arg is simply the SNVS dev */ +static void snvs_secvio_dispatch(unsigned long indev) +{ + struct device *dev = (struct device *)indev; + struct snvs_secvio_drv_private *svpriv = dev_get_drvdata(dev); + unsigned long flags; + int i; + + + /* Look through stored causes, call each handler if exists */ + for (i = 0; i < MAX_SECVIO_SOURCES; i++) + if (svpriv->irqcause & (1 << i)) { + spin_lock_irqsave(&svpriv->svlock, flags); + svpriv->intsrc[i].handler(dev, i, + svpriv->intsrc[i].ext); + spin_unlock_irqrestore(&svpriv->svlock, flags); + }; + + /* Re-enable now-serviced interrupts */ + clrsetbits_32(&svpriv->svregs->hp.secvio_intcfg, 0, svpriv->irqcause); +} + +/* + * Default cause handler, used in lieu of an application-defined handler. + * All it does at this time is print a console message. It could force a halt. + */ +static void snvs_secvio_default(struct device *dev, u32 cause, void *ext) +{ + struct snvs_secvio_drv_private *svpriv = dev_get_drvdata(dev); + + dev_err(dev, "Unhandled Security Violation Interrupt %d = %s\n", + cause, svpriv->intsrc[cause].intname); +} + +/* + * Install an application-defined handler for a specified cause + * Arguments: + * - dev points to SNVS-owning device + * - cause interrupt source cause + * - handler application-defined handler, gets called with dev + * source cause, and locally-defined handler argument + * - cause_description points to a string to override the default cause + * name, this can be used as an alternate for error + * messages and such. If left NULL, the default + * description string is used. + * - ext pointer to any extra data needed by the handler. + */ +int snvs_secvio_install_handler(struct device *dev, enum secvio_cause cause, + void (*handler)(struct device *dev, u32 cause, + void *ext), + u8 *cause_description, void *ext) +{ + unsigned long flags; + struct snvs_secvio_drv_private *svpriv; + + svpriv = dev_get_drvdata(dev); + + if ((handler == NULL) || (cause > SECVIO_CAUSE_SOURCE_5)) + return -EINVAL; + + spin_lock_irqsave(&svpriv->svlock, flags); + svpriv->intsrc[cause].handler = handler; + if (cause_description != NULL) + svpriv->intsrc[cause].intname = cause_description; + if (ext != NULL) + svpriv->intsrc[cause].ext = ext; + spin_unlock_irqrestore(&svpriv->svlock, flags); + + return 0; +} +EXPORT_SYMBOL(snvs_secvio_install_handler); + +/* + * Remove an application-defined handler for a specified cause (and, by + * implication, restore the "default". + * Arguments: + * - dev points to SNVS-owning device + * - cause interrupt source cause + */ +int snvs_secvio_remove_handler(struct device *dev, enum secvio_cause cause) +{ + unsigned long flags; + struct snvs_secvio_drv_private *svpriv; + + svpriv = dev_get_drvdata(dev); + + if (cause > SECVIO_CAUSE_SOURCE_5) + return -EINVAL; + + spin_lock_irqsave(&svpriv->svlock, flags); + svpriv->intsrc[cause].intname = violation_src_name[cause]; + svpriv->intsrc[cause].handler = snvs_secvio_default; + svpriv->intsrc[cause].ext = NULL; + spin_unlock_irqrestore(&svpriv->svlock, flags); + return 0; +} +EXPORT_SYMBOL(snvs_secvio_remove_handler); + +static int snvs_secvio_remove(struct platform_device *pdev) +{ + struct device *svdev; + struct snvs_secvio_drv_private *svpriv; + int i; + + svdev = &pdev->dev; + svpriv = dev_get_drvdata(svdev); + + clk_enable(svpriv->clk); + /* Set all sources to nonfatal */ + wr_reg32(&svpriv->svregs->hp.secvio_intcfg, 0); + + /* Remove tasklets and release interrupt */ + for_each_possible_cpu(i) + tasklet_kill(&svpriv->irqtask[i]); + + clk_disable_unprepare(svpriv->clk); + free_irq(svpriv->irq, svdev); + iounmap(svpriv->svregs); + kfree(svpriv); + + return 0; +} + +static int snvs_secvio_probe(struct platform_device *pdev) +{ + struct device *svdev; + struct snvs_secvio_drv_private *svpriv; + struct device_node *np, *npirq; + struct snvs_full __iomem *snvsregs; + int i, error; + u32 hpstate; + const void *jtd, *wtd, *itd, *etd; + u32 td_en; + + svpriv = kzalloc(sizeof(struct snvs_secvio_drv_private), GFP_KERNEL); + if (!svpriv) + return -ENOMEM; + + svdev = &pdev->dev; + dev_set_drvdata(svdev, svpriv); + svpriv->pdev = pdev; + np = pdev->dev.of_node; + + npirq = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-secvio"); + if (!npirq) { + dev_err(svdev, "can't find secvio node\n"); + kfree(svpriv); + return -EINVAL; + } + svpriv->irq = irq_of_parse_and_map(npirq, 0); + if (svpriv->irq <= 0) { + dev_err(svdev, "can't identify secvio interrupt\n"); + kfree(svpriv); + return -EINVAL; + } + + jtd = of_get_property(npirq, "jtag-tamper", NULL); + wtd = of_get_property(npirq, "watchdog-tamper", NULL); + itd = of_get_property(npirq, "internal-boot-tamper", NULL); + etd = of_get_property(npirq, "external-pin-tamper", NULL); + if (!jtd | !wtd | !itd | !etd ) { + dev_err(svdev, "can't identify all tamper alarm configuration\n"); + kfree(svpriv); + return -EINVAL; + } + + /* + * Configure all sources according to device tree property. + * If the property is enabled then the source is ser as + * fatal violations except LP section, + * source #5 (typically used as an external tamper detect), and + * source #3 (typically unused). Whenever the transition to + * secure mode has occurred, these will now be "fatal" violations + */ + td_en = HP_SECVIO_INTEN_SRC0; + if (!strcmp(jtd, "enabled")) + td_en |= HP_SECVIO_INTEN_SRC1; + if (!strcmp(wtd, "enabled")) + td_en |= HP_SECVIO_INTEN_SRC2; + if (!strcmp(itd, "enabled")) + td_en |= HP_SECVIO_INTEN_SRC4; + if (!strcmp(etd, "enabled")) + td_en |= HP_SECVIO_INTEN_SRC5; + + snvsregs = of_iomap(np, 0); + if (!snvsregs) { + dev_err(svdev, "register mapping failed\n"); + return -ENOMEM; + } + svpriv->svregs = (struct snvs_full __force *)snvsregs; + + svpriv->clk = devm_clk_get(&pdev->dev, "ipg"); + if (IS_ERR(svpriv->clk)) { + dev_err(&pdev->dev, "can't get snvs clock\n"); + svpriv->clk = NULL; + } + + clk_prepare_enable(svpriv->clk); + + /* Write the Secvio Enable Config the SVCR */ + wr_reg32(&svpriv->svregs->hp.secvio_ctl, td_en); + wr_reg32(&svpriv->svregs->hp.secvio_intcfg, td_en); + + /* Device data set up. Now init interrupt source descriptions */ + for (i = 0; i < MAX_SECVIO_SOURCES; i++) { + svpriv->intsrc[i].intname = violation_src_name[i]; + svpriv->intsrc[i].handler = snvs_secvio_default; + } + /* Connect main handler */ + for_each_possible_cpu(i) + tasklet_init(&svpriv->irqtask[i], snvs_secvio_dispatch, + (unsigned long)svdev); + + error = request_irq(svpriv->irq, snvs_secvio_interrupt, + IRQF_SHARED, DRIVER_NAME, svdev); + if (error) { + dev_err(svdev, "can't connect secvio interrupt\n"); + irq_dispose_mapping(svpriv->irq); + svpriv->irq = 0; + iounmap(svpriv->svregs); + kfree(svpriv); + return -EINVAL; + } + + hpstate = (rd_reg32(&svpriv->svregs->hp.status) & + HP_STATUS_SSM_ST_MASK) >> HP_STATUS_SSM_ST_SHIFT; + dev_info(svdev, "violation handlers armed - %s state\n", + snvs_ssm_state_name[hpstate]); + + clk_disable(svpriv->clk); + + return 0; +} + +static struct of_device_id snvs_secvio_match[] = { + { + .compatible = "fsl,imx6q-caam-snvs", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, snvs_secvio_match); + +static struct platform_driver snvs_secvio_driver = { + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = snvs_secvio_match, + }, + .probe = snvs_secvio_probe, + .remove = snvs_secvio_remove, +}; + +module_platform_driver(snvs_secvio_driver); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_DESCRIPTION("FSL SNVS Security Violation Handler"); +MODULE_AUTHOR("Freescale Semiconductor - MCU"); diff --git a/drivers/crypto/caam/secvio.h b/drivers/crypto/caam/secvio.h new file mode 100644 index 00000000000000..a7a245a3d7c9cf --- /dev/null +++ b/drivers/crypto/caam/secvio.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * CAAM Security Violation Handler + * + * Copyright 2012-2015 Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + */ + +#ifndef SECVIO_H +#define SECVIO_H + +#include "snvsregs.h" + + +/* + * Defines the published interfaces to install/remove application-specified + * handlers for catching violations + */ + +#define MAX_SECVIO_SOURCES 6 + +/* these are the untranslated causes */ +enum secvio_cause { + SECVIO_CAUSE_SOURCE_0, + SECVIO_CAUSE_SOURCE_1, + SECVIO_CAUSE_SOURCE_2, + SECVIO_CAUSE_SOURCE_3, + SECVIO_CAUSE_SOURCE_4, + SECVIO_CAUSE_SOURCE_5 +}; + +/* These are common "recommended" cause definitions for most devices */ +#define SECVIO_CAUSE_CAAM_VIOLATION SECVIO_CAUSE_SOURCE_0 +#define SECVIO_CAUSE_JTAG_ALARM SECVIO_CAUSE_SOURCE_1 +#define SECVIO_CAUSE_WATCHDOG SECVIO_CAUSE_SOURCE_2 +#define SECVIO_CAUSE_EXTERNAL_BOOT SECVIO_CAUSE_SOURCE_4 +#define SECVIO_CAUSE_TAMPER_DETECT SECVIO_CAUSE_SOURCE_5 + +int snvs_secvio_install_handler(struct device *dev, enum secvio_cause cause, + void (*handler)(struct device *dev, u32 cause, + void *ext), + u8 *cause_description, void *ext); +int snvs_secvio_remove_handler(struct device *dev, enum secvio_cause cause); + +/* + * Private data definitions for the secvio "driver" + */ + +struct secvio_int_src { + const u8 *intname; /* Points to a descriptive name for source */ + void *ext; /* Extended data to pass to the handler */ + void (*handler)(struct device *dev, u32 cause, void *ext); +}; + +struct snvs_secvio_drv_private { + struct platform_device *pdev; + spinlock_t svlock ____cacheline_aligned; + struct tasklet_struct irqtask[NR_CPUS]; + struct snvs_full __iomem *svregs; /* both HP and LP domains */ + struct clk *clk; + int irq; + u32 irqcause; /* stashed cause of violation interrupt */ + + /* Registered handlers for each violation */ + struct secvio_int_src intsrc[MAX_SECVIO_SOURCES]; + +}; + +#endif /* SECVIO_H */ diff --git a/drivers/crypto/caam/sg_sw_qm.h b/drivers/crypto/caam/sg_sw_qm.h index d56cc7efbc135a..9465b577336f98 100644 --- a/drivers/crypto/caam/sg_sw_qm.h +++ b/drivers/crypto/caam/sg_sw_qm.h @@ -7,46 +7,61 @@ #ifndef __SG_SW_QM_H #define __SG_SW_QM_H -#include +#include #include "regs.h" +static inline void cpu_to_hw_sg(struct qm_sg_entry *qm_sg_ptr) +{ + dma_addr_t addr = qm_sg_ptr->opaque; + + qm_sg_ptr->opaque = cpu_to_caam64(addr); + qm_sg_ptr->sgt_efl = cpu_to_caam32(qm_sg_ptr->sgt_efl); +} + static inline void __dma_to_qm_sg(struct qm_sg_entry *qm_sg_ptr, dma_addr_t dma, - u16 offset) + u32 len, u16 offset) { - qm_sg_entry_set64(qm_sg_ptr, dma); + qm_sg_ptr->addr = dma; + qm_sg_ptr->length = len; qm_sg_ptr->__reserved2 = 0; qm_sg_ptr->bpid = 0; - qm_sg_ptr->offset = cpu_to_be16(offset & QM_SG_OFF_MASK); + qm_sg_ptr->__reserved3 = 0; + qm_sg_ptr->offset = offset & QM_SG_OFFSET_MASK; + + cpu_to_hw_sg(qm_sg_ptr); } static inline void dma_to_qm_sg_one(struct qm_sg_entry *qm_sg_ptr, dma_addr_t dma, u32 len, u16 offset) { - __dma_to_qm_sg(qm_sg_ptr, dma, offset); - qm_sg_entry_set_len(qm_sg_ptr, len); + qm_sg_ptr->extension = 0; + qm_sg_ptr->final = 0; + __dma_to_qm_sg(qm_sg_ptr, dma, len, offset); } static inline void dma_to_qm_sg_one_last(struct qm_sg_entry *qm_sg_ptr, dma_addr_t dma, u32 len, u16 offset) { - __dma_to_qm_sg(qm_sg_ptr, dma, offset); - qm_sg_entry_set_f(qm_sg_ptr, len); + qm_sg_ptr->extension = 0; + qm_sg_ptr->final = 1; + __dma_to_qm_sg(qm_sg_ptr, dma, len, offset); } static inline void dma_to_qm_sg_one_ext(struct qm_sg_entry *qm_sg_ptr, dma_addr_t dma, u32 len, u16 offset) { - __dma_to_qm_sg(qm_sg_ptr, dma, offset); - qm_sg_ptr->cfg = cpu_to_be32(QM_SG_EXT | (len & QM_SG_LEN_MASK)); + qm_sg_ptr->extension = 1; + qm_sg_ptr->final = 0; + __dma_to_qm_sg(qm_sg_ptr, dma, len, offset); } static inline void dma_to_qm_sg_one_last_ext(struct qm_sg_entry *qm_sg_ptr, dma_addr_t dma, u32 len, u16 offset) { - __dma_to_qm_sg(qm_sg_ptr, dma, offset); - qm_sg_ptr->cfg = cpu_to_be32(QM_SG_EXT | QM_SG_FIN | - (len & QM_SG_LEN_MASK)); + qm_sg_ptr->extension = 1; + qm_sg_ptr->final = 1; + __dma_to_qm_sg(qm_sg_ptr, dma, len, offset); } /* @@ -79,7 +94,10 @@ static inline void sg_to_qm_sg_last(struct scatterlist *sg, int len, struct qm_sg_entry *qm_sg_ptr, u16 offset) { qm_sg_ptr = sg_to_qm_sg(sg, len, qm_sg_ptr, offset); - qm_sg_entry_set_f(qm_sg_ptr, qm_sg_entry_get_len(qm_sg_ptr)); + + qm_sg_ptr->sgt_efl = caam32_to_cpu(qm_sg_ptr->sgt_efl); + qm_sg_ptr->final = 1; + qm_sg_ptr->sgt_efl = cpu_to_caam32(qm_sg_ptr->sgt_efl); } #endif /* __SG_SW_QM_H */ diff --git a/drivers/crypto/caam/sm.h b/drivers/crypto/caam/sm.h new file mode 100644 index 00000000000000..614c9b4d373f27 --- /dev/null +++ b/drivers/crypto/caam/sm.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * CAAM Secure Memory/Keywrap API Definitions + * + * Copyright 2008-2015 Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + */ + +#ifndef SM_H +#define SM_H + + +/* Storage access permissions */ +#define SM_PERM_READ 0x01 +#define SM_PERM_WRITE 0x02 +#define SM_PERM_BLOB 0x03 + +/* Define treatment of secure memory vs. general memory blobs */ +#define SM_SECMEM 0 +#define SM_GENMEM 1 + +/* Define treatment of red/black keys */ +#define RED_KEY 0 +#define BLACK_KEY 1 + +/* Define key encryption/covering options */ +#define KEY_COVER_ECB 0 /* cover key in AES-ECB */ +#define KEY_COVER_CCM 1 /* cover key with AES-CCM */ + +/* + * Round a key size up to an AES blocksize boundary so to allow for + * padding out to a full block + */ +#define AES_BLOCK_PAD(x) ((x % 16) ? ((x >> 4) + 1) << 4 : x) + +/* Define space required for BKEK + MAC tag storage in any blob */ +#define BLOB_OVERHEAD (32 + 16) + +/* Keystore maintenance functions */ +void sm_init_keystore(struct device *dev); +u32 sm_detect_keystore_units(struct device *dev); +int sm_establish_keystore(struct device *dev, u32 unit); +void sm_release_keystore(struct device *dev, u32 unit); +int caam_sm_example_init(struct platform_device *pdev); + +/* Keystore accessor functions */ +extern int sm_keystore_slot_alloc(struct device *dev, u32 unit, u32 size, + u32 *slot); +extern int sm_keystore_slot_dealloc(struct device *dev, u32 unit, u32 slot); +extern int sm_keystore_slot_load(struct device *dev, u32 unit, u32 slot, + const u8 *key_data, u32 key_length); +extern int sm_keystore_slot_read(struct device *dev, u32 unit, u32 slot, + u32 key_length, u8 *key_data); +extern int sm_keystore_cover_key(struct device *dev, u32 unit, u32 slot, + u16 key_length, u8 keyauth); +extern int sm_keystore_slot_export(struct device *dev, u32 unit, u32 slot, + u8 keycolor, u8 keyauth, u8 *outbuf, + u16 keylen, u8 *keymod); +extern int sm_keystore_slot_import(struct device *dev, u32 unit, u32 slot, + u8 keycolor, u8 keyauth, u8 *inbuf, + u16 keylen, u8 *keymod); + +/* Prior functions from legacy API, deprecated */ +extern int sm_keystore_slot_encapsulate(struct device *dev, u32 unit, + u32 inslot, u32 outslot, u16 secretlen, + u8 *keymod, u16 keymodlen); +extern int sm_keystore_slot_decapsulate(struct device *dev, u32 unit, + u32 inslot, u32 outslot, u16 secretlen, + u8 *keymod, u16 keymodlen); + +/* Data structure to hold per-slot information */ +struct keystore_data_slot_info { + u8 allocated; /* Track slot assignments */ + u32 key_length; /* Size of the key */ +}; + +/* Data structure to hold keystore information */ +struct keystore_data { + void *base_address; /* Virtual base of secure memory pages */ + void *phys_address; /* Physical base of secure memory pages */ + u32 slot_count; /* Number of slots in the keystore */ + struct keystore_data_slot_info *slot; /* Per-slot information */ +}; + +/* store the detected attributes of a secure memory page */ +struct sm_page_descriptor { + u16 phys_pagenum; /* may be discontiguous */ + u16 own_part; /* Owning partition */ + void *pg_base; /* Calculated virtual address */ + void *pg_phys; /* Calculated physical address */ + struct keystore_data *ksdata; +}; + +struct caam_drv_private_sm { + struct device *parentdev; /* this ends up as the controller */ + struct device *smringdev; /* ring that owns this instance */ + struct platform_device *sm_pdev; /* Secure Memory platform device */ + spinlock_t kslock ____cacheline_aligned; + + /* SM Register offset from JR base address */ + u32 sm_reg_offset; + + /* Default parameters for geometry */ + u32 max_pages; /* maximum pages this instance can support */ + u32 top_partition; /* highest partition number in this instance */ + u32 top_page; /* highest page number in this instance */ + u32 page_size; /* page size */ + u32 slot_size; /* selected size of each storage block */ + + /* Partition/Page Allocation Map */ + u32 localpages; /* Number of pages we can access */ + struct sm_page_descriptor *pagedesc; /* Allocated per-page */ + + /* Installed handlers for keystore access */ + int (*data_init)(struct device *dev, u32 unit); + void (*data_cleanup)(struct device *dev, u32 unit); + int (*slot_alloc)(struct device *dev, u32 unit, u32 size, u32 *slot); + int (*slot_dealloc)(struct device *dev, u32 unit, u32 slot); + void *(*slot_get_address)(struct device *dev, u32 unit, u32 handle); + void *(*slot_get_physical)(struct device *dev, u32 unit, u32 handle); + u32 (*slot_get_base)(struct device *dev, u32 unit, u32 handle); + u32 (*slot_get_offset)(struct device *dev, u32 unit, u32 handle); + u32 (*slot_get_slot_size)(struct device *dev, u32 unit, u32 handle); +}; + +#endif /* SM_H */ diff --git a/drivers/crypto/caam/sm_store.c b/drivers/crypto/caam/sm_store.c new file mode 100644 index 00000000000000..a26c6c63b2c0f8 --- /dev/null +++ b/drivers/crypto/caam/sm_store.c @@ -0,0 +1,1270 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * CAAM Secure Memory Storage Interface + * + * Copyright 2008-2015 Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * + * Loosely based on the SHW Keystore API for SCC/SCC2 + * Experimental implementation and NOT intended for upstream use. Expect + * this interface to be amended significantly in the future once it becomes + * integrated into live applications. + * + * Known issues: + * + * - Executes one instance of an secure memory "driver". This is tied to the + * fact that job rings can't run as standalone instances in the present + * configuration. + * + * - It does not expose a userspace interface. The value of a userspace + * interface for access to secrets is a point for further architectural + * discussion. + * + * - Partition/permission management is not part of this interface. It + * depends on some level of "knowledge" agreed upon between bootloader, + * provisioning applications, and OS-hosted software (which uses this + * driver). + * + * - No means of identifying the location or purpose of secrets managed by + * this interface exists; "slot location" and format of a given secret + * needs to be agreed upon between bootloader, provisioner, and OS-hosted + * application. + */ + +#include "compat.h" +#include "regs.h" +#include "jr.h" +#include "desc.h" +#include "intern.h" +#include "error.h" +#include "sm.h" +#include + +#define SECMEM_KEYMOD_LEN 8 +#define GENMEM_KEYMOD_LEN 16 + +#ifdef SM_DEBUG_CONT +void sm_show_page(struct device *dev, struct sm_page_descriptor *pgdesc) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + u32 i, *smdata; + + dev_info(dev, "physical page %d content at 0x%08x\n", + pgdesc->phys_pagenum, pgdesc->pg_base); + smdata = pgdesc->pg_base; + for (i = 0; i < (smpriv->page_size / sizeof(u32)); i += 4) + dev_info(dev, "[0x%08x] 0x%08x 0x%08x 0x%08x 0x%08x\n", + (u32)&smdata[i], smdata[i], smdata[i+1], smdata[i+2], + smdata[i+3]); +} +#endif + +#define INITIAL_DESCSZ 16 /* size of tmp buffer for descriptor const. */ + +static __always_inline u32 sm_send_cmd(struct caam_drv_private_sm *smpriv, + struct caam_drv_private_jr *jrpriv, + u32 cmd, u32 *status) +{ + void __iomem *write_address; + void __iomem *read_address; + + if (smpriv->sm_reg_offset == SM_V1_OFFSET) { + struct caam_secure_mem_v1 *sm_regs_v1; + + sm_regs_v1 = (struct caam_secure_mem_v1 *) + ((void *)jrpriv->rregs + SM_V1_OFFSET); + write_address = &sm_regs_v1->sm_cmd; + read_address = &sm_regs_v1->sm_status; + + } else if (smpriv->sm_reg_offset == SM_V2_OFFSET) { + struct caam_secure_mem_v2 *sm_regs_v2; + + sm_regs_v2 = (struct caam_secure_mem_v2 *) + ((void *)jrpriv->rregs + SM_V2_OFFSET); + write_address = &sm_regs_v2->sm_cmd; + read_address = &sm_regs_v2->sm_status; + + } else { + return -EINVAL; + } + + wr_reg32(write_address, cmd); + + udelay(10); + + /* Read until the command has terminated and the status is correct */ + do { + *status = rd_reg32(read_address); + } while (((*status & SMCS_CMDERR_MASK) >> SMCS_CMDERR_SHIFT) + == SMCS_CMDERR_INCOMP); + + return 0; +} + +/* + * Construct a black key conversion job descriptor + * + * This function constructs a job descriptor capable of performing + * a key blackening operation on a plaintext secure memory resident object. + * + * - desc pointer to a pointer to the descriptor generated by this + * function. Caller will be responsible to kfree() this + * descriptor after execution. + * - key physical pointer to the plaintext, which will also hold + * the result. Since encryption occurs in place, caller must + * ensure that the space is large enough to accommodate the + * blackened key + * - keysz size of the plaintext + * - auth if a CCM-covered key is required, use KEY_COVER_CCM, else + * use KEY_COVER_ECB. + * + * KEY to key1 from @key_addr LENGTH 16 BYTES; + * FIFO STORE from key1[ecb] TO @key_addr LENGTH 16 BYTES; + * + * Note that this variant uses the JDKEK only; it does not accommodate the + * trusted key encryption key at this time. + * + */ +static int blacken_key_jobdesc(u32 **desc, void *key, u16 keysz, bool auth) +{ + u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; + u16 dsize, idx; + + memset(tmpdesc, 0, INITIAL_DESCSZ * sizeof(u32)); + idx = 1; + + /* Load key to class 1 key register */ + tmpdesc[idx++] = CMD_KEY | CLASS_1 | (keysz & KEY_LENGTH_MASK); + tmpdesc[idx++] = (uintptr_t)key; + + /* ...and write back out via FIFO store*/ + tmpdesc[idx] = CMD_FIFO_STORE | CLASS_1 | (keysz & KEY_LENGTH_MASK); + + /* plus account for ECB/CCM option in FIFO_STORE */ + if (auth == KEY_COVER_ECB) + tmpdesc[idx] |= FIFOST_TYPE_KEY_KEK; + else + tmpdesc[idx] |= FIFOST_TYPE_KEY_CCM_JKEK; + + idx++; + tmpdesc[idx++] = (uintptr_t)key; + + /* finish off the job header */ + tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK); + dsize = idx * sizeof(u32); + + /* now allocate execution buffer and coat it with executable */ + tdesc = kmalloc(dsize, GFP_KERNEL | GFP_DMA); + if (tdesc == NULL) + return 0; + + memcpy(tdesc, tmpdesc, dsize); + *desc = tdesc; + + return dsize; +} + +/* + * Construct a blob encapsulation job descriptor + * + * This function dynamically constructs a blob encapsulation job descriptor + * from the following arguments: + * + * - desc pointer to a pointer to the descriptor generated by this + * function. Caller will be responsible to kfree() this + * descriptor after execution. + * - keymod Physical pointer to a key modifier, which must reside in a + * contiguous piece of memory. Modifier will be assumed to be + * 8 bytes long for a blob of type SM_SECMEM, or 16 bytes long + * for a blob of type SM_GENMEM (see blobtype argument). + * - secretbuf Physical pointer to a secret, normally a black or red key, + * possibly residing within an accessible secure memory page, + * of the secret to be encapsulated to an output blob. + * - outbuf Physical pointer to the destination buffer to receive the + * encapsulated output. This buffer will need to be 48 bytes + * larger than the input because of the added encapsulation data. + * The generated descriptor will account for the increase in size, + * but the caller must also account for this increase in the + * buffer allocator. + * - secretsz Size of input secret, in bytes. This is limited to 65536 + * less the size of blob overhead, since the length embeds into + * DECO pointer in/out instructions. + * - keycolor Determines if the source data is covered (black key) or + * plaintext (red key). RED_KEY or BLACK_KEY are defined in + * for this purpose. + * - blobtype Determine if encapsulated blob should be a secure memory + * blob (SM_SECMEM), with partition data embedded with key + * material, or a general memory blob (SM_GENMEM). + * - auth If BLACK_KEY source is covered via AES-CCM, specify + * KEY_COVER_CCM, else uses AES-ECB (KEY_COVER_ECB). + * + * Upon completion, desc points to a buffer containing a CAAM job + * descriptor which encapsulates data into an externally-storable blob + * suitable for use across power cycles. + * + * This is an example of a black key encapsulation job into a general memory + * blob. Notice the 16-byte key modifier in the LOAD instruction. Also note + * the output 48 bytes longer than the input: + * + * [00] B0800008 jobhdr: stidx=0 len=8 + * [01] 14400010 ld: ccb2-key len=16 offs=0 + * [02] 08144891 ptr->@0x08144891 + * [03] F800003A seqoutptr: len=58 + * [04] 01000000 out_ptr->@0x01000000 + * [05] F000000A seqinptr: len=10 + * [06] 09745090 in_ptr->@0x09745090 + * [07] 870D0004 operation: encap blob reg=memory, black, format=normal + * + * This is an example of a red key encapsulation job for storing a red key + * into a secure memory blob. Note the 8 byte modifier on the 12 byte offset + * in the LOAD instruction; this accounts for blob permission storage: + * + * [00] B0800008 jobhdr: stidx=0 len=8 + * [01] 14400C08 ld: ccb2-key len=8 offs=12 + * [02] 087D0784 ptr->@0x087d0784 + * [03] F8000050 seqoutptr: len=80 + * [04] 09251BB2 out_ptr->@0x09251bb2 + * [05] F0000020 seqinptr: len=32 + * [06] 40000F31 in_ptr->@0x40000f31 + * [07] 870D0008 operation: encap blob reg=memory, red, sec_mem, + * format=normal + * + * Note: this function only generates 32-bit pointers at present, and should + * be refactored using a scheme that allows both 32 and 64 bit addressing + */ + +static int blob_encap_jobdesc(u32 **desc, dma_addr_t keymod, + void *secretbuf, dma_addr_t outbuf, + u16 secretsz, u8 keycolor, u8 blobtype, u8 auth) +{ + u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; + u16 dsize, idx; + + memset(tmpdesc, 0, INITIAL_DESCSZ * sizeof(u32)); + idx = 1; + + /* + * Key modifier works differently for secure/general memory blobs + * This accounts for the permission/protection data encapsulated + * within the blob if a secure memory blob is requested + */ + if (blobtype == SM_SECMEM) + tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | + LDST_SRCDST_BYTE_KEY | + ((12 << LDST_OFFSET_SHIFT) & LDST_OFFSET_MASK) + | (8 & LDST_LEN_MASK); + else /* is general memory blob */ + tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | + LDST_SRCDST_BYTE_KEY | (16 & LDST_LEN_MASK); + + tmpdesc[idx++] = (u32)keymod; + + /* + * Encapsulation output must include space for blob key encryption + * key and MAC tag + */ + tmpdesc[idx++] = CMD_SEQ_OUT_PTR | (secretsz + BLOB_OVERHEAD); + tmpdesc[idx++] = (u32)outbuf; + + /* Input data, should be somewhere in secure memory */ + tmpdesc[idx++] = CMD_SEQ_IN_PTR | secretsz; + tmpdesc[idx++] = (uintptr_t)secretbuf; + + /* Set blob encap, then color */ + tmpdesc[idx] = CMD_OPERATION | OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB; + + if (blobtype == SM_SECMEM) + tmpdesc[idx] |= OP_PCL_BLOB_PTXT_SECMEM; + + if (auth == KEY_COVER_CCM) + tmpdesc[idx] |= OP_PCL_BLOB_EKT; + + if (keycolor == BLACK_KEY) + tmpdesc[idx] |= OP_PCL_BLOB_BLACK; + + idx++; + tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK); + dsize = idx * sizeof(u32); + + tdesc = kmalloc(dsize, GFP_KERNEL | GFP_DMA); + if (tdesc == NULL) + return 0; + + memcpy(tdesc, tmpdesc, dsize); + *desc = tdesc; + return dsize; +} + +/* + * Construct a blob decapsulation job descriptor + * + * This function dynamically constructs a blob decapsulation job descriptor + * from the following arguments: + * + * - desc pointer to a pointer to the descriptor generated by this + * function. Caller will be responsible to kfree() this + * descriptor after execution. + * - keymod Physical pointer to a key modifier, which must reside in a + * contiguous piece of memory. Modifier will be assumed to be + * 8 bytes long for a blob of type SM_SECMEM, or 16 bytes long + * for a blob of type SM_GENMEM (see blobtype argument). + * - blobbuf Physical pointer (into external memory) of the blob to + * be decapsulated. Blob must reside in a contiguous memory + * segment. + * - outbuf Physical pointer of the decapsulated output, possibly into + * a location within a secure memory page. Must be contiguous. + * - secretsz Size of encapsulated secret in bytes (not the size of the + * input blob). + * - keycolor Determines if decapsulated content is encrypted (BLACK_KEY) + * or left as plaintext (RED_KEY). + * - blobtype Determine if encapsulated blob should be a secure memory + * blob (SM_SECMEM), with partition data embedded with key + * material, or a general memory blob (SM_GENMEM). + * - auth If decapsulation path is specified by BLACK_KEY, then if + * AES-CCM is requested for key covering use KEY_COVER_CCM, else + * use AES-ECB (KEY_COVER_ECB). + * + * Upon completion, desc points to a buffer containing a CAAM job descriptor + * that decapsulates a key blob from external memory into a black (encrypted) + * key or red (plaintext) content. + * + * This is an example of a black key decapsulation job from a general memory + * blob. Notice the 16-byte key modifier in the LOAD instruction. + * + * [00] B0800008 jobhdr: stidx=0 len=8 + * [01] 14400010 ld: ccb2-key len=16 offs=0 + * [02] 08A63B7F ptr->@0x08a63b7f + * [03] F8000010 seqoutptr: len=16 + * [04] 01000000 out_ptr->@0x01000000 + * [05] F000003A seqinptr: len=58 + * [06] 01000010 in_ptr->@0x01000010 + * [07] 860D0004 operation: decap blob reg=memory, black, format=normal + * + * This is an example of a red key decapsulation job for restoring a red key + * from a secure memory blob. Note the 8 byte modifier on the 12 byte offset + * in the LOAD instruction: + * + * [00] B0800008 jobhdr: stidx=0 len=8 + * [01] 14400C08 ld: ccb2-key len=8 offs=12 + * [02] 01000000 ptr->@0x01000000 + * [03] F8000020 seqoutptr: len=32 + * [04] 400000E6 out_ptr->@0x400000e6 + * [05] F0000050 seqinptr: len=80 + * [06] 08F0C0EA in_ptr->@0x08f0c0ea + * [07] 860D0008 operation: decap blob reg=memory, red, sec_mem, + * format=normal + * + * Note: this function only generates 32-bit pointers at present, and should + * be refactored using a scheme that allows both 32 and 64 bit addressing + */ + +static int blob_decap_jobdesc(u32 **desc, dma_addr_t keymod, dma_addr_t blobbuf, + u8 *outbuf, u16 secretsz, u8 keycolor, + u8 blobtype, u8 auth) +{ + u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; + u16 dsize, idx; + + memset(tmpdesc, 0, INITIAL_DESCSZ * sizeof(u32)); + idx = 1; + + /* Load key modifier */ + if (blobtype == SM_SECMEM) + tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | + LDST_SRCDST_BYTE_KEY | + ((12 << LDST_OFFSET_SHIFT) & LDST_OFFSET_MASK) + | (8 & LDST_LEN_MASK); + else /* is general memory blob */ + tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | + LDST_SRCDST_BYTE_KEY | (16 & LDST_LEN_MASK); + + tmpdesc[idx++] = (u32)keymod; + + /* Compensate BKEK + MAC tag over size of encapsulated secret */ + tmpdesc[idx++] = CMD_SEQ_IN_PTR | (secretsz + BLOB_OVERHEAD); + tmpdesc[idx++] = (u32)blobbuf; + tmpdesc[idx++] = CMD_SEQ_OUT_PTR | secretsz; + tmpdesc[idx++] = (uintptr_t)outbuf; + + /* Decapsulate from secure memory partition to black blob */ + tmpdesc[idx] = CMD_OPERATION | OP_TYPE_DECAP_PROTOCOL | OP_PCLID_BLOB; + + if (blobtype == SM_SECMEM) + tmpdesc[idx] |= OP_PCL_BLOB_PTXT_SECMEM; + + if (auth == KEY_COVER_CCM) + tmpdesc[idx] |= OP_PCL_BLOB_EKT; + + if (keycolor == BLACK_KEY) + tmpdesc[idx] |= OP_PCL_BLOB_BLACK; + + idx++; + tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK); + dsize = idx * sizeof(u32); + + tdesc = kmalloc(dsize, GFP_KERNEL | GFP_DMA); + if (tdesc == NULL) + return 0; + + memcpy(tdesc, tmpdesc, dsize); + *desc = tdesc; + return dsize; +} + +/* + * Pseudo-synchronous ring access functions for carrying out key + * encapsulation and decapsulation + */ + +struct sm_key_job_result { + int error; + struct completion completion; +}; + +void sm_key_job_done(struct device *dev, u32 *desc, u32 err, void *context) +{ + struct sm_key_job_result *res = context; + + if (err) + caam_jr_strstatus(dev, err); + + res->error = err; /* save off the error for postprocessing */ + + complete(&res->completion); /* mark us complete */ +} + +static int sm_key_job(struct device *ksdev, u32 *jobdesc) +{ + struct sm_key_job_result testres = {0}; + struct caam_drv_private_sm *kspriv; + int rtn = 0; + + kspriv = dev_get_drvdata(ksdev); + + init_completion(&testres.completion); + + rtn = caam_jr_enqueue(kspriv->smringdev, jobdesc, sm_key_job_done, + &testres); + if (rtn != -EINPROGRESS) + goto exit; + + wait_for_completion_interruptible(&testres.completion); + rtn = testres.error; + +exit: + return rtn; +} + +/* + * Following section establishes the default methods for keystore access + * They are NOT intended for use external to this module + * + * In the present version, these are the only means for the higher-level + * interface to deal with the mechanics of accessing the phyiscal keystore + */ + + +int slot_alloc(struct device *dev, u32 unit, u32 size, u32 *slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; + u32 i; +#ifdef SM_DEBUG + dev_info(dev, "slot_alloc(): requesting slot for %d bytes\n", size); +#endif + + if (size > smpriv->slot_size) + return -EKEYREJECTED; + + for (i = 0; i < ksdata->slot_count; i++) { + if (ksdata->slot[i].allocated == 0) { + ksdata->slot[i].allocated = 1; + (*slot) = i; +#ifdef SM_DEBUG + dev_info(dev, "slot_alloc(): new slot %d allocated\n", + *slot); +#endif + return 0; + } + } + + return -ENOSPC; +} +EXPORT_SYMBOL(slot_alloc); + +int slot_dealloc(struct device *dev, u32 unit, u32 slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; + u8 __iomem *slotdata; + +#ifdef SM_DEBUG + dev_info(dev, "slot_dealloc(): releasing slot %d\n", slot); +#endif + if (slot >= ksdata->slot_count) + return -EINVAL; + slotdata = ksdata->base_address + slot * smpriv->slot_size; + + if (ksdata->slot[slot].allocated == 1) { + /* Forcibly overwrite the data from the keystore */ + memset_io(ksdata->base_address + slot * smpriv->slot_size, 0, + smpriv->slot_size); + + ksdata->slot[slot].allocated = 0; +#ifdef SM_DEBUG + dev_info(dev, "slot_dealloc(): slot %d released\n", slot); +#endif + return 0; + } + + return -EINVAL; +} +EXPORT_SYMBOL(slot_dealloc); + +void *slot_get_address(struct device *dev, u32 unit, u32 slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; + + if (slot >= ksdata->slot_count) + return NULL; + +#ifdef SM_DEBUG + dev_info(dev, "slot_get_address(): slot %d is 0x%08x\n", slot, + (u32)ksdata->base_address + slot * smpriv->slot_size); +#endif + + return ksdata->base_address + slot * smpriv->slot_size; +} + +void *slot_get_physical(struct device *dev, u32 unit, u32 slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; + + if (slot >= ksdata->slot_count) + return NULL; + +#ifdef SM_DEBUG + dev_info(dev, "%s: slot %d is 0x%08x\n", __func__, slot, + (u32)ksdata->phys_address + slot * smpriv->slot_size); +#endif + + return ksdata->phys_address + slot * smpriv->slot_size; +} + +u32 slot_get_base(struct device *dev, u32 unit, u32 slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; + + /* + * There could potentially be more than one secure partition object + * associated with this keystore. For now, there is just one. + */ + + (void)slot; + +#ifdef SM_DEBUG + dev_info(dev, "slot_get_base(): slot %d = 0x%08x\n", + slot, (u32)ksdata->base_address); +#endif + + return (uintptr_t)(ksdata->base_address); +} + +u32 slot_get_offset(struct device *dev, u32 unit, u32 slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; + + if (slot >= ksdata->slot_count) + return -EINVAL; + +#ifdef SM_DEBUG + dev_info(dev, "slot_get_offset(): slot %d = %d\n", slot, + slot * smpriv->slot_size); +#endif + + return slot * smpriv->slot_size; +} + +u32 slot_get_slot_size(struct device *dev, u32 unit, u32 slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + + +#ifdef SM_DEBUG + dev_info(dev, "slot_get_slot_size(): slot %d = %d\n", slot, + smpriv->slot_size); +#endif + /* All slots are the same size in the default implementation */ + return smpriv->slot_size; +} + + + +int kso_init_data(struct device *dev, u32 unit) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + struct keystore_data *keystore_data = NULL; + u32 slot_count; + u32 keystore_data_size; + + /* + * Calculate the required size of the keystore data structure, based + * on the number of keys that can fit in the partition. + */ + slot_count = smpriv->page_size / smpriv->slot_size; +#ifdef SM_DEBUG + dev_info(dev, "kso_init_data: %d slots initializing\n", slot_count); +#endif + + keystore_data_size = sizeof(struct keystore_data) + + slot_count * + sizeof(struct keystore_data_slot_info); + + keystore_data = kzalloc(keystore_data_size, GFP_KERNEL); + + if (!keystore_data) + return -ENOMEM; + +#ifdef SM_DEBUG + dev_info(dev, "kso_init_data: keystore data size = %d\n", + keystore_data_size); +#endif + + /* + * Place the slot information structure directly after the keystore data + * structure. + */ + keystore_data->slot = (struct keystore_data_slot_info *) + (keystore_data + 1); + keystore_data->slot_count = slot_count; + + smpriv->pagedesc[unit].ksdata = keystore_data; + smpriv->pagedesc[unit].ksdata->base_address = + smpriv->pagedesc[unit].pg_base; + smpriv->pagedesc[unit].ksdata->phys_address = + smpriv->pagedesc[unit].pg_phys; + + return 0; +} + +void kso_cleanup_data(struct device *dev, u32 unit) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + struct keystore_data *keystore_data = NULL; + + if (smpriv->pagedesc[unit].ksdata != NULL) + keystore_data = smpriv->pagedesc[unit].ksdata; + + /* Release the allocated keystore management data */ + kfree(smpriv->pagedesc[unit].ksdata); + + return; +} + + + +/* + * Keystore management section + */ + +void sm_init_keystore(struct device *dev) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + + smpriv->data_init = kso_init_data; + smpriv->data_cleanup = kso_cleanup_data; + smpriv->slot_alloc = slot_alloc; + smpriv->slot_dealloc = slot_dealloc; + smpriv->slot_get_address = slot_get_address; + smpriv->slot_get_physical = slot_get_physical; + smpriv->slot_get_base = slot_get_base; + smpriv->slot_get_offset = slot_get_offset; + smpriv->slot_get_slot_size = slot_get_slot_size; +#ifdef SM_DEBUG + dev_info(dev, "sm_init_keystore(): handlers installed\n"); +#endif +} +EXPORT_SYMBOL(sm_init_keystore); + +/* Return available pages/units */ +u32 sm_detect_keystore_units(struct device *dev) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + + return smpriv->localpages; +} +EXPORT_SYMBOL(sm_detect_keystore_units); + +/* + * Do any keystore specific initializations + */ +int sm_establish_keystore(struct device *dev, u32 unit) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + +#ifdef SM_DEBUG + dev_info(dev, "sm_establish_keystore(): unit %d initializing\n", unit); +#endif + + if (smpriv->data_init == NULL) + return -EINVAL; + + /* Call the data_init function for any user setup */ + return smpriv->data_init(dev, unit); +} +EXPORT_SYMBOL(sm_establish_keystore); + +void sm_release_keystore(struct device *dev, u32 unit) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + +#ifdef SM_DEBUG + dev_info(dev, "sm_establish_keystore(): unit %d releasing\n", unit); +#endif + if ((smpriv != NULL) && (smpriv->data_cleanup != NULL)) + smpriv->data_cleanup(dev, unit); + + return; +} +EXPORT_SYMBOL(sm_release_keystore); + +/* + * Subsequent interfacce (sm_keystore_*) forms the accessor interfacce to + * the keystore + */ +int sm_keystore_slot_alloc(struct device *dev, u32 unit, u32 size, u32 *slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + int retval = -EINVAL; + + spin_lock(&smpriv->kslock); + + if ((smpriv->slot_alloc == NULL) || + (smpriv->pagedesc[unit].ksdata == NULL)) + goto out; + + retval = smpriv->slot_alloc(dev, unit, size, slot); + +out: + spin_unlock(&smpriv->kslock); + return retval; +} +EXPORT_SYMBOL(sm_keystore_slot_alloc); + +int sm_keystore_slot_dealloc(struct device *dev, u32 unit, u32 slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + int retval = -EINVAL; + + spin_lock(&smpriv->kslock); + + if ((smpriv->slot_alloc == NULL) || + (smpriv->pagedesc[unit].ksdata == NULL)) + goto out; + + retval = smpriv->slot_dealloc(dev, unit, slot); +out: + spin_unlock(&smpriv->kslock); + return retval; +} +EXPORT_SYMBOL(sm_keystore_slot_dealloc); + +int sm_keystore_slot_load(struct device *dev, u32 unit, u32 slot, + const u8 *key_data, u32 key_length) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + int retval = -EINVAL; + u32 slot_size; + u8 __iomem *slot_location; + + spin_lock(&smpriv->kslock); + + slot_size = smpriv->slot_get_slot_size(dev, unit, slot); + + if (key_length > slot_size) { + retval = -EFBIG; + goto out; + } + + slot_location = smpriv->slot_get_address(dev, unit, slot); + + memcpy_toio(slot_location, key_data, key_length); + + retval = 0; + +out: + spin_unlock(&smpriv->kslock); + return retval; +} +EXPORT_SYMBOL(sm_keystore_slot_load); + +int sm_keystore_slot_read(struct device *dev, u32 unit, u32 slot, + u32 key_length, u8 *key_data) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + int retval = -EINVAL; + u8 __iomem *slot_addr; + u32 slot_size; + + spin_lock(&smpriv->kslock); + + slot_addr = smpriv->slot_get_address(dev, unit, slot); + slot_size = smpriv->slot_get_slot_size(dev, unit, slot); + + if (key_length > slot_size) { + retval = -EKEYREJECTED; + goto out; + } + + memcpy_fromio(key_data, slot_addr, key_length); + retval = 0; + +out: + spin_unlock(&smpriv->kslock); + return retval; +} +EXPORT_SYMBOL(sm_keystore_slot_read); + +/* + * Blacken a clear key in a slot. Operates "in place". + * Limited to class 1 keys at the present time + */ +int sm_keystore_cover_key(struct device *dev, u32 unit, u32 slot, + u16 key_length, u8 keyauth) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + int retval = 0; + u8 __iomem *slotaddr; + void *slotphys; + u32 dsize, jstat; + u32 __iomem *coverdesc = NULL; + + /* Get the address of the object in the slot */ + slotaddr = (u8 *)smpriv->slot_get_address(dev, unit, slot); + slotphys = (u8 *)smpriv->slot_get_physical(dev, unit, slot); + + dsize = blacken_key_jobdesc(&coverdesc, slotphys, key_length, keyauth); + if (!dsize) + return -ENOMEM; + jstat = sm_key_job(dev, coverdesc); + if (jstat) + retval = -EIO; + + kfree(coverdesc); + return retval; +} +EXPORT_SYMBOL(sm_keystore_cover_key); + +/* Export a black/red key to a blob in external memory */ +int sm_keystore_slot_export(struct device *dev, u32 unit, u32 slot, u8 keycolor, + u8 keyauth, u8 *outbuf, u16 keylen, u8 *keymod) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + int retval = 0; + u8 __iomem *slotaddr, *lkeymod; + u8 __iomem *slotphys; + dma_addr_t keymod_dma, outbuf_dma; + u32 dsize, jstat; + u32 __iomem *encapdesc = NULL; + struct device *dev_for_dma_op; + + /* Use the ring as device for DMA operations */ + dev_for_dma_op = smpriv->smringdev; + + /* Get the base address(es) of the specified slot */ + slotaddr = (u8 *)smpriv->slot_get_address(dev, unit, slot); + slotphys = smpriv->slot_get_physical(dev, unit, slot); + + /* Allocate memory for key modifier compatible with DMA */ + lkeymod = kmalloc(SECMEM_KEYMOD_LEN, GFP_KERNEL | GFP_DMA); + if (!lkeymod) { + retval = (-ENOMEM); + goto exit; + } + + /* Get DMA address for the key modifier */ + keymod_dma = dma_map_single(dev_for_dma_op, lkeymod, + SECMEM_KEYMOD_LEN, DMA_TO_DEVICE); + if (dma_mapping_error(dev_for_dma_op, keymod_dma)) { + dev_err(dev, "unable to map keymod: %p\n", lkeymod); + retval = (-ENOMEM); + goto free_keymod; + } + + /* Copy the keymod and synchronize the DMA */ + memcpy(lkeymod, keymod, SECMEM_KEYMOD_LEN); + dma_sync_single_for_device(dev_for_dma_op, keymod_dma, + SECMEM_KEYMOD_LEN, DMA_TO_DEVICE); + + /* Get DMA address for the destination */ + outbuf_dma = dma_map_single(dev_for_dma_op, outbuf, + keylen + BLOB_OVERHEAD, DMA_FROM_DEVICE); + if (dma_mapping_error(dev_for_dma_op, outbuf_dma)) { + dev_err(dev, "unable to map outbuf: %p\n", outbuf); + retval = (-ENOMEM); + goto unmap_keymod; + } + + /* Build the encapsulation job descriptor */ + dsize = blob_encap_jobdesc(&encapdesc, keymod_dma, slotphys, outbuf_dma, + keylen, keycolor, SM_SECMEM, keyauth); + if (!dsize) { + dev_err(dev, "can't alloc an encapsulation descriptor\n"); + retval = -ENOMEM; + goto unmap_outbuf; + } + + /* Run the job */ + jstat = sm_key_job(dev, encapdesc); + if (jstat) { + retval = (-EIO); + goto free_desc; + } + + /* Synchronize the data received */ + dma_sync_single_for_cpu(dev_for_dma_op, outbuf_dma, + keylen + BLOB_OVERHEAD, DMA_FROM_DEVICE); + +free_desc: + kfree(encapdesc); + +unmap_outbuf: + dma_unmap_single(dev_for_dma_op, outbuf_dma, keylen + BLOB_OVERHEAD, + DMA_FROM_DEVICE); + +unmap_keymod: + dma_unmap_single(dev_for_dma_op, keymod_dma, SECMEM_KEYMOD_LEN, + DMA_TO_DEVICE); + +free_keymod: + kfree(lkeymod); + +exit: + return retval; +} +EXPORT_SYMBOL(sm_keystore_slot_export); + +/* Import a black/red key from a blob residing in external memory */ +int sm_keystore_slot_import(struct device *dev, u32 unit, u32 slot, u8 keycolor, + u8 keyauth, u8 *inbuf, u16 keylen, u8 *keymod) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + int retval = 0; + u8 __iomem *slotaddr, *lkeymod; + u8 __iomem *slotphys; + dma_addr_t keymod_dma, inbuf_dma; + u32 dsize, jstat; + u32 __iomem *decapdesc = NULL; + struct device *dev_for_dma_op; + + /* Use the ring as device for DMA operations */ + dev_for_dma_op = smpriv->smringdev; + + /* Get the base address(es) of the specified slot */ + slotaddr = (u8 *)smpriv->slot_get_address(dev, unit, slot); + slotphys = smpriv->slot_get_physical(dev, unit, slot); + + /* Allocate memory for key modifier compatible with DMA */ + lkeymod = kmalloc(SECMEM_KEYMOD_LEN, GFP_KERNEL | GFP_DMA); + if (!lkeymod) { + retval = (-ENOMEM); + goto exit; + } + + /* Get DMA address for the key modifier */ + keymod_dma = dma_map_single(dev_for_dma_op, lkeymod, + SECMEM_KEYMOD_LEN, DMA_TO_DEVICE); + if (dma_mapping_error(dev_for_dma_op, keymod_dma)) { + dev_err(dev, "unable to map keymod: %p\n", lkeymod); + retval = (-ENOMEM); + goto free_keymod; + } + + /* Copy the keymod and synchronize the DMA */ + memcpy(lkeymod, keymod, SECMEM_KEYMOD_LEN); + dma_sync_single_for_device(dev_for_dma_op, keymod_dma, + SECMEM_KEYMOD_LEN, DMA_TO_DEVICE); + + /* Get DMA address for the input */ + inbuf_dma = dma_map_single(dev_for_dma_op, inbuf, + keylen + BLOB_OVERHEAD, DMA_TO_DEVICE); + if (dma_mapping_error(dev_for_dma_op, inbuf_dma)) { + dev_err(dev, "unable to map inbuf: %p\n", (void *)inbuf_dma); + retval = (-ENOMEM); + goto unmap_keymod; + } + + /* synchronize the DMA */ + dma_sync_single_for_device(dev_for_dma_op, inbuf_dma, + keylen + BLOB_OVERHEAD, DMA_TO_DEVICE); + + /* Build the encapsulation job descriptor */ + dsize = blob_decap_jobdesc(&decapdesc, keymod_dma, inbuf_dma, slotphys, + keylen, keycolor, SM_SECMEM, keyauth); + if (!dsize) { + dev_err(dev, "can't alloc a decapsulation descriptor\n"); + retval = -ENOMEM; + goto unmap_inbuf; + } + + /* Run the job */ + jstat = sm_key_job(dev, decapdesc); + + /* + * May want to expand upon error meanings a bit. Any CAAM status + * is reported as EIO, but we might want to look for something more + * meaningful for something like an ICV error on restore, otherwise + * the caller is left guessing. + */ + if (jstat) { + retval = (-EIO); + goto free_desc; + } + +free_desc: + kfree(decapdesc); + +unmap_inbuf: + dma_unmap_single(dev_for_dma_op, inbuf_dma, keylen + BLOB_OVERHEAD, + DMA_TO_DEVICE); + +unmap_keymod: + dma_unmap_single(dev_for_dma_op, keymod_dma, SECMEM_KEYMOD_LEN, + DMA_TO_DEVICE); + +free_keymod: + kfree(lkeymod); + +exit: + return retval; +} +EXPORT_SYMBOL(sm_keystore_slot_import); + +/* + * Initialization/shutdown subsystem + * Assumes statically-invoked startup/shutdown from the controller driver + * for the present time, to be reworked when a device tree becomes + * available. This code will not modularize in present form. + * + * Also, simply uses ring 0 for execution at the present + */ + +int caam_sm_startup(struct device *ctrldev) +{ + struct device *smdev; + struct caam_drv_private *ctrlpriv; + struct caam_drv_private_sm *smpriv; + struct caam_drv_private_jr *jrpriv; /* need this for reg page */ + struct platform_device *sm_pdev; + struct sm_page_descriptor *lpagedesc; + u32 page, pgstat, lpagect, detectedpage, smvid, smpart; + int ret = 0; + + struct device_node *np; + ctrlpriv = dev_get_drvdata(ctrldev); + + if (!ctrlpriv->sm_present) + return 0; + + /* + * Set up the private block for secure memory + * Only one instance is possible + */ + smpriv = kzalloc(sizeof(struct caam_drv_private_sm), GFP_KERNEL); + if (smpriv == NULL) { + dev_err(ctrldev, "can't alloc private mem for secure memory\n"); + ret = -ENOMEM; + goto exit; + } + smpriv->parentdev = ctrldev; /* copy of parent dev is handy */ + spin_lock_init(&smpriv->kslock); + + /* Create the dev */ + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-sm"); + if (np) + of_node_clear_flag(np, OF_POPULATED); + sm_pdev = of_platform_device_create(np, "caam_sm", ctrldev); + + if (sm_pdev == NULL) { + ret = -EINVAL; + goto free_smpriv; + } + + /* Save a pointer to the platform device for Secure Memory */ + smpriv->sm_pdev = sm_pdev; + smdev = &sm_pdev->dev; + dev_set_drvdata(smdev, smpriv); + ctrlpriv->smdev = smdev; + + /* Set the Secure Memory Register Map Version */ + smvid = rd_reg32(&ctrlpriv->jr[0]->perfmon.smvid); + smpart = rd_reg32(&ctrlpriv->jr[0]->perfmon.smpart); + + if (smvid < SMVID_V2) + smpriv->sm_reg_offset = SM_V1_OFFSET; + else + smpriv->sm_reg_offset = SM_V2_OFFSET; + + /* + * Collect configuration limit data for reference + * This batch comes from the partition data/vid registers in perfmon + */ + smpriv->max_pages = ((smpart & SMPART_MAX_NUMPG_MASK) >> + SMPART_MAX_NUMPG_SHIFT) + 1; + smpriv->top_partition = ((smpart & SMPART_MAX_PNUM_MASK) >> + SMPART_MAX_PNUM_SHIFT) + 1; + smpriv->top_page = ((smpart & SMPART_MAX_PG_MASK) >> + SMPART_MAX_PG_SHIFT) + 1; + smpriv->page_size = 1024 << ((smvid & SMVID_PG_SIZE_MASK) >> + SMVID_PG_SIZE_SHIFT); + smpriv->slot_size = 1 << CONFIG_CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE; + +#ifdef SM_DEBUG + dev_info(smdev, "max pages = %d, top partition = %d\n", + smpriv->max_pages, smpriv->top_partition); + dev_info(smdev, "top page = %d, page size = %d (total = %d)\n", + smpriv->top_page, smpriv->page_size, + smpriv->top_page * smpriv->page_size); + dev_info(smdev, "selected slot size = %d\n", smpriv->slot_size); +#endif + + /* + * Now probe for partitions/pages to which we have access. Note that + * these have likely been set up by a bootloader or platform + * provisioning application, so we have to assume that we "inherit" + * a configuration and work within the constraints of what it might be. + * + * Assume use of the zeroth ring in the present iteration (until + * we can divorce the controller and ring drivers, and then assign + * an SM instance to any ring instance). + */ + smpriv->smringdev = caam_jr_alloc(); + if (!smpriv->smringdev) { + dev_err(smdev, "Device for job ring not created\n"); + ret = -ENODEV; + goto unregister_smpdev; + } + + jrpriv = dev_get_drvdata(smpriv->smringdev); + lpagect = 0; + pgstat = 0; + lpagedesc = kzalloc(sizeof(struct sm_page_descriptor) + * smpriv->max_pages, GFP_KERNEL); + if (lpagedesc == NULL) { + ret = -ENOMEM; + goto free_smringdev; + } + + for (page = 0; page < smpriv->max_pages; page++) { + u32 page_ownership; + + if (sm_send_cmd(smpriv, jrpriv, + ((page << SMC_PAGE_SHIFT) & SMC_PAGE_MASK) | + (SMC_CMD_PAGE_INQUIRY & SMC_CMD_MASK), + &pgstat)) { + ret = -EINVAL; + goto free_lpagedesc; + } + + page_ownership = (pgstat & SMCS_PGWON_MASK) >> SMCS_PGOWN_SHIFT; + if ((page_ownership == SMCS_PGOWN_OWNED) + || (page_ownership == SMCS_PGOWN_NOOWN)) { + /* page allocated */ + lpagedesc[page].phys_pagenum = + (pgstat & SMCS_PAGE_MASK) >> SMCS_PAGE_SHIFT; + lpagedesc[page].own_part = + (pgstat & SMCS_PART_SHIFT) >> SMCS_PART_MASK; + lpagedesc[page].pg_base = (u8 *)ctrlpriv->sm_base + + (smpriv->page_size * page); + if (ctrlpriv->scu_en) { +/* FIXME: get different addresses viewed by CPU and CAAM from + * platform property + */ + lpagedesc[page].pg_phys = (u8 *)0x20800000 + + (smpriv->page_size * page); + } else { + lpagedesc[page].pg_phys = + (u8 *) ctrlpriv->sm_phy + + (smpriv->page_size * page); + } + lpagect++; +#ifdef SM_DEBUG + dev_info(smdev, + "physical page %d, owning partition = %d\n", + lpagedesc[page].phys_pagenum, + lpagedesc[page].own_part); +#endif + } + } + + smpriv->pagedesc = kzalloc(sizeof(struct sm_page_descriptor) * lpagect, + GFP_KERNEL); + if (smpriv->pagedesc == NULL) { + ret = -ENOMEM; + goto free_lpagedesc; + } + smpriv->localpages = lpagect; + + detectedpage = 0; + for (page = 0; page < smpriv->max_pages; page++) { + if (lpagedesc[page].pg_base != NULL) { /* e.g. live entry */ + memcpy(&smpriv->pagedesc[detectedpage], + &lpagedesc[page], + sizeof(struct sm_page_descriptor)); +#ifdef SM_DEBUG_CONT + sm_show_page(smdev, &smpriv->pagedesc[detectedpage]); +#endif + detectedpage++; + } + } + + kfree(lpagedesc); + + sm_init_keystore(smdev); + + goto exit; + +free_lpagedesc: + kfree(lpagedesc); +free_smringdev: + caam_jr_free(smpriv->smringdev); +unregister_smpdev: + of_device_unregister(smpriv->sm_pdev); +free_smpriv: + kfree(smpriv); + +exit: + return ret; +} + +void caam_sm_shutdown(struct device *ctrldev) +{ + struct device *smdev; + struct caam_drv_private *priv; + struct caam_drv_private_sm *smpriv; + + priv = dev_get_drvdata(ctrldev); + if (!priv->sm_present) + return; + + smdev = priv->smdev; + + /* Return if resource not initialized by startup */ + if (smdev == NULL) + return; + + smpriv = dev_get_drvdata(smdev); + + caam_jr_free(smpriv->smringdev); + + /* Remove Secure Memory Platform Device */ + of_device_unregister(smpriv->sm_pdev); + + kfree(smpriv->pagedesc); + kfree(smpriv); +} +EXPORT_SYMBOL(caam_sm_shutdown); diff --git a/drivers/crypto/caam/sm_test.c b/drivers/crypto/caam/sm_test.c new file mode 100644 index 00000000000000..df80eb7cfc357f --- /dev/null +++ b/drivers/crypto/caam/sm_test.c @@ -0,0 +1,582 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Secure Memory / Keystore Exemplification Module + * + * Copyright 2012-2015 Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * + * This module has been overloaded as an example to show: + * - Secure memory subsystem initialization/shutdown + * - Allocation/deallocation of "slots" in a secure memory page + * - Loading and unloading of key material into slots + * - Covering of secure memory objects into "black keys" (ECB only at present) + * - Verification of key covering (by differentiation only) + * - Exportation of keys into secure memory blobs (with display of result) + * - Importation of keys from secure memory blobs (with display of result) + * - Verification of re-imported keys where possible. + * + * The module does not show the use of key objects as working key register + * source material at this time. + * + * This module can use a substantial amount of refactoring, which may occur + * after the API gets some mileage. Furthermore, expect this module to + * eventually disappear once the API is integrated into "real" software. + */ + +#include "compat.h" +#include "regs.h" +#include "intern.h" +#include "desc.h" +#include "error.h" +#include "jr.h" +#include "sm.h" + +/* Fixed known pattern for a key modifier */ +static u8 skeymod[] = { + 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, + 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00 +}; + +/* Fixed known pattern for a key */ +static u8 clrkey[] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x0f, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, + 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, + 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, + 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, + 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, + 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, + 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, + 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, + 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, + 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, + 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, + 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, + 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, + 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, + 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, + 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, + 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, + 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, + 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, + 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff +}; + +static void key_display(struct device *dev, const char *label, u16 size, + u8 *key) +{ + unsigned i; + + dev_dbg(dev, "%s", label); + for (i = 0; i < size; i += 8) + dev_dbg(dev, + "[%04d] %02x %02x %02x %02x %02x %02x %02x %02x\n", + i, key[i], key[i + 1], key[i + 2], key[i + 3], + key[i + 4], key[i + 5], key[i + 6], key[i + 7]); +} + +int caam_sm_example_init(struct platform_device *pdev) +{ + struct device *ctrldev, *ksdev; + struct caam_drv_private *ctrlpriv; + struct caam_drv_private_sm *kspriv; + u32 unit, units; + int rtnval; + u8 clrkey8[8], clrkey16[16], clrkey24[24], clrkey32[32]; + u8 blkkey8[AES_BLOCK_PAD(8)], blkkey16[AES_BLOCK_PAD(16)]; + u8 blkkey24[AES_BLOCK_PAD(24)], blkkey32[AES_BLOCK_PAD(32)]; + u8 rstkey8[AES_BLOCK_PAD(8)], rstkey16[AES_BLOCK_PAD(16)]; + u8 rstkey24[AES_BLOCK_PAD(24)], rstkey32[AES_BLOCK_PAD(32)]; + u8 __iomem *blob8, *blob16, *blob24, *blob32; + u32 keyslot8, keyslot16, keyslot24, keyslot32 = 0; + + blob8 = blob16 = blob24 = blob32 = NULL; + + /* + * 3.5.x and later revs for MX6 should be able to ditch this + * and detect via dts property + */ + ctrldev = &pdev->dev; + ctrlpriv = dev_get_drvdata(ctrldev); + + /* + * If ctrlpriv is NULL, it's probably because the caam driver wasn't + * properly initialized (e.g. RNG4 init failed). Thus, bail out here. + */ + if (!ctrlpriv) + return -ENODEV; + + ksdev = ctrlpriv->smdev; + kspriv = dev_get_drvdata(ksdev); + if (kspriv == NULL) + return -ENODEV; + + /* What keystores are available ? */ + units = sm_detect_keystore_units(ksdev); + if (!units) + dev_err(ksdev, "blkkey_ex: no keystore units available\n"); + + /* + * MX6 bootloader stores some stuff in unit 0, so let's + * use 1 or above + */ + if (units < 2) { + dev_err(ksdev, "blkkey_ex: insufficient keystore units\n"); + return -ENODEV; + } + unit = 1; + + dev_info(ksdev, "blkkey_ex: %d keystore units available\n", units); + + /* Initialize/Establish Keystore */ + sm_establish_keystore(ksdev, unit); /* Initalize store in #1 */ + + /* + * Now let's set up buffers for blobs in DMA-able memory. All are + * larger than need to be so that blob size can be seen. + */ + blob8 = kzalloc(128, GFP_KERNEL | GFP_DMA); + blob16 = kzalloc(128, GFP_KERNEL | GFP_DMA); + blob24 = kzalloc(128, GFP_KERNEL | GFP_DMA); + blob32 = kzalloc(128, GFP_KERNEL | GFP_DMA); + + if ((blob8 == NULL) || (blob16 == NULL) || (blob24 == NULL) || + (blob32 == NULL)) { + rtnval = -ENOMEM; + dev_err(ksdev, "blkkey_ex: can't get blob buffers\n"); + goto freemem; + } + + /* Initialize clear keys with a known and recognizable pattern */ + memcpy(clrkey8, clrkey, 8); + memcpy(clrkey16, clrkey, 16); + memcpy(clrkey24, clrkey, 24); + memcpy(clrkey32, clrkey, 32); + + memset(blkkey8, 0, AES_BLOCK_PAD(8)); + memset(blkkey16, 0, AES_BLOCK_PAD(16)); + memset(blkkey24, 0, AES_BLOCK_PAD(24)); + memset(blkkey32, 0, AES_BLOCK_PAD(32)); + + memset(rstkey8, 0, AES_BLOCK_PAD(8)); + memset(rstkey16, 0, AES_BLOCK_PAD(16)); + memset(rstkey24, 0, AES_BLOCK_PAD(24)); + memset(rstkey32, 0, AES_BLOCK_PAD(32)); + + /* + * Allocate keyslots. Since we're going to blacken keys in-place, + * we want slots big enough to pad out to the next larger AES blocksize + * so pad them out. + */ + rtnval = sm_keystore_slot_alloc(ksdev, unit, AES_BLOCK_PAD(8), + &keyslot8); + if (rtnval) + goto freemem; + + rtnval = sm_keystore_slot_alloc(ksdev, unit, AES_BLOCK_PAD(16), + &keyslot16); + if (rtnval) + goto dealloc_slot8; + + rtnval = sm_keystore_slot_alloc(ksdev, unit, AES_BLOCK_PAD(24), + &keyslot24); + if (rtnval) + goto dealloc_slot16; + + rtnval = sm_keystore_slot_alloc(ksdev, unit, AES_BLOCK_PAD(32), + &keyslot32); + if (rtnval) + goto dealloc_slot24; + + + /* Now load clear key data into the newly allocated slots */ + rtnval = sm_keystore_slot_load(ksdev, unit, keyslot8, clrkey8, 8); + if (rtnval) + goto dealloc; + + rtnval = sm_keystore_slot_load(ksdev, unit, keyslot16, clrkey16, 16); + if (rtnval) + goto dealloc; + + rtnval = sm_keystore_slot_load(ksdev, unit, keyslot24, clrkey24, 24); + if (rtnval) + goto dealloc; + + rtnval = sm_keystore_slot_load(ksdev, unit, keyslot32, clrkey32, 32); + if (rtnval) + goto dealloc; + + /* + * All cleartext keys are loaded into slots (in an unprotected + * partition at this time) + * + * Cover keys in-place + */ + rtnval = sm_keystore_cover_key(ksdev, unit, keyslot8, 8, KEY_COVER_ECB); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't cover 64-bit key\n"); + goto dealloc; + } + + rtnval = sm_keystore_cover_key(ksdev, unit, keyslot16, 16, + KEY_COVER_ECB); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't cover 128-bit key\n"); + goto dealloc; + } + + rtnval = sm_keystore_cover_key(ksdev, unit, keyslot24, 24, + KEY_COVER_ECB); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't cover 192-bit key\n"); + goto dealloc; + } + + rtnval = sm_keystore_cover_key(ksdev, unit, keyslot32, 32, + KEY_COVER_ECB); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't cover 256-bit key\n"); + goto dealloc; + } + + /* + * Keys should be covered and appear sufficiently "random" + * as a result of the covering (blackening) process. Assuming + * non-secure mode, read them back out for examination; they should + * appear as random data, completely differing from the clear + * inputs. So, this will read them back from secure memory and + * compare them. If they match the clear key, then the covering + * operation didn't occur. + */ + + rtnval = sm_keystore_slot_read(ksdev, unit, keyslot8, AES_BLOCK_PAD(8), + blkkey8); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't read 64-bit black key\n"); + goto dealloc; + } + + rtnval = sm_keystore_slot_read(ksdev, unit, keyslot16, + AES_BLOCK_PAD(16), blkkey16); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't read 128-bit black key\n"); + goto dealloc; + } + + rtnval = sm_keystore_slot_read(ksdev, unit, keyslot24, + AES_BLOCK_PAD(24), blkkey24); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't read 192-bit black key\n"); + goto dealloc; + } + + rtnval = sm_keystore_slot_read(ksdev, unit, keyslot32, + AES_BLOCK_PAD(32), blkkey32); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't read 256-bit black key\n"); + goto dealloc; + } + + rtnval = -EINVAL; + if (!memcmp(blkkey8, clrkey8, 8)) { + dev_err(ksdev, "blkkey_ex: 64-bit key cover failed\n"); + goto dealloc; + } + + if (!memcmp(blkkey16, clrkey16, 16)) { + dev_err(ksdev, "blkkey_ex: 128-bit key cover failed\n"); + goto dealloc; + } + + if (!memcmp(blkkey24, clrkey24, 24)) { + dev_err(ksdev, "blkkey_ex: 192-bit key cover failed\n"); + goto dealloc; + } + + if (!memcmp(blkkey32, clrkey32, 32)) { + dev_err(ksdev, "blkkey_ex: 256-bit key cover failed\n"); + goto dealloc; + } + + + key_display(ksdev, "64-bit clear key:", 8, clrkey8); + key_display(ksdev, "64-bit black key:", AES_BLOCK_PAD(8), blkkey8); + + key_display(ksdev, "128-bit clear key:", 16, clrkey16); + key_display(ksdev, "128-bit black key:", AES_BLOCK_PAD(16), blkkey16); + + key_display(ksdev, "192-bit clear key:", 24, clrkey24); + key_display(ksdev, "192-bit black key:", AES_BLOCK_PAD(24), blkkey24); + + key_display(ksdev, "256-bit clear key:", 32, clrkey32); + key_display(ksdev, "256-bit black key:", AES_BLOCK_PAD(32), blkkey32); + + /* + * Now encapsulate all keys as SM blobs out to external memory + * Blobs will appear as random-looking blocks of data different + * from the original source key, and 48 bytes longer than the + * original key, to account for the extra data encapsulated within. + */ + key_display(ksdev, "64-bit unwritten blob:", 96, blob8); + key_display(ksdev, "128-bit unwritten blob:", 96, blob16); + key_display(ksdev, "196-bit unwritten blob:", 96, blob24); + key_display(ksdev, "256-bit unwritten blob:", 96, blob32); + + rtnval = sm_keystore_slot_export(ksdev, unit, keyslot8, BLACK_KEY, + KEY_COVER_ECB, blob8, 8, skeymod); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't encapsulate 64-bit key\n"); + goto dealloc; + } + + rtnval = sm_keystore_slot_export(ksdev, unit, keyslot16, BLACK_KEY, + KEY_COVER_ECB, blob16, 16, skeymod); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't encapsulate 128-bit key\n"); + goto dealloc; + } + + rtnval = sm_keystore_slot_export(ksdev, unit, keyslot24, BLACK_KEY, + KEY_COVER_ECB, blob24, 24, skeymod); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't encapsulate 192-bit key\n"); + goto dealloc; + } + + rtnval = sm_keystore_slot_export(ksdev, unit, keyslot32, BLACK_KEY, + KEY_COVER_ECB, blob32, 32, skeymod); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't encapsulate 256-bit key\n"); + goto dealloc; + } + + key_display(ksdev, "64-bit black key in blob:", 96, blob8); + key_display(ksdev, "128-bit black key in blob:", 96, blob16); + key_display(ksdev, "192-bit black key in blob:", 96, blob24); + key_display(ksdev, "256-bit black key in blob:", 96, blob32); + + /* + * Now re-import black keys from secure-memory blobs stored + * in general memory from the previous operation. Since we are + * working with black keys, and since power has not cycled, the + * restored black keys should match the original blackened keys + * (this would not be true if the blobs were save in some non-volatile + * store, and power was cycled between the save and restore) + */ + rtnval = sm_keystore_slot_import(ksdev, unit, keyslot8, BLACK_KEY, + KEY_COVER_ECB, blob8, 8, skeymod); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't decapsulate 64-bit blob\n"); + goto dealloc; + } + + rtnval = sm_keystore_slot_import(ksdev, unit, keyslot16, BLACK_KEY, + KEY_COVER_ECB, blob16, 16, skeymod); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't decapsulate 128-bit blob\n"); + goto dealloc; + } + + rtnval = sm_keystore_slot_import(ksdev, unit, keyslot24, BLACK_KEY, + KEY_COVER_ECB, blob24, 24, skeymod); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't decapsulate 196-bit blob\n"); + goto dealloc; + } + + rtnval = sm_keystore_slot_import(ksdev, unit, keyslot32, BLACK_KEY, + KEY_COVER_ECB, blob32, 32, skeymod); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't decapsulate 256-bit blob\n"); + goto dealloc; + } + + + /* + * Blobs are now restored as black keys. Read those black keys back + * for a comparison with the original black key, they should match + */ + rtnval = sm_keystore_slot_read(ksdev, unit, keyslot8, AES_BLOCK_PAD(8), + rstkey8); + if (rtnval) { + dev_err(ksdev, + "blkkey_ex: can't read restored 64-bit black key\n"); + goto dealloc; + } + + rtnval = sm_keystore_slot_read(ksdev, unit, keyslot16, + AES_BLOCK_PAD(16), rstkey16); + if (rtnval) { + dev_err(ksdev, + "blkkey_ex: can't read restored 128-bit black key\n"); + goto dealloc; + } + + rtnval = sm_keystore_slot_read(ksdev, unit, keyslot24, + AES_BLOCK_PAD(24), rstkey24); + if (rtnval) { + dev_err(ksdev, + "blkkey_ex: can't read restored 196-bit black key\n"); + goto dealloc; + } + + rtnval = sm_keystore_slot_read(ksdev, unit, keyslot32, + AES_BLOCK_PAD(32), rstkey32); + if (rtnval) { + dev_err(ksdev, + "blkkey_ex: can't read restored 256-bit black key\n"); + goto dealloc; + } + + key_display(ksdev, "restored 64-bit black key:", AES_BLOCK_PAD(8), + rstkey8); + key_display(ksdev, "restored 128-bit black key:", AES_BLOCK_PAD(16), + rstkey16); + key_display(ksdev, "restored 192-bit black key:", AES_BLOCK_PAD(24), + rstkey24); + key_display(ksdev, "restored 256-bit black key:", AES_BLOCK_PAD(32), + rstkey32); + + /* + * Compare the restored black keys with the original blackened keys + * As long as we're operating within the same power cycle, a black key + * restored from a blob should match the original black key IF the + * key happens to be of a size that matches a multiple of the AES + * blocksize. Any key that is padded to fill the block size will not + * match, excepting a key that exceeds a block; only the first full + * blocks will match (assuming ECB). + * + * Therefore, compare the 16 and 32 bit keys, they should match. + * The 24 bit key can only match within the first 16 byte block. + */ + + if (memcmp(rstkey16, blkkey16, AES_BLOCK_PAD(16))) { + dev_err(ksdev, "blkkey_ex: 128-bit restored key mismatch\n"); + rtnval = -EINVAL; + } + + /* Only first AES block will match, remainder subject to padding */ + if (memcmp(rstkey24, blkkey24, 16)) { + dev_err(ksdev, "blkkey_ex: 192-bit restored key mismatch\n"); + rtnval = -EINVAL; + } + + if (memcmp(rstkey32, blkkey32, AES_BLOCK_PAD(32))) { + dev_err(ksdev, "blkkey_ex: 256-bit restored key mismatch\n"); + rtnval = -EINVAL; + } + + + /* Remove keys from keystore */ +dealloc: + sm_keystore_slot_dealloc(ksdev, unit, keyslot32); +dealloc_slot24: + sm_keystore_slot_dealloc(ksdev, unit, keyslot24); +dealloc_slot16: + sm_keystore_slot_dealloc(ksdev, unit, keyslot16); +dealloc_slot8: + sm_keystore_slot_dealloc(ksdev, unit, keyslot8); + + /* Free resources */ +freemem: + kfree(blob8); + kfree(blob16); + kfree(blob24); + kfree(blob32); + + /* Disconnect from keystore and leave */ + sm_release_keystore(ksdev, unit); + + return rtnval; +} +EXPORT_SYMBOL(caam_sm_example_init); + +void caam_sm_example_shutdown(void) +{ + /* unused in present version */ + struct device_node *dev_node; + struct platform_device *pdev; + + /* + * Do of_find_compatible_node() then of_find_device_by_node() + * once a functional device tree is available + */ + dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); + if (!dev_node) { + dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0"); + if (!dev_node) + return; + } + + pdev = of_find_device_by_node(dev_node); + if (!pdev) + return; + + of_node_get(dev_node); + +} + +static int __init caam_sm_test_init(void) +{ + struct device_node *dev_node; + struct platform_device *pdev; + struct caam_drv_private *priv; + int ret; + + /* + * Do of_find_compatible_node() then of_find_device_by_node() + * once a functional device tree is available + */ + dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); + if (!dev_node) { + dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0"); + if (!dev_node) + return -ENODEV; + } + + pdev = of_find_device_by_node(dev_node); + if (!pdev) + return -ENODEV; + + of_node_put(dev_node); + + priv = dev_get_drvdata(&pdev->dev); + if (!priv) { + dev_info(&pdev->dev, "SM driver not ready, aborting tests\n"); + return -ENODEV; + } + if (!priv->sm_present) { + dev_info(&pdev->dev, "No SM support, skipping tests\n"); + return -ENODEV; + } + + ret = caam_sm_example_init(pdev); + if (ret) + dev_err(&pdev->dev, "SM test failed: %d\n", ret); + else + dev_info(&pdev->dev, "SM test passed\n"); + + return ret; +} + + +/* Module-based initialization needs to wait for dev tree */ +#ifdef CONFIG_OF +module_init(caam_sm_test_init); +module_exit(caam_sm_example_shutdown); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_DESCRIPTION("FSL CAAM Black Key Usage Example"); +MODULE_AUTHOR("Freescale Semiconductor - NMSG/MAD"); +#endif diff --git a/drivers/crypto/caam/snvsregs.h b/drivers/crypto/caam/snvsregs.h new file mode 100644 index 00000000000000..4a7e7693328f9f --- /dev/null +++ b/drivers/crypto/caam/snvsregs.h @@ -0,0 +1,239 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * SNVS hardware register-level view + * + * Copyright 2012-2015 Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + */ + +#ifndef SNVSREGS_H +#define SNVSREGS_H + +#include +#include + +/* + * SNVS High Power Domain + * Includes security violations, HA counter, RTC, alarm + */ +struct snvs_hp { + u32 lock; /* HPLR - HP Lock */ + u32 cmd; /* HPCOMR - HP Command */ + u32 ctl; /* HPCR - HP Control */ + u32 secvio_intcfg; /* HPSICR - Security Violation Int Config */ + u32 secvio_ctl; /* HPSVCR - Security Violation Control */ + u32 status; /* HPSR - HP Status */ + u32 secvio_status; /* HPSVSR - Security Violation Status */ + u32 ha_counteriv; /* High Assurance Counter IV */ + u32 ha_counter; /* High Assurance Counter */ + u32 rtc_msb; /* Real Time Clock/Counter MSB */ + u32 rtc_lsb; /* Real Time Counter LSB */ + u32 time_alarm_msb; /* Time Alarm MSB */ + u32 time_alarm_lsb; /* Time Alarm LSB */ +}; + +#define HP_LOCK_HAC_LCK 0x00040000 +#define HP_LOCK_HPSICR_LCK 0x00020000 +#define HP_LOCK_HPSVCR_LCK 0x00010000 +#define HP_LOCK_MKEYSEL_LCK 0x00000200 +#define HP_LOCK_TAMPCFG_LCK 0x00000100 +#define HP_LOCK_TAMPFLT_LCK 0x00000080 +#define HP_LOCK_SECVIO_LCK 0x00000040 +#define HP_LOCK_GENP_LCK 0x00000020 +#define HP_LOCK_MONOCTR_LCK 0x00000010 +#define HP_LOCK_CALIB_LCK 0x00000008 +#define HP_LOCK_SRTC_LCK 0x00000004 +#define HP_LOCK_ZMK_RD_LCK 0x00000002 +#define HP_LOCK_ZMK_WT_LCK 0x00000001 + +#define HP_CMD_NONPRIV_AXS 0x80000000 +#define HP_CMD_HAC_STOP 0x00080000 +#define HP_CMD_HAC_CLEAR 0x00040000 +#define HP_CMD_HAC_LOAD 0x00020000 +#define HP_CMD_HAC_CFG_EN 0x00010000 +#define HP_CMD_SNVS_MSTR_KEY 0x00002000 +#define HP_CMD_PROG_ZMK 0x00001000 +#define HP_CMD_SW_LPSV 0x00000400 +#define HP_CMD_SW_FSV 0x00000200 +#define HP_CMD_SW_SV 0x00000100 +#define HP_CMD_LP_SWR_DIS 0x00000020 +#define HP_CMD_LP_SWR 0x00000010 +#define HP_CMD_SSM_SFNS_DIS 0x00000004 +#define HP_CMD_SSM_ST_DIS 0x00000002 +#define HP_CMD_SMM_ST 0x00000001 + +#define HP_CTL_TIME_SYNC 0x00010000 +#define HP_CTL_CAL_VAL_SHIFT 10 +#define HP_CTL_CAL_VAL_MASK (0x1f << HP_CTL_CALIB_SHIFT) +#define HP_CTL_CALIB_EN 0x00000100 +#define HP_CTL_PI_FREQ_SHIFT 4 +#define HP_CTL_PI_FREQ_MASK (0xf << HP_CTL_PI_FREQ_SHIFT) +#define HP_CTL_PI_EN 0x00000008 +#define HP_CTL_TIMEALARM_EN 0x00000002 +#define HP_CTL_RTC_EN 0x00000001 + +#define HP_SECVIO_INTEN_EN 0x10000000 +#define HP_SECVIO_INTEN_SRC5 0x00000020 +#define HP_SECVIO_INTEN_SRC4 0x00000010 +#define HP_SECVIO_INTEN_SRC3 0x00000008 +#define HP_SECVIO_INTEN_SRC2 0x00000004 +#define HP_SECVIO_INTEN_SRC1 0x00000002 +#define HP_SECVIO_INTEN_SRC0 0x00000001 +#define HP_SECVIO_INTEN_ALL 0x8000003f + +#define HP_SECVIO_ICTL_CFG_SHIFT 30 +#define HP_SECVIO_ICTL_CFG_MASK (0x3 << HP_SECVIO_ICTL_CFG_SHIFT) +#define HP_SECVIO_ICTL_CFG5_SHIFT 5 +#define HP_SECVIO_ICTL_CFG5_MASK (0x3 << HP_SECVIO_ICTL_CFG5_SHIFT) +#define HP_SECVIO_ICTL_CFG_DISABLE 0 +#define HP_SECVIO_ICTL_CFG_NONFATAL 1 +#define HP_SECVIO_ICTL_CFG_FATAL 2 +#define HP_SECVIO_ICTL_CFG4_FATAL 0x00000010 +#define HP_SECVIO_ICTL_CFG3_FATAL 0x00000008 +#define HP_SECVIO_ICTL_CFG2_FATAL 0x00000004 +#define HP_SECVIO_ICTL_CFG1_FATAL 0x00000002 +#define HP_SECVIO_ICTL_CFG0_FATAL 0x00000001 + +#define HP_STATUS_ZMK_ZERO 0x80000000 +#define HP_STATUS_OTPMK_ZERO 0x08000000 +#define HP_STATUS_OTPMK_SYN_SHIFT 16 +#define HP_STATUS_OTPMK_SYN_MASK (0x1ff << HP_STATUS_OTPMK_SYN_SHIFT) +#define HP_STATUS_SSM_ST_SHIFT 8 +#define HP_STATUS_SSM_ST_MASK (0xf << HP_STATUS_SSM_ST_SHIFT) +#define HP_STATUS_SSM_ST_INIT 0 +#define HP_STATUS_SSM_ST_HARDFAIL 1 +#define HP_STATUS_SSM_ST_SOFTFAIL 3 +#define HP_STATUS_SSM_ST_INITINT 8 +#define HP_STATUS_SSM_ST_CHECK 9 +#define HP_STATUS_SSM_ST_NONSECURE 11 +#define HP_STATUS_SSM_ST_TRUSTED 13 +#define HP_STATUS_SSM_ST_SECURE 15 + +#define HP_SECVIOST_ZMK_ECC_FAIL 0x08000000 /* write to clear */ +#define HP_SECVIOST_ZMK_SYN_SHIFT 16 +#define HP_SECVIOST_ZMK_SYN_MASK (0x1ff << HP_SECVIOST_ZMK_SYN_SHIFT) +#define HP_SECVIOST_SECVIO5 0x00000020 +#define HP_SECVIOST_SECVIO4 0x00000010 +#define HP_SECVIOST_SECVIO3 0x00000008 +#define HP_SECVIOST_SECVIO2 0x00000004 +#define HP_SECVIOST_SECVIO1 0x00000002 +#define HP_SECVIOST_SECVIO0 0x00000001 +#define HP_SECVIOST_SECVIOMASK 0x0000003f + +/* + * SNVS Low Power Domain + * Includes glitch detector, SRTC, alarm, monotonic counter, ZMK + */ +struct snvs_lp { + u32 lock; + u32 ctl; + u32 mstr_key_ctl; /* Master Key Control */ + u32 secvio_ctl; /* Security Violation Control */ + u32 tamper_filt_cfg; /* Tamper Glitch Filters Configuration */ + u32 tamper_det_cfg; /* Tamper Detectors Configuration */ + u32 status; + u32 srtc_msb; /* Secure Real Time Clock/Counter MSB */ + u32 srtc_lsb; /* Secure Real Time Clock/Counter LSB */ + u32 time_alarm; /* Time Alarm */ + u32 smc_msb; /* Secure Monotonic Counter MSB */ + u32 smc_lsb; /* Secure Monotonic Counter LSB */ + u32 pwr_glitch_det; /* Power Glitch Detector */ + u32 gen_purpose; + u32 zmk[8]; /* Zeroizable Master Key */ +}; + +#define LP_LOCK_MKEYSEL_LCK 0x00000200 +#define LP_LOCK_TAMPDET_LCK 0x00000100 +#define LP_LOCK_TAMPFLT_LCK 0x00000080 +#define LP_LOCK_SECVIO_LCK 0x00000040 +#define LP_LOCK_GENP_LCK 0x00000020 +#define LP_LOCK_MONOCTR_LCK 0x00000010 +#define LP_LOCK_CALIB_LCK 0x00000008 +#define LP_LOCK_SRTC_LCK 0x00000004 +#define LP_LOCK_ZMK_RD_LCK 0x00000002 +#define LP_LOCK_ZMK_WT_LCK 0x00000001 + +#define LP_CTL_CAL_VAL_SHIFT 10 +#define LP_CTL_CAL_VAL_MASK (0x1f << LP_CTL_CAL_VAL_SHIFT) +#define LP_CTL_CALIB_EN 0x00000100 +#define LP_CTL_SRTC_INVAL_EN 0x00000010 +#define LP_CTL_WAKE_INT_EN 0x00000008 +#define LP_CTL_MONOCTR_EN 0x00000004 +#define LP_CTL_TIMEALARM_EN 0x00000002 +#define LP_CTL_SRTC_EN 0x00000001 + +#define LP_MKEYCTL_ZMKECC_SHIFT 8 +#define LP_MKEYCTL_ZMKECC_MASK (0xff << LP_MKEYCTL_ZMKECC_SHIFT) +#define LP_MKEYCTL_ZMKECC_EN 0x00000010 +#define LP_MKEYCTL_ZMKECC_VAL 0x00000008 +#define LP_MKEYCTL_ZMKECC_PROG 0x00000004 +#define LP_MKEYCTL_MKSEL_SHIFT 0 +#define LP_MKEYCTL_MKSEL_MASK (3 << LP_MKEYCTL_MKSEL_SHIFT) +#define LP_MKEYCTL_MK_OTP 0 +#define LP_MKEYCTL_MK_ZMK 2 +#define LP_MKEYCTL_MK_COMB 3 + +#define LP_SECVIO_CTL_SRC5 0x20 +#define LP_SECVIO_CTL_SRC4 0x10 +#define LP_SECVIO_CTL_SRC3 0x08 +#define LP_SECVIO_CTL_SRC2 0x04 +#define LP_SECVIO_CTL_SRC1 0x02 +#define LP_SECVIO_CTL_SRC0 0x01 + +#define LP_TAMPFILT_EXT2_EN 0x80000000 +#define LP_TAMPFILT_EXT2_SHIFT 24 +#define LP_TAMPFILT_EXT2_MASK (0x1f << LP_TAMPFILT_EXT2_SHIFT) +#define LP_TAMPFILT_EXT1_EN 0x00800000 +#define LP_TAMPFILT_EXT1_SHIFT 16 +#define LP_TAMPFILT_EXT1_MASK (0x1f << LP_TAMPFILT_EXT1_SHIFT) +#define LP_TAMPFILT_WM_EN 0x00000080 +#define LP_TAMPFILT_WM_SHIFT 0 +#define LP_TAMPFILT_WM_MASK (0x1f << LP_TAMPFILT_WM_SHIFT) + +#define LP_TAMPDET_OSC_BPS 0x10000000 +#define LP_TAMPDET_VRC_SHIFT 24 +#define LP_TAMPDET_VRC_MASK (3 << LP_TAMPFILT_VRC_SHIFT) +#define LP_TAMPDET_HTDC_SHIFT 20 +#define LP_TAMPDET_HTDC_MASK (3 << LP_TAMPFILT_HTDC_SHIFT) +#define LP_TAMPDET_LTDC_SHIFT 16 +#define LP_TAMPDET_LTDC_MASK (3 << LP_TAMPFILT_LTDC_SHIFT) +#define LP_TAMPDET_POR_OBS 0x00008000 +#define LP_TAMPDET_PFD_OBS 0x00004000 +#define LP_TAMPDET_ET2_EN 0x00000400 +#define LP_TAMPDET_ET1_EN 0x00000200 +#define LP_TAMPDET_WMT2_EN 0x00000100 +#define LP_TAMPDET_WMT1_EN 0x00000080 +#define LP_TAMPDET_VT_EN 0x00000040 +#define LP_TAMPDET_TT_EN 0x00000020 +#define LP_TAMPDET_CT_EN 0x00000010 +#define LP_TAMPDET_MCR_EN 0x00000004 +#define LP_TAMPDET_SRTCR_EN 0x00000002 + +#define LP_STATUS_SECURE +#define LP_STATUS_NONSECURE +#define LP_STATUS_SCANEXIT 0x00100000 /* all write 1 clear here on */ +#define LP_STATUS_EXT_SECVIO 0x00010000 +#define LP_STATUS_ET2 0x00000400 +#define LP_STATUS_ET1 0x00000200 +#define LP_STATUS_WMT2 0x00000100 +#define LP_STATUS_WMT1 0x00000080 +#define LP_STATUS_VTD 0x00000040 +#define LP_STATUS_TTD 0x00000020 +#define LP_STATUS_CTD 0x00000010 +#define LP_STATUS_PGD 0x00000008 +#define LP_STATUS_MCR 0x00000004 +#define LP_STATUS_SRTCR 0x00000002 +#define LP_STATUS_LPTA 0x00000001 + +/* Full SNVS register page, including version/options */ +struct snvs_full { + struct snvs_hp hp; + struct snvs_lp lp; + u32 rsvd[731]; /* deadspace 0x08c-0xbf7 */ + + /* Version / Revision / Option ID space - end of register page */ + u32 vid; /* 0xbf8 HP Version ID (VID 1) */ + u32 opt_rev; /* 0xbfc HP Options / Revision (VID 2) */ +}; + +#endif /* SNVSREGS_H */ diff --git a/drivers/crypto/caam/tag_object.c b/drivers/crypto/caam/tag_object.c new file mode 100644 index 00000000000000..d046b65cc746b6 --- /dev/null +++ b/drivers/crypto/caam/tag_object.c @@ -0,0 +1,260 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Copyright 2018-2019 NXP + */ + +#include +#include +#include + +#include "tag_object.h" +#include "desc.h" + +/* + * Magic number to clearly identify the structure is for us + * 0x54 = 'T' + * 0x61 = 'a' + * 0x67 = 'g' + * 0x4f = 'O' + */ +#define TAG_OBJECT_MAGIC 0x5461674f + +/** + * struct tagged_object - Structure representing a tagged object + * @tag : The configuration of the data + * @object : The object + */ +struct tagged_object { + struct tag_object_conf tag; + char object; +}; + +/** + * is_bk_type() - Determines if black key type. + * @type: The type + * + * Return: True if black key type, False otherwise. + */ +static bool is_bk_type(enum tag_type type) +{ + return (type == TAG_TYPE_BLACK_KEY_ECB) || + (type == TAG_TYPE_BLACK_KEY_ECB_TRUSTED) || + (type == TAG_TYPE_BLACK_KEY_CCM) || + (type == TAG_TYPE_BLACK_KEY_CCM_TRUSTED); +} + +/** + * is_bk_conf() - Determines if black key conf. + * @tag_obj_conf : The tag object conf + * + * Return: True if black key conf, False otherwise. + */ +bool is_bk_conf(const struct tag_object_conf *tag_obj_conf) +{ + return is_bk_type(tag_obj_conf->header.type); +} +EXPORT_SYMBOL(is_bk_conf); + +/** + * get_bk_conf() - Gets the block conf. + * @tag_obj_conf : The tag object conf + * + * Return: The block conf. + */ +const struct blackey_conf *get_bk_conf(const struct tag_object_conf *tag_obj_conf) +{ + return &tag_obj_conf->conf.bk_conf; +} + +/** + * get_tag_object_overhead() - Gets the tag object overhead. + * + * Return: The tag object overhead. + */ +size_t get_tag_object_overhead(void) +{ + return TAG_OVERHEAD; +} +EXPORT_SYMBOL(get_tag_object_overhead); + +/** + * is_valid_type() - Determines if valid type. + * @type : The type + * + * Return: True if valid type, False otherwise. + */ +bool is_valid_type(enum tag_type type) +{ + return (type > TAG_TYPE_NOT_SUPPORTED) && (type < NB_TAG_TYPE); +} +EXPORT_SYMBOL(is_valid_type); + +/** + * is_valid_header() - Determines if valid header. + * @header : The header + * + * Return: True if valid tag object conf, False otherwise. + */ +static bool is_valid_header(const struct conf_header *header) +{ + bool valid = header->_magic_number == TAG_OBJECT_MAGIC; + + valid = valid && is_valid_type(header->type); + + return valid; +} + +/** + * is_valid_tag_object_conf() - Determines if valid tag object conf. + * @tag_obj_conf : The tag object conf + * + * Return: True if valid header, False otherwise. + */ +bool is_valid_tag_object_conf(const struct tag_object_conf *tag_obj_conf) +{ + bool valid = true; + + valid = is_valid_header(&tag_obj_conf->header); + + return valid; +} +EXPORT_SYMBOL(is_valid_tag_object_conf); + +/** + * get_tag_object_conf() - Gets a pointer on the tag object conf. + * @tag_obj_conf : The tag object conf + * @buffer : The buffer + * @size : The size + * + * Return: 0 if success, else error code + */ +int get_tag_object_conf(const void *buffer, size_t size, + struct tag_object_conf **tag_obj_conf) +{ + bool is_valid; + struct tagged_object *tago = (struct tagged_object *)buffer; + size_t conf_size = get_tag_object_overhead(); + + /* Check we can retrieve the conf */ + if (size < conf_size) + return -EINVAL; + + is_valid = is_valid_tag_object_conf(&tago->tag); + + *tag_obj_conf = &tago->tag; + + return (is_valid) ? 0 : -EINVAL; +} +EXPORT_SYMBOL(get_tag_object_conf); + +/** + * init_tag_object_header() - Initialize the tag object header + * @conf_header : The configuration header + * @type : The type + * + * It initialize the header structure + */ +void init_tag_object_header(struct conf_header *conf_header, + enum tag_type type) +{ + conf_header->_magic_number = TAG_OBJECT_MAGIC; + conf_header->type = type; +} +EXPORT_SYMBOL(init_tag_object_header); + +/** + * set_tag_object_conf() - Sets the tag object conf. + * @tag_obj_conf : The tag object conf + * @buffer : The buffer + * @obj_size : The object size + * @to_size : The tagged object size + * + * Return: 0 if success, else error code + */ +int set_tag_object_conf(const struct tag_object_conf *tag_obj_conf, + void *buffer, size_t obj_size, u32 *to_size) +{ + struct tagged_object *tago = buffer; + size_t conf_size = get_tag_object_overhead(); + size_t req_size = obj_size + conf_size; + + /* Check we can set the conf */ + if (*to_size < req_size) { + *to_size = req_size; + return -EINVAL; + } + + /* Move the object */ + memmove(&tago->object, buffer, obj_size); + + /* Copy the tag */ + memcpy(&tago->tag, tag_obj_conf, conf_size); + + *to_size = req_size; + + return 0; +} +EXPORT_SYMBOL(set_tag_object_conf); + +/** + * init_blackey_conf() - Initialize the black key configuration + * @blackey_conf : The blackey conf + * @len : The length + * @ccm : The ccm + * @tk : The trusted key + * + * It initialize the black key configuration structure + */ +void init_blackey_conf(struct blackey_conf *blackey_conf, + size_t len, bool ccm, bool tk) +{ + blackey_conf->real_len = len; + blackey_conf->load = KEY_ENC + | ((ccm) ? KEY_EKT : 0) + | ((tk) ? KEY_TK : 0); +} +EXPORT_SYMBOL(init_blackey_conf); + +/** + * get_blackey_conf() - Get the black key configuration + * @blackey_conf : The blackey conf + * @real_len : The real length + * @load_param : The load parameter + * + * It retrieve the black key configuration + */ +void get_blackey_conf(const struct blackey_conf *blackey_conf, + u32 *real_len, u32 *load_param) +{ + *real_len = blackey_conf->real_len; + *load_param = blackey_conf->load; +} +EXPORT_SYMBOL(get_blackey_conf); + +/** + * get_tagged_data() - Get a pointer on the data and the size + * @tagged_object : Pointer on the tagged object + * @tagged_object_size : tagged object size in bytes + * @data : Pointer on the data + * @data_size : data size in bytes + * + * Return: 0 if success, else error code + */ +int get_tagged_data(const void *tagged_object, size_t tagged_object_size, + const void **data, u32 *data_size) +{ + struct tagged_object *tago = + (struct tagged_object *)tagged_object; + size_t conf_size = get_tag_object_overhead(); + + /* Check we can retrieve the object */ + if (tagged_object_size < conf_size) + return -EINVAL; + + /* Retrieve the object */ + *data = &tago->object; + *data_size = tagged_object_size - conf_size; + + return 0; +} +EXPORT_SYMBOL(get_tagged_data); diff --git a/drivers/crypto/caam/tag_object.h b/drivers/crypto/caam/tag_object.h new file mode 100644 index 00000000000000..4ad41d68e29b1a --- /dev/null +++ b/drivers/crypto/caam/tag_object.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright 2018-2019 NXP + */ + +#ifndef _TAG_OBJECT_H_ +#define _TAG_OBJECT_H_ + +#include + +#define TAG_MIN_SIZE (2 * sizeof(struct conf_header)) +#define TAG_OVERHEAD sizeof(struct tag_object_conf) + +/** + * enum tag_type - Type of data represented by the tag + */ +enum tag_type { + /** @TAG_TYPE_NOT_SUPPORTED: The type is not supported */ + TAG_TYPE_NOT_SUPPORTED = 0, + + /* Type that passes is_tag_type_valid() */ + /** @TAG_TYPE_BLACK_KEY_ECB: Black key encrypted with ECB */ + TAG_TYPE_BLACK_KEY_ECB, + /** + * @TAG_TYPE_BLACK_KEY_ECB_TRUSTED: ECB Black key created by trusted + * descriptor + */ + TAG_TYPE_BLACK_KEY_ECB_TRUSTED, + /** @TAG_TYPE_BLACK_KEY_CCM: Black key encrypted with CCM */ + TAG_TYPE_BLACK_KEY_CCM, + /** + * @TAG_TYPE_BLACK_KEY_CCM_TRUSTED: CCM Black key created by trusted + * descriptor + */ + TAG_TYPE_BLACK_KEY_CCM_TRUSTED, + + /** @NB_TAG_TYPE: Number of type of tag */ + NB_TAG_TYPE, +}; + +/** + * struct conf_header - Common struture holding the type of data and the magic + * number + * @_magic_number : A magic number to identify the structure + * @type : The type of data contained + */ +struct conf_header { + u32 _magic_number; + u32 type; +}; + +/** + * struct blackey_conf - Configuration for a black key + * @load : Load parameter for CAAM + * @real_len : Length of the key before encryption + */ +struct blackey_conf { + u32 load; + u32 real_len; +}; + +/** + * struct tag_object_conf - Common structure which is the tag applied to data + * @header : Part of the data initialized with common function + * :c:func:`init_tag_object_header` + * @conf : Configuration data about the object tagged, initialized with + * specific function + */ +struct tag_object_conf { + struct conf_header header; + union { + struct blackey_conf bk_conf; + } conf; +}; + +bool is_bk_conf(const struct tag_object_conf *tag_obj_conf); + +bool is_valid_tag_object_conf(const struct tag_object_conf *tag_obj_conf); + +void init_tag_object_header(struct conf_header *conf_header, + enum tag_type type); + +int get_tag_object_conf(const void *buffer, size_t buffer_size, + struct tag_object_conf **tag_obj_conf); + +int set_tag_object_conf(const struct tag_object_conf *tag_obj_conf, + void *buffer, size_t obj_size, u32 *to_size); + +size_t get_tag_object_overhead(void); + +void get_blackey_conf(const struct blackey_conf *blackey_conf, + u32 *real_len, u32 *load_param); + +void init_blackey_conf(struct blackey_conf *blackey_conf, + size_t len, bool ccm, bool tk); + +int get_tagged_data(const void *buffer, size_t buffer_size, + const void **data, u32 *data_size); + +#endif /* _TAG_OBJECT_H_ */ diff --git a/drivers/crypto/mxs-dcp.c b/drivers/crypto/mxs-dcp.c index f8a48a84df2ab3..871a8b028c4969 100644 --- a/drivers/crypto/mxs-dcp.c +++ b/drivers/crypto/mxs-dcp.c @@ -299,6 +299,9 @@ static int mxs_dcp_aes_block_crypt(struct crypto_async_request *arq) int init = 0; bool limit_hit = false; + if (!req->nbytes) + return 0; + actx->fill = 0; /* Copy the key from the temporary location. */ diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c index eba7e3fe769cfd..7c23fc36cfe6b2 100644 --- a/drivers/dma-buf/dma-buf.c +++ b/drivers/dma-buf/dma-buf.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -359,6 +360,36 @@ static long dma_buf_ioctl(struct file *file, dmabuf = file->private_data; switch (cmd) { + case DMA_BUF_IOCTL_PHYS: { + struct dma_buf_attachment *attachment = NULL; + struct sg_table *sgt = NULL; + unsigned long phys = 0; + struct device dev; + + if (!dmabuf || IS_ERR(dmabuf)) { + return -EFAULT; + } + memset(&dev, 0, sizeof(dev)); + device_initialize(&dev); + dev.coherent_dma_mask = DMA_BIT_MASK(64); + dev.dma_mask = &dev.coherent_dma_mask; + arch_setup_dma_ops(&dev, 0, 0, NULL, false); + attachment = dma_buf_attach(dmabuf, &dev); + if (!attachment || IS_ERR(attachment)) { + return -EFAULT; + } + + sgt = dma_buf_map_attachment(attachment, DMA_BIDIRECTIONAL); + if (sgt && !IS_ERR(sgt)) { + phys = sg_dma_address(sgt->sgl); + dma_buf_unmap_attachment(attachment, sgt, + DMA_BIDIRECTIONAL); + } + dma_buf_detach(dmabuf, attachment); + if (copy_to_user((void __user *) arg, &phys, sizeof(phys))) + return -EFAULT; + return 0; + } case DMA_BUF_IOCTL_SYNC: if (copy_from_user(&sync, (void __user *) arg, sizeof(sync))) return -EFAULT; diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 7af874b69ffb9e..5be6f69d0f47b6 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -131,6 +131,24 @@ config COH901318 help Enable support for ST-Ericsson COH 901 318 DMA. +config CRYPTO_DEV_FSL_CAAM_DMA + tristate "CAAM DMA engine support" + depends on CRYPTO_DEV_FSL_CAAM_JR + default n + select DMA_ENGINE + select ASYNC_CORE + select ASYNC_TX_ENABLE_CHANNEL_SWITCH + help + Selecting this will offload the DMA operations for users of + the scatter gather memcopy API to the CAAM via job rings. The + CAAM is a hardware module that provides hardware acceleration to + cryptographic operations. It has a built-in DMA controller that can + be programmed to read/write cryptographic data. This module defines + a DMA driver that uses the DMA capabilities of the CAAM. + + To compile this as a module, choose M here: the module + will be called caam_dma. + config DMA_BCM2835 tristate "BCM2835 DMA engine support" depends on ARCH_BCM2835 @@ -227,6 +245,17 @@ config FSL_QDMA or dequeuing DMA jobs from, different work queues. This module can be found on NXP Layerscape SoCs. The qdma driver only work on SoCs with a DPAA hardware block. +config FSL_EDMA_V3 + tristate "Freescale eDMA v3 engine support" + depends on OF + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + help + Support the Freescale eDMA v3 engine with programmable channel. + This driver is based on FSL_EDMA but big changes come such as + different interrupt for different channel, different register + scope for different channel. + This module can be found on Freescale i.MX8QM. config FSL_RAID tristate "Freescale RAID engine Support" @@ -409,6 +438,8 @@ config MXS_DMA Support the MXS DMA engine. This engine including APBH-DMA and APBX-DMA is integrated into some Freescale chips. +source "drivers/dma/pxp/Kconfig" + config MX3_IPU bool "MX3x Image Processing Unit support" depends on ARCH_MXC @@ -651,7 +682,6 @@ config ZX_DMA help Support the DMA engine for ZTE ZX family platform devices. - # driver files source "drivers/dma/bestcomm/Kconfig" @@ -669,6 +699,8 @@ source "drivers/dma/sh/Kconfig" source "drivers/dma/ti/Kconfig" +source "drivers/dma/fsl-dpaa2-qdma/Kconfig" + # clients comment "DMA Clients" depends on DMA_ENGINE diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index f5ce8665e944e2..6c977c171706fb 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_DW_EDMA) += dw-edma/ obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o obj-$(CONFIG_FSL_DMA) += fsldma.o obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o +obj-$(CONFIG_FSL_EDMA_V3) += fsl-edma-v3.o obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o obj-$(CONFIG_FSL_QDMA) += fsl-qdma.o obj-$(CONFIG_FSL_RAID) += fsl_raid.o @@ -59,6 +60,8 @@ obj-$(CONFIG_PCH_DMA) += pch_dma.o obj-$(CONFIG_PL330_DMA) += pl330.o obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/ obj-$(CONFIG_PXA_DMA) += pxa_dma.o +obj-$(CONFIG_MXC_PXP_V2) += pxp/ +obj-$(CONFIG_MXC_PXP_V3) += pxp/ obj-$(CONFIG_RENESAS_DMA) += sh/ obj-$(CONFIG_SIRF_DMA) += sirf-dma.o obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o @@ -75,6 +78,8 @@ obj-$(CONFIG_UNIPHIER_MDMAC) += uniphier-mdmac.o obj-$(CONFIG_XGENE_DMA) += xgene-dma.o obj-$(CONFIG_ZX_DMA) += zx_dma.o obj-$(CONFIG_ST_FDMA) += st_fdma.o +obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_DMA) += caam_dma.o +obj-$(CONFIG_FSL_DPAA2_QDMA) += fsl-dpaa2-qdma/ obj-y += mediatek/ obj-y += qcom/ diff --git a/drivers/dma/caam_dma.c b/drivers/dma/caam_dma.c new file mode 100644 index 00000000000000..2cd47c9b3ec557 --- /dev/null +++ b/drivers/dma/caam_dma.c @@ -0,0 +1,463 @@ +/* + * caam support for SG DMA + * + * Copyright 2016 Freescale Semiconductor, Inc + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the names of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +#include "dmaengine.h" + +#include "../crypto/caam/regs.h" +#include "../crypto/caam/jr.h" +#include "../crypto/caam/error.h" +#include "../crypto/caam/desc_constr.h" + +#define DESC_DMA_MEMCPY_LEN ((CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN_MIN) / \ + CAAM_CMD_SZ) + +/* + * This is max chunk size of a DMA transfer. If a buffer is larger than this + * value it is internally broken into chunks of max CAAM_DMA_CHUNK_SIZE bytes + * and for each chunk a DMA transfer request is issued. + * This value is the largest number on 16 bits that is a multiple of 256 bytes + * (the largest configurable CAAM DMA burst size). + */ +#define CAAM_DMA_CHUNK_SIZE 65280 + +struct caam_dma_sh_desc { + u32 desc[DESC_DMA_MEMCPY_LEN] ____cacheline_aligned; + dma_addr_t desc_dma; +}; + +/* caam dma extended descriptor */ +struct caam_dma_edesc { + struct dma_async_tx_descriptor async_tx; + struct list_head node; + struct caam_dma_ctx *ctx; + dma_addr_t src_dma; + dma_addr_t dst_dma; + unsigned int src_len; + unsigned int dst_len; + u32 jd[] ____cacheline_aligned; +}; + +/* + * caam_dma_ctx - per jr/channel context + * @chan: dma channel used by async_tx API + * @node: list_head used to attach to the global dma_ctx_list + * @jrdev: Job Ring device + * @pending_q: queue of pending (submitted, but not enqueued) jobs + * @done_not_acked: jobs that have been completed by jr, but maybe not acked + * @edesc_lock: protects extended descriptor + */ +struct caam_dma_ctx { + struct dma_chan chan; + struct list_head node; + struct device *jrdev; + struct list_head pending_q; + struct list_head done_not_acked; + spinlock_t edesc_lock; +}; + +static struct dma_device *dma_dev; +static struct caam_dma_sh_desc *dma_sh_desc; +static LIST_HEAD(dma_ctx_list); + +static dma_cookie_t caam_dma_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct caam_dma_edesc *edesc = NULL; + struct caam_dma_ctx *ctx = NULL; + dma_cookie_t cookie; + + edesc = container_of(tx, struct caam_dma_edesc, async_tx); + ctx = container_of(tx->chan, struct caam_dma_ctx, chan); + + spin_lock_bh(&ctx->edesc_lock); + + cookie = dma_cookie_assign(tx); + list_add_tail(&edesc->node, &ctx->pending_q); + + spin_unlock_bh(&ctx->edesc_lock); + + return cookie; +} + +static void caam_jr_chan_free_edesc(struct caam_dma_edesc *edesc) +{ + struct caam_dma_ctx *ctx = edesc->ctx; + struct caam_dma_edesc *_edesc = NULL; + + spin_lock_bh(&ctx->edesc_lock); + + list_add_tail(&edesc->node, &ctx->done_not_acked); + list_for_each_entry_safe(edesc, _edesc, &ctx->done_not_acked, node) { + if (async_tx_test_ack(&edesc->async_tx)) { + list_del(&edesc->node); + kfree(edesc); + } + } + + spin_unlock_bh(&ctx->edesc_lock); +} + +static void caam_dma_done(struct device *dev, u32 *hwdesc, u32 err, + void *context) +{ + struct caam_dma_edesc *edesc = context; + struct caam_dma_ctx *ctx = edesc->ctx; + dma_async_tx_callback callback; + void *callback_param; + + if (err) + caam_jr_strstatus(ctx->jrdev, err); + + dma_run_dependencies(&edesc->async_tx); + + spin_lock_bh(&ctx->edesc_lock); + dma_cookie_complete(&edesc->async_tx); + spin_unlock_bh(&ctx->edesc_lock); + + callback = edesc->async_tx.callback; + callback_param = edesc->async_tx.callback_param; + + dma_descriptor_unmap(&edesc->async_tx); + + caam_jr_chan_free_edesc(edesc); + + if (callback) + callback(callback_param); +} + +static void caam_dma_memcpy_init_job_desc(struct caam_dma_edesc *edesc) +{ + u32 *jd = edesc->jd; + u32 *sh_desc = dma_sh_desc->desc; + dma_addr_t desc_dma = dma_sh_desc->desc_dma; + + /* init the job descriptor */ + init_job_desc_shared(jd, desc_dma, desc_len(sh_desc), HDR_REVERSE); + + /* set SEQIN PTR */ + append_seq_in_ptr(jd, edesc->src_dma, edesc->src_len, 0); + + /* set SEQOUT PTR */ + append_seq_out_ptr(jd, edesc->dst_dma, edesc->dst_len, 0); + + print_hex_dump_debug("caam dma desc@" __stringify(__LINE__) ": ", + DUMP_PREFIX_ADDRESS, 16, 4, jd, desc_bytes(jd), 1); +} + +static struct dma_async_tx_descriptor * +caam_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst, dma_addr_t src, + size_t len, unsigned long flags) +{ + struct caam_dma_edesc *edesc; + struct caam_dma_ctx *ctx = container_of(chan, struct caam_dma_ctx, + chan); + + edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN, GFP_DMA | GFP_NOWAIT); + if (!edesc) + return ERR_PTR(-ENOMEM); + + dma_async_tx_descriptor_init(&edesc->async_tx, chan); + edesc->async_tx.tx_submit = caam_dma_tx_submit; + edesc->async_tx.flags = flags; + edesc->async_tx.cookie = -EBUSY; + + edesc->src_dma = src; + edesc->src_len = len; + edesc->dst_dma = dst; + edesc->dst_len = len; + edesc->ctx = ctx; + + caam_dma_memcpy_init_job_desc(edesc); + + return &edesc->async_tx; +} + +/* This function can be called in an interrupt context */ +static void caam_dma_issue_pending(struct dma_chan *chan) +{ + struct caam_dma_ctx *ctx = container_of(chan, struct caam_dma_ctx, + chan); + struct caam_dma_edesc *edesc, *_edesc; + + spin_lock_bh(&ctx->edesc_lock); + list_for_each_entry_safe(edesc, _edesc, &ctx->pending_q, node) { + int ret = caam_jr_enqueue(ctx->jrdev, edesc->jd, + caam_dma_done, edesc); + if (ret != -EINPROGRESS) + break; + list_del(&edesc->node); + } + spin_unlock_bh(&ctx->edesc_lock); +} + +static void caam_dma_free_chan_resources(struct dma_chan *chan) +{ + struct caam_dma_ctx *ctx = container_of(chan, struct caam_dma_ctx, + chan); + struct caam_dma_edesc *edesc, *_edesc; + + spin_lock_bh(&ctx->edesc_lock); + list_for_each_entry_safe(edesc, _edesc, &ctx->pending_q, node) { + list_del(&edesc->node); + kfree(edesc); + } + list_for_each_entry_safe(edesc, _edesc, &ctx->done_not_acked, node) { + list_del(&edesc->node); + kfree(edesc); + } + spin_unlock_bh(&ctx->edesc_lock); +} + +static int caam_dma_jr_chan_bind(void) +{ + struct device *jrdev; + struct caam_dma_ctx *ctx; + int bonds = 0; + int i; + + for (i = 0; i < caam_jr_driver_probed(); i++) { + jrdev = caam_jridx_alloc(i); + if (IS_ERR(jrdev)) { + pr_err("job ring device %d allocation failed\n", i); + continue; + } + + ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); + if (!ctx) { + caam_jr_free(jrdev); + continue; + } + + ctx->chan.device = dma_dev; + ctx->chan.private = ctx; + + ctx->jrdev = jrdev; + + INIT_LIST_HEAD(&ctx->pending_q); + INIT_LIST_HEAD(&ctx->done_not_acked); + INIT_LIST_HEAD(&ctx->node); + spin_lock_init(&ctx->edesc_lock); + + dma_cookie_init(&ctx->chan); + + /* add the context of this channel to the context list */ + list_add_tail(&ctx->node, &dma_ctx_list); + + /* add this channel to the device chan list */ + list_add_tail(&ctx->chan.device_node, &dma_dev->channels); + + bonds++; + } + + return bonds; +} + +static inline void caam_jr_dma_free(struct dma_chan *chan) +{ + struct caam_dma_ctx *ctx = container_of(chan, struct caam_dma_ctx, + chan); + + list_del(&ctx->node); + list_del(&chan->device_node); + caam_jr_free(ctx->jrdev); + kfree(ctx); +} + +static void set_caam_dma_desc(u32 *desc) +{ + u32 *jmp_cmd; + + /* dma shared descriptor */ + init_sh_desc(desc, HDR_SHARE_NEVER | (1 << HDR_START_IDX_SHIFT)); + + /* REG1 = CAAM_DMA_CHUNK_SIZE */ + append_math_add_imm_u32(desc, REG1, ZERO, IMM, CAAM_DMA_CHUNK_SIZE); + + /* REG0 = SEQINLEN - CAAM_DMA_CHUNK_SIZE */ + append_math_sub_imm_u32(desc, REG0, SEQINLEN, IMM, CAAM_DMA_CHUNK_SIZE); + + /* + * if (REG0 > 0) + * jmp to LABEL1 + */ + jmp_cmd = append_jump(desc, JUMP_TEST_INVALL | JUMP_COND_MATH_N | + JUMP_COND_MATH_Z); + + /* REG1 = SEQINLEN */ + append_math_sub(desc, REG1, SEQINLEN, ZERO, CAAM_CMD_SZ); + + /* LABEL1 */ + set_jump_tgt_here(desc, jmp_cmd); + + /* VARSEQINLEN = REG1 */ + append_math_add(desc, VARSEQINLEN, REG1, ZERO, CAAM_CMD_SZ); + + /* VARSEQOUTLEN = REG1 */ + append_math_add(desc, VARSEQOUTLEN, REG1, ZERO, CAAM_CMD_SZ); + + /* do FIFO STORE */ + append_seq_fifo_store(desc, 0, FIFOST_TYPE_METADATA | LDST_VLF); + + /* do FIFO LOAD */ + append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | + FIFOLD_TYPE_IFIFO | LDST_VLF); + + /* + * if (REG0 > 0) + * jmp 0xF8 (after shared desc header) + */ + append_jump(desc, JUMP_TEST_INVALL | JUMP_COND_MATH_N | + JUMP_COND_MATH_Z | 0xF8); + + print_hex_dump_debug("caam dma shdesc@" __stringify(__LINE__) ": ", + DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), + 1); +} + +static int caam_dma_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device *ctrldev = dev->parent; + struct dma_chan *chan, *_chan; + u32 *sh_desc; + int err = -ENOMEM; + int bonds; + + if (!caam_jr_driver_probed()) { + dev_info(dev, "Defer probing after JR driver probing\n"); + return -EPROBE_DEFER; + } + + dma_dev = kzalloc(sizeof(*dma_dev), GFP_KERNEL); + if (!dma_dev) + return -ENOMEM; + + dma_sh_desc = kzalloc(sizeof(*dma_sh_desc), GFP_KERNEL | GFP_DMA); + if (!dma_sh_desc) + goto desc_err; + + sh_desc = dma_sh_desc->desc; + set_caam_dma_desc(sh_desc); + dma_sh_desc->desc_dma = dma_map_single(ctrldev, sh_desc, + desc_bytes(sh_desc), + DMA_TO_DEVICE); + if (dma_mapping_error(ctrldev, dma_sh_desc->desc_dma)) { + dev_err(dev, "unable to map dma descriptor\n"); + goto map_err; + } + + INIT_LIST_HEAD(&dma_dev->channels); + + bonds = caam_dma_jr_chan_bind(); + if (!bonds) { + err = -ENODEV; + goto jr_bind_err; + } + + dma_dev->dev = dev; + dma_dev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; + dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask); + dma_cap_set(DMA_PRIVATE, dma_dev->cap_mask); + dma_dev->device_tx_status = dma_cookie_status; + dma_dev->device_issue_pending = caam_dma_issue_pending; + dma_dev->device_prep_dma_memcpy = caam_dma_prep_memcpy; + dma_dev->device_free_chan_resources = caam_dma_free_chan_resources; + + err = dma_async_device_register(dma_dev); + if (err) { + dev_err(dev, "Failed to register CAAM DMA engine\n"); + goto jr_bind_err; + } + + dev_info(dev, "caam dma support with %d job rings\n", bonds); + + return err; + +jr_bind_err: + list_for_each_entry_safe(chan, _chan, &dma_dev->channels, device_node) + caam_jr_dma_free(chan); + + dma_unmap_single(ctrldev, dma_sh_desc->desc_dma, desc_bytes(sh_desc), + DMA_TO_DEVICE); +map_err: + kfree(dma_sh_desc); +desc_err: + kfree(dma_dev); + return err; +} + +static int caam_dma_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device *ctrldev = dev->parent; + struct caam_dma_ctx *ctx, *_ctx; + + dma_async_device_unregister(dma_dev); + + list_for_each_entry_safe(ctx, _ctx, &dma_ctx_list, node) { + list_del(&ctx->node); + caam_jr_free(ctx->jrdev); + kfree(ctx); + } + + dma_unmap_single(ctrldev, dma_sh_desc->desc_dma, + desc_bytes(dma_sh_desc->desc), DMA_TO_DEVICE); + + kfree(dma_sh_desc); + kfree(dma_dev); + + dev_info(dev, "caam dma support disabled\n"); + return 0; +} + +static struct platform_driver caam_dma_driver = { + .driver = { + .name = "caam-dma", + }, + .probe = caam_dma_probe, + .remove = caam_dma_remove, +}; +module_platform_driver(caam_dma_driver); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_DESCRIPTION("NXP CAAM support for DMA engine"); +MODULE_AUTHOR("NXP Semiconductors"); +MODULE_ALIAS("platform:caam-dma"); diff --git a/drivers/dma/fsl-dpaa2-qdma/Kconfig b/drivers/dma/fsl-dpaa2-qdma/Kconfig new file mode 100644 index 00000000000000..258ed6be934d37 --- /dev/null +++ b/drivers/dma/fsl-dpaa2-qdma/Kconfig @@ -0,0 +1,9 @@ +menuconfig FSL_DPAA2_QDMA + tristate "NXP DPAA2 QDMA" + depends on ARM64 + depends on FSL_MC_BUS && FSL_MC_DPIO + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + help + NXP Data Path Acceleration Architecture 2 QDMA driver, + using the NXP MC bus driver. diff --git a/drivers/dma/fsl-dpaa2-qdma/Makefile b/drivers/dma/fsl-dpaa2-qdma/Makefile new file mode 100644 index 00000000000000..c1d0226f2bd77b --- /dev/null +++ b/drivers/dma/fsl-dpaa2-qdma/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +# Makefile for the NXP DPAA2 qDMA controllers +obj-$(CONFIG_FSL_DPAA2_QDMA) += dpaa2-qdma.o dpdmai.o diff --git a/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c new file mode 100644 index 00000000000000..c70a7965f140d8 --- /dev/null +++ b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c @@ -0,0 +1,825 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright 2019 NXP + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../virt-dma.h" +#include "dpdmai.h" +#include "dpaa2-qdma.h" + +static bool smmu_disable = true; + +static struct dpaa2_qdma_chan *to_dpaa2_qdma_chan(struct dma_chan *chan) +{ + return container_of(chan, struct dpaa2_qdma_chan, vchan.chan); +} + +static struct dpaa2_qdma_comp *to_fsl_qdma_comp(struct virt_dma_desc *vd) +{ + return container_of(vd, struct dpaa2_qdma_comp, vdesc); +} + +static int dpaa2_qdma_alloc_chan_resources(struct dma_chan *chan) +{ + struct dpaa2_qdma_chan *dpaa2_chan = to_dpaa2_qdma_chan(chan); + struct dpaa2_qdma_engine *dpaa2_qdma = dpaa2_chan->qdma; + struct device *dev = &dpaa2_qdma->priv->dpdmai_dev->dev; + + dpaa2_chan->fd_pool = dma_pool_create("fd_pool", dev, + sizeof(struct dpaa2_fd), + sizeof(struct dpaa2_fd), 0); + if (!dpaa2_chan->fd_pool) + goto err; + + dpaa2_chan->fl_pool = dma_pool_create("fl_pool", dev, + sizeof(struct dpaa2_fl_entry), + sizeof(struct dpaa2_fl_entry), 0); + if (!dpaa2_chan->fl_pool) + goto err_fd; + + dpaa2_chan->sdd_pool = + dma_pool_create("sdd_pool", dev, + sizeof(struct dpaa2_qdma_sd_d), + sizeof(struct dpaa2_qdma_sd_d), 0); + if (!dpaa2_chan->sdd_pool) + goto err_fl; + + return dpaa2_qdma->desc_allocated++; +err_fl: + dma_pool_destroy(dpaa2_chan->fl_pool); +err_fd: + dma_pool_destroy(dpaa2_chan->fd_pool); +err: + return -ENOMEM; +} + +static void dpaa2_qdma_free_chan_resources(struct dma_chan *chan) +{ + struct dpaa2_qdma_chan *dpaa2_chan = to_dpaa2_qdma_chan(chan); + struct dpaa2_qdma_engine *dpaa2_qdma = dpaa2_chan->qdma; + unsigned long flags; + + LIST_HEAD(head); + + spin_lock_irqsave(&dpaa2_chan->vchan.lock, flags); + vchan_get_all_descriptors(&dpaa2_chan->vchan, &head); + spin_unlock_irqrestore(&dpaa2_chan->vchan.lock, flags); + + vchan_dma_desc_free_list(&dpaa2_chan->vchan, &head); + + dpaa2_dpdmai_free_comp(dpaa2_chan, &dpaa2_chan->comp_used); + dpaa2_dpdmai_free_comp(dpaa2_chan, &dpaa2_chan->comp_free); + + dma_pool_destroy(dpaa2_chan->fd_pool); + dma_pool_destroy(dpaa2_chan->fl_pool); + dma_pool_destroy(dpaa2_chan->sdd_pool); + dpaa2_qdma->desc_allocated--; +} + +/* + * Request a command descriptor for enqueue. + */ +static struct dpaa2_qdma_comp * +dpaa2_qdma_request_desc(struct dpaa2_qdma_chan *dpaa2_chan) +{ + struct dpaa2_qdma_priv *qdma_priv = dpaa2_chan->qdma->priv; + struct device *dev = &qdma_priv->dpdmai_dev->dev; + struct dpaa2_qdma_comp *comp_temp = NULL; + unsigned long flags; + + spin_lock_irqsave(&dpaa2_chan->queue_lock, flags); + if (list_empty(&dpaa2_chan->comp_free)) { + spin_unlock_irqrestore(&dpaa2_chan->queue_lock, flags); + comp_temp = kzalloc(sizeof(*comp_temp), GFP_NOWAIT); + if (!comp_temp) + goto err; + comp_temp->fd_virt_addr = + dma_pool_alloc(dpaa2_chan->fd_pool, GFP_NOWAIT, + &comp_temp->fd_bus_addr); + if (!comp_temp->fd_virt_addr) + goto err_comp; + + comp_temp->fl_virt_addr = + dma_pool_alloc(dpaa2_chan->fl_pool, GFP_NOWAIT, + &comp_temp->fl_bus_addr); + if (!comp_temp->fl_virt_addr) + goto err_fd_virt; + + comp_temp->desc_virt_addr = + dma_pool_alloc(dpaa2_chan->sdd_pool, GFP_NOWAIT, + &comp_temp->desc_bus_addr); + if (!comp_temp->desc_virt_addr) + goto err_fl_virt; + + comp_temp->qchan = dpaa2_chan; + return comp_temp; + } + + comp_temp = list_first_entry(&dpaa2_chan->comp_free, + struct dpaa2_qdma_comp, list); + list_del(&comp_temp->list); + spin_unlock_irqrestore(&dpaa2_chan->queue_lock, flags); + + comp_temp->qchan = dpaa2_chan; + + return comp_temp; + +err_fl_virt: + dma_pool_free(dpaa2_chan->fl_pool, + comp_temp->fl_virt_addr, + comp_temp->fl_bus_addr); +err_fd_virt: + dma_pool_free(dpaa2_chan->fd_pool, + comp_temp->fd_virt_addr, + comp_temp->fd_bus_addr); +err_comp: + kfree(comp_temp); +err: + dev_err(dev, "Failed to request descriptor\n"); + return NULL; +} + +static void +dpaa2_qdma_populate_fd(u32 format, struct dpaa2_qdma_comp *dpaa2_comp) +{ + struct dpaa2_fd *fd; + + fd = dpaa2_comp->fd_virt_addr; + memset(fd, 0, sizeof(struct dpaa2_fd)); + + /* fd populated */ + dpaa2_fd_set_addr(fd, dpaa2_comp->fl_bus_addr); + + /* + * Bypass memory translation, Frame list format, short length disable + * we need to disable BMT if fsl-mc use iova addr + */ + if (smmu_disable) + dpaa2_fd_set_bpid(fd, QMAN_FD_BMT_ENABLE); + dpaa2_fd_set_format(fd, QMAN_FD_FMT_ENABLE | QMAN_FD_SL_DISABLE); + + dpaa2_fd_set_frc(fd, format | QDMA_SER_CTX); +} + +/* first frame list for descriptor buffer */ +static void +dpaa2_qdma_populate_first_framel(struct dpaa2_fl_entry *f_list, + struct dpaa2_qdma_comp *dpaa2_comp, + bool wrt_changed) +{ + struct dpaa2_qdma_sd_d *sdd; + + sdd = dpaa2_comp->desc_virt_addr; + memset(sdd, 0, 2 * (sizeof(*sdd))); + + /* source descriptor CMD */ + sdd->cmd = cpu_to_le32(QDMA_SD_CMD_RDTTYPE_COHERENT); + sdd++; + + /* dest descriptor CMD */ + if (wrt_changed) + sdd->cmd = cpu_to_le32(LX2160_QDMA_DD_CMD_WRTTYPE_COHERENT); + else + sdd->cmd = cpu_to_le32(QDMA_DD_CMD_WRTTYPE_COHERENT); + + memset(f_list, 0, sizeof(struct dpaa2_fl_entry)); + + /* first frame list to source descriptor */ + dpaa2_fl_set_addr(f_list, dpaa2_comp->desc_bus_addr); + dpaa2_fl_set_len(f_list, 0x20); + dpaa2_fl_set_format(f_list, QDMA_FL_FMT_SBF | QDMA_FL_SL_LONG); + + /* bypass memory translation */ + if (smmu_disable) + f_list->bpid = cpu_to_le16(QDMA_FL_BMT_ENABLE); +} + +/* source and destination frame list */ +static void +dpaa2_qdma_populate_frames(struct dpaa2_fl_entry *f_list, + dma_addr_t dst, dma_addr_t src, + size_t len, uint8_t fmt) +{ + /* source frame list to source buffer */ + memset(f_list, 0, sizeof(struct dpaa2_fl_entry)); + + dpaa2_fl_set_addr(f_list, src); + dpaa2_fl_set_len(f_list, len); + + /* single buffer frame or scatter gather frame */ + dpaa2_fl_set_format(f_list, (fmt | QDMA_FL_SL_LONG)); + + /* bypass memory translation */ + if (smmu_disable) + f_list->bpid = cpu_to_le16(QDMA_FL_BMT_ENABLE); + + f_list++; + + /* destination frame list to destination buffer */ + memset(f_list, 0, sizeof(struct dpaa2_fl_entry)); + + dpaa2_fl_set_addr(f_list, dst); + dpaa2_fl_set_len(f_list, len); + dpaa2_fl_set_format(f_list, (fmt | QDMA_FL_SL_LONG)); + /* single buffer frame or scatter gather frame */ + dpaa2_fl_set_final(f_list, QDMA_FL_F); + /* bypass memory translation */ + if (smmu_disable) + f_list->bpid = cpu_to_le16(QDMA_FL_BMT_ENABLE); +} + +static struct dma_async_tx_descriptor +*dpaa2_qdma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst, + dma_addr_t src, size_t len, ulong flags) +{ + struct dpaa2_qdma_chan *dpaa2_chan = to_dpaa2_qdma_chan(chan); + struct dpaa2_qdma_engine *dpaa2_qdma; + struct dpaa2_qdma_comp *dpaa2_comp; + struct dpaa2_fl_entry *f_list; + bool wrt_changed; + + dpaa2_qdma = dpaa2_chan->qdma; + dpaa2_comp = dpaa2_qdma_request_desc(dpaa2_chan); + if (!dpaa2_comp) + return NULL; + + wrt_changed = (bool)dpaa2_qdma->qdma_wrtype_fixup; + + /* populate Frame descriptor */ + dpaa2_qdma_populate_fd(QDMA_FD_LONG_FORMAT, dpaa2_comp); + + f_list = dpaa2_comp->fl_virt_addr; + + /* first frame list for descriptor buffer (logn format) */ + dpaa2_qdma_populate_first_framel(f_list, dpaa2_comp, wrt_changed); + + f_list++; + + dpaa2_qdma_populate_frames(f_list, dst, src, len, QDMA_FL_FMT_SBF); + + return vchan_tx_prep(&dpaa2_chan->vchan, &dpaa2_comp->vdesc, flags); +} + +static void dpaa2_qdma_issue_pending(struct dma_chan *chan) +{ + struct dpaa2_qdma_chan *dpaa2_chan = to_dpaa2_qdma_chan(chan); + struct dpaa2_qdma_comp *dpaa2_comp; + struct virt_dma_desc *vdesc; + struct dpaa2_fd *fd; + unsigned long flags; + int err; + + spin_lock_irqsave(&dpaa2_chan->queue_lock, flags); + spin_lock(&dpaa2_chan->vchan.lock); + if (vchan_issue_pending(&dpaa2_chan->vchan)) { + vdesc = vchan_next_desc(&dpaa2_chan->vchan); + if (!vdesc) + goto err_enqueue; + dpaa2_comp = to_fsl_qdma_comp(vdesc); + + fd = dpaa2_comp->fd_virt_addr; + + list_del(&vdesc->node); + list_add_tail(&dpaa2_comp->list, &dpaa2_chan->comp_used); + + err = dpaa2_io_service_enqueue_fq(NULL, dpaa2_chan->fqid, fd); + if (err) { + list_del(&dpaa2_comp->list); + list_add_tail(&dpaa2_comp->list, + &dpaa2_chan->comp_free); + } + } +err_enqueue: + spin_unlock(&dpaa2_chan->vchan.lock); + spin_unlock_irqrestore(&dpaa2_chan->queue_lock, flags); +} + +static int __cold dpaa2_qdma_setup(struct fsl_mc_device *ls_dev) +{ + struct dpaa2_qdma_priv_per_prio *ppriv; + struct device *dev = &ls_dev->dev; + struct dpaa2_qdma_priv *priv; + u8 prio_def = DPDMAI_PRIO_NUM; + int err = -EINVAL; + int i; + + priv = dev_get_drvdata(dev); + + priv->dev = dev; + priv->dpqdma_id = ls_dev->obj_desc.id; + + /* Get the handle for the DPDMAI this interface is associate with */ + err = dpdmai_open(priv->mc_io, 0, priv->dpqdma_id, &ls_dev->mc_handle); + if (err) { + dev_err(dev, "dpdmai_open() failed\n"); + return err; + } + + dev_dbg(dev, "Opened dpdmai object successfully\n"); + + err = dpdmai_get_attributes(priv->mc_io, 0, ls_dev->mc_handle, + &priv->dpdmai_attr); + if (err) { + dev_err(dev, "dpdmai_get_attributes() failed\n"); + goto exit; + } + + if (priv->dpdmai_attr.version.major > DPDMAI_VER_MAJOR) { + dev_err(dev, "DPDMAI major version mismatch\n" + "Found %u.%u, supported version is %u.%u\n", + priv->dpdmai_attr.version.major, + priv->dpdmai_attr.version.minor, + DPDMAI_VER_MAJOR, DPDMAI_VER_MINOR); + goto exit; + } + + if (priv->dpdmai_attr.version.minor > DPDMAI_VER_MINOR) { + dev_err(dev, "DPDMAI minor version mismatch\n" + "Found %u.%u, supported version is %u.%u\n", + priv->dpdmai_attr.version.major, + priv->dpdmai_attr.version.minor, + DPDMAI_VER_MAJOR, DPDMAI_VER_MINOR); + goto exit; + } + + priv->num_pairs = min(priv->dpdmai_attr.num_of_priorities, prio_def); + ppriv = kcalloc(priv->num_pairs, sizeof(*ppriv), GFP_KERNEL); + if (!ppriv) { + err = -ENOMEM; + goto exit; + } + priv->ppriv = ppriv; + + for (i = 0; i < priv->num_pairs; i++) { + err = dpdmai_get_rx_queue(priv->mc_io, 0, ls_dev->mc_handle, + i, &priv->rx_queue_attr[i]); + if (err) { + dev_err(dev, "dpdmai_get_rx_queue() failed\n"); + goto exit; + } + ppriv->rsp_fqid = priv->rx_queue_attr[i].fqid; + + err = dpdmai_get_tx_queue(priv->mc_io, 0, ls_dev->mc_handle, + i, &priv->tx_fqid[i]); + if (err) { + dev_err(dev, "dpdmai_get_tx_queue() failed\n"); + goto exit; + } + ppriv->req_fqid = priv->tx_fqid[i]; + ppriv->prio = i; + ppriv->priv = priv; + ppriv++; + } + + return 0; +exit: + dpdmai_close(priv->mc_io, 0, ls_dev->mc_handle); + return err; +} + +static void dpaa2_qdma_fqdan_cb(struct dpaa2_io_notification_ctx *ctx) +{ + struct dpaa2_qdma_priv_per_prio *ppriv = container_of(ctx, + struct dpaa2_qdma_priv_per_prio, nctx); + struct dpaa2_qdma_comp *dpaa2_comp, *_comp_tmp; + struct dpaa2_qdma_priv *priv = ppriv->priv; + u32 n_chans = priv->dpaa2_qdma->n_chans; + struct dpaa2_qdma_chan *qchan; + const struct dpaa2_fd *fd_eq; + const struct dpaa2_fd *fd; + struct dpaa2_dq *dq; + int is_last = 0; + int found; + u8 status; + int err; + int i; + + do { + err = dpaa2_io_service_pull_fq(NULL, ppriv->rsp_fqid, + ppriv->store); + } while (err); + + while (!is_last) { + do { + dq = dpaa2_io_store_next(ppriv->store, &is_last); + } while (!is_last && !dq); + if (!dq) { + dev_err(priv->dev, "FQID returned no valid frames!\n"); + continue; + } + + /* obtain FD and process the error */ + fd = dpaa2_dq_fd(dq); + + status = dpaa2_fd_get_ctrl(fd) & 0xff; + if (status) + dev_err(priv->dev, "FD error occurred\n"); + found = 0; + for (i = 0; i < n_chans; i++) { + qchan = &priv->dpaa2_qdma->chans[i]; + spin_lock(&qchan->queue_lock); + if (list_empty(&qchan->comp_used)) { + spin_unlock(&qchan->queue_lock); + continue; + } + list_for_each_entry_safe(dpaa2_comp, _comp_tmp, + &qchan->comp_used, list) { + fd_eq = dpaa2_comp->fd_virt_addr; + + if (le64_to_cpu(fd_eq->simple.addr) == + le64_to_cpu(fd->simple.addr)) { + spin_lock(&qchan->vchan.lock); + vchan_cookie_complete(& + dpaa2_comp->vdesc); + spin_unlock(&qchan->vchan.lock); + found = 1; + break; + } + } + spin_unlock(&qchan->queue_lock); + if (found) + break; + } + } + + dpaa2_io_service_rearm(NULL, ctx); +} + +static int __cold dpaa2_qdma_dpio_setup(struct dpaa2_qdma_priv *priv) +{ + struct dpaa2_qdma_priv_per_prio *ppriv; + struct device *dev = priv->dev; + int err = -EINVAL; + int i, num; + + num = priv->num_pairs; + ppriv = priv->ppriv; + for (i = 0; i < num; i++) { + ppriv->nctx.is_cdan = 0; + ppriv->nctx.desired_cpu = DPAA2_IO_ANY_CPU; + ppriv->nctx.id = ppriv->rsp_fqid; + ppriv->nctx.cb = dpaa2_qdma_fqdan_cb; + err = dpaa2_io_service_register(NULL, &ppriv->nctx, dev); + if (err) { + dev_err(dev, "Notification register failed\n"); + goto err_service; + } + + ppriv->store = + dpaa2_io_store_create(DPAA2_QDMA_STORE_SIZE, dev); + if (!ppriv->store) { + dev_err(dev, "dpaa2_io_store_create() failed\n"); + goto err_store; + } + + ppriv++; + } + return 0; + +err_store: + dpaa2_io_service_deregister(NULL, &ppriv->nctx, dev); +err_service: + ppriv--; + while (ppriv >= priv->ppriv) { + dpaa2_io_service_deregister(NULL, &ppriv->nctx, dev); + dpaa2_io_store_destroy(ppriv->store); + ppriv--; + } + return err; +} + +static void dpaa2_dpmai_store_free(struct dpaa2_qdma_priv *priv) +{ + struct dpaa2_qdma_priv_per_prio *ppriv = priv->ppriv; + int i; + + for (i = 0; i < priv->num_pairs; i++) { + dpaa2_io_store_destroy(ppriv->store); + ppriv++; + } +} + +static void dpaa2_dpdmai_dpio_free(struct dpaa2_qdma_priv *priv) +{ + struct dpaa2_qdma_priv_per_prio *ppriv = priv->ppriv; + struct device *dev = priv->dev; + int i; + + for (i = 0; i < priv->num_pairs; i++) { + dpaa2_io_service_deregister(NULL, &ppriv->nctx, dev); + ppriv++; + } +} + +static int __cold dpaa2_dpdmai_bind(struct dpaa2_qdma_priv *priv) +{ + struct dpdmai_rx_queue_cfg rx_queue_cfg; + struct dpaa2_qdma_priv_per_prio *ppriv; + struct device *dev = priv->dev; + struct fsl_mc_device *ls_dev; + int i, num; + int err; + + ls_dev = to_fsl_mc_device(dev); + num = priv->num_pairs; + ppriv = priv->ppriv; + for (i = 0; i < num; i++) { + rx_queue_cfg.options = DPDMAI_QUEUE_OPT_USER_CTX | + DPDMAI_QUEUE_OPT_DEST; + rx_queue_cfg.user_ctx = ppriv->nctx.qman64; + rx_queue_cfg.dest_cfg.dest_type = DPDMAI_DEST_DPIO; + rx_queue_cfg.dest_cfg.dest_id = ppriv->nctx.dpio_id; + rx_queue_cfg.dest_cfg.priority = ppriv->prio; + err = dpdmai_set_rx_queue(priv->mc_io, 0, ls_dev->mc_handle, + rx_queue_cfg.dest_cfg.priority, + &rx_queue_cfg); + if (err) { + dev_err(dev, "dpdmai_set_rx_queue() failed\n"); + return err; + } + + ppriv++; + } + + return 0; +} + +static int __cold dpaa2_dpdmai_dpio_unbind(struct dpaa2_qdma_priv *priv) +{ + struct dpaa2_qdma_priv_per_prio *ppriv = priv->ppriv; + struct device *dev = priv->dev; + struct fsl_mc_device *ls_dev; + int err = 0; + int i; + + ls_dev = to_fsl_mc_device(dev); + + for (i = 0; i < priv->num_pairs; i++) { + ppriv->nctx.qman64 = 0; + ppriv->nctx.dpio_id = 0; + ppriv++; + } + + err = dpdmai_reset(priv->mc_io, 0, ls_dev->mc_handle); + if (err) + dev_err(dev, "dpdmai_reset() failed\n"); + + return err; +} + +static void dpaa2_dpdmai_free_comp(struct dpaa2_qdma_chan *qchan, + struct list_head *head) +{ + struct dpaa2_qdma_comp *comp_tmp, *_comp_tmp; + unsigned long flags; + + list_for_each_entry_safe(comp_tmp, _comp_tmp, + head, list) { + spin_lock_irqsave(&qchan->queue_lock, flags); + list_del(&comp_tmp->list); + spin_unlock_irqrestore(&qchan->queue_lock, flags); + dma_pool_free(qchan->fd_pool, + comp_tmp->fd_virt_addr, + comp_tmp->fd_bus_addr); + dma_pool_free(qchan->fl_pool, + comp_tmp->fl_virt_addr, + comp_tmp->fl_bus_addr); + dma_pool_free(qchan->sdd_pool, + comp_tmp->desc_virt_addr, + comp_tmp->desc_bus_addr); + kfree(comp_tmp); + } +} + +static void dpaa2_dpdmai_free_channels(struct dpaa2_qdma_engine *dpaa2_qdma) +{ + struct dpaa2_qdma_chan *qchan; + int num, i; + + num = dpaa2_qdma->n_chans; + for (i = 0; i < num; i++) { + qchan = &dpaa2_qdma->chans[i]; + dpaa2_dpdmai_free_comp(qchan, &qchan->comp_used); + dpaa2_dpdmai_free_comp(qchan, &qchan->comp_free); + dma_pool_destroy(qchan->fd_pool); + dma_pool_destroy(qchan->fl_pool); + dma_pool_destroy(qchan->sdd_pool); + } +} + +static void dpaa2_qdma_free_desc(struct virt_dma_desc *vdesc) +{ + struct dpaa2_qdma_comp *dpaa2_comp; + struct dpaa2_qdma_chan *qchan; + unsigned long flags; + + dpaa2_comp = to_fsl_qdma_comp(vdesc); + qchan = dpaa2_comp->qchan; + spin_lock_irqsave(&qchan->queue_lock, flags); + list_del(&dpaa2_comp->list); + list_add_tail(&dpaa2_comp->list, &qchan->comp_free); + spin_unlock_irqrestore(&qchan->queue_lock, flags); +} + +static int dpaa2_dpdmai_init_channels(struct dpaa2_qdma_engine *dpaa2_qdma) +{ + struct dpaa2_qdma_priv *priv = dpaa2_qdma->priv; + struct dpaa2_qdma_chan *dpaa2_chan; + int num = priv->num_pairs; + int i; + + INIT_LIST_HEAD(&dpaa2_qdma->dma_dev.channels); + for (i = 0; i < dpaa2_qdma->n_chans; i++) { + dpaa2_chan = &dpaa2_qdma->chans[i]; + dpaa2_chan->qdma = dpaa2_qdma; + dpaa2_chan->fqid = priv->tx_fqid[i % num]; + dpaa2_chan->vchan.desc_free = dpaa2_qdma_free_desc; + vchan_init(&dpaa2_chan->vchan, &dpaa2_qdma->dma_dev); + spin_lock_init(&dpaa2_chan->queue_lock); + INIT_LIST_HEAD(&dpaa2_chan->comp_used); + INIT_LIST_HEAD(&dpaa2_chan->comp_free); + } + return 0; +} + +static int dpaa2_qdma_probe(struct fsl_mc_device *dpdmai_dev) +{ + struct device *dev = &dpdmai_dev->dev; + struct dpaa2_qdma_engine *dpaa2_qdma; + struct dpaa2_qdma_priv *priv; + int err; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + dev_set_drvdata(dev, priv); + priv->dpdmai_dev = dpdmai_dev; + + priv->iommu_domain = iommu_get_domain_for_dev(dev); + if (priv->iommu_domain) + smmu_disable = false; + + /* obtain a MC portal */ + err = fsl_mc_portal_allocate(dpdmai_dev, 0, &priv->mc_io); + if (err) { + if (err == -ENXIO) + err = -EPROBE_DEFER; + else + dev_err(dev, "MC portal allocation failed\n"); + goto err_mcportal; + } + + /* DPDMAI initialization */ + err = dpaa2_qdma_setup(dpdmai_dev); + if (err) { + dev_err(dev, "dpaa2_dpdmai_setup() failed\n"); + goto err_dpdmai_setup; + } + + /* DPIO */ + err = dpaa2_qdma_dpio_setup(priv); + if (err) { + dev_err(dev, "dpaa2_dpdmai_dpio_setup() failed\n"); + goto err_dpio_setup; + } + + /* DPDMAI binding to DPIO */ + err = dpaa2_dpdmai_bind(priv); + if (err) { + dev_err(dev, "dpaa2_dpdmai_bind() failed\n"); + goto err_bind; + } + + /* DPDMAI enable */ + err = dpdmai_enable(priv->mc_io, 0, dpdmai_dev->mc_handle); + if (err) { + dev_err(dev, "dpdmai_enable() faile\n"); + goto err_enable; + } + + dpaa2_qdma = kzalloc(sizeof(*dpaa2_qdma), GFP_KERNEL); + if (!dpaa2_qdma) { + err = -ENOMEM; + goto err_eng; + } + + priv->dpaa2_qdma = dpaa2_qdma; + dpaa2_qdma->priv = priv; + + dpaa2_qdma->desc_allocated = 0; + dpaa2_qdma->n_chans = NUM_CH; + + dpaa2_dpdmai_init_channels(dpaa2_qdma); + + if (soc_device_match(soc_fixup_tuning)) + dpaa2_qdma->qdma_wrtype_fixup = true; + else + dpaa2_qdma->qdma_wrtype_fixup = false; + + dma_cap_set(DMA_PRIVATE, dpaa2_qdma->dma_dev.cap_mask); + dma_cap_set(DMA_SLAVE, dpaa2_qdma->dma_dev.cap_mask); + dma_cap_set(DMA_MEMCPY, dpaa2_qdma->dma_dev.cap_mask); + + dpaa2_qdma->dma_dev.dev = dev; + dpaa2_qdma->dma_dev.device_alloc_chan_resources = + dpaa2_qdma_alloc_chan_resources; + dpaa2_qdma->dma_dev.device_free_chan_resources = + dpaa2_qdma_free_chan_resources; + dpaa2_qdma->dma_dev.device_tx_status = dma_cookie_status; + dpaa2_qdma->dma_dev.device_prep_dma_memcpy = dpaa2_qdma_prep_memcpy; + dpaa2_qdma->dma_dev.device_issue_pending = dpaa2_qdma_issue_pending; + + err = dma_async_device_register(&dpaa2_qdma->dma_dev); + if (err) { + dev_err(dev, "Can't register NXP QDMA engine.\n"); + goto err_dpaa2_qdma; + } + + return 0; + +err_dpaa2_qdma: + kfree(dpaa2_qdma); +err_eng: + dpdmai_disable(priv->mc_io, 0, dpdmai_dev->mc_handle); +err_enable: + dpaa2_dpdmai_dpio_unbind(priv); +err_bind: + dpaa2_dpmai_store_free(priv); + dpaa2_dpdmai_dpio_free(priv); +err_dpio_setup: + kfree(priv->ppriv); + dpdmai_close(priv->mc_io, 0, dpdmai_dev->mc_handle); +err_dpdmai_setup: + fsl_mc_portal_free(priv->mc_io); +err_mcportal: + kfree(priv); + dev_set_drvdata(dev, NULL); + return err; +} + +static int dpaa2_qdma_remove(struct fsl_mc_device *ls_dev) +{ + struct dpaa2_qdma_engine *dpaa2_qdma; + struct dpaa2_qdma_priv *priv; + struct device *dev; + + dev = &ls_dev->dev; + priv = dev_get_drvdata(dev); + dpaa2_qdma = priv->dpaa2_qdma; + + dpdmai_disable(priv->mc_io, 0, ls_dev->mc_handle); + dpaa2_dpdmai_dpio_unbind(priv); + dpaa2_dpmai_store_free(priv); + dpaa2_dpdmai_dpio_free(priv); + dpdmai_close(priv->mc_io, 0, ls_dev->mc_handle); + fsl_mc_portal_free(priv->mc_io); + dev_set_drvdata(dev, NULL); + dpaa2_dpdmai_free_channels(dpaa2_qdma); + + dma_async_device_unregister(&dpaa2_qdma->dma_dev); + kfree(priv); + kfree(dpaa2_qdma); + + return 0; +} + +static const struct fsl_mc_device_id dpaa2_qdma_id_table[] = { + { + .vendor = FSL_MC_VENDOR_FREESCALE, + .obj_type = "dpdmai", + }, + { .vendor = 0x0 } +}; + +static struct fsl_mc_driver dpaa2_qdma_driver = { + .driver = { + .name = "dpaa2-qdma", + .owner = THIS_MODULE, + }, + .probe = dpaa2_qdma_probe, + .remove = dpaa2_qdma_remove, + .match_id_table = dpaa2_qdma_id_table +}; + +static int __init dpaa2_qdma_driver_init(void) +{ + return fsl_mc_driver_register(&(dpaa2_qdma_driver)); +} +late_initcall(dpaa2_qdma_driver_init); + +static void __exit fsl_qdma_exit(void) +{ + fsl_mc_driver_unregister(&(dpaa2_qdma_driver)); +} +module_exit(fsl_qdma_exit); + +MODULE_ALIAS("platform:fsl-dpaa2-qdma"); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("NXP Layerscape DPAA2 qDMA engine driver"); diff --git a/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h new file mode 100644 index 00000000000000..7d571849c569cb --- /dev/null +++ b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright 2019 NXP */ + +#ifndef __DPAA2_QDMA_H +#define __DPAA2_QDMA_H + +#define DPAA2_QDMA_STORE_SIZE 16 +#define NUM_CH 8 + +struct dpaa2_qdma_sd_d { + u32 rsv:32; + union { + struct { + u32 ssd:12; /* souce stride distance */ + u32 sss:12; /* souce stride size */ + u32 rsv1:8; + } sdf; + struct { + u32 dsd:12; /* Destination stride distance */ + u32 dss:12; /* Destination stride size */ + u32 rsv2:8; + } ddf; + } df; + u32 rbpcmd; /* Route-by-port command */ + u32 cmd; +} __attribute__((__packed__)); + +/* Source descriptor command read transaction type for RBP=0: */ +/* coherent copy of cacheable memory */ +#define QDMA_SD_CMD_RDTTYPE_COHERENT (0xb << 28) +/* Destination descriptor command write transaction type for RBP=0: */ +/* coherent copy of cacheable memory */ +#define QDMA_DD_CMD_WRTTYPE_COHERENT (0x6 << 28) +#define LX2160_QDMA_DD_CMD_WRTTYPE_COHERENT (0xb << 28) + +#define QMAN_FD_FMT_ENABLE BIT(0) /* frame list table enable */ +#define QMAN_FD_BMT_ENABLE BIT(15) /* bypass memory translation */ +#define QMAN_FD_BMT_DISABLE (0) /* bypass memory translation */ +#define QMAN_FD_SL_DISABLE (0) /* short lengthe disabled */ +#define QMAN_FD_SL_ENABLE BIT(14) /* short lengthe enabled */ + +#define QDMA_FINAL_BIT_DISABLE (0) /* final bit disable */ +#define QDMA_FINAL_BIT_ENABLE BIT(31) /* final bit enable */ + +#define QDMA_FD_SHORT_FORMAT BIT(11) /* short format */ +#define QDMA_FD_LONG_FORMAT (0) /* long format */ +#define QDMA_SER_DISABLE (8) /* no notification */ +#define QDMA_SER_CTX BIT(8) /* notification by FQD_CTX[fqid] */ +#define QDMA_SER_DEST (2 << 8) /* notification by destination desc */ +#define QDMA_SER_BOTH (3 << 8) /* soruce and dest notification */ +#define QDMA_FD_SPF_ENALBE BIT(30) /* source prefetch enable */ + +#define QMAN_FD_VA_ENABLE BIT(14) /* Address used is virtual address */ +#define QMAN_FD_VA_DISABLE (0)/* Address used is a real address */ +/* Flow Context: 49bit physical address */ +#define QMAN_FD_CBMT_ENABLE BIT(15) +#define QMAN_FD_CBMT_DISABLE (0) /* Flow Context: 64bit virtual address */ +#define QMAN_FD_SC_DISABLE (0) /* stashing control */ + +#define QDMA_FL_FMT_SBF (0x0) /* Single buffer frame */ +#define QDMA_FL_FMT_SGE (0x2) /* Scatter gather frame */ +#define QDMA_FL_BMT_ENABLE BIT(15) /* enable bypass memory translation */ +#define QDMA_FL_BMT_DISABLE (0x0) /* enable bypass memory translation */ +#define QDMA_FL_SL_LONG (0x0)/* long length */ +#define QDMA_FL_SL_SHORT (0x1) /* short length */ +#define QDMA_FL_F (0x1)/* last frame list bit */ + +/*Description of Frame list table structure*/ +struct dpaa2_qdma_chan { + struct dpaa2_qdma_engine *qdma; + struct virt_dma_chan vchan; + struct virt_dma_desc vdesc; + enum dma_status status; + u32 fqid; + + /* spinlock used by dpaa2 qdma driver */ + spinlock_t queue_lock; + struct dma_pool *fd_pool; + struct dma_pool *fl_pool; + struct dma_pool *sdd_pool; + + struct list_head comp_used; + struct list_head comp_free; + +}; + +struct dpaa2_qdma_comp { + dma_addr_t fd_bus_addr; + dma_addr_t fl_bus_addr; + dma_addr_t desc_bus_addr; + struct dpaa2_fd *fd_virt_addr; + struct dpaa2_fl_entry *fl_virt_addr; + struct dpaa2_qdma_sd_d *desc_virt_addr; + struct dpaa2_qdma_chan *qchan; + struct virt_dma_desc vdesc; + struct list_head list; +}; + +struct dpaa2_qdma_engine { + struct dma_device dma_dev; + u32 n_chans; + struct dpaa2_qdma_chan chans[NUM_CH]; + int qdma_wrtype_fixup; + int desc_allocated; + + struct dpaa2_qdma_priv *priv; +}; + +/* + * dpaa2_qdma_priv - driver private data + */ +struct dpaa2_qdma_priv { + int dpqdma_id; + + struct iommu_domain *iommu_domain; + struct dpdmai_attr dpdmai_attr; + struct device *dev; + struct fsl_mc_io *mc_io; + struct fsl_mc_device *dpdmai_dev; + u8 num_pairs; + + struct dpaa2_qdma_engine *dpaa2_qdma; + struct dpaa2_qdma_priv_per_prio *ppriv; + + struct dpdmai_rx_queue_attr rx_queue_attr[DPDMAI_PRIO_NUM]; + u32 tx_fqid[DPDMAI_PRIO_NUM]; +}; + +struct dpaa2_qdma_priv_per_prio { + int req_fqid; + int rsp_fqid; + int prio; + + struct dpaa2_io_store *store; + struct dpaa2_io_notification_ctx nctx; + + struct dpaa2_qdma_priv *priv; +}; + +static struct soc_device_attribute soc_fixup_tuning[] = { + { .family = "QorIQ LX2160A"}, + { }, +}; + +/* FD pool size: one FD + 3 Frame list + 2 source/destination descriptor */ +#define FD_POOL_SIZE (sizeof(struct dpaa2_fd) + \ + sizeof(struct dpaa2_fl_entry) * 3 + \ + sizeof(struct dpaa2_qdma_sd_d) * 2) + +static void dpaa2_dpdmai_free_channels(struct dpaa2_qdma_engine *dpaa2_qdma); +static void dpaa2_dpdmai_free_comp(struct dpaa2_qdma_chan *qchan, + struct list_head *head); +#endif /* __DPAA2_QDMA_H */ diff --git a/drivers/dma/fsl-dpaa2-qdma/dpdmai.c b/drivers/dma/fsl-dpaa2-qdma/dpdmai.c new file mode 100644 index 00000000000000..fbc2b2f39becef --- /dev/null +++ b/drivers/dma/fsl-dpaa2-qdma/dpdmai.c @@ -0,0 +1,366 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright 2019 NXP + +#include +#include +#include +#include "dpdmai.h" + +struct dpdmai_rsp_get_attributes { + __le32 id; + u8 num_of_priorities; + u8 pad0[3]; + __le16 major; + __le16 minor; +}; + +struct dpdmai_cmd_queue { + __le32 dest_id; + u8 priority; + u8 queue; + u8 dest_type; + u8 pad; + __le64 user_ctx; + union { + __le32 options; + __le32 fqid; + }; +}; + +struct dpdmai_rsp_get_tx_queue { + __le64 pad; + __le32 fqid; +}; + +#define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \ + ((_cmd).params[_param] |= mc_enc((_offset), (_width), _arg)) + +/* cmd, param, offset, width, type, arg_name */ +#define DPDMAI_CMD_CREATE(_cmd, _cfg) \ +do { \ + typeof(_cmd) (cmd) = (_cmd); \ + typeof(_cfg) (cfg) = (_cfg); \ + MC_CMD_OP(cmd, 0, 8, 8, u8, (cfg)->priorities[0]);\ + MC_CMD_OP(cmd, 0, 16, 8, u8, (cfg)->priorities[1]);\ +} while (0) + +static inline u64 mc_enc(int lsoffset, int width, u64 val) +{ + return (val & MAKE_UMASK64(width)) << lsoffset; +} + +/** + * dpdmai_open() - Open a control session for the specified object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @dpdmai_id: DPDMAI unique ID + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpdmai_create() function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent commands for + * this specific object. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpdmai_open(struct fsl_mc_io *mc_io, u32 cmd_flags, + int dpdmai_id, u16 *token) +{ + struct fsl_mc_command cmd = { 0 }; + __le64 *cmd_dpdmai_id; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_OPEN, + cmd_flags, 0); + + cmd_dpdmai_id = cmd.params; + *cmd_dpdmai_id = cpu_to_le32(dpdmai_id); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + *token = mc_cmd_hdr_read_token(&cmd); + + return 0; +} + +/** + * dpdmai_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPDMAI object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpdmai_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) +{ + struct fsl_mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_CLOSE, + cmd_flags, token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +/** + * dpdmai_create() - Create the DPDMAI object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @cfg: Configuration structure + * @token: Returned token; use in subsequent API calls + * + * Create the DPDMAI object, allocate required resources and + * perform required initialization. + * + * The object can be created either by declaring it in the + * DPL file, or by calling this function. + * + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent calls to + * this specific object. For objects that are created using the + * DPL file, call dpdmai_open() function to get an authentication + * token first. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpdmai_create(struct fsl_mc_io *mc_io, u32 cmd_flags, + const struct dpdmai_cfg *cfg, u16 *token) +{ + struct fsl_mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_CREATE, + cmd_flags, 0); + DPDMAI_CMD_CREATE(cmd, cfg); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + *token = mc_cmd_hdr_read_token(&cmd); + + return 0; +} + +/** + * dpdmai_enable() - Enable the DPDMAI, allow sending and receiving frames. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPDMAI object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpdmai_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) +{ + struct fsl_mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_ENABLE, + cmd_flags, token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +/** + * dpdmai_disable() - Disable the DPDMAI, stop sending and receiving frames. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPDMAI object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpdmai_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) +{ + struct fsl_mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_DISABLE, + cmd_flags, token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +/** + * dpdmai_reset() - Reset the DPDMAI, returns the object to initial state. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPDMAI object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpdmai_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) +{ + struct fsl_mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_RESET, + cmd_flags, token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +/** + * dpdmai_get_attributes() - Retrieve DPDMAI attributes. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPDMAI object + * @attr: Returned object's attributes + * + * Return: '0' on Success; Error code otherwise. + */ +int dpdmai_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 token, struct dpdmai_attr *attr) +{ + struct dpdmai_rsp_get_attributes *rsp_params; + struct fsl_mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_GET_ATTR, + cmd_flags, token); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + rsp_params = (struct dpdmai_rsp_get_attributes *)cmd.params; + attr->id = le32_to_cpu(rsp_params->id); + attr->version.major = le16_to_cpu(rsp_params->major); + attr->version.minor = le16_to_cpu(rsp_params->minor); + attr->num_of_priorities = rsp_params->num_of_priorities; + + return 0; +} + +/** + * dpdmai_set_rx_queue() - Set Rx queue configuration + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPDMAI object + * @priority: Select the queue relative to number of + * priorities configured at DPDMAI creation + * @cfg: Rx queue configuration + * + * Return: '0' on Success; Error code otherwise. + */ +int dpdmai_set_rx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 priority, const struct dpdmai_rx_queue_cfg *cfg) +{ + struct dpdmai_cmd_queue *cmd_params; + struct fsl_mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_SET_RX_QUEUE, + cmd_flags, token); + + cmd_params = (struct dpdmai_cmd_queue *)cmd.params; + cmd_params->dest_id = cpu_to_le32(cfg->dest_cfg.dest_id); + cmd_params->priority = cfg->dest_cfg.priority; + cmd_params->queue = priority; + cmd_params->dest_type = cfg->dest_cfg.dest_type; + cmd_params->user_ctx = cpu_to_le64(cfg->user_ctx); + cmd_params->options = cpu_to_le32(cfg->options); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +/** + * dpdmai_get_rx_queue() - Retrieve Rx queue attributes. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPDMAI object + * @priority: Select the queue relative to number of + * priorities configured at DPDMAI creation + * @attr: Returned Rx queue attributes + * + * Return: '0' on Success; Error code otherwise. + */ +int dpdmai_get_rx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 priority, struct dpdmai_rx_queue_attr *attr) +{ + struct dpdmai_cmd_queue *cmd_params; + struct fsl_mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_GET_RX_QUEUE, + cmd_flags, token); + + cmd_params = (struct dpdmai_cmd_queue *)cmd.params; + cmd_params->queue = priority; + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + attr->dest_cfg.dest_id = le32_to_cpu(cmd_params->dest_id); + attr->dest_cfg.priority = cmd_params->priority; + attr->dest_cfg.dest_type = cmd_params->dest_type; + attr->user_ctx = le64_to_cpu(cmd_params->user_ctx); + attr->fqid = le32_to_cpu(cmd_params->fqid); + + return 0; +} + +/** + * dpdmai_get_tx_queue() - Retrieve Tx queue attributes. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPDMAI object + * @priority: Select the queue relative to number of + * priorities configured at DPDMAI creation + * @fqid: Returned Tx queue + * + * Return: '0' on Success; Error code otherwise. + */ +int dpdmai_get_tx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 token, u8 priority, u32 *fqid) +{ + struct dpdmai_rsp_get_tx_queue *rsp_params; + struct dpdmai_cmd_queue *cmd_params; + struct fsl_mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_GET_TX_QUEUE, + cmd_flags, token); + + cmd_params = (struct dpdmai_cmd_queue *)cmd.params; + cmd_params->queue = priority; + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + + rsp_params = (struct dpdmai_rsp_get_tx_queue *)cmd.params; + *fqid = le32_to_cpu(rsp_params->fqid); + + return 0; +} diff --git a/drivers/dma/fsl-dpaa2-qdma/dpdmai.h b/drivers/dma/fsl-dpaa2-qdma/dpdmai.h new file mode 100644 index 00000000000000..6d785093da8ef6 --- /dev/null +++ b/drivers/dma/fsl-dpaa2-qdma/dpdmai.h @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright 2019 NXP */ + +#ifndef __FSL_DPDMAI_H +#define __FSL_DPDMAI_H + +/* DPDMAI Version */ +#define DPDMAI_VER_MAJOR 2 +#define DPDMAI_VER_MINOR 2 + +#define DPDMAI_CMD_BASE_VERSION 0 +#define DPDMAI_CMD_ID_OFFSET 4 + +#define DPDMAI_CMDID_FORMAT(x) (((x) << DPDMAI_CMD_ID_OFFSET) | \ + DPDMAI_CMD_BASE_VERSION) + +/* Command IDs */ +#define DPDMAI_CMDID_CLOSE DPDMAI_CMDID_FORMAT(0x800) +#define DPDMAI_CMDID_OPEN DPDMAI_CMDID_FORMAT(0x80E) +#define DPDMAI_CMDID_CREATE DPDMAI_CMDID_FORMAT(0x90E) + +#define DPDMAI_CMDID_ENABLE DPDMAI_CMDID_FORMAT(0x002) +#define DPDMAI_CMDID_DISABLE DPDMAI_CMDID_FORMAT(0x003) +#define DPDMAI_CMDID_GET_ATTR DPDMAI_CMDID_FORMAT(0x004) +#define DPDMAI_CMDID_RESET DPDMAI_CMDID_FORMAT(0x005) +#define DPDMAI_CMDID_IS_ENABLED DPDMAI_CMDID_FORMAT(0x006) + +#define DPDMAI_CMDID_SET_IRQ DPDMAI_CMDID_FORMAT(0x010) +#define DPDMAI_CMDID_GET_IRQ DPDMAI_CMDID_FORMAT(0x011) +#define DPDMAI_CMDID_SET_IRQ_ENABLE DPDMAI_CMDID_FORMAT(0x012) +#define DPDMAI_CMDID_GET_IRQ_ENABLE DPDMAI_CMDID_FORMAT(0x013) +#define DPDMAI_CMDID_SET_IRQ_MASK DPDMAI_CMDID_FORMAT(0x014) +#define DPDMAI_CMDID_GET_IRQ_MASK DPDMAI_CMDID_FORMAT(0x015) +#define DPDMAI_CMDID_GET_IRQ_STATUS DPDMAI_CMDID_FORMAT(0x016) +#define DPDMAI_CMDID_CLEAR_IRQ_STATUS DPDMAI_CMDID_FORMAT(0x017) + +#define DPDMAI_CMDID_SET_RX_QUEUE DPDMAI_CMDID_FORMAT(0x1A0) +#define DPDMAI_CMDID_GET_RX_QUEUE DPDMAI_CMDID_FORMAT(0x1A1) +#define DPDMAI_CMDID_GET_TX_QUEUE DPDMAI_CMDID_FORMAT(0x1A2) + +#define MC_CMD_HDR_TOKEN_O 32 /* Token field offset */ +#define MC_CMD_HDR_TOKEN_S 16 /* Token field size */ + +#define MAKE_UMASK64(_width) \ + ((u64)((_width) < 64 ? ((u64)1 << (_width)) - 1 : (u64)-1)) + +/* Data Path DMA Interface API + * Contains initialization APIs and runtime control APIs for DPDMAI + */ + +/** + * Maximum number of Tx/Rx priorities per DPDMAI object + */ +#define DPDMAI_PRIO_NUM 2 + +/* DPDMAI queue modification options */ + +/** + * Select to modify the user's context associated with the queue + */ +#define DPDMAI_QUEUE_OPT_USER_CTX 0x1 + +/** + * Select to modify the queue's destination + */ +#define DPDMAI_QUEUE_OPT_DEST 0x2 + +/** + * struct dpdmai_cfg - Structure representing DPDMAI configuration + * @priorities: Priorities for the DMA hardware processing; valid priorities are + * configured with values 1-8; the entry following last valid entry + * should be configured with 0 + */ +struct dpdmai_cfg { + u8 priorities[DPDMAI_PRIO_NUM]; +}; + +/** + * struct dpdmai_attr - Structure representing DPDMAI attributes + * @id: DPDMAI object ID + * @version: DPDMAI version + * @num_of_priorities: number of priorities + */ +struct dpdmai_attr { + int id; + /** + * struct version - DPDMAI version + * @major: DPDMAI major version + * @minor: DPDMAI minor version + */ + struct { + u16 major; + u16 minor; + } version; + u8 num_of_priorities; +}; + +/** + * enum dpdmai_dest - DPDMAI destination types + * @DPDMAI_DEST_NONE: Unassigned destination; The queue is set in parked mode + * and does not generate FQDAN notifications; user is expected to dequeue + * from the queue based on polling or other user-defined method + * @DPDMAI_DEST_DPIO: The queue is set in schedule mode and generates FQDAN + * notifications to the specified DPIO; user is expected to dequeue + * from the queue only after notification is received + * @DPDMAI_DEST_DPCON: The queue is set in schedule mode and does not generate + * FQDAN notifications, but is connected to the specified DPCON object; + * user is expected to dequeue from the DPCON channel + */ +enum dpdmai_dest { + DPDMAI_DEST_NONE = 0, + DPDMAI_DEST_DPIO = 1, + DPDMAI_DEST_DPCON = 2 +}; + +/** + * struct dpdmai_dest_cfg - Structure representing DPDMAI destination parameters + * @dest_type: Destination type + * @dest_id: Either DPIO ID or DPCON ID, depending on the destination type + * @priority: Priority selection within the DPIO or DPCON channel; valid values + * are 0-1 or 0-7, depending on the number of priorities in that + * channel; not relevant for 'DPDMAI_DEST_NONE' option + */ +struct dpdmai_dest_cfg { + enum dpdmai_dest dest_type; + int dest_id; + u8 priority; +}; + +/** + * struct dpdmai_rx_queue_cfg - DPDMAI RX queue configuration + * @options: Flags representing the suggested modifications to the queue; + * Use any combination of 'DPDMAI_QUEUE_OPT_' flags + * @user_ctx: User context value provided in the frame descriptor of each + * dequeued frame; + * valid only if 'DPDMAI_QUEUE_OPT_USER_CTX' is contained in 'options' + * @dest_cfg: Queue destination parameters; + * valid only if 'DPDMAI_QUEUE_OPT_DEST' is contained in 'options' + */ +struct dpdmai_rx_queue_cfg { + struct dpdmai_dest_cfg dest_cfg; + u32 options; + u64 user_ctx; + +}; + +/** + * struct dpdmai_rx_queue_attr - Structure representing attributes of Rx queues + * @user_ctx: User context value provided in the frame descriptor of each + * dequeued frame + * @dest_cfg: Queue destination configuration + * @fqid: Virtual FQID value to be used for dequeue operations + */ +struct dpdmai_rx_queue_attr { + struct dpdmai_dest_cfg dest_cfg; + u64 user_ctx; + u32 fqid; +}; + +int dpdmai_open(struct fsl_mc_io *mc_io, u32 cmd_flags, + int dpdmai_id, u16 *token); +int dpdmai_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); +int dpdmai_create(struct fsl_mc_io *mc_io, u32 cmd_flags, + const struct dpdmai_cfg *cfg, u16 *token); +int dpdmai_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); +int dpdmai_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); +int dpdmai_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); +int dpdmai_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 token, struct dpdmai_attr *attr); +int dpdmai_set_rx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 priority, const struct dpdmai_rx_queue_cfg *cfg); +int dpdmai_get_rx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 priority, struct dpdmai_rx_queue_attr *attr); +int dpdmai_get_tx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 token, u8 priority, u32 *fqid); + +#endif /* __FSL_DPDMAI_H */ diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index d6010486ee502b..4a13e158065a1f 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -109,10 +109,15 @@ void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan, u32 ch = fsl_chan->vchan.chan.chan_id; void __iomem *muxaddr; unsigned int chans_per_mux, ch_off; + int endian_diff[4] = {3, 1, -1, -3}; u32 dmamux_nr = fsl_chan->edma->drvdata->dmamuxs; chans_per_mux = fsl_chan->edma->n_chans / dmamux_nr; ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux; + + if (fsl_chan->edma->drvdata->mux_swap) + ch_off += endian_diff[ch_off % 4]; + muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux]; slot = EDMAMUX_CHCFG_SOURCE(slot); @@ -305,6 +310,11 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan, return len; } +void fsl_edma_get_realcnt(struct fsl_edma_chan *fsl_chan) +{ + fsl_chan->chn_real_count = fsl_edma_desc_residue(fsl_chan, NULL, true); +} + enum dma_status fsl_edma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *txstate) { @@ -314,8 +324,12 @@ enum dma_status fsl_edma_tx_status(struct dma_chan *chan, unsigned long flags; status = dma_cookie_status(chan, cookie, txstate); - if (status == DMA_COMPLETE) + if (status == DMA_COMPLETE) { + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + txstate->residue = fsl_chan->chn_real_count; + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); return status; + } if (!txstate) return fsl_chan->status; diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h index 6ff7063a8a2f84..b254dc65698041 100644 --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h @@ -126,6 +126,7 @@ struct fsl_edma_chan { u32 dma_dev_size; enum dma_data_direction dma_dir; char chan_name[16]; + u32 chn_real_count; }; struct fsl_edma_desc { @@ -147,6 +148,7 @@ struct fsl_edma_drvdata { enum edma_version version; u32 dmamuxs; bool has_dmaclk; + bool mux_swap; int (*setup_irq)(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma); }; @@ -229,6 +231,7 @@ int fsl_edma_pause(struct dma_chan *chan); int fsl_edma_resume(struct dma_chan *chan); int fsl_edma_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg); +void fsl_edma_get_realcnt(struct fsl_edma_chan *fsl_chan); enum dma_status fsl_edma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *txstate); struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic( diff --git a/drivers/dma/fsl-edma-v3.c b/drivers/dma/fsl-edma-v3.c new file mode 100644 index 00000000000000..7204124a074255 --- /dev/null +++ b/drivers/dma/fsl-edma-v3.c @@ -0,0 +1,1151 @@ +/* + * drivers/dma/fsl-edma3-v3.c + * + * Copyright 2017-2018 NXP . + * + * Driver for the Freescale eDMA engine v3. This driver based on fsl-edma3.c + * but changed to meet the IP change on i.MX8QM: every dma channel is specific + * to hardware. For example, channel 14 for LPUART1 receive request and channel + * 13 for transmit requesst. The eDMA block can be found on i.MX8QM + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "virt-dma.h" + +#define EDMA_CH_CSR 0x00 +#define EDMA_CH_ES 0x04 +#define EDMA_CH_INT 0x08 +#define EDMA_CH_SBR 0x0C +#define EDMA_CH_PRI 0x10 +#define EDMA_TCD_SADDR 0x20 +#define EDMA_TCD_SOFF 0x24 +#define EDMA_TCD_ATTR 0x26 +#define EDMA_TCD_NBYTES 0x28 +#define EDMA_TCD_SLAST 0x2C +#define EDMA_TCD_DADDR 0x30 +#define EDMA_TCD_DOFF 0x34 +#define EDMA_TCD_CITER_ELINK 0x36 +#define EDMA_TCD_CITER 0x36 +#define EDMA_TCD_DLAST_SGA 0x38 +#define EDMA_TCD_CSR 0x3C +#define EDMA_TCD_BITER_ELINK 0x3E +#define EDMA_TCD_BITER 0x3E + +#define EDMA_CH_SBR_RD BIT(22) +#define EDMA_CH_SBR_WR BIT(21) +#define EDMA_CH_CSR_ERQ BIT(0) +#define EDMA_CH_CSR_EARQ BIT(1) +#define EDMA_CH_CSR_EEI BIT(2) +#define EDMA_CH_CSR_DONE BIT(30) +#define EDMA_CH_CSR_ACTIVE BIT(31) + +#define EDMA_TCD_ATTR_DSIZE(x) (((x) & 0x0007)) +#define EDMA_TCD_ATTR_DMOD(x) (((x) & 0x001F) << 3) +#define EDMA_TCD_ATTR_SSIZE(x) (((x) & 0x0007) << 8) +#define EDMA_TCD_ATTR_SMOD(x) (((x) & 0x001F) << 11) +#define EDMA_TCD_ATTR_SSIZE_8BIT (0x0000) +#define EDMA_TCD_ATTR_SSIZE_16BIT (0x0100) +#define EDMA_TCD_ATTR_SSIZE_32BIT (0x0200) +#define EDMA_TCD_ATTR_SSIZE_64BIT (0x0300) +#define EDMA_TCD_ATTR_SSIZE_16BYTE (0x0400) +#define EDMA_TCD_ATTR_SSIZE_32BYTE (0x0500) +#define EDMA_TCD_ATTR_SSIZE_64BYTE (0x0600) +#define EDMA_TCD_ATTR_DSIZE_8BIT (0x0000) +#define EDMA_TCD_ATTR_DSIZE_16BIT (0x0001) +#define EDMA_TCD_ATTR_DSIZE_32BIT (0x0002) +#define EDMA_TCD_ATTR_DSIZE_64BIT (0x0003) +#define EDMA_TCD_ATTR_DSIZE_16BYTE (0x0004) +#define EDMA_TCD_ATTR_DSIZE_32BYTE (0x0005) +#define EDMA_TCD_ATTR_DSIZE_64BYTE (0x0006) + +#define EDMA_TCD_SOFF_SOFF(x) (x) +#define EDMA_TCD_NBYTES_NBYTES(x) (x) +#define EDMA_TCD_NBYTES_MLOFF(x) (x << 10) +#define EDMA_TCD_NBYTES_DMLOE (1 << 30) +#define EDMA_TCD_NBYTES_SMLOE (1 << 31) +#define EDMA_TCD_SLAST_SLAST(x) (x) +#define EDMA_TCD_DADDR_DADDR(x) (x) +#define EDMA_TCD_CITER_CITER(x) ((x) & 0x7FFF) +#define EDMA_TCD_DOFF_DOFF(x) (x) +#define EDMA_TCD_DLAST_SGA_DLAST_SGA(x) (x) +#define EDMA_TCD_BITER_BITER(x) ((x) & 0x7FFF) + +#define EDMA_TCD_CSR_START BIT(0) +#define EDMA_TCD_CSR_INT_MAJOR BIT(1) +#define EDMA_TCD_CSR_INT_HALF BIT(2) +#define EDMA_TCD_CSR_D_REQ BIT(3) +#define EDMA_TCD_CSR_E_SG BIT(4) +#define EDMA_TCD_CSR_E_LINK BIT(5) +#define EDMA_TCD_CSR_ACTIVE BIT(6) +#define EDMA_TCD_CSR_DONE BIT(7) + +#define FSL_EDMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ + BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) | \ + BIT(DMA_SLAVE_BUSWIDTH_16_BYTES)) + +#define ARGS_RX BIT(0) +#define ARGS_REMOTE BIT(1) +#define ARGS_DFIFO BIT(2) + +/* channel name template define in dts */ +#define CHAN_PREFIX "edma0-chan" +#define CHAN_POSFIX "-tx" + +enum fsl_edma3_pm_state { + RUNNING = 0, + SUSPENDED, +}; + +struct fsl_edma3_hw_tcd { + __le32 saddr; + __le16 soff; + __le16 attr; + __le32 nbytes; + __le32 slast; + __le32 daddr; + __le16 doff; + __le16 citer; + __le32 dlast_sga; + __le16 csr; + __le16 biter; +}; + +struct fsl_edma3_sw_tcd { + dma_addr_t ptcd; + struct fsl_edma3_hw_tcd *vtcd; +}; + +struct fsl_edma3_slave_config { + enum dma_transfer_direction dir; + enum dma_slave_buswidth addr_width; + u32 dev_addr; + u32 dev2_addr; /* source addr for dev2dev */ + u32 burst; + u32 attr; +}; + +struct fsl_edma3_chan { + struct virt_dma_chan vchan; + enum dma_status status; + enum fsl_edma3_pm_state pm_state; + bool idle; + bool used; + struct fsl_edma3_engine *edma3; + struct fsl_edma3_desc *edesc; + struct fsl_edma3_slave_config fsc; + void __iomem *membase; + int txirq; + int hw_chanid; + int priority; + int is_rxchan; + int is_remote; + int is_dfifo; + struct dma_pool *tcd_pool; + u32 chn_real_count; + char txirq_name[32]; + struct platform_device *pdev; + struct device *dev; +}; + +struct fsl_edma3_desc { + struct virt_dma_desc vdesc; + struct fsl_edma3_chan *echan; + bool iscyclic; + unsigned int n_tcds; + struct fsl_edma3_sw_tcd tcd[]; +}; + +struct fsl_edma3_reg_save { + u32 csr; + u32 sbr; +}; + +struct fsl_edma3_engine { + struct dma_device dma_dev; + unsigned long irqflag; + struct mutex fsl_edma3_mutex; + u32 n_chans; + int errirq; + #define MAX_CHAN_NUM 32 + struct fsl_edma3_reg_save edma_regs[MAX_CHAN_NUM]; + bool swap; /* remote/local swapped on Audio edma */ + struct fsl_edma3_chan chans[]; +}; + +static struct fsl_edma3_chan *to_fsl_edma3_chan(struct dma_chan *chan) +{ + return container_of(chan, struct fsl_edma3_chan, vchan.chan); +} + +static struct fsl_edma3_desc *to_fsl_edma3_desc(struct virt_dma_desc *vd) +{ + return container_of(vd, struct fsl_edma3_desc, vdesc); +} + +static void fsl_edma3_enable_request(struct fsl_edma3_chan *fsl_chan) +{ + void __iomem *addr = fsl_chan->membase; + u32 val; + + val = readl(addr + EDMA_CH_SBR); + /* Remote/local swapped wrongly on iMX8 QM Audio edma */ + if (fsl_chan->edma3->swap) { + if (!fsl_chan->is_rxchan) + val |= EDMA_CH_SBR_RD; + else + val |= EDMA_CH_SBR_WR; + } else { + if (fsl_chan->is_rxchan) + val |= EDMA_CH_SBR_RD; + else + val |= EDMA_CH_SBR_WR; + } + + if (fsl_chan->is_remote) + val &= ~(EDMA_CH_SBR_RD | EDMA_CH_SBR_WR); + + writel(val, addr + EDMA_CH_SBR); + + val = readl(addr + EDMA_CH_CSR); + + val |= EDMA_CH_CSR_ERQ; + writel(val, addr + EDMA_CH_CSR); + + fsl_chan->used = true; +} + +static void fsl_edma3_disable_request(struct fsl_edma3_chan *fsl_chan) +{ + void __iomem *addr = fsl_chan->membase; + u32 val = readl(addr + EDMA_CH_CSR); + + val &= ~EDMA_CH_CSR_ERQ; + writel(val, addr + EDMA_CH_CSR); +} + +static unsigned int fsl_edma3_get_tcd_attr(enum dma_slave_buswidth addr_width) +{ + switch (addr_width) { + case 1: + return EDMA_TCD_ATTR_SSIZE_8BIT | EDMA_TCD_ATTR_DSIZE_8BIT; + case 2: + return EDMA_TCD_ATTR_SSIZE_16BIT | EDMA_TCD_ATTR_DSIZE_16BIT; + case 4: + return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT; + case 8: + return EDMA_TCD_ATTR_SSIZE_64BIT | EDMA_TCD_ATTR_DSIZE_64BIT; + case 16: + return EDMA_TCD_ATTR_SSIZE_16BYTE | EDMA_TCD_ATTR_DSIZE_16BYTE; + case 32: + return EDMA_TCD_ATTR_SSIZE_32BYTE | EDMA_TCD_ATTR_DSIZE_32BYTE; + case 64: + return EDMA_TCD_ATTR_SSIZE_64BYTE | EDMA_TCD_ATTR_DSIZE_64BYTE; + default: + return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT; + } +} + +static void fsl_edma3_free_desc(struct virt_dma_desc *vdesc) +{ + struct fsl_edma3_desc *fsl_desc; + int i; + + fsl_desc = to_fsl_edma3_desc(vdesc); + for (i = 0; i < fsl_desc->n_tcds; i++) + dma_pool_free(fsl_desc->echan->tcd_pool, fsl_desc->tcd[i].vtcd, + fsl_desc->tcd[i].ptcd); + kfree(fsl_desc); +} + +static int fsl_edma3_terminate_all(struct dma_chan *chan) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + unsigned long flags; + LIST_HEAD(head); + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + fsl_edma3_disable_request(fsl_chan); + fsl_chan->edesc = NULL; + fsl_chan->idle = true; + fsl_chan->used = false; + fsl_chan->vchan.cyclic = NULL; + vchan_get_all_descriptors(&fsl_chan->vchan, &head); + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + vchan_dma_desc_free_list(&fsl_chan->vchan, &head); + return 0; +} + +static int fsl_edma3_pause(struct dma_chan *chan) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + unsigned long flags; + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + if (fsl_chan->edesc) { + fsl_edma3_disable_request(fsl_chan); + fsl_chan->status = DMA_PAUSED; + fsl_chan->idle = true; + } + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + return 0; +} + +static int fsl_edma3_resume(struct dma_chan *chan) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + unsigned long flags; + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + if (fsl_chan->edesc) { + fsl_edma3_enable_request(fsl_chan); + fsl_chan->status = DMA_IN_PROGRESS; + fsl_chan->idle = false; + } + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + return 0; +} + +static int fsl_edma3_slave_config(struct dma_chan *chan, + struct dma_slave_config *cfg) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + + fsl_chan->fsc.dir = cfg->direction; + if (cfg->direction == DMA_DEV_TO_MEM) { + fsl_chan->fsc.dev_addr = cfg->src_addr; + fsl_chan->fsc.addr_width = cfg->src_addr_width; + fsl_chan->fsc.burst = cfg->src_maxburst; + fsl_chan->fsc.attr = fsl_edma3_get_tcd_attr + (cfg->src_addr_width); + } else if (cfg->direction == DMA_MEM_TO_DEV) { + fsl_chan->fsc.dev_addr = cfg->dst_addr; + fsl_chan->fsc.addr_width = cfg->dst_addr_width; + fsl_chan->fsc.burst = cfg->dst_maxburst; + fsl_chan->fsc.attr = fsl_edma3_get_tcd_attr + (cfg->dst_addr_width); + } else if (cfg->direction == DMA_DEV_TO_DEV) { + fsl_chan->fsc.dev2_addr = cfg->src_addr; + fsl_chan->fsc.dev_addr = cfg->dst_addr; + fsl_chan->fsc.addr_width = cfg->dst_addr_width; + fsl_chan->fsc.burst = cfg->dst_maxburst; + fsl_chan->fsc.attr = fsl_edma3_get_tcd_attr + (cfg->dst_addr_width); + } else { + return -EINVAL; + } + return 0; +} + +static size_t fsl_edma3_desc_residue(struct fsl_edma3_chan *fsl_chan, + struct virt_dma_desc *vdesc, bool in_progress) +{ + struct fsl_edma3_desc *edesc = fsl_chan->edesc; + void __iomem *addr = fsl_chan->membase; + enum dma_transfer_direction dir = fsl_chan->fsc.dir; + dma_addr_t cur_addr, dma_addr; + size_t len, size; + int i; + + /* calculate the total size in this desc */ + for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++) + len += le32_to_cpu(edesc->tcd[i].vtcd->nbytes) + * le16_to_cpu(edesc->tcd[i].vtcd->biter); + + if (!in_progress) + return len; + + if (dir == DMA_MEM_TO_DEV) + cur_addr = readl(addr + EDMA_TCD_SADDR); + else + cur_addr = readl(addr + EDMA_TCD_DADDR); + + /* figure out the finished and calculate the residue */ + for (i = 0; i < fsl_chan->edesc->n_tcds; i++) { + size = le32_to_cpu(edesc->tcd[i].vtcd->nbytes) + * le16_to_cpu(edesc->tcd[i].vtcd->biter); + if (dir == DMA_MEM_TO_DEV) + dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->saddr); + else + dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->daddr); + + len -= size; + if (cur_addr >= dma_addr && cur_addr < dma_addr + size) { + len += dma_addr + size - cur_addr; + break; + } + } + + return len; +} + +static enum dma_status fsl_edma3_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, struct dma_tx_state *txstate) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + struct virt_dma_desc *vdesc; + enum dma_status status; + unsigned long flags; + + status = dma_cookie_status(chan, cookie, txstate); + if (status == DMA_COMPLETE) { + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + txstate->residue = fsl_chan->chn_real_count; + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + return status; + } + + if (!txstate) + return fsl_chan->status; + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + vdesc = vchan_find_desc(&fsl_chan->vchan, cookie); + if (fsl_chan->edesc && cookie == fsl_chan->edesc->vdesc.tx.cookie) + txstate->residue = fsl_edma3_desc_residue(fsl_chan, vdesc, + true); + else if (fsl_chan->edesc && vdesc) + txstate->residue = fsl_edma3_desc_residue(fsl_chan, vdesc, + false); + else + txstate->residue = 0; + + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + + return fsl_chan->status; +} + +static void fsl_edma3_set_tcd_regs(struct fsl_edma3_chan *fsl_chan, + struct fsl_edma3_hw_tcd *tcd) +{ + void __iomem *addr = fsl_chan->membase; + /* + * TCD parameters are stored in struct fsl_edma3_hw_tcd in little + * endian format. However, we need to load the TCD registers in + * big- or little-endian obeying the eDMA engine model endian. + */ + writew(0, addr + EDMA_TCD_CSR); + writel(le32_to_cpu(tcd->saddr), addr + EDMA_TCD_SADDR); + writel(le32_to_cpu(tcd->daddr), addr + EDMA_TCD_DADDR); + + writew(le16_to_cpu(tcd->attr), addr + EDMA_TCD_ATTR); + writew(le16_to_cpu(tcd->soff), addr + EDMA_TCD_SOFF); + + writel(le32_to_cpu(tcd->nbytes), addr + EDMA_TCD_NBYTES); + writel(le32_to_cpu(tcd->slast), addr + EDMA_TCD_SLAST); + + writew(le16_to_cpu(tcd->citer), addr + EDMA_TCD_CITER); + writew(le16_to_cpu(tcd->biter), addr + EDMA_TCD_BITER); + writew(le16_to_cpu(tcd->doff), addr + EDMA_TCD_DOFF); + + writel(le32_to_cpu(tcd->dlast_sga), addr + EDMA_TCD_DLAST_SGA); + + /* Must clear CHa_CSR[DONE] bit before enable TCDa_CSR[ESG] */ + writel(readl(addr + EDMA_CH_CSR), addr + EDMA_CH_CSR); + + writew(le16_to_cpu(tcd->csr), addr + EDMA_TCD_CSR); +} + +static inline +void fsl_edma3_fill_tcd(struct fsl_edma3_chan *fsl_chan, + struct fsl_edma3_hw_tcd *tcd, u32 src, u32 dst, + u16 attr, u16 soff, u32 nbytes, u32 slast, u16 citer, + u16 biter, u16 doff, u32 dlast_sga, bool major_int, + bool disable_req, bool enable_sg) +{ + u16 csr = 0; + + /* + * eDMA hardware SGs require the TCDs to be stored in little + * endian format irrespective of the register endian model. + * So we put the value in little endian in memory, waiting + * for fsl_edma3_set_tcd_regs doing the swap. + */ + tcd->saddr = cpu_to_le32(src); + tcd->daddr = cpu_to_le32(dst); + + tcd->attr = cpu_to_le16(attr); + + tcd->soff = cpu_to_le16(EDMA_TCD_SOFF_SOFF(soff)); + + if (fsl_chan->is_dfifo) { + /* set mloff as -8 */ + nbytes |= EDMA_TCD_NBYTES_MLOFF(-8); + /* enable DMLOE/SMLOE */ + if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) { + nbytes |= EDMA_TCD_NBYTES_DMLOE; + nbytes &= ~EDMA_TCD_NBYTES_SMLOE; + } else { + nbytes |= EDMA_TCD_NBYTES_SMLOE; + nbytes &= ~EDMA_TCD_NBYTES_DMLOE; + } + } + + tcd->nbytes = cpu_to_le32(EDMA_TCD_NBYTES_NBYTES(nbytes)); + tcd->slast = cpu_to_le32(EDMA_TCD_SLAST_SLAST(slast)); + + tcd->citer = cpu_to_le16(EDMA_TCD_CITER_CITER(citer)); + tcd->doff = cpu_to_le16(EDMA_TCD_DOFF_DOFF(doff)); + + tcd->dlast_sga = cpu_to_le32(EDMA_TCD_DLAST_SGA_DLAST_SGA(dlast_sga)); + + tcd->biter = cpu_to_le16(EDMA_TCD_BITER_BITER(biter)); + if (major_int) + csr |= EDMA_TCD_CSR_INT_MAJOR; + + if (disable_req) + csr |= EDMA_TCD_CSR_D_REQ; + + if (enable_sg) + csr |= EDMA_TCD_CSR_E_SG; + + if (fsl_chan->is_rxchan) + csr |= EDMA_TCD_CSR_ACTIVE; + + tcd->csr = cpu_to_le16(csr); +} + +static struct fsl_edma3_desc *fsl_edma3_alloc_desc(struct fsl_edma3_chan + *fsl_chan, int sg_len) +{ + struct fsl_edma3_desc *fsl_desc; + int i; + + fsl_desc = kzalloc(sizeof(*fsl_desc) + sizeof(struct fsl_edma3_sw_tcd) + * sg_len, GFP_ATOMIC); + if (!fsl_desc) + return NULL; + + fsl_desc->echan = fsl_chan; + fsl_desc->n_tcds = sg_len; + for (i = 0; i < sg_len; i++) { + fsl_desc->tcd[i].vtcd = dma_pool_alloc(fsl_chan->tcd_pool, + GFP_ATOMIC, &fsl_desc->tcd[i].ptcd); + if (!fsl_desc->tcd[i].vtcd) + goto err; + } + return fsl_desc; + +err: + while (--i >= 0) + dma_pool_free(fsl_chan->tcd_pool, fsl_desc->tcd[i].vtcd, + fsl_desc->tcd[i].ptcd); + kfree(fsl_desc); + return NULL; +} + +static struct dma_async_tx_descriptor *fsl_edma3_prep_dma_cyclic( + struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, + size_t period_len, enum dma_transfer_direction direction, + unsigned long flags) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + struct fsl_edma3_desc *fsl_desc; + dma_addr_t dma_buf_next; + int sg_len, i; + u32 src_addr, dst_addr, last_sg, nbytes; + u16 soff, doff, iter; + bool major_int = true; + + sg_len = buf_len / period_len; + fsl_desc = fsl_edma3_alloc_desc(fsl_chan, sg_len); + if (!fsl_desc) + return NULL; + fsl_desc->iscyclic = true; + + dma_buf_next = dma_addr; + nbytes = fsl_chan->fsc.addr_width * fsl_chan->fsc.burst; + iter = period_len / nbytes; + + for (i = 0; i < sg_len; i++) { + if (dma_buf_next >= dma_addr + buf_len) + dma_buf_next = dma_addr; + + /* get next sg's physical address */ + last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd; + + if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) { + src_addr = dma_buf_next; + dst_addr = fsl_chan->fsc.dev_addr; + soff = fsl_chan->fsc.addr_width; + if (fsl_chan->is_dfifo) + doff = 4; + else + doff = 0; + } else if (fsl_chan->fsc.dir == DMA_DEV_TO_MEM) { + src_addr = fsl_chan->fsc.dev_addr; + dst_addr = dma_buf_next; + if (fsl_chan->is_dfifo) + soff = 4; + else + soff = 0; + doff = fsl_chan->fsc.addr_width; + } else { + /* DMA_DEV_TO_DEV */ + src_addr = fsl_chan->fsc.dev2_addr; + dst_addr = fsl_chan->fsc.dev_addr; + soff = 0; + doff = 0; + major_int = false; + } + + fsl_edma3_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, + dst_addr, fsl_chan->fsc.attr, soff, nbytes, 0, + iter, iter, doff, last_sg, major_int, false, true); + dma_buf_next += period_len; + } + + return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); +} + +static struct dma_async_tx_descriptor *fsl_edma3_prep_slave_sg( + struct dma_chan *chan, struct scatterlist *sgl, + unsigned int sg_len, enum dma_transfer_direction direction, + unsigned long flags, void *context) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + struct fsl_edma3_desc *fsl_desc; + struct scatterlist *sg; + u32 src_addr, dst_addr, last_sg, nbytes; + u16 soff, doff, iter; + int i; + + if (!is_slave_direction(fsl_chan->fsc.dir)) + return NULL; + + fsl_desc = fsl_edma3_alloc_desc(fsl_chan, sg_len); + if (!fsl_desc) + return NULL; + fsl_desc->iscyclic = false; + + nbytes = fsl_chan->fsc.addr_width * fsl_chan->fsc.burst; + for_each_sg(sgl, sg, sg_len, i) { + /* get next sg's physical address */ + last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd; + + if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) { + src_addr = sg_dma_address(sg); + dst_addr = fsl_chan->fsc.dev_addr; + soff = fsl_chan->fsc.addr_width; + doff = 0; + } else if (fsl_chan->fsc.dir == DMA_DEV_TO_MEM) { + src_addr = fsl_chan->fsc.dev_addr; + dst_addr = sg_dma_address(sg); + soff = 0; + doff = fsl_chan->fsc.addr_width; + } else { + /* DMA_DEV_TO_DEV */ + src_addr = fsl_chan->fsc.dev2_addr; + dst_addr = fsl_chan->fsc.dev_addr; + soff = 0; + doff = 0; + } + + iter = sg_dma_len(sg) / nbytes; + if (i < sg_len - 1) { + last_sg = fsl_desc->tcd[(i + 1)].ptcd; + fsl_edma3_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, + src_addr, dst_addr, fsl_chan->fsc.attr, + soff, nbytes, 0, iter, iter, doff, + last_sg, false, false, true); + } else { + last_sg = 0; + fsl_edma3_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, + src_addr, dst_addr, fsl_chan->fsc.attr, + soff, nbytes, 0, iter, iter, doff, + last_sg, true, true, false); + } + } + + return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); +} + +static void fsl_edma3_xfer_desc(struct fsl_edma3_chan *fsl_chan) +{ + struct virt_dma_desc *vdesc; + + vdesc = vchan_next_desc(&fsl_chan->vchan); + if (!vdesc) + return; + fsl_chan->edesc = to_fsl_edma3_desc(vdesc); + fsl_edma3_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd); + fsl_edma3_enable_request(fsl_chan); + fsl_chan->status = DMA_IN_PROGRESS; + fsl_chan->idle = false; +} + +static size_t fsl_edma3_desc_residue(struct fsl_edma3_chan *fsl_chan, + struct virt_dma_desc *vdesc, bool in_progress); + +static void fsl_edma3_get_realcnt(struct fsl_edma3_chan *fsl_chan) +{ + fsl_chan->chn_real_count = fsl_edma3_desc_residue(fsl_chan, NULL, true); +} + +static irqreturn_t fsl_edma3_tx_handler(int irq, void *dev_id) +{ + struct fsl_edma3_chan *fsl_chan = dev_id; + unsigned int intr; + void __iomem *base_addr; + + spin_lock(&fsl_chan->vchan.lock); + + /* Ignore this interrupt since channel has been freeed with power off */ + if (!fsl_chan->edesc && !fsl_chan->tcd_pool) + goto irq_handled; + + base_addr = fsl_chan->membase; + + intr = readl(base_addr + EDMA_CH_INT); + if (!intr) + goto irq_handled; + + writel(1, base_addr + EDMA_CH_INT); + + /* Ignore this interrupt since channel has been disabled already */ + if (!fsl_chan->edesc) + goto irq_handled; + + if (!fsl_chan->edesc->iscyclic) { + fsl_edma3_get_realcnt(fsl_chan); + list_del(&fsl_chan->edesc->vdesc.node); + vchan_cookie_complete(&fsl_chan->edesc->vdesc); + fsl_chan->edesc = NULL; + fsl_chan->status = DMA_COMPLETE; + fsl_chan->idle = true; + } else { + vchan_cyclic_callback(&fsl_chan->edesc->vdesc); + } + + if (!fsl_chan->edesc) + fsl_edma3_xfer_desc(fsl_chan); +irq_handled: + spin_unlock(&fsl_chan->vchan.lock); + + return IRQ_HANDLED; +} + +static void fsl_edma3_issue_pending(struct dma_chan *chan) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + unsigned long flags; + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + + if (unlikely(fsl_chan->pm_state != RUNNING)) { + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + /* cannot submit due to suspend */ + return; + } + + if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->edesc) + fsl_edma3_xfer_desc(fsl_chan); + + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); +} + +static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + struct fsl_edma3_engine *fsl_edma3 = ofdma->of_dma_data; + struct dma_chan *chan, *_chan; + struct fsl_edma3_chan *fsl_chan; + + if (dma_spec->args_count != 3) + return NULL; + + mutex_lock(&fsl_edma3->fsl_edma3_mutex); + list_for_each_entry_safe(chan, _chan, &fsl_edma3->dma_dev.channels, + device_node) { + if (chan->client_count) + continue; + + fsl_chan = to_fsl_edma3_chan(chan); + if (fsl_chan->hw_chanid == dma_spec->args[0]) { + chan = dma_get_slave_channel(chan); + chan->device->privatecnt++; + fsl_chan->priority = dma_spec->args[1]; + fsl_chan->is_rxchan = dma_spec->args[2] & ARGS_RX; + fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE; + fsl_chan->is_dfifo = dma_spec->args[2] & ARGS_DFIFO; + mutex_unlock(&fsl_edma3->fsl_edma3_mutex); + return chan; + } + } + mutex_unlock(&fsl_edma3->fsl_edma3_mutex); + return NULL; +} + +static int fsl_edma3_alloc_chan_resources(struct dma_chan *chan) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + struct platform_device *pdev = fsl_chan->pdev; + int ret; + + fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev, + sizeof(struct fsl_edma3_hw_tcd), + 32, 0); + pm_runtime_get_sync(fsl_chan->dev); + /* clear meaningless pending irq anyway */ + if (readl(fsl_chan->membase + EDMA_CH_INT)) + writel(1, fsl_chan->membase + EDMA_CH_INT); + + ret = devm_request_irq(&pdev->dev, fsl_chan->txirq, + fsl_edma3_tx_handler, fsl_chan->edma3->irqflag, + fsl_chan->txirq_name, fsl_chan); + if (ret) { + dev_err(&pdev->dev, "Can't register %s IRQ.\n", + fsl_chan->txirq_name); + return ret; + } + + return 0; +} + +static void fsl_edma3_free_chan_resources(struct dma_chan *chan) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + unsigned long flags; + LIST_HEAD(head); + + devm_free_irq(&fsl_chan->pdev->dev, fsl_chan->txirq, fsl_chan); + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + fsl_edma3_disable_request(fsl_chan); + fsl_chan->edesc = NULL; + vchan_get_all_descriptors(&fsl_chan->vchan, &head); + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + + vchan_dma_desc_free_list(&fsl_chan->vchan, &head); + dma_pool_destroy(fsl_chan->tcd_pool); + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + fsl_chan->tcd_pool = NULL; + fsl_chan->used = false; + /* Clear interrupt before power off */ + if (readl(fsl_chan->membase + EDMA_CH_INT)) + writel(1, fsl_chan->membase + EDMA_CH_INT); + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + + pm_runtime_put_sync(fsl_chan->dev); +} + +static void fsl_edma3_synchronize(struct dma_chan *chan) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + + vchan_synchronize(&fsl_chan->vchan); +} + +static struct device *fsl_edma3_attach_pd(struct device *dev, + struct device_node *np, int index) +{ + const char *domn = "edma0-chan01"; + struct device *pd_chan; + struct device_link *link; + int ret; + + ret = of_property_read_string_index(np, "power-domain-names", index, + &domn); + if (ret) { + dev_err(dev, "parse power-domain-names error.(%d)\n", ret); + return NULL; + } + + pd_chan = dev_pm_domain_attach_by_name(dev, domn); + if (!pd_chan) + return NULL; + + link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS | + DL_FLAG_PM_RUNTIME | + DL_FLAG_RPM_ACTIVE); + if (IS_ERR(link)) { + dev_err(dev, "Failed to add device_link to %s: %ld\n", domn, + PTR_ERR(link)); + return NULL; + } + + return pd_chan; +} + +static int fsl_edma3_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct fsl_edma3_engine *fsl_edma3; + struct fsl_edma3_chan *fsl_chan; + struct resource *res; + int len, chans; + int ret, i; + + ret = of_property_read_u32(np, "dma-channels", &chans); + if (ret) { + dev_err(&pdev->dev, "Can't get dma-channels.\n"); + return ret; + } + + len = sizeof(*fsl_edma3) + sizeof(*fsl_chan) * chans; + fsl_edma3 = devm_kzalloc(&pdev->dev, len, GFP_KERNEL); + if (!fsl_edma3) + return -ENOMEM; + + /* Audio edma rx/tx channel shared interrupt */ + if (of_property_read_bool(np, "shared-interrupt")) + fsl_edma3->irqflag = IRQF_SHARED; + + fsl_edma3->swap = of_device_is_compatible(np, "fsl,imx8qm-adma"); + fsl_edma3->n_chans = chans; + + INIT_LIST_HEAD(&fsl_edma3->dma_dev.channels); + for (i = 0; i < fsl_edma3->n_chans; i++) { + struct fsl_edma3_chan *fsl_chan = &fsl_edma3->chans[i]; + const char *txirq_name; + char chanid[3], id_len = 0; + char *p = chanid; + unsigned long val; + + fsl_chan->edma3 = fsl_edma3; + fsl_chan->pdev = pdev; + fsl_chan->pm_state = RUNNING; + fsl_chan->idle = true; + /* Get per channel membase */ + res = platform_get_resource(pdev, IORESOURCE_MEM, i); + fsl_chan->membase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(fsl_chan->membase)) + return PTR_ERR(fsl_chan->membase); + + /* Get the hardware chanel id by the channel membase + * channel0:0x10000, channel1:0x20000... total 32 channels + */ + fsl_chan->hw_chanid = (res->start >> 16) & 0x1f; + + ret = of_property_read_string_index(np, "interrupt-names", i, + &txirq_name); + if (ret) { + dev_err(&pdev->dev, "read interrupt-names fail.\n"); + return ret; + } + /* Get channel id length from dts, one-digit or double-digit */ + id_len = strlen(txirq_name) - strlen(CHAN_PREFIX) - + strlen(CHAN_POSFIX); + if (id_len > 2) { + dev_err(&pdev->dev, "%s is edmaX-chanX-tx in dts?\n", + res->name); + return -EINVAL; + } + /* Grab channel id from txirq_name */ + strncpy(p, txirq_name + strlen(CHAN_PREFIX), id_len); + *(p + id_len) = '\0'; + + /* check if the channel id match well with hw_chanid */ + ret = kstrtoul(chanid, 0, &val); + if (ret || val != fsl_chan->hw_chanid) { + dev_err(&pdev->dev, "%s,wrong id?\n", txirq_name); + return -EINVAL; + } + + /* request channel irq */ + fsl_chan->txirq = platform_get_irq_byname(pdev, txirq_name); + if (fsl_chan->txirq < 0) { + dev_err(&pdev->dev, "Can't get %s irq.\n", txirq_name); + return fsl_chan->txirq; + } + + memcpy(fsl_chan->txirq_name, txirq_name, strlen(txirq_name)); + + fsl_chan->vchan.desc_free = fsl_edma3_free_desc; + vchan_init(&fsl_chan->vchan, &fsl_edma3->dma_dev); + fsl_chan->used = false; + } + + mutex_init(&fsl_edma3->fsl_edma3_mutex); + + dma_cap_set(DMA_PRIVATE, fsl_edma3->dma_dev.cap_mask); + dma_cap_set(DMA_SLAVE, fsl_edma3->dma_dev.cap_mask); + dma_cap_set(DMA_CYCLIC, fsl_edma3->dma_dev.cap_mask); + + fsl_edma3->dma_dev.dev = &pdev->dev; + fsl_edma3->dma_dev.device_alloc_chan_resources + = fsl_edma3_alloc_chan_resources; + fsl_edma3->dma_dev.device_free_chan_resources + = fsl_edma3_free_chan_resources; + fsl_edma3->dma_dev.device_tx_status = fsl_edma3_tx_status; + fsl_edma3->dma_dev.device_prep_slave_sg = fsl_edma3_prep_slave_sg; + fsl_edma3->dma_dev.device_prep_dma_cyclic = fsl_edma3_prep_dma_cyclic; + fsl_edma3->dma_dev.device_config = fsl_edma3_slave_config; + fsl_edma3->dma_dev.device_pause = fsl_edma3_pause; + fsl_edma3->dma_dev.device_resume = fsl_edma3_resume; + fsl_edma3->dma_dev.device_terminate_all = fsl_edma3_terminate_all; + fsl_edma3->dma_dev.device_issue_pending = fsl_edma3_issue_pending; + fsl_edma3->dma_dev.device_synchronize = fsl_edma3_synchronize; + + fsl_edma3->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS; + fsl_edma3->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS; + fsl_edma3->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | + BIT(DMA_MEM_TO_DEV) | + BIT(DMA_DEV_TO_DEV); + + platform_set_drvdata(pdev, fsl_edma3); + + ret = dma_async_device_register(&fsl_edma3->dma_dev); + if (ret) { + dev_err(&pdev->dev, "Can't register Freescale eDMA engine.\n"); + return ret; + } + /* Attach power domains from dts for each dma chanel device */ + for (i = 0; i < fsl_edma3->n_chans; i++) { + struct fsl_edma3_chan *fsl_chan = &fsl_edma3->chans[i]; + struct device *dev; + + dev = fsl_edma3_attach_pd(&pdev->dev, np, i); + if (!dev) { + dev_err(dev, "edma channel attach failed.\n"); + return -EINVAL; + } + + fsl_chan->dev = dev; + /* clear meaningless pending irq anyway */ + writel(1, fsl_chan->membase + EDMA_CH_INT); + pm_runtime_put_sync(dev); + } + + ret = of_dma_controller_register(np, fsl_edma3_xlate, fsl_edma3); + if (ret) { + dev_err(&pdev->dev, "Can't register Freescale eDMA of_dma.\n"); + dma_async_device_unregister(&fsl_edma3->dma_dev); + return ret; + } + + pm_runtime_dont_use_autosuspend(&pdev->dev); + pm_runtime_enable(&pdev->dev); + + return 0; +} + +static int fsl_edma3_remove(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct fsl_edma3_engine *fsl_edma3 = platform_get_drvdata(pdev); + + of_dma_controller_free(np); + dma_async_device_unregister(&fsl_edma3->dma_dev); + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int fsl_edma3_suspend_late(struct device *dev) +{ + struct fsl_edma3_engine *fsl_edma = dev_get_drvdata(dev); + struct fsl_edma3_chan *fsl_chan; + unsigned long flags; + void __iomem *addr; + int i; + + for (i = 0; i < fsl_edma->n_chans; i++) { + fsl_chan = &fsl_edma->chans[i]; + addr = fsl_chan->membase; + + if (!fsl_chan->used) + continue; + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + fsl_edma->edma_regs[i].csr = readl(addr + EDMA_CH_CSR); + fsl_edma->edma_regs[i].sbr = readl(addr + EDMA_CH_SBR); + /* Make sure chan is idle or will force disable. */ + if (unlikely(!fsl_chan->idle)) { + dev_warn(dev, "WARN: There is non-idle channel."); + fsl_edma3_disable_request(fsl_chan); + } + fsl_chan->pm_state = SUSPENDED; + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + } + + return 0; +} + +static int fsl_edma3_resume_early(struct device *dev) +{ + struct fsl_edma3_engine *fsl_edma = dev_get_drvdata(dev); + struct fsl_edma3_chan *fsl_chan; + void __iomem *addr; + unsigned long flags; + int i; + + for (i = 0; i < fsl_edma->n_chans; i++) { + fsl_chan = &fsl_edma->chans[i]; + addr = fsl_chan->membase; + + if (!fsl_chan->used) + continue; + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + writel(fsl_edma->edma_regs[i].csr, addr + EDMA_CH_CSR); + writel(fsl_edma->edma_regs[i].sbr, addr + EDMA_CH_SBR); + /* restore tcd if this channel not terminated before suspend */ + if (fsl_chan->edesc) + fsl_edma3_set_tcd_regs(fsl_chan, + fsl_chan->edesc->tcd[0].vtcd); + fsl_chan->pm_state = RUNNING; + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + } + + return 0; +} +#endif + +static const struct dev_pm_ops fsl_edma3_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(fsl_edma3_suspend_late, + fsl_edma3_resume_early) +}; + +static const struct of_device_id fsl_edma3_dt_ids[] = { + { .compatible = "fsl,imx8qm-edma", }, + { .compatible = "fsl,imx8qm-adma", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, fsl_edma3_dt_ids); + +static struct platform_driver fsl_edma3_driver = { + .driver = { + .name = "fsl-edma-v3", + .of_match_table = fsl_edma3_dt_ids, + .pm = &fsl_edma3_pm_ops, + }, + .probe = fsl_edma3_probe, + .remove = fsl_edma3_remove, +}; + +static int __init fsl_edma3_init(void) +{ + return platform_driver_register(&fsl_edma3_driver); +} +fs_initcall(fsl_edma3_init); + +static void __exit fsl_edma3_exit(void) +{ + platform_driver_unregister(&fsl_edma3_driver); +} +module_exit(fsl_edma3_exit); + +MODULE_ALIAS("platform:fsl-edma3"); +MODULE_DESCRIPTION("Freescale eDMA-V3 engine driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/dma/fsl-edma.c b/drivers/dma/fsl-edma.c index 6760ae4b295693..5d2f2274492377 100644 --- a/drivers/dma/fsl-edma.c +++ b/drivers/dma/fsl-edma.c @@ -53,6 +53,7 @@ static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id) } if (!fsl_chan->edesc->iscyclic) { + fsl_edma_get_realcnt(fsl_chan); list_del(&fsl_chan->edesc->vdesc.node); vchan_cookie_complete(&fsl_chan->edesc->vdesc); fsl_chan->edesc = NULL; @@ -240,6 +241,13 @@ static struct fsl_edma_drvdata vf610_data = { .setup_irq = fsl_edma_irq_init, }; +static struct fsl_edma_drvdata ls1028a_data = { + .version = v1, + .dmamuxs = DMAMUX_NR, + .mux_swap = true, + .setup_irq = fsl_edma_irq_init, +}; + static struct fsl_edma_drvdata imx7ulp_data = { .version = v3, .dmamuxs = 1, @@ -249,6 +257,7 @@ static struct fsl_edma_drvdata imx7ulp_data = { static const struct of_device_id fsl_edma_dt_ids[] = { { .compatible = "fsl,vf610-edma", .data = &vf610_data}, + { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data}, { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data}, { /* sentinel */ } }; diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c index 67736c801f3caa..09ae4282ad5679 100644 --- a/drivers/dma/imx-sdma.c +++ b/drivers/dma/imx-sdma.c @@ -8,7 +8,8 @@ // // Based on code from Freescale: // -// Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. +// Copyright 2004-2016 Freescale Semiconductor, Inc. All Rights Reserved. +// Copyright 2018 NXP. #include #include @@ -23,10 +24,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -74,6 +77,9 @@ #define SDMA_CHNENBL0_IMX35 0x200 #define SDMA_CHNENBL0_IMX31 0x080 #define SDMA_CHNPRI_0 0x100 +#define SDMA_DONE0_CONFIG 0x1000 +#define SDMA_DONE0_CONFIG_DONE_SEL 0x7 +#define SDMA_DONE0_CONFIG_DONE_DIS 0x6 /* * Buffer descriptor status values. @@ -168,6 +174,8 @@ #define SDMA_WATERMARK_LEVEL_SPDIF BIT(10) #define SDMA_WATERMARK_LEVEL_SP BIT(11) #define SDMA_WATERMARK_LEVEL_DP BIT(12) +#define SDMA_WATERMARK_LEVEL_SD BIT(13) +#define SDMA_WATERMARK_LEVEL_DD BIT(14) #define SDMA_WATERMARK_LEVEL_HWML (0xFF << 16) #define SDMA_WATERMARK_LEVEL_LWE BIT(28) #define SDMA_WATERMARK_LEVEL_HWE BIT(29) @@ -175,12 +183,17 @@ #define SDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ + BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) #define SDMA_DMA_DIRECTIONS (BIT(DMA_DEV_TO_MEM) | \ BIT(DMA_MEM_TO_DEV) | \ BIT(DMA_DEV_TO_DEV)) +#define SDMA_WATERMARK_LEVEL_FIFOS_OFF 12 +#define SDMA_WATERMARK_LEVEL_SW_DONE BIT(23) +#define SDMA_WATERMARK_LEVEL_SW_DONE_SEL_OFF 24 + /* * Mode/Count of data node descriptors - IPCv2 */ @@ -360,6 +373,7 @@ struct sdma_desc { struct sdma_channel { struct virt_dma_chan vc; struct sdma_desc *desc; + struct list_head terminated_node; struct sdma_engine *sdma; unsigned int channel; enum dma_transfer_direction direction; @@ -377,9 +391,14 @@ struct sdma_channel { unsigned long watermark_level; u32 shp_addr, per_addr; enum dma_status status; - bool context_loaded; struct imx_dma_data data; struct work_struct terminate_worker; + bool is_ram_script; + bool src_dualfifo; + bool dst_dualfifo; + unsigned int fifo_num; + bool sw_done; + u32 sw_done_sel; }; #define IMX_DMA_SG_LOOP BIT(0) @@ -389,6 +408,15 @@ struct sdma_channel { #define MXC_SDMA_MIN_PRIORITY 1 #define MXC_SDMA_MAX_PRIORITY 7 +/* + * 0x78(SDMA_XTRIG_CONF2+4)~0x100(SDMA_CHNPRI_O) registers are reserved and + * can't be accessed. Skip these register touch in suspend/resume. Also below + * two macros are only used on i.mx6sx. + */ +#define MXC_SDMA_RESERVED_REG (SDMA_CHNPRI_0 - SDMA_XTRIG_CONF2 - 4) +#define MXC_SDMA_SAVED_REG_NUM (((SDMA_CHNENBL0_IMX35 + 4 * 48) - \ + MXC_SDMA_RESERVED_REG) / 4) + #define SDMA_FIRMWARE_MAGIC 0x414d4453 /** @@ -420,6 +448,15 @@ struct sdma_driver_data { int num_events; struct sdma_script_start_addrs *script_addrs; bool check_ratio; + /* + * ecspi ERR009165 fixed should be done in sdma script + * and it be fixed in soc from i.mx6ul. + * please get more information from below link: + * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf + */ + bool ecspi_fixed; + bool has_done0; + bool pm_runtime; }; struct sdma_engine { @@ -427,9 +464,14 @@ struct sdma_engine { struct device_dma_parameters dma_parms; struct sdma_channel channel[MAX_DMA_CHANNELS]; struct sdma_channel_control *channel_control; + u32 save_regs[MXC_SDMA_SAVED_REG_NUM]; + u32 save_done0_regs[2]; + const char *fw_name; void __iomem *regs; struct sdma_context_data *context; dma_addr_t context_phys; + dma_addr_t ccb_phys; + bool is_on; struct dma_device dma_device; struct clk *clk_ipg; struct clk *clk_ahb; @@ -444,12 +486,21 @@ struct sdma_engine { struct sdma_buffer_descriptor *bd0; /* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/ bool clk_ratio; + struct gen_pool *iram_pool; + bool fw_loaded; + u32 fw_fail; + unsigned short ram_code_start; }; static int sdma_config_write(struct dma_chan *chan, struct dma_slave_config *dmaengine_cfg, enum dma_transfer_direction direction); +static int sdma_get_firmware(struct sdma_engine *sdma, + const char *fw_name); +static int sdma_get_firmware_wait(struct sdma_engine *sdma, + const char *fw_name); + static struct sdma_driver_data sdma_imx31 = { .chnenbl0 = SDMA_CHNENBL0_IMX31, .num_events = 32, @@ -540,6 +591,31 @@ static struct sdma_driver_data sdma_imx6q = { .script_addrs = &sdma_script_imx6q, }; +static struct sdma_script_start_addrs sdma_script_imx6sx = { + .ap_2_ap_addr = 642, + .uart_2_mcu_addr = 817, + .mcu_2_app_addr = 747, + .uartsh_2_mcu_addr = 1032, + .mcu_2_shp_addr = 960, + .app_2_mcu_addr = 683, + .shp_2_mcu_addr = 891, + .spdif_2_mcu_addr = 1100, + .mcu_2_spdif_addr = 1134, +}; + +static struct sdma_driver_data sdma_imx6sx = { + .chnenbl0 = SDMA_CHNENBL0_IMX35, + .num_events = 48, + .script_addrs = &sdma_script_imx6sx, +}; + +static struct sdma_driver_data sdma_imx6ul = { + .chnenbl0 = SDMA_CHNENBL0_IMX35, + .num_events = 48, + .script_addrs = &sdma_script_imx6sx, + .ecspi_fixed = true, +}; + static struct sdma_script_start_addrs sdma_script_imx7d = { .ap_2_ap_addr = 644, .uart_2_mcu_addr = 819, @@ -563,6 +639,17 @@ static struct sdma_driver_data sdma_imx8mq = { .num_events = 48, .script_addrs = &sdma_script_imx7d, .check_ratio = 1, + .ecspi_fixed = true, +}; + +static struct sdma_driver_data sdma_imx8mp = { + .chnenbl0 = SDMA_CHNENBL0_IMX35, + .num_events = 48, + .script_addrs = &sdma_script_imx7d, + .check_ratio = 1, + .ecspi_fixed = true, + .has_done0 = true, + .pm_runtime = true, }; static const struct platform_device_id sdma_devtypes[] = { @@ -584,12 +671,21 @@ static const struct platform_device_id sdma_devtypes[] = { }, { .name = "imx6q-sdma", .driver_data = (unsigned long)&sdma_imx6q, + }, { + .name = "imx6sx-sdma", + .driver_data = (unsigned long)&sdma_imx6sx, }, { .name = "imx7d-sdma", .driver_data = (unsigned long)&sdma_imx7d, + }, { + .name = "imx6ul-sdma", + .driver_data = (unsigned long)&sdma_imx6ul, }, { .name = "imx8mq-sdma", .driver_data = (unsigned long)&sdma_imx8mq, + }, { + .name = "imx8mp-sdma", + .driver_data = (unsigned long)&sdma_imx8mp, }, { /* sentinel */ } @@ -603,8 +699,11 @@ static const struct of_device_id sdma_dt_ids[] = { { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, }, { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, }, { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, }, + { .compatible = "fsl,imx6sx-sdma", .data = &sdma_imx6sx, }, { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, }, + { .compatible = "fsl,imx6ul-sdma", .data = &sdma_imx6ul, }, { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, }, + { .compatible = "fsl,imx8mp-sdma", .data = &sdma_imx8mp, }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, sdma_dt_ids); @@ -695,10 +794,13 @@ static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, int ret; unsigned long flags; - buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL); - if (!buf_virt) { + if (sdma->iram_pool) + buf_virt = gen_pool_dma_alloc(sdma->iram_pool, size, &buf_phys); + else + buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, + GFP_KERNEL); + if (!buf_virt) return -ENOMEM; - } spin_lock_irqsave(&sdma->channel_0_lock, flags); @@ -714,7 +816,10 @@ static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, spin_unlock_irqrestore(&sdma->channel_0_lock, flags); - dma_free_coherent(sdma->dev, size, buf_virt, buf_phys); + if (sdma->iram_pool) + gen_pool_free(sdma->iram_pool, (unsigned long)buf_virt, size); + else + dma_free_coherent(sdma->dev, size, buf_virt, buf_phys); return ret; } @@ -729,6 +834,21 @@ static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event) val = readl_relaxed(sdma->regs + chnenbl); __set_bit(channel, &val); writel_relaxed(val, sdma->regs + chnenbl); + + /* Set SDMA_DONEx_CONFIG is sw_done enabled */ + if (sdmac->sw_done) { + u32 offset = SDMA_DONE0_CONFIG + sdmac->sw_done_sel / 4; + u32 done_sel = SDMA_DONE0_CONFIG_DONE_SEL + + ((sdmac->sw_done_sel % 4) << 3); + u32 sw_done_dis = SDMA_DONE0_CONFIG_DONE_DIS + + ((sdmac->sw_done_sel % 4) << 3); + + val = readl_relaxed(sdma->regs + offset); + __set_bit(done_sel, &val); + __clear_bit(sw_done_dis, &val); + writel_relaxed(val, sdma->regs + offset); + } + } static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) @@ -852,6 +972,9 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id) struct sdma_engine *sdma = dev_id; unsigned long stat; + clk_enable(sdma->clk_ipg); + clk_enable(sdma->clk_ahb); + stat = readl_relaxed(sdma->regs + SDMA_H_INTR); writel_relaxed(stat, sdma->regs + SDMA_H_INTR); /* channel 0 is special and not handled here, see run_channel0() */ @@ -866,7 +989,10 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id) desc = sdmac->desc; if (desc) { if (sdmac->flags & IMX_DMA_SG_LOOP) { - sdma_update_channel_loop(sdmac); + if (sdmac->peripheral_type != IMX_DMATYPE_HDMI) + sdma_update_channel_loop(sdmac); + else + vchan_cyclic_callback(&desc->vd); } else { mxc_sdma_handle_channel_normal(sdmac); vchan_cookie_complete(&desc->vd); @@ -878,6 +1004,9 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id) __clear_bit(channel, &stat); } + clk_disable(sdma->clk_ipg); + clk_disable(sdma->clk_ahb); + return IRQ_HANDLED; } @@ -925,6 +1054,10 @@ static void sdma_get_pc(struct sdma_channel *sdmac, emi_2_per = sdma->script_addrs->mcu_2_ata_addr; break; case IMX_DMATYPE_CSPI: + per_2_emi = sdma->script_addrs->app_2_mcu_addr; + emi_2_per = sdma->script_addrs->mcu_2_ecspi_addr; + sdmac->is_ram_script = true; + break; case IMX_DMATYPE_EXT: case IMX_DMATYPE_SSI: case IMX_DMATYPE_SAI: @@ -934,6 +1067,7 @@ static void sdma_get_pc(struct sdma_channel *sdmac, case IMX_DMATYPE_SSI_DUAL: per_2_emi = sdma->script_addrs->ssish_2_mcu_addr; emi_2_per = sdma->script_addrs->mcu_2_ssish_addr; + sdmac->is_ram_script = true; break; case IMX_DMATYPE_SSI_SP: case IMX_DMATYPE_MMC: @@ -948,11 +1082,13 @@ static void sdma_get_pc(struct sdma_channel *sdmac, per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; per_2_per = sdma->script_addrs->per_2_per_addr; + sdmac->is_ram_script = true; break; case IMX_DMATYPE_ASRC_SP: per_2_emi = sdma->script_addrs->shp_2_mcu_addr; emi_2_per = sdma->script_addrs->mcu_2_shp_addr; per_2_per = sdma->script_addrs->per_2_per_addr; + sdmac->is_ram_script = true; break; case IMX_DMATYPE_MSHC: per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; @@ -968,6 +1104,14 @@ static void sdma_get_pc(struct sdma_channel *sdmac, case IMX_DMATYPE_IPU_MEMORY: emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; break; + case IMX_DMATYPE_HDMI: + emi_2_per = sdma->script_addrs->hdmi_dma_addr; + sdmac->is_ram_script = true; + break; + case IMX_DMATYPE_MULTI_SAI: + per_2_emi = sdma->script_addrs->sai_2_mcu_addr; + emi_2_per = sdma->script_addrs->mcu_2_sai_addr; + sdmac->is_ram_script = true; default: break; } @@ -988,9 +1132,6 @@ static int sdma_load_context(struct sdma_channel *sdmac) int ret; unsigned long flags; - if (sdmac->context_loaded) - return 0; - if (sdmac->direction == DMA_DEV_TO_MEM) load_address = sdmac->pc_from_device; else if (sdmac->direction == DMA_DEV_TO_DEV) @@ -1018,11 +1159,16 @@ static int sdma_load_context(struct sdma_channel *sdmac) /* Send by context the event mask,base address for peripheral * and watermark level */ - context->gReg[0] = sdmac->event_mask[1]; - context->gReg[1] = sdmac->event_mask[0]; - context->gReg[2] = sdmac->per_addr; - context->gReg[6] = sdmac->shp_addr; - context->gReg[7] = sdmac->watermark_level; + if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) { + context->gReg[4] = sdmac->per_addr; + context->gReg[6] = sdmac->shp_addr; + } else { + context->gReg[0] = sdmac->event_mask[1]; + context->gReg[1] = sdmac->event_mask[0]; + context->gReg[2] = sdmac->per_addr; + context->gReg[6] = sdmac->shp_addr; + context->gReg[7] = sdmac->watermark_level; + } bd0->mode.command = C0_SETDM; bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; @@ -1033,7 +1179,30 @@ static int sdma_load_context(struct sdma_channel *sdmac) spin_unlock_irqrestore(&sdma->channel_0_lock, flags); - sdmac->context_loaded = true; + return ret; +} + +static int sdma_save_restore_context(struct sdma_engine *sdma, bool save) +{ + struct sdma_context_data *context = sdma->context; + struct sdma_buffer_descriptor *bd0 = sdma->bd0; + unsigned long flags; + int ret; + + spin_lock_irqsave(&sdma->channel_0_lock, flags); + + if (save) + bd0->mode.command = C0_GETDM; + else + bd0->mode.command = C0_SETDM; + + bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; + bd0->mode.count = MAX_DMA_CHANNELS * sizeof(*context) / 4; + bd0->buffer_addr = sdma->context_phys; + bd0->ext_buffer_addr = 2048; + ret = sdma_run_channel0(sdma); + + spin_unlock_irqrestore(&sdma->channel_0_lock, flags); return ret; } @@ -1058,9 +1227,6 @@ static void sdma_channel_terminate_work(struct work_struct *work) { struct sdma_channel *sdmac = container_of(work, struct sdma_channel, terminate_worker); - unsigned long flags; - LIST_HEAD(head); - /* * According to NXP R&D team a delay of one BD SDMA cost time * (maximum is 1ms) should be added after disable of the channel @@ -1069,22 +1235,25 @@ static void sdma_channel_terminate_work(struct work_struct *work) */ usleep_range(1000, 2000); - spin_lock_irqsave(&sdmac->vc.lock, flags); - vchan_get_all_descriptors(&sdmac->vc, &head); - sdmac->desc = NULL; - spin_unlock_irqrestore(&sdmac->vc.lock, flags); - vchan_dma_desc_free_list(&sdmac->vc, &head); - sdmac->context_loaded = false; + vchan_dma_desc_free_list(&sdmac->vc, &sdmac->terminated_node); } static int sdma_disable_channel_async(struct dma_chan *chan) { struct sdma_channel *sdmac = to_sdma_chan(chan); + unsigned long flags; sdma_disable_channel(chan); - if (sdmac->desc) + spin_lock_irqsave(&sdmac->vc.lock, flags); + if (sdmac->desc) { + vchan_get_all_descriptors(&sdmac->vc, &sdmac->terminated_node); + sdmac->desc = NULL; + spin_unlock_irqrestore(&sdmac->vc.lock, flags); schedule_work(&sdmac->terminate_worker); + return 0; + } + spin_unlock_irqrestore(&sdmac->vc.lock, flags); return 0; } @@ -1136,12 +1305,36 @@ static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac) sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP; sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT; + + if (sdmac->src_dualfifo) + sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SD; + if (sdmac->dst_dualfifo) + sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DD; +} + +static void sdma_set_watermarklevel_for_sais(struct sdma_channel *sdmac) +{ + sdmac->watermark_level &= ~(0xFF << SDMA_WATERMARK_LEVEL_FIFOS_OFF | + SDMA_WATERMARK_LEVEL_SW_DONE | + 0xf << SDMA_WATERMARK_LEVEL_SW_DONE_SEL_OFF); + + if (sdmac->sw_done) + sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SW_DONE | + sdmac->sw_done_sel << + SDMA_WATERMARK_LEVEL_SW_DONE_SEL_OFF; + + /* For fifo_num + * bit 12-15 is the fifo number; + * bit 16-19 is the fifo offset, + * so here only need to shift left fifo_num 12 bit for watermake_level + */ + sdmac->watermark_level |= sdmac->fifo_num<< + SDMA_WATERMARK_LEVEL_FIFOS_OFF; } static int sdma_config_channel(struct dma_chan *chan) { struct sdma_channel *sdmac = to_sdma_chan(chan); - int ret; sdma_disable_channel(chan); @@ -1171,8 +1364,21 @@ static int sdma_config_channel(struct dma_chan *chan) if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP || sdmac->peripheral_type == IMX_DMATYPE_ASRC) sdma_set_watermarklevel_for_p2p(sdmac); - } else + } else { + /* + * ERR009165 fixed from i.mx6ul, no errata need, + * set bit31 to let sdma script skip the errata. + */ + if (sdmac->peripheral_type == IMX_DMATYPE_CSPI && + sdmac->direction == DMA_MEM_TO_DEV && + sdmac->sdma->drvdata->ecspi_fixed) + __set_bit(31, &sdmac->watermark_level); + else if (sdmac->peripheral_type == + IMX_DMATYPE_MULTI_SAI) + sdma_set_watermarklevel_for_sais(sdmac); + __set_bit(sdmac->event_id0, sdmac->event_mask); + } /* Address */ sdmac->shp_addr = sdmac->per_address; @@ -1181,9 +1387,7 @@ static int sdma_config_channel(struct dma_chan *chan) sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */ } - ret = sdma_load_context(sdmac); - - return ret; + return 0; } static int sdma_set_channel_priority(struct sdma_channel *sdmac, @@ -1206,8 +1410,12 @@ static int sdma_request_channel0(struct sdma_engine *sdma) { int ret = -EBUSY; - sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, &sdma->bd0_phys, - GFP_NOWAIT); + if (sdma->iram_pool) + sdma->bd0 = gen_pool_dma_alloc(sdma->iram_pool, PAGE_SIZE, + &sdma->bd0_phys); + else + sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, + &sdma->bd0_phys, GFP_NOWAIT); if (!sdma->bd0) { ret = -ENOMEM; goto out; @@ -1227,10 +1435,15 @@ static int sdma_request_channel0(struct sdma_engine *sdma) static int sdma_alloc_bd(struct sdma_desc *desc) { u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); + struct sdma_engine *sdma = desc->sdmac->sdma; int ret = 0; - desc->bd = dma_alloc_coherent(desc->sdmac->sdma->dev, bd_size, - &desc->bd_phys, GFP_NOWAIT); + if (sdma->iram_pool) + desc->bd = gen_pool_dma_alloc(sdma->iram_pool, PAGE_SIZE, + &desc->bd_phys); + else + desc->bd = dma_alloc_coherent(sdma->dev, bd_size, + &desc->bd_phys, GFP_NOWAIT); if (!desc->bd) { ret = -ENOMEM; goto out; @@ -1242,9 +1455,14 @@ static int sdma_alloc_bd(struct sdma_desc *desc) static void sdma_free_bd(struct sdma_desc *desc) { u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); + struct sdma_engine *sdma = desc->sdmac->sdma; - dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd, - desc->bd_phys); + if (sdma->iram_pool) + gen_pool_free(sdma->iram_pool, (unsigned long)desc->bd, + PAGE_SIZE); + else + dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd, + desc->bd_phys); } static void sdma_desc_free(struct virt_dma_desc *vd) @@ -1255,6 +1473,90 @@ static void sdma_desc_free(struct virt_dma_desc *vd) kfree(desc); } +static int sdma_runtime_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct sdma_engine *sdma = platform_get_drvdata(pdev); + + sdma->fw_loaded = false; + sdma->is_on = false; + + clk_disable(sdma->clk_ipg); + clk_disable(sdma->clk_ahb); + + /* free channel0 bd */ + if (sdma->iram_pool) + gen_pool_free(sdma->iram_pool, (unsigned long)sdma->bd0, + PAGE_SIZE); + else + dma_free_coherent(sdma->dev, PAGE_SIZE, sdma->bd0, + sdma->bd0_phys); + + return 0; +} + +static int sdma_runtime_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct sdma_engine *sdma = platform_get_drvdata(pdev); + int i, ret; + + ret = clk_enable(sdma->clk_ipg); + if (ret) + return ret; + ret = clk_enable(sdma->clk_ahb); + if (ret) + goto disable_clk_ipg; + + /* Be sure SDMA has not started yet */ + writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); + + /* disable all channels */ + for (i = 0; i < sdma->drvdata->num_events; i++) + writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); + + /* All channels have priority 0 */ + for (i = 0; i < MAX_DMA_CHANNELS; i++) + writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); + + ret = sdma_request_channel0(sdma); + if (ret) + return ret; + + sdma_config_ownership(&sdma->channel[0], false, true, false); + + /* Set Command Channel (Channel Zero) */ + writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); + + /* Set bits of CONFIG register but with static context switching */ + if (sdma->clk_ratio) + writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG); + else + writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); + + writel_relaxed(sdma->ccb_phys, sdma->regs + SDMA_H_C0PTR); + + /* Initializes channel's priorities */ + sdma_set_channel_priority(&sdma->channel[0], 7); + + if (sdma->drvdata->pm_runtime) + ret = sdma_get_firmware_wait(sdma, sdma->fw_name); + else + ret = sdma_get_firmware(sdma, sdma->fw_name); + if (ret) + dev_warn(sdma->dev, "failed to get firmware.\n"); + + sdma->is_on = true; + + return 0; + +disable_clk_ipg: + clk_disable(sdma->clk_ipg); + dev_err(sdma->dev, "initialisation failed with %d\n", ret); + + return ret; +} + static int sdma_alloc_chan_resources(struct dma_chan *chan) { struct sdma_channel *sdmac = to_sdma_chan(chan); @@ -1298,25 +1600,21 @@ static int sdma_alloc_chan_resources(struct dma_chan *chan) sdmac->peripheral_type = data->peripheral_type; sdmac->event_id0 = data->dma_request; sdmac->event_id1 = data->dma_request2; + sdmac->src_dualfifo = data->src_dualfifo; + sdmac->dst_dualfifo = data->dst_dualfifo; + /* Get software done selector if sw_done enabled */ + if (data->done_sel & BIT(31)) { + sdmac->sw_done = true; + sdmac->sw_done_sel = (data->done_sel >> 8) & 0xff; + } - ret = clk_enable(sdmac->sdma->clk_ipg); - if (ret) - return ret; - ret = clk_enable(sdmac->sdma->clk_ahb); - if (ret) - goto disable_clk_ipg; + pm_runtime_get_sync(sdmac->sdma->dev); ret = sdma_set_channel_priority(sdmac, prio); if (ret) - goto disable_clk_ahb; + return ret; return 0; - -disable_clk_ahb: - clk_disable(sdmac->sdma->clk_ahb); -disable_clk_ipg: - clk_disable(sdmac->sdma->clk_ipg); - return ret; } static void sdma_free_chan_resources(struct dma_chan *chan) @@ -1328,19 +1626,17 @@ static void sdma_free_chan_resources(struct dma_chan *chan) sdma_channel_synchronize(chan); - if (sdmac->event_id0 >= 0) - sdma_event_disable(sdmac, sdmac->event_id0); + sdma_event_disable(sdmac, sdmac->event_id0); + if (sdmac->event_id1) sdma_event_disable(sdmac, sdmac->event_id1); sdmac->event_id0 = 0; sdmac->event_id1 = 0; - sdmac->context_loaded = false; sdma_set_channel_priority(sdmac, 0); - clk_disable(sdma->clk_ipg); - clk_disable(sdma->clk_ahb); + pm_runtime_put_sync(sdma->dev); } static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac, @@ -1348,6 +1644,11 @@ static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac, { struct sdma_desc *desc; + if (!sdmac->sdma->fw_loaded && sdmac->is_ram_script) { + dev_err(sdmac->sdma->dev, "sdma firmware not ready!\n"); + goto err_out; + } + desc = kzalloc((sizeof(*desc)), GFP_NOWAIT); if (!desc) goto err_out; @@ -1363,7 +1664,7 @@ static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac, desc->sdmac = sdmac; desc->num_bd = bds; - if (sdma_alloc_bd(desc)) + if (bds && sdma_alloc_bd(desc)) goto err_desc_out; /* No slave_config called in MEMCPY case, so do here */ @@ -1484,6 +1785,9 @@ static struct dma_async_tx_descriptor *sdma_prep_slave_sg( if (count & 3 || sg->dma_address & 3) goto err_bd_out; break; + case DMA_SLAVE_BUSWIDTH_3_BYTES: + bd->mode.command = 3; + break; case DMA_SLAVE_BUSWIDTH_2_BYTES: bd->mode.command = 2; if (count & 1 || sg->dma_address & 1) @@ -1528,13 +1832,16 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( { struct sdma_channel *sdmac = to_sdma_chan(chan); struct sdma_engine *sdma = sdmac->sdma; - int num_periods = buf_len / period_len; + int num_periods = 0; int channel = sdmac->channel; int i = 0, buf = 0; struct sdma_desc *desc; dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); + if (sdmac->peripheral_type != IMX_DMATYPE_HDMI) + num_periods = buf_len / period_len; + sdma_config_write(chan, &sdmac->slave_config, direction); desc = sdma_transfer_init(sdmac, direction, num_periods); @@ -1551,6 +1858,9 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( goto err_bd_out; } + if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) + return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); + while (buf < buf_len) { struct sdma_buffer_descriptor *bd = &desc->bd[i]; int param; @@ -1598,11 +1908,15 @@ static int sdma_config_write(struct dma_chan *chan, { struct sdma_channel *sdmac = to_sdma_chan(chan); + sdmac->watermark_level = 0; + sdmac->is_ram_script = false; + if (direction == DMA_DEV_TO_MEM) { sdmac->per_address = dmaengine_cfg->src_addr; sdmac->watermark_level = dmaengine_cfg->src_maxburst * dmaengine_cfg->src_addr_width; sdmac->word_size = dmaengine_cfg->src_addr_width; + sdmac->fifo_num = dmaengine_cfg->src_fifo_num; } else if (direction == DMA_DEV_TO_DEV) { sdmac->per_address2 = dmaengine_cfg->src_addr; sdmac->per_address = dmaengine_cfg->dst_addr; @@ -1611,11 +1925,16 @@ static int sdma_config_write(struct dma_chan *chan, sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) & SDMA_WATERMARK_LEVEL_HWML; sdmac->word_size = dmaengine_cfg->dst_addr_width; + } else if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) { + sdmac->per_address = dmaengine_cfg->dst_addr; + sdmac->per_address2 = dmaengine_cfg->src_addr; + sdmac->watermark_level = 0; } else { sdmac->per_address = dmaengine_cfg->dst_addr; sdmac->watermark_level = dmaengine_cfg->dst_maxburst * dmaengine_cfg->dst_addr_width; sdmac->word_size = dmaengine_cfg->dst_addr_width; + sdmac->fifo_num = dmaengine_cfg->dst_fifo_num; } sdmac->direction = direction; return sdma_config_channel(chan); @@ -1629,11 +1948,9 @@ static int sdma_config(struct dma_chan *chan, memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg)); /* Set ENBLn earlier to make sure dma request triggered after that */ - if (sdmac->event_id0 >= 0) { - if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) - return -EINVAL; - sdma_event_enable(sdmac, sdmac->event_id0); - } + if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) + return -EINVAL; + sdma_event_enable(sdmac, sdmac->event_id0); if (sdmac->event_id1) { if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events) @@ -1694,8 +2011,8 @@ static void sdma_issue_pending(struct dma_chan *chan) #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38 -#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41 -#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42 +#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 45 +#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 46 static void sdma_add_scripts(struct sdma_engine *sdma, const struct sdma_script_start_addrs *addr) @@ -1729,12 +2046,21 @@ static void sdma_load_firmware(const struct firmware *fw, void *context) unsigned short *ram_code; if (!fw) { - dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); - /* In this case we just use the ROM firmware. */ + /* Load firmware once more time if timeout */ + if (sdma->fw_fail) + dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); + else { + request_firmware_nowait(THIS_MODULE, + FW_ACTION_HOTPLUG, sdma->fw_name, + sdma->dev, GFP_KERNEL, sdma, + sdma_load_firmware); + sdma->fw_fail++; + } + return; } - if (fw->size < sizeof(*header)) + if (fw->size < sizeof(*header) || sdma->fw_loaded) goto err_firmware; header = (struct sdma_firmware_header *)fw->data; @@ -1763,19 +2089,18 @@ static void sdma_load_firmware(const struct firmware *fw, void *context) addr = (void *)header + header->script_addrs_start; ram_code = (void *)header + header->ram_code_start; + sdma->ram_code_start = header->ram_code_start; - clk_enable(sdma->clk_ipg); - clk_enable(sdma->clk_ahb); /* download the RAM image for SDMA */ sdma_load_script(sdma, ram_code, header->ram_code_size, addr->ram_code_start_addr); - clk_disable(sdma->clk_ipg); - clk_disable(sdma->clk_ahb); sdma_add_scripts(sdma, addr); - dev_info(sdma->dev, "loaded firmware %d.%d\n", + sdma->fw_loaded = true; + + dev_info_once(sdma->dev, "loaded firmware %d.%d\n", header->version_major, header->version_minor); @@ -1861,79 +2186,51 @@ static int sdma_get_firmware(struct sdma_engine *sdma, return ret; } -static int sdma_init(struct sdma_engine *sdma) +static int sdma_get_firmware_wait(struct sdma_engine *sdma, + const char *fw_name) { - int i, ret; - dma_addr_t ccb_phys; + const struct firmware *fw = NULL; + int ret; - ret = clk_enable(sdma->clk_ipg); - if (ret) + ret = request_firmware(&fw, fw_name, sdma->dev); + if (ret < 0 || !fw) { + dev_err(sdma->dev, "unable to find firmware\n"); return ret; - ret = clk_enable(sdma->clk_ahb); - if (ret) - goto disable_clk_ipg; + } + + sdma_load_firmware(fw, (void *)sdma); + + return 0; +} + +static int sdma_init_sw(struct sdma_engine *sdma) +{ + int ret, ccbsize; if (sdma->drvdata->check_ratio && (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg))) sdma->clk_ratio = 1; - /* Be sure SDMA has not started yet */ - writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); - - sdma->channel_control = dma_alloc_coherent(sdma->dev, - MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) + - sizeof(struct sdma_context_data), - &ccb_phys, GFP_KERNEL); + ccbsize = MAX_DMA_CHANNELS * (sizeof(struct sdma_channel_control) + + sizeof(struct sdma_context_data)); + if (sdma->iram_pool) + sdma->channel_control = gen_pool_dma_alloc(sdma->iram_pool, + ccbsize, &sdma->ccb_phys); + else + sdma->channel_control = dma_alloc_coherent(sdma->dev, ccbsize, + &sdma->ccb_phys, GFP_KERNEL); if (!sdma->channel_control) { ret = -ENOMEM; - goto err_dma_alloc; + return ret; } sdma->context = (void *)sdma->channel_control + MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); - sdma->context_phys = ccb_phys + + sdma->context_phys = sdma->ccb_phys + MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); - /* disable all channels */ - for (i = 0; i < sdma->drvdata->num_events; i++) - writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); - - /* All channels have priority 0 */ - for (i = 0; i < MAX_DMA_CHANNELS; i++) - writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); - - ret = sdma_request_channel0(sdma); - if (ret) - goto err_dma_alloc; - - sdma_config_ownership(&sdma->channel[0], false, true, false); - - /* Set Command Channel (Channel Zero) */ - writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); - - /* Set bits of CONFIG register but with static context switching */ - if (sdma->clk_ratio) - writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG); - else - writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); - - writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); - - /* Initializes channel's priorities */ - sdma_set_channel_priority(&sdma->channel[0], 7); - - clk_disable(sdma->clk_ipg); - clk_disable(sdma->clk_ahb); - return 0; - -err_dma_alloc: - clk_disable(sdma->clk_ahb); -disable_clk_ipg: - clk_disable(sdma->clk_ipg); - dev_err(sdma->dev, "initialisation failed with %d\n", ret); - return ret; } static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param) @@ -1960,9 +2257,14 @@ static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec, if (dma_spec->args_count != 3) return NULL; + memset(&data, 0, sizeof(data)); + data.dma_request = dma_spec->args[0]; data.peripheral_type = dma_spec->args[1]; - data.priority = dma_spec->args[2]; + /* Get sw_done setting if sw_done enabled */ + if (dma_spec->args[2] & BIT(31)) + data.done_sel = dma_spec->args[2]; + data.priority = dma_spec->args[2] & 0xff; /* * init dma_request2 to zero, which is not used by the dts. * For P2P, dma_request2 is init from dma_request_channel(), @@ -2072,6 +2374,7 @@ static int sdma_probe(struct platform_device *pdev) sdmac->channel = i; sdmac->vc.desc_free = sdma_desc_free; + INIT_LIST_HEAD(&sdmac->terminated_node); INIT_WORK(&sdmac->terminate_worker, sdma_channel_terminate_work); /* @@ -2083,7 +2386,7 @@ static int sdma_probe(struct platform_device *pdev) vchan_init(&sdmac->vc, &sdma->dma_device); } - ret = sdma_init(sdma); + ret = sdma_init_sw(sdma); if (ret) goto err_init; @@ -2138,18 +2441,14 @@ static int sdma_probe(struct platform_device *pdev) sdma->spba_end_addr = spba_res.end; } of_node_put(spba_bus); + + sdma->iram_pool = of_gen_pool_get(np, "iram", 0); + if (sdma->iram_pool) + dev_info(&pdev->dev, "alloc bd from iram. \n"); } - /* - * Kick off firmware loading as the very last step: - * attempt to load firmware only if we're not on the error path, because - * the firmware callback requires a fully functional and allocated sdma - * instance. - */ if (pdata) { - ret = sdma_get_firmware(sdma, pdata->fw_name); - if (ret) - dev_warn(&pdev->dev, "failed to get firmware from platform data\n"); + sdma->fw_name = pdata->fw_name; } else { /* * Because that device tree does not encode ROM script address, @@ -2158,15 +2457,16 @@ static int sdma_probe(struct platform_device *pdev) */ ret = of_property_read_string(np, "fsl,sdma-ram-script-name", &fw_name); - if (ret) { + if (ret) dev_warn(&pdev->dev, "failed to get firmware name\n"); - } else { - ret = sdma_get_firmware(sdma, fw_name); - if (ret) - dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); - } + else + sdma->fw_name = fw_name; } + pm_runtime_enable(&pdev->dev); + if (!sdma->drvdata->pm_runtime) + pm_runtime_get_sync(&pdev->dev); + return 0; err_register: @@ -2188,6 +2488,7 @@ static int sdma_remove(struct platform_device *pdev) devm_free_irq(&pdev->dev, sdma->irq, sdma); dma_async_device_unregister(&sdma->dma_device); kfree(sdma->script_addrs); + pm_runtime_put_sync_suspend(sdma->dev); clk_unprepare(sdma->clk_ahb); clk_unprepare(sdma->clk_ipg); /* Kill the tasklet */ @@ -2202,10 +2503,131 @@ static int sdma_remove(struct platform_device *pdev) return 0; } +#ifdef CONFIG_PM_SLEEP +static int sdma_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct sdma_engine *sdma = platform_get_drvdata(pdev); + int i, ret = 0; + + /* Do nothing if not i.MX6SX or i.MX7D, i.MX8MP */ + if (sdma->drvdata != &sdma_imx6sx && sdma->drvdata != &sdma_imx7d + && sdma->drvdata != &sdma_imx6ul && sdma->drvdata != &sdma_imx8mp) + return 0; + + if (!sdma->is_on) + return 0; + + ret = sdma_save_restore_context(sdma, true); + if (ret) { + dev_err(sdma->dev, "save context error!\n"); + return ret; + } + + /* save regs */ + for (i = 0; i < MXC_SDMA_SAVED_REG_NUM; i++) { + /* + * 0x78(SDMA_XTRIG_CONF2+4)~0x100(SDMA_CHNPRI_O) registers are + * reserved and can't be touched. Skip these regs. + */ + if (i > SDMA_XTRIG_CONF2 / 4) + sdma->save_regs[i] = readl_relaxed(sdma->regs + + MXC_SDMA_RESERVED_REG + + 4 * i); + else + sdma->save_regs[i] = readl_relaxed(sdma->regs + 4 * i); + } + + if (sdma->drvdata->has_done0) { + for (i = 0; i < 2; i++) + sdma->save_done0_regs[i] = + readl_relaxed(sdma->regs + SDMA_DONE0_CONFIG + 4 * i); + } + + return 0; +} + +static int sdma_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct sdma_engine *sdma = platform_get_drvdata(pdev); + unsigned long timeout = jiffies + msecs_to_jiffies(2); + int i, ret; + + /* Do nothing if not i.MX6SX or i.MX7D, i.MX8MP*/ + if (sdma->drvdata != &sdma_imx6sx && sdma->drvdata != &sdma_imx7d + && sdma->drvdata != &sdma_imx6ul && sdma->drvdata != &sdma_imx8mp) + return 0; + + if (!sdma->is_on) + return 0; + + /* Do nothing if mega/fast mix not turned off */ + if (readl_relaxed(sdma->regs + SDMA_H_C0PTR)) + return 0; + + /* Firmware was lost, mark as "not ready" */ + sdma->fw_loaded = false; + + /* restore regs and load firmware */ + for (i = 0; i < MXC_SDMA_SAVED_REG_NUM; i++) { + /* + * 0x78(SDMA_XTRIG_CONF2+4)~0x100(SDMA_CHNPRI_O) registers are + * reserved and can't be touched. Skip these regs. + */ + if (i > SDMA_XTRIG_CONF2 / 4) + writel_relaxed(sdma->save_regs[i], sdma->regs + + MXC_SDMA_RESERVED_REG + 4 * i); + /* set static context switch mode before channel0 running */ + else if (i == SDMA_H_CONFIG / 4) + writel_relaxed(sdma->save_regs[i] & ~SDMA_H_CONFIG_CSM, + sdma->regs + SDMA_H_CONFIG); + else + writel_relaxed(sdma->save_regs[i], sdma->regs + 4 * i); + } + + /* restore SDMA_DONEx_CONFIG */ + if (sdma->drvdata->has_done0) { + for (i = 0; i < 2; i++) + writel_relaxed(sdma->save_done0_regs[i], + sdma->regs + SDMA_DONE0_CONFIG + 4 * i); + } + + /* prepare priority for channel0 to start */ + sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY); + + ret = sdma_get_firmware(sdma, sdma->fw_name); + if (ret) { + dev_warn(&pdev->dev, "failed to get firmware\n"); + return ret; + } + /* wait firmware loaded */ + do { + if (time_after(jiffies, timeout)) { + dev_warn(&pdev->dev, "failed to load firmware\n"); + break; + } + usleep_range(50, 500); + } while (!sdma->fw_loaded); + + ret = sdma_save_restore_context(sdma, false); + if (ret) + dev_err(sdma->dev, "restore context error!\n"); + + return ret; +} +#endif + +static const struct dev_pm_ops sdma_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(sdma_suspend, sdma_resume) + SET_RUNTIME_PM_OPS(sdma_runtime_suspend, sdma_runtime_resume, NULL) +}; + static struct platform_driver sdma_driver = { .driver = { .name = "imx-sdma", .of_match_table = sdma_dt_ids, + .pm = &sdma_pm_ops, }, .id_table = sdma_devtypes, .remove = sdma_remove, diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c index 3039bba0e4d559..9e3027114f59b9 100644 --- a/drivers/dma/mxs-dma.c +++ b/drivers/dma/mxs-dma.c @@ -25,6 +25,8 @@ #include #include #include +#include +#include #include @@ -39,6 +41,8 @@ #define dma_is_apbh(mxs_dma) ((mxs_dma)->type == MXS_DMA_APBH) #define apbh_is_old(mxs_dma) ((mxs_dma)->dev_id == IMX23_DMA) +#define MXS_DMA_RPM_TIMEOUT 50 /* ms */ + #define HW_APBHX_CTRL0 0x000 #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29) #define BM_APBH_CTRL0_APB_BURST_EN (1 << 28) @@ -118,6 +122,7 @@ struct mxs_dma_chan { enum dma_status status; unsigned int flags; bool reset; + struct dma_pool *ccw_pool; #define MXS_DMA_SG_LOOP (1 << 0) #define MXS_DMA_USE_SEMAPHORE (1 << 1) }; @@ -416,11 +421,13 @@ static int mxs_dma_alloc_chan_resources(struct dma_chan *chan) { struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; + struct device *dev = &mxs_dma->pdev->dev; int ret; - mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev, - CCW_BLOCK_SIZE, - &mxs_chan->ccw_phys, GFP_KERNEL); + mxs_chan->ccw = dma_pool_zalloc(mxs_chan->ccw_pool, + GFP_ATOMIC, + &mxs_chan->ccw_phys); + if (!mxs_chan->ccw) { ret = -ENOMEM; goto err_alloc; @@ -431,9 +438,11 @@ static int mxs_dma_alloc_chan_resources(struct dma_chan *chan) if (ret) goto err_irq; - ret = clk_prepare_enable(mxs_dma->clk); - if (ret) + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "Failed to enable clock\n"); goto err_clk; + } mxs_dma_reset_chan(chan); @@ -448,8 +457,8 @@ static int mxs_dma_alloc_chan_resources(struct dma_chan *chan) err_clk: free_irq(mxs_chan->chan_irq, mxs_dma); err_irq: - dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE, - mxs_chan->ccw, mxs_chan->ccw_phys); + dma_pool_free(mxs_chan->ccw_pool, mxs_chan->ccw, + mxs_chan->ccw_phys); err_alloc: return ret; } @@ -458,15 +467,18 @@ static void mxs_dma_free_chan_resources(struct dma_chan *chan) { struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; + struct device *dev = &mxs_dma->pdev->dev; mxs_dma_disable_chan(chan); free_irq(mxs_chan->chan_irq, mxs_dma); - dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE, - mxs_chan->ccw, mxs_chan->ccw_phys); + dma_pool_free(mxs_chan->ccw_pool, mxs_chan->ccw, + mxs_chan->ccw_phys); + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); - clk_disable_unprepare(mxs_dma->clk); } /* @@ -689,14 +701,32 @@ static enum dma_status mxs_dma_tx_status(struct dma_chan *chan, return mxs_chan->status; } -static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma) +static int mxs_dma_init_rpm(struct mxs_dma_engine *mxs_dma) +{ + struct device *dev = &mxs_dma->pdev->dev; + + pm_runtime_enable(dev); + pm_runtime_set_autosuspend_delay(dev, MXS_DMA_RPM_TIMEOUT); + pm_runtime_use_autosuspend(dev); + + return 0; +} + +static int mxs_dma_init(struct mxs_dma_engine *mxs_dma) { + struct device *dev = &mxs_dma->pdev->dev; int ret; - ret = clk_prepare_enable(mxs_dma->clk); + ret = mxs_dma_init_rpm(mxs_dma); if (ret) return ret; + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "Failed to enable clock\n"); + return ret; + } + ret = stmp_reset_block(mxs_dma->base); if (ret) goto err_out; @@ -714,7 +744,8 @@ static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma) mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET); err_out: - clk_disable_unprepare(mxs_dma->clk); + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); return ret; } @@ -729,6 +760,12 @@ static bool mxs_dma_filter_fn(struct dma_chan *chan, void *fn_param) struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; int chan_irq; + if (strcmp(chan->device->dev->driver->name, "mxs-dma")) + return false; + + if (!mxs_dma) + return false; + if (chan->chan_id != param->chan_id) return false; @@ -760,7 +797,7 @@ static struct dma_chan *mxs_dma_xlate(struct of_phandle_args *dma_spec, ofdma->of_node); } -static int __init mxs_dma_probe(struct platform_device *pdev) +static int mxs_dma_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; const struct platform_device_id *id_entry; @@ -768,6 +805,7 @@ static int __init mxs_dma_probe(struct platform_device *pdev) const struct mxs_dma_type *dma_type; struct mxs_dma_engine *mxs_dma; struct resource *iores; + struct dma_pool *ccw_pool; int ret, i; mxs_dma = devm_kzalloc(&pdev->dev, sizeof(*mxs_dma), GFP_KERNEL); @@ -815,19 +853,31 @@ static int __init mxs_dma_probe(struct platform_device *pdev) tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet, (unsigned long) mxs_chan); - /* Add the channel to mxs_chan list */ list_add_tail(&mxs_chan->chan.device_node, &mxs_dma->dma_device.channels); } + platform_set_drvdata(pdev, mxs_dma); + mxs_dma->pdev = pdev; + ret = mxs_dma_init(mxs_dma); if (ret) return ret; - mxs_dma->pdev = pdev; mxs_dma->dma_device.dev = &pdev->dev; + /* create the dma pool */ + ccw_pool = dma_pool_create("ccw_pool", + mxs_dma->dma_device.dev, + CCW_BLOCK_SIZE, 32, 0); + + for (i = 0; i < MXS_DMA_CHANNELS; i++) { + struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i]; + + mxs_chan->ccw_pool = ccw_pool; + } + /* mxs_dma gets 65535 bytes maximum sg size */ mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms; dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES); @@ -863,16 +913,83 @@ static int __init mxs_dma_probe(struct platform_device *pdev) return 0; } +static int mxs_dma_remove(struct platform_device *pdev) +{ + struct mxs_dma_engine *mxs_dma = platform_get_drvdata(pdev); + int i; + + dma_async_device_unregister(&mxs_dma->dma_device); + dma_pool_destroy(mxs_dma->mxs_chans[0].ccw_pool); + + for (i = 0; i < MXS_DMA_CHANNELS; i++) { + struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i]; + + tasklet_kill(&mxs_chan->tasklet); + mxs_chan->ccw_pool = NULL; + } + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int mxs_dma_pm_suspend(struct device *dev) +{ + int ret; + + ret = pm_runtime_force_suspend(dev); + + return ret; +} + +static int mxs_dma_pm_resume(struct device *dev) +{ + struct mxs_dma_engine *mxs_dma = dev_get_drvdata(dev); + int ret; + + ret = mxs_dma_init(mxs_dma); + if (ret) + return ret; + + return 0; +} +#endif + +int mxs_dma_runtime_suspend(struct device *dev) +{ + struct mxs_dma_engine *mxs_dma = dev_get_drvdata(dev); + + clk_disable_unprepare(mxs_dma->clk); + + return 0; +} + +int mxs_dma_runtime_resume(struct device *dev) +{ + struct mxs_dma_engine *mxs_dma = dev_get_drvdata(dev); + int ret; + + ret = clk_prepare_enable(mxs_dma->clk); + if (ret) { + dev_err(&mxs_dma->pdev->dev, "failed to enable the clock\n"); + return ret; + } + + return 0; +} + +static const struct dev_pm_ops mxs_dma_pm_ops = { + SET_RUNTIME_PM_OPS(mxs_dma_runtime_suspend, mxs_dma_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(mxs_dma_pm_suspend, mxs_dma_pm_resume) +}; + static struct platform_driver mxs_dma_driver = { .driver = { .name = "mxs-dma", + .pm = &mxs_dma_pm_ops, .of_match_table = mxs_dma_dt_ids, }, .id_table = mxs_dma_ids, + .remove = mxs_dma_remove, + .probe = mxs_dma_probe, }; - -static int __init mxs_dma_module_init(void) -{ - return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe); -} -subsys_initcall(mxs_dma_module_init); +module_platform_driver(mxs_dma_driver); diff --git a/drivers/dma/pxp/Kconfig b/drivers/dma/pxp/Kconfig new file mode 100644 index 00000000000000..76717f7d78e17a --- /dev/null +++ b/drivers/dma/pxp/Kconfig @@ -0,0 +1,22 @@ +config MXC_PXP_V2 + bool "MXC PxP V2 support" + depends on ARM + select DMA_ENGINE + help + Support the PxP (Pixel Pipeline) on i.MX6 DualLite and i.MX6 SoloLite. + If unsure, select N. + +config MXC_PXP_V3 + bool "MXC PxP V3 support" + depends on ARM + select DMA_ENGINE + help + Support the PxP V3(Pixel Pipeline) on i.MX7D. The PxP V3 supports + more functions than PxP V2, dithering, reagl/-D and etc. + If unsure, select N. + +config MXC_PXP_CLIENT_DEVICE + bool "MXC PxP Client Device" + default y + depends on MXC_PXP_V2 || MXC_PXP_V3 + diff --git a/drivers/dma/pxp/Makefile b/drivers/dma/pxp/Makefile new file mode 100644 index 00000000000000..42e4ace02fbda0 --- /dev/null +++ b/drivers/dma/pxp/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_MXC_PXP_V2) += pxp_dma_v2.o +obj-$(CONFIG_MXC_PXP_V3) += pxp_dma_v3.o +obj-$(CONFIG_MXC_PXP_CLIENT_DEVICE) += pxp_device.o diff --git a/drivers/dma/pxp/pxp_device.c b/drivers/dma/pxp/pxp_device.c new file mode 100644 index 00000000000000..2504adf1ae4a35 --- /dev/null +++ b/drivers/dma/pxp/pxp_device.c @@ -0,0 +1,897 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2010-2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BUFFER_HASH_ORDER 4 + +static struct pxp_buffer_hash bufhash; +static struct pxp_irq_info irq_info[NR_PXP_VIRT_CHANNEL]; +static int major; +static struct class *pxp_class; +static struct device *pxp_dev; + +static int pxp_ht_create(struct pxp_buffer_hash *hash, int order) +{ + unsigned long i; + unsigned long table_size; + + table_size = 1U << order; + + hash->order = order; + hash->hash_table = kmalloc(sizeof(*hash->hash_table) * table_size, GFP_KERNEL); + + if (!hash->hash_table) { + pr_err("%s: Out of memory for hash table\n", __func__); + return -ENOMEM; + } + + for (i = 0; i < table_size; i++) + INIT_HLIST_HEAD(&hash->hash_table[i]); + + return 0; +} + +static int pxp_ht_insert_item(struct pxp_buffer_hash *hash, + struct pxp_buf_obj *new) +{ + unsigned long hashkey; + struct hlist_head *h_list; + + hashkey = hash_long(new->offset >> PAGE_SHIFT, hash->order); + h_list = &hash->hash_table[hashkey]; + + spin_lock(&hash->hash_lock); + hlist_add_head_rcu(&new->item, h_list); + spin_unlock(&hash->hash_lock); + + return 0; +} + +static int pxp_ht_remove_item(struct pxp_buffer_hash *hash, + struct pxp_buf_obj *obj) +{ + spin_lock(&hash->hash_lock); + hlist_del_init_rcu(&obj->item); + spin_unlock(&hash->hash_lock); + return 0; +} + +static struct hlist_node *pxp_ht_find_key(struct pxp_buffer_hash *hash, + unsigned long key) +{ + struct pxp_buf_obj *entry; + struct hlist_head *h_list; + unsigned long hashkey; + + hashkey = hash_long(key, hash->order); + h_list = &hash->hash_table[hashkey]; + + hlist_for_each_entry_rcu(entry, h_list, item) { + if (entry->offset >> PAGE_SHIFT == key) + return &entry->item; + } + + return NULL; +} + +static void pxp_ht_destroy(struct pxp_buffer_hash *hash) +{ + kfree(hash->hash_table); + hash->hash_table = NULL; +} + +static int pxp_buffer_handle_create(struct pxp_file *file_priv, + struct pxp_buf_obj *obj, + uint32_t *handlep) +{ + int ret; + + idr_preload(GFP_KERNEL); + spin_lock(&file_priv->buffer_lock); + + ret = idr_alloc(&file_priv->buffer_idr, obj, 1, 0, GFP_NOWAIT); + + spin_unlock(&file_priv->buffer_lock); + idr_preload_end(); + + if (ret < 0) + return ret; + + *handlep = ret; + + return 0; +} + +static struct pxp_buf_obj * +pxp_buffer_object_lookup(struct pxp_file *file_priv, + uint32_t handle) +{ + struct pxp_buf_obj *obj; + + spin_lock(&file_priv->buffer_lock); + + obj = idr_find(&file_priv->buffer_idr, handle); + if (!obj) { + spin_unlock(&file_priv->buffer_lock); + return NULL; + } + + spin_unlock(&file_priv->buffer_lock); + + return obj; +} + +static int pxp_buffer_handle_delete(struct pxp_file *file_priv, + uint32_t handle) +{ + struct pxp_buf_obj *obj; + + spin_lock(&file_priv->buffer_lock); + + obj = idr_find(&file_priv->buffer_idr, handle); + if (!obj) { + spin_unlock(&file_priv->buffer_lock); + return -EINVAL; + } + + idr_remove(&file_priv->buffer_idr, handle); + spin_unlock(&file_priv->buffer_lock); + + return 0; +} + +static int pxp_channel_handle_create(struct pxp_file *file_priv, + struct pxp_chan_obj *obj, + uint32_t *handlep) +{ + int ret; + + idr_preload(GFP_KERNEL); + spin_lock(&file_priv->channel_lock); + + ret = idr_alloc(&file_priv->channel_idr, obj, 0, 0, GFP_NOWAIT); + + spin_unlock(&file_priv->channel_lock); + idr_preload_end(); + + if (ret < 0) + return ret; + + *handlep = ret; + + return 0; +} + +static struct pxp_chan_obj * +pxp_channel_object_lookup(struct pxp_file *file_priv, + uint32_t handle) +{ + struct pxp_chan_obj *obj; + + spin_lock(&file_priv->channel_lock); + + obj = idr_find(&file_priv->channel_idr, handle); + if (!obj) { + spin_unlock(&file_priv->channel_lock); + return NULL; + } + + spin_unlock(&file_priv->channel_lock); + + return obj; +} + +static int pxp_channel_handle_delete(struct pxp_file *file_priv, + uint32_t handle) +{ + struct pxp_chan_obj *obj; + + spin_lock(&file_priv->channel_lock); + + obj = idr_find(&file_priv->channel_idr, handle); + if (!obj) { + spin_unlock(&file_priv->channel_lock); + return -EINVAL; + } + + idr_remove(&file_priv->channel_idr, handle); + spin_unlock(&file_priv->channel_lock); + + return 0; +} + +static int pxp_alloc_dma_buffer(struct pxp_buf_obj *obj) +{ + obj->virtual = dma_alloc_coherent(pxp_dev, PAGE_ALIGN(obj->size), + (dma_addr_t *) (&obj->offset), + GFP_DMA | GFP_KERNEL); + pr_debug("[ALLOC] mem alloc phys_addr = 0x%lx\n", obj->offset); + + if (obj->virtual == NULL) { + printk(KERN_ERR "Physical memory allocation error!\n"); + return -1; + } + + return 0; +} + +static void pxp_free_dma_buffer(struct pxp_buf_obj *obj) +{ + if (obj->virtual != NULL) { + dma_free_coherent(pxp_dev, PAGE_ALIGN(obj->size), + obj->virtual, (dma_addr_t)obj->offset); + } +} + +static int +pxp_buffer_object_free(int id, void *ptr, void *data) +{ + struct pxp_file *file_priv = data; + struct pxp_buf_obj *obj = ptr; + int ret; + + ret = pxp_buffer_handle_delete(file_priv, obj->handle); + if (ret < 0) + return ret; + + pxp_ht_remove_item(&bufhash, obj); + pxp_free_dma_buffer(obj); + kfree(obj); + + return 0; +} + +static int +pxp_channel_object_free(int id, void *ptr, void *data) +{ + struct pxp_file *file_priv = data; + struct pxp_chan_obj *obj = ptr; + int chan_id; + + chan_id = obj->chan->chan_id; + wait_event(irq_info[chan_id].waitq, + atomic_read(&irq_info[chan_id].irq_pending) == 0); + + pxp_channel_handle_delete(file_priv, obj->handle); + dma_release_channel(obj->chan); + kfree(obj); + + return 0; +} + +static void pxp_free_buffers(struct pxp_file *file_priv) +{ + idr_for_each(&file_priv->buffer_idr, + &pxp_buffer_object_free, file_priv); + idr_destroy(&file_priv->buffer_idr); +} + +static void pxp_free_channels(struct pxp_file *file_priv) +{ + idr_for_each(&file_priv->channel_idr, + &pxp_channel_object_free, file_priv); + idr_destroy(&file_priv->channel_idr); +} + +/* Callback function triggered after PxP receives an EOF interrupt */ +static void pxp_dma_done(void *arg) +{ + struct pxp_tx_desc *tx_desc = to_tx_desc(arg); + struct dma_chan *chan = tx_desc->txd.chan; + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + int chan_id = pxp_chan->dma_chan.chan_id; + + pr_debug("DMA Done ISR, chan_id %d\n", chan_id); + + atomic_dec(&irq_info[chan_id].irq_pending); + irq_info[chan_id].hist_status = tx_desc->hist_status; + + wake_up(&(irq_info[chan_id].waitq)); +} + +static int pxp_ioc_config_chan(struct pxp_file *priv, unsigned long arg) +{ + struct scatterlist *sg; + struct pxp_tx_desc *desc; + struct dma_async_tx_descriptor *txd; + struct pxp_config_data *pxp_conf; + dma_cookie_t cookie; + int handle, chan_id; + struct dma_chan *chan; + struct pxp_chan_obj *obj; + int i = 0, j = 0, k = 0, m = 0, length, ret, sg_len; + + pxp_conf = kzalloc(sizeof(*pxp_conf), GFP_KERNEL); + if (!pxp_conf) + return -ENOMEM; + + ret = copy_from_user(pxp_conf, + (struct pxp_config_data *)arg, + sizeof(struct pxp_config_data)); + if (ret) { + kfree(pxp_conf); + return -EFAULT; + } + + handle = pxp_conf->handle; + obj = pxp_channel_object_lookup(priv, handle); + if (!obj) { + kfree(pxp_conf); + return -EINVAL; + } + chan = obj->chan; + chan_id = chan->chan_id; + + sg_len = 3; + if (pxp_conf->proc_data.engine_enable & PXP_ENABLE_WFE_A) + sg_len += 4; + if (pxp_conf->proc_data.engine_enable & PXP_ENABLE_WFE_B) + sg_len += 4; + if (pxp_conf->proc_data.engine_enable & PXP_ENABLE_DITHER) + sg_len += 4; + + sg = kmalloc(sizeof(*sg) * sg_len, GFP_KERNEL); + if (!sg) { + kfree(pxp_conf); + return -ENOMEM; + } + + sg_init_table(sg, sg_len); + + txd = chan->device->device_prep_slave_sg(chan, + sg, sg_len, + DMA_TO_DEVICE, + DMA_PREP_INTERRUPT, + NULL); + if (!txd) { + pr_err("Error preparing a DMA transaction descriptor.\n"); + kfree(pxp_conf); + kfree(sg); + return -EIO; + } + + txd->callback_param = txd; + txd->callback = pxp_dma_done; + + desc = to_tx_desc(txd); + + length = desc->len; + for (i = 0; i < length; i++) { + if (i == 0) { /* S0 */ + memcpy(&desc->proc_data, + &pxp_conf->proc_data, + sizeof(struct pxp_proc_data)); + memcpy(&desc->layer_param.s0_param, + &pxp_conf->s0_param, + sizeof(struct pxp_layer_param)); + desc = desc->next; + } else if (i == 1) { /* Output */ + memcpy(&desc->layer_param.out_param, + &pxp_conf->out_param, + sizeof(struct pxp_layer_param)); + desc = desc->next; + } else if (i == 2) { + /* OverLay */ + memcpy(&desc->layer_param.ol_param, + &pxp_conf->ol_param, + sizeof(struct pxp_layer_param)); + desc = desc->next; + } else if ((pxp_conf->proc_data.engine_enable & PXP_ENABLE_WFE_A) && (j < 4)) { + for (j = 0; j < 4; j++) { + if (j == 0) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_a_fetch_param[0], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_A_FETCH0; + } else if (j == 1) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_a_fetch_param[1], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_A_FETCH1; + } else if (j == 2) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_a_store_param[0], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_A_STORE0; + } else if (j == 3) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_a_store_param[1], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_A_STORE1; + } + + desc = desc->next; + } + + i += 4; + + } else if ((pxp_conf->proc_data.engine_enable & PXP_ENABLE_WFE_B) && (m < 4)) { + for (m = 0; m < 4; m++) { + if (m == 0) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_b_fetch_param[0], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_B_FETCH0; + } else if (m == 1) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_b_fetch_param[1], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_B_FETCH1; + } else if (m == 2) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_b_store_param[0], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_B_STORE0; + } else if (m == 3) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_b_store_param[1], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_B_STORE1; + } + + desc = desc->next; + } + + i += 4; + + } else if ((pxp_conf->proc_data.engine_enable & PXP_ENABLE_DITHER) && (k < 4)) { + for (k = 0; k < 4; k++) { + if (k == 0) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->dither_fetch_param[0], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_DITHER_FETCH0; + } else if (k == 1) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->dither_fetch_param[1], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_DITHER_FETCH1; + } else if (k == 2) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->dither_store_param[0], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_DITHER_STORE0; + } else if (k == 3) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->dither_store_param[1], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_DITHER_STORE1; + } + + desc = desc->next; + } + + i += 4; + } + } + + cookie = txd->tx_submit(txd); + if (cookie < 0) { + pr_err("Error tx_submit\n"); + kfree(pxp_conf); + kfree(sg); + return -EIO; + } + + atomic_inc(&irq_info[chan_id].irq_pending); + + kfree(pxp_conf); + kfree(sg); + + return 0; +} + +static int pxp_device_open(struct inode *inode, struct file *filp) +{ + struct pxp_file *priv; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + + if (!priv) + return -ENOMEM; + + filp->private_data = priv; + priv->filp = filp; + + idr_init(&priv->buffer_idr); + spin_lock_init(&priv->buffer_lock); + + idr_init(&priv->channel_idr); + spin_lock_init(&priv->channel_lock); + + return 0; +} + +static int pxp_device_release(struct inode *inode, struct file *filp) +{ + struct pxp_file *priv = filp->private_data; + + if (priv) { + pxp_free_channels(priv); + pxp_free_buffers(priv); + kfree(priv); + filp->private_data = NULL; + } + + return 0; +} + +static int pxp_device_mmap(struct file *file, struct vm_area_struct *vma) +{ + int request_size; + struct hlist_node *node; + struct pxp_buf_obj *obj; + + request_size = vma->vm_end - vma->vm_start; + + pr_debug("start=0x%x, pgoff=0x%x, size=0x%x\n", + (unsigned int)(vma->vm_start), (unsigned int)(vma->vm_pgoff), + request_size); + + node = pxp_ht_find_key(&bufhash, vma->vm_pgoff); + if (!node) + return -EINVAL; + + obj = list_entry(node, struct pxp_buf_obj, item); + if (obj->offset + (obj->size >> PAGE_SHIFT) < + (vma->vm_pgoff + vma_pages(vma))) + return -ENOMEM; + + switch (obj->mem_type) { + case MEMORY_TYPE_UNCACHED: + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + break; + case MEMORY_TYPE_WC: + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + break; + case MEMORY_TYPE_CACHED: + break; + default: + pr_err("%s: invalid memory type!\n", __func__); + return -EINVAL; + } + + return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, + request_size, vma->vm_page_prot) ? -EAGAIN : 0; +} + +static bool chan_filter(struct dma_chan *chan, void *arg) +{ + if (imx_dma_is_pxp(chan)) + return true; + else + return false; +} + +static long pxp_device_ioctl(struct file *filp, + unsigned int cmd, unsigned long arg) +{ + int ret = 0; + struct pxp_file *file_priv = filp->private_data; + + switch (cmd) { + case PXP_IOC_GET_CHAN: + { + int ret; + struct dma_chan *chan = NULL; + dma_cap_mask_t mask; + struct pxp_chan_obj *obj = NULL; + + pr_debug("drv: PXP_IOC_GET_CHAN Line %d\n", __LINE__); + + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + dma_cap_set(DMA_PRIVATE, mask); + + chan = dma_request_channel(mask, chan_filter, NULL); + if (!chan) { + pr_err("Unsccessfully received channel!\n"); + return -EBUSY; + } + + pr_debug("Successfully received channel." + "chan_id %d\n", chan->chan_id); + + obj = kzalloc(sizeof(*obj), GFP_KERNEL); + if (!obj) { + dma_release_channel(chan); + return -ENOMEM; + } + obj->chan = chan; + + ret = pxp_channel_handle_create(file_priv, obj, + &obj->handle); + if (ret) { + dma_release_channel(chan); + kfree(obj); + return ret; + } + + init_waitqueue_head(&(irq_info[chan->chan_id].waitq)); + if (put_user(obj->handle, (u32 __user *) arg)) { + pxp_channel_handle_delete(file_priv, obj->handle); + dma_release_channel(chan); + kfree(obj); + return -EFAULT; + } + + break; + } + case PXP_IOC_PUT_CHAN: + { + int handle; + struct pxp_chan_obj *obj; + + if (get_user(handle, (u32 __user *) arg)) + return -EFAULT; + + pr_debug("%d release handle %d\n", __LINE__, handle); + + obj = pxp_channel_object_lookup(file_priv, handle); + if (!obj) + return -EINVAL; + + pxp_channel_handle_delete(file_priv, obj->handle); + dma_release_channel(obj->chan); + kfree(obj); + + break; + } + case PXP_IOC_CONFIG_CHAN: + { + int ret; + + ret = pxp_ioc_config_chan(file_priv, arg); + if (ret) + return ret; + + break; + } + case PXP_IOC_START_CHAN: + { + int handle; + struct pxp_chan_obj *obj = NULL; + + if (get_user(handle, (u32 __user *) arg)) + return -EFAULT; + + obj = pxp_channel_object_lookup(file_priv, handle); + if (!obj) + return -EINVAL; + + dma_async_issue_pending(obj->chan); + + break; + } + case PXP_IOC_GET_PHYMEM: + { + struct pxp_mem_desc buffer; + struct pxp_buf_obj *obj; + + ret = copy_from_user(&buffer, + (struct pxp_mem_desc *)arg, + sizeof(struct pxp_mem_desc)); + if (ret) + return -EFAULT; + + pr_debug("[ALLOC] mem alloc size = 0x%x\n", + buffer.size); + + obj = kzalloc(sizeof(*obj), GFP_KERNEL); + if (!obj) + return -ENOMEM; + obj->size = buffer.size; + obj->mem_type = buffer.mtype; + + ret = pxp_alloc_dma_buffer(obj); + if (ret == -1) { + printk(KERN_ERR + "Physical memory allocation error!\n"); + kfree(obj); + return ret; + } + + ret = pxp_buffer_handle_create(file_priv, obj, &obj->handle); + if (ret) { + pxp_free_dma_buffer(obj); + kfree(obj); + return ret; + } + buffer.handle = obj->handle; + buffer.phys_addr = obj->offset; + + ret = copy_to_user((void __user *)arg, &buffer, + sizeof(struct pxp_mem_desc)); + if (ret) { + pxp_buffer_handle_delete(file_priv, buffer.handle); + pxp_free_dma_buffer(obj); + kfree(obj); + return -EFAULT; + } + + pxp_ht_insert_item(&bufhash, obj); + + break; + } + case PXP_IOC_PUT_PHYMEM: + { + struct pxp_mem_desc pxp_mem; + struct pxp_buf_obj *obj; + + ret = copy_from_user(&pxp_mem, + (struct pxp_mem_desc *)arg, + sizeof(struct pxp_mem_desc)); + if (ret) + return -EACCES; + + obj = pxp_buffer_object_lookup(file_priv, pxp_mem.handle); + if (!obj) + return -EINVAL; + + ret = pxp_buffer_handle_delete(file_priv, obj->handle); + if (ret) + return ret; + + pxp_ht_remove_item(&bufhash, obj); + pxp_free_dma_buffer(obj); + kfree(obj); + + break; + } + case PXP_IOC_FLUSH_PHYMEM: + { + int ret; + struct pxp_mem_flush flush; + struct pxp_buf_obj *obj; + + ret = copy_from_user(&flush, + (struct pxp_mem_flush *)arg, + sizeof(struct pxp_mem_flush)); + if (ret) + return -EACCES; + + obj = pxp_buffer_object_lookup(file_priv, flush.handle); + if (!obj) + return -EINVAL; + + switch (flush.type) { + case CACHE_CLEAN: + dma_sync_single_for_device(NULL, obj->offset, + obj->size, DMA_TO_DEVICE); + break; + case CACHE_INVALIDATE: + dma_sync_single_for_device(NULL, obj->offset, + obj->size, DMA_FROM_DEVICE); + break; + case CACHE_FLUSH: + dma_sync_single_for_device(NULL, obj->offset, + obj->size, DMA_TO_DEVICE); + dma_sync_single_for_device(NULL, obj->offset, + obj->size, DMA_FROM_DEVICE); + break; + default: + pr_err("%s: invalid cache flush type\n", __func__); + return -EINVAL; + } + + break; + } + case PXP_IOC_WAIT4CMPLT: + { + struct pxp_chan_handle chan_handle; + int ret, chan_id, handle; + struct pxp_chan_obj *obj = NULL; + + ret = copy_from_user(&chan_handle, + (struct pxp_chan_handle *)arg, + sizeof(struct pxp_chan_handle)); + if (ret) + return -EFAULT; + + handle = chan_handle.handle; + obj = pxp_channel_object_lookup(file_priv, handle); + if (!obj) + return -EINVAL; + chan_id = obj->chan->chan_id; + + ret = wait_event_interruptible + (irq_info[chan_id].waitq, + (atomic_read(&irq_info[chan_id].irq_pending) == 0)); + if (ret < 0) + return -ERESTARTSYS; + + chan_handle.hist_status = irq_info[chan_id].hist_status; + ret = copy_to_user((struct pxp_chan_handle *)arg, + &chan_handle, + sizeof(struct pxp_chan_handle)); + if (ret) + return -EFAULT; + break; + } + default: + break; + } + + return 0; +} + +static const struct file_operations pxp_device_fops = { + .open = pxp_device_open, + .release = pxp_device_release, + .unlocked_ioctl = pxp_device_ioctl, + .mmap = pxp_device_mmap, +}; + +int register_pxp_device(void) +{ + int ret; + + if (!major) { + major = register_chrdev(0, "pxp_device", &pxp_device_fops); + if (major < 0) { + printk(KERN_ERR "Unable to register pxp device\n"); + ret = major; + goto register_cdev_fail; + } + + pxp_class = class_create(THIS_MODULE, "pxp_device"); + if (IS_ERR(pxp_class)) { + ret = PTR_ERR(pxp_class); + goto pxp_class_fail; + } + + pxp_dev = device_create(pxp_class, NULL, MKDEV(major, 0), + NULL, "pxp_device"); + if (IS_ERR(pxp_dev)) { + ret = PTR_ERR(pxp_dev); + goto dev_create_fail; + } + pxp_dev->dma_mask = kmalloc(sizeof(*pxp_dev->dma_mask), + GFP_KERNEL); + *pxp_dev->dma_mask = DMA_BIT_MASK(32); + pxp_dev->coherent_dma_mask = DMA_BIT_MASK(32); + } + + ret = pxp_ht_create(&bufhash, BUFFER_HASH_ORDER); + if (ret) { + goto ht_create_fail; + } + spin_lock_init(&(bufhash.hash_lock)); + + pr_debug("PxP_Device registered Successfully\n"); + return 0; + +ht_create_fail: + device_destroy(pxp_class, MKDEV(major, 0)); +dev_create_fail: + class_destroy(pxp_class); +pxp_class_fail: + unregister_chrdev(major, "pxp_device"); +register_cdev_fail: + return ret; +} + +void unregister_pxp_device(void) +{ + pxp_ht_destroy(&bufhash); + if (major) { + device_destroy(pxp_class, MKDEV(major, 0)); + class_destroy(pxp_class); + unregister_chrdev(major, "pxp_device"); + major = 0; + } +} diff --git a/drivers/dma/pxp/pxp_dma_v2.c b/drivers/dma/pxp/pxp_dma_v2.c new file mode 100644 index 00000000000000..7b83dedc629b9e --- /dev/null +++ b/drivers/dma/pxp/pxp_dma_v2.c @@ -0,0 +1,1849 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + */ +/* + * Based on STMP378X PxP driver + * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "regs-pxp_v2.h" + +#define PXP_DOWNSCALE_THRESHOLD 0x4000 + +static LIST_HEAD(head); +static int timeout_in_ms = 600; +static unsigned int block_size; +static struct kmem_cache *tx_desc_cache; + +struct pxp_dma { + struct dma_device dma; +}; + +struct pxps { + struct platform_device *pdev; + struct clk *clk; + struct clk *clk_disp_axi; /* may exist on some SoC for gating */ + void __iomem *base; + int irq; /* PXP IRQ to the CPU */ + + spinlock_t lock; + struct mutex clk_mutex; + int clk_stat; +#define CLK_STAT_OFF 0 +#define CLK_STAT_ON 1 + int pxp_ongoing; + int lut_state; + + struct device *dev; + struct pxp_dma pxp_dma; + struct pxp_channel channel[NR_PXP_VIRT_CHANNEL]; + struct work_struct work; + + /* describes most recent processing configuration */ + struct pxp_config_data pxp_conf_state; + + /* to turn clock off when pxp is inactive */ + struct timer_list clk_timer; + + /* for pxp config dispatch asynchronously*/ + struct task_struct *dispatch; + wait_queue_head_t thread_waitq; + struct completion complete; +}; + +#define to_pxp_dma(d) container_of(d, struct pxp_dma, dma) +#define to_tx_desc(tx) container_of(tx, struct pxp_tx_desc, txd) +#define to_pxp_channel(d) container_of(d, struct pxp_channel, dma_chan) +#define to_pxp(id) container_of(id, struct pxps, pxp_dma) + +#define PXP_DEF_BUFS 2 +#define PXP_MIN_PIX 8 + +/* + * PXP common functions + */ +static void dump_pxp_reg(struct pxps *pxp) +{ + dev_dbg(pxp->dev, "PXP_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_CTRL)); + dev_dbg(pxp->dev, "PXP_STAT 0x%x", + __raw_readl(pxp->base + HW_PXP_STAT)); + dev_dbg(pxp->dev, "PXP_OUT_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_CTRL)); + dev_dbg(pxp->dev, "PXP_OUT_BUF 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_BUF)); + dev_dbg(pxp->dev, "PXP_OUT_BUF2 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_BUF2)); + dev_dbg(pxp->dev, "PXP_OUT_PITCH 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_PITCH)); + dev_dbg(pxp->dev, "PXP_OUT_LRC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_LRC)); + dev_dbg(pxp->dev, "PXP_OUT_PS_ULC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_PS_ULC)); + dev_dbg(pxp->dev, "PXP_OUT_PS_LRC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_PS_LRC)); + dev_dbg(pxp->dev, "PXP_OUT_AS_ULC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_AS_ULC)); + dev_dbg(pxp->dev, "PXP_OUT_AS_LRC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_AS_LRC)); + dev_dbg(pxp->dev, "PXP_PS_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_CTRL)); + dev_dbg(pxp->dev, "PXP_PS_BUF 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_BUF)); + dev_dbg(pxp->dev, "PXP_PS_UBUF 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_UBUF)); + dev_dbg(pxp->dev, "PXP_PS_VBUF 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_VBUF)); + dev_dbg(pxp->dev, "PXP_PS_PITCH 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_PITCH)); + dev_dbg(pxp->dev, "PXP_PS_BACKGROUND 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_BACKGROUND)); + dev_dbg(pxp->dev, "PXP_PS_SCALE 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_SCALE)); + dev_dbg(pxp->dev, "PXP_PS_OFFSET 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_OFFSET)); + dev_dbg(pxp->dev, "PXP_PS_CLRKEYLOW 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_CLRKEYLOW)); + dev_dbg(pxp->dev, "PXP_PS_CLRKEYHIGH 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_CLRKEYHIGH)); + dev_dbg(pxp->dev, "PXP_AS_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_CTRL)); + dev_dbg(pxp->dev, "PXP_AS_BUF 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_BUF)); + dev_dbg(pxp->dev, "PXP_AS_PITCH 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_PITCH)); + dev_dbg(pxp->dev, "PXP_AS_CLRKEYLOW 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_CLRKEYLOW)); + dev_dbg(pxp->dev, "PXP_AS_CLRKEYHIGH 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_CLRKEYHIGH)); + dev_dbg(pxp->dev, "PXP_CSC1_COEF0 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC1_COEF0)); + dev_dbg(pxp->dev, "PXP_CSC1_COEF1 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC1_COEF1)); + dev_dbg(pxp->dev, "PXP_CSC1_COEF2 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC1_COEF2)); + dev_dbg(pxp->dev, "PXP_CSC2_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_CTRL)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF0 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF0)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF1 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF1)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF2 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF2)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF3 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF3)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF4 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF4)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF5 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF5)); + dev_dbg(pxp->dev, "PXP_LUT_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_CTRL)); + dev_dbg(pxp->dev, "PXP_LUT_ADDR 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_ADDR)); + dev_dbg(pxp->dev, "PXP_LUT_DATA 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_DATA)); + dev_dbg(pxp->dev, "PXP_LUT_EXTMEM 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_EXTMEM)); + dev_dbg(pxp->dev, "PXP_CFA 0x%x", + __raw_readl(pxp->base + HW_PXP_CFA)); + dev_dbg(pxp->dev, "PXP_HIST_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST_CTRL)); + dev_dbg(pxp->dev, "PXP_HIST2_PARAM 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST2_PARAM)); + dev_dbg(pxp->dev, "PXP_HIST4_PARAM 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST4_PARAM)); + dev_dbg(pxp->dev, "PXP_HIST8_PARAM0 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST8_PARAM0)); + dev_dbg(pxp->dev, "PXP_HIST8_PARAM1 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST8_PARAM1)); + dev_dbg(pxp->dev, "PXP_HIST16_PARAM0 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST16_PARAM0)); + dev_dbg(pxp->dev, "PXP_HIST16_PARAM1 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST16_PARAM1)); + dev_dbg(pxp->dev, "PXP_HIST16_PARAM2 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST16_PARAM2)); + dev_dbg(pxp->dev, "PXP_HIST16_PARAM3 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST16_PARAM3)); + dev_dbg(pxp->dev, "PXP_POWER 0x%x", + __raw_readl(pxp->base + HW_PXP_POWER)); + dev_dbg(pxp->dev, "PXP_NEXT 0x%x", + __raw_readl(pxp->base + HW_PXP_NEXT)); + dev_dbg(pxp->dev, "PXP_DEBUGCTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_DEBUGCTRL)); + dev_dbg(pxp->dev, "PXP_DEBUG 0x%x", + __raw_readl(pxp->base + HW_PXP_DEBUG)); + dev_dbg(pxp->dev, "PXP_VERSION 0x%x", + __raw_readl(pxp->base + HW_PXP_VERSION)); +} + +static bool is_yuv(u32 pix_fmt) +{ + switch (pix_fmt) { + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_YVYU: + case PXP_PIX_FMT_VYUY: + case PXP_PIX_FMT_Y41P: + case PXP_PIX_FMT_VUY444: + case PXP_PIX_FMT_NV12: + case PXP_PIX_FMT_NV21: + case PXP_PIX_FMT_NV16: + case PXP_PIX_FMT_NV61: + case PXP_PIX_FMT_GREY: + case PXP_PIX_FMT_GY04: + case PXP_PIX_FMT_YVU410P: + case PXP_PIX_FMT_YUV410P: + case PXP_PIX_FMT_YVU420P: + case PXP_PIX_FMT_YUV420P: + case PXP_PIX_FMT_YUV420P2: + case PXP_PIX_FMT_YVU422P: + case PXP_PIX_FMT_YUV422P: + return true; + default: + return false; + } +} + +static void pxp_soft_reset(struct pxps *pxp) +{ + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_CLR); + __raw_writel(BM_PXP_CTRL_CLKGATE, pxp->base + HW_PXP_CTRL_CLR); + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_SET); + while (!(__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_CLKGATE)) + dev_dbg(pxp->dev, "%s: wait for clock gate off", __func__); + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_CLR); + __raw_writel(BM_PXP_CTRL_CLKGATE, pxp->base + HW_PXP_CTRL_CLR); +} + +static void pxp_set_ctrl(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + u32 ctrl; + u32 fmt_ctrl; + int need_swap = 0; /* to support YUYV and YVYU formats */ + + /* Configure S0 input format */ + switch (pxp_conf->s0_param.pixel_fmt) { + case PXP_PIX_FMT_XRGB32: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB888; + break; + case PXP_PIX_FMT_RGB565: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB565; + break; + case PXP_PIX_FMT_RGB555: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB555; + break; + case PXP_PIX_FMT_YUV420P: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV420; + break; + case PXP_PIX_FMT_YVU420P: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV420; + break; + case PXP_PIX_FMT_GREY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y8; + break; + case PXP_PIX_FMT_GY04: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y4; + break; + case PXP_PIX_FMT_VUY444: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV1P444; + break; + case PXP_PIX_FMT_YUV422P: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV422; + break; + case PXP_PIX_FMT_UYVY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422; + break; + case PXP_PIX_FMT_YUYV: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422; + need_swap = 1; + break; + case PXP_PIX_FMT_VYUY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__VYUY1P422; + break; + case PXP_PIX_FMT_YVYU: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__VYUY1P422; + need_swap = 1; + break; + case PXP_PIX_FMT_NV12: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV2P420; + break; + case PXP_PIX_FMT_NV21: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YVU2P420; + break; + case PXP_PIX_FMT_NV16: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV2P422; + break; + case PXP_PIX_FMT_NV61: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YVU2P422; + break; + default: + fmt_ctrl = 0; + } + + ctrl = BF_PXP_PS_CTRL_FORMAT(fmt_ctrl) | BF_PXP_PS_CTRL_SWAP(need_swap); + __raw_writel(ctrl, pxp->base + HW_PXP_PS_CTRL_SET); + + /* Configure output format based on out_channel format */ + switch (pxp_conf->out_param.pixel_fmt) { + case PXP_PIX_FMT_XRGB32: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888; + break; + case PXP_PIX_FMT_BGRA32: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__ARGB8888; + break; + case PXP_PIX_FMT_RGB24: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888P; + break; + case PXP_PIX_FMT_RGB565: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB565; + break; + case PXP_PIX_FMT_RGB555: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB555; + break; + case PXP_PIX_FMT_GREY: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y8; + break; + case PXP_PIX_FMT_GY04: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y4; + break; + case PXP_PIX_FMT_UYVY: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__UYVY1P422; + break; + case PXP_PIX_FMT_VYUY: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__VYUY1P422; + break; + case PXP_PIX_FMT_NV12: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P420; + break; + case PXP_PIX_FMT_NV21: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YVU2P420; + break; + case PXP_PIX_FMT_NV16: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P422; + break; + case PXP_PIX_FMT_NV61: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YVU2P422; + break; + default: + fmt_ctrl = 0; + } + + ctrl = BF_PXP_OUT_CTRL_FORMAT(fmt_ctrl); + __raw_writel(ctrl, pxp->base + HW_PXP_OUT_CTRL); + + ctrl = 0; + if (proc_data->scaling) + ; + if (proc_data->vflip) + ctrl |= BM_PXP_CTRL_VFLIP; + if (proc_data->hflip) + ctrl |= BM_PXP_CTRL_HFLIP; + if (proc_data->rotate) + ctrl |= BF_PXP_CTRL_ROTATE(proc_data->rotate / 90); + + /* In default, the block size is set to 8x8 + * But block size can be set to 16x16 due to + * blocksize variable modification + */ + ctrl |= block_size << 23; + + __raw_writel(ctrl, pxp->base + HW_PXP_CTRL); +} + +static int pxp_start(struct pxps *pxp) +{ + __raw_writel(BM_PXP_CTRL_IRQ_ENABLE, pxp->base + HW_PXP_CTRL_SET); + __raw_writel(BM_PXP_CTRL_ENABLE, pxp->base + HW_PXP_CTRL_SET); + dump_pxp_reg(pxp); + + return 0; +} + +static void pxp_set_outbuf(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *out_params = &pxp_conf->out_param; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + + __raw_writel(out_params->paddr, pxp->base + HW_PXP_OUT_BUF); + + if ((out_params->pixel_fmt == PXP_PIX_FMT_NV12) || + (out_params->pixel_fmt == PXP_PIX_FMT_NV21) || + (out_params->pixel_fmt == PXP_PIX_FMT_NV16) || + (out_params->pixel_fmt == PXP_PIX_FMT_NV61)) { + dma_addr_t Y, U; + + Y = out_params->paddr; + U = Y + (out_params->width * out_params->height); + + __raw_writel(U, pxp->base + HW_PXP_OUT_BUF2); + } + + if (proc_data->rotate == 90 || proc_data->rotate == 270) + __raw_writel(BF_PXP_OUT_LRC_X(out_params->height - 1) | + BF_PXP_OUT_LRC_Y(out_params->width - 1), + pxp->base + HW_PXP_OUT_LRC); + else + __raw_writel(BF_PXP_OUT_LRC_X(out_params->width - 1) | + BF_PXP_OUT_LRC_Y(out_params->height - 1), + pxp->base + HW_PXP_OUT_LRC); + + if (out_params->pixel_fmt == PXP_PIX_FMT_RGB24) { + __raw_writel(out_params->stride * 3, + pxp->base + HW_PXP_OUT_PITCH); + } else if (out_params->pixel_fmt == PXP_PIX_FMT_BGRA32 || + out_params->pixel_fmt == PXP_PIX_FMT_XRGB32) { + __raw_writel(out_params->stride << 2, + pxp->base + HW_PXP_OUT_PITCH); + } else if ((out_params->pixel_fmt == PXP_PIX_FMT_RGB565) || + (out_params->pixel_fmt == PXP_PIX_FMT_RGB555)) { + __raw_writel(out_params->stride << 1, + pxp->base + HW_PXP_OUT_PITCH); + } else if (out_params->pixel_fmt == PXP_PIX_FMT_UYVY || + (out_params->pixel_fmt == PXP_PIX_FMT_VYUY)) { + __raw_writel(out_params->stride << 1, + pxp->base + HW_PXP_OUT_PITCH); + } else if (out_params->pixel_fmt == PXP_PIX_FMT_GREY || + out_params->pixel_fmt == PXP_PIX_FMT_NV12 || + out_params->pixel_fmt == PXP_PIX_FMT_NV21 || + out_params->pixel_fmt == PXP_PIX_FMT_NV16 || + out_params->pixel_fmt == PXP_PIX_FMT_NV61) { + __raw_writel(out_params->stride, + pxp->base + HW_PXP_OUT_PITCH); + } else if (out_params->pixel_fmt == PXP_PIX_FMT_GY04) { + __raw_writel(out_params->stride >> 1, + pxp->base + HW_PXP_OUT_PITCH); + } else { + __raw_writel(0, pxp->base + HW_PXP_OUT_PITCH); + } + + /* set global alpha if necessary */ + if (out_params->global_alpha_enable) { + __raw_writel(out_params->global_alpha << 24, + pxp->base + HW_PXP_OUT_CTRL_SET); + __raw_writel(BM_PXP_OUT_CTRL_ALPHA_OUTPUT, + pxp->base + HW_PXP_OUT_CTRL_SET); + } +} + +static void pxp_set_s0colorkey(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + + /* Low and high are set equal. V4L does not allow a chromakey range */ + if (s0_params->color_key_enable == 0 || s0_params->color_key == -1) { + /* disable color key */ + __raw_writel(0xFFFFFF, pxp->base + HW_PXP_PS_CLRKEYLOW); + __raw_writel(0, pxp->base + HW_PXP_PS_CLRKEYHIGH); + } else { + __raw_writel(s0_params->color_key, + pxp->base + HW_PXP_PS_CLRKEYLOW); + __raw_writel(s0_params->color_key, + pxp->base + HW_PXP_PS_CLRKEYHIGH); + } +} + +static void pxp_set_olcolorkey(int layer_no, struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *ol_params = &pxp_conf->ol_param[layer_no]; + + /* Low and high are set equal. V4L does not allow a chromakey range */ + if (ol_params->color_key_enable != 0 && ol_params->color_key != -1) { + __raw_writel(ol_params->color_key, + pxp->base + HW_PXP_AS_CLRKEYLOW); + __raw_writel(ol_params->color_key, + pxp->base + HW_PXP_AS_CLRKEYHIGH); + } else { + /* disable color key */ + __raw_writel(0xFFFFFF, pxp->base + HW_PXP_AS_CLRKEYLOW); + __raw_writel(0, pxp->base + HW_PXP_AS_CLRKEYHIGH); + } +} + +static void pxp_set_oln(int layer_no, struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *olparams_data = &pxp_conf->ol_param[layer_no]; + dma_addr_t phys_addr = olparams_data->paddr; + u32 pitch = olparams_data->stride ? olparams_data->stride : + olparams_data->width; + + __raw_writel(phys_addr, pxp->base + HW_PXP_AS_BUF); + + /* Fixme */ + if (olparams_data->width == 0 && olparams_data->height == 0) { + __raw_writel(0xffffffff, pxp->base + HW_PXP_OUT_AS_ULC); + __raw_writel(0x0, pxp->base + HW_PXP_OUT_AS_LRC); + } else { + __raw_writel(0x0, pxp->base + HW_PXP_OUT_AS_ULC); + __raw_writel(BF_PXP_OUT_AS_LRC_X(olparams_data->width - 1) | + BF_PXP_OUT_AS_LRC_Y(olparams_data->height - 1), + pxp->base + HW_PXP_OUT_AS_LRC); + } + + if ((olparams_data->pixel_fmt == PXP_PIX_FMT_BGRA32) || + (olparams_data->pixel_fmt == PXP_PIX_FMT_XRGB32)) { + __raw_writel(pitch << 2, + pxp->base + HW_PXP_AS_PITCH); + } else if ((olparams_data->pixel_fmt == PXP_PIX_FMT_RGB565) || + (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB555)) { + __raw_writel(pitch << 1, + pxp->base + HW_PXP_AS_PITCH); + } else { + __raw_writel(0, pxp->base + HW_PXP_AS_PITCH); + } +} + +static void pxp_set_olparam(int layer_no, struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *olparams_data = &pxp_conf->ol_param[layer_no]; + u32 olparam; + + olparam = BF_PXP_AS_CTRL_ALPHA(olparams_data->global_alpha); + if (olparams_data->pixel_fmt == PXP_PIX_FMT_XRGB32) { + olparam |= + BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__RGB888); + } else if (olparams_data->pixel_fmt == PXP_PIX_FMT_BGRA32) { + olparam |= + BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__ARGB8888); + if (!olparams_data->combine_enable) { + olparam |= + BF_PXP_AS_CTRL_ALPHA_CTRL + (BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs); + olparam |= 0x3 << 16; + } + } else if (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB565) { + olparam |= + BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__RGB565); + } else if (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB555) { + olparam |= + BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__RGB555); + } + + if (olparams_data->global_alpha_enable) { + if (olparams_data->global_override) { + olparam |= + BF_PXP_AS_CTRL_ALPHA_CTRL + (BV_PXP_AS_CTRL_ALPHA_CTRL__Override); + } else { + olparam |= + BF_PXP_AS_CTRL_ALPHA_CTRL + (BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply); + } + if (olparams_data->alpha_invert) + olparam |= BM_PXP_AS_CTRL_ALPHA_INVERT; + } + if (olparams_data->color_key_enable) + olparam |= BM_PXP_AS_CTRL_ENABLE_COLORKEY; + + __raw_writel(olparam, pxp->base + HW_PXP_AS_CTRL); +} + +static void pxp_set_s0param(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + struct pxp_layer_param *out_params = &pxp_conf->out_param; + u32 s0param_ulc, s0param_lrc; + + /* contains the coordinate for the PS in the OUTPUT buffer. */ + if ((pxp_conf->s0_param).width == 0 && + (pxp_conf->s0_param).height == 0) { + __raw_writel(0xffffffff, pxp->base + HW_PXP_OUT_PS_ULC); + __raw_writel(0x0, pxp->base + HW_PXP_OUT_PS_LRC); + } else { + switch (proc_data->rotate) { + case 0: + s0param_ulc = BF_PXP_OUT_PS_ULC_X(proc_data->drect.left); + s0param_ulc |= BF_PXP_OUT_PS_ULC_Y(proc_data->drect.top); + s0param_lrc = BF_PXP_OUT_PS_LRC_X(((s0param_ulc & BM_PXP_OUT_PS_ULC_X) >> 16) + proc_data->drect.width - 1); + s0param_lrc |= BF_PXP_OUT_PS_LRC_Y((s0param_ulc & BM_PXP_OUT_PS_ULC_Y) + proc_data->drect.height - 1); + break; + case 90: + s0param_ulc = BF_PXP_OUT_PS_ULC_Y(out_params->width - (proc_data->drect.left + proc_data->drect.width)); + s0param_ulc |= BF_PXP_OUT_PS_ULC_X(proc_data->drect.top); + s0param_lrc = BF_PXP_OUT_PS_LRC_X(((s0param_ulc & BM_PXP_OUT_PS_ULC_X) >> 16) + proc_data->drect.height - 1); + s0param_lrc |= BF_PXP_OUT_PS_LRC_Y((s0param_ulc & BM_PXP_OUT_PS_ULC_Y) + proc_data->drect.width - 1); + break; + case 180: + s0param_ulc = BF_PXP_OUT_PS_ULC_X(out_params->width - (proc_data->drect.left + proc_data->drect.width)); + s0param_ulc |= BF_PXP_OUT_PS_ULC_Y(out_params->height - (proc_data->drect.top + proc_data->drect.height)); + s0param_lrc = BF_PXP_OUT_PS_LRC_X(((s0param_ulc & BM_PXP_OUT_PS_ULC_X) >> 16) + proc_data->drect.width - 1); + s0param_lrc |= BF_PXP_OUT_PS_LRC_Y((s0param_ulc & BM_PXP_OUT_PS_ULC_Y) + proc_data->drect.height - 1); + break; + case 270: + s0param_ulc = BF_PXP_OUT_PS_ULC_X(out_params->height - (proc_data->drect.top + proc_data->drect.height)); + s0param_ulc |= BF_PXP_OUT_PS_ULC_Y(proc_data->drect.left); + s0param_lrc = BF_PXP_OUT_PS_LRC_X(((s0param_ulc & BM_PXP_OUT_PS_ULC_X) >> 16) + proc_data->drect.height - 1); + s0param_lrc |= BF_PXP_OUT_PS_LRC_Y((s0param_ulc & BM_PXP_OUT_PS_ULC_Y) + proc_data->drect.width - 1); + break; + default: + return; + } + __raw_writel(s0param_ulc, pxp->base + HW_PXP_OUT_PS_ULC); + __raw_writel(s0param_lrc, pxp->base + HW_PXP_OUT_PS_LRC); + } + + /* Since user apps always pass the rotated drect + * to this driver, we need to first swap the width + * and height which is used to calculate the scale + * factors later. + */ + if (proc_data->rotate == 90 || proc_data->rotate == 270) { + int temp; + temp = proc_data->drect.width; + proc_data->drect.width = proc_data->drect.height; + proc_data->drect.height = temp; + } +} + +/* crop behavior is re-designed in h/w. */ +static void pxp_set_s0crop(struct pxps *pxp) +{ + /* + * place-holder, it's implemented in other functions in this driver. + * Refer to "Clipping source images" section in RM for detail. + */ +} + +static int pxp_set_scaling(struct pxps *pxp) +{ + int ret = 0; + u32 xscale, yscale, s0scale; + u32 decx, decy, xdec = 0, ydec = 0; + struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data; + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + struct pxp_layer_param *out_params = &pxp_conf->out_param; + + proc_data->scaling = 1; + + if (!proc_data->drect.width || !proc_data->drect.height) { + pr_err("Invalid drect width and height passed in\n"); + return -EINVAL; + } + + decx = proc_data->srect.width / proc_data->drect.width; + decy = proc_data->srect.height / proc_data->drect.height; + if (decx > 1) { + if (decx >= 2 && decx < 4) { + decx = 2; + xdec = 1; + } else if (decx >= 4 && decx < 8) { + decx = 4; + xdec = 2; + } else if (decx >= 8) { + decx = 8; + xdec = 3; + } + xscale = proc_data->srect.width * 0x1000 / + (proc_data->drect.width * decx); + } else { + if (!is_yuv(s0_params->pixel_fmt) || + (is_yuv(s0_params->pixel_fmt) == + is_yuv(out_params->pixel_fmt)) || + (s0_params->pixel_fmt == PXP_PIX_FMT_GREY) || + (s0_params->pixel_fmt == PXP_PIX_FMT_GY04) || + (s0_params->pixel_fmt == PXP_PIX_FMT_VUY444)) { + if ((proc_data->srect.width > 1) && + (proc_data->drect.width > 1)) + xscale = (proc_data->srect.width - 1) * 0x1000 / + (proc_data->drect.width - 1); + else + xscale = proc_data->srect.width * 0x1000 / + proc_data->drect.width; + } else { + if ((proc_data->srect.width > 2) && + (proc_data->drect.width > 1)) + xscale = (proc_data->srect.width - 2) * 0x1000 / + (proc_data->drect.width - 1); + else + xscale = proc_data->srect.width * 0x1000 / + proc_data->drect.width; + } + } + if (decy > 1) { + if (decy >= 2 && decy < 4) { + decy = 2; + ydec = 1; + } else if (decy >= 4 && decy < 8) { + decy = 4; + ydec = 2; + } else if (decy >= 8) { + decy = 8; + ydec = 3; + } + yscale = proc_data->srect.height * 0x1000 / + (proc_data->drect.height * decy); + } else { + if ((proc_data->srect.height > 1) && + (proc_data->drect.height > 1)) + yscale = (proc_data->srect.height - 1) * 0x1000 / + (proc_data->drect.height - 1); + else + yscale = proc_data->srect.height * 0x1000 / + proc_data->drect.height; + } + + __raw_writel((xdec << 10) | (ydec << 8), pxp->base + HW_PXP_PS_CTRL); + + if (xscale > PXP_DOWNSCALE_THRESHOLD) + xscale = PXP_DOWNSCALE_THRESHOLD; + if (yscale > PXP_DOWNSCALE_THRESHOLD) + yscale = PXP_DOWNSCALE_THRESHOLD; + s0scale = BF_PXP_PS_SCALE_YSCALE(yscale) | + BF_PXP_PS_SCALE_XSCALE(xscale); + __raw_writel(s0scale, pxp->base + HW_PXP_PS_SCALE); + + pxp_set_ctrl(pxp); + + return ret; +} + +static void pxp_set_bg(struct pxps *pxp) +{ + __raw_writel(pxp->pxp_conf_state.proc_data.bgcolor, + pxp->base + HW_PXP_PS_BACKGROUND); +} + +static void pxp_set_lut(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + int lut_op = pxp_conf->proc_data.lut_transform; + u32 reg_val; + int i; + bool use_cmap = (lut_op & PXP_LUT_USE_CMAP) ? true : false; + u8 *cmap = pxp_conf->proc_data.lut_map; + u32 entry_src; + u32 pix_val; + u8 entry[4]; + + /* + * If LUT already configured as needed, return... + * Unless CMAP is needed and it has been updated. + */ + if ((pxp->lut_state == lut_op) && + !(use_cmap && pxp_conf->proc_data.lut_map_updated)) + return; + + if (lut_op == PXP_LUT_NONE) { + __raw_writel(BM_PXP_LUT_CTRL_BYPASS, + pxp->base + HW_PXP_LUT_CTRL); + } else if (((lut_op & PXP_LUT_INVERT) != 0) + && ((lut_op & PXP_LUT_BLACK_WHITE) != 0)) { + /* Fill out LUT table with inverted monochromized values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) { + entry_src = use_cmap ? + cmap[pix_val + i] : pix_val + i; + entry[i] = (entry_src < 0x80) ? 0xFF : 0x00; + } + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } else if ((lut_op & PXP_LUT_INVERT) != 0) { + /* Fill out LUT table with 8-bit inverted values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) { + entry_src = use_cmap ? + cmap[pix_val + i] : pix_val + i; + entry[i] = ~entry_src & 0xFF; + } + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } else if ((lut_op & PXP_LUT_BLACK_WHITE) != 0) { + /* Fill out LUT table with 8-bit monochromized values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) { + entry_src = use_cmap ? + cmap[pix_val + i] : pix_val + i; + entry[i] = (entry_src < 0x80) ? 0x00 : 0xFF; + } + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } else if (use_cmap) { + /* Fill out LUT table using colormap values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) + entry[i] = cmap[pix_val + i]; + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } + + pxp->lut_state = lut_op; +} + +static void pxp_set_csc(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + struct pxp_layer_param *ol_params = &pxp_conf->ol_param[0]; + struct pxp_layer_param *out_params = &pxp_conf->out_param; + + bool input_is_YUV = is_yuv(s0_params->pixel_fmt); + bool output_is_YUV = is_yuv(out_params->pixel_fmt); + + if (input_is_YUV && output_is_YUV) { + /* + * Input = YUV, Output = YUV + * No CSC unless we need to do combining + */ + if (ol_params->combine_enable) { + /* Must convert to RGB for combining with RGB overlay */ + + /* CSC1 - YUV->RGB */ + __raw_writel(0x04030000, pxp->base + HW_PXP_CSC1_COEF0); + __raw_writel(0x01230208, pxp->base + HW_PXP_CSC1_COEF1); + __raw_writel(0x076b079c, pxp->base + HW_PXP_CSC1_COEF2); + + /* CSC2 - RGB->YUV */ + __raw_writel(0x4, pxp->base + HW_PXP_CSC2_CTRL); + __raw_writel(0x0096004D, pxp->base + HW_PXP_CSC2_COEF0); + __raw_writel(0x05DA001D, pxp->base + HW_PXP_CSC2_COEF1); + __raw_writel(0x007005B6, pxp->base + HW_PXP_CSC2_COEF2); + __raw_writel(0x057C009E, pxp->base + HW_PXP_CSC2_COEF3); + __raw_writel(0x000005E6, pxp->base + HW_PXP_CSC2_COEF4); + __raw_writel(0x00000000, pxp->base + HW_PXP_CSC2_COEF5); + } else { + /* Input & Output both YUV, so bypass both CSCs */ + + /* CSC1 - Bypass */ + __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0); + + /* CSC2 - Bypass */ + __raw_writel(0x1, pxp->base + HW_PXP_CSC2_CTRL); + } + } else if (input_is_YUV && !output_is_YUV) { + /* + * Input = YUV, Output = RGB + * Use CSC1 to convert to RGB + */ + + /* CSC1 - YUV->RGB */ + __raw_writel(0x84ab01f0, pxp->base + HW_PXP_CSC1_COEF0); + __raw_writel(0x01980204, pxp->base + HW_PXP_CSC1_COEF1); + __raw_writel(0x0730079c, pxp->base + HW_PXP_CSC1_COEF2); + + /* CSC2 - Bypass */ + __raw_writel(0x1, pxp->base + HW_PXP_CSC2_CTRL); + } else if (!input_is_YUV && output_is_YUV) { + /* + * Input = RGB, Output = YUV + * Use CSC2 to convert to YUV + */ + + /* CSC1 - Bypass */ + __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0); + + /* CSC2 - RGB->YUV */ + __raw_writel(0x4, pxp->base + HW_PXP_CSC2_CTRL); + __raw_writel(0x0096004D, pxp->base + HW_PXP_CSC2_COEF0); + __raw_writel(0x05DA001D, pxp->base + HW_PXP_CSC2_COEF1); + __raw_writel(0x007005B6, pxp->base + HW_PXP_CSC2_COEF2); + __raw_writel(0x057C009E, pxp->base + HW_PXP_CSC2_COEF3); + __raw_writel(0x000005E6, pxp->base + HW_PXP_CSC2_COEF4); + __raw_writel(0x00000000, pxp->base + HW_PXP_CSC2_COEF5); + } else { + /* + * Input = RGB, Output = RGB + * Input & Output both RGB, so bypass both CSCs + */ + + /* CSC1 - Bypass */ + __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0); + + /* CSC2 - Bypass */ + __raw_writel(0x1, pxp->base + HW_PXP_CSC2_CTRL); + } + + /* YCrCb colorspace */ + /* Not sure when we use this...no YCrCb formats are defined for PxP */ + /* + __raw_writel(0x84ab01f0, HW_PXP_CSCCOEFF0_ADDR); + __raw_writel(0x01230204, HW_PXP_CSCCOEFF1_ADDR); + __raw_writel(0x0730079c, HW_PXP_CSCCOEFF2_ADDR); + */ + +} + +static void pxp_set_s0buf(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + dma_addr_t Y, U, V; + dma_addr_t Y1, U1, V1; + u32 offset, bpp = 1; + u32 pitch = s0_params->stride ? s0_params->stride : + s0_params->width; + + Y = s0_params->paddr; + + if ((s0_params->pixel_fmt == PXP_PIX_FMT_RGB565) || + (s0_params->pixel_fmt == PXP_PIX_FMT_RGB555)) + bpp = 2; + else if (s0_params->pixel_fmt == PXP_PIX_FMT_XRGB32) + bpp = 4; + offset = (proc_data->srect.top * s0_params->width + + proc_data->srect.left) * bpp; + /* clipping or cropping */ + Y1 = Y + offset; + __raw_writel(Y1, pxp->base + HW_PXP_PS_BUF); + if ((s0_params->pixel_fmt == PXP_PIX_FMT_YUV420P) || + (s0_params->pixel_fmt == PXP_PIX_FMT_YVU420P) || + (s0_params->pixel_fmt == PXP_PIX_FMT_GREY) || + (s0_params->pixel_fmt == PXP_PIX_FMT_YUV422P)) { + /* Set to 1 if YUV format is 4:2:2 rather than 4:2:0 */ + int s = 2; + if (s0_params->pixel_fmt == PXP_PIX_FMT_YUV422P) + s = 1; + + offset = proc_data->srect.top * s0_params->width / 4 + + proc_data->srect.left / 2; + U = Y + (s0_params->width * s0_params->height); + U1 = U + offset; + V = U + ((s0_params->width * s0_params->height) >> s); + V1 = V + offset; + if (s0_params->pixel_fmt == PXP_PIX_FMT_YVU420P) { + __raw_writel(V1, pxp->base + HW_PXP_PS_UBUF); + __raw_writel(U1, pxp->base + HW_PXP_PS_VBUF); + } else { + __raw_writel(U1, pxp->base + HW_PXP_PS_UBUF); + __raw_writel(V1, pxp->base + HW_PXP_PS_VBUF); + } + } else if ((s0_params->pixel_fmt == PXP_PIX_FMT_NV12) || + (s0_params->pixel_fmt == PXP_PIX_FMT_NV21) || + (s0_params->pixel_fmt == PXP_PIX_FMT_NV16) || + (s0_params->pixel_fmt == PXP_PIX_FMT_NV61)) { + int s = 2; + if ((s0_params->pixel_fmt == PXP_PIX_FMT_NV16) || + (s0_params->pixel_fmt == PXP_PIX_FMT_NV61)) + s = 1; + + offset = (proc_data->srect.top * s0_params->width + + proc_data->srect.left) / s; + U = Y + (s0_params->width * s0_params->height); + U1 = U + offset; + + __raw_writel(U1, pxp->base + HW_PXP_PS_UBUF); + } + + /* TODO: only support RGB565, Y8, Y4, YUV420 */ + if (s0_params->pixel_fmt == PXP_PIX_FMT_GREY || + s0_params->pixel_fmt == PXP_PIX_FMT_YUV420P || + s0_params->pixel_fmt == PXP_PIX_FMT_YVU420P || + s0_params->pixel_fmt == PXP_PIX_FMT_NV12 || + s0_params->pixel_fmt == PXP_PIX_FMT_NV21 || + s0_params->pixel_fmt == PXP_PIX_FMT_NV16 || + s0_params->pixel_fmt == PXP_PIX_FMT_NV61 || + s0_params->pixel_fmt == PXP_PIX_FMT_YUV422P) { + __raw_writel(pitch, pxp->base + HW_PXP_PS_PITCH); + } + else if (s0_params->pixel_fmt == PXP_PIX_FMT_GY04) + __raw_writel(pitch >> 1, + pxp->base + HW_PXP_PS_PITCH); + else if (s0_params->pixel_fmt == PXP_PIX_FMT_XRGB32 || + s0_params->pixel_fmt == PXP_PIX_FMT_VUY444) + __raw_writel(pitch << 2, + pxp->base + HW_PXP_PS_PITCH); + else if (s0_params->pixel_fmt == PXP_PIX_FMT_UYVY || + s0_params->pixel_fmt == PXP_PIX_FMT_YUYV || + s0_params->pixel_fmt == PXP_PIX_FMT_VYUY || + s0_params->pixel_fmt == PXP_PIX_FMT_YVYU) + __raw_writel(pitch << 1, + pxp->base + HW_PXP_PS_PITCH); + else if ((s0_params->pixel_fmt == PXP_PIX_FMT_RGB565) || + (s0_params->pixel_fmt == PXP_PIX_FMT_RGB555)) + __raw_writel(pitch << 1, + pxp->base + HW_PXP_PS_PITCH); + else + __raw_writel(0, pxp->base + HW_PXP_PS_PITCH); +} + +/** + * pxp_config() - configure PxP for a processing task + * @pxps: PXP context. + * @pxp_chan: PXP channel. + * @return: 0 on success or negative error code on failure. + */ +static int pxp_config(struct pxps *pxp, struct pxp_channel *pxp_chan) +{ + /* Configure PxP regs */ + pxp_set_ctrl(pxp); + pxp_set_s0param(pxp); + pxp_set_s0crop(pxp); + pxp_set_scaling(pxp); + pxp_set_s0colorkey(pxp); + + pxp_set_oln(0, pxp); + pxp_set_olparam(0, pxp); + pxp_set_olcolorkey(0, pxp); + + pxp_set_csc(pxp); + pxp_set_bg(pxp); + pxp_set_lut(pxp); + + pxp_set_s0buf(pxp); + pxp_set_outbuf(pxp); + + return 0; +} + +static void pxp_clk_enable(struct pxps *pxp) +{ + mutex_lock(&pxp->clk_mutex); + + if (pxp->clk_stat == CLK_STAT_ON) { + mutex_unlock(&pxp->clk_mutex); + return; + } + + pm_runtime_get_sync(pxp->dev); + + if (pxp->clk_disp_axi) + clk_prepare_enable(pxp->clk_disp_axi); + clk_prepare_enable(pxp->clk); + pxp->clk_stat = CLK_STAT_ON; + + mutex_unlock(&pxp->clk_mutex); +} + +static void pxp_clk_disable(struct pxps *pxp) +{ + unsigned long flags; + + mutex_lock(&pxp->clk_mutex); + + if (pxp->clk_stat == CLK_STAT_OFF) { + mutex_unlock(&pxp->clk_mutex); + return; + } + + spin_lock_irqsave(&pxp->lock, flags); + if ((pxp->pxp_ongoing == 0) && list_empty(&head)) { + spin_unlock_irqrestore(&pxp->lock, flags); + clk_disable_unprepare(pxp->clk); + if (pxp->clk_disp_axi) + clk_disable_unprepare(pxp->clk_disp_axi); + pxp->clk_stat = CLK_STAT_OFF; + pm_runtime_put_sync_suspend(pxp->dev); + } else + spin_unlock_irqrestore(&pxp->lock, flags); + + mutex_unlock(&pxp->clk_mutex); +} + +static inline void clkoff_callback(struct work_struct *w) +{ + struct pxps *pxp = container_of(w, struct pxps, work); + + pxp_clk_disable(pxp); +} + +static void pxp_clkoff_timer(struct timer_list *t) +{ + struct pxps *pxp = from_timer(pxp, t, clk_timer); + + if ((pxp->pxp_ongoing == 0) && list_empty(&head)) + schedule_work(&pxp->work); + else + mod_timer(&pxp->clk_timer, + jiffies + msecs_to_jiffies(timeout_in_ms)); +} + +static struct pxp_tx_desc *pxpdma_first_queued(struct pxp_channel *pxp_chan) +{ + return list_entry(pxp_chan->queue.next, struct pxp_tx_desc, list); +} + +/* called with pxp_chan->lock held */ +static void __pxpdma_dostart(struct pxp_channel *pxp_chan) +{ + struct pxp_dma *pxp_dma = to_pxp_dma(pxp_chan->dma_chan.device); + struct pxps *pxp = to_pxp(pxp_dma); + struct pxp_tx_desc *desc; + struct pxp_tx_desc *child; + int i = 0; + + memset(&pxp->pxp_conf_state.s0_param, 0, sizeof(struct pxp_layer_param)); + memset(&pxp->pxp_conf_state.out_param, 0, sizeof(struct pxp_layer_param)); + memset(pxp->pxp_conf_state.ol_param, 0, sizeof(struct pxp_layer_param) * 8); + memset(&pxp->pxp_conf_state.proc_data, 0, sizeof(struct pxp_proc_data)); + /* S0 */ + desc = list_first_entry(&head, struct pxp_tx_desc, list); + memcpy(&pxp->pxp_conf_state.s0_param, + &desc->layer_param.s0_param, sizeof(struct pxp_layer_param)); + memcpy(&pxp->pxp_conf_state.proc_data, + &desc->proc_data, sizeof(struct pxp_proc_data)); + + /* Save PxP configuration */ + list_for_each_entry(child, &desc->tx_list, list) { + if (i == 0) { /* Output */ + memcpy(&pxp->pxp_conf_state.out_param, + &child->layer_param.out_param, + sizeof(struct pxp_layer_param)); + } else { /* Overlay */ + memcpy(&pxp->pxp_conf_state.ol_param[i - 1], + &child->layer_param.ol_param, + sizeof(struct pxp_layer_param)); + } + + i++; + } + pr_debug("%s:%d S0 w/h %d/%d paddr %08x\n", __func__, __LINE__, + pxp->pxp_conf_state.s0_param.width, + pxp->pxp_conf_state.s0_param.height, + pxp->pxp_conf_state.s0_param.paddr); + pr_debug("%s:%d OUT w/h %d/%d paddr %08x\n", __func__, __LINE__, + pxp->pxp_conf_state.out_param.width, + pxp->pxp_conf_state.out_param.height, + pxp->pxp_conf_state.out_param.paddr); +} + +static void pxpdma_dostart_work(struct pxps *pxp) +{ + struct pxp_channel *pxp_chan = NULL; + unsigned long flags; + struct pxp_tx_desc *desc = NULL; + + spin_lock_irqsave(&pxp->lock, flags); + + desc = list_entry(head.next, struct pxp_tx_desc, list); + pxp_chan = to_pxp_channel(desc->txd.chan); + + __pxpdma_dostart(pxp_chan); + + /* Configure PxP */ + pxp_config(pxp, pxp_chan); + + pxp_start(pxp); + + spin_unlock_irqrestore(&pxp->lock, flags); +} + +static void pxpdma_dequeue(struct pxp_channel *pxp_chan, struct pxps *pxp) +{ + unsigned long flags; + struct pxp_tx_desc *desc = NULL; + + do { + desc = pxpdma_first_queued(pxp_chan); + spin_lock_irqsave(&pxp->lock, flags); + list_move_tail(&desc->list, &head); + spin_unlock_irqrestore(&pxp->lock, flags); + } while (!list_empty(&pxp_chan->queue)); +} + +static dma_cookie_t pxp_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct pxp_tx_desc *desc = to_tx_desc(tx); + struct pxp_channel *pxp_chan = to_pxp_channel(tx->chan); + dma_cookie_t cookie; + + dev_dbg(&pxp_chan->dma_chan.dev->device, "received TX\n"); + + /* pxp_chan->lock can be taken under ichan->lock, but not v.v. */ + spin_lock(&pxp_chan->lock); + + cookie = pxp_chan->dma_chan.cookie; + + if (++cookie < 0) + cookie = 1; + + /* from dmaengine.h: "last cookie value returned to client" */ + pxp_chan->dma_chan.cookie = cookie; + tx->cookie = cookie; + + /* Here we add the tx descriptor to our PxP task queue. */ + list_add_tail(&desc->list, &pxp_chan->queue); + + spin_unlock(&pxp_chan->lock); + + dev_dbg(&pxp_chan->dma_chan.dev->device, "done TX\n"); + + return cookie; +} + +/** + * pxp_init_channel() - initialize a PXP channel. + * @pxp_dma: PXP DMA context. + * @pchan: pointer to the channel object. + * @return 0 on success or negative error code on failure. + */ +static int pxp_init_channel(struct pxp_dma *pxp_dma, + struct pxp_channel *pxp_chan) +{ + int ret = 0; + + /* + * We are using _virtual_ channel here. + * Each channel contains all parameters of corresponding layers + * for one transaction; each layer is represented as one descriptor + * (i.e., pxp_tx_desc) here. + */ + + INIT_LIST_HEAD(&pxp_chan->queue); + + return ret; +} + +static irqreturn_t pxp_irq(int irq, void *dev_id) +{ + struct pxps *pxp = dev_id; + struct pxp_channel *pxp_chan; + struct pxp_tx_desc *desc; + struct pxp_tx_desc *child, *_child; + dma_async_tx_callback callback; + void *callback_param; + unsigned long flags; + u32 hist_status; + + dump_pxp_reg(pxp); + + hist_status = + __raw_readl(pxp->base + HW_PXP_HIST_CTRL) & BM_PXP_HIST_CTRL_STATUS; + + __raw_writel(BM_PXP_STAT_IRQ, pxp->base + HW_PXP_STAT_CLR); + + /* set the SFTRST bit to be 1 to reset + * the PXP block to its default state. + */ + pxp_soft_reset(pxp); + + spin_lock_irqsave(&pxp->lock, flags); + + if (list_empty(&head)) { + pxp->pxp_ongoing = 0; + spin_unlock_irqrestore(&pxp->lock, flags); + return IRQ_NONE; + } + + /* Get descriptor and call callback */ + desc = list_entry(head.next, struct pxp_tx_desc, list); + pxp_chan = to_pxp_channel(desc->txd.chan); + + pxp_chan->completed = desc->txd.cookie; + + callback = desc->txd.callback; + callback_param = desc->txd.callback_param; + + /* Send histogram status back to caller */ + desc->hist_status = hist_status; + + if ((desc->txd.flags & DMA_PREP_INTERRUPT) && callback) + callback(callback_param); + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; + + list_for_each_entry_safe(child, _child, &desc->tx_list, list) { + list_del_init(&child->list); + kmem_cache_free(tx_desc_cache, (void *)child); + } + list_del_init(&desc->list); + kmem_cache_free(tx_desc_cache, (void *)desc); + + complete(&pxp->complete); + pxp->pxp_ongoing = 0; + mod_timer(&pxp->clk_timer, jiffies + msecs_to_jiffies(timeout_in_ms)); + + spin_unlock_irqrestore(&pxp->lock, flags); + + return IRQ_HANDLED; +} + +/* allocate/free dma tx descriptor dynamically*/ +static struct pxp_tx_desc *pxpdma_desc_alloc(struct pxp_channel *pxp_chan) +{ + struct pxp_tx_desc *desc = NULL; + struct dma_async_tx_descriptor *txd = NULL; + + desc = kmem_cache_alloc(tx_desc_cache, GFP_KERNEL | __GFP_ZERO); + if (desc == NULL) + return NULL; + + INIT_LIST_HEAD(&desc->list); + INIT_LIST_HEAD(&desc->tx_list); + txd = &desc->txd; + dma_async_tx_descriptor_init(txd, &pxp_chan->dma_chan); + txd->tx_submit = pxp_tx_submit; + + return desc; +} + +/* Allocate and initialise a transfer descriptor. */ +static struct dma_async_tx_descriptor *pxp_prep_slave_sg(struct dma_chan *chan, + struct scatterlist + *sgl, + unsigned int sg_len, + enum + dma_transfer_direction + direction, + unsigned long tx_flags, + void *context) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + struct pxps *pxp = to_pxp(pxp_dma); + struct pxp_tx_desc *pos = NULL, *next = NULL; + struct pxp_tx_desc *desc = NULL; + struct pxp_tx_desc *first = NULL, *prev = NULL; + struct scatterlist *sg; + dma_addr_t phys_addr; + int i; + + if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV) { + dev_err(chan->device->dev, "Invalid DMA direction %d!\n", + direction); + return NULL; + } + + if (unlikely(sg_len < 2)) + return NULL; + + for_each_sg(sgl, sg, sg_len, i) { + desc = pxpdma_desc_alloc(pxp_chan); + if (!desc) { + dev_err(chan->device->dev, "no enough memory to allocate tx descriptor\n"); + + if (first) { + list_for_each_entry_safe(pos, next, &first->tx_list, list) { + list_del_init(&pos->list); + kmem_cache_free(tx_desc_cache, (void*)pos); + } + list_del_init(&first->list); + kmem_cache_free(tx_desc_cache, (void*)first); + } + + return NULL; + } + + phys_addr = sg_dma_address(sg); + + if (!first) { + first = desc; + + desc->layer_param.s0_param.paddr = phys_addr; + } else { + list_add_tail(&desc->list, &first->tx_list); + prev->next = desc; + desc->next = NULL; + + if (i == 1) + desc->layer_param.out_param.paddr = phys_addr; + else + desc->layer_param.ol_param.paddr = phys_addr; + } + + prev = desc; + } + + pxp->pxp_conf_state.layer_nr = sg_len; + first->txd.flags = tx_flags; + first->len = sg_len; + pr_debug("%s:%d first %p, first->len %d, flags %08x\n", + __func__, __LINE__, first, first->len, first->txd.flags); + + return &first->txd; +} + +static void pxp_issue_pending(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + struct pxps *pxp = to_pxp(pxp_dma); + + spin_lock(&pxp_chan->lock); + + if (list_empty(&pxp_chan->queue)) { + spin_unlock(&pxp_chan->lock); + return; + } + + pxpdma_dequeue(pxp_chan, pxp); + pxp_chan->status = PXP_CHANNEL_READY; + + spin_unlock(&pxp_chan->lock); + + pxp_clk_enable(pxp); + wake_up_interruptible(&pxp->thread_waitq); +} + +static void __pxp_terminate_all(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; +} + +static int pxp_device_terminate_all(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + spin_lock(&pxp_chan->lock); + __pxp_terminate_all(chan); + spin_unlock(&pxp_chan->lock); + + return 0; +} + +static int pxp_alloc_chan_resources(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + int ret; + + /* dmaengine.c now guarantees to only offer free channels */ + BUG_ON(chan->client_count > 1); + WARN_ON(pxp_chan->status != PXP_CHANNEL_FREE); + + chan->cookie = 1; + pxp_chan->completed = -ENXIO; + + pr_debug("%s dma_chan.chan_id %d\n", __func__, chan->chan_id); + ret = pxp_init_channel(pxp_dma, pxp_chan); + if (ret < 0) + goto err_chan; + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; + + dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n", + chan->chan_id, pxp_chan->eof_irq); + + return ret; + +err_chan: + return ret; +} + +static void pxp_free_chan_resources(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + spin_lock(&pxp_chan->lock); + + __pxp_terminate_all(chan); + + pxp_chan->status = PXP_CHANNEL_FREE; + + spin_unlock(&pxp_chan->lock); +} + +static enum dma_status pxp_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + if (cookie != chan->cookie) + return DMA_ERROR; + + if (txstate) { + txstate->last = pxp_chan->completed; + txstate->used = chan->cookie; + txstate->residue = 0; + } + return DMA_COMPLETE; +} + +static int pxp_dma_init(struct pxps *pxp) +{ + struct pxp_dma *pxp_dma = &pxp->pxp_dma; + struct dma_device *dma = &pxp_dma->dma; + int i; + + dma_cap_set(DMA_SLAVE, dma->cap_mask); + dma_cap_set(DMA_PRIVATE, dma->cap_mask); + + /* Compulsory common fields */ + dma->dev = pxp->dev; + dma->device_alloc_chan_resources = pxp_alloc_chan_resources; + dma->device_free_chan_resources = pxp_free_chan_resources; + dma->device_tx_status = pxp_tx_status; + dma->device_issue_pending = pxp_issue_pending; + + /* Compulsory for DMA_SLAVE fields */ + dma->device_prep_slave_sg = pxp_prep_slave_sg; + dma->device_terminate_all = pxp_device_terminate_all; + + /* Initialize PxP Channels */ + INIT_LIST_HEAD(&dma->channels); + for (i = 0; i < NR_PXP_VIRT_CHANNEL; i++) { + struct pxp_channel *pxp_chan = pxp->channel + i; + struct dma_chan *dma_chan = &pxp_chan->dma_chan; + + spin_lock_init(&pxp_chan->lock); + + /* Only one EOF IRQ for PxP, shared by all channels */ + pxp_chan->eof_irq = pxp->irq; + pxp_chan->status = PXP_CHANNEL_FREE; + pxp_chan->completed = -ENXIO; + snprintf(pxp_chan->eof_name, sizeof(pxp_chan->eof_name), + "PXP EOF %d", i); + + dma_chan->device = &pxp_dma->dma; + dma_chan->cookie = 1; + dma_chan->chan_id = i; + list_add_tail(&dma_chan->device_node, &dma->channels); + } + + return dma_async_device_register(&pxp_dma->dma); +} + +static ssize_t clk_off_timeout_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", timeout_in_ms); +} + +static ssize_t clk_off_timeout_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int val; + if (sscanf(buf, "%d", &val) > 0) { + timeout_in_ms = val; + return count; + } + return -EINVAL; +} + +static DEVICE_ATTR(clk_off_timeout, 0644, clk_off_timeout_show, + clk_off_timeout_store); + +static ssize_t block_size_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%d\n", block_size); +} + +static ssize_t block_size_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + char **last = NULL; + + block_size = simple_strtoul(buf, last, 0); + if (block_size > 1) + block_size = 1; + + return count; +} +static DEVICE_ATTR(block_size, S_IWUSR | S_IRUGO, + block_size_show, block_size_store); + +static const struct of_device_id imx_pxpdma_dt_ids[] = { + { .compatible = "fsl,imx6dl-pxp-dma", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx_pxpdma_dt_ids); + +static int has_pending_task(struct pxps *pxp, struct pxp_channel *task) +{ + int found; + unsigned long flags; + + spin_lock_irqsave(&pxp->lock, flags); + found = !list_empty(&head); + spin_unlock_irqrestore(&pxp->lock, flags); + + return found; +} + +static int pxp_dispatch_thread(void *argv) +{ + struct pxps *pxp = (struct pxps *)argv; + struct pxp_channel *pending = NULL; + unsigned long flags; + + set_freezable(); + + while (!kthread_should_stop()) { + int ret; + ret = wait_event_freezable(pxp->thread_waitq, + has_pending_task(pxp, pending) || + kthread_should_stop()); + if (ret < 0) + continue; + + if (kthread_should_stop()) + break; + + spin_lock_irqsave(&pxp->lock, flags); + pxp->pxp_ongoing = 1; + spin_unlock_irqrestore(&pxp->lock, flags); + init_completion(&pxp->complete); + pxpdma_dostart_work(pxp); + ret = wait_for_completion_timeout(&pxp->complete, 2 * HZ); + if (ret == 0) { + printk(KERN_EMERG "%s: task is timeout\n\n", __func__); + break; + } + } + + return 0; +} + +static int pxp_probe(struct platform_device *pdev) +{ + struct pxps *pxp; + struct resource *res; + int irq; + int err = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + irq = platform_get_irq(pdev, 0); + if (!res || irq < 0) { + err = -ENODEV; + goto exit; + } + + pxp = devm_kzalloc(&pdev->dev, sizeof(*pxp), GFP_KERNEL); + if (!pxp) { + dev_err(&pdev->dev, "failed to allocate control object\n"); + err = -ENOMEM; + goto exit; + } + + pxp->dev = &pdev->dev; + + platform_set_drvdata(pdev, pxp); + pxp->irq = irq; + + spin_lock_init(&pxp->lock); + mutex_init(&pxp->clk_mutex); + + pxp->base = devm_ioremap_resource(&pdev->dev, res); + if (pxp->base == NULL) { + dev_err(&pdev->dev, "Couldn't ioremap regs\n"); + err = -ENODEV; + goto exit; + } + + pxp->pdev = pdev; + + pxp->clk_disp_axi = devm_clk_get(&pdev->dev, "disp-axi"); + if (IS_ERR(pxp->clk_disp_axi)) + pxp->clk_disp_axi = NULL; + pxp->clk = devm_clk_get(&pdev->dev, "pxp-axi"); + + err = devm_request_irq(&pdev->dev, pxp->irq, pxp_irq, 0, + "pxp-dmaengine", pxp); + if (err) + goto exit; + /* Initialize DMA engine */ + err = pxp_dma_init(pxp); + if (err < 0) + goto exit; + + if (device_create_file(&pdev->dev, &dev_attr_clk_off_timeout)) { + dev_err(&pdev->dev, + "Unable to create file from clk_off_timeout\n"); + goto exit; + } + + device_create_file(&pdev->dev, &dev_attr_block_size); + pxp_clk_enable(pxp); + dump_pxp_reg(pxp); + pxp_clk_disable(pxp); + + INIT_WORK(&pxp->work, clkoff_callback); + timer_setup(&pxp->clk_timer, pxp_clkoff_timer, 0); + + init_waitqueue_head(&pxp->thread_waitq); + /* allocate a kernel thread to dispatch pxp conf */ + pxp->dispatch = kthread_run(pxp_dispatch_thread, pxp, "pxp_dispatch"); + if (IS_ERR(pxp->dispatch)) { + err = PTR_ERR(pxp->dispatch); + goto exit; + } + tx_desc_cache = kmem_cache_create("tx_desc", sizeof(struct pxp_tx_desc), + 0, SLAB_HWCACHE_ALIGN, NULL); + if (!tx_desc_cache) { + err = -ENOMEM; + goto exit; + } + + register_pxp_device(); + + pm_runtime_enable(pxp->dev); + +exit: + if (err) + dev_err(&pdev->dev, "Exiting (unsuccessfully) pxp_probe()\n"); + return err; +} + +static int pxp_remove(struct platform_device *pdev) +{ + struct pxps *pxp = platform_get_drvdata(pdev); + + unregister_pxp_device(); + kmem_cache_destroy(tx_desc_cache); + kthread_stop(pxp->dispatch); + cancel_work_sync(&pxp->work); + del_timer_sync(&pxp->clk_timer); + clk_disable_unprepare(pxp->clk); + if (pxp->clk_disp_axi) + clk_disable_unprepare(pxp->clk_disp_axi); + device_remove_file(&pdev->dev, &dev_attr_clk_off_timeout); + device_remove_file(&pdev->dev, &dev_attr_block_size); + dma_async_device_unregister(&(pxp->pxp_dma.dma)); + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int pxp_suspend(struct device *dev) +{ + struct pxps *pxp = dev_get_drvdata(dev); + + pxp_clk_enable(pxp); + while (__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_ENABLE) + ; + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL); + pxp_clk_disable(pxp); + + return 0; +} + +static int pxp_resume(struct device *dev) +{ + struct pxps *pxp = dev_get_drvdata(dev); + + pxp_clk_enable(pxp); + /* Pull PxP out of reset */ + __raw_writel(0, pxp->base + HW_PXP_CTRL); + pxp_clk_disable(pxp); + + return 0; +} +#else +#define pxp_suspend NULL +#define pxp_resume NULL +#endif + +#ifdef CONFIG_PM +static int pxp_runtime_suspend(struct device *dev) +{ + dev_dbg(dev, "pxp busfreq high release.\n"); + return 0; +} + +static int pxp_runtime_resume(struct device *dev) +{ + dev_dbg(dev, "pxp busfreq high request.\n"); + return 0; +} +#else +#define pxp_runtime_suspend NULL +#define pxp_runtime_resume NULL +#endif + +static const struct dev_pm_ops pxp_pm_ops = { + SET_RUNTIME_PM_OPS(pxp_runtime_suspend, pxp_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pxp_suspend, pxp_resume) +}; + +static struct platform_driver pxp_driver = { + .driver = { + .name = "imx-pxp", + .of_match_table = of_match_ptr(imx_pxpdma_dt_ids), + .pm = &pxp_pm_ops, + }, + .probe = pxp_probe, + .remove = pxp_remove, +}; + +module_platform_driver(pxp_driver); + + +MODULE_DESCRIPTION("i.MX PxP driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/dma/pxp/pxp_dma_v3.c b/drivers/dma/pxp/pxp_dma_v3.c new file mode 100644 index 00000000000000..0b6afe03c1fa81 --- /dev/null +++ b/drivers/dma/pxp/pxp_dma_v3.c @@ -0,0 +1,8153 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. + * + * Copyright 2017-2019 NXP + */ +/* + * Based on STMP378X PxP driver + * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "regs-pxp_v3.h" +#include "reg_bitfields.h" + +#ifdef CONFIG_MXC_FPGA_M4_TEST +#include "cm4_image.c" +#define FPGA_TCML_ADDR 0x0C7F8000 +#define PINCTRL 0x0C018000 +#define PIN_DOUT 0x700 +void __iomem *fpga_tcml_base; +void __iomem *pinctrl_base; +#endif + + +#define PXP_FILL_TIMEOUT 3000 +#define busy_wait(cond) \ + ({ \ + unsigned long end_jiffies = jiffies + \ + msecs_to_jiffies(PXP_FILL_TIMEOUT); \ + bool succeeded = false; \ + do { \ + if (cond) { \ + succeeded = true; \ + break; \ + } \ + cpu_relax(); \ + } while (time_after(end_jiffies, jiffies)); \ + succeeded; \ + }) + +#define PXP_DOWNSCALE_THRESHOLD 0x4000 + +#define CONFIG_FB_MXC_EINK_FPGA + +/* define all the pxp 2d nodes */ +#define PXP_2D_PS 0 +#define PXP_2D_AS 1 +#define PXP_2D_INPUT_FETCH0 2 +#define PXP_2D_INPUT_FETCH1 3 +#define PXP_2D_CSC1 4 +#define PXP_2D_ROTATION1 5 +#define PXP_2D_ALPHA0_S0 6 +#define PXP_2D_ALPHA0_S1 7 +#define PXP_2D_ALPHA1_S0 8 +#define PXP_2D_ALPHA1_S1 9 +#define PXP_2D_CSC2 10 +#define PXP_2D_LUT 11 +#define PXP_2D_ROTATION0 12 +#define PXP_2D_OUT 13 +#define PXP_2D_INPUT_STORE0 14 +#define PXP_2D_INPUT_STORE1 15 +#define PXP_2D_NUM 16 + +#define PXP_2D_ALPHA0_S0_S1 0xaa +#define PXP_2D_ALPHA1_S0_S1 0xbb + +#define PXP_2D_MUX_BASE 50 +#define PXP_2D_MUX_MUX0 (PXP_2D_MUX_BASE + 0) +#define PXP_2D_MUX_MUX1 (PXP_2D_MUX_BASE + 1) +#define PXP_2D_MUX_MUX2 (PXP_2D_MUX_BASE + 2) +#define PXP_2D_MUX_MUX3 (PXP_2D_MUX_BASE + 3) +#define PXP_2D_MUX_MUX4 (PXP_2D_MUX_BASE + 4) +#define PXP_2D_MUX_MUX5 (PXP_2D_MUX_BASE + 5) +#define PXP_2D_MUX_MUX6 (PXP_2D_MUX_BASE + 6) +#define PXP_2D_MUX_MUX7 (PXP_2D_MUX_BASE + 7) +#define PXP_2D_MUX_MUX8 (PXP_2D_MUX_BASE + 8) +#define PXP_2D_MUX_MUX9 (PXP_2D_MUX_BASE + 9) +#define PXP_2D_MUX_MUX10 (PXP_2D_MUX_BASE + 10) +#define PXP_2D_MUX_MUX11 (PXP_2D_MUX_BASE + 11) +#define PXP_2D_MUX_MUX12 (PXP_2D_MUX_BASE + 12) +#define PXP_2D_MUX_MUX13 (PXP_2D_MUX_BASE + 13) +#define PXP_2D_MUX_MUX14 (PXP_2D_MUX_BASE + 14) +#define PXP_2D_MUX_MUX15 (PXP_2D_MUX_BASE + 15) + +/* define pxp 2d node types */ +#define PXP_2D_TYPE_INPUT 1 +#define PXP_2D_TYPE_ALU 2 +#define PXP_2D_TYPE_OUTPUT 3 + +#define DISTANCE_INFINITY 0xffff +#define NO_PATH_NODE 0xffffffff + +#define PXP_MAX_INPUT_NUM 2 +#define PXP_MAX_OUTPUT_NUM 2 + +#define FETCH_NOOP 0x01 +#define FETCH_EXPAND 0x02 +#define FETCH_SHIFT 0x04 + +#define STORE_NOOP 0x01 +#define STORE_SHIFT 0x02 +#define STORE_SHRINK 0x04 + +#define NEED_YUV_SWAP 0x02 + +#define IN_NEED_COMPOSITE (0x01 | IN_NEED_FMT_UNIFIED) +#define IN_NEED_CSC (0x02 | IN_NEED_FMT_UNIFIED) +#define IN_NEED_SCALE (0x04 | IN_NEED_FMT_UNIFIED) +#define IN_NEED_ROTATE_FLIP (0x08 | IN_NEED_FMT_UNIFIED) +#define IN_NEED_FMT_UNIFIED 0x10 +#define IN_NEED_SHIFT 0x20 +#define IN_NEED_LUT (0x40 | IN_NEED_UNIFIED) + +#define OUT_NEED_SHRINK 0x100 +#define OUT_NEED_SHIFT 0x200 + +#define PXP_ROTATE_0 0 +#define PXP_ROTATE_90 1 +#define PXP_ROTATE_180 2 +#define PXP_ROTATE_270 3 + +#define PXP_H_FLIP 1 +#define PXP_V_FLIP 2 + +#define PXP_OP_TYPE_2D 0x001 +#define PXP_OP_TYPE_DITHER 0x002 +#define PXP_OP_TYPE_WFE_A 0x004 +#define PXP_OP_TYPE_WFE_B 0x008 + +/* define store engine output mode */ +#define STORE_MODE_NORMAL 1 +#define STORE_MODE_BYPASS 2 +#define STORE_MODE_DUAL 3 +#define STORE_MODE_HANDSHAKE 4 + +/* define fetch engine input mode */ +#define FETCH_MODE_NORMAL 1 +#define FETCH_MODE_BYPASS 2 +#define FETCH_MODE_HANDSHAKE 3 + +#define COMMON_FMT_BPP 32 + +#define R_COMP 0 +#define G_COMP 1 +#define B_COMP 2 +#define A_COMP 3 + +#define Y_COMP 0 +#define U_COMP 1 +#define V_COMP 2 +#define Y1_COMP 4 + +static LIST_HEAD(head); +static int timeout_in_ms = 600; +static unsigned int block_size; +static struct kmem_cache *tx_desc_cache; +static struct kmem_cache *edge_node_cache; +static struct pxp_collision_info col_info; +static bool v3p_flag; +static int alpha_blending_version; +static bool pxp_legacy; + +struct pxp_dma { + struct dma_device dma; +}; + +enum pxp_alpha_blending_version { + PXP_ALPHA_BLENDING_NONE = 0x0, + PXP_ALPHA_BLENDING_V1 = 0x1, + PXP_ALPHA_BLENDING_V2 = 0x2, +}; + +struct pxp_alpha_global { + unsigned int color_key_enable; + bool combine_enable; + bool global_alpha_enable; + bool global_override; + bool alpha_invert; + bool local_alpha_enable; + unsigned char global_alpha; + int comp_mask; +}; + +struct rectangle { + uint16_t x; + uint16_t y; + uint16_t width; + uint16_t height; +}; + +struct pxp_alpha_info { + uint8_t alpha_mode; + uint8_t rop_type; + + struct pxp_alpha s0_alpha; + struct pxp_alpha s1_alpha; +}; + +struct pxp_op_info{ + uint16_t op_type; + uint16_t rotation; + uint8_t flip; + uint8_t fill_en; + uint32_t fill_data; + uint8_t alpha_blending; + struct pxp_alpha_info alpha_info; + + /* Dithering specific data */ + uint32_t dither_mode; + uint32_t quant_bit; + + /* + * partial: + * 0 - full update + * 1 - partial update + * alpha_en: + * 0 - upd is {Y4[3:0],4'b0000} format + * 1 - upd is {Y4[3:0],3'b000,alpha} format + * reagl_en: + * 0 - use normal waveform algorithm + * 1 - enable reagl/-d waveform algorithm + * detection_only: + * 0 - write working buffer + * 1 - do no write working buffer, detection only + * lut: + * valid value 0-63 + * set to the lut used for next update + */ + bool partial_update; + bool alpha_en; + bool lut_update; + bool reagl_en; /* enable reagl/-d */ + bool reagl_d_en; /* enable reagl or reagl-d */ + bool detection_only; + int lut; + uint32_t lut_status_1; + uint32_t lut_status_2; +}; + +struct pxp_pixmap { + uint8_t channel_id; + uint8_t bpp; + int32_t pitch; + uint16_t width; + uint16_t height; + struct rectangle crop; + uint32_t rotate; + uint8_t flip; + uint32_t format; /* fourcc pixmap format */ + uint32_t flags; + bool valid; + dma_addr_t paddr; + struct pxp_alpha_global g_alpha; +}; + +struct pxp_task_info { + uint8_t input_num; + uint8_t output_num; + struct pxp_pixmap input[PXP_MAX_INPUT_NUM]; + struct pxp_pixmap output[PXP_MAX_OUTPUT_NUM]; + struct pxp_op_info op_info; + uint32_t pxp_2d_flags; +}; + +struct pxps { + struct platform_device *pdev; + struct clk *ipg_clk; + struct clk *axi_clk; + void __iomem *base; + int irq; /* PXP IRQ to the CPU */ + + spinlock_t lock; + struct mutex clk_mutex; + int clk_stat; +#define CLK_STAT_OFF 0 +#define CLK_STAT_ON 1 + int pxp_ongoing; + int lut_state; + + struct device *dev; + struct pxp_dma pxp_dma; + struct pxp_channel channel[NR_PXP_VIRT_CHANNEL]; + struct work_struct work; + + const struct pxp_devdata *devdata; + struct pxp_task_info task; + + /* describes most recent processing configuration */ + struct pxp_config_data pxp_conf_state; + + /* to turn clock off when pxp is inactive */ + struct timer_list clk_timer; + + /* for pxp config dispatch asynchronously*/ + struct task_struct *dispatch; + wait_queue_head_t thread_waitq; + struct completion complete; +}; + +#define to_pxp_dma(d) container_of(d, struct pxp_dma, dma) +#define to_tx_desc(tx) container_of(tx, struct pxp_tx_desc, txd) +#define to_pxp_channel(d) container_of(d, struct pxp_channel, dma_chan) +#define to_pxp(id) container_of(id, struct pxps, pxp_dma) + +#define to_pxp_task_info(op) container_of((op), struct pxp_task_info, op_info) +#define to_pxp_from_task(task) container_of((task), struct pxps, task) + +#define PXP_DEF_BUFS 2 +#define PXP_MIN_PIX 8 + +static uint8_t active_bpp(uint8_t bpp) +{ + switch(bpp) { + case 8: + return 0x0; + case 16: + return 0x1; + case 32: + return 0x2; + case 64: + return 0x3; + default: + return 0xff; + } +} + +static uint8_t rotate_map(uint32_t degree) +{ + switch (degree) { + case 0: + return PXP_ROTATE_0; + case 90: + return PXP_ROTATE_90; + case 180: + return PXP_ROTATE_180; + case 270: + return PXP_ROTATE_270; + default: + return 0; + } +} + +static uint8_t expand_format(uint32_t format) +{ + switch (format) { + case PXP_PIX_FMT_RGB565: + case PXP_PIX_FMT_BGR565: + return 0x0; + case PXP_PIX_FMT_RGB555: + return 0x1; + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_YVYU: + return 0x5; + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_VYUY: + return 0x6; + case PXP_PIX_FMT_NV16: + return 0x7; + default: + return 0xff; + } +} + +struct color_component { + uint8_t id; + uint8_t offset; + uint8_t length; + uint8_t mask; +}; + +struct color { + uint32_t format; + struct color_component comp[4]; +}; + +struct color rgb_colors[] = { + { + .format = PXP_PIX_FMT_RGB565, + .comp = { + { .id = B_COMP, .offset = 0, .length = 5, .mask = 0x1f, }, + { .id = G_COMP, .offset = 5, .length = 6, .mask = 0x3f, }, + { .id = R_COMP, .offset = 11, .length = 5, .mask = 0x1f, }, + { .id = A_COMP, .offset = 0, .length = 0, .mask = 0x0, }, + }, + }, { + .format = PXP_PIX_FMT_BGR565, + .comp = { + { .id = R_COMP, .offset = 0, .length = 5, .mask = 0x1f, }, + { .id = G_COMP, .offset = 5, .length = 6, .mask = 0x3f, }, + { .id = B_COMP, .offset = 11, .length = 6, .mask = 0x3f, }, + { .id = A_COMP, .offset = 0, .length = 0, .mask = 0x0, }, + }, + }, { + .format = PXP_PIX_FMT_ARGB555, + .comp = { + { .id = B_COMP, .offset = 0, .length = 5, .mask = 0x1f, }, + { .id = G_COMP, .offset = 5, .length = 5, .mask = 0x1f, }, + { .id = R_COMP, .offset = 10, .length = 5, .mask = 0x1f, }, + { .id = A_COMP, .offset = 15, .length = 1, .mask = 0x1, }, + }, + }, { + .format = PXP_PIX_FMT_XRGB555, + .comp = { + { .id = B_COMP, .offset = 0, .length = 5, .mask = 0x1f, }, + { .id = G_COMP, .offset = 5, .length = 5, .mask = 0x1f, }, + { .id = R_COMP, .offset = 10, .length = 5, .mask = 0x1f, }, + { .id = A_COMP, .offset = 15, .length = 1, .mask = 0x1, }, + }, + }, { + .format = PXP_PIX_FMT_RGB555, + .comp = { + { .id = B_COMP, .offset = 0, .length = 5, .mask = 0x1f, }, + { .id = G_COMP, .offset = 5, .length = 5, .mask = 0x1f, }, + { .id = R_COMP, .offset = 10, .length = 5, .mask = 0x1f, }, + { .id = A_COMP, .offset = 15, .length = 1, .mask = 0x1, }, + }, + }, { + .format = PXP_PIX_FMT_RGBA555, + .comp = { + { .id = A_COMP, .offset = 0, .length = 1, .mask = 0x1, }, + { .id = B_COMP, .offset = 1, .length = 5, .mask = 0x1f, }, + { .id = G_COMP, .offset = 6, .length = 5, .mask = 0x1f, }, + { .id = R_COMP, .offset = 11, .length = 5, .mask = 0x1f, }, + }, + }, { + .format = PXP_PIX_FMT_ARGB444, + .comp = { + { .id = B_COMP, .offset = 0, .length = 4, .mask = 0xf, }, + { .id = G_COMP, .offset = 4, .length = 4, .mask = 0xf, }, + { .id = R_COMP, .offset = 8, .length = 4, .mask = 0xf, }, + { .id = A_COMP, .offset = 12, .length = 4, .mask = 0xf, }, + }, + }, { + .format = PXP_PIX_FMT_XRGB444, + .comp = { + { .id = B_COMP, .offset = 0, .length = 4, .mask = 0xf, }, + { .id = G_COMP, .offset = 4, .length = 4, .mask = 0xf, }, + { .id = R_COMP, .offset = 8, .length = 4, .mask = 0xf, }, + { .id = A_COMP, .offset = 12, .length = 4, .mask = 0xf, }, + }, + }, { + .format = PXP_PIX_FMT_RGBA444, + .comp = { + { .id = A_COMP, .offset = 0, .length = 4, .mask = 0xf, }, + { .id = B_COMP, .offset = 4, .length = 4, .mask = 0xf, }, + { .id = G_COMP, .offset = 8, .length = 4, .mask = 0xf, }, + { .id = R_COMP, .offset = 12, .length = 4, .mask = 0xf, }, + }, + }, { + .format = PXP_PIX_FMT_RGB24, + .comp = { + { .id = B_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 0, .length = 0, .mask = 0x0, }, + }, + }, { + .format = PXP_PIX_FMT_BGR24, + .comp = { + { .id = R_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 0, .length = 0, .mask = 0x0, }, + }, + }, { + .format = PXP_PIX_FMT_XRGB32, + .comp = { + { .id = B_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_RGBX32, + .comp = { + { .id = A_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_XBGR32, + .comp = { + { .id = R_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_BGRX32, + .comp = { + { .id = A_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_ARGB32, + .comp = { + { .id = B_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_ABGR32, + .comp = { + { .id = R_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_RGBA32, + .comp = { + { .id = A_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_BGRA32, + .comp = { + { .id = A_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, +}; + +/* only one plane yuv formats */ +struct color yuv_colors[] = { + { + .format = PXP_PIX_FMT_GREY, + .comp = { + { .id = Y_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = U_COMP, .offset = 8, .length = 0, .mask = 0x00, }, + { .id = V_COMP, .offset = 16, .length = 0, .mask = 0x00, }, + { .id = A_COMP, .offset = 24, .length = 0, .mask = 0x00, }, + }, + }, { + .format = PXP_PIX_FMT_YUYV, + .comp = { + { .id = V_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = Y1_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = U_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = Y_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_UYVY, + .comp = { + { .id = Y1_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = V_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = Y_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = U_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_YVYU, + .comp = { + { .id = U_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = Y1_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = V_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = Y_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_VYUY, + .comp = { + { .id = Y1_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = U_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = Y_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = V_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_YUV444, + .comp = { + { .id = V_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = U_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = Y_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_YVU444, + .comp = { + { .id = U_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = V_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = Y_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, +}; + +/* 4 to 1 mux */ +struct mux { + uint32_t id; + uint8_t mux_inputs[4]; + uint8_t mux_outputs[2]; +}; + +/* Adjacent list structure */ +struct edge_node { + uint32_t adjvex; + uint32_t prev_vnode; + struct edge_node *next; + uint32_t mux_used; + struct mux_config muxes; +}; + +struct vetex_node { + uint8_t type; + struct edge_node *first; +}; + +struct path_node { + struct list_head node; + uint32_t id; + uint32_t distance; + uint32_t prev_node; +}; + +static struct vetex_node adj_list[PXP_2D_NUM]; +static struct path_node path_table[PXP_2D_NUM][PXP_2D_NUM]; + +static bool adj_array_v3[PXP_2D_NUM][PXP_2D_NUM] = { + /* 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 */ + {0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 0 */ + {0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1 */ + {0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0}, /* 2 */ + {0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1}, /* 3 */ + {0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 4 */ + {0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 0, 1, 0}, /* 5 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0}, /* 6 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0}, /* 7 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0}, /* 8 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0}, /* 9 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0}, /* 10 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0}, /* 11 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0}, /* 12 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 13 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 14 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 15 */ +}; + + +static struct mux muxes_v3[16] = { + { + /* mux0 */ + .id = 0, + .mux_inputs = {PXP_2D_CSC1, PXP_2D_INPUT_FETCH0, PXP_2D_INPUT_FETCH1, 0xff}, + .mux_outputs = {PXP_2D_ROTATION1, 0xff}, + }, { + /* mux1 */ + .id = 1, + .mux_inputs = {PXP_2D_INPUT_FETCH0, PXP_2D_ROTATION1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_ALPHA1_S1, PXP_2D_MUX_MUX5}, + }, { + /* mux2 */ + .id = 2, + .mux_inputs = {PXP_2D_INPUT_FETCH1, PXP_2D_ROTATION1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_ALPHA1_S0, 0xff}, + }, { + /* mux3 */ + .id = 3, + .mux_inputs = {PXP_2D_CSC1, PXP_2D_ROTATION1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_ALPHA0_S0, 0xff}, + }, { + /* mux4 is not used in ULT1 */ + .id = 4, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux5 */ + .id = 5, + .mux_inputs = {PXP_2D_MUX_MUX1, PXP_2D_ALPHA1_S0_S1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX7, 0xff}, + }, { + /* mux6 */ + .id = 6, + .mux_inputs = {PXP_2D_ALPHA1_S0_S1, PXP_2D_ALPHA0_S0_S1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_CSC2, 0xff}, + }, { + /* mux7 */ + .id = 7, + .mux_inputs = {PXP_2D_MUX_MUX5, PXP_2D_CSC2, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX9, PXP_2D_MUX_MUX10}, + }, { + /* mux8 */ + .id = 8, + .mux_inputs = {PXP_2D_CSC2, PXP_2D_ALPHA0_S0_S1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX9, PXP_2D_MUX_MUX11}, + }, { + /* mux9 */ + .id = 9, + .mux_inputs = {PXP_2D_MUX_MUX7, PXP_2D_MUX_MUX8, 0xff, 0xff}, + .mux_outputs = {PXP_2D_LUT, 0xff}, + }, { + /* mux10 */ + .id = 10, + .mux_inputs = {PXP_2D_MUX_MUX7, PXP_2D_LUT, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX12, PXP_2D_MUX_MUX15}, + }, { + /* mux11 */ + .id = 11, + .mux_inputs = {PXP_2D_LUT, PXP_2D_MUX_MUX8, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX12, PXP_2D_MUX_MUX14}, + }, { + /* mux12 */ + .id = 12, + .mux_inputs = {PXP_2D_MUX_MUX10, PXP_2D_MUX_MUX11, 0xff, 0xff}, + .mux_outputs = {PXP_2D_ROTATION0, 0xff}, + }, { + /* mux13 */ + .id = 13, + .mux_inputs = {PXP_2D_INPUT_FETCH1, 0xff, 0xff, 0xff}, + .mux_outputs = {PXP_2D_INPUT_STORE1, 0xff}, + }, { + /* mux14 */ + .id = 14, + .mux_inputs = {PXP_2D_ROTATION0, PXP_2D_MUX_MUX11, 0xff, 0xff}, + .mux_outputs = {PXP_2D_OUT, 0xff}, + }, { + /* mux15 */ + .id = 15, + .mux_inputs = {PXP_2D_INPUT_FETCH0, PXP_2D_MUX_MUX10, 0xff, 0xff}, + .mux_outputs = {PXP_2D_INPUT_STORE0, 0xff}, + }, +}; + +static bool adj_array_v3p[PXP_2D_NUM][PXP_2D_NUM] = { + /* 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 */ + {0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 0 */ + {0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 2 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 3 */ + {0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 4 */ + {0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 5 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0}, /* 6 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0}, /* 7 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 8 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 9 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0}, /* 10 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0}, /* 11 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0}, /* 12 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 13 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 14 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 15 */ +}; + +static struct mux muxes_v3p[16] = { + { + /* mux0 */ + .id = 0, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux1 */ + .id = 1, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux2 */ + .id = 2, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux3 */ + .id = 3, + .mux_inputs = {PXP_2D_CSC1, PXP_2D_ROTATION1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_ALPHA0_S0, 0xff}, + }, { + /* mux4 is not used in ULT1 */ + .id = 4, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux5 */ + .id = 5, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux6 */ + .id = 6, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux7 */ + .id = 7, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux8 */ + .id = 8, + .mux_inputs = {PXP_2D_CSC2, PXP_2D_ALPHA0_S0_S1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX9, PXP_2D_MUX_MUX11}, + }, { + /* mux9 */ + .id = 9, + .mux_inputs = {0xff, PXP_2D_MUX_MUX8, 0xff, 0xff}, + .mux_outputs = {PXP_2D_LUT, 0xff}, + }, { + /* mux10 */ + .id = 10, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux11 */ + .id = 11, + .mux_inputs = {PXP_2D_LUT, PXP_2D_MUX_MUX8, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX12, PXP_2D_ROTATION0}, + }, { + /* mux12 */ + .id = 12, + .mux_inputs = {PXP_2D_ROTATION0, PXP_2D_MUX_MUX11, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX14, 0xff}, + }, { + /* mux13 */ + .id = 13, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux14 */ + .id = 14, + .mux_inputs = {0xff, PXP_2D_MUX_MUX12, 0xff, 0xff}, + .mux_outputs = {PXP_2D_OUT, 0xff}, + }, { + /* mux15 */ + .id = 15, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, +}; + +static void __iomem *pxp_reg_base; + +#define pxp_writel(val, reg) writel(val, pxp_reg_base + (reg)) + +static __attribute__((aligned (1024*4))) unsigned int active_matrix_data_8x8[64]={ + 0x06050100, 0x04030207, 0x06050100, 0x04030207, + 0x00040302, 0x07060501, 0x00040302, 0x07060501, + 0x02070605, 0x01000403, 0x02070605, 0x01000403, + 0x05010004, 0x03020706, 0x05010004, 0x03020706, + 0x04030207, 0x06050100, 0x04030207, 0x06050100, + 0x07060501, 0x00040302, 0x07060501, 0x00040302, + 0x01000403, 0x02070605, 0x01000403, 0x02070605, + 0x03020706, 0x05010004, 0x03020706, 0x05010004, + 0x06050100, 0x04030207, 0x06050100, 0x04030207, + 0x00040302, 0x07060501, 0x00040302, 0x07060501, + 0x02070605, 0x01000403, 0x02070605, 0x01000403, + 0x05010004, 0x03020706, 0x05010004, 0x03020706, + 0x04030207, 0x06050100, 0x04030207, 0x06050100, + 0x07060501, 0x00040302, 0x07060501, 0x00040302, + 0x01000403, 0x02070605, 0x01000403, 0x02070605, + 0x03020706, 0x05010004, 0x03020706, 0x05010004 + }; + +static __attribute__((aligned (1024*4))) unsigned int bit1_dither_data_8x8[64] = { + + 1, 49*2, 13*2, 61*2, 4*2, 52*2, 16*2, 64*2, + 33*2, 17*2, 45*2, 29*2, 36*2, 20*2, 48*2, 32*2, + 9*2, 57*2, 5*2, 53*2, 12*2, 60*2, 8*2, 56*2, + 41*2, 25*2, 37*2, 21*2, 44*2, 28*2, 40*2, 24*2, + 3*2, 51*2, 15*2, 63*2, 2*2, 50*2, 14*2, 62*2, + 35*2, 19*2, 47*2, 31*2, 34*2, 18*2, 46*2, 30*2, + 11*2, 59*2, 7*2, 55*2, 10*2, 58*2, 6*2, 54*2, + 43*2, 27*2, 39*2, 23*2, 42*2, 26*2, 38*2, 22*2 +}; + +static __attribute__((aligned (1024*4))) unsigned int bit2_dither_data_8x8[64] = { + + 1, 49, 13, 61, 4, 52, 16, 64, + 33, 17, 45, 29, 36, 20, 48, 32, + 9, 57, 5, 53, 12, 60, 8, 56, + 41, 25, 37, 21, 44, 28, 40, 24, + 3, 51, 15, 63, 2, 50, 14, 62, + 35, 19, 47, 31, 34, 18, 46, 30, + 11, 59, 7, 55, 10, 58, 6, 54, + 43, 27, 39, 23, 42, 26, 38, 22 +}; + +static __attribute__((aligned (1024*4))) unsigned int bit4_dither_data_8x8[64] = { + + 1, 49/4, 13/4, 61/4, 4/4, 52/4, 16/4, 64/4, + 33/4, 17/4, 45/4, 29/4, 36/4, 20/4, 48/4, 32/4, + 9/4, 57/4, 5/4, 53/4, 12/4, 60/4, 8/4, 56/4, + 41/4, 25/4, 37/4, 21/4, 44/4, 28/4, 40/4, 24/4, + 3/4, 51/4, 15/4, 63/4, 2/4, 50/4, 14/4, 62/4, + 35/4, 19/4, 47/4, 31/4, 34/4, 18/4, 46/4, 30/4, + 11/4, 59/4, 7/4, 55/4, 10/4, 58/4, 6/4, 54/4, + 43/4, 27/4, 39/4, 23/4, 42/4, 26/4, 38/4, 22/4 +}; + +static void pxp_dithering_configure(struct pxps *pxp); +static void pxp_dithering_configure_v3p(struct pxps *pxp); +static void pxp_dithering_process(struct pxps *pxp); +static void pxp_wfe_a_process(struct pxps *pxp); +static void pxp_wfe_a_process_v3p(struct pxps *pxp); +static void pxp_wfe_a_configure(struct pxps *pxp); +static void pxp_wfe_a_configure_v3p(struct pxps *pxp); +static void pxp_wfe_b_process(struct pxps *pxp); +static void pxp_wfe_b_configure(struct pxps *pxp); +static void pxp_lut_status_set(struct pxps *pxp, unsigned int lut); +static void pxp_lut_status_set_v3p(struct pxps *pxp, unsigned int lut); +static void pxp_lut_status_clr(unsigned int lut); +static void pxp_lut_status_clr_v3p(unsigned int lut); +static void pxp_start2(struct pxps *pxp); +static void pxp_data_path_config_v3p(struct pxps *pxp); +static void pxp_soft_reset(struct pxps *pxp); +static void pxp_collision_detection_disable(struct pxps *pxp); +static void pxp_collision_detection_enable(struct pxps *pxp, + unsigned int width, + unsigned int height); +static void pxp_luts_activate(struct pxps *pxp, u64 lut_status); +static bool pxp_collision_status_report(struct pxps *pxp, struct pxp_collision_info *info); +static void pxp_histogram_status_report(struct pxps *pxp, u32 *hist_status); +static void pxp_histogram_enable(struct pxps *pxp, + unsigned int width, + unsigned int height); +static void pxp_histogram_disable(struct pxps *pxp); +static void pxp_lut_cleanup_multiple(struct pxps *pxp, u64 lut, bool set); +static void pxp_lut_cleanup_multiple_v3p(struct pxps *pxp, u64 lut, bool set); +static void pxp_luts_deactivate(struct pxps *pxp, u64 lut_status); +static void pxp_set_colorkey(struct pxps *pxp); + +enum { + DITHER0_LUT = 0x0, /* Select the LUT memory for access */ + DITHER0_ERR0 = 0x1, /* Select the ERR0 memory for access */ + DITHER0_ERR1 = 0x2, /* Select the ERR1 memory for access */ + DITHER1_LUT = 0x3, /* Select the LUT memory for access */ + DITHER2_LUT = 0x4, /* Select the LUT memory for access */ + ALU_A = 0x5, /* Select the ALU instr memory for access */ + ALU_B = 0x6, /* Select the ALU instr memory for access */ + WFE_A = 0x7, /* Select the WFE_A instr memory for access */ + WFE_B = 0x8, /* Select the WFE_B instr memory for access */ + RESERVED = 0x15, +}; + +enum pxp_devtype { + PXP_V3, + PXP_V3P, /* minor changes over V3, use WFE_B to replace WFE_A */ +}; + +#define pxp_is_v3(pxp) (pxp->devdata->version == 30) +#define pxp_is_v3p(pxp) (pxp->devdata->version == 31) + +struct pxp_devdata { + void (*pxp_wfe_a_configure)(struct pxps *pxp); + void (*pxp_wfe_a_process)(struct pxps *pxp); + void (*pxp_lut_status_set)(struct pxps *pxp, unsigned int lut); + void (*pxp_lut_status_clr)(unsigned int lut); + void (*pxp_dithering_configure)(struct pxps *pxp); + void (*pxp_lut_cleanup_multiple)(struct pxps *pxp, u64 lut, bool set); + void (*pxp_data_path_config)(struct pxps *pxp); + unsigned int version; +}; + +static const struct pxp_devdata pxp_devdata[] = { + [PXP_V3] = { + .pxp_wfe_a_configure = pxp_wfe_a_configure, + .pxp_wfe_a_process = pxp_wfe_a_process, + .pxp_lut_status_set = pxp_lut_status_set, + .pxp_lut_status_clr = pxp_lut_status_clr, + .pxp_lut_cleanup_multiple = pxp_lut_cleanup_multiple, + .pxp_dithering_configure = pxp_dithering_configure, + .pxp_data_path_config = NULL, + .version = 30, + }, + [PXP_V3P] = { + .pxp_wfe_a_configure = pxp_wfe_a_configure_v3p, + .pxp_wfe_a_process = pxp_wfe_a_process_v3p, + .pxp_lut_status_set = pxp_lut_status_set_v3p, + .pxp_lut_status_clr = pxp_lut_status_clr_v3p, + .pxp_lut_cleanup_multiple = pxp_lut_cleanup_multiple_v3p, + .pxp_dithering_configure = pxp_dithering_configure_v3p, + .pxp_data_path_config = pxp_data_path_config_v3p, + .version = 31, + }, +}; + +/* + * PXP common functions + */ +static void dump_pxp_reg(struct pxps *pxp) +{ + dev_dbg(pxp->dev, "PXP_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_CTRL)); + dev_dbg(pxp->dev, "PXP_STAT 0x%x", + __raw_readl(pxp->base + HW_PXP_STAT)); + dev_dbg(pxp->dev, "PXP_OUT_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_CTRL)); + dev_dbg(pxp->dev, "PXP_OUT_BUF 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_BUF)); + dev_dbg(pxp->dev, "PXP_OUT_BUF2 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_BUF2)); + dev_dbg(pxp->dev, "PXP_OUT_PITCH 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_PITCH)); + dev_dbg(pxp->dev, "PXP_OUT_LRC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_LRC)); + dev_dbg(pxp->dev, "PXP_OUT_PS_ULC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_PS_ULC)); + dev_dbg(pxp->dev, "PXP_OUT_PS_LRC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_PS_LRC)); + dev_dbg(pxp->dev, "PXP_OUT_AS_ULC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_AS_ULC)); + dev_dbg(pxp->dev, "PXP_OUT_AS_LRC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_AS_LRC)); + dev_dbg(pxp->dev, "PXP_PS_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_CTRL)); + dev_dbg(pxp->dev, "PXP_PS_BUF 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_BUF)); + dev_dbg(pxp->dev, "PXP_PS_UBUF 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_UBUF)); + dev_dbg(pxp->dev, "PXP_PS_VBUF 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_VBUF)); + dev_dbg(pxp->dev, "PXP_PS_PITCH 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_PITCH)); + dev_dbg(pxp->dev, "PXP_PS_BACKGROUND_0 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_BACKGROUND_0)); + dev_dbg(pxp->dev, "PXP_PS_SCALE 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_SCALE)); + dev_dbg(pxp->dev, "PXP_PS_OFFSET 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_OFFSET)); + dev_dbg(pxp->dev, "PXP_PS_CLRKEYLOW_0 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_CLRKEYLOW_0)); + dev_dbg(pxp->dev, "PXP_PS_CLRKEYHIGH 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_CLRKEYHIGH_0)); + dev_dbg(pxp->dev, "PXP_AS_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_CTRL)); + dev_dbg(pxp->dev, "PXP_AS_BUF 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_BUF)); + dev_dbg(pxp->dev, "PXP_AS_PITCH 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_PITCH)); + dev_dbg(pxp->dev, "PXP_AS_CLRKEYLOW 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_CLRKEYLOW_0)); + dev_dbg(pxp->dev, "PXP_AS_CLRKEYHIGH 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_CLRKEYHIGH_0)); + dev_dbg(pxp->dev, "PXP_CSC1_COEF0 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC1_COEF0)); + dev_dbg(pxp->dev, "PXP_CSC1_COEF1 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC1_COEF1)); + dev_dbg(pxp->dev, "PXP_CSC1_COEF2 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC1_COEF2)); + dev_dbg(pxp->dev, "PXP_CSC2_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_CTRL)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF0 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF0)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF1 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF1)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF2 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF2)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF3 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF3)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF4 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF4)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF5 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF5)); + dev_dbg(pxp->dev, "PXP_LUT_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_CTRL)); + dev_dbg(pxp->dev, "PXP_LUT_ADDR 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_ADDR)); + dev_dbg(pxp->dev, "PXP_LUT_DATA 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_DATA)); + dev_dbg(pxp->dev, "PXP_LUT_EXTMEM 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_EXTMEM)); + dev_dbg(pxp->dev, "PXP_CFA 0x%x", + __raw_readl(pxp->base + HW_PXP_CFA)); + dev_dbg(pxp->dev, "PXP_ALPHA_A_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_ALPHA_A_CTRL)); + dev_dbg(pxp->dev, "PXP_ALPHA_B_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_ALPHA_B_CTRL)); + dev_dbg(pxp->dev, "PXP_POWER_REG0 0x%x", + __raw_readl(pxp->base + HW_PXP_POWER_REG0)); + dev_dbg(pxp->dev, "PXP_NEXT 0x%x", + __raw_readl(pxp->base + HW_PXP_NEXT)); + dev_dbg(pxp->dev, "PXP_DEBUGCTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_DEBUGCTRL)); + dev_dbg(pxp->dev, "PXP_DEBUG 0x%x", + __raw_readl(pxp->base + HW_PXP_DEBUG)); + dev_dbg(pxp->dev, "PXP_VERSION 0x%x", + __raw_readl(pxp->base + HW_PXP_VERSION)); +} + +static void dump_pxp_reg2(struct pxps *pxp) +{ +#ifdef DEBUG + int i = 0; + + for (i=0; i< ((0x33C0/0x10) + 1);i++) { + printk("0x%08x: 0x%08x\n", 0x10*i, __raw_readl(pxp->base + 0x10*i)); + } +#endif +} + +static void print_param(struct pxp_layer_param *p, char *s) +{ + pr_debug("%s: t/l/w/h/s %d/%d/%d/%d/%d, addr %x\n", s, + p->top, p->left, p->width, p->height, p->stride, p->paddr); +} + +/* when it is, return yuv plane number */ +static uint8_t is_yuv(uint32_t format) +{ + switch (format) { + case PXP_PIX_FMT_GREY: + case PXP_PIX_FMT_GY04: + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_YVYU: + case PXP_PIX_FMT_VYUY: + case PXP_PIX_FMT_YUV444: + case PXP_PIX_FMT_YVU444: + case PXP_PIX_FMT_VUY444: + return 1; + case PXP_PIX_FMT_NV12: + case PXP_PIX_FMT_NV21: + case PXP_PIX_FMT_NV16: + case PXP_PIX_FMT_NV61: + return 2; + case PXP_PIX_FMT_YUV420P: + case PXP_PIX_FMT_YUV422P: + case PXP_PIX_FMT_YVU420P: + case PXP_PIX_FMT_YVU422P: + return 3; + default: + return 0; + } +} + +static u32 get_bpp_from_fmt(u32 pix_fmt) +{ + unsigned int bpp = 0; + + switch (pix_fmt) { + case PXP_PIX_FMT_GREY: + case PXP_PIX_FMT_NV16: + case PXP_PIX_FMT_NV61: + case PXP_PIX_FMT_NV12: + case PXP_PIX_FMT_NV21: + case PXP_PIX_FMT_YUV422P: + case PXP_PIX_FMT_YVU422P: + case PXP_PIX_FMT_YUV420P: + case PXP_PIX_FMT_YVU420P: + bpp = 8; + break; + case PXP_PIX_FMT_RGB555: + case PXP_PIX_FMT_ARGB555: + case PXP_PIX_FMT_XRGB555: + case PXP_PIX_FMT_RGBA555: + case PXP_PIX_FMT_ARGB444: + case PXP_PIX_FMT_XRGB444: + case PXP_PIX_FMT_RGBA444: + case PXP_PIX_FMT_RGB565: + case PXP_PIX_FMT_BGR565: + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_YVYU: + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_VYUY: + bpp = 16; + break; + case PXP_PIX_FMT_RGB24: + case PXP_PIX_FMT_BGR24: + bpp = 24; + break; + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_RGBX32: + case PXP_PIX_FMT_XBGR32: + case PXP_PIX_FMT_BGRX32: + case PXP_PIX_FMT_ARGB32: + case PXP_PIX_FMT_RGBA32: + case PXP_PIX_FMT_ABGR32: + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_YUV444: + case PXP_PIX_FMT_YVU444: + case PXP_PIX_FMT_VUY444: + bpp = 32; + break; + default: + pr_err("%s: pix_fmt unsupport yet: 0x%x\n", __func__, pix_fmt); + break; + } + + return bpp; +} + +static uint32_t pxp_parse_ps_fmt(uint32_t format) +{ + uint32_t fmt_ctrl; + + switch (format) { + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_ARGB32: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB888; + break; + case PXP_PIX_FMT_RGB565: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB565; + break; + case PXP_PIX_FMT_RGB555: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB555; + break; + case PXP_PIX_FMT_YUV420P: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV420; + break; + case PXP_PIX_FMT_YVU420P: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV420; + break; + case PXP_PIX_FMT_GREY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y8; + break; + case PXP_PIX_FMT_GY04: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y4; + break; + case PXP_PIX_FMT_VUY444: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV1P444; + break; + case PXP_PIX_FMT_YUV422P: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV422; + break; + case PXP_PIX_FMT_UYVY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422; + break; + case PXP_PIX_FMT_YUYV: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422; + break; + case PXP_PIX_FMT_VYUY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__VYUY1P422; + break; + case PXP_PIX_FMT_YVYU: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__VYUY1P422; + break; + case PXP_PIX_FMT_NV12: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV2P420; + break; + case PXP_PIX_FMT_NV21: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YVU2P420; + break; + case PXP_PIX_FMT_NV16: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV2P422; + break; + case PXP_PIX_FMT_NV61: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YVU2P422; + break; + case PXP_PIX_FMT_RGBA32: + case PXP_PIX_FMT_RGBX32: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGBA888; + break; + default: + pr_debug("PS doesn't support this format\n"); + fmt_ctrl = 0; + } + + return fmt_ctrl; +} + +static void pxp_set_colorkey(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + struct pxp_layer_param *ol_params = &pxp_conf->ol_param[0]; + + /* Low and high are set equal. V4L does not allow a chromakey range */ + if (s0_params->color_key_enable == 0 || s0_params->color_key == -1) { + /* disable color key */ + pxp_writel(0xFFFFFF, HW_PXP_PS_CLRKEYLOW_0); + pxp_writel(0, HW_PXP_PS_CLRKEYHIGH_0); + } else { + pxp_writel(s0_params->color_key, HW_PXP_PS_CLRKEYLOW_0); + pxp_writel(s0_params->color_key, HW_PXP_PS_CLRKEYHIGH_0); + } + + if (ol_params->color_key_enable != 0 && ol_params->color_key != -1) { + pxp_writel(ol_params->color_key, HW_PXP_AS_CLRKEYLOW_0); + pxp_writel(ol_params->color_key, HW_PXP_AS_CLRKEYHIGH_0); + } else { + /* disable color key */ + pxp_writel(0xFFFFFF, HW_PXP_AS_CLRKEYLOW_0); + pxp_writel(0, HW_PXP_AS_CLRKEYHIGH_0); + } +} + +static uint32_t pxp_parse_as_fmt(uint32_t format) +{ + uint32_t fmt_ctrl; + + switch (format) { + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_ARGB32: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__ARGB8888; + break; + case PXP_PIX_FMT_RGBA32: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGBA8888; + break; + case PXP_PIX_FMT_XRGB32: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGB888; + break; + case PXP_PIX_FMT_ARGB555: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__ARGB1555; + break; + case PXP_PIX_FMT_ARGB444: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__ARGB4444; + break; + case PXP_PIX_FMT_RGBA555: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGBA5551; + break; + case PXP_PIX_FMT_RGBA444: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGBA4444; + break; + case PXP_PIX_FMT_RGB555: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGB555; + break; + case PXP_PIX_FMT_RGB444: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGB444; + break; + case PXP_PIX_FMT_RGB565: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGB565; + break; + default: + pr_debug("AS doesn't support this format\n"); + fmt_ctrl = 0xf; + break; + } + + return fmt_ctrl; +} + +static uint32_t pxp_parse_out_fmt(uint32_t format) +{ + uint32_t fmt_ctrl; + + switch (format) { + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_ARGB32: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__ARGB8888; + break; + case PXP_PIX_FMT_XRGB32: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888; + break; + case PXP_PIX_FMT_RGB24: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888P; + break; + case PXP_PIX_FMT_RGB565: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB565; + break; + case PXP_PIX_FMT_RGB555: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB555; + break; + case PXP_PIX_FMT_GREY: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y8; + break; + case PXP_PIX_FMT_GY04: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y4; + break; + case PXP_PIX_FMT_UYVY: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__UYVY1P422; + break; + case PXP_PIX_FMT_VYUY: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__VYUY1P422; + break; + case PXP_PIX_FMT_NV12: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P420; + break; + case PXP_PIX_FMT_NV21: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YVU2P420; + break; + case PXP_PIX_FMT_NV16: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P422; + break; + case PXP_PIX_FMT_NV61: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YVU2P422; + break; + default: + pr_debug("OUT doesn't support this format\n"); + fmt_ctrl = 0; + } + + return fmt_ctrl; +} + +static void set_mux(struct mux_config *path_ctrl) +{ + struct mux_config *mux = path_ctrl; + + *(uint32_t *)path_ctrl = 0xFFFFFFFF; + + mux->mux0_sel = 0; + mux->mux3_sel = 1; + mux->mux6_sel = 1; + mux->mux8_sel = 0; + mux->mux9_sel = 1; + mux->mux11_sel = 0; + mux->mux12_sel = 1; + mux->mux14_sel = 0; +} + +static void set_mux_val(struct mux_config *muxes, + uint32_t mux_id, + uint32_t mux_val) +{ + BUG_ON(!muxes); + BUG_ON(mux_id > 15); + + switch (mux_id) { + case 0: + muxes->mux0_sel = mux_val; + break; + case 1: + muxes->mux1_sel = mux_val; + break; + case 2: + muxes->mux2_sel = mux_val; + break; + case 3: + muxes->mux3_sel = mux_val; + break; + case 4: + muxes->mux4_sel = mux_val; + break; + case 5: + muxes->mux5_sel = mux_val; + break; + case 6: + muxes->mux6_sel = mux_val; + break; + case 7: + muxes->mux7_sel = mux_val; + break; + case 8: + muxes->mux8_sel = mux_val; + break; + case 9: + muxes->mux9_sel = mux_val; + break; + case 10: + muxes->mux10_sel = mux_val; + break; + case 11: + muxes->mux11_sel = mux_val; + break; + case 12: + muxes->mux12_sel = mux_val; + break; + case 13: + muxes->mux13_sel = mux_val; + break; + case 14: + muxes->mux14_sel = mux_val; + break; + case 15: + muxes->mux15_sel = mux_val; + break; + default: + break; + } +} + +static uint32_t get_mux_val(struct mux_config *muxes, + uint32_t mux_id) +{ + BUG_ON(!muxes); + BUG_ON(mux_id > 15); + + switch (mux_id) { + case 0: + return muxes->mux0_sel; + case 1: + return muxes->mux1_sel; + case 2: + return muxes->mux2_sel; + case 3: + return muxes->mux3_sel; + case 4: + return muxes->mux4_sel; + case 5: + return muxes->mux5_sel; + case 6: + return muxes->mux6_sel; + case 7: + return muxes->mux7_sel; + case 8: + return muxes->mux8_sel; + case 9: + return muxes->mux9_sel; + case 10: + return muxes->mux10_sel; + case 11: + return muxes->mux11_sel; + case 12: + return muxes->mux12_sel; + case 13: + return muxes->mux13_sel; + case 14: + return muxes->mux14_sel; + case 15: + return muxes->mux15_sel; + default: + return -EINVAL; + } +} + +static uint32_t pxp_store_ctrl_config(struct pxp_pixmap *out, uint8_t mode, + uint8_t fill_en, uint8_t combine_2ch) +{ + struct store_ctrl ctrl; + uint8_t output_active_bpp; + + memset((void*)&ctrl, 0x0, sizeof(ctrl)); + + if (combine_2ch) { + ctrl.combine_2channel = 1; + if (out) { + output_active_bpp = active_bpp(out->bpp); + ctrl.pack_in_sel = (output_active_bpp < 0x3) ? 1 : 0; + ctrl.store_memory_en = 1; + } + } else { + if (fill_en) { + ctrl.fill_data_en = 1; + ctrl.wr_num_bytes = 2; + } + ctrl.store_memory_en = 1; + } + + if (out->rotate || out->flip) + ctrl.block_en = 1; + + ctrl.ch_en = 1; + + return *(uint32_t *)&ctrl; +} + +static uint32_t pxp_store_size_config(struct pxp_pixmap *out) +{ + struct store_size size; + + memset((void*)&size, 0x0, sizeof(size)); + + size.out_height = out->height - 1; + size.out_width = out->width - 1; + + return *(uint32_t *)&size; +} + +static uint32_t pxp_store_pitch_config(struct pxp_pixmap *out0, + struct pxp_pixmap *out1) +{ + struct store_pitch pitch; + + memset((void*)&pitch, 0x0, sizeof(pitch)); + + pitch.ch0_out_pitch = out0->pitch; + pitch.ch1_out_pitch = out1 ? out1->pitch : 0; + + return *(uint32_t *)&pitch; +} + +static struct color *pxp_find_rgb_color(uint32_t format) +{ + int i; + + for (i = 0; i < sizeof(rgb_colors) / sizeof(struct color); i++) { + if (rgb_colors[i].format == format) + return &rgb_colors[i]; + } + + return NULL; +} + +static struct color_component *pxp_find_comp(struct color *color, uint8_t id) +{ + int i; + + for (i = 0; i < 4; i++) { + if (id == color->comp[i].id) + return &color->comp[i]; + } + + return NULL; +} + +static struct color *pxp_find_yuv_color(uint32_t format) +{ + int i; + + for (i = 0; i < sizeof(yuv_colors) / sizeof(struct color); i++) { + if (yuv_colors[i].format == format) + return &yuv_colors[i]; + } + + return NULL; +} + +static uint64_t pxp_store_d_shift_calc(uint32_t in_fmt, uint32_t out_fmt, + struct store_d_mask *d_mask) +{ + int i, shift_width, shift_flag, drop = 0; + struct store_d_shift d_shift; + struct color *input_color, *output_color; + struct color_component *input_comp, *output_comp; + + BUG_ON((in_fmt == out_fmt)); + memset((void*)&d_shift, 0x0, sizeof(d_shift)); + memset((void*)d_mask, 0x0, sizeof(*d_mask) * 8); + + if (!is_yuv(in_fmt)) { + input_color = pxp_find_rgb_color(in_fmt); + output_color = pxp_find_rgb_color(out_fmt); + } else { + input_color = pxp_find_yuv_color(in_fmt); + output_color = pxp_find_yuv_color(out_fmt); + } + + for (i = 0; i < 4; i++) { + input_comp = &input_color->comp[i]; + if (!input_comp->length) + continue; + + output_comp = pxp_find_comp(output_color, input_comp->id); + if (!output_comp->length) + continue; + + /* only rgb format can drop color bits */ + if (input_comp->length > output_comp->length) { + drop = input_comp->length - output_comp->length; + input_comp->offset += drop; + } + d_mask[i].d_mask_l = output_comp->mask << input_comp->offset; + + shift_width = input_comp->offset - output_comp->offset; + if (shift_width > 0) + shift_flag = 0; /* right shift */ + else if (shift_width < 0) { + shift_flag = 1; /* left shift */ + shift_width = -shift_width; + } else + shift_width = shift_flag = 0; /* no shift require */ + + switch (i) { + case 0: + d_shift.d_shift_width0 = shift_width; + d_shift.d_shift_flag0 = shift_flag; + break; + case 1: + d_shift.d_shift_width1 = shift_width; + d_shift.d_shift_flag1 = shift_flag; + break; + case 2: + d_shift.d_shift_width2 = shift_width; + d_shift.d_shift_flag2 = shift_flag; + break; + case 3: + d_shift.d_shift_width3 = shift_width; + d_shift.d_shift_flag3 = shift_flag; + break; + default: + printk(KERN_ERR "unsupport d shift\n"); + break; + } + + input_comp->offset -= drop; + } + + return *(uint64_t *)&d_shift; +} + +static uint32_t pxp_store_shift_ctrl_config(struct pxp_pixmap *out, + uint8_t shift_bypass) +{ + struct store_shift_ctrl shift_ctrl; + + memset((void*)&shift_ctrl, 0x0, sizeof(shift_ctrl)); + + shift_ctrl.output_active_bpp = active_bpp(out->bpp); + /* Not general data */ + if (!shift_bypass) { + switch(out->format) { + case PXP_PIX_FMT_YUYV: + shift_bypass = 1; + /* fall through */ + case PXP_PIX_FMT_YVYU: + shift_ctrl.out_yuv422_1p_en = 1; + break; + case PXP_PIX_FMT_NV16: + shift_bypass = 1; + /* fall through */ + case PXP_PIX_FMT_NV61: + shift_ctrl.out_yuv422_2p_en = 1; + break; + default: + break; + } + } + shift_ctrl.shift_bypass = shift_bypass; + + return *(uint32_t *)&shift_ctrl; +} + +static uint32_t pxp_fetch_ctrl_config(struct pxp_pixmap *in, + uint8_t mode) +{ + struct fetch_ctrl ctrl; + + memset((void*)&ctrl, 0x0, sizeof(ctrl)); + + if (mode == FETCH_MODE_NORMAL) + ctrl.bypass_pixel_en = 0; + + if (in->flip == PXP_H_FLIP) + ctrl.hflip = 1; + else if (in->flip == PXP_V_FLIP) + ctrl.vflip = 1; + + ctrl.rotation_angle = rotate_map(in->rotate); + + if (in->rotate || in->flip) + ctrl.block_en = 1; + + ctrl.ch_en = 1; + + return *(uint32_t *)&ctrl; +} + +static uint32_t pxp_fetch_active_size_ulc(struct pxp_pixmap *in) +{ + struct fetch_active_size_ulc size_ulc; + + memset((void*)&size_ulc, 0x0, sizeof(size_ulc)); + + size_ulc.active_size_ulc_x = 0; + size_ulc.active_size_ulc_y = 0; + + return *(uint32_t *)&size_ulc; +} + +static uint32_t pxp_fetch_active_size_lrc(struct pxp_pixmap *in) +{ + struct fetch_active_size_lrc size_lrc; + + memset((void*)&size_lrc, 0x0, sizeof(size_lrc)); + + size_lrc.active_size_lrc_x = in->crop.width - 1; + size_lrc.active_size_lrc_y = in->crop.height - 1; + + return *(uint32_t *)&size_lrc; +} + +static uint32_t pxp_fetch_pitch_config(struct pxp_pixmap *in0, + struct pxp_pixmap *in1) +{ + struct fetch_pitch pitch; + + memset((void*)&pitch, 0x0, sizeof(pitch)); + + if (in0) + pitch.ch0_input_pitch = in0->pitch; + if (in1) + pitch.ch1_input_pitch = in1->pitch; + + return *(uint32_t *)&pitch; +} + +static uint32_t pxp_fetch_shift_ctrl_config(struct pxp_pixmap *in, + uint8_t shift_bypass, + uint8_t need_expand) +{ + uint8_t input_expand_format; + struct fetch_shift_ctrl shift_ctrl; + + memset((void*)&shift_ctrl, 0x0, sizeof(shift_ctrl)); + + shift_ctrl.input_active_bpp = active_bpp(in->bpp); + shift_ctrl.shift_bypass = shift_bypass; + + if (in->bpp == 32) + need_expand = 0; + + if (need_expand) { + input_expand_format = expand_format(in->format); + + if (input_expand_format <= 0x7) { + shift_ctrl.expand_en = 1; + shift_ctrl.expand_format = input_expand_format; + } + } + + return *(uint32_t *)&shift_ctrl; +} + +static uint32_t pxp_fetch_shift_calc(uint32_t in_fmt, uint32_t out_fmt, + struct fetch_shift_width *shift_width) +{ + int i; + struct fetch_shift_offset shift_offset; + struct color *input_color, *output_color; + struct color_component *input_comp, *output_comp; + + memset((void*)&shift_offset, 0x0, sizeof(shift_offset)); + memset((void*)shift_width, 0x0, sizeof(*shift_width)); + + if (!is_yuv(in_fmt)) { + input_color = pxp_find_rgb_color(in_fmt); + output_color = pxp_find_rgb_color(out_fmt); + } else { + input_color = pxp_find_yuv_color(in_fmt); + output_color = pxp_find_yuv_color(out_fmt); + } + + for(i = 0; i < 4; i++) { + output_comp = &output_color->comp[i]; + if (!output_comp->length) + continue; + + input_comp = pxp_find_comp(input_color, output_comp->id); + switch (i) { + case 0: + shift_offset.offset0 = input_comp->offset; + shift_width->width0 = input_comp->length; + break; + case 1: + shift_offset.offset1 = input_comp->offset; + shift_width->width1 = input_comp->length; + break; + case 2: + shift_offset.offset2 = input_comp->offset; + shift_width->width2 = input_comp->length; + break; + case 3: + shift_offset.offset3 = input_comp->offset; + shift_width->width3 = input_comp->length; + break; + } + } + + return *(uint32_t *)&shift_offset; +} + +static int pxp_start(struct pxps *pxp) +{ + __raw_writel(BM_PXP_CTRL_ENABLE_ROTATE1 | BM_PXP_CTRL_ENABLE | + BM_PXP_CTRL_ENABLE_CSC2 | BM_PXP_CTRL_ENABLE_LUT | + BM_PXP_CTRL_ENABLE_PS_AS_OUT | BM_PXP_CTRL_ENABLE_ROTATE0, + pxp->base + HW_PXP_CTRL_SET); + dump_pxp_reg(pxp); + + return 0; +} + +static bool fmt_ps_support(uint32_t format) +{ + switch (format) { + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_ARGB32: + case PXP_PIX_FMT_RGB555: + case PXP_PIX_FMT_XRGB555: + case PXP_PIX_FMT_ARGB555: + case PXP_PIX_FMT_RGB444: + case PXP_PIX_FMT_XRGB444: + case PXP_PIX_FMT_ARGB444: + case PXP_PIX_FMT_RGB565: + case PXP_PIX_FMT_YUV444: + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_VUY444: + /* need word byte swap */ + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_VYUY: + /* need word byte swap */ + case PXP_PIX_FMT_YVYU: + case PXP_PIX_FMT_GREY: + case PXP_PIX_FMT_GY04: + case PXP_PIX_FMT_NV16: + case PXP_PIX_FMT_NV12: + case PXP_PIX_FMT_NV61: + case PXP_PIX_FMT_NV21: + case PXP_PIX_FMT_YUV422P: + case PXP_PIX_FMT_YUV420P: + case PXP_PIX_FMT_YVU420P: + case PXP_PIX_FMT_RGBA32: + case PXP_PIX_FMT_RGBX32: + case PXP_PIX_FMT_RGBA555: + case PXP_PIX_FMT_RGBA444: + return true; + default: + return false; + } +} + +static bool fmt_as_support(uint32_t format) +{ + switch (format) { + case PXP_PIX_FMT_ARGB32: + case PXP_PIX_FMT_RGBA32: + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_ARGB555: + case PXP_PIX_FMT_ARGB444: + case PXP_PIX_FMT_RGBA555: + case PXP_PIX_FMT_RGBA444: + case PXP_PIX_FMT_RGB555: + case PXP_PIX_FMT_RGB444: + case PXP_PIX_FMT_RGB565: + return true; + default: + return false; + } +} + +static bool fmt_out_support(uint32_t format) +{ + switch (format) { + case PXP_PIX_FMT_ARGB32: + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_RGB24: + case PXP_PIX_FMT_ARGB555: + case PXP_PIX_FMT_ARGB444: + case PXP_PIX_FMT_RGB555: + case PXP_PIX_FMT_RGB444: + case PXP_PIX_FMT_RGB565: + case PXP_PIX_FMT_YUV444: + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_VYUY: + case PXP_PIX_FMT_GREY: + case PXP_PIX_FMT_GY04: + case PXP_PIX_FMT_NV16: + case PXP_PIX_FMT_NV12: + case PXP_PIX_FMT_NV61: + case PXP_PIX_FMT_NV21: + return true; + default: + return false; + } +} + +/* common means 'ARGB32/XRGB32/YUV444' */ +static uint8_t fmt_fetch_to_common(uint32_t in) +{ + switch (in) { + case PXP_PIX_FMT_ARGB32: + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_YUV444: + return FETCH_NOOP; + + case PXP_PIX_FMT_RGB565: + case PXP_PIX_FMT_RGB555: + case PXP_PIX_FMT_ARGB555: + case PXP_PIX_FMT_RGB444: + case PXP_PIX_FMT_ARGB444: + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_NV16: + return FETCH_EXPAND; + + case PXP_PIX_FMT_RGBA32: + case PXP_PIX_FMT_RGBX32: + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_BGRX32: + case PXP_PIX_FMT_ABGR32: + case PXP_PIX_FMT_XBGR32: + case PXP_PIX_FMT_YVU444: + return FETCH_SHIFT; + + case PXP_PIX_FMT_BGR565: + case PXP_PIX_FMT_YVYU: + case PXP_PIX_FMT_VYUY: + return FETCH_EXPAND | FETCH_SHIFT; + + default: + return 0; + } +} + +static uint8_t fmt_store_from_common(uint32_t out) +{ + switch (out) { + case PXP_PIX_FMT_ARGB32: + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_YUV444: + return STORE_NOOP; + + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_NV16: + return STORE_SHRINK; + + case PXP_PIX_FMT_RGBA32: + case PXP_PIX_FMT_RGBX32: + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_BGRX32: + case PXP_PIX_FMT_ABGR32: + case PXP_PIX_FMT_XBGR32: + case PXP_PIX_FMT_YVU444: + case PXP_PIX_FMT_RGB565: + case PXP_PIX_FMT_RGB555: + case PXP_PIX_FMT_ARGB555: + case PXP_PIX_FMT_RGB444: + case PXP_PIX_FMT_ARGB444: + case PXP_PIX_FMT_GREY: + return STORE_SHIFT; + + case PXP_PIX_FMT_YVYU: + case PXP_PIX_FMT_NV61: + return STORE_SHIFT | STORE_SHRINK; + + default: + return 0; + } +} + +static void filter_possible_inputs(struct pxp_pixmap *input, + uint32_t *possible) +{ + uint8_t clear = 0xff; + uint8_t position = 0; + + do { + position = find_next_bit((unsigned long *)possible, 32, position); + if (position >= sizeof(uint32_t) * 8) + break; + + switch (position) { + case PXP_2D_PS: + if (!fmt_ps_support(input->format)) + clear = PXP_2D_PS; + break; + case PXP_2D_AS: + if (!fmt_as_support(input->format)) + clear = PXP_2D_AS; + break; + case PXP_2D_INPUT_FETCH0: + case PXP_2D_INPUT_FETCH1: + if ((is_yuv(input->format) == 3)) { + clear = position; + break; + } + if ((input->flags & IN_NEED_FMT_UNIFIED) || + is_yuv(input->format) == 2) + if (!fmt_fetch_to_common(input->format)) + clear = position; + break; + default: + pr_err("invalid input node: %d\n", position); + clear = position; + break; + } + + if (clear != 0xff) { + clear_bit(clear, (unsigned long*)possible); + clear = 0xff; + } + + position++; + } while (1); +} + +static void filter_possible_outputs(struct pxp_pixmap *output, + uint32_t *possible) +{ + uint8_t clear = 0xff; + uint8_t position = 0; + + do { + position = find_next_bit((unsigned long *)possible, 32, position); + if (position >= sizeof(uint32_t) * 8) + break; + + switch (position) { + case PXP_2D_OUT: + if (!fmt_out_support(output->format)) + clear = PXP_2D_OUT; + break; + case PXP_2D_INPUT_STORE0: + case PXP_2D_INPUT_STORE1: + if (output->flags) { + if (!fmt_store_from_common(output->format)) + clear = position; + } + break; + default: + pr_err("invalid output node: %d\n", position); + clear = position; + break; + } + + if (clear != 0xff) { + clear_bit(clear, (unsigned long*)possible); + clear = 0xff; + } + + position++; + } while (1); +} + +static uint32_t calc_shortest_path(uint32_t *nodes_used) +{ + uint32_t distance = 0; + uint32_t from = 0, to = 0, bypass, end; + + do { + from = find_next_bit((unsigned long *)nodes_used, 32, from); + if (from >= sizeof(uint32_t) * 8) + break; + + if (to != 0) { + if (path_table[to][from].distance == DISTANCE_INFINITY) + return DISTANCE_INFINITY; + + distance += path_table[to][from].distance; + /* backtrace */ + end = from; + while (1) { + bypass = path_table[to][end].prev_node; + if (bypass == to) + break; + set_bit(bypass, (unsigned long*)nodes_used); + end = bypass; + } + } + + to = find_next_bit((unsigned long *)nodes_used, 32, from + 1); + if (to >= sizeof(uint32_t) * 8) + break; + + if (path_table[from][to].distance == DISTANCE_INFINITY) + return DISTANCE_INFINITY; + + distance += path_table[from][to].distance; + /* backtrace */ + end = to; + while (1) { + bypass = path_table[from][end].prev_node; + if (bypass == from) + break; + set_bit(bypass, (unsigned long*)nodes_used); + end = bypass; + } + + from = to + 1; + } while (1); + + return distance; +} + +static uint32_t find_best_path(uint32_t inputs, + uint32_t outputs, + struct pxp_pixmap *in, + uint32_t *nodes_used) +{ + uint32_t outs; + uint32_t nodes_add, best_nodes_used = 0; + uint8_t in_pos = 0, out_pos = 0; + uint32_t nodes_in_path, best_nodes_in_path = 0; + uint32_t best_distance = DISTANCE_INFINITY, distance; + + do { + outs = outputs; + in_pos = find_next_bit((unsigned long *)&inputs, 32, in_pos); + if (in_pos >= sizeof(uint32_t) * 8) + break; + nodes_add = 0; + set_bit(in_pos, (unsigned long *)&nodes_add); + + switch (in_pos) { + case PXP_2D_PS: + if ((in->flags & IN_NEED_CSC) == IN_NEED_CSC) { + if (is_yuv(in->format)) + set_bit(PXP_2D_CSC1, + (unsigned long *)&nodes_add); + else + set_bit(PXP_2D_CSC2, + (unsigned long *)&nodes_add); + } + if ((in->flags & IN_NEED_ROTATE_FLIP) == IN_NEED_ROTATE_FLIP) + set_bit(PXP_2D_ROTATION1, + (unsigned long *)&nodes_add); + clear_bit(PXP_2D_INPUT_STORE0, (unsigned long *)&outs); + break; + case PXP_2D_AS: + if ((in->flags & IN_NEED_CSC) == IN_NEED_CSC) + set_bit(PXP_2D_CSC2, + (unsigned long *)&nodes_add); + if ((in->flags & IN_NEED_ROTATE_FLIP) == IN_NEED_ROTATE_FLIP) + set_bit(PXP_2D_ROTATION0, + (unsigned long *)&nodes_add); + clear_bit(PXP_2D_INPUT_STORE0, (unsigned long *)&outs); + break; + case PXP_2D_INPUT_FETCH0: + case PXP_2D_INPUT_FETCH1: + if ((in->flags & IN_NEED_CSC) == IN_NEED_CSC) + set_bit(PXP_2D_CSC2, + (unsigned long *)&nodes_add); + clear_bit(PXP_2D_OUT, (unsigned long *)&outs); + if ((in->flags & IN_NEED_ROTATE_FLIP) == IN_NEED_ROTATE_FLIP) + set_bit(PXP_2D_ROTATION1, + (unsigned long *)&nodes_add); + break; + default: + /* alph0_s0/s1, alpha1_s0/s1 */ + break; + } + + nodes_add |= *nodes_used; + + do { + out_pos = find_next_bit((unsigned long *)&outs, 32, out_pos); + if (out_pos >= sizeof(uint32_t) * 8) + break; + set_bit(out_pos, (unsigned long *)&nodes_add); + + switch(out_pos) { + case PXP_2D_ALPHA0_S0: + case PXP_2D_ALPHA0_S1: + case PXP_2D_ALPHA1_S0: + case PXP_2D_ALPHA1_S1: + clear_bit(PXP_2D_CSC2, (unsigned long *)&nodes_add); + clear_bit(PXP_2D_ROTATION0, (unsigned long *)&nodes_add); + clear_bit(PXP_2D_LUT, (unsigned long *)&nodes_add); + break; + default: + break; + } + + nodes_in_path = nodes_add; + distance = calc_shortest_path(&nodes_in_path); + if (best_distance > distance) { + best_distance = distance; + best_nodes_used = nodes_add; + best_nodes_in_path = nodes_in_path; + } + pr_debug("%s: out_pos = %d, nodes_in_path = 0x%x, nodes_add = 0x%x, distance = 0x%x\n", + __func__, out_pos, nodes_in_path, nodes_add, distance); + + clear_bit(out_pos, (unsigned long *)&nodes_add); + + out_pos++; + } while (1); + + in_pos++; + } while (1); + + *nodes_used = best_nodes_used; + + return best_nodes_in_path; +} + +static uint32_t ps_calc_scaling(struct pxp_pixmap *input, + struct pxp_pixmap *output, + struct ps_ctrl *ctrl) +{ + struct ps_scale scale; + uint32_t decx, decy; + + memset((void*)&scale, 0x0, sizeof(scale)); + + if (!output->crop.width || !output->crop.height) { + pr_err("Invalid drect width and height passed in\n"); + return 0; + } + + if ((input->rotate == 90) || (input->rotate == 270)) + swap(output->crop.width, output->crop.height); + + decx = input->crop.width / output->crop.width; + decy = input->crop.height / output->crop.height; + + if (decx > 1) { + if (decx >= 2 && decx < 4) { + decx = 2; + ctrl->decx = 1; + } else if (decx >= 4 && decx < 8) { + decx = 4; + ctrl->decx = 2; + } else if (decx >= 8) { + decx = 8; + ctrl->decx = 3; + } + scale.xscale = input->crop.width * 0x1000 / + (output->crop.width * decx); + + /* A factor greater than 2 is not supported + * with the bilinear filter, so correct it in + * driver + */ + if (((scale.xscale >> BP_PXP_PS_SCALE_OFFSET) & 0x3) > 2) { + scale.xscale &= (~(0x3 << BP_PXP_PS_SCALE_OFFSET)); + scale.xscale |= (0x2 << BP_PXP_PS_SCALE_OFFSET); + pr_warn("%s: scale.xscale is larger than 2, forcing to 2" + "input w/h=(%d,%d), output w/h=(%d, %d)\n", + __func__, input->crop.width, input->crop.height, + output->crop.width, output->crop.height); + } + } else { + if (!is_yuv(input->format) || + (is_yuv(input->format) == is_yuv(output->format)) || + (input->format == PXP_PIX_FMT_GREY) || + (input->format == PXP_PIX_FMT_GY04) || + (input->format == PXP_PIX_FMT_VUY444)) { + if ((input->crop.width > 1) && + (output->crop.width > 1)) + scale.xscale = (input->crop.width - 1) * 0x1000 / + (output->crop.width - 1); + else + scale.xscale = input->crop.width * 0x1000 / + output->crop.width; + } else { + if ((input->crop.width > 2) && + (output->crop.width > 1)) + scale.xscale = (input->crop.width - 2) * 0x1000 / + (output->crop.width - 1); + else + scale.xscale = input->crop.width * 0x1000 / + output->crop.width; + } + } + + if (decy > 1) { + if (decy >= 2 && decy < 4) { + decy = 2; + ctrl->decy = 1; + } else if (decy >= 4 && decy < 8) { + decy = 4; + ctrl->decy = 2; + } else if (decy >= 8) { + decy = 8; + ctrl->decy = 3; + } + scale.yscale = input->crop.height * 0x1000 / + (output->crop.height * decy); + + /* A factor greater than 2 is not supported + * with the bilinear filter, so correct it in + * driver + */ + if (((scale.yscale >> BP_PXP_PS_SCALE_OFFSET) & 0x3) > 2) { + scale.yscale &= (~(0x3 << BP_PXP_PS_SCALE_OFFSET)); + scale.yscale |= (0x2 << BP_PXP_PS_SCALE_OFFSET); + pr_warn("%s: scale.yscale is larger than 2, forcing to 2" + "input w/h=(%d,%d), output w/h=(%d, %d)\n", + __func__, input->crop.width, input->crop.height, + output->crop.width, output->crop.height); + } + } else { + if ((input->crop.height > 1) && (output->crop.height > 1)) + scale.yscale = (input->crop.height - 1) * 0x1000 / + (output->crop.height - 1); + else + scale.yscale = input->crop.height * 0x1000 / + output->crop.height; + } + + return *(uint32_t *)&scale; +} + +static int pxp_ps_config(struct pxp_pixmap *input, + struct pxp_pixmap *output) +{ + uint32_t offset, U, V; + struct ps_ctrl ctrl; + struct coordinate out_ps_ulc, out_ps_lrc; + + memset((void*)&ctrl, 0x0, sizeof(ctrl)); + + ctrl.format = pxp_parse_ps_fmt(input->format); + + switch (output->rotate) { + case 0: + out_ps_ulc.x = output->crop.x; + out_ps_ulc.y = output->crop.y; + out_ps_lrc.x = out_ps_ulc.x + output->crop.width - 1; + out_ps_lrc.y = out_ps_ulc.y + output->crop.height - 1; + break; + case 90: + out_ps_ulc.x = output->crop.y; + out_ps_ulc.y = output->width - (output->crop.x + output->crop.width); + out_ps_lrc.x = out_ps_ulc.x + output->crop.height - 1; + out_ps_lrc.y = out_ps_ulc.y + output->crop.width - 1; + break; + case 180: + out_ps_ulc.x = output->width - (output->crop.x + output->crop.width); + out_ps_ulc.y = output->height - (output->crop.y + output->crop.height); + out_ps_lrc.x = out_ps_ulc.x + output->crop.width - 1; + out_ps_lrc.y = out_ps_ulc.y + output->crop.height - 1; + break; + case 270: + out_ps_ulc.x = output->height - (output->crop.y + output->crop.height); + out_ps_ulc.y = output->crop.x; + out_ps_lrc.x = out_ps_ulc.x + output->crop.height - 1; + out_ps_lrc.y = out_ps_ulc.y + output->crop.width - 1; + break; + default: + pr_err("PxP only support rotate 0 90 180 270\n"); + return -EINVAL; + break; + } + + if ((input->format == PXP_PIX_FMT_YUYV) || + (input->format == PXP_PIX_FMT_YVYU)) + ctrl.wb_swap = 1; + + pxp_writel(ps_calc_scaling(input, output, &ctrl), + HW_PXP_PS_SCALE); + pxp_writel(*(uint32_t *)&ctrl, HW_PXP_PS_CTRL); + + offset = input->crop.y * input->pitch + + input->crop.x * (input->bpp >> 3); + + pxp_writel(input->paddr + offset, HW_PXP_PS_BUF); + + switch (is_yuv(input->format)) { + case 0: /* RGB */ + case 1: /* 1 Plane YUV */ + break; + case 2: /* NV16,NV61,NV12,NV21 */ + if ((input->format == PXP_PIX_FMT_NV16) || + (input->format == PXP_PIX_FMT_NV61)) { + U = input->paddr + input->width * input->height; + pxp_writel(U + offset, HW_PXP_PS_UBUF); + } + else { + U = input->paddr + input->width * input->height; + pxp_writel(U + (offset >> 1), HW_PXP_PS_UBUF); + } + break; + case 3: /* YUV422P, YUV420P */ + if (input->format == PXP_PIX_FMT_YUV422P) { + U = input->paddr + input->width * input->height; + pxp_writel(U + (offset >> 1), HW_PXP_PS_UBUF); + V = U + (input->width * input->height >> 1); + pxp_writel(V + (offset >> 1), HW_PXP_PS_VBUF); + } else if (input->format == PXP_PIX_FMT_YUV420P) { + U = input->paddr + input->width * input->height; + pxp_writel(U + (offset >> 2), HW_PXP_PS_UBUF); + V = U + (input->width * input->height >> 2); + pxp_writel(V + (offset >> 2), HW_PXP_PS_VBUF); + } else if (input->format == PXP_PIX_FMT_YVU420P) { + U = input->paddr + input->width * input->height; + V = U + (input->width * input->height >> 2); + pxp_writel(U + (offset >> 2), HW_PXP_PS_VBUF); + pxp_writel(V + (offset >> 2), HW_PXP_PS_UBUF); + } + + break; + default: + break; + } + + pxp_writel(input->pitch, HW_PXP_PS_PITCH); + pxp_writel(*(uint32_t *)&out_ps_ulc, HW_PXP_OUT_PS_ULC); + pxp_writel(*(uint32_t *)&out_ps_lrc, HW_PXP_OUT_PS_LRC); + + pxp_writel(BF_PXP_CTRL_ENABLE_PS_AS_OUT(1) | + BF_PXP_CTRL_IRQ_ENABLE(1), + HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_as_config(struct pxp_pixmap *input, + struct pxp_pixmap *output) +{ + uint32_t offset; + struct as_ctrl ctrl; + struct coordinate out_as_ulc, out_as_lrc; + + memset((void*)&ctrl, 0x0, sizeof(ctrl)); + + ctrl.format = pxp_parse_as_fmt(input->format); + + if (alpha_blending_version == PXP_ALPHA_BLENDING_V1) { + if (input->format == PXP_PIX_FMT_BGRA32) { + if (!input->g_alpha.combine_enable) { + ctrl.alpha_ctrl = BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs; + ctrl.rop = 0x3; + } + } + + if (input->g_alpha.global_alpha_enable) { + if (input->g_alpha.global_override) + ctrl.alpha_ctrl = BV_PXP_AS_CTRL_ALPHA_CTRL__Override; + else + ctrl.alpha_ctrl = BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply; + + if (input->g_alpha.alpha_invert) + ctrl.alpha0_invert = 0x1; + } + + if (input->g_alpha.color_key_enable) { + ctrl.enable_colorkey = 1; + } + + ctrl.alpha = input->g_alpha.global_alpha; + } + + out_as_ulc.x = out_as_ulc.y = 0; + if (input->g_alpha.combine_enable) { + out_as_lrc.x = input->width - 1; + out_as_lrc.y = input->height - 1; + } else { + out_as_lrc.x = output->crop.width - 1; + out_as_lrc.y = output->crop.height - 1; + } + + offset = input->crop.y * input->pitch + + input->crop.x * (input->bpp >> 3); + pxp_writel(input->paddr + offset, HW_PXP_AS_BUF); + + pxp_writel(input->pitch, HW_PXP_AS_PITCH); + pxp_writel(*(uint32_t *)&out_as_ulc, HW_PXP_OUT_AS_ULC); + pxp_writel(*(uint32_t *)&out_as_lrc, HW_PXP_OUT_AS_LRC); + + pxp_writel(*(uint32_t *)&ctrl, HW_PXP_AS_CTRL); + pxp_writel(BF_PXP_CTRL_ENABLE_PS_AS_OUT(1) | + BF_PXP_CTRL_IRQ_ENABLE(1), + HW_PXP_CTRL_SET); + + return 0; +} + +static uint32_t pxp_fetch_size_config(struct pxp_pixmap *input) +{ + struct fetch_size total_size; + + memset((void*)&total_size, 0x0, sizeof(total_size)); + + total_size.input_total_width = input->width - 1; + total_size.input_total_height = input->height - 1; + + return *(uint32_t *)&total_size; +} + +static int pxp_fetch_config(struct pxp_pixmap *input, + uint32_t fetch_index) +{ + uint8_t shift_bypass = 1, expand_en = 0; + uint32_t flags, pitch = 0, offset, UV = 0; + uint32_t in_fmt, out_fmt; + uint32_t size_ulc, size_lrc; + uint32_t fetch_ctrl, total_size; + uint32_t shift_ctrl, shift_offset = 0; + struct fetch_shift_width shift_width; + + memset((unsigned int *)&shift_width, 0x0, sizeof(shift_width)); + fetch_ctrl = pxp_fetch_ctrl_config(input, FETCH_MODE_NORMAL); + size_ulc = pxp_fetch_active_size_ulc(input); + size_lrc = pxp_fetch_active_size_lrc(input); + total_size = pxp_fetch_size_config(input); + + if (input->flags) { + flags = fmt_fetch_to_common(input->format); + shift_bypass = (flags & FETCH_SHIFT) ? 0 : 1; + expand_en = (flags & FETCH_EXPAND) ? 1 : 0; + + if (!shift_bypass) { + if (expand_en) { + if (is_yuv(input->format)) { + in_fmt = PXP_PIX_FMT_YVU444; + out_fmt = PXP_PIX_FMT_YUV444; + } else { + in_fmt = PXP_PIX_FMT_ABGR32; + out_fmt = PXP_PIX_FMT_ARGB32; + } + } else { + in_fmt = input->format; + out_fmt = is_yuv(input->format) ? + PXP_PIX_FMT_YUV444 : + PXP_PIX_FMT_ARGB32; + } + + shift_offset = pxp_fetch_shift_calc(in_fmt, out_fmt, + &shift_width); + } + } + shift_ctrl = pxp_fetch_shift_ctrl_config(input, shift_bypass, expand_en); + + offset = input->crop.y * input->pitch + + input->crop.x * (input->bpp >> 3); + if (is_yuv(input->format) == 2) + UV = input->paddr + input->width * input->height; + + switch (fetch_index) { + case PXP_2D_INPUT_FETCH0: + pitch = __raw_readl(pxp_reg_base + HW_PXP_INPUT_FETCH_PITCH); + pitch |= pxp_fetch_pitch_config(input, NULL); + pxp_writel(fetch_ctrl, HW_PXP_INPUT_FETCH_CTRL_CH0); + pxp_writel(size_ulc, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0); + pxp_writel(size_lrc, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0); + pxp_writel(total_size, HW_PXP_INPUT_FETCH_SIZE_CH0); + pxp_writel(shift_ctrl, HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0); + pxp_writel(input->paddr + offset, HW_PXP_INPUT_FETCH_ADDR_0_CH0); + if (UV) + pxp_writel(UV + offset, HW_PXP_INPUT_FETCH_ADDR_1_CH0); + pxp_writel(shift_ctrl, HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0); + if (shift_offset) + pxp_writel(*(uint32_t *)&shift_offset, HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0); + pxp_writel(*(uint32_t *)&shift_width, HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0); + break; + case PXP_2D_INPUT_FETCH1: + pitch = __raw_readl(pxp_reg_base + HW_PXP_INPUT_FETCH_PITCH); + pitch |= pxp_fetch_pitch_config(NULL, input); + pxp_writel(fetch_ctrl, HW_PXP_INPUT_FETCH_CTRL_CH1); + pxp_writel(size_ulc, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1); + pxp_writel(size_lrc, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1); + pxp_writel(total_size, HW_PXP_INPUT_FETCH_SIZE_CH1); + pxp_writel(shift_ctrl, HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1); + pxp_writel(input->paddr + offset, HW_PXP_INPUT_FETCH_ADDR_0_CH1); + if (UV) + pxp_writel(UV + offset, HW_PXP_INPUT_FETCH_ADDR_1_CH1); + pxp_writel(shift_ctrl, HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1); + if (shift_offset) + pxp_writel(*(uint32_t *)&shift_offset, HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1); + pxp_writel(*(uint32_t *)&shift_width, HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1); + break; + default: + break; + } + + pxp_writel(pitch, HW_PXP_INPUT_FETCH_PITCH); + pxp_writel(BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(1), HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_csc1_config(struct pxp_pixmap *input, + bool is_ycbcr) +{ + BUG_ON(!is_yuv(input->format)); + + if (!is_ycbcr) { + /* YUV -> RGB */ + pxp_writel(0x04030000, HW_PXP_CSC1_COEF0); + pxp_writel(0x01230208, HW_PXP_CSC1_COEF1); + pxp_writel(0x076b079c, HW_PXP_CSC1_COEF2); + + return 0; + } + + /* YCbCr -> RGB */ + pxp_writel(0x84ab01f0, HW_PXP_CSC1_COEF0); + pxp_writel(0x01980204, HW_PXP_CSC1_COEF1); + pxp_writel(0x0730079c, HW_PXP_CSC1_COEF2); + + return 0; +} + +static int pxp_rotation1_config(struct pxp_pixmap *input) +{ + uint8_t rotate; + + if (input->flip == PXP_H_FLIP) + pxp_writel(BF_PXP_CTRL_HFLIP1(1), HW_PXP_CTRL_SET); + else if (input->flip == PXP_V_FLIP) + pxp_writel(BF_PXP_CTRL_VFLIP1(1), HW_PXP_CTRL_SET); + + rotate = rotate_map(input->rotate); + pxp_writel(BF_PXP_CTRL_ROTATE1(rotate), HW_PXP_CTRL_SET); + + pxp_writel(BF_PXP_CTRL_ENABLE_ROTATE1(1), HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_rotation0_config(struct pxp_pixmap *input) +{ + uint8_t rotate; + + if (input->flip == PXP_H_FLIP) + pxp_writel(BF_PXP_CTRL_HFLIP0(1), HW_PXP_CTRL_SET); + else if (input->flip == PXP_V_FLIP) + pxp_writel(BF_PXP_CTRL_VFLIP0(1), HW_PXP_CTRL_SET); + + rotate = rotate_map(input->rotate); + pxp_writel(BF_PXP_CTRL_ROTATE0(rotate), HW_PXP_CTRL_SET); + + pxp_writel(BF_PXP_CTRL_ENABLE_ROTATE0(1), HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_csc2_config(struct pxp_pixmap *output) +{ + if (is_yuv(output->format)) { + /* RGB -> YUV */ + pxp_writel(0x4, HW_PXP_CSC2_CTRL); + pxp_writel(0x0096004D, HW_PXP_CSC2_COEF0); + pxp_writel(0x05DA001D, HW_PXP_CSC2_COEF1); + pxp_writel(0x007005B6, HW_PXP_CSC2_COEF2); + pxp_writel(0x057C009E, HW_PXP_CSC2_COEF3); + pxp_writel(0x000005E6, HW_PXP_CSC2_COEF4); + pxp_writel(0x00000000, HW_PXP_CSC2_COEF5); + } + + pxp_writel(BF_PXP_CTRL_ENABLE_CSC2(1), HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_out_config(struct pxp_pixmap *output) +{ + uint32_t offset, UV; + struct out_ctrl ctrl; + struct coordinate out_lrc; + + memset((void*)&ctrl, 0x0, sizeof(ctrl)); + + ctrl.format = pxp_parse_out_fmt(output->format); + offset = output->crop.y * output->pitch + + output->crop.x * (output->bpp >> 3); + + pxp_writel(*(uint32_t *)&ctrl, HW_PXP_OUT_CTRL); + + pxp_writel(output->paddr, HW_PXP_OUT_BUF); + if (is_yuv(output->format) == 2) { + UV = output->paddr + output->width * output->height; + if ((output->format == PXP_PIX_FMT_NV16) || + (output->format == PXP_PIX_FMT_NV61)) + pxp_writel(UV + offset, HW_PXP_OUT_BUF2); + else + pxp_writel(UV + (offset >> 1), HW_PXP_OUT_BUF2); + } + + if (output->rotate == 90 || output->rotate == 270) { + out_lrc.y = output->width - 1; + out_lrc.x = output->height - 1; + } else { + out_lrc.x = output->width - 1; + out_lrc.y = output->height - 1; + } + + pxp_writel(*(uint32_t *)&out_lrc, HW_PXP_OUT_LRC); + + pxp_writel(output->pitch, HW_PXP_OUT_PITCH); + + /* set global alpha if necessary */ + if (output->g_alpha.global_alpha_enable) { + pxp_writel(output->g_alpha.global_alpha << 24, HW_PXP_OUT_CTRL_SET); + pxp_writel(BM_PXP_OUT_CTRL_ALPHA_OUTPUT, HW_PXP_OUT_CTRL_SET); + } + + pxp_writel(BF_PXP_CTRL_ENABLE_PS_AS_OUT(1) | + BF_PXP_CTRL_IRQ_ENABLE(1), + HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_store_config(struct pxp_pixmap *output, + struct pxp_op_info *op) +{ + uint8_t combine_2ch, flags; + uint32_t in_fmt, out_fmt, offset, UV = 0; + uint64_t d_shift = 0; + struct store_d_mask d_mask[8]; + uint32_t store_ctrl, store_size, store_pitch, shift_ctrl; + + memset((void*)d_mask, 0x0, sizeof(*d_mask) * 8); + combine_2ch = (output->bpp == 64) ? 1 : 0; + store_ctrl = pxp_store_ctrl_config(output, STORE_MODE_NORMAL, + op->fill_en, combine_2ch); + store_size = pxp_store_size_config(output); + store_pitch = pxp_store_pitch_config(output, NULL); + + pxp_writel(store_ctrl, HW_PXP_INPUT_STORE_CTRL_CH0); + + if (output->flags) { + flags = fmt_store_from_common(output->format); + if (flags == STORE_NOOP) + shift_ctrl = pxp_store_shift_ctrl_config(output, 1); + else if (flags & STORE_SHIFT) { + in_fmt = is_yuv(output->format) ? PXP_PIX_FMT_YUV444 : + PXP_PIX_FMT_ARGB32; + out_fmt = (flags & STORE_SHRINK) ? PXP_PIX_FMT_YVU444 : + output->format; + d_shift = pxp_store_d_shift_calc(in_fmt, out_fmt, d_mask); + shift_ctrl = pxp_store_shift_ctrl_config(output, 0); + } else + shift_ctrl = pxp_store_shift_ctrl_config(output, 0); + + if (flags & STORE_SHIFT) { + pxp_writel((uint32_t)d_shift, HW_PXP_INPUT_STORE_D_SHIFT_L_CH0); + /* TODO use only 4 masks */ + pxp_writel(d_mask[0].d_mask_l, HW_PXP_INPUT_STORE_D_MASK0_L_CH0); + pxp_writel(d_mask[0].d_mask_h, HW_PXP_INPUT_STORE_D_MASK0_H_CH0); + pxp_writel(d_mask[1].d_mask_l, HW_PXP_INPUT_STORE_D_MASK1_L_CH0); + pxp_writel(d_mask[1].d_mask_h, HW_PXP_INPUT_STORE_D_MASK1_H_CH0); + pxp_writel(d_mask[2].d_mask_l, HW_PXP_INPUT_STORE_D_MASK2_L_CH0); + pxp_writel(d_mask[2].d_mask_h, HW_PXP_INPUT_STORE_D_MASK2_H_CH0); + pxp_writel(d_mask[3].d_mask_l, HW_PXP_INPUT_STORE_D_MASK3_L_CH0); + pxp_writel(d_mask[3].d_mask_h, HW_PXP_INPUT_STORE_D_MASK3_H_CH0); + } + } else + shift_ctrl = pxp_store_shift_ctrl_config(output, 1); + + pxp_writel(shift_ctrl, HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0); + pxp_writel(store_size, HW_PXP_INPUT_STORE_SIZE_CH0); + pxp_writel(store_pitch, HW_PXP_INPUT_STORE_PITCH); + if (op->fill_en) { + uint32_t lrc; + + lrc = (output->width - 1) | ((output->height - 1) << 16); + pxp_writel(op->fill_data, HW_PXP_INPUT_STORE_FILL_DATA_CH0); + + pxp_writel(0x1, HW_PXP_INPUT_FETCH_CTRL_CH0); + pxp_writel(0, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0); + pxp_writel(lrc, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0); + } + + offset = output->crop.y * output->pitch + + output->crop.x * (output->bpp >> 3); + if (is_yuv(output->format == 2)) { + UV = output->paddr + output->width * output->height; + pxp_writel(UV + offset, HW_PXP_INPUT_STORE_ADDR_1_CH0); + } + pxp_writel(output->paddr + offset, HW_PXP_INPUT_STORE_ADDR_0_CH0); + + pxp_writel(BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(1), HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_alpha_config(struct pxp_op_info *op, + uint8_t alpha_node) +{ + uint32_t as_ctrl; + struct pxp_alpha_ctrl alpha_ctrl; + struct pxp_alpha_info *alpha = &op->alpha_info; + struct pxp_alpha *s0_alpha, *s1_alpha; + + memset((void*)&alpha_ctrl, 0x0, sizeof(alpha_ctrl)); + + if (alpha_blending_version != PXP_ALPHA_BLENDING_V1) { + if (alpha->alpha_mode == ALPHA_MODE_ROP) { + switch (alpha_node) { + case PXP_2D_ALPHA0_S0: + as_ctrl = __raw_readl(pxp_reg_base + HW_PXP_AS_CTRL); + as_ctrl |= BF_PXP_AS_CTRL_ALPHA_CTRL(BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs); + as_ctrl |= BF_PXP_AS_CTRL_ROP(alpha->rop_type); + pxp_writel(as_ctrl, HW_PXP_AS_CTRL); + break; + case PXP_2D_ALPHA1_S0: + pxp_writel(BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE | + BF_PXP_ALPHA_B_CTRL_1_ROP(alpha->rop_type), + HW_PXP_ALPHA_B_CTRL_1); + pxp_writel(BF_PXP_CTRL_ENABLE_ALPHA_B(1), HW_PXP_CTRL_SET); + break; + default: + break; + } + + return 0; + } + + s0_alpha = &alpha->s0_alpha; + s1_alpha = &alpha->s1_alpha; + + alpha_ctrl.poter_duff_enable = 1; + + alpha_ctrl.s0_s1_factor_mode = s1_alpha->factor_mode; + alpha_ctrl.s0_global_alpha_mode = s0_alpha->global_alpha_mode; + alpha_ctrl.s0_alpha_mode = s0_alpha->alpha_mode; + alpha_ctrl.s0_color_mode = s0_alpha->color_mode; + + alpha_ctrl.s1_s0_factor_mode = s0_alpha->factor_mode; + alpha_ctrl.s1_global_alpha_mode = s1_alpha->global_alpha_mode; + alpha_ctrl.s1_alpha_mode = s1_alpha->alpha_mode; + alpha_ctrl.s1_color_mode = s1_alpha->color_mode; + + alpha_ctrl.s0_global_alpha = s0_alpha->global_alpha_value; + alpha_ctrl.s1_global_alpha = s1_alpha->global_alpha_value; + + switch (alpha_node) { + case PXP_2D_ALPHA0_S0: + pxp_writel(*(uint32_t *)&alpha_ctrl, HW_PXP_ALPHA_A_CTRL); + break; + case PXP_2D_ALPHA1_S0: + pxp_writel(*(uint32_t *)&alpha_ctrl, HW_PXP_ALPHA_B_CTRL); + pxp_writel(BF_PXP_CTRL_ENABLE_ALPHA_B(1), HW_PXP_CTRL_SET); + break; + default: + break; + } + } + + return 0; +} + +static void pxp_lut_config(struct pxp_op_info *op) +{ + struct pxp_task_info *task = to_pxp_task_info(op); + struct pxps *pxp = to_pxp_from_task(task); + struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data; + int lut_op = proc_data->lut_transform; + u32 reg_val; + int i; + bool use_cmap = (lut_op & PXP_LUT_USE_CMAP) ? true : false; + u8 *cmap = proc_data->lut_map; + u32 entry_src; + u32 pix_val; + u8 entry[4]; + + /* + * If LUT already configured as needed, return... + * Unless CMAP is needed and it has been updated. + */ + if ((pxp->lut_state == lut_op) && + !(use_cmap && proc_data->lut_map_updated)) + return; + + if (lut_op == PXP_LUT_NONE) { + __raw_writel(BM_PXP_LUT_CTRL_BYPASS, + pxp->base + HW_PXP_LUT_CTRL); + } else if (((lut_op & PXP_LUT_INVERT) != 0) + && ((lut_op & PXP_LUT_BLACK_WHITE) != 0)) { + /* Fill out LUT table with inverted monochromized values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) { + entry_src = use_cmap ? + cmap[pix_val + i] : pix_val + i; + entry[i] = (entry_src < 0x80) ? 0xFF : 0x00; + } + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } else if ((lut_op & PXP_LUT_INVERT) != 0) { + /* Fill out LUT table with 8-bit inverted values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) { + entry_src = use_cmap ? + cmap[pix_val + i] : pix_val + i; + entry[i] = ~entry_src & 0xFF; + } + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } else if ((lut_op & PXP_LUT_BLACK_WHITE) != 0) { + /* Fill out LUT table with 8-bit monochromized values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) { + entry_src = use_cmap ? + cmap[pix_val + i] : pix_val + i; + entry[i] = (entry_src < 0x80) ? 0x00 : 0xFF; + } + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } else if (use_cmap) { + /* Fill out LUT table using colormap values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) + entry[i] = cmap[pix_val + i]; + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } + + pxp_writel(BM_PXP_CTRL_ENABLE_ROTATE1 | BM_PXP_CTRL_ENABLE_ROTATE0 | + BM_PXP_CTRL_ENABLE_CSC2 | BM_PXP_CTRL_ENABLE_LUT, + HW_PXP_CTRL_SET); + + pxp->lut_state = lut_op; +} + +static int pxp_2d_task_config(struct pxp_pixmap *input, + struct pxp_pixmap *output, + struct pxp_op_info *op, + uint32_t nodes_used) +{ + uint8_t position = 0; + + + do { + position = find_next_bit((unsigned long *)&nodes_used, 32, position); + if (position >= sizeof(uint32_t) * 8) + break; + + switch (position) { + case PXP_2D_PS: + pxp_ps_config(input, output); + break; + case PXP_2D_AS: + pxp_as_config(input, output); + break; + case PXP_2D_INPUT_FETCH0: + case PXP_2D_INPUT_FETCH1: + pxp_fetch_config(input, position); + break; + case PXP_2D_CSC1: + pxp_csc1_config(input, true); + break; + case PXP_2D_ROTATION1: + pxp_rotation1_config(input); + break; + case PXP_2D_ALPHA0_S0: + case PXP_2D_ALPHA1_S0: + pxp_alpha_config(op, position); + break; + case PXP_2D_ALPHA0_S1: + case PXP_2D_ALPHA1_S1: + break; + case PXP_2D_CSC2: + pxp_csc2_config(output); + break; + case PXP_2D_LUT: + pxp_lut_config(op); + break; + case PXP_2D_ROTATION0: + pxp_rotation0_config(input); + break; + case PXP_2D_OUT: + pxp_out_config(output); + break; + case PXP_2D_INPUT_STORE0: + case PXP_2D_INPUT_STORE1: + pxp_store_config(output, op); + break; + default: + break; + } + + position++; + } while (1); + + return 0; +} + +static void mux_config_helper(struct mux_config *path_ctrl, + struct edge_node *enode) +{ + uint32_t mux_val, mux_pos = 0; + + if (enode->mux_used) { + do { + mux_pos = find_next_bit((unsigned long *)&enode->mux_used, + 32, mux_pos); + if (mux_pos >= 16) + break; + + mux_val = get_mux_val(&enode->muxes, mux_pos); + pr_debug("%s: mux_pos = %d, mux_val = %d\n", + __func__, mux_pos, mux_val); + set_mux_val(path_ctrl, mux_pos, mux_val); + + mux_pos++; + } while (1); + } +} + +static void pxp_2d_calc_mux(uint32_t nodes, struct mux_config *path_ctrl) +{ + struct edge_node *enode; + uint8_t from = 0, to = 0; + + do { + from = find_next_bit((unsigned long *)&nodes, 32, from); + if (from >= sizeof(uint32_t) * 8) + break; + + if (to != 0) { + enode = adj_list[to].first; + while (enode) { + if (enode->adjvex == from) { + mux_config_helper(path_ctrl, enode); + break; + } + enode = enode->next; + } + } + + to = find_next_bit((unsigned long *)&nodes, 32, from + 1); + if (to >= sizeof(uint32_t) * 8) + break; + + enode = adj_list[from].first; + while (enode) { + if (enode->adjvex == to) { + mux_config_helper(path_ctrl, enode); + break; + } + enode = enode->next; + } + + from = to + 1; + } while (1); +} + +static int pxp_2d_op_handler(struct pxps *pxp) +{ + struct mux_config path_ctrl0; + struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data; + struct pxp_task_info *task = &pxp->task; + struct pxp_op_info *op = &task->op_info; + struct pxp_pixmap *input, *output, *input_s0, *input_s1; + uint32_t possible_inputs, possible_outputs; + uint32_t possible_inputs_s0, possible_inputs_s1; + uint32_t inputs_filter_s0, inputs_filter_s1; + uint32_t nodes_used = 0, nodes_in_path; + uint32_t partial_nodes_used = 0; + uint32_t nodes_used_s0 = 0, nodes_used_s1 = 0; + uint32_t nodes_in_path_s0, nodes_in_path_s1; + uint32_t val; + + output = &task->output[0]; + if (!output->pitch) + return -EINVAL; + + *(unsigned int*)&path_ctrl0 = 0xffffffff; + +reparse: + switch (task->input_num) { + case 0: + /* Fill operation: use input store engine */ + if (is_yuv(output->format) > 1) + return -EINVAL; + + if (output->bpp > 32) + return -EINVAL; + + nodes_used = 1 << PXP_2D_INPUT_STORE0; + pxp_2d_task_config(NULL, output, op, nodes_used); + break; + case 1: + /* No Composite */ + possible_inputs = (1 << PXP_2D_PS) | + (1 << PXP_2D_AS) | + (1 << PXP_2D_INPUT_FETCH0); + possible_outputs = (1 << PXP_2D_OUT) | + (1 << PXP_2D_INPUT_STORE0); + + input = &task->input[0]; + if (!input->pitch) + return -EINVAL; + + if (input->rotate || input->flip) { + input->flags |= IN_NEED_ROTATE_FLIP; + output->rotate = input->rotate; + output->flip = input->flip; + } + + if (!is_yuv(input->format) != !is_yuv(output->format)) + input->flags |= IN_NEED_CSC; + else if (input->format != output->format) + input->flags |= IN_NEED_FMT_UNIFIED; + + if ((input->rotate == 90) || (input->rotate == 270)) { + if ((input->crop.width != output->crop.height) || + (input->crop.height != output->crop.width)) + input->flags |= IN_NEED_SCALE; + } else { + if ((input->crop.width != output->crop.width) || + (input->crop.height != output->crop.height)) + input->flags |= IN_NEED_SCALE; + } + + if (input->flags) { + /* only ps has scaling function */ + if ((input->flags & IN_NEED_SCALE) == IN_NEED_SCALE) + possible_inputs = 1 << PXP_2D_PS; + output->flags |= (output->bpp < 32) ? OUT_NEED_SHRINK : + OUT_NEED_SHIFT; + } + + filter_possible_inputs(input, &possible_inputs); + filter_possible_outputs(output, &possible_outputs); + + if (!possible_inputs || !possible_outputs) { + dev_err(&pxp->pdev->dev, "unsupport 2d operation\n"); + return -EINVAL; + } + + if (proc_data->lut_transform) + nodes_used |= (1 << PXP_2D_LUT); + + nodes_in_path = find_best_path(possible_inputs, + possible_outputs, + input, &nodes_used); + + if (nodes_in_path & (1 << PXP_2D_ROTATION1)) { + clear_bit(PXP_2D_ROTATION1, (unsigned long *)&nodes_in_path); + set_bit(PXP_2D_ROTATION0, (unsigned long *)&nodes_in_path); + } + + if (nodes_used & (1 << PXP_2D_ROTATION1)) { + clear_bit(PXP_2D_ROTATION1, (unsigned long *)&nodes_used); + set_bit(PXP_2D_ROTATION0, (unsigned long *)&nodes_used); + } + + pr_debug("%s: nodes_in_path = 0x%x, nodes_used = 0x%x\n", + __func__, nodes_in_path, nodes_used); + if (!nodes_used) { + dev_err(&pxp->pdev->dev, "unsupport 2d operation\n"); + return -EINVAL; + } + + /* If use input fetch0, should use + * alpha b instead of alpha a */ + if (nodes_in_path & (1 << PXP_2D_ALPHA0_S0)) { + if (nodes_in_path & (1 << PXP_2D_INPUT_FETCH0)) { + clear_bit(PXP_2D_ALPHA0_S0, + (unsigned long *)&nodes_in_path); + set_bit(PXP_2D_ALPHA1_S1, + (unsigned long *)&nodes_in_path); + } + } + + /* In this case input read in + * by input fetch engine + */ + if ((nodes_in_path & (1 << PXP_2D_ALPHA1_S1)) || + (nodes_in_path & (1 << PXP_2D_ALPHA1_S0))) { + memcpy(&task->input[1], input, sizeof(*input)); + if (input->rotate == 90 || input->rotate == 270) { + uint32_t temp; + + input = &task->input[1]; + input->rotate = 0; + input->flags = 0; + temp = input->width; + input->width = input->height; + input->height = temp; + input->pitch = input->width * (input->bpp >> 3); + temp = input->crop.width; + input->crop.width = input->crop.height; + input->crop.height = temp; + } + + op->alpha_info.alpha_mode = ALPHA_MODE_ROP; + /* s0 AND s1 */ + op->alpha_info.rop_type = 0x0; + task->input_num = 2; + goto reparse; + } + + pxp_2d_calc_mux(nodes_in_path, &path_ctrl0); + pr_debug("%s: path_ctrl0 = 0x%x\n", + __func__, *(uint32_t *)&path_ctrl0); + pxp_2d_task_config(input, output, op, nodes_used); + + if (is_yuv(input->format) && is_yuv(output->format)) { + val = readl(pxp_reg_base + HW_PXP_CSC1_COEF0); + val |= (BF_PXP_CSC1_COEF0_YCBCR_MODE(1) | + BF_PXP_CSC1_COEF0_BYPASS(1)); + pxp_writel(val, HW_PXP_CSC1_COEF0); + } + break; + case 2: + /* Composite */ + input_s0 = &task->input[0]; + input_s1 = &task->input[1]; + if (!input_s0->pitch || !input_s1->pitch) + return -EINVAL; + + possible_inputs_s0 = (1 << PXP_2D_PS) | + (1 << PXP_2D_INPUT_FETCH0) | + (1 << PXP_2D_INPUT_FETCH1); + possible_inputs_s1 = (1 << PXP_2D_AS) | + (1 << PXP_2D_INPUT_FETCH0); + possible_outputs = (1 << PXP_2D_OUT) | + (1 << PXP_2D_INPUT_STORE0); + + if (input_s0->rotate || input_s0->flip) { + input_s0->flags |= IN_NEED_ROTATE_FLIP; + output->rotate = input_s0->rotate; + output->flip = input_s0->flip; + } + if (input_s1->rotate || input_s1->flip) { + input_s1->flags |= IN_NEED_ROTATE_FLIP; + clear_bit(PXP_2D_AS, + (unsigned long *)&possible_inputs_s1); + } + + if (is_yuv(input_s0->format) && is_yuv(input_s1->format)) + return -EINVAL; + + if (is_yuv(input_s0->format)){ + /* need do yuv -> rgb conversion by csc1 */ + possible_inputs_s0 = 1 << PXP_2D_PS; + input_s0->flags |= IN_NEED_CSC; + } else if (is_yuv(input_s1->format)) { + possible_inputs_s1 = 1 << PXP_2D_PS; + input_s1->flags |= IN_NEED_CSC; + } + + filter_possible_inputs(input_s0, &possible_inputs_s0); + filter_possible_inputs(input_s1, &possible_inputs_s1); + + if (!possible_inputs_s0 || !possible_inputs_s0) + return -EINVAL; + + filter_possible_outputs(output, &possible_outputs); + if (!possible_outputs) + return -EINVAL; + + pr_debug("%s: poss_s0 = 0x%x, poss_s1 = 0x%x, poss_out = 0x%x\n", + __func__, possible_inputs_s0, possible_inputs_s1, possible_outputs); + + inputs_filter_s0 = possible_inputs_s0; + inputs_filter_s1 = possible_inputs_s1; + + /* Using alpha0, possible cases: + * 1. PS --> S0, AS --> S1; + */ + if (possible_inputs_s1 & (1 << PXP_2D_AS)) { + clear_bit(PXP_2D_INPUT_FETCH0, + (unsigned long *)&possible_inputs_s0); + clear_bit(PXP_2D_INPUT_FETCH1, + (unsigned long *)&possible_inputs_s0); + clear_bit(PXP_2D_INPUT_STORE0, + (unsigned long *)&possible_outputs); + + if (!possible_inputs_s0 || !possible_outputs) + goto alpha1; + + nodes_in_path_s0 = find_best_path(possible_inputs_s0, + 1 << PXP_2D_ALPHA0_S0, + input_s0, + &partial_nodes_used); + if (!nodes_in_path_s0) + goto alpha1; + + nodes_used_s0 |= partial_nodes_used; + partial_nodes_used = 0; + + if (is_yuv(output->format)) + set_bit(PXP_2D_CSC2, + (unsigned long *)&partial_nodes_used); + if (output->rotate || output->flip) + set_bit(PXP_2D_ROTATION0, + (unsigned long *)&partial_nodes_used); + + nodes_in_path_s0 |= find_best_path(1 << PXP_2D_ALPHA0_S0, + possible_outputs, + input_s0, + &partial_nodes_used); + if (!(nodes_in_path_s0 & possible_outputs)) + goto alpha1; + nodes_used_s0 |= partial_nodes_used; + + possible_inputs_s1 = (1 << PXP_2D_AS); + nodes_in_path_s1 = find_best_path(possible_inputs_s1, + 1 << PXP_2D_ALPHA0_S1, + input_s1, + &nodes_used_s1); + if (!nodes_in_path_s1) + goto alpha1; + + goto config; + } +alpha1: + partial_nodes_used = 0; + possible_inputs_s0 = inputs_filter_s0; + possible_inputs_s1 = inputs_filter_s1; + + /* Using alpha1, possible cases: + * 1. FETCH1 --> S0, FETCH0 --> S1; + */ + clear_bit(PXP_2D_PS, + (unsigned long *)&possible_inputs_s0); + clear_bit(PXP_2D_INPUT_FETCH0, + (unsigned long *)&possible_inputs_s0); + clear_bit(PXP_2D_OUT, + (unsigned long *)&possible_outputs); + + if (!possible_inputs_s0 || !possible_outputs) + return -EINVAL; + + nodes_in_path_s0 = find_best_path(possible_inputs_s0, + 1 << PXP_2D_ALPHA1_S0, + input_s0, + &partial_nodes_used); + pr_debug("%s: nodes_in_path_s0 = 0x%x\n", __func__, nodes_in_path_s0); + BUG_ON(!nodes_in_path_s0); + + nodes_used_s0 |= partial_nodes_used; + if ((nodes_used_s0 & (1 << PXP_2D_INPUT_FETCH0)) || + (nodes_used_s0 & (1 << PXP_2D_INPUT_FETCH1))) + clear_bit(PXP_2D_OUT, (unsigned long *)&possible_outputs); + else + clear_bit(PXP_2D_INPUT_STORE0, + (unsigned long *)&possible_outputs); + partial_nodes_used = 0; + + if (is_yuv(output->format)) + set_bit(PXP_2D_CSC2, + (unsigned long *)&partial_nodes_used); + if (output->rotate || output->flip) + set_bit(PXP_2D_ROTATION0, + (unsigned long *)&partial_nodes_used); + + nodes_in_path_s0 |= find_best_path(1 << PXP_2D_ALPHA1_S0, + possible_outputs, + input_s0, + &partial_nodes_used); + BUG_ON(!(nodes_in_path_s0 & possible_outputs)); + nodes_used_s0 |= partial_nodes_used; + pr_debug("%s: nodes_in_path_s0 = 0x%x, nodes_used_s0 = 0x%x\n", + __func__, nodes_in_path_s0, nodes_used_s0); + + clear_bit(PXP_2D_AS, + (unsigned long *)&possible_inputs_s1); + BUG_ON(!possible_inputs_s1); + + nodes_in_path_s1 = find_best_path(possible_inputs_s1, + 1 << PXP_2D_ALPHA1_S1, + input_s1, + &nodes_used_s1); + pr_debug("%s: poss_s1 = 0x%x, nodes_used_s1 = 0x%x\n", + __func__, possible_inputs_s1, nodes_used_s1); + BUG_ON(!nodes_in_path_s1); + /* To workaround an IC bug */ + path_ctrl0.mux4_sel = 0x0; +config: + if (nodes_in_path_s0 & (1 << PXP_2D_ROTATION1)) { + clear_bit(PXP_2D_ROTATION1, (unsigned long *)&nodes_in_path_s0); + set_bit(PXP_2D_ROTATION0, (unsigned long *)&nodes_in_path_s0); + } + + pr_debug("%s: nodes_in_path_s0 = 0x%x, nodes_used_s0 = 0x%x, nodes_in_path_s1 = 0x%x, nodes_used_s1 = 0x%x\n", + __func__, nodes_in_path_s0, nodes_used_s0, nodes_in_path_s1, nodes_used_s1); + pxp_2d_calc_mux(nodes_in_path_s0, &path_ctrl0); + pxp_2d_calc_mux(nodes_in_path_s1, &path_ctrl0); + + pr_debug("%s: s0 paddr = 0x%x, s1 paddr = 0x%x, out paddr = 0x%x\n", + __func__, input_s0->paddr, input_s1->paddr, output->paddr); + + if (nodes_used_s0 & (1 << PXP_2D_ROTATION1)) { + clear_bit(PXP_2D_ROTATION1, (unsigned long *)&nodes_used_s0); + set_bit(PXP_2D_ROTATION0, (unsigned long *)&nodes_used_s0); + } + + pxp_2d_task_config(input_s0, output, op, nodes_used_s0); + pxp_2d_task_config(input_s1, output, op, nodes_used_s1); + break; + default: + break; + } + + __raw_writel(proc_data->bgcolor, + pxp->base + HW_PXP_PS_BACKGROUND_0); + pxp_set_colorkey(pxp); + + if (proc_data->lut_transform && pxp_is_v3(pxp)) + set_mux(&path_ctrl0); + + pr_debug("%s: path_ctrl0 = 0x%x\n", + __func__, *(uint32_t *)&path_ctrl0); + pxp_writel(*(uint32_t *)&path_ctrl0, HW_PXP_DATA_PATH_CTRL0); + + return 0; +} + +/** + * pxp_config() - configure PxP for a processing task + * @pxps: PXP context. + * @pxp_chan: PXP channel. + * @return: 0 on success or negative error code on failure. + */ +static int pxp_config(struct pxps *pxp, struct pxp_channel *pxp_chan) +{ + int ret = 0; + struct pxp_task_info *task = &pxp->task; + struct pxp_op_info *op = &task->op_info; + struct pxp_config_data *pxp_conf_data = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf_data->proc_data; + + switch (op->op_type) { + case PXP_OP_TYPE_2D: + pxp_writel(0xffffffff, HW_PXP_OUT_AS_ULC); + pxp_writel(0x0, HW_PXP_OUT_AS_LRC); + pxp_writel(0xffffffff, HW_PXP_OUT_PS_ULC); + pxp_writel(0x0, HW_PXP_OUT_PS_LRC); + pxp_writel(0x0, HW_PXP_INPUT_FETCH_PITCH); + pxp_writel(0x40000000, HW_PXP_CSC1_COEF0); + ret = pxp_2d_op_handler(pxp); + break; + case PXP_OP_TYPE_DITHER: + pxp_dithering_process(pxp); + if (pxp_is_v3p(pxp)) { + __raw_writel( + BM_PXP_CTRL_ENABLE | + BM_PXP_CTRL_ENABLE_DITHER | + BM_PXP_CTRL_ENABLE_CSC2 | + BM_PXP_CTRL_ENABLE_LUT | + BM_PXP_CTRL_ENABLE_ROTATE0 | + BM_PXP_CTRL_ENABLE_PS_AS_OUT, + pxp->base + HW_PXP_CTRL_SET); + return 0; + } + break; + case PXP_OP_TYPE_WFE_A: + pxp_luts_deactivate(pxp, proc_data->lut_sels); + + if (proc_data->lut_cleanup == 0) { + /* We should enable histogram in standard mode + * in wfe_a processing for waveform mode selection + */ + pxp_histogram_enable(pxp, pxp_conf_data->wfe_a_fetch_param[0].width, + pxp_conf_data->wfe_a_fetch_param[0].height); + + pxp_luts_activate(pxp, (u64)proc_data->lut_status_1 | + ((u64)proc_data->lut_status_2 << 32)); + + /* collision detection should be always enable in standard mode */ + pxp_collision_detection_enable(pxp, pxp_conf_data->wfe_a_fetch_param[0].width, + pxp_conf_data->wfe_a_fetch_param[0].height); + } + + if (pxp->devdata && pxp->devdata->pxp_wfe_a_configure) + pxp->devdata->pxp_wfe_a_configure(pxp); + if (pxp->devdata && pxp->devdata->pxp_wfe_a_process) + pxp->devdata->pxp_wfe_a_process(pxp); + break; + case PXP_OP_TYPE_WFE_B: + pxp_wfe_b_configure(pxp); + pxp_wfe_b_process(pxp); + break; + default: + /* Unsupport */ + ret = -EINVAL; + pr_err("Invalid pxp operation type passed\n"); + break; + } + + return ret; +} + +static void pxp_clk_enable(struct pxps *pxp) +{ + mutex_lock(&pxp->clk_mutex); + + if (pxp->clk_stat == CLK_STAT_ON) { + mutex_unlock(&pxp->clk_mutex); + return; + } + + pm_runtime_get_sync(pxp->dev); + + clk_prepare_enable(pxp->ipg_clk); + clk_prepare_enable(pxp->axi_clk); + pxp->clk_stat = CLK_STAT_ON; + + mutex_unlock(&pxp->clk_mutex); +} + +static void pxp_clk_disable(struct pxps *pxp) +{ + unsigned long flags; + + mutex_lock(&pxp->clk_mutex); + + if (pxp->clk_stat == CLK_STAT_OFF) { + mutex_unlock(&pxp->clk_mutex); + return; + } + + spin_lock_irqsave(&pxp->lock, flags); + if ((pxp->pxp_ongoing == 0) && list_empty(&head)) { + spin_unlock_irqrestore(&pxp->lock, flags); + clk_disable_unprepare(pxp->ipg_clk); + clk_disable_unprepare(pxp->axi_clk); + pxp->clk_stat = CLK_STAT_OFF; + } else + spin_unlock_irqrestore(&pxp->lock, flags); + + pm_runtime_put_sync_suspend(pxp->dev); + + mutex_unlock(&pxp->clk_mutex); +} + +static inline void clkoff_callback(struct work_struct *w) +{ + struct pxps *pxp = container_of(w, struct pxps, work); + + pxp_clk_disable(pxp); +} + +static void pxp_clkoff_timer(struct timer_list *t) +{ + struct pxps *pxp = from_timer(pxp, t, clk_timer); + + if ((pxp->pxp_ongoing == 0) && list_empty(&head)) + schedule_work(&pxp->work); + else + mod_timer(&pxp->clk_timer, + jiffies + msecs_to_jiffies(timeout_in_ms)); +} + +static struct pxp_tx_desc *pxpdma_first_queued(struct pxp_channel *pxp_chan) +{ + return list_entry(pxp_chan->queue.next, struct pxp_tx_desc, list); +} + +static int convert_param_to_pixmap(struct pxp_pixmap *pixmap, + struct pxp_layer_param *param) +{ + if (!param->width || !param->height) + return -EINVAL; + + pixmap->width = param->width; + pixmap->height = param->height; + pixmap->format = param->pixel_fmt; + pixmap->paddr = param->paddr; + pixmap->bpp = get_bpp_from_fmt(pixmap->format); + + if (pxp_legacy) { + pixmap->pitch = (param->stride) ? (param->stride * pixmap->bpp >> 3) : + (param->width * pixmap->bpp >> 3); + } else { + if (!param->stride || (param->stride == param->width)) + pixmap->pitch = param->width * pixmap->bpp >> 3; + else + pixmap->pitch = param->stride; + } + + pixmap->crop.x = param->crop.left; + pixmap->crop.y = param->crop.top; + pixmap->crop.width = param->crop.width; + pixmap->crop.height = param->crop.height; + + pixmap->g_alpha.color_key_enable = param->color_key_enable; + pixmap->g_alpha.combine_enable = param->combine_enable; + pixmap->g_alpha.global_alpha_enable = param->global_alpha_enable; + pixmap->g_alpha.global_override = param->global_override; + pixmap->g_alpha.global_alpha = param->global_alpha; + pixmap->g_alpha.alpha_invert = param->alpha_invert; + pixmap->g_alpha.local_alpha_enable = param->local_alpha_enable; + pixmap->g_alpha.comp_mask = param->comp_mask; + + return 0; +} + +/* called with pxp_chan->lock held */ +static void __pxpdma_dostart(struct pxp_channel *pxp_chan) +{ + struct pxp_dma *pxp_dma = to_pxp_dma(pxp_chan->dma_chan.device); + struct pxps *pxp = to_pxp(pxp_dma); + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &config_data->proc_data; + struct pxp_tx_desc *desc; + struct pxp_tx_desc *child; + struct pxp_task_info *task = &pxp->task; + struct pxp_op_info *op = &task->op_info; + struct pxp_alpha_info *alpha = &op->alpha_info; + struct pxp_layer_param *param = NULL; + struct pxp_pixmap *input, *output; + int i = 0, ret; + bool combine_enable = false; + int delta_x, delta_y; + + memset(&pxp->pxp_conf_state.s0_param, 0, sizeof(struct pxp_layer_param)); + memset(&pxp->pxp_conf_state.out_param, 0, sizeof(struct pxp_layer_param)); + memset(pxp->pxp_conf_state.ol_param, 0, sizeof(struct pxp_layer_param)); + memset(&pxp->pxp_conf_state.proc_data, 0, sizeof(struct pxp_proc_data)); + + memset(task, 0, sizeof(*task)); + /* S0 */ + desc = list_first_entry(&head, struct pxp_tx_desc, list); + memcpy(&pxp->pxp_conf_state.s0_param, + &desc->layer_param.s0_param, sizeof(struct pxp_layer_param)); + memcpy(&pxp->pxp_conf_state.proc_data, + &desc->proc_data, sizeof(struct pxp_proc_data)); + + if (proc_data->combine_enable) + alpha_blending_version = PXP_ALPHA_BLENDING_V2; + else + alpha_blending_version = PXP_ALPHA_BLENDING_NONE; + + pxp_legacy = (proc_data->pxp_legacy) ? true : false; + + param = &pxp->pxp_conf_state.s0_param; + if (param->pixel_fmt == PXP_PIX_FMT_YUV420P || + param->pixel_fmt == PXP_PIX_FMT_YVU420P) { + delta_x = proc_data->srect.left - ALIGN_DOWN(proc_data->srect.left, 2); + delta_y = proc_data->srect.top - ALIGN_DOWN(proc_data->srect.top, 2); + + proc_data->srect.left = ALIGN_DOWN(proc_data->srect.left, 2); + proc_data->srect.top = ALIGN_DOWN(proc_data->srect.top, 2); + + proc_data->srect.width = proc_data->srect.width + delta_x; + proc_data->srect.height = proc_data->srect.height + delta_y; + } + + /* Save PxP configuration */ + list_for_each_entry(child, &desc->tx_list, list) { + if (i == 0) { /* Output */ + memcpy(&pxp->pxp_conf_state.out_param, + &child->layer_param.out_param, + sizeof(struct pxp_layer_param)); + } else if (i == 1) { /* Overlay */ + memcpy(&pxp->pxp_conf_state.ol_param[i - 1], + &child->layer_param.ol_param, + sizeof(struct pxp_layer_param)); + if (pxp->pxp_conf_state.ol_param[i - 1].width != 0 && + pxp->pxp_conf_state.ol_param[i - 1].height != 0) { + if (pxp->pxp_conf_state.ol_param[i - 1].combine_enable) + alpha_blending_version = PXP_ALPHA_BLENDING_V1; + } + } + + if (proc_data->engine_enable & PXP_ENABLE_DITHER) { + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_DITHER_FETCH0) + memcpy(&pxp->pxp_conf_state.dither_fetch_param[0], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_DITHER_FETCH1) + memcpy(&pxp->pxp_conf_state.dither_fetch_param[1], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_DITHER_STORE0) + memcpy(&pxp->pxp_conf_state.dither_store_param[0], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_DITHER_STORE1) + memcpy(&pxp->pxp_conf_state.dither_store_param[1], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + op->op_type = PXP_OP_TYPE_DITHER; + } + + if (proc_data->engine_enable & PXP_ENABLE_WFE_A) { + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_A_FETCH0) + memcpy(&pxp->pxp_conf_state.wfe_a_fetch_param[0], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_A_FETCH1) + memcpy(&pxp->pxp_conf_state.wfe_a_fetch_param[1], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_A_STORE0) + memcpy(&pxp->pxp_conf_state.wfe_a_store_param[0], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_A_STORE1) + memcpy(&pxp->pxp_conf_state.wfe_a_store_param[1], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + op->op_type = PXP_OP_TYPE_WFE_A; + } + + if (proc_data->engine_enable & PXP_ENABLE_WFE_B) { + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_B_FETCH0) + memcpy(&pxp->pxp_conf_state.wfe_b_fetch_param[0], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_B_FETCH1) + memcpy(&pxp->pxp_conf_state.wfe_b_fetch_param[1], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_B_STORE0) + memcpy(&pxp->pxp_conf_state.wfe_b_store_param[0], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_B_STORE1) + memcpy(&pxp->pxp_conf_state.wfe_b_store_param[1], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + op->op_type = PXP_OP_TYPE_WFE_B; + } + + i++; + } + + if (!op->op_type) { + op->op_type = PXP_OP_TYPE_2D; + + if ((alpha_blending_version == PXP_ALPHA_BLENDING_V1) || + (alpha_blending_version == PXP_ALPHA_BLENDING_V2)) + combine_enable = true; + + if (combine_enable) + task->input_num = 2; + else if (proc_data->fill_en) + task->input_num = 0; + else + task->input_num = 1; + + output = &task->output[0]; + switch (task->input_num) { + case 0: + op->fill_en = 1; + op->fill_data = proc_data->bgcolor; + break; + case 1: + param = &pxp->pxp_conf_state.s0_param; + input = &task->input[0]; + + ret = convert_param_to_pixmap(input, param); + if (ret < 0) { + param = &pxp->pxp_conf_state.ol_param[0]; + ret = convert_param_to_pixmap(input, param); + BUG_ON(ret < 0); + } else { + input->crop.x = proc_data->srect.left; + input->crop.y = proc_data->srect.top; + input->crop.width = proc_data->srect.width; + input->crop.height = proc_data->srect.height; + } + + input->rotate = proc_data->rotate; + input->flip = (proc_data->hflip) ? PXP_H_FLIP : + (proc_data->vflip) ? PXP_V_FLIP : 0; + break; + case 2: + /* s0 */ + param = &pxp->pxp_conf_state.s0_param; + input = &task->input[0]; + + ret = convert_param_to_pixmap(input, param); + BUG_ON(ret < 0); + input->crop.x = proc_data->srect.left; + input->crop.y = proc_data->srect.top; + input->crop.width = proc_data->srect.width; + input->crop.height = proc_data->srect.height; + alpha->s0_alpha = param->alpha; + + input->rotate = proc_data->rotate; + input->flip = (proc_data->hflip) ? PXP_H_FLIP : + (proc_data->vflip) ? PXP_V_FLIP : 0; + + /* overlay */ + param = &pxp->pxp_conf_state.ol_param[0]; + input = &task->input[1]; + + ret = convert_param_to_pixmap(input, param); + BUG_ON(ret < 0); + alpha->s1_alpha = param->alpha; + alpha->alpha_mode = proc_data->alpha_mode; + break; + } + + param = &pxp->pxp_conf_state.out_param; + ret = convert_param_to_pixmap(output, param); + BUG_ON(ret < 0); + + output->crop.x = proc_data->drect.left; + output->crop.y = proc_data->drect.top; + output->crop.width = proc_data->drect.width; + output->crop.height = proc_data->drect.height; + } + + pr_debug("%s:%d S0 w/h %d/%d paddr %08x\n", __func__, __LINE__, + pxp->pxp_conf_state.s0_param.width, + pxp->pxp_conf_state.s0_param.height, + pxp->pxp_conf_state.s0_param.paddr); + pr_debug("%s:%d S0 crop (top, left)=(%d, %d), (width, height)=(%d, %d)\n", + __func__, __LINE__, + pxp->pxp_conf_state.s0_param.crop.top, + pxp->pxp_conf_state.s0_param.crop.left, + pxp->pxp_conf_state.s0_param.crop.width, + pxp->pxp_conf_state.s0_param.crop.height); + pr_debug("%s:%d OUT w/h %d/%d paddr %08x\n", __func__, __LINE__, + pxp->pxp_conf_state.out_param.width, + pxp->pxp_conf_state.out_param.height, + pxp->pxp_conf_state.out_param.paddr); +} + +static int pxpdma_dostart_work(struct pxps *pxp) +{ + int ret; + struct pxp_channel *pxp_chan = NULL; + unsigned long flags; + dma_async_tx_callback callback; + void *callback_param; + struct pxp_tx_desc *desc = NULL; + struct pxp_tx_desc *child, *_child; + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &config_data->proc_data; + + spin_lock_irqsave(&pxp->lock, flags); + + desc = list_entry(head.next, struct pxp_tx_desc, list); + pxp_chan = to_pxp_channel(desc->txd.chan); + + __pxpdma_dostart(pxp_chan); + + /* Configure PxP */ + ret = pxp_config(pxp, pxp_chan); + if (ret) { + callback = desc->txd.callback; + callback_param = desc->txd.callback_param; + + callback(callback_param); + + /* Unsupport operation */ + list_for_each_entry_safe(child, _child, &desc->tx_list, list) { + list_del_init(&child->list); + kmem_cache_free(tx_desc_cache, (void *)child); + } + list_del_init(&desc->list); + kmem_cache_free(tx_desc_cache, (void *)desc); + + spin_unlock_irqrestore(&pxp->lock, flags); + return -EINVAL; + } + + if (proc_data->working_mode & PXP_MODE_STANDARD) { + if(!pxp_is_v3p(pxp) || !(proc_data->engine_enable & PXP_ENABLE_DITHER)) + pxp_start2(pxp); + } else + pxp_start(pxp); + + spin_unlock_irqrestore(&pxp->lock, flags); + + return 0; +} + +static void pxpdma_dequeue(struct pxp_channel *pxp_chan, struct pxps *pxp) +{ + unsigned long flags; + struct pxp_tx_desc *desc = NULL; + + do { + desc = pxpdma_first_queued(pxp_chan); + spin_lock_irqsave(&pxp->lock, flags); + list_move_tail(&desc->list, &head); + spin_unlock_irqrestore(&pxp->lock, flags); + } while (!list_empty(&pxp_chan->queue)); +} + +static dma_cookie_t pxp_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct pxp_tx_desc *desc = to_tx_desc(tx); + struct pxp_channel *pxp_chan = to_pxp_channel(tx->chan); + dma_cookie_t cookie; + + dev_dbg(&pxp_chan->dma_chan.dev->device, "received TX\n"); + + /* pxp_chan->lock can be taken under ichan->lock, but not v.v. */ + spin_lock(&pxp_chan->lock); + + cookie = pxp_chan->dma_chan.cookie; + + if (++cookie < 0) + cookie = 1; + + /* from dmaengine.h: "last cookie value returned to client" */ + pxp_chan->dma_chan.cookie = cookie; + tx->cookie = cookie; + + /* Here we add the tx descriptor to our PxP task queue. */ + list_add_tail(&desc->list, &pxp_chan->queue); + + spin_unlock(&pxp_chan->lock); + + dev_dbg(&pxp_chan->dma_chan.dev->device, "done TX\n"); + + return cookie; +} + +/** + * pxp_init_channel() - initialize a PXP channel. + * @pxp_dma: PXP DMA context. + * @pchan: pointer to the channel object. + * @return 0 on success or negative error code on failure. + */ +static int pxp_init_channel(struct pxp_dma *pxp_dma, + struct pxp_channel *pxp_chan) +{ + int ret = 0; + + /* + * We are using _virtual_ channel here. + * Each channel contains all parameters of corresponding layers + * for one transaction; each layer is represented as one descriptor + * (i.e., pxp_tx_desc) here. + */ + + INIT_LIST_HEAD(&pxp_chan->queue); + + return ret; +} + +static irqreturn_t pxp_irq(int irq, void *dev_id) +{ + struct pxps *pxp = dev_id; + struct pxp_channel *pxp_chan; + struct pxp_tx_desc *desc; + struct pxp_tx_desc *child, *_child; + dma_async_tx_callback callback; + void *callback_param; + unsigned long flags; + u32 hist_status; + int pxp_irq_status = 0; + + dump_pxp_reg(pxp); + + if (__raw_readl(pxp->base + HW_PXP_STAT) & BM_PXP_STAT_IRQ0) + __raw_writel(BM_PXP_STAT_IRQ0, pxp->base + HW_PXP_STAT_CLR); + else { + int irq_clr = 0; + + pxp_irq_status = __raw_readl(pxp->base + HW_PXP_IRQ); + BUG_ON(!pxp_irq_status); + + if (pxp_irq_status & BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ) + irq_clr |= BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ) + irq_clr |= BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_FIRST_CH0_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_FIRST_CH0_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_FIRST_CH1_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_FIRST_CH1_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_FIRST_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_FIRST_STORE_IRQ; + + if (pxp_irq_status & BM_PXP_IRQ_WFE_B_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_WFE_B_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_WFE_A_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_WFE_A_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_DITHER_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_DITHER_STORE_IRQ; + + if (pxp_irq_status & BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ; + + if (pxp_irq_status & BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ; + + if (pxp_irq_status & BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ) + irq_clr |= BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ) + irq_clr |= BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_DITHER_CH0_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_DITHER_CH0_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_DITHER_CH1_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_DITHER_CH1_STORE_IRQ; + /*XXX other irqs status clear should be added below */ + + __raw_writel(irq_clr, pxp->base + HW_PXP_IRQ_CLR); + + pxp_writel(BM_PXP_CTRL_ENABLE, HW_PXP_CTRL_CLR); + } + pxp_collision_status_report(pxp, &col_info); + pxp_histogram_status_report(pxp, &hist_status); + /*XXX before a new update operation, we should + * always clear all the collision information + */ + pxp_collision_detection_disable(pxp); + pxp_histogram_disable(pxp); + + pxp_writel(0x0, HW_PXP_CTRL); + pxp_soft_reset(pxp); + if (pxp->devdata && pxp->devdata->pxp_data_path_config) + pxp->devdata->pxp_data_path_config(pxp); + __raw_writel(0xffff, pxp->base + HW_PXP_IRQ_MASK); + + spin_lock_irqsave(&pxp->lock, flags); + if (list_empty(&head)) { + pxp->pxp_ongoing = 0; + spin_unlock_irqrestore(&pxp->lock, flags); + return IRQ_NONE; + } + + /* Get descriptor and call callback */ + desc = list_entry(head.next, struct pxp_tx_desc, list); + pxp_chan = to_pxp_channel(desc->txd.chan); + + pxp_chan->completed = desc->txd.cookie; + + callback = desc->txd.callback; + callback_param = desc->txd.callback_param; + + /* Send histogram status back to caller */ + desc->hist_status = hist_status; + + if ((desc->txd.flags & DMA_PREP_INTERRUPT) && callback) + callback(callback_param); + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; + + list_for_each_entry_safe(child, _child, &desc->tx_list, list) { + list_del_init(&child->list); + kmem_cache_free(tx_desc_cache, (void *)child); + } + list_del_init(&desc->list); + kmem_cache_free(tx_desc_cache, (void *)desc); + + complete(&pxp->complete); + pxp->pxp_ongoing = 0; + mod_timer(&pxp->clk_timer, jiffies + msecs_to_jiffies(timeout_in_ms)); + + spin_unlock_irqrestore(&pxp->lock, flags); + + return IRQ_HANDLED; +} + +/* allocate/free dma tx descriptor dynamically*/ +static struct pxp_tx_desc *pxpdma_desc_alloc(struct pxp_channel *pxp_chan) +{ + struct pxp_tx_desc *desc = NULL; + struct dma_async_tx_descriptor *txd = NULL; + + desc = kmem_cache_alloc(tx_desc_cache, GFP_KERNEL | __GFP_ZERO); + if (desc == NULL) + return NULL; + + INIT_LIST_HEAD(&desc->list); + INIT_LIST_HEAD(&desc->tx_list); + txd = &desc->txd; + dma_async_tx_descriptor_init(txd, &pxp_chan->dma_chan); + txd->tx_submit = pxp_tx_submit; + + return desc; +} + + +/* Allocate and initialise a transfer descriptor. */ +static struct dma_async_tx_descriptor *pxp_prep_slave_sg(struct dma_chan *chan, + struct scatterlist + *sgl, + unsigned int sg_len, + enum + dma_transfer_direction + direction, + unsigned long tx_flags, + void *context) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + struct pxps *pxp = to_pxp(pxp_dma); + struct pxp_tx_desc *pos = NULL, *next = NULL; + struct pxp_tx_desc *desc = NULL; + struct pxp_tx_desc *first = NULL, *prev = NULL; + struct scatterlist *sg; + dma_addr_t phys_addr; + int i; + + if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV) { + dev_err(chan->device->dev, "Invalid DMA direction %d!\n", + direction); + return NULL; + } + + if (unlikely(sg_len < 2)) + return NULL; + + for_each_sg(sgl, sg, sg_len, i) { + desc = pxpdma_desc_alloc(pxp_chan); + if (!desc) { + dev_err(chan->device->dev, "no enough memory to allocate tx descriptor\n"); + + if (first) { + list_for_each_entry_safe(pos, next, &first->tx_list, list) { + list_del_init(&pos->list); + kmem_cache_free(tx_desc_cache, (void*)pos); + } + list_del_init(&first->list); + kmem_cache_free(tx_desc_cache, (void*)first); + } + + return NULL; + } + + phys_addr = sg_dma_address(sg); + + if (!first) { + first = desc; + + desc->layer_param.s0_param.paddr = phys_addr; + } else { + list_add_tail(&desc->list, &first->tx_list); + prev->next = desc; + desc->next = NULL; + + if (i == 1) + desc->layer_param.out_param.paddr = phys_addr; + else + desc->layer_param.ol_param.paddr = phys_addr; + } + + prev = desc; + } + + pxp->pxp_conf_state.layer_nr = sg_len; + first->txd.flags = tx_flags; + first->len = sg_len; + pr_debug("%s:%d first %p, first->len %d, flags %08x\n", + __func__, __LINE__, first, first->len, first->txd.flags); + + return &first->txd; +} + +static void pxp_issue_pending(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + struct pxps *pxp = to_pxp(pxp_dma); + + spin_lock(&pxp_chan->lock); + + if (list_empty(&pxp_chan->queue)) { + spin_unlock(&pxp_chan->lock); + return; + } + + pxpdma_dequeue(pxp_chan, pxp); + pxp_chan->status = PXP_CHANNEL_READY; + + spin_unlock(&pxp_chan->lock); + + pxp_clk_enable(pxp); + wake_up_interruptible(&pxp->thread_waitq); +} + +static void __pxp_terminate_all(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + pxp_chan->status = PXP_CHANNEL_INITIALIZED; +} + +static int pxp_device_terminate_all(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + spin_lock(&pxp_chan->lock); + __pxp_terminate_all(chan); + spin_unlock(&pxp_chan->lock); + + return 0; +} + +static int pxp_alloc_chan_resources(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + int ret; + + /* dmaengine.c now guarantees to only offer free channels */ + BUG_ON(chan->client_count > 1); + WARN_ON(pxp_chan->status != PXP_CHANNEL_FREE); + + chan->cookie = 1; + pxp_chan->completed = -ENXIO; + + pr_debug("%s dma_chan.chan_id %d\n", __func__, chan->chan_id); + ret = pxp_init_channel(pxp_dma, pxp_chan); + if (ret < 0) + goto err_chan; + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; + + dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n", + chan->chan_id, pxp_chan->eof_irq); + + return ret; + +err_chan: + return ret; +} + +static void pxp_free_chan_resources(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + spin_lock(&pxp_chan->lock); + + __pxp_terminate_all(chan); + + pxp_chan->status = PXP_CHANNEL_FREE; + + spin_unlock(&pxp_chan->lock); +} + +static enum dma_status pxp_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + if (cookie != chan->cookie) + return DMA_ERROR; + + if (txstate) { + txstate->last = pxp_chan->completed; + txstate->used = chan->cookie; + txstate->residue = 0; + } + return DMA_COMPLETE; +} + +static void pxp_data_path_config_v3p(struct pxps *pxp) +{ + u32 val = 0; + + __raw_writel( + BF_PXP_DATA_PATH_CTRL0_MUX15_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(1)| + BF_PXP_DATA_PATH_CTRL0_MUX13_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX12_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX11_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX10_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX9_SEL(1)| + BF_PXP_DATA_PATH_CTRL0_MUX8_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX7_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX6_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX5_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX4_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX3_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX2_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX1_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX0_SEL(0), + pxp->base + HW_PXP_DATA_PATH_CTRL0); + + /* + * MUX17: HIST_B as histogram: 0: output buffer, 1: wfe_store + * MUX16: HIST_A as collision: 0: output buffer, 1: wfe_store + */ + if (pxp_is_v3(pxp)) + val = BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(1)| + BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(0); + else if (pxp_is_v3p(pxp)) + val = BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(1)| + BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(1); + __raw_writel(val, pxp->base + HW_PXP_DATA_PATH_CTRL1); +} + +static void pxp_soft_reset(struct pxps *pxp) +{ + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_CLR); + __raw_writel(BM_PXP_CTRL_CLKGATE, pxp->base + HW_PXP_CTRL_CLR); + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_SET); + while (!(__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_CLKGATE)) + dev_dbg(pxp->dev, "%s: wait for clock gate off", __func__); + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_CLR); + __raw_writel(BM_PXP_CTRL_CLKGATE, pxp->base + HW_PXP_CTRL_CLR); +} + +static void pxp_sram_init(struct pxps *pxp, u32 select, + u32 buffer_addr, u32 length) +{ + u32 i; + + __raw_writel( + BF_PXP_INIT_MEM_CTRL_ADDR(0) | + BF_PXP_INIT_MEM_CTRL_SELECT(select) | + BF_PXP_INIT_MEM_CTRL_START(1), + pxp->base + HW_PXP_INIT_MEM_CTRL); + + if ((select == WFE_A) || (select == WFE_B)) { + for (i = 0; i < length / 2; i++) { + __raw_writel(*(((u32*)buffer_addr) + 2 * i + 1), + pxp->base + HW_PXP_INIT_MEM_DATA_HIGH); + + __raw_writel(*(((u32*)buffer_addr) + 2 * i), + pxp->base + HW_PXP_INIT_MEM_DATA); + } + } else { + for (i = 0; i < length; i++) { + __raw_writel(*(((u32*) buffer_addr) + i), + pxp->base + HW_PXP_INIT_MEM_DATA); + } + } + + __raw_writel( + BF_PXP_INIT_MEM_CTRL_ADDR(0) | + BF_PXP_INIT_MEM_CTRL_SELECT(select) | + BF_PXP_INIT_MEM_CTRL_START(0), + pxp->base + HW_PXP_INIT_MEM_CTRL); +} + +/* + * wfe a configuration + * configure wfe a engine for waveform processing + * including its fetch and store module + */ +static void pxp_wfe_a_configure(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + + /* FETCH */ + __raw_writel( + BF_PXP_WFA_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFA_FETCH_CTRL); + + __raw_writel( + BF_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL(1) | + BF_PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS(0) | + BF_PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS(3), + pxp->base + HW_PXP_WFA_ARRAY_PIXEL0_MASK); + + __raw_writel( + BF_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL(1) | + BF_PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS(4) | + BF_PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS(7), + pxp->base + HW_PXP_WFA_ARRAY_PIXEL1_MASK); + + __raw_writel( + BF_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL(1) | + BF_PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS(8) | + BF_PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS(9), + pxp->base + HW_PXP_WFA_ARRAY_PIXEL2_MASK); + + __raw_writel( + BF_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL(1) | + BF_PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS(10) | + BF_PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS(15), + pxp->base + HW_PXP_WFA_ARRAY_PIXEL3_MASK); + + __raw_writel( + BF_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL(0) | + BF_PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS(4) | + BF_PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS(7), + pxp->base + HW_PXP_WFA_ARRAY_PIXEL4_MASK); + + __raw_writel(1, pxp->base + HW_PXP_WFA_ARRAY_REG2); + + /* STORE */ + __raw_writel( + BF_PXP_WFE_A_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL(1)| + BF_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES(8)| + BF_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL(1) | + BF_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH0); + + __raw_writel( + BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES(16), + pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH1); + + __raw_writel( + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(0)| + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(0), + pxp->base + HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH0); + + + __raw_writel( + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(1)| + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(0), + pxp->base + HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH1); + + __raw_writel(BF_PXP_WFE_A_STORE_FILL_DATA_CH0_FILL_DATA_CH0(0), + pxp->base + HW_PXP_WFE_A_STORE_FILL_DATA_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(0x0), + pxp->base + HW_PXP_WFE_A_STORE_D_MASK0_H_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0xf), /* fetch CP */ + pxp->base + HW_PXP_WFE_A_STORE_D_MASK0_L_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), + pxp->base + HW_PXP_WFE_A_STORE_D_MASK1_H_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0xf00), /* fetch NP */ + pxp->base + HW_PXP_WFE_A_STORE_D_MASK1_L_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x0), + pxp->base + HW_PXP_WFE_A_STORE_D_MASK2_H_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x00000), + pxp->base + HW_PXP_WFE_A_STORE_D_MASK2_L_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(0x0), + pxp->base + HW_PXP_WFE_A_STORE_D_MASK3_H_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(0x3f000000), /* fetch LUT */ + pxp->base + HW_PXP_WFE_A_STORE_D_MASK3_L_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(0xf), + pxp->base + HW_PXP_WFE_A_STORE_D_MASK4_H_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(0x0), /* fetch Y4 */ + pxp->base + HW_PXP_WFE_A_STORE_D_MASK4_L_CH0); + + __raw_writel( + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(32) | + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(1) | + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(28)| + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1) | + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(24)| + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(1)| + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(18)| + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(1), + pxp->base + HW_PXP_WFE_A_STORE_D_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(28) | + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(0) | + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(0)| + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(0) | + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(0)| + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(0) | + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(0), + pxp->base + HW_PXP_WFE_A_STORE_D_SHIFT_H_CH0); + + __raw_writel( + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(1)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(1)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(32+6)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(1)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(32+6)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(1), + pxp->base + HW_PXP_WFE_A_STORE_F_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4(0)| + BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5(0)| + BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6(0)| + BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7(0), + pxp->base + HW_PXP_WFE_A_STORE_F_MASK_H_CH0); + + + __raw_writel( + BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0(0x1) | + BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1(0x2) | + BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2(0x4) | + BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3(0x8), + pxp->base + HW_PXP_WFE_A_STORE_F_MASK_L_CH0); + + /* ALU */ + __raw_writel(BF_PXP_ALU_A_INST_ENTRY_ENTRY_ADDR(0), + pxp->base + HW_PXP_ALU_A_INST_ENTRY); + + __raw_writel(BF_PXP_ALU_A_PARAM_PARAM0(0) | + BF_PXP_ALU_A_PARAM_PARAM1(0), + pxp->base + HW_PXP_ALU_A_PARAM); + + __raw_writel(BF_PXP_ALU_A_CONFIG_BUF_ADDR(0), + pxp->base + HW_PXP_ALU_A_CONFIG); + + __raw_writel(BF_PXP_ALU_A_LUT_CONFIG_MODE(0) | + BF_PXP_ALU_A_LUT_CONFIG_EN(0), + pxp->base + HW_PXP_ALU_A_LUT_CONFIG); + + __raw_writel(BF_PXP_ALU_A_LUT_DATA0_LUT_DATA_L(0), + pxp->base + HW_PXP_ALU_A_LUT_DATA0); + + __raw_writel(BF_PXP_ALU_A_LUT_DATA1_LUT_DATA_H(0), + pxp->base + HW_PXP_ALU_A_LUT_DATA1); + + __raw_writel(BF_PXP_ALU_A_CTRL_BYPASS (1) | + BF_PXP_ALU_A_CTRL_ENABLE (1) | + BF_PXP_ALU_A_CTRL_START (0) | + BF_PXP_ALU_A_CTRL_SW_RESET (0), + pxp->base + HW_PXP_ALU_A_CTRL); + + /* WFE A */ + __raw_writel(0x3F3F0303, pxp->base + HW_PXP_WFE_A_STAGE1_MUX0); + __raw_writel(0x0C00000C, pxp->base + HW_PXP_WFE_A_STAGE1_MUX1); + __raw_writel(0x01040000, pxp->base + HW_PXP_WFE_A_STAGE1_MUX2); + __raw_writel(0x0A0A0904, pxp->base + HW_PXP_WFE_A_STAGE1_MUX3); + __raw_writel(0x00000B0B, pxp->base + HW_PXP_WFE_A_STAGE1_MUX4); + + __raw_writel(0x1800280E, pxp->base + HW_PXP_WFE_A_STAGE2_MUX0); + __raw_writel(0x00280E01, pxp->base + HW_PXP_WFE_A_STAGE2_MUX1); + __raw_writel(0x280E0118, pxp->base + HW_PXP_WFE_A_STAGE2_MUX2); + __raw_writel(0x00011800, pxp->base + HW_PXP_WFE_A_STAGE2_MUX3); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STAGE2_MUX4); + __raw_writel(0x1800280E, pxp->base + HW_PXP_WFE_A_STAGE2_MUX5); + __raw_writel(0x00280E01, pxp->base + HW_PXP_WFE_A_STAGE2_MUX6); + __raw_writel(0x1A0E0118, pxp->base + HW_PXP_WFE_A_STAGE2_MUX7); + __raw_writel(0x1B012911, pxp->base + HW_PXP_WFE_A_STAGE2_MUX8); + __raw_writel(0x00002911, pxp->base + HW_PXP_WFE_A_STAGE2_MUX9); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STAGE2_MUX10); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STAGE2_MUX11); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STAGE2_MUX12); + + __raw_writel(0x07060504, pxp->base + HW_PXP_WFE_A_STAGE3_MUX0); + __raw_writel(0x3F3F3F08, pxp->base + HW_PXP_WFE_A_STAGE3_MUX1); + __raw_writel(0x03020100, pxp->base + HW_PXP_WFE_A_STAGE3_MUX2); + __raw_writel(0x3F3F3F3F, pxp->base + HW_PXP_WFE_A_STAGE3_MUX3); + + __raw_writel(0x001F1F1F, pxp->base + HW_PXP_WFE_A_STAGE2_5X6_MASKS_0); + __raw_writel(0x3f030100, pxp->base + HW_PXP_WFE_A_STAGE2_5X6_ADDR_0); + + __raw_writel(0x00000700, pxp->base + HW_PXP_WFE_A_STG2_5X1_OUT0); + __raw_writel(0x00007000, pxp->base + HW_PXP_WFE_A_STG2_5X1_OUT1); + __raw_writel(0x0000A000, pxp->base + HW_PXP_WFE_A_STG2_5X1_OUT2); + __raw_writel(0x000000C0, pxp->base + HW_PXP_WFE_A_STG2_5X1_OUT3); + __raw_writel(0x071F1F1F, pxp->base + HW_PXP_WFE_A_STG2_5X1_MASKS); + + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_2); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_3); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_4); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_5); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_6); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_7); + + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_0); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_1); + __raw_writel(0x04050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_2); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_3); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_4); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_5); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_6); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_7); + + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_0); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_1); + __raw_writel(0x05080808, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_2); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_3); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_4); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_5); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_6); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_7); + + __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_0); + __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_1); + __raw_writel(0x070C0C0C, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_2); + __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_3); + __raw_writel(0X0F0F0F0F, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_4); + __raw_writel(0X0F0F0F0F, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_5); + __raw_writel(0X0F0F0F0F, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_6); + __raw_writel(0X0F0F0F0F, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_7); + + if (pxp->devdata && pxp->devdata->pxp_lut_cleanup_multiple) + pxp->devdata->pxp_lut_cleanup_multiple(pxp, + proc_data->lut_sels, 1); +} + +static void pxp_wfe_a_configure_v3p(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + + /* FETCH */ + __raw_writel( + BF_PXP_WFB_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFB_FETCH_CTRL); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS(3), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL0_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS(4) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL1_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS(8) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS(9), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL2_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS(10) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS(15), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL3_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS(4) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL4_MASK); + + __raw_writel(1, pxp->base + HW_PXP_WFB_ARRAY_REG2); + + /* STORE */ + __raw_writel( + BF_PXP_WFE_B_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES(8)| + BF_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL(1) | + BF_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL(1)| + BF_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES(16), + pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(0), + pxp->base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0); + + + __raw_writel( + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(1)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(0), + pxp->base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1); + + __raw_writel(BF_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0(0), + pxp->base + HW_PXP_WFE_B_STORE_FILL_DATA_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK0_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0xf), /* fetch CP */ + pxp->base + HW_PXP_WFE_B_STORE_D_MASK0_L_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0xf00), /* fetch NP */ + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_L_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x00000), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_L_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK3_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(0x3f000000), /* fetch LUT */ + pxp->base + HW_PXP_WFE_B_STORE_D_MASK3_L_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(0xf), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK4_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(0x0), /* fetch Y4 */ + pxp->base + HW_PXP_WFE_B_STORE_D_MASK4_L_CH0); + + __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK5_H_CH0); + __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK5_L_CH0); + __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK6_H_CH0); + __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK6_L_CH0); + __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK7_H_CH0); + __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK7_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(32) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(1) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(28)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(24)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(1)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(18)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(1), + pxp->base + HW_PXP_WFE_B_STORE_D_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(28) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(0), + pxp->base + HW_PXP_WFE_B_STORE_D_SHIFT_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(32+6)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(32+6)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(1), + pxp->base + HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(0), + pxp->base + HW_PXP_WFE_B_STORE_F_SHIFT_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0(0x1) | + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1(0x2) | + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2(0x4) | + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3(0x8), + pxp->base + HW_PXP_WFE_B_STORE_F_MASK_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4(0x0)| + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5(0x0)| + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6(0x0)| + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7(0x0), + pxp->base + HW_PXP_WFE_B_STORE_F_MASK_H_CH0); + + + /* ALU */ + __raw_writel(BF_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR(0), + pxp->base + HW_PXP_ALU_B_INST_ENTRY); + + __raw_writel(BF_PXP_ALU_B_PARAM_PARAM0(0) | + BF_PXP_ALU_B_PARAM_PARAM1(0), + pxp->base + HW_PXP_ALU_B_PARAM); + + __raw_writel(BF_PXP_ALU_B_CONFIG_BUF_ADDR(0), + pxp->base + HW_PXP_ALU_B_CONFIG); + + __raw_writel(BF_PXP_ALU_B_LUT_CONFIG_MODE(0) | + BF_PXP_ALU_B_LUT_CONFIG_EN(0), + pxp->base + HW_PXP_ALU_B_LUT_CONFIG); + + __raw_writel(BF_PXP_ALU_B_LUT_DATA0_LUT_DATA_L(0), + pxp->base + HW_PXP_ALU_B_LUT_DATA0); + + __raw_writel(BF_PXP_ALU_B_LUT_DATA1_LUT_DATA_H(0), + pxp->base + HW_PXP_ALU_B_LUT_DATA1); + + __raw_writel(BF_PXP_ALU_B_CTRL_BYPASS (1) | + BF_PXP_ALU_B_CTRL_ENABLE (1) | + BF_PXP_ALU_B_CTRL_START (0) | + BF_PXP_ALU_B_CTRL_SW_RESET (0), + pxp->base + HW_PXP_ALU_B_CTRL); + + /* WFE A */ + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX2); + __raw_writel(0x03000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX3); + __raw_writel(0x00000003, pxp->base + HW_PXP_WFE_B_STAGE1_MUX4); + __raw_writel(0x04000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX5); + __raw_writel(0x0A090401, pxp->base + HW_PXP_WFE_B_STAGE1_MUX6); + __raw_writel(0x000B0B0A, pxp->base + HW_PXP_WFE_B_STAGE1_MUX7); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX8); + + __raw_writel(0x1901290C, pxp->base + HW_PXP_WFE_B_STAGE2_MUX0); + __raw_writel(0x01290C02, pxp->base + HW_PXP_WFE_B_STAGE2_MUX1); + __raw_writel(0x290C0219, pxp->base + HW_PXP_WFE_B_STAGE2_MUX2); + __raw_writel(0x00021901, pxp->base + HW_PXP_WFE_B_STAGE2_MUX3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STAGE2_MUX4); + __raw_writel(0x1901290C, pxp->base + HW_PXP_WFE_B_STAGE2_MUX5); + __raw_writel(0x01290C02, pxp->base + HW_PXP_WFE_B_STAGE2_MUX6); + __raw_writel(0x1B0C0219, pxp->base + HW_PXP_WFE_B_STAGE2_MUX7); + __raw_writel(0x1C022A0F, pxp->base + HW_PXP_WFE_B_STAGE2_MUX8); + __raw_writel(0x02002A0F, pxp->base + HW_PXP_WFE_B_STAGE2_MUX9); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STAGE2_MUX10); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STAGE2_MUX11); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STAGE2_MUX12); + + __raw_writel(0x2a123a1d, pxp->base + HW_PXP_WFE_B_STAGE3_MUX0); + __raw_writel(0x00000013, pxp->base + HW_PXP_WFE_B_STAGE3_MUX1); + __raw_writel(0x2a123a1d, pxp->base + HW_PXP_WFE_B_STAGE3_MUX2); + __raw_writel(0x00000013, pxp->base + HW_PXP_WFE_B_STAGE3_MUX3); + __raw_writel(0x3b202c1d, pxp->base + HW_PXP_WFE_B_STAGE3_MUX4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX5); + __raw_writel(0x003b202d, pxp->base + HW_PXP_WFE_B_STAGE3_MUX6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX7); + __raw_writel(0x07060504, pxp->base + HW_PXP_WFE_B_STAGE3_MUX8); + __raw_writel(0x00000008, pxp->base + HW_PXP_WFE_B_STAGE3_MUX9); + __raw_writel(0x03020100, pxp->base + HW_PXP_WFE_B_STAGE3_MUX10); + + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_7); + + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_7); + + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_5X8_MASKS_0); + + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X1_OUT0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X1_MASKS); + + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_2); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_3); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_4); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_5); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_6); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_7); + + __raw_writel(0x00000700, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT0); + __raw_writel(0x00007000, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT1); + __raw_writel(0x0000A000, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT2); + __raw_writel(0x000000C0, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT3); + __raw_writel(0x070F1F1F, pxp->base + HW_PXP_WFE_B_STG2_5X1_MASKS); + + __raw_writel(0x001F1F1F, pxp->base + HW_PXP_WFE_B_STAGE2_5X6_MASKS_0); + __raw_writel(0x3f232120, pxp->base + HW_PXP_WFE_B_STAGE2_5X6_ADDR_0); + + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_0); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_1); + __raw_writel(0x04050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_2); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_3); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_4); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_5); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_6); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_7); + + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_0); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_1); + __raw_writel(0x05080808, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_2); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_3); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_4); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_5); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_6); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_7); + + __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_0); + __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_1); + __raw_writel(0x070C0C0C, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_2); + __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_3); + __raw_writel(0x0F0F0F0F, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_4); + __raw_writel(0x0F0F0F0F, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_5); + __raw_writel(0x0F0F0F0F, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_6); + __raw_writel(0x0F0F0F0F, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_7); + + __raw_writel(0x070F1F1F, pxp->base + HW_PXP_WFE_B_STG3_F8X1_MASKS); + + __raw_writel(0x00000700, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_7); + + __raw_writel(0x00007000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_7); + + __raw_writel(0x0000A000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_7); + + __raw_writel(0x000000C0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_7); + + if (pxp->devdata && pxp->devdata->pxp_lut_cleanup_multiple) + pxp->devdata->pxp_lut_cleanup_multiple(pxp, + proc_data->lut_sels, 1); +} + +/* + * wfe a processing + * use wfe a to process an update + * x,y,width,height: + * coordinate and size of the update region + * wb: + * working buffer, 16bpp + * upd: + * update buffer, in Y4 with or without alpha, 8bpp + * twb: + * temp working buffer, 16bpp + * only used when reagl_en is 1 + * y4c: + * y4c buffer, {Y4[3:0],3'b000,collision}, 8bpp + * lut: + * valid value 0-63 + * set to the lut used for next update + * partial: + * 0 - full update + * 1 - partial update + * reagl_en: + * 0 - use normal waveform algorithm + * 1 - enable reagl/-d waveform algorithm + * detection_only: + * 0 - write working buffer + * 1 - do no write working buffer, detection only + * alpha_en: + * 0 - upd is {Y4[3:0],4'b0000} format + * 1 - upd is {Y4[3:0],3'b000,alpha} format + */ +static void pxp_wfe_a_process(struct pxps *pxp) +{ + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &config_data->proc_data; + struct pxp_layer_param *fetch_ch0 = &config_data->wfe_a_fetch_param[0]; + struct pxp_layer_param *fetch_ch1 = &config_data->wfe_a_fetch_param[1]; + struct pxp_layer_param *store_ch0 = &config_data->wfe_a_store_param[0]; + struct pxp_layer_param *store_ch1 = &config_data->wfe_a_store_param[1]; + int v; + + if (fetch_ch0->width != fetch_ch1->width || + fetch_ch0->height != fetch_ch1->height) { + dev_err(pxp->dev, "width/height should be same for two fetch " + "channels\n"); + } + + print_param(fetch_ch0, "wfe_a fetch_ch0"); + print_param(fetch_ch1, "wfe_a fetch_ch1"); + print_param(store_ch0, "wfe_a store_ch0"); + print_param(store_ch1, "wfe_a store_ch1"); + + /* Fetch */ + __raw_writel(fetch_ch0->paddr, pxp->base + HW_PXP_WFA_FETCH_BUF1_ADDR); + + __raw_writel(BF_PXP_WFA_FETCH_BUF1_CORD_YCORD(fetch_ch0->top) | + BF_PXP_WFA_FETCH_BUF1_CORD_XCORD(fetch_ch0->left), + pxp->base + HW_PXP_WFA_FETCH_BUF1_CORD); + + __raw_writel(fetch_ch0->stride, pxp->base + HW_PXP_WFA_FETCH_BUF1_PITCH); + + __raw_writel(BF_PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT(fetch_ch0->height - 1) | + BF_PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH(fetch_ch0->width - 1), + pxp->base + HW_PXP_WFA_FETCH_BUF1_SIZE); + + __raw_writel(fetch_ch1->paddr, pxp->base + HW_PXP_WFA_FETCH_BUF2_ADDR); + + __raw_writel(BF_PXP_WFA_FETCH_BUF2_CORD_YCORD(fetch_ch1->top) | + BF_PXP_WFA_FETCH_BUF2_CORD_XCORD(fetch_ch1->left), + pxp->base + HW_PXP_WFA_FETCH_BUF2_CORD); + + __raw_writel(fetch_ch1->stride * 2, pxp->base + HW_PXP_WFA_FETCH_BUF2_PITCH); + + __raw_writel(BF_PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT(fetch_ch1->height - 1) | + BF_PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH(fetch_ch1->width - 1), + pxp->base + HW_PXP_WFA_FETCH_BUF2_SIZE); + + /* Store */ + __raw_writel(BF_PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH(store_ch0->width - 1) | + BF_PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT(store_ch0->height - 1), + pxp->base + HW_PXP_WFE_A_STORE_SIZE_CH0); + + + __raw_writel(BF_PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH(store_ch1->width - 1) | + BF_PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT(store_ch1->height - 1), + pxp->base + HW_PXP_WFE_A_STORE_SIZE_CH1); + + __raw_writel(BF_PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH(store_ch0->stride) | + BF_PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH(store_ch1->stride * 2), + pxp->base + HW_PXP_WFE_A_STORE_PITCH); + + __raw_writel(BF_PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(store_ch0->paddr), + pxp->base + HW_PXP_WFE_A_STORE_ADDR_0_CH0); + __raw_writel(BF_PXP_WFE_A_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_WFE_A_STORE_ADDR_1_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0( + store_ch1->paddr + (store_ch1->left + store_ch1->top * + store_ch1->stride) * 2), + pxp->base + HW_PXP_WFE_A_STORE_ADDR_0_CH1); + + __raw_writel(BF_PXP_WFE_A_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_WFE_A_STORE_ADDR_1_CH1); + + /* ALU */ + __raw_writel(BF_PXP_ALU_A_BUF_SIZE_BUF_WIDTH(fetch_ch0->width) | + BF_PXP_ALU_A_BUF_SIZE_BUF_HEIGHT(fetch_ch0->height), + pxp->base + HW_PXP_ALU_A_BUF_SIZE); + + /* WFE */ + __raw_writel(BF_PXP_WFE_A_DIMENSIONS_WIDTH(fetch_ch0->width) | + BF_PXP_WFE_A_DIMENSIONS_HEIGHT(fetch_ch0->height), + pxp->base + HW_PXP_WFE_A_DIMENSIONS); + + /* Here it should be fetch_ch1 */ + __raw_writel(BF_PXP_WFE_A_OFFSET_X_OFFSET(fetch_ch1->left) | + BF_PXP_WFE_A_OFFSET_Y_OFFSET(fetch_ch1->top), + pxp->base + HW_PXP_WFE_A_OFFSET); + + __raw_writel((proc_data->lut & 0x000000FF) | 0x00000F00, + pxp->base + HW_PXP_WFE_A_SW_DATA_REGS); + __raw_writel((proc_data->partial_update | (proc_data->reagl_en << 1)), + pxp->base + HW_PXP_WFE_A_SW_FLAG_REGS); + + __raw_writel( + BF_PXP_WFE_A_CTRL_ENABLE(1) | + BF_PXP_WFE_A_CTRL_SW_RESET(1), + pxp->base + HW_PXP_WFE_A_CTRL); + + if (proc_data->alpha_en) { + __raw_writel(BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS(0), + pxp->base + HW_PXP_WFA_ARRAY_FLAG0_MASK); + } else { + __raw_writel(BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL(2) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS(0), + pxp->base + HW_PXP_WFA_ARRAY_FLAG0_MASK); + } + + /* disable CH1 when only doing detection */ + v = __raw_readl(pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH1); + if (proc_data->detection_only) { + v &= ~BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1); + printk(KERN_EMERG "%s: detection only happens\n", __func__); + } else + v |= BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1); + __raw_writel(v, pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH1); +} + +static void pxp_wfe_a_process_v3p(struct pxps *pxp) +{ + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &config_data->proc_data; + struct pxp_layer_param *fetch_ch0 = &config_data->wfe_a_fetch_param[0]; + struct pxp_layer_param *fetch_ch1 = &config_data->wfe_a_fetch_param[1]; + struct pxp_layer_param *store_ch0 = &config_data->wfe_a_store_param[0]; + struct pxp_layer_param *store_ch1 = &config_data->wfe_a_store_param[1]; + int v; + + if (fetch_ch0->width != fetch_ch1->width || + fetch_ch0->height != fetch_ch1->height) { + dev_err(pxp->dev, "width/height should be same for two fetch " + "channels\n"); + } + + print_param(fetch_ch0, "wfe_a fetch_ch0"); + print_param(fetch_ch1, "wfe_a fetch_ch1"); + print_param(store_ch0, "wfe_a store_ch0"); + print_param(store_ch1, "wfe_a store_ch1"); + + /* Fetch */ + __raw_writel(fetch_ch0->paddr, pxp->base + HW_PXP_WFB_FETCH_BUF1_ADDR); + + __raw_writel(BF_PXP_WFB_FETCH_BUF1_CORD_YCORD(fetch_ch0->top) | + BF_PXP_WFB_FETCH_BUF1_CORD_XCORD(fetch_ch0->left), + pxp->base + HW_PXP_WFB_FETCH_BUF1_CORD); + + __raw_writel(fetch_ch0->stride, pxp->base + HW_PXP_WFB_FETCH_BUF1_PITCH); + + __raw_writel(BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT(fetch_ch0->height - 1) | + BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH(fetch_ch0->width - 1), + pxp->base + HW_PXP_WFB_FETCH_BUF1_SIZE); + + __raw_writel(fetch_ch1->paddr, pxp->base + HW_PXP_WFB_FETCH_BUF2_ADDR); + + __raw_writel(BF_PXP_WFB_FETCH_BUF2_CORD_YCORD(fetch_ch1->top) | + BF_PXP_WFB_FETCH_BUF2_CORD_XCORD(fetch_ch1->left), + pxp->base + HW_PXP_WFB_FETCH_BUF2_CORD); + + __raw_writel(fetch_ch1->stride * 2, pxp->base + HW_PXP_WFB_FETCH_BUF2_PITCH); + + __raw_writel(BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT(fetch_ch1->height - 1) | + BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH(fetch_ch1->width - 1), + pxp->base + HW_PXP_WFB_FETCH_BUF2_SIZE); + + /* Store */ + __raw_writel(BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH(store_ch0->width - 1) | + BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT(store_ch0->height - 1), + pxp->base + HW_PXP_WFE_B_STORE_SIZE_CH0); + + + __raw_writel(BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH(store_ch1->width - 1) | + BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT(store_ch1->height - 1), + pxp->base + HW_PXP_WFE_B_STORE_SIZE_CH1); + + __raw_writel(BF_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH(store_ch0->stride) | + BF_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH(store_ch1->stride * 2), + pxp->base + HW_PXP_WFE_B_STORE_PITCH); + + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(store_ch0->paddr), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_0_CH0); + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_1_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0( + store_ch1->paddr + (store_ch1->left + store_ch1->top * + store_ch1->stride) * 2), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_0_CH1); + + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_1_CH1); + + /* ALU */ + __raw_writel(BF_PXP_ALU_B_BUF_SIZE_BUF_WIDTH(fetch_ch0->width) | + BF_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT(fetch_ch0->height), + pxp->base + HW_PXP_ALU_B_BUF_SIZE); + + /* WFE */ + __raw_writel(BF_PXP_WFE_B_DIMENSIONS_WIDTH(fetch_ch0->width) | + BF_PXP_WFE_B_DIMENSIONS_HEIGHT(fetch_ch0->height), + pxp->base + HW_PXP_WFE_B_DIMENSIONS); + + /* Here it should be fetch_ch1 */ + __raw_writel(BF_PXP_WFE_B_OFFSET_X_OFFSET(fetch_ch1->left) | + BF_PXP_WFE_B_OFFSET_Y_OFFSET(fetch_ch1->top), + pxp->base + HW_PXP_WFE_B_OFFSET); + + __raw_writel((proc_data->lut & 0x000000FF) | 0x00000F00, + pxp->base + HW_PXP_WFE_B_SW_DATA_REGS); + __raw_writel((proc_data->partial_update | (proc_data->reagl_en << 1)), + pxp->base + HW_PXP_WFE_B_SW_FLAG_REGS); + + __raw_writel( + BF_PXP_WFE_B_CTRL_ENABLE(1) | + BF_PXP_WFE_B_CTRL_SW_RESET(1), + pxp->base + HW_PXP_WFE_B_CTRL); + + if (proc_data->alpha_en) { + __raw_writel(BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS(0), + pxp->base + HW_PXP_WFB_ARRAY_FLAG0_MASK); + } else { + __raw_writel(BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL(2) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS(0), + pxp->base + HW_PXP_WFB_ARRAY_FLAG0_MASK); + } + + /* disable CH1 when only doing detection */ + v = __raw_readl(pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH1); + if (proc_data->detection_only) { + v &= ~BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(1); + printk(KERN_EMERG "%s: detection only happens\n", __func__); + } else + v |= BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(1); + __raw_writel(v, pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH1); +} + +/* + * wfe b configuration + * + * configure wfe b engnine for reagl/-d waveform processing + */ +static void pxp_wfe_b_configure(struct pxps *pxp) +{ + /* Fetch */ + __raw_writel( + BF_PXP_WFB_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFB_FETCH_CTRL); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL0_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS(10) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS(15), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL1_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS(2) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL2_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL3_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X(1) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X(1) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL4_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X(1) | + BF_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL5_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y(1) | + BF_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y(1) | + BF_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL6_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y(1) | + BF_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL7_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS(8) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS(8), + pxp->base + HW_PXP_WFB_ARRAY_FLAG0_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG1_MASK_H_OFS(9) | + BF_PXP_WFB_ARRAY_FLAG1_MASK_L_OFS(9), + pxp->base + HW_PXP_WFB_ARRAY_FLAG1_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X(1) | + BF_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X(1) | + BF_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG2_MASK_H_OFS(8) | + BF_PXP_WFB_ARRAY_FLAG2_MASK_L_OFS(8), + pxp->base + HW_PXP_WFB_ARRAY_FLAG2_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X(1) | + BF_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X(1) | + BF_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG3_MASK_H_OFS(9) | + BF_PXP_WFB_ARRAY_FLAG3_MASK_L_OFS(9), + pxp->base + HW_PXP_WFB_ARRAY_FLAG3_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X(1) | + BF_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG4_MASK_H_OFS(8) | + BF_PXP_WFB_ARRAY_FLAG4_MASK_L_OFS(8), + pxp->base + HW_PXP_WFB_ARRAY_FLAG4_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X(1) | + BF_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG5_MASK_H_OFS(9) | + BF_PXP_WFB_ARRAY_FLAG5_MASK_L_OFS(9), + pxp->base + HW_PXP_WFB_ARRAY_FLAG5_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y(1) | + BF_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y(1) | + BF_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG6_MASK_H_OFS(8) | + BF_PXP_WFB_ARRAY_FLAG6_MASK_L_OFS(8), + pxp->base + HW_PXP_WFB_ARRAY_FLAG6_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y(1) | + BF_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y(1) | + BF_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG7_MASK_H_OFS(9) | + BF_PXP_WFB_ARRAY_FLAG7_MASK_L_OFS(9), + pxp->base + HW_PXP_WFB_ARRAY_FLAG7_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y(1) | + BF_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG8_MASK_H_OFS(8) | + BF_PXP_WFB_ARRAY_FLAG8_MASK_L_OFS(8), + pxp->base + HW_PXP_WFB_ARRAY_FLAG8_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y(1) | + BF_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG9_MASK_H_OFS(9) | + BF_PXP_WFB_ARRAY_FLAG9_MASK_L_OFS(9), + pxp->base + HW_PXP_WFB_ARRAY_FLAG9_MASK); + + pxp_sram_init(pxp, WFE_B, (u32)active_matrix_data_8x8, 64); + + /* Store */ + __raw_writel( + BF_PXP_WFE_B_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES(32)| + BF_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL(1) | + BF_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL(1)| + BF_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES(32), + pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(1)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(0), + pxp->base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(1)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(0), + pxp->base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1); + + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_1_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(0), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_0_CH1); + + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_1_CH1); + + __raw_writel(BF_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0(0), + pxp->base + HW_PXP_WFE_B_STORE_FILL_DATA_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(0x00000000), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK0_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0xff), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK0_L_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0x3f00), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_L_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(0), + pxp->base + HW_PXP_WFE_B_STORE_D_SHIFT_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(2)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(6)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(0), + pxp->base + HW_PXP_WFE_B_STORE_D_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(8)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(0), + pxp->base + HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4(0)| + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5(0)| + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6(0)| + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7(0), + pxp->base + HW_PXP_WFE_B_STORE_F_MASK_H_CH0); + + /* ALU */ + __raw_writel(BF_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR(0), + pxp->base + HW_PXP_ALU_B_INST_ENTRY); + + __raw_writel(BF_PXP_ALU_B_PARAM_PARAM0(0) | + BF_PXP_ALU_B_PARAM_PARAM1(0), + pxp->base + HW_PXP_ALU_B_PARAM); + + __raw_writel(BF_PXP_ALU_B_CONFIG_BUF_ADDR(0), + pxp->base + HW_PXP_ALU_B_CONFIG); + + __raw_writel(BF_PXP_ALU_B_LUT_CONFIG_MODE(0) | + BF_PXP_ALU_B_LUT_CONFIG_EN(0), + pxp->base + HW_PXP_ALU_B_LUT_CONFIG); + + __raw_writel(BF_PXP_ALU_B_LUT_DATA0_LUT_DATA_L(0), + pxp->base + HW_PXP_ALU_B_LUT_DATA0); + + __raw_writel(BF_PXP_ALU_B_LUT_DATA1_LUT_DATA_H(0), + pxp->base + HW_PXP_ALU_B_LUT_DATA1); + + __raw_writel( + BF_PXP_ALU_B_CTRL_BYPASS (1) | + BF_PXP_ALU_B_CTRL_ENABLE (1) | + BF_PXP_ALU_B_CTRL_START (0) | + BF_PXP_ALU_B_CTRL_SW_RESET (0), + pxp->base + HW_PXP_ALU_B_CTRL); + + /* WFE */ + __raw_writel(0x00000402, pxp->base + HW_PXP_WFE_B_SW_DATA_REGS); + + __raw_writel(0x02040608, pxp->base + HW_PXP_WFE_B_STAGE1_MUX0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX4); + __raw_writel(0x03000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX5); + __raw_writel(0x050A040A, pxp->base + HW_PXP_WFE_B_STAGE1_MUX6); + __raw_writel(0x070A060A, pxp->base + HW_PXP_WFE_B_STAGE1_MUX7); + __raw_writel(0x0000000A, pxp->base + HW_PXP_WFE_B_STAGE1_MUX8); + + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX4); + __raw_writel(0x1C1E2022, pxp->base + HW_PXP_WFE_B_STAGE2_MUX5); + __raw_writel(0x1215181A, pxp->base + HW_PXP_WFE_B_STAGE2_MUX6); + __raw_writel(0x00000C0F, pxp->base + HW_PXP_WFE_B_STAGE2_MUX7); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX8); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX9); + __raw_writel(0x01000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX10); + __raw_writel(0x000C010B, pxp->base + HW_PXP_WFE_B_STAGE2_MUX11); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX12); + + __raw_writel(0x09000C01, pxp->base + HW_PXP_WFE_B_STAGE3_MUX0); + __raw_writel(0x003A2A1D, pxp->base + HW_PXP_WFE_B_STAGE3_MUX1); + __raw_writel(0x09000C01, pxp->base + HW_PXP_WFE_B_STAGE3_MUX2); + __raw_writel(0x003A2A1D, pxp->base + HW_PXP_WFE_B_STAGE3_MUX3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX7); + __raw_writel(0x07060504, pxp->base + HW_PXP_WFE_B_STAGE3_MUX8); + __raw_writel(0x00000008, pxp->base + HW_PXP_WFE_B_STAGE3_MUX9); + __raw_writel(0x00001211, pxp->base + HW_PXP_WFE_B_STAGE3_MUX10); + + __raw_writel(0x02010100, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_0); + __raw_writel(0x03020201, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_1); + __raw_writel(0x03020201, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_2); + __raw_writel(0x04030302, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_7); + + __raw_writel(0x02010100, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_0); + __raw_writel(0x03020201, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_1); + __raw_writel(0x03020201, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_2); + __raw_writel(0x04030302, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_7); + + __raw_writel(0x0000000F, pxp->base + HW_PXP_WFE_B_STAGE1_5X8_MASKS_0); + + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X1_OUT0); + __raw_writel(0x0000000F, pxp->base + HW_PXP_WFE_B_STG1_5X1_MASKS); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STAGE2_5X6_MASKS_0); + __raw_writel(0x3F3F3F3F, pxp->base + HW_PXP_WFE_B_STAGE2_5X6_ADDR_0); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_7); + + __raw_writel(0x00008000, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT0); + __raw_writel(0x0000FFFE, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT3); + __raw_writel(0x00000F0F, pxp->base + HW_PXP_WFE_B_STG2_5X1_MASKS); + + __raw_writel(0x00007F7F, pxp->base + HW_PXP_WFE_B_STG3_F8X1_MASKS); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_0); + __raw_writel(0x00FF00FF, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_2); + __raw_writel(0x000000FF, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_0); + __raw_writel(0xFF3FFF3F, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_2); + __raw_writel(0xFFFFFF1F, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_7); + + __raw_writel( + BF_PXP_WFE_B_CTRL_ENABLE(1) | + BF_PXP_WFE_B_CTRL_SW_RESET(1), + pxp->base + HW_PXP_WFE_B_CTRL); +} + +/* wfe b processing + * use wfe b to process an update + * call this function only after pxp_wfe_a_processing + * x,y,width,height: + * coordinate and size of the update region + * twb: + * temp working buffer, 16bpp + * only used when reagl_en is 1 + * wb: + * working buffer, 16bpp + * lut: + * lut buffer, 8bpp + * lut_update: + * 0 - wfe_b is used for reagl/reagl-d operation + * 1 - wfe_b is used for lut update operation + * reagl_d_en: + * 0 - use reagl waveform algorithm + * 1 - use reagl/-d waveform algorithm + */ +static void pxp_wfe_b_process(struct pxps *pxp) +{ + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &config_data->proc_data; + struct pxp_layer_param *fetch_ch0 = &config_data->wfe_b_fetch_param[0]; + struct pxp_layer_param *fetch_ch1 = &config_data->wfe_b_fetch_param[1]; + struct pxp_layer_param *store_ch0 = &config_data->wfe_b_store_param[0]; + struct pxp_layer_param *store_ch1 = &config_data->wfe_b_store_param[1]; + static int comp_mask; + /* Fetch */ + + print_param(fetch_ch0, "wfe_b fetch_ch0"); + print_param(fetch_ch1, "wfe_b fetch_ch1"); + print_param(store_ch0, "wfe_b store_ch0"); + print_param(store_ch1, "wfe_b store_ch1"); + + __raw_writel(fetch_ch0->paddr, pxp->base + HW_PXP_WFB_FETCH_BUF1_ADDR); + + __raw_writel( + BF_PXP_WFB_FETCH_BUF1_CORD_YCORD(fetch_ch0->top) | + BF_PXP_WFB_FETCH_BUF1_CORD_XCORD(fetch_ch0->left), + pxp->base + HW_PXP_WFB_FETCH_BUF1_CORD); + + __raw_writel(fetch_ch0->stride, + pxp->base + HW_PXP_WFB_FETCH_BUF1_PITCH); + + __raw_writel( + BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT(fetch_ch0->height-1) | + BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH(fetch_ch0->width-1), + pxp->base + HW_PXP_WFB_FETCH_BUF1_SIZE); + + __raw_writel(fetch_ch1->paddr, pxp->base + HW_PXP_WFB_FETCH_BUF2_ADDR); + + __raw_writel(fetch_ch1->stride * 2, + pxp->base + HW_PXP_WFB_FETCH_BUF2_PITCH); + + __raw_writel( + BF_PXP_WFB_FETCH_BUF2_CORD_YCORD(fetch_ch1->top) | + BF_PXP_WFB_FETCH_BUF2_CORD_XCORD(fetch_ch1->left), + pxp->base + HW_PXP_WFB_FETCH_BUF2_CORD); + + __raw_writel( + BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT(fetch_ch1->height-1) | + BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH(fetch_ch1->width-1), + pxp->base + HW_PXP_WFB_FETCH_BUF2_SIZE); + + if (!proc_data->lut_update) { + __raw_writel( + BF_PXP_WFB_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFB_FETCH_CTRL); + } else { + __raw_writel( + BF_PXP_WFB_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFB_FETCH_CTRL); + } + +#ifdef CONFIG_REAGLD_ALGO_CHECK + __raw_writel( + (__raw_readl(pxp->base + HW_PXP_WFE_B_SW_DATA_REGS) & 0x0000FFFF) | ((fetch_ch0->comp_mask&0x000000FF)<<16), + pxp->base + HW_PXP_WFE_B_SW_DATA_REGS); +#else + __raw_writel( + (__raw_readl(pxp->base + HW_PXP_WFE_B_SW_DATA_REGS) & 0x0000FFFF) | ((comp_mask&0x000000FF)<<16), + pxp->base + HW_PXP_WFE_B_SW_DATA_REGS); + + /* comp_mask only need to be updated upon REAGL-D, 0,1,...7, 0,1,... */ + if (proc_data->reagl_d_en) { + comp_mask++; + if (comp_mask>7) + comp_mask = 0; + } +#endif + + /* Store */ + __raw_writel( + BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH(store_ch0->width-1)| + BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT(store_ch0->height-1), + pxp->base + HW_PXP_WFE_B_STORE_SIZE_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH(store_ch1->width-1)| + BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT(store_ch1->height-1), + pxp->base + HW_PXP_WFE_B_STORE_SIZE_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH(store_ch0->stride * 2)| + BF_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH(store_ch1->stride * 2), + pxp->base + HW_PXP_WFE_B_STORE_PITCH); + + __raw_writel( + BF_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(store_ch0->paddr + + (store_ch0->left + store_ch0->top * store_ch0->stride) * 2), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_0_CH0); + + if (proc_data->lut_update) { + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x3f0000), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0(0x30)| + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1(0)| + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2(0)| + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3(0), + pxp->base + HW_PXP_WFE_B_STORE_F_MASK_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(4)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(0), + pxp->base + HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0); + } else { + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0x3f00), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0(3)| + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1(0)| + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2(0)| + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3(0), + pxp->base + HW_PXP_WFE_B_STORE_F_MASK_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(8)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(0), + pxp->base + HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0); + } + + /* ALU */ + __raw_writel( + BF_PXP_ALU_B_BUF_SIZE_BUF_WIDTH(fetch_ch0->width) | + BF_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT(fetch_ch0->height), + pxp->base + HW_PXP_ALU_B_BUF_SIZE); + + /* WFE */ + __raw_writel( + BF_PXP_WFE_B_DIMENSIONS_WIDTH(fetch_ch0->width) | + BF_PXP_WFE_B_DIMENSIONS_HEIGHT(fetch_ch0->height), + pxp->base + HW_PXP_WFE_B_DIMENSIONS); + + __raw_writel( /*TODO check*/ + BF_PXP_WFE_B_OFFSET_X_OFFSET(fetch_ch0->left) | + BF_PXP_WFE_B_OFFSET_Y_OFFSET(fetch_ch0->top), + pxp->base + HW_PXP_WFE_B_OFFSET); + + __raw_writel(proc_data->reagl_d_en, pxp->base + HW_PXP_WFE_B_SW_FLAG_REGS); +} + +void pxp_fill( + u32 bpp, + u32 value, + u32 width, + u32 height, + u32 output_buffer, + u32 output_pitch) +{ + u32 active_bpp; + u32 pitch; + + if (bpp == 8) { + active_bpp = 0; + pitch = output_pitch; + } else if(bpp == 16) { + active_bpp = 1; + pitch = output_pitch * 2; + } else { + active_bpp = 2; + pitch = output_pitch * 4; + } + + __raw_writel( + BF_PXP_WFE_B_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES(32)| + BF_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL(0) | + BF_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN(0), + pxp_reg_base + HW_PXP_WFE_B_STORE_CTRL_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES(16), + pxp_reg_base + HW_PXP_WFE_B_STORE_CTRL_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH(width-1)| + BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT(height-1), + pxp_reg_base + HW_PXP_WFE_B_STORE_SIZE_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH(width-1)| + BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT(height-1), + pxp_reg_base + HW_PXP_WFE_B_STORE_SIZE_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH(pitch)| + BF_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH(pitch), + pxp_reg_base + HW_PXP_WFE_B_STORE_PITCH); + + __raw_writel( + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(active_bpp)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(1), + pxp_reg_base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(active_bpp)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(0), + pxp_reg_base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(output_buffer), + pxp_reg_base + HW_PXP_WFE_B_STORE_ADDR_0_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(0), + pxp_reg_base + HW_PXP_WFE_B_STORE_ADDR_1_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(output_buffer), + pxp_reg_base + HW_PXP_WFE_B_STORE_ADDR_0_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(0), + pxp_reg_base + HW_PXP_WFE_B_STORE_ADDR_1_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0(value), + pxp_reg_base + HW_PXP_WFE_B_STORE_FILL_DATA_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(0x00000000), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK0_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0x000000ff), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK0_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x00000000), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK1_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0x000000ff), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK1_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x00000000), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK2_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x000000ff), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK2_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(32)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(40)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(1)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(0), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_CTRL2_ENABLE (1) | + BF_PXP_CTRL2_ROTATE0 (0) | + BF_PXP_CTRL2_HFLIP0 (0) | + BF_PXP_CTRL2_VFLIP0 (0) | + BF_PXP_CTRL2_ROTATE1 (0) | + BF_PXP_CTRL2_HFLIP1 (0) | + BF_PXP_CTRL2_VFLIP1 (0) | + BF_PXP_CTRL2_ENABLE_DITHER (0) | + BF_PXP_CTRL2_ENABLE_WFE_A (0) | + BF_PXP_CTRL2_ENABLE_WFE_B (1) | + BF_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE (0) | + BF_PXP_CTRL2_ENABLE_ALPHA_B (0) | + BF_PXP_CTRL2_BLOCK_SIZE (0) | + BF_PXP_CTRL2_ENABLE_CSC2 (0) | + BF_PXP_CTRL2_ENABLE_LUT (0) | + BF_PXP_CTRL2_ENABLE_ROTATE0 (0) | + BF_PXP_CTRL2_ENABLE_ROTATE1 (0), + pxp_reg_base + HW_PXP_CTRL2); + + if (busy_wait(BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ & + __raw_readl(pxp_reg_base + HW_PXP_IRQ)) == false) + printk("%s: wait for completion timeout\n", __func__); +} +EXPORT_SYMBOL(pxp_fill); + +static void pxp_lut_cleanup_multiple(struct pxps *pxp, u64 lut, bool set) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + + if (proc_data->lut_cleanup == 1) { + if (set) { + __raw_writel((u32)lut, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_0 + 0x4); + __raw_writel((u32)(lut>>32), pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_1 + 0x4); + } else { + pxp_luts_deactivate(pxp, lut); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_1); + } + } +} + +static void pxp_lut_cleanup_multiple_v3p(struct pxps *pxp, u64 lut, bool set) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + + if (proc_data->lut_cleanup == 1) { + if (set) { + __raw_writel((u32)lut, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_0 + 0x4); + __raw_writel((u32)(lut>>32), pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_1 + 0x4); + } else { + pxp_luts_deactivate(pxp, lut); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_1); + } + } +} + +#ifdef CONFIG_MXC_FPGA_M4_TEST +void m4_process(void) +{ + __raw_writel(0x7, pinctrl_base + PIN_DOUT); /* M4 Start */ + + while (!(__raw_readl(pxp_reg_base + HW_PXP_HANDSHAKE_CPU_STORE) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY)); + + __raw_writel(0x3, pinctrl_base + PIN_DOUT); /* M4 Stop */ + + +} +#else +void m4_process(void) {} +#endif +EXPORT_SYMBOL(m4_process); + +static void pxp_lut_status_set(struct pxps *pxp, unsigned int lut) +{ + if(lut<32) + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_0) | (1 << lut), + pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_0); + else { + lut = lut -32; + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_1) | (1 << lut), + pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_1); + } +} + +static void pxp_lut_status_set_v3p(struct pxps *pxp, unsigned int lut) +{ + if(lut<32) + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_0) | (1 << lut), + pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_0); + else { + lut = lut -32; + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_1) | (1 << lut), + pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_1); + } +} + +static void pxp_luts_activate(struct pxps *pxp, u64 lut_status) +{ + int i = 0; + + if (!lut_status) + return; + + for (i = 0; i < 64; i++) { + if (lut_status & (1ULL << i)) + if (pxp->devdata && pxp->devdata->pxp_lut_status_set) + pxp->devdata->pxp_lut_status_set(pxp, i); + } +} + +static void pxp_lut_status_clr(unsigned int lut) +{ + if(lut<32) + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_0) & (~(1 << lut)), + pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_0); + else + { + lut = lut -32; + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_1) & (~(1 << lut)), + pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_1); + } +} + +static void pxp_lut_status_clr_v3p(unsigned int lut) +{ + if(lut<32) + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_0) & (~(1 << lut)), + pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_0); + else + { + lut = lut -32; + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_1) & (~(1 << lut)), + pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_1); + } +} + +/* this function should be called in the epdc + * driver explicitly when some epdc lut becomes + * idle. So it should be exported. + */ +static void pxp_luts_deactivate(struct pxps *pxp, u64 lut_status) +{ + int i = 0; + + if (!lut_status) + return; + + for (i = 0; i < 64; i++) { + if (lut_status & (1ULL << i)) + if (pxp->devdata && pxp->devdata->pxp_lut_status_clr) + pxp->devdata->pxp_lut_status_clr(i); + } +} + +/* use histogram_B engine to calculate histogram status */ +static void pxp_histogram_enable(struct pxps *pxp, + unsigned int width, + unsigned int height) +{ + u32 val = 0; + + __raw_writel( + BF_PXP_HIST_B_BUF_SIZE_HEIGHT(height)| + BF_PXP_HIST_B_BUF_SIZE_WIDTH(width), + pxp->base + HW_PXP_HIST_B_BUF_SIZE); + + if (pxp_is_v3(pxp)) + val = 64; + else if (pxp_is_v3p(pxp)) + val = 64 + 4; + + __raw_writel( + BF_PXP_HIST_B_MASK_MASK_EN(1)| + BF_PXP_HIST_B_MASK_MASK_MODE(0)| + BF_PXP_HIST_B_MASK_MASK_OFFSET(val)| + BF_PXP_HIST_B_MASK_MASK_WIDTH(0)| + BF_PXP_HIST_B_MASK_MASK_VALUE0(1) | + BF_PXP_HIST_B_MASK_MASK_VALUE1(0), + pxp->base + HW_PXP_HIST_B_MASK); + + __raw_writel( + BF_PXP_HIST_B_CTRL_PIXEL_WIDTH(3)| + BF_PXP_HIST_B_CTRL_PIXEL_OFFSET(8)| + BF_PXP_HIST_B_CTRL_CLEAR(0)| + BF_PXP_HIST_B_CTRL_ENABLE(1), + pxp->base + HW_PXP_HIST_B_CTRL); +} + +static void pxp_histogram_status_report(struct pxps *pxp, u32 *hist_status) +{ + BUG_ON(!hist_status); + + *hist_status = (__raw_readl(pxp->base + HW_PXP_HIST_B_CTRL) & BM_PXP_HIST_B_CTRL_STATUS) + >> BP_PXP_HIST_B_CTRL_STATUS; + dev_dbg(pxp->dev, "%d pixels are used to calculate histogram status %d\n", + __raw_readl(pxp->base + HW_PXP_HIST_B_TOTAL_PIXEL), *hist_status); +} + +static void pxp_histogram_disable(struct pxps *pxp) +{ + __raw_writel( + BF_PXP_HIST_B_CTRL_PIXEL_WIDTH(3)| + BF_PXP_HIST_B_CTRL_PIXEL_OFFSET(4)| + BF_PXP_HIST_B_CTRL_CLEAR(1)| + BF_PXP_HIST_B_CTRL_ENABLE(0), + pxp->base + HW_PXP_HIST_B_CTRL); +} + +/* the collision detection function will be + * called by epdc driver when required + */ +static void pxp_collision_detection_enable(struct pxps *pxp, + unsigned int width, + unsigned int height) +{ + u32 val = 0; + + __raw_writel( + BF_PXP_HIST_A_BUF_SIZE_HEIGHT(height)| + BF_PXP_HIST_A_BUF_SIZE_WIDTH(width), + pxp_reg_base + HW_PXP_HIST_A_BUF_SIZE); + + if (pxp_is_v3(pxp)) + val = 65; + else if (pxp_is_v3p(pxp)) + val = 65 + 4; + + __raw_writel( + BF_PXP_HIST_A_MASK_MASK_EN(1)| + BF_PXP_HIST_A_MASK_MASK_MODE(0)| + BF_PXP_HIST_A_MASK_MASK_OFFSET(val)| + BF_PXP_HIST_A_MASK_MASK_WIDTH(0)| + BF_PXP_HIST_A_MASK_MASK_VALUE0(1) | + BF_PXP_HIST_A_MASK_MASK_VALUE1(0), + pxp_reg_base + HW_PXP_HIST_A_MASK); + + __raw_writel( + BF_PXP_HIST_A_CTRL_PIXEL_WIDTH(6)| + BF_PXP_HIST_A_CTRL_PIXEL_OFFSET(24)| + BF_PXP_HIST_A_CTRL_CLEAR(0)| + BF_PXP_HIST_A_CTRL_ENABLE(1), + pxp_reg_base + HW_PXP_HIST_A_CTRL); +} + +static void pxp_collision_detection_disable(struct pxps *pxp) +{ + __raw_writel( + BF_PXP_HIST_A_CTRL_PIXEL_WIDTH(6)| + BF_PXP_HIST_A_CTRL_PIXEL_OFFSET(24)| + BF_PXP_HIST_A_CTRL_CLEAR(1)| + BF_PXP_HIST_A_CTRL_ENABLE(0), + pxp_reg_base + HW_PXP_HIST_A_CTRL); +} + +/* this function can be called in the epdc callback + * function in the pxp_irq() to let the epdc know + * the collision information for the previous working + * buffer update. + */ +static bool pxp_collision_status_report(struct pxps *pxp, struct pxp_collision_info *info) +{ + unsigned int count; + + BUG_ON(!info); + memset(info, 0x0, sizeof(*info)); + + info->pixel_cnt = count = __raw_readl(pxp->base + HW_PXP_HIST_A_TOTAL_PIXEL); + if (!count) + return false; + + dev_dbg(pxp->dev, "%s: pixel_cnt = %d\n", __func__, info->pixel_cnt); + info->rect_min_x = __raw_readl(pxp->base + HW_PXP_HIST_A_ACTIVE_AREA_X) & 0xffff; + dev_dbg(pxp->dev, "%s: rect_min_x = %d\n", __func__, info->rect_min_x); + info->rect_max_x = (__raw_readl(pxp->base + HW_PXP_HIST_A_ACTIVE_AREA_X) >> 16) & 0xffff; + dev_dbg(pxp->dev, "%s: rect_max_x = %d\n", __func__, info->rect_max_x); + info->rect_min_y = __raw_readl(pxp->base + HW_PXP_HIST_A_ACTIVE_AREA_Y) & 0xffff; + dev_dbg(pxp->dev, "%s: rect_min_y = %d\n", __func__, info->rect_min_y); + info->rect_max_y = (__raw_readl(pxp->base + HW_PXP_HIST_A_ACTIVE_AREA_Y) >> 16) & 0xffff; + dev_dbg(pxp->dev, "%s: rect_max_y = %d\n", __func__, info->rect_max_y); + + info->victim_luts[0] = __raw_readl(pxp->base + HW_PXP_HIST_A_RAW_STAT0); + dev_dbg(pxp->dev, "%s: victim_luts[0] = 0x%x\n", __func__, info->victim_luts[0]); + info->victim_luts[1] = __raw_readl(pxp->base + HW_PXP_HIST_A_RAW_STAT1); + dev_dbg(pxp->dev, "%s: victim_luts[1] = 0x%x\n", __func__, info->victim_luts[1]); + + return true; +} + +void pxp_get_collision_info(struct pxp_collision_info *info) +{ + BUG_ON(!info); + + memcpy(info, &col_info, sizeof(struct pxp_collision_info)); +} +EXPORT_SYMBOL(pxp_get_collision_info); + +static void dither_prefetch_config(struct pxps *pxp) +{ + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_layer_param *fetch_ch0 = &config_data->dither_fetch_param[0]; + struct pxp_layer_param *fetch_ch1 = &config_data->dither_fetch_param[1]; + + print_param(fetch_ch0, "dither fetch_ch0"); + print_param(fetch_ch1, "dither fetch_ch1"); + __raw_writel( + BF_PXP_DITHER_FETCH_CTRL_CH0_CH_EN(1) | + BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16(0)| + BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_HFLIP(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_VFLIP(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES(32) | + BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_DITHER_FETCH_CTRL_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_CTRL_CH1_CH_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16(0)| + BF_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_HFLIP(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_VFLIP(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES(2) | + BF_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM(0), + pxp->base + HW_PXP_DITHER_FETCH_CTRL_CH1); + + __raw_writel( + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X(0) | + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y(0), + pxp->base + HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0); + __raw_writel( + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X(fetch_ch0->width - 1) | + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y(fetch_ch0->height - 1), + pxp->base + HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X(0) | + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y(0), + pxp->base + HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1); + __raw_writel( + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X(fetch_ch1->width - 1) | + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y(fetch_ch1->height - 1), + pxp->base + HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1); + __raw_writel( + BF_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH(fetch_ch0->width - 1) | + BF_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT(fetch_ch0->height - 1), + pxp->base + HW_PXP_DITHER_FETCH_SIZE_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH(fetch_ch1->width - 1) | + BF_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT(fetch_ch1->height - 1), + pxp->base + HW_PXP_DITHER_FETCH_SIZE_CH1); + + __raw_writel( + BF_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH(fetch_ch0->stride) | + BF_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH(fetch_ch1->stride), + pxp->base + HW_PXP_DITHER_FETCH_PITCH); + + __raw_writel( + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP(0) | + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT(0) | + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN(0) | + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS(1), + pxp->base + HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP(0) | + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT(0) | + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN(0) | + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS(1), + pxp->base + HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1); + + __raw_writel( + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0(0) | + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1(0) | + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2(0) | + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3(0), + pxp->base + HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0(0) | + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1(0) | + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2(0) | + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3(0), + pxp->base + HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1); + + __raw_writel( + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0(7) | + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1(7) | + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2(7) | + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3(7), + pxp->base + HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0(7) | + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1(7) | + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2(7) | + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3(7), + pxp->base + HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1); + + __raw_writel( + BF_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0(fetch_ch0->paddr), + pxp->base + HW_PXP_DITHER_FETCH_ADDR_0_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1(0), + pxp->base + HW_PXP_DITHER_FETCH_ADDR_1_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0(fetch_ch1->paddr), + pxp->base + HW_PXP_DITHER_FETCH_ADDR_0_CH1); + + __raw_writel( + BF_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1(0), + pxp->base + HW_PXP_DITHER_FETCH_ADDR_1_CH1); +} + +static void dither_store_config(struct pxps *pxp) +{ + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_layer_param *store_ch0 = &config_data->dither_store_param[0]; + struct pxp_layer_param *store_ch1 = &config_data->dither_store_param[1]; + + print_param(store_ch0, "dither store_ch0"); + print_param(store_ch1, "dither store_ch1"); + + __raw_writel( + BF_PXP_DITHER_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES(32)| + BF_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL(0) | + BF_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_DITHER_STORE_CTRL_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_CTRL_CH1_CH_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES(32), + pxp->base + HW_PXP_DITHER_STORE_CTRL_CH1); + + __raw_writel( + BF_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(store_ch0->width - 1) | + BF_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(store_ch0->height - 1), + pxp->base + HW_PXP_DITHER_STORE_SIZE_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH(store_ch1->width - 1) | + BF_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT(store_ch1->height - 1), + pxp->base + HW_PXP_DITHER_STORE_SIZE_CH1); + + __raw_writel( + BF_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH(store_ch0->stride) | + BF_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH(store_ch1->stride), + pxp->base + HW_PXP_DITHER_STORE_PITCH); + + __raw_writel( + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(0)| + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(1), + pxp->base + HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(0)| + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(0)| + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(0), + pxp->base + HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1); + + __raw_writel( + BF_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(store_ch0->paddr), + pxp->base + HW_PXP_DITHER_STORE_ADDR_0_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_DITHER_STORE_ADDR_1_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(store_ch1->paddr), + pxp->base + HW_PXP_DITHER_STORE_ADDR_0_CH1); + + __raw_writel( + BF_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_DITHER_STORE_ADDR_1_CH1); + + __raw_writel( + BF_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0(0), + pxp->base + HW_PXP_DITHER_STORE_FILL_DATA_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(0xffffff), + pxp->base + HW_PXP_DITHER_STORE_D_MASK0_H_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0x0), + pxp->base + HW_PXP_DITHER_STORE_D_MASK0_L_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), + pxp->base + HW_PXP_DITHER_STORE_D_MASK1_H_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0xff), + pxp->base + HW_PXP_DITHER_STORE_D_MASK1_L_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(32) | + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(0) | + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(32)| + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1) | + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(0)| + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(0)| + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(0)| + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(0), + pxp->base + HW_PXP_DITHER_STORE_D_SHIFT_L_CH0); +} + +static void pxp_set_final_lut_data(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + + if (proc_data->quant_bit < 2) { + pxp_sram_init(pxp, DITHER0_LUT, (u32)bit1_dither_data_8x8, 64); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA0(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA1(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA2(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA3(0x0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA0); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA4(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA5(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA6(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA7(0x0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA1); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA8(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA9(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA10(0xf0)| + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA11(0xf0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA2); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA12(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA13(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA14(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA15(0xf0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA3); + } else if (proc_data->quant_bit < 4) { + pxp_sram_init(pxp, DITHER0_LUT, (u32)bit2_dither_data_8x8, 64); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA0(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA1(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA2(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA3(0x0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA0); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA4(0x50) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA5(0x50) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA6(0x50) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA7(0x50), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA1); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA8(0xa0) | + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA9(0xa0) | + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA10(0xa0)| + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA11(0xa0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA2); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA12(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA13(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA14(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA15(0xf0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA3); + } else { + pxp_sram_init(pxp, DITHER0_LUT, (u32)bit4_dither_data_8x8, 64); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA0(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA1(0x10) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA2(0x20) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA3(0x30), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA0); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA4(0x40) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA5(0x50) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA6(0x60) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA7(0x70), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA1); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA8(0x80) | + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA9(0x90) | + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA10(0xa0)| + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA11(0xb0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA2); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA12(0xc0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA13(0xd0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA14(0xe0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA15(0xf0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA3); + } +} + +static void pxp_dithering_process(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + u32 val = 0; + + if (pxp->devdata && pxp->devdata->pxp_dithering_configure) + pxp->devdata->pxp_dithering_configure(pxp); + + if (pxp_is_v3(pxp)) + val = BF_PXP_DITHER_CTRL_ENABLE0 (1) | + BF_PXP_DITHER_CTRL_ENABLE1 (0) | + BF_PXP_DITHER_CTRL_ENABLE2 (0) | + BF_PXP_DITHER_CTRL_DITHER_MODE2 (0) | + BF_PXP_DITHER_CTRL_DITHER_MODE1 (0) | + BF_PXP_DITHER_CTRL_DITHER_MODE0(proc_data->dither_mode) | + BF_PXP_DITHER_CTRL_LUT_MODE (0) | + BF_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE (1) | + BF_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE (0) | + BF_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE (0) | + BF_PXP_DITHER_CTRL_BUSY2 (0) | + BF_PXP_DITHER_CTRL_BUSY1 (0) | + BF_PXP_DITHER_CTRL_BUSY0 (0); + else if (pxp_is_v3p(pxp)) { + if (proc_data->dither_mode != 0 && + proc_data->dither_mode != 3) { + dev_err(pxp->dev, "Not supported dithering mode. " + "Forced to be Orderred mode!\n"); + proc_data->dither_mode = 3; + } + + val = BF_PXP_DITHER_CTRL_ENABLE0 (1) | + BF_PXP_DITHER_CTRL_ENABLE1 (1) | + BF_PXP_DITHER_CTRL_ENABLE2 (1) | + BF_PXP_DITHER_CTRL_DITHER_MODE2(proc_data->dither_mode) | + BF_PXP_DITHER_CTRL_DITHER_MODE1(proc_data->dither_mode) | + BF_PXP_DITHER_CTRL_DITHER_MODE0(proc_data->dither_mode) | + BF_PXP_DITHER_CTRL_LUT_MODE (0) | + BF_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE (1) | + BF_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE (1) | + BF_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE (1) | + BF_PXP_DITHER_CTRL_FINAL_LUT_ENABLE (0) | + BF_PXP_DITHER_CTRL_BUSY2 (0) | + BF_PXP_DITHER_CTRL_BUSY1 (0) | + BF_PXP_DITHER_CTRL_BUSY0 (0); + } + __raw_writel(val, pxp->base + HW_PXP_DITHER_CTRL); + + switch(proc_data->dither_mode) { + case PXP_DITHER_PASS_THROUGH: + /* no more settings required */ + break; + case PXP_DITHER_FLOYD: + case PXP_DITHER_ATKINSON: + case PXP_DITHER_ORDERED: + if(!proc_data->quant_bit || proc_data->quant_bit > 7) { + dev_err(pxp->dev, "unsupported quantization bit number!\n"); + return; + } + __raw_writel( + BF_PXP_DITHER_CTRL_FINAL_LUT_ENABLE(1) | + BF_PXP_DITHER_CTRL_NUM_QUANT_BIT(proc_data->quant_bit), + pxp->base + HW_PXP_DITHER_CTRL_SET); + pxp_set_final_lut_data(pxp); + + break; + case PXP_DITHER_QUANT_ONLY: + if(!proc_data->quant_bit || proc_data->quant_bit > 7) { + dev_err(pxp->dev, "unsupported quantization bit number!\n"); + return; + } + __raw_writel( + BF_PXP_DITHER_CTRL_NUM_QUANT_BIT(proc_data->quant_bit), + pxp->base + HW_PXP_DITHER_CTRL_SET); + break; + default: + /* unknown mode */ + dev_err(pxp->dev, "unknown dithering mode passed!\n"); + __raw_writel(0x0, pxp->base + HW_PXP_DITHER_CTRL); + return; + } +} + +static void pxp_dithering_configure(struct pxps *pxp) +{ + dither_prefetch_config(pxp); + dither_store_config(pxp); +} + +static void pxp_dithering_configure_v3p(struct pxps *pxp) +{ + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_layer_param *fetch_ch0 = &config_data->dither_fetch_param[0]; + struct pxp_layer_param *store_ch0 = &config_data->dither_store_param[0]; + + __raw_writel(BF_PXP_CTRL_BLOCK_SIZE(BV_PXP_CTRL_BLOCK_SIZE__8X8) | + BF_PXP_CTRL_ROTATE0(BV_PXP_CTRL_ROTATE0__ROT_0) | + BM_PXP_CTRL_IRQ_ENABLE, + pxp->base + HW_PXP_CTRL); + + __raw_writel(BF_PXP_PS_CTRL_DECX(BV_PXP_PS_CTRL_DECX__DISABLE) | + BF_PXP_PS_CTRL_DECY(BV_PXP_PS_CTRL_DECY__DISABLE) | + BF_PXP_PS_CTRL_FORMAT(BV_PXP_PS_CTRL_FORMAT__Y8), + pxp->base + HW_PXP_PS_CTRL); + + __raw_writel(BF_PXP_OUT_CTRL_FORMAT(BV_PXP_OUT_CTRL_FORMAT__Y8), + pxp->base + HW_PXP_OUT_CTRL); + + __raw_writel(BF_PXP_PS_SCALE_YSCALE(4096) | + BF_PXP_PS_SCALE_XSCALE(4096), + pxp->base + HW_PXP_PS_SCALE); + + __raw_writel(store_ch0->paddr, pxp->base + HW_PXP_OUT_BUF); + + __raw_writel(store_ch0->stride, pxp->base + HW_PXP_OUT_PITCH); + + __raw_writel(BF_PXP_OUT_LRC_X(store_ch0->width - 1) | + BF_PXP_OUT_LRC_Y(store_ch0->height - 1), + pxp->base + HW_PXP_OUT_LRC); + + __raw_writel(BF_PXP_OUT_AS_ULC_X(1) | + BF_PXP_OUT_AS_ULC_Y(1), + pxp->base + HW_PXP_OUT_AS_ULC); + + __raw_writel(BF_PXP_OUT_AS_LRC_X(0) | + BF_PXP_OUT_AS_LRC_Y(0), + pxp->base + HW_PXP_OUT_AS_LRC); + + __raw_writel(BF_PXP_OUT_PS_ULC_X(0) | + BF_PXP_OUT_PS_ULC_Y(0), + pxp->base + HW_PXP_OUT_PS_ULC); + + __raw_writel(BF_PXP_OUT_PS_LRC_X(fetch_ch0->width - 1) | + BF_PXP_OUT_PS_LRC_Y(fetch_ch0->height - 1), + pxp->base + HW_PXP_OUT_PS_LRC); + + __raw_writel(fetch_ch0->paddr, pxp->base + HW_PXP_PS_BUF); + + __raw_writel(fetch_ch0->stride, pxp->base + HW_PXP_PS_PITCH); + + __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0); + + __raw_writel(BF_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(store_ch0->width-1)| + BF_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(store_ch0->height-1), + pxp->base + HW_PXP_DITHER_STORE_SIZE_CH0); + + __raw_writel(BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(1), + pxp->base + HW_PXP_DATA_PATH_CTRL0_CLR); +} + +static void pxp_start2(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + int dither_wfe_a_handshake = 0; + int wfe_a_b_handshake = 0; + int count = 0; + + int wfe_a_enable = ((proc_data->engine_enable & PXP_ENABLE_WFE_A) == PXP_ENABLE_WFE_A); + int wfe_b_enable = ((proc_data->engine_enable & PXP_ENABLE_WFE_B) == PXP_ENABLE_WFE_B); + int dither_enable = ((proc_data->engine_enable & PXP_ENABLE_DITHER) == PXP_ENABLE_DITHER); + int handshake = ((proc_data->engine_enable & PXP_ENABLE_HANDSHAKE) == PXP_ENABLE_HANDSHAKE); + int dither_bypass = ((proc_data->engine_enable & PXP_ENABLE_DITHER_BYPASS) == PXP_ENABLE_DITHER_BYPASS); + u32 val = 0; + + if (dither_enable) + count++; + if (wfe_a_enable) + count++; + if (wfe_b_enable) + count++; + + if (count == 0) + return; + if (handshake && (count == 1)) { + dev_warn(pxp->dev, "Warning: Can not use handshake mode when " + "only one sub-block is enabled!\n"); + handshake = 0; + } + + if (handshake && wfe_b_enable && (wfe_a_enable == 0)) { + dev_err(pxp->dev, "WFE_B only works when WFE_A is enabled!\n"); + return; + } + + if (handshake && dither_enable && wfe_a_enable) + dither_wfe_a_handshake = 1; + if (handshake && wfe_a_enable && wfe_b_enable) + wfe_a_b_handshake = 1; + + dev_dbg(pxp->dev, "handshake %d, dither_wfe_a_handshake %d, " + "wfe_a_b_handshake %d, dither_bypass %d\n", + handshake, + dither_wfe_a_handshake, + wfe_a_b_handshake, + dither_bypass); + + if (handshake) { + /* for handshake, we only enable the last completion INT */ + if (wfe_b_enable) + __raw_writel(0x8000, pxp->base + HW_PXP_IRQ_MASK); + else if (wfe_a_enable) + __raw_writel(0x4000, pxp->base + HW_PXP_IRQ_MASK); + + /* Dither fetch */ + __raw_writel( + BF_PXP_DITHER_FETCH_CTRL_CH0_CH_EN(1) | + BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16(0)| + BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_HFLIP(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_VFLIP(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES(32) | + BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_DITHER_FETCH_CTRL_CH0); + + if (dither_bypass) { + /* Dither store */ + __raw_writel( + BF_PXP_DITHER_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES(32)| + BF_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL(0) | + BF_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_DITHER_STORE_CTRL_CH0); + + /* WFE_A fetch */ + __raw_writel( + BF_PXP_WFA_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP(2) | + BF_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFA_FETCH_CTRL); + + } else if (dither_wfe_a_handshake) { + /* Dither store */ + __raw_writel( + BF_PXP_DITHER_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES(32)| + BF_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL(0) | + BF_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_DITHER_STORE_CTRL_CH0); + + /* WFE_A fetch */ + __raw_writel( + BF_PXP_WFA_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE(1) | + BF_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFA_FETCH_CTRL); + } + + if (wfe_a_b_handshake) { + /* WFE_A Store */ + __raw_writel( + BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES(16), + pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH1); + + /* WFE_B fetch */ + __raw_writel( + BF_PXP_WFB_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFB_FETCH_CTRL); + } else { + /* WFE_A Store */ + __raw_writel( + BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES(16), + pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH1); + } + + if (pxp_is_v3(pxp)) + val = BF_PXP_CTRL_ENABLE_WFE_A(wfe_a_enable) | + BF_PXP_CTRL_ENABLE_WFE_B(wfe_b_enable); + else if (pxp_is_v3p(pxp)) + val = BF_PXP_CTRL_ENABLE_WFE_B(wfe_a_enable | + wfe_b_enable); + + /* trigger operation */ + __raw_writel( + BF_PXP_CTRL_ENABLE(1) | + BF_PXP_CTRL_IRQ_ENABLE(0) | + BF_PXP_CTRL_NEXT_IRQ_ENABLE(0) | + BF_PXP_CTRL_LUT_DMA_IRQ_ENABLE(0) | + BF_PXP_CTRL_ENABLE_LCD0_HANDSHAKE(1) | + BF_PXP_CTRL_HANDSHAKE_ABORT_SKIP(1) | + BF_PXP_CTRL_ROTATE0(0) | + BF_PXP_CTRL_HFLIP0(0) | + BF_PXP_CTRL_VFLIP0(0) | + BF_PXP_CTRL_ROTATE1(0) | + BF_PXP_CTRL_HFLIP1(0) | + BF_PXP_CTRL_VFLIP1(0) | + BF_PXP_CTRL_ENABLE_PS_AS_OUT(0) | + BF_PXP_CTRL_ENABLE_DITHER(dither_enable) | + BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(0) | + BF_PXP_CTRL_ENABLE_ALPHA_B(0) | + BF_PXP_CTRL_BLOCK_SIZE(1) | + BF_PXP_CTRL_ENABLE_CSC2(0) | + BF_PXP_CTRL_ENABLE_LUT(1) | + BF_PXP_CTRL_ENABLE_ROTATE0(0) | + BF_PXP_CTRL_ENABLE_ROTATE1(0) | + BF_PXP_CTRL_EN_REPEAT(0) | + val, + pxp->base + HW_PXP_CTRL); + + return; + } + + if (pxp_is_v3(pxp)) + val = BF_PXP_CTRL_ENABLE_WFE_A(wfe_a_enable) | + BF_PXP_CTRL_ENABLE_WFE_B(wfe_b_enable) | + BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(0) | + BF_PXP_CTRL_ENABLE_ALPHA_B(0); + else if (pxp_is_v3p(pxp)) + val = BF_PXP_CTRL_ENABLE_WFE_B(wfe_a_enable | + wfe_b_enable); + + __raw_writel( + BF_PXP_CTRL_ENABLE(1) | + BF_PXP_CTRL_IRQ_ENABLE(0) | + BF_PXP_CTRL_NEXT_IRQ_ENABLE(0) | + BF_PXP_CTRL_LUT_DMA_IRQ_ENABLE(0) | + BF_PXP_CTRL_ENABLE_LCD0_HANDSHAKE(0) | + BF_PXP_CTRL_ROTATE0(0) | + BF_PXP_CTRL_HFLIP0(0) | + BF_PXP_CTRL_VFLIP0(0) | + BF_PXP_CTRL_ROTATE1(0) | + BF_PXP_CTRL_HFLIP1(0) | + BF_PXP_CTRL_VFLIP1(0) | + BF_PXP_CTRL_ENABLE_PS_AS_OUT(0) | + BF_PXP_CTRL_ENABLE_DITHER(dither_enable) | + BF_PXP_CTRL_BLOCK_SIZE(0) | + BF_PXP_CTRL_ENABLE_CSC2(0) | + BF_PXP_CTRL_ENABLE_LUT(0) | + BF_PXP_CTRL_ENABLE_ROTATE0(0) | + BF_PXP_CTRL_ENABLE_ROTATE1(0) | + BF_PXP_CTRL_EN_REPEAT(0) | + val, + pxp->base + HW_PXP_CTRL); + + if (pxp_is_v3(pxp)) + val = BF_PXP_CTRL2_ENABLE_WFE_A (0) | + BF_PXP_CTRL2_ENABLE_WFE_B (0) | + BF_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE (0) | + BF_PXP_CTRL2_ENABLE_ALPHA_B (0); + else if (pxp_is_v3p(pxp)) + val = BF_PXP_CTRL2_ENABLE_WFE_B(0); + + __raw_writel( + BF_PXP_CTRL2_ENABLE (0) | + BF_PXP_CTRL2_ROTATE0 (0) | + BF_PXP_CTRL2_HFLIP0 (0) | + BF_PXP_CTRL2_VFLIP0 (0) | + BF_PXP_CTRL2_ROTATE1 (0) | + BF_PXP_CTRL2_HFLIP1 (0) | + BF_PXP_CTRL2_VFLIP1 (0) | + BF_PXP_CTRL2_ENABLE_DITHER (0) | + BF_PXP_CTRL2_BLOCK_SIZE (0) | + BF_PXP_CTRL2_ENABLE_CSC2 (0) | + BF_PXP_CTRL2_ENABLE_LUT (0) | + BF_PXP_CTRL2_ENABLE_ROTATE0 (0) | + BF_PXP_CTRL2_ENABLE_ROTATE1 (0), + pxp->base + HW_PXP_CTRL2); + + dump_pxp_reg2(pxp); +} + +static int pxp_dma_init(struct pxps *pxp) +{ + struct pxp_dma *pxp_dma = &pxp->pxp_dma; + struct dma_device *dma = &pxp_dma->dma; + int i; + + dma_cap_set(DMA_SLAVE, dma->cap_mask); + dma_cap_set(DMA_PRIVATE, dma->cap_mask); + + /* Compulsory common fields */ + dma->dev = pxp->dev; + dma->device_alloc_chan_resources = pxp_alloc_chan_resources; + dma->device_free_chan_resources = pxp_free_chan_resources; + dma->device_tx_status = pxp_tx_status; + dma->device_issue_pending = pxp_issue_pending; + + /* Compulsory for DMA_SLAVE fields */ + dma->device_prep_slave_sg = pxp_prep_slave_sg; + dma->device_terminate_all = pxp_device_terminate_all; + + /* Initialize PxP Channels */ + INIT_LIST_HEAD(&dma->channels); + for (i = 0; i < NR_PXP_VIRT_CHANNEL; i++) { + struct pxp_channel *pxp_chan = pxp->channel + i; + struct dma_chan *dma_chan = &pxp_chan->dma_chan; + + spin_lock_init(&pxp_chan->lock); + + /* Only one EOF IRQ for PxP, shared by all channels */ + pxp_chan->eof_irq = pxp->irq; + pxp_chan->status = PXP_CHANNEL_FREE; + pxp_chan->completed = -ENXIO; + snprintf(pxp_chan->eof_name, sizeof(pxp_chan->eof_name), + "PXP EOF %d", i); + + dma_chan->device = &pxp_dma->dma; + dma_chan->cookie = 1; + dma_chan->chan_id = i; + list_add_tail(&dma_chan->device_node, &dma->channels); + } + + return dma_async_device_register(&pxp_dma->dma); +} + +static ssize_t clk_off_timeout_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", timeout_in_ms); +} + +static ssize_t clk_off_timeout_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int val; + if (sscanf(buf, "%d", &val) > 0) { + timeout_in_ms = val; + return count; + } + return -EINVAL; +} + +static DEVICE_ATTR(clk_off_timeout, 0644, clk_off_timeout_show, + clk_off_timeout_store); + +static ssize_t block_size_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%d\n", block_size); +} + +static ssize_t block_size_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + char **last = NULL; + + block_size = simple_strtoul(buf, last, 0); + if (block_size > 1) + block_size = 1; + + return count; +} +static DEVICE_ATTR(block_size, S_IWUSR | S_IRUGO, + block_size_show, block_size_store); + +static struct platform_device_id imx_pxpdma_devtype[] = { + { + .name = "imx7d-pxp-dma", + .driver_data = PXP_V3, + }, { + .name = "imx6ull-pxp-dma", + .driver_data = PXP_V3P, + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(platform, imx_pxpdma_devtype); + +static const struct of_device_id imx_pxpdma_dt_ids[] = { + { .compatible = "fsl,imx7d-pxp-dma", .data = &imx_pxpdma_devtype[0], }, + { .compatible = "fsl,imx6ull-pxp-dma", .data = &imx_pxpdma_devtype[1], }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx_pxpdma_dt_ids); + +static int has_pending_task(struct pxps *pxp, struct pxp_channel *task) +{ + int found; + unsigned long flags; + + spin_lock_irqsave(&pxp->lock, flags); + found = !list_empty(&head); + spin_unlock_irqrestore(&pxp->lock, flags); + + return found; +} + +static int pxp_dispatch_thread(void *argv) +{ + struct pxps *pxp = (struct pxps *)argv; + struct pxp_channel *pending = NULL; + unsigned long flags; + + set_freezable(); + + while (!kthread_should_stop()) { + int ret; + ret = wait_event_freezable(pxp->thread_waitq, + has_pending_task(pxp, pending) || + kthread_should_stop()); + if (ret < 0) + continue; + + if (kthread_should_stop()) + break; + + spin_lock_irqsave(&pxp->lock, flags); + pxp->pxp_ongoing = 1; + spin_unlock_irqrestore(&pxp->lock, flags); + init_completion(&pxp->complete); + ret = pxpdma_dostart_work(pxp); + if (ret) { + pxp->pxp_ongoing = 0; + continue; + } + ret = wait_for_completion_timeout(&pxp->complete, 2 * HZ); + if (ret == 0) { + printk(KERN_EMERG "%s: task is timeout\n\n", __func__); + break; + } + if (pxp->devdata && pxp->devdata->pxp_lut_cleanup_multiple) + pxp->devdata->pxp_lut_cleanup_multiple(pxp, 0, 0); + } + + return 0; +} + +static int pxp_init_interrupt(struct platform_device *pdev) +{ + int legacy_irq, std_irq, err; + struct pxps *pxp = platform_get_drvdata(pdev); + + legacy_irq = platform_get_irq(pdev, 0); + if (legacy_irq < 0) { + dev_err(&pdev->dev, "failed to get pxp legacy irq: %d\n", + legacy_irq); + return legacy_irq; + } + + std_irq = platform_get_irq(pdev, 1); + if (std_irq < 0) { + dev_err(&pdev->dev, "failed to get pxp standard irq: %d\n", + std_irq); + return std_irq; + } + + err = devm_request_irq(&pdev->dev, legacy_irq, pxp_irq, 0, + "pxp-dmaengine-legacy", pxp); + if (err) { + dev_err(&pdev->dev, "Request pxp legacy irq failed: %d\n", err); + return err; + } + + err = devm_request_irq(&pdev->dev, std_irq, pxp_irq, 0, + "pxp-dmaengine-std", pxp); + if (err) { + dev_err(&pdev->dev, "Request pxp standard irq failed: %d\n", + err); + return err; + } + + pxp->irq = legacy_irq; + + /* enable all the possible irq raised by PXP */ + __raw_writel(0xffff, pxp->base + HW_PXP_IRQ_MASK); + + return 0; +} + +static int pxp_create_attrs(struct platform_device *pdev) +{ + int ret = 0; + + if ((ret = device_create_file(&pdev->dev, &dev_attr_clk_off_timeout))) { + dev_err(&pdev->dev, + "Unable to create file from clk_off_timeout\n"); + return ret; + } + + if ((ret = device_create_file(&pdev->dev, &dev_attr_block_size))) { + device_remove_file(&pdev->dev, &dev_attr_clk_off_timeout); + + dev_err(&pdev->dev, + "Unable to create file from block_size\n"); + return ret; + } + + return 0; +} + +static void pxp_remove_attrs(struct platform_device *pdev) +{ + device_remove_file(&pdev->dev, &dev_attr_clk_off_timeout); + device_remove_file(&pdev->dev, &dev_attr_block_size); +} + +static void pxp_init_timer(struct pxps *pxp) +{ + INIT_WORK(&pxp->work, clkoff_callback); + + timer_setup(&pxp->clk_timer, pxp_clkoff_timer, 0); +} + +static bool is_mux_node(uint32_t node_id) +{ + if ((node_id < PXP_2D_MUX_MUX0) || + (node_id > PXP_2D_MUX_MUX15)) + return false; + + return true; +} + +static bool search_mux_chain(uint32_t mux_id, + struct edge_node *enode) +{ + bool found = false; + uint32_t i, j, next_mux = 0; + uint32_t output; + struct mux *muxes; + + muxes = (v3p_flag) ? muxes_v3p : muxes_v3; + + for (i = 0; i < 2; i++) { + output = muxes[mux_id].mux_outputs[i]; + if (output == 0xff) + break; + + if ((output == enode->adjvex)) { + /* found */ + found = true; + break; + } else if (is_mux_node(output)) { + next_mux = output - PXP_2D_MUX_BASE; + found = search_mux_chain(next_mux, enode); + + if (found) { + for (j = 0; j < 4; j++) { + if (muxes[next_mux].mux_inputs[j] == + (mux_id + PXP_2D_MUX_BASE)) + break; + } + + set_bit(next_mux, (unsigned long *)&enode->mux_used); + set_mux_val(&enode->muxes, next_mux, j); + break; + } + } + } + + return found; +} + +static void enode_mux_config(unsigned int vnode_id, + struct edge_node *enode) +{ + uint32_t i, j; + bool via_mux = false, need_search = false; + struct mux *muxes; + + BUG_ON(vnode_id >= PXP_2D_NUM); + BUG_ON(enode->adjvex >= PXP_2D_NUM); + + muxes = (v3p_flag) ? muxes_v3p : muxes_v3; + + for (i = 0; i < 16; i++) { + for (j = 0; j < 4; j++) { + if (muxes[i].mux_inputs[j] == 0xff) + break; + + if (muxes[i].mux_inputs[j] == vnode_id) + need_search = true; + else if (muxes[i].mux_inputs[j] == PXP_2D_ALPHA0_S0_S1) { + if ((vnode_id == PXP_2D_ALPHA0_S0) || + (vnode_id == PXP_2D_ALPHA0_S1)) + need_search = true; + } else if (muxes[i].mux_inputs[j] == PXP_2D_ALPHA1_S0_S1) { + if ((vnode_id == PXP_2D_ALPHA1_S0) || + (vnode_id == PXP_2D_ALPHA1_S1)) + need_search = true; + } + + if (need_search) { + via_mux = search_mux_chain(i, enode); + need_search = false; + break; + } + } + + if (via_mux) { + set_bit(i, (unsigned long *)&enode->mux_used); + set_mux_val(&enode->muxes, i, j); + break; + } + } +} + +static int pxp_create_initial_graph(struct platform_device *pdev) +{ + int i, j, first; + static bool (*adj_array)[PXP_2D_NUM]; + struct edge_node *enode, *curr = NULL; + + adj_array = (v3p_flag) ? adj_array_v3p : adj_array_v3; + + for (i = 0; i < PXP_2D_NUM; i++) { + switch (i) { + case PXP_2D_PS: + case PXP_2D_AS: + case PXP_2D_INPUT_FETCH0: + case PXP_2D_INPUT_FETCH1: + adj_list[i].type = PXP_2D_TYPE_INPUT; + break; + case PXP_2D_OUT: + case PXP_2D_INPUT_STORE0: + case PXP_2D_INPUT_STORE1: + adj_list[i].type = PXP_2D_TYPE_OUTPUT; + break; + default: + adj_list[i].type = PXP_2D_TYPE_ALU; + break; + } + + first = -1; + + for (j = 0; j < PXP_2D_NUM; j++) { + if (adj_array[i][j]) { + enode = kmem_cache_alloc(edge_node_cache, + GFP_KERNEL | __GFP_ZERO); + if (!enode) { + dev_err(&pdev->dev, "allocate edge node failed\n"); + return -ENOMEM; + } + enode->adjvex = j; + enode->prev_vnode = i; + + if (unlikely(first == -1)) { + first = j; + adj_list[i].first = enode; + } else + curr->next = enode; + + curr = enode; + enode_mux_config(i, enode); + dev_dbg(&pdev->dev, "(%d -> %d): mux_used 0x%x, mux_config 0x%x\n\n", + i, j, enode->mux_used, *(unsigned int*)&enode->muxes); + } + } + } + + return 0; +} + +/* Calculate the shortest paths start via + * 'from' node to other nodes + */ +static void pxp_find_shortest_path(unsigned int from) +{ + int i; + struct edge_node *enode; + struct path_node *pnode, *adjnode; + struct list_head queue; + + INIT_LIST_HEAD(&queue); + list_add_tail(&path_table[from][from].node, &queue); + + while(!list_empty(&queue)) { + pnode = list_entry(queue.next, struct path_node, node); + enode = adj_list[pnode->id].first; + while (enode) { + adjnode = &path_table[from][enode->adjvex]; + + if (adjnode->distance == DISTANCE_INFINITY) { + adjnode->distance = pnode->distance + 1; + adjnode->prev_node = pnode->id; + list_add_tail(&adjnode->node, &queue); + } + + enode = enode->next; + } + list_del_init(&pnode->node); + } + + for (i = 0; i < PXP_2D_NUM; i++) + pr_debug("From %u: to %d (id = %d, distance = 0x%x, prev_node = %d\n", + from, i, path_table[from][i].id, path_table[from][i].distance, + path_table[from][i].prev_node); +} + +static int pxp_gen_shortest_paths(struct platform_device *pdev) +{ + int i, j; + + for (i = 0; i < PXP_2D_NUM; i++) { + for (j = 0; j < PXP_2D_NUM; j++) { + path_table[i][j].id = j; + path_table[i][j].distance = DISTANCE_INFINITY; + path_table[i][j].prev_node = NO_PATH_NODE; + INIT_LIST_HEAD(&path_table[i][j].node); + } + + path_table[i][i].distance = 0; + + pxp_find_shortest_path(i); + } + + return 0; +} + +#ifdef CONFIG_MXC_FPGA_M4_TEST +static void pxp_config_m4(struct platform_device *pdev) +{ + fpga_tcml_base = ioremap(FPGA_TCML_ADDR, SZ_32K); + if (fpga_tcml_base == NULL) { + dev_err(&pdev->dev, + "get fpga_tcml_base error.\n"); + goto exit; + } + pinctrl_base = ioremap(PINCTRL, SZ_4K); + if (pinctrl_base == NULL) { + dev_err(&pdev->dev, + "get fpga_tcml_base error.\n"); + goto exit; + } + + __raw_writel(0xC0000000, pinctrl_base + 0x08); + __raw_writel(0x3, pinctrl_base + PIN_DOUT); + int i; + + for (i = 0; i < 1024 * 32 / 4; i++) + *(((unsigned int *)(fpga_tcml_base)) + i) = cm4_image[i]; +} +#endif + +static int pxp_probe(struct platform_device *pdev) +{ + const struct of_device_id *of_id = + of_match_device(imx_pxpdma_dt_ids, &pdev->dev); + struct pxps *pxp; + struct resource *res; + int err = 0; + + if (of_id) + pdev->id_entry = of_id->data; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + pxp = devm_kzalloc(&pdev->dev, sizeof(*pxp), GFP_KERNEL); + if (!pxp) { + dev_err(&pdev->dev, "failed to allocate control object\n"); + err = -ENOMEM; + goto exit; + } + + pxp->dev = &pdev->dev; + + platform_set_drvdata(pdev, pxp); + + spin_lock_init(&pxp->lock); + mutex_init(&pxp->clk_mutex); + + pxp->base = devm_ioremap_resource(&pdev->dev, res); + if (pxp->base == NULL) { + dev_err(&pdev->dev, "Couldn't ioremap regs\n"); + err = -ENODEV; + goto exit; + } + pxp_reg_base = pxp->base; + + pxp->pdev = pdev; + pxp->devdata = &pxp_devdata[pdev->id_entry->driver_data]; + + v3p_flag = (pxp_is_v3p(pxp)) ? true : false; + + pxp->ipg_clk = devm_clk_get(&pdev->dev, "pxp_ipg"); + pxp->axi_clk = devm_clk_get(&pdev->dev, "pxp_axi"); + + if (IS_ERR(pxp->ipg_clk) || IS_ERR(pxp->axi_clk)) { + dev_err(&pdev->dev, "pxp clocks invalid\n"); + err = -EINVAL; + goto exit; + } + + pxp_soft_reset(pxp); + pxp_writel(0x0, HW_PXP_CTRL); + /* Initialize DMA engine */ + err = pxp_dma_init(pxp); + if (err < 0) + goto exit; + + pxp_clk_enable(pxp); + pxp_soft_reset(pxp); + + /* Initialize PXP Interrupt */ + err = pxp_init_interrupt(pdev); + if (err < 0) + goto exit; + + if (pxp->devdata && pxp->devdata->pxp_data_path_config) + pxp->devdata->pxp_data_path_config(pxp); + /* enable all the possible irq raised by PXP */ + __raw_writel(0xffff, pxp->base + HW_PXP_IRQ_MASK); + + dump_pxp_reg(pxp); + pxp_clk_disable(pxp); + + pxp_init_timer(pxp); + + init_waitqueue_head(&pxp->thread_waitq); + /* allocate a kernel thread to dispatch pxp conf */ + pxp->dispatch = kthread_run(pxp_dispatch_thread, pxp, "pxp_dispatch"); + if (IS_ERR(pxp->dispatch)) { + err = PTR_ERR(pxp->dispatch); + goto exit; + } + tx_desc_cache = kmem_cache_create("tx_desc", sizeof(struct pxp_tx_desc), + 0, SLAB_HWCACHE_ALIGN, NULL); + if (!tx_desc_cache) { + err = -ENOMEM; + goto exit; + } + + edge_node_cache = kmem_cache_create("edge_node", sizeof(struct edge_node), + 0, SLAB_HWCACHE_ALIGN, NULL); + if (!edge_node_cache) { + err = -ENOMEM; + kmem_cache_destroy(tx_desc_cache); + goto exit; + } + + err = pxp_create_attrs(pdev); + if (err) { + kmem_cache_destroy(tx_desc_cache); + kmem_cache_destroy(edge_node_cache); + goto exit; + } + + if ((err = pxp_create_initial_graph(pdev))) { + kmem_cache_destroy(tx_desc_cache); + kmem_cache_destroy(edge_node_cache); + goto exit; + } + + pxp_gen_shortest_paths(pdev); + +#ifdef CONFIG_MXC_FPGA_M4_TEST + pxp_config_m4(pdev); +#endif + register_pxp_device(); + pm_runtime_enable(pxp->dev); + +exit: + if (err) + dev_err(&pdev->dev, "Exiting (unsuccessfully) pxp_probe()\n"); + return err; +} + +static int pxp_remove(struct platform_device *pdev) +{ + struct pxps *pxp = platform_get_drvdata(pdev); + + unregister_pxp_device(); + kmem_cache_destroy(tx_desc_cache); + kmem_cache_destroy(edge_node_cache); + kthread_stop(pxp->dispatch); + cancel_work_sync(&pxp->work); + del_timer_sync(&pxp->clk_timer); + clk_disable_unprepare(pxp->ipg_clk); + clk_disable_unprepare(pxp->axi_clk); + pxp_remove_attrs(pdev); + dma_async_device_unregister(&(pxp->pxp_dma.dma)); + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int pxp_suspend(struct device *dev) +{ + struct pxps *pxp = dev_get_drvdata(dev); + + pxp_clk_enable(pxp); + while (__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_ENABLE) + ; + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL); + pxp_clk_disable(pxp); + + return 0; +} + +static int pxp_resume(struct device *dev) +{ + struct pxps *pxp = dev_get_drvdata(dev); + + pxp_clk_enable(pxp); + /* Pull PxP out of reset */ + pxp_soft_reset(pxp); + if (pxp->devdata && pxp->devdata->pxp_data_path_config) + pxp->devdata->pxp_data_path_config(pxp); + /* enable all the possible irq raised by PXP */ + __raw_writel(0xffff, pxp->base + HW_PXP_IRQ_MASK); + pxp_clk_disable(pxp); + + return 0; +} +#else +#define pxp_suspend NULL +#define pxp_resume NULL +#endif + +#ifdef CONFIG_PM +static int pxp_runtime_suspend(struct device *dev) +{ + dev_dbg(dev, "pxp busfreq high release.\n"); + + return 0; +} + +static int pxp_runtime_resume(struct device *dev) +{ + dev_dbg(dev, "pxp busfreq high request.\n"); + + return 0; +} +#else +#define pxp_runtime_suspend NULL +#define pxp_runtime_resume NULL +#endif + +static const struct dev_pm_ops pxp_pm_ops = { + SET_RUNTIME_PM_OPS(pxp_runtime_suspend, pxp_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pxp_suspend, pxp_resume) +}; + +static struct platform_driver pxp_driver = { + .driver = { + .name = "imx-pxp-v3", + .of_match_table = of_match_ptr(imx_pxpdma_dt_ids), + .pm = &pxp_pm_ops, + }, + .probe = pxp_probe, + .remove = pxp_remove, +}; + +static int __init pxp_init(void) +{ + return platform_driver_register(&pxp_driver); +} +late_initcall(pxp_init); + +static void __exit pxp_exit(void) +{ + platform_driver_unregister(&pxp_driver); +} +module_exit(pxp_exit); + + +MODULE_DESCRIPTION("i.MX PxP driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/dma/pxp/reg_bitfields.h b/drivers/dma/pxp/reg_bitfields.h new file mode 100644 index 00000000000000..0acb83d8e4a7ad --- /dev/null +++ b/drivers/dma/pxp/reg_bitfields.h @@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ + +#ifndef _REG_BITFIELDS_H +#define _REG_BITFIELDS_H +struct mux_config { + uint32_t mux0_sel : 2; + uint32_t mux1_sel : 2; + uint32_t mux2_sel : 2; + uint32_t mux3_sel : 2; + uint32_t mux4_sel : 2; + uint32_t mux5_sel : 2; + uint32_t mux6_sel : 2; + uint32_t mux7_sel : 2; + uint32_t mux8_sel : 2; + uint32_t mux9_sel : 2; + uint32_t mux10_sel : 2; + uint32_t mux11_sel : 2; + uint32_t mux12_sel : 2; + uint32_t mux13_sel : 2; + uint32_t mux14_sel : 2; + uint32_t mux15_sel : 2; +}; + +/* legacy engine registers */ +struct ps_ctrl { + uint32_t format : 6; + uint32_t wb_swap : 1; + uint32_t rsvd0 : 1; + uint32_t decy : 2; + uint32_t decx : 2; + uint32_t rsvd1 : 20; +}; + +struct ps_scale { + uint32_t xscale : 15; + uint32_t rsvd1 : 1; + uint32_t yscale : 15; + uint32_t rsvd2 : 1; +}; + +struct ps_offset { + uint32_t xoffset : 12; + uint32_t rsvd1 : 4; + uint32_t yoffset : 12; + uint32_t rsvd2 : 4; +}; + +struct as_ctrl { + uint32_t rsvd0 : 1; + uint32_t alpha_ctrl : 2; + uint32_t enable_colorkey : 1; + uint32_t format : 4; + uint32_t alpha : 8; + uint32_t rop : 4; + uint32_t alpha0_invert : 1; + uint32_t alpha1_invert : 1; + uint32_t rsvd1 : 10; +}; + +struct out_ctrl { + uint32_t format : 5; + uint32_t rsvd0 : 3; + uint32_t interlaced_output : 2; + uint32_t rsvd1 : 13; + uint32_t alpha_output : 1; + uint32_t alpha : 8; +}; + +struct coordinate { + uint32_t y : 14; + uint32_t rsvd0 : 2; + uint32_t x : 14; + uint32_t rsvd1 : 2; +}; + +struct pxp_alpha_ctrl { + uint32_t poter_duff_enable : 1; + uint32_t s0_s1_factor_mode : 2; + uint32_t s0_global_alpha_mode : 2; + uint32_t s0_alpha_mode : 1; + uint32_t s0_color_mode : 1; + uint32_t rsvd1 : 1; + uint32_t s1_s0_factor_mode : 2; + uint32_t s1_global_alpha_mode : 2; + uint32_t s1_alpha_mode : 1; + uint32_t s1_color_mode : 1; + uint32_t rsvd0 : 2; + uint32_t s0_global_alpha : 8; + uint32_t s1_global_alpha : 8; +}; + +/* store engine registers */ +struct store_ctrl { + uint32_t ch_en : 1; + uint32_t block_en : 1; + uint32_t block_16 : 1; + uint32_t handshake_en : 1; + uint32_t array_en : 1; + uint32_t array_line_num : 2; + uint32_t rsvd3 : 1; + uint32_t store_bypass_en : 1; + uint32_t store_memory_en : 1; + uint32_t pack_in_sel : 1; + uint32_t fill_data_en : 1; + uint32_t rsvd2 : 4; + uint32_t wr_num_bytes : 2; + uint32_t rsvd1 : 6; + uint32_t combine_2channel : 1; + uint32_t rsvd0 : 6; + uint32_t arbit_en : 1; +}; + +struct store_size { + uint32_t out_width : 16; + uint32_t out_height : 16; +}; + +struct store_pitch { + uint32_t ch0_out_pitch : 16; + uint32_t ch1_out_pitch : 16; +}; + +struct store_shift_ctrl { + uint32_t rsvd2 : 2; + uint32_t output_active_bpp : 2; + uint32_t out_yuv422_1p_en : 1; + uint32_t out_yuv422_2p_en : 1; + uint32_t rsvd1 : 1; + uint32_t shift_bypass : 1; + uint32_t rsvd0 : 24; +}; + +struct store_d_shift { + uint64_t d_shift_width0 : 6; + uint64_t rsvd3 : 1; + uint64_t d_shift_flag0 : 1; + uint64_t d_shift_width1 : 6; + uint64_t rsvd2 : 1; + uint64_t d_shift_flag1 : 1; + uint64_t d_shift_width2 : 6; + uint64_t rsvd1 : 1; + uint64_t d_shift_flag2 : 1; + uint64_t d_shift_width3 : 6; + uint64_t rsvd0 : 1; + uint64_t d_shift_flag3 : 1; + + uint64_t d_shift_width4 : 6; + uint64_t rsvd7 : 1; + uint64_t d_shift_flag4 : 1; + uint64_t d_shift_width5 : 6; + uint64_t rsvd6 : 1; + uint64_t d_shift_flag5 : 1; + uint64_t d_shift_width6 : 6; + uint64_t rsvd5 : 1; + uint64_t d_shift_flag6 : 1; + uint64_t d_shift_width7 : 6; + uint64_t rsvd4 : 1; + uint64_t d_shift_flag7 : 1; +}; + +struct store_f_shift { + uint64_t f_shift_width0 : 6; + uint64_t rsvd3 : 1; + uint64_t f_shift_flag0 : 1; + uint64_t f_shift_width1 : 6; + uint64_t rsvd2 : 1; + uint64_t f_shift_flag1 : 1; + uint64_t f_shift_width2 : 6; + uint64_t rsvd1 : 1; + uint64_t f_shift_flag2 : 1; + uint64_t f_shift_width3 : 6; + uint64_t rsvd0 : 1; + uint64_t f_shift_flag3 : 1; + + uint64_t f_shift_width4 : 6; + uint64_t rsvd7 : 1; + uint64_t f_shift_flag4 : 1; + uint64_t f_shift_width5 : 6; + uint64_t rsvd6 : 1; + uint64_t f_shift_flag5 : 1; + uint64_t f_shift_width6 : 6; + uint64_t rsvd5 : 1; + uint64_t f_shift_flag6 : 1; + uint64_t f_shift_width7 : 6; + uint64_t rsvd4 : 1; + uint64_t f_shift_flag7 : 1; +}; + +struct store_d_mask { + uint64_t d_mask_l : 32; + uint64_t d_mask_h : 32; +}; + +/* fetch engine registers */ +struct fetch_ctrl { + uint32_t ch_en : 1; + uint32_t block_en : 1; + uint32_t block_16 : 1; + uint32_t handshake_en : 1; + uint32_t bypass_pixel_en : 1; + uint32_t high_byte : 1; + uint32_t rsvd4 : 3; + uint32_t hflip : 1; + uint32_t vflip : 1; + uint32_t rsvd3 : 1; + uint32_t rotation_angle : 2; + uint32_t rsvd2 : 2; + uint32_t rd_num_bytes : 2; + uint32_t rsvd1 : 6; + uint32_t handshake_scan_line_num : 2; + uint32_t rsvd0 : 5; + uint32_t arbit_en : 1; +}; + +struct fetch_active_size_ulc { + uint32_t active_size_ulc_x : 16; + uint32_t active_size_ulc_y : 16; +}; + +struct fetch_active_size_lrc { + uint32_t active_size_lrc_x : 16; + uint32_t active_size_lrc_y : 16; +}; + +struct fetch_size { + uint32_t input_total_width : 16; + uint32_t input_total_height : 16; +}; + +struct fetch_pitch { + uint32_t ch0_input_pitch : 16; + uint32_t ch1_input_pitch : 16; +}; + +struct fetch_shift_ctrl { + uint32_t input_active_bpp : 2; + uint32_t rsvd1 : 6; + uint32_t expand_format : 3; + uint32_t expand_en : 1; + uint32_t shift_bypass : 1; + uint32_t rsvd0 : 19; +}; + +struct fetch_shift_offset { + uint32_t offset0 : 5; + uint32_t rsvd3 : 3; + uint32_t offset1 : 5; + uint32_t rsvd2 : 3; + uint32_t offset2 : 5; + uint32_t rsvd1 : 3; + uint32_t offset3 : 5; + uint32_t rsvd0 : 3; +}; + +struct fetch_shift_width { + uint32_t width0 : 4; + uint32_t width1 : 4; + uint32_t width2 : 4; + uint32_t width3 : 4; + uint32_t rsvd0 : 16; +}; +#endif diff --git a/drivers/dma/pxp/regs-pxp_v2.h b/drivers/dma/pxp/regs-pxp_v2.h new file mode 100644 index 00000000000000..0e2ef8933ed111 --- /dev/null +++ b/drivers/dma/pxp/regs-pxp_v2.h @@ -0,0 +1,1139 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Freescale PXP Register Definitions + * + * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.29 + * Template revision: 1.3 + */ + +#ifndef __ARCH_ARM___PXP_H +#define __ARCH_ARM___PXP_H + +#define HW_PXP_CTRL (0x00000000) +#define HW_PXP_CTRL_SET (0x00000004) +#define HW_PXP_CTRL_CLR (0x00000008) +#define HW_PXP_CTRL_TOG (0x0000000c) + +#define BM_PXP_CTRL_SFTRST 0x80000000 +#define BM_PXP_CTRL_CLKGATE 0x40000000 +#define BM_PXP_CTRL_RSVD4 0x20000000 +#define BM_PXP_CTRL_EN_REPEAT 0x10000000 +#define BP_PXP_CTRL_RSVD3 26 +#define BM_PXP_CTRL_RSVD3 0x0C000000 +#define BF_PXP_CTRL_RSVD3(v) \ + (((v) << 26) & BM_PXP_CTRL_RSVD3) +#define BP_PXP_CTRL_INTERLACED_INPUT 24 +#define BM_PXP_CTRL_INTERLACED_INPUT 0x03000000 +#define BF_PXP_CTRL_INTERLACED_INPUT(v) \ + (((v) << 24) & BM_PXP_CTRL_INTERLACED_INPUT) +#define BV_PXP_CTRL_INTERLACED_INPUT__PROGRESSIVE 0x0 +#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD0 0x2 +#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD1 0x3 +#define BM_PXP_CTRL_BLOCK_SIZE 0x00800000 +#define BV_PXP_CTRL_BLOCK_SIZE__8X8 0x0 +#define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x1 +#define BM_PXP_CTRL_ROT_POS 0x00400000 +#define BM_PXP_CTRL_IN_PLACE 0x00200000 +#define BP_PXP_CTRL_RSVD1 12 +#define BM_PXP_CTRL_RSVD1 0x001FF000 +#define BF_PXP_CTRL_RSVD1(v) \ + (((v) << 12) & BM_PXP_CTRL_RSVD1) +#define BM_PXP_CTRL_VFLIP 0x00000800 +#define BM_PXP_CTRL_HFLIP 0x00000400 +#define BP_PXP_CTRL_ROTATE 8 +#define BM_PXP_CTRL_ROTATE 0x00000300 +#define BF_PXP_CTRL_ROTATE(v) \ + (((v) << 8) & BM_PXP_CTRL_ROTATE) +#define BV_PXP_CTRL_ROTATE__ROT_0 0x0 +#define BV_PXP_CTRL_ROTATE__ROT_90 0x1 +#define BV_PXP_CTRL_ROTATE__ROT_180 0x2 +#define BV_PXP_CTRL_ROTATE__ROT_270 0x3 +#define BP_PXP_CTRL_RSVD0 5 +#define BM_PXP_CTRL_RSVD0 0x000000E0 +#define BF_PXP_CTRL_RSVD0(v) \ + (((v) << 5) & BM_PXP_CTRL_RSVD0) +#define BM_PXP_CTRL_ENABLE_LCD_HANDSHAKE 0x00000010 +#define BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE 0x00000008 +#define BM_PXP_CTRL_NEXT_IRQ_ENABLE 0x00000004 +#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 +#define BM_PXP_CTRL_ENABLE 0x00000001 + +#define HW_PXP_STAT (0x00000010) +#define HW_PXP_STAT_SET (0x00000014) +#define HW_PXP_STAT_CLR (0x00000018) +#define HW_PXP_STAT_TOG (0x0000001c) + +#define BP_PXP_STAT_BLOCKX 24 +#define BM_PXP_STAT_BLOCKX 0xFF000000 +#define BF_PXP_STAT_BLOCKX(v) \ + (((v) << 24) & BM_PXP_STAT_BLOCKX) +#define BP_PXP_STAT_BLOCKY 16 +#define BM_PXP_STAT_BLOCKY 0x00FF0000 +#define BF_PXP_STAT_BLOCKY(v) \ + (((v) << 16) & BM_PXP_STAT_BLOCKY) +#define BP_PXP_STAT_RSVD2 9 +#define BM_PXP_STAT_RSVD2 0x0000FE00 +#define BF_PXP_STAT_RSVD2(v) \ + (((v) << 9) & BM_PXP_STAT_RSVD2) +#define BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ 0x00000100 +#define BP_PXP_STAT_AXI_ERROR_ID 4 +#define BM_PXP_STAT_AXI_ERROR_ID 0x000000F0 +#define BF_PXP_STAT_AXI_ERROR_ID(v) \ + (((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID) +#define BM_PXP_STAT_NEXT_IRQ 0x00000008 +#define BM_PXP_STAT_AXI_READ_ERROR 0x00000004 +#define BM_PXP_STAT_AXI_WRITE_ERROR 0x00000002 +#define BM_PXP_STAT_IRQ 0x00000001 + +#define HW_PXP_OUT_CTRL (0x00000020) +#define HW_PXP_OUT_CTRL_SET (0x00000024) +#define HW_PXP_OUT_CTRL_CLR (0x00000028) +#define HW_PXP_OUT_CTRL_TOG (0x0000002c) + +#define BP_PXP_OUT_CTRL_ALPHA 24 +#define BM_PXP_OUT_CTRL_ALPHA 0xFF000000 +#define BF_PXP_OUT_CTRL_ALPHA(v) \ + (((v) << 24) & BM_PXP_OUT_CTRL_ALPHA) +#define BM_PXP_OUT_CTRL_ALPHA_OUTPUT 0x00800000 +#define BP_PXP_OUT_CTRL_RSVD1 10 +#define BM_PXP_OUT_CTRL_RSVD1 0x007FFC00 +#define BF_PXP_OUT_CTRL_RSVD1(v) \ + (((v) << 10) & BM_PXP_OUT_CTRL_RSVD1) +#define BP_PXP_OUT_CTRL_INTERLACED_OUTPUT 8 +#define BM_PXP_OUT_CTRL_INTERLACED_OUTPUT 0x00000300 +#define BF_PXP_OUT_CTRL_INTERLACED_OUTPUT(v) \ + (((v) << 8) & BM_PXP_OUT_CTRL_INTERLACED_OUTPUT) +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0 +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD0 0x1 +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD1 0x2 +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3 +#define BP_PXP_OUT_CTRL_RSVD0 5 +#define BM_PXP_OUT_CTRL_RSVD0 0x000000E0 +#define BF_PXP_OUT_CTRL_RSVD0(v) \ + (((v) << 5) & BM_PXP_OUT_CTRL_RSVD0) +#define BP_PXP_OUT_CTRL_FORMAT 0 +#define BM_PXP_OUT_CTRL_FORMAT 0x0000001F +#define BF_PXP_OUT_CTRL_FORMAT(v) \ + (((v) << 0) & BM_PXP_OUT_CTRL_FORMAT) +#define BV_PXP_OUT_CTRL_FORMAT__ARGB8888 0x0 +#define BV_PXP_OUT_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_OUT_CTRL_FORMAT__RGB888P 0x5 +#define BV_PXP_OUT_CTRL_FORMAT__ARGB1555 0x8 +#define BV_PXP_OUT_CTRL_FORMAT__ARGB4444 0x9 +#define BV_PXP_OUT_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_OUT_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_OUT_CTRL_FORMAT__RGB565 0xE +#define BV_PXP_OUT_CTRL_FORMAT__YUV1P444 0x10 +#define BV_PXP_OUT_CTRL_FORMAT__UYVY1P422 0x12 +#define BV_PXP_OUT_CTRL_FORMAT__VYUY1P422 0x13 +#define BV_PXP_OUT_CTRL_FORMAT__Y8 0x14 +#define BV_PXP_OUT_CTRL_FORMAT__Y4 0x15 +#define BV_PXP_OUT_CTRL_FORMAT__YUV2P422 0x18 +#define BV_PXP_OUT_CTRL_FORMAT__YUV2P420 0x19 +#define BV_PXP_OUT_CTRL_FORMAT__YVU2P422 0x1A +#define BV_PXP_OUT_CTRL_FORMAT__YVU2P420 0x1B + +#define HW_PXP_OUT_BUF (0x00000030) + +#define BP_PXP_OUT_BUF_ADDR 0 +#define BM_PXP_OUT_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_OUT_BUF_ADDR(v) (v) + +#define HW_PXP_OUT_BUF2 (0x00000040) + +#define BP_PXP_OUT_BUF2_ADDR 0 +#define BM_PXP_OUT_BUF2_ADDR 0xFFFFFFFF +#define BF_PXP_OUT_BUF2_ADDR(v) (v) + +#define HW_PXP_OUT_PITCH (0x00000050) + +#define BP_PXP_OUT_PITCH_RSVD 16 +#define BM_PXP_OUT_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_OUT_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_OUT_PITCH_RSVD) +#define BP_PXP_OUT_PITCH_PITCH 0 +#define BM_PXP_OUT_PITCH_PITCH 0x0000FFFF +#define BF_PXP_OUT_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_OUT_PITCH_PITCH) + +#define HW_PXP_OUT_LRC (0x00000060) + +#define BP_PXP_OUT_LRC_RSVD1 30 +#define BM_PXP_OUT_LRC_RSVD1 0xC0000000 +#define BF_PXP_OUT_LRC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_LRC_RSVD1) +#define BP_PXP_OUT_LRC_X 16 +#define BM_PXP_OUT_LRC_X 0x3FFF0000 +#define BF_PXP_OUT_LRC_X(v) \ + (((v) << 16) & BM_PXP_OUT_LRC_X) +#define BP_PXP_OUT_LRC_RSVD0 14 +#define BM_PXP_OUT_LRC_RSVD0 0x0000C000 +#define BF_PXP_OUT_LRC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_LRC_RSVD0) +#define BP_PXP_OUT_LRC_Y 0 +#define BM_PXP_OUT_LRC_Y 0x00003FFF +#define BF_PXP_OUT_LRC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_LRC_Y) + +#define HW_PXP_OUT_PS_ULC (0x00000070) + +#define BP_PXP_OUT_PS_ULC_RSVD1 30 +#define BM_PXP_OUT_PS_ULC_RSVD1 0xC0000000 +#define BF_PXP_OUT_PS_ULC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_PS_ULC_RSVD1) +#define BP_PXP_OUT_PS_ULC_X 16 +#define BM_PXP_OUT_PS_ULC_X 0x3FFF0000 +#define BF_PXP_OUT_PS_ULC_X(v) \ + (((v) << 16) & BM_PXP_OUT_PS_ULC_X) +#define BP_PXP_OUT_PS_ULC_RSVD0 14 +#define BM_PXP_OUT_PS_ULC_RSVD0 0x0000C000 +#define BF_PXP_OUT_PS_ULC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_PS_ULC_RSVD0) +#define BP_PXP_OUT_PS_ULC_Y 0 +#define BM_PXP_OUT_PS_ULC_Y 0x00003FFF +#define BF_PXP_OUT_PS_ULC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_PS_ULC_Y) + +#define HW_PXP_OUT_PS_LRC (0x00000080) + +#define BP_PXP_OUT_PS_LRC_RSVD1 30 +#define BM_PXP_OUT_PS_LRC_RSVD1 0xC0000000 +#define BF_PXP_OUT_PS_LRC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_PS_LRC_RSVD1) +#define BP_PXP_OUT_PS_LRC_X 16 +#define BM_PXP_OUT_PS_LRC_X 0x3FFF0000 +#define BF_PXP_OUT_PS_LRC_X(v) \ + (((v) << 16) & BM_PXP_OUT_PS_LRC_X) +#define BP_PXP_OUT_PS_LRC_RSVD0 14 +#define BM_PXP_OUT_PS_LRC_RSVD0 0x0000C000 +#define BF_PXP_OUT_PS_LRC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_PS_LRC_RSVD0) +#define BP_PXP_OUT_PS_LRC_Y 0 +#define BM_PXP_OUT_PS_LRC_Y 0x00003FFF +#define BF_PXP_OUT_PS_LRC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_PS_LRC_Y) + +#define HW_PXP_OUT_AS_ULC (0x00000090) + +#define BP_PXP_OUT_AS_ULC_RSVD1 30 +#define BM_PXP_OUT_AS_ULC_RSVD1 0xC0000000 +#define BF_PXP_OUT_AS_ULC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_AS_ULC_RSVD1) +#define BP_PXP_OUT_AS_ULC_X 16 +#define BM_PXP_OUT_AS_ULC_X 0x3FFF0000 +#define BF_PXP_OUT_AS_ULC_X(v) \ + (((v) << 16) & BM_PXP_OUT_AS_ULC_X) +#define BP_PXP_OUT_AS_ULC_RSVD0 14 +#define BM_PXP_OUT_AS_ULC_RSVD0 0x0000C000 +#define BF_PXP_OUT_AS_ULC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_AS_ULC_RSVD0) +#define BP_PXP_OUT_AS_ULC_Y 0 +#define BM_PXP_OUT_AS_ULC_Y 0x00003FFF +#define BF_PXP_OUT_AS_ULC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_AS_ULC_Y) + +#define HW_PXP_OUT_AS_LRC (0x000000a0) + +#define BP_PXP_OUT_AS_LRC_RSVD1 30 +#define BM_PXP_OUT_AS_LRC_RSVD1 0xC0000000 +#define BF_PXP_OUT_AS_LRC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_AS_LRC_RSVD1) +#define BP_PXP_OUT_AS_LRC_X 16 +#define BM_PXP_OUT_AS_LRC_X 0x3FFF0000 +#define BF_PXP_OUT_AS_LRC_X(v) \ + (((v) << 16) & BM_PXP_OUT_AS_LRC_X) +#define BP_PXP_OUT_AS_LRC_RSVD0 14 +#define BM_PXP_OUT_AS_LRC_RSVD0 0x0000C000 +#define BF_PXP_OUT_AS_LRC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_AS_LRC_RSVD0) +#define BP_PXP_OUT_AS_LRC_Y 0 +#define BM_PXP_OUT_AS_LRC_Y 0x00003FFF +#define BF_PXP_OUT_AS_LRC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_AS_LRC_Y) + +#define HW_PXP_PS_CTRL (0x000000b0) +#define HW_PXP_PS_CTRL_SET (0x000000b4) +#define HW_PXP_PS_CTRL_CLR (0x000000b8) +#define HW_PXP_PS_CTRL_TOG (0x000000bc) + +#define BP_PXP_PS_CTRL_RSVD1 12 +#define BM_PXP_PS_CTRL_RSVD1 0xFFFFF000 +#define BF_PXP_PS_CTRL_RSVD1(v) \ + (((v) << 12) & BM_PXP_PS_CTRL_RSVD1) +#define BP_PXP_PS_CTRL_DECX 10 +#define BM_PXP_PS_CTRL_DECX 0x00000C00 +#define BF_PXP_PS_CTRL_DECX(v) \ + (((v) << 10) & BM_PXP_PS_CTRL_DECX) +#define BV_PXP_PS_CTRL_DECX__DISABLE 0x0 +#define BV_PXP_PS_CTRL_DECX__DECX2 0x1 +#define BV_PXP_PS_CTRL_DECX__DECX4 0x2 +#define BV_PXP_PS_CTRL_DECX__DECX8 0x3 +#define BP_PXP_PS_CTRL_DECY 8 +#define BM_PXP_PS_CTRL_DECY 0x00000300 +#define BF_PXP_PS_CTRL_DECY(v) \ + (((v) << 8) & BM_PXP_PS_CTRL_DECY) +#define BV_PXP_PS_CTRL_DECY__DISABLE 0x0 +#define BV_PXP_PS_CTRL_DECY__DECY2 0x1 +#define BV_PXP_PS_CTRL_DECY__DECY4 0x2 +#define BV_PXP_PS_CTRL_DECY__DECY8 0x3 +#define BP_PXP_PS_CTRL_SWAP 5 +#define BM_PXP_PS_CTRL_SWAP 0x000000E0 +#define BF_PXP_PS_CTRL_SWAP(v) \ + (((v) << 5) & BM_PXP_PS_CTRL_SWAP) +#define BP_PXP_PS_CTRL_FORMAT 0 +#define BM_PXP_PS_CTRL_FORMAT 0x0000001F +#define BF_PXP_PS_CTRL_FORMAT(v) \ + (((v) << 0) & BM_PXP_PS_CTRL_FORMAT) +#define BV_PXP_PS_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_PS_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_PS_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_PS_CTRL_FORMAT__RGB565 0xE +#define BV_PXP_PS_CTRL_FORMAT__YUV1P444 0x10 +#define BV_PXP_PS_CTRL_FORMAT__UYVY1P422 0x12 +#define BV_PXP_PS_CTRL_FORMAT__VYUY1P422 0x13 +#define BV_PXP_PS_CTRL_FORMAT__Y8 0x14 +#define BV_PXP_PS_CTRL_FORMAT__Y4 0x15 +#define BV_PXP_PS_CTRL_FORMAT__YUV2P422 0x18 +#define BV_PXP_PS_CTRL_FORMAT__YUV2P420 0x19 +#define BV_PXP_PS_CTRL_FORMAT__YVU2P422 0x1A +#define BV_PXP_PS_CTRL_FORMAT__YVU2P420 0x1B +#define BV_PXP_PS_CTRL_FORMAT__YUV422 0x1E +#define BV_PXP_PS_CTRL_FORMAT__YUV420 0x1F + +#define HW_PXP_PS_BUF (0x000000c0) + +#define BP_PXP_PS_BUF_ADDR 0 +#define BM_PXP_PS_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_PS_BUF_ADDR(v) (v) + +#define HW_PXP_PS_UBUF (0x000000d0) + +#define BP_PXP_PS_UBUF_ADDR 0 +#define BM_PXP_PS_UBUF_ADDR 0xFFFFFFFF +#define BF_PXP_PS_UBUF_ADDR(v) (v) + +#define HW_PXP_PS_VBUF (0x000000e0) + +#define BP_PXP_PS_VBUF_ADDR 0 +#define BM_PXP_PS_VBUF_ADDR 0xFFFFFFFF +#define BF_PXP_PS_VBUF_ADDR(v) (v) + +#define HW_PXP_PS_PITCH (0x000000f0) + +#define BP_PXP_PS_PITCH_RSVD 16 +#define BM_PXP_PS_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_PS_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_PS_PITCH_RSVD) +#define BP_PXP_PS_PITCH_PITCH 0 +#define BM_PXP_PS_PITCH_PITCH 0x0000FFFF +#define BF_PXP_PS_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_PS_PITCH_PITCH) + +#define HW_PXP_PS_BACKGROUND (0x00000100) + +#define BP_PXP_PS_BACKGROUND_RSVD 24 +#define BM_PXP_PS_BACKGROUND_RSVD 0xFF000000 +#define BF_PXP_PS_BACKGROUND_RSVD(v) \ + (((v) << 24) & BM_PXP_PS_BACKGROUND_RSVD) +#define BP_PXP_PS_BACKGROUND_COLOR 0 +#define BM_PXP_PS_BACKGROUND_COLOR 0x00FFFFFF +#define BF_PXP_PS_BACKGROUND_COLOR(v) \ + (((v) << 0) & BM_PXP_PS_BACKGROUND_COLOR) + +#define HW_PXP_PS_SCALE (0x00000110) + +#define BM_PXP_PS_SCALE_RSVD2 0x80000000 +#define BP_PXP_PS_SCALE_YSCALE 16 +#define BM_PXP_PS_SCALE_YSCALE 0x7FFF0000 +#define BF_PXP_PS_SCALE_YSCALE(v) \ + (((v) << 16) & BM_PXP_PS_SCALE_YSCALE) +#define BM_PXP_PS_SCALE_RSVD1 0x00008000 +#define BP_PXP_PS_SCALE_XSCALE 0 +#define BM_PXP_PS_SCALE_XSCALE 0x00007FFF +#define BF_PXP_PS_SCALE_XSCALE(v) \ + (((v) << 0) & BM_PXP_PS_SCALE_XSCALE) + +#define HW_PXP_PS_OFFSET (0x00000120) + +#define BP_PXP_PS_OFFSET_RSVD2 28 +#define BM_PXP_PS_OFFSET_RSVD2 0xF0000000 +#define BF_PXP_PS_OFFSET_RSVD2(v) \ + (((v) << 28) & BM_PXP_PS_OFFSET_RSVD2) +#define BP_PXP_PS_OFFSET_YOFFSET 16 +#define BM_PXP_PS_OFFSET_YOFFSET 0x0FFF0000 +#define BF_PXP_PS_OFFSET_YOFFSET(v) \ + (((v) << 16) & BM_PXP_PS_OFFSET_YOFFSET) +#define BP_PXP_PS_OFFSET_RSVD1 12 +#define BM_PXP_PS_OFFSET_RSVD1 0x0000F000 +#define BF_PXP_PS_OFFSET_RSVD1(v) \ + (((v) << 12) & BM_PXP_PS_OFFSET_RSVD1) +#define BP_PXP_PS_OFFSET_XOFFSET 0 +#define BM_PXP_PS_OFFSET_XOFFSET 0x00000FFF +#define BF_PXP_PS_OFFSET_XOFFSET(v) \ + (((v) << 0) & BM_PXP_PS_OFFSET_XOFFSET) + +#define HW_PXP_PS_CLRKEYLOW (0x00000130) + +#define BP_PXP_PS_CLRKEYLOW_RSVD1 24 +#define BM_PXP_PS_CLRKEYLOW_RSVD1 0xFF000000 +#define BF_PXP_PS_CLRKEYLOW_RSVD1(v) \ + (((v) << 24) & BM_PXP_PS_CLRKEYLOW_RSVD1) +#define BP_PXP_PS_CLRKEYLOW_PIXEL 0 +#define BM_PXP_PS_CLRKEYLOW_PIXEL 0x00FFFFFF +#define BF_PXP_PS_CLRKEYLOW_PIXEL(v) \ + (((v) << 0) & BM_PXP_PS_CLRKEYLOW_PIXEL) + +#define HW_PXP_PS_CLRKEYHIGH (0x00000140) + +#define BP_PXP_PS_CLRKEYHIGH_RSVD1 24 +#define BM_PXP_PS_CLRKEYHIGH_RSVD1 0xFF000000 +#define BF_PXP_PS_CLRKEYHIGH_RSVD1(v) \ + (((v) << 24) & BM_PXP_PS_CLRKEYHIGH_RSVD1) +#define BP_PXP_PS_CLRKEYHIGH_PIXEL 0 +#define BM_PXP_PS_CLRKEYHIGH_PIXEL 0x00FFFFFF +#define BF_PXP_PS_CLRKEYHIGH_PIXEL(v) \ + (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_PIXEL) + +#define HW_PXP_AS_CTRL (0x00000150) + +#define BP_PXP_AS_CTRL_RSVD1 21 +#define BM_PXP_AS_CTRL_RSVD1 0xFFE00000 +#define BF_PXP_AS_CTRL_RSVD1(v) \ + (((v) << 21) & BM_PXP_AS_CTRL_RSVD1) +#define BM_PXP_AS_CTRL_ALPHA_INVERT 0x00100000 +#define BP_PXP_AS_CTRL_ROP 16 +#define BM_PXP_AS_CTRL_ROP 0x000F0000 +#define BF_PXP_AS_CTRL_ROP(v) \ + (((v) << 16) & BM_PXP_AS_CTRL_ROP) +#define BV_PXP_AS_CTRL_ROP__MASKAS 0x0 +#define BV_PXP_AS_CTRL_ROP__MASKNOTAS 0x1 +#define BV_PXP_AS_CTRL_ROP__MASKASNOT 0x2 +#define BV_PXP_AS_CTRL_ROP__MERGEAS 0x3 +#define BV_PXP_AS_CTRL_ROP__MERGENOTAS 0x4 +#define BV_PXP_AS_CTRL_ROP__MERGEASNOT 0x5 +#define BV_PXP_AS_CTRL_ROP__NOTCOPYAS 0x6 +#define BV_PXP_AS_CTRL_ROP__NOT 0x7 +#define BV_PXP_AS_CTRL_ROP__NOTMASKAS 0x8 +#define BV_PXP_AS_CTRL_ROP__NOTMERGEAS 0x9 +#define BV_PXP_AS_CTRL_ROP__XORAS 0xA +#define BV_PXP_AS_CTRL_ROP__NOTXORAS 0xB +#define BP_PXP_AS_CTRL_ALPHA 8 +#define BM_PXP_AS_CTRL_ALPHA 0x0000FF00 +#define BF_PXP_AS_CTRL_ALPHA(v) \ + (((v) << 8) & BM_PXP_AS_CTRL_ALPHA) +#define BP_PXP_AS_CTRL_FORMAT 4 +#define BM_PXP_AS_CTRL_FORMAT 0x000000F0 +#define BF_PXP_AS_CTRL_FORMAT(v) \ + (((v) << 4) & BM_PXP_AS_CTRL_FORMAT) +#define BV_PXP_AS_CTRL_FORMAT__ARGB8888 0x0 +#define BV_PXP_AS_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_AS_CTRL_FORMAT__ARGB1555 0x8 +#define BV_PXP_AS_CTRL_FORMAT__ARGB4444 0x9 +#define BV_PXP_AS_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_AS_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_AS_CTRL_FORMAT__RGB565 0xE +#define BM_PXP_AS_CTRL_ENABLE_COLORKEY 0x00000008 +#define BP_PXP_AS_CTRL_ALPHA_CTRL 1 +#define BM_PXP_AS_CTRL_ALPHA_CTRL 0x00000006 +#define BF_PXP_AS_CTRL_ALPHA_CTRL(v) \ + (((v) << 1) & BM_PXP_AS_CTRL_ALPHA_CTRL) +#define BV_PXP_AS_CTRL_ALPHA_CTRL__Embedded 0x0 +#define BV_PXP_AS_CTRL_ALPHA_CTRL__Override 0x1 +#define BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply 0x2 +#define BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs 0x3 +#define BM_PXP_AS_CTRL_RSVD0 0x00000001 + +#define HW_PXP_AS_BUF (0x00000160) + +#define BP_PXP_AS_BUF_ADDR 0 +#define BM_PXP_AS_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_AS_BUF_ADDR(v) (v) + +#define HW_PXP_AS_PITCH (0x00000170) + +#define BP_PXP_AS_PITCH_RSVD 16 +#define BM_PXP_AS_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_AS_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_AS_PITCH_RSVD) +#define BP_PXP_AS_PITCH_PITCH 0 +#define BM_PXP_AS_PITCH_PITCH 0x0000FFFF +#define BF_PXP_AS_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_AS_PITCH_PITCH) + +#define HW_PXP_AS_CLRKEYLOW (0x00000180) + +#define BP_PXP_AS_CLRKEYLOW_RSVD1 24 +#define BM_PXP_AS_CLRKEYLOW_RSVD1 0xFF000000 +#define BF_PXP_AS_CLRKEYLOW_RSVD1(v) \ + (((v) << 24) & BM_PXP_AS_CLRKEYLOW_RSVD1) +#define BP_PXP_AS_CLRKEYLOW_PIXEL 0 +#define BM_PXP_AS_CLRKEYLOW_PIXEL 0x00FFFFFF +#define BF_PXP_AS_CLRKEYLOW_PIXEL(v) \ + (((v) << 0) & BM_PXP_AS_CLRKEYLOW_PIXEL) + +#define HW_PXP_AS_CLRKEYHIGH (0x00000190) + +#define BP_PXP_AS_CLRKEYHIGH_RSVD1 24 +#define BM_PXP_AS_CLRKEYHIGH_RSVD1 0xFF000000 +#define BF_PXP_AS_CLRKEYHIGH_RSVD1(v) \ + (((v) << 24) & BM_PXP_AS_CLRKEYHIGH_RSVD1) +#define BP_PXP_AS_CLRKEYHIGH_PIXEL 0 +#define BM_PXP_AS_CLRKEYHIGH_PIXEL 0x00FFFFFF +#define BF_PXP_AS_CLRKEYHIGH_PIXEL(v) \ + (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_PIXEL) + +#define HW_PXP_CSC1_COEF0 (0x000001a0) + +#define BM_PXP_CSC1_COEF0_YCBCR_MODE 0x80000000 +#define BM_PXP_CSC1_COEF0_BYPASS 0x40000000 +#define BM_PXP_CSC1_COEF0_RSVD1 0x20000000 +#define BP_PXP_CSC1_COEF0_C0 18 +#define BM_PXP_CSC1_COEF0_C0 0x1FFC0000 +#define BF_PXP_CSC1_COEF0_C0(v) \ + (((v) << 18) & BM_PXP_CSC1_COEF0_C0) +#define BP_PXP_CSC1_COEF0_UV_OFFSET 9 +#define BM_PXP_CSC1_COEF0_UV_OFFSET 0x0003FE00 +#define BF_PXP_CSC1_COEF0_UV_OFFSET(v) \ + (((v) << 9) & BM_PXP_CSC1_COEF0_UV_OFFSET) +#define BP_PXP_CSC1_COEF0_Y_OFFSET 0 +#define BM_PXP_CSC1_COEF0_Y_OFFSET 0x000001FF +#define BF_PXP_CSC1_COEF0_Y_OFFSET(v) \ + (((v) << 0) & BM_PXP_CSC1_COEF0_Y_OFFSET) + +#define HW_PXP_CSC1_COEF1 (0x000001b0) + +#define BP_PXP_CSC1_COEF1_RSVD1 27 +#define BM_PXP_CSC1_COEF1_RSVD1 0xF8000000 +#define BF_PXP_CSC1_COEF1_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC1_COEF1_RSVD1) +#define BP_PXP_CSC1_COEF1_C1 16 +#define BM_PXP_CSC1_COEF1_C1 0x07FF0000 +#define BF_PXP_CSC1_COEF1_C1(v) \ + (((v) << 16) & BM_PXP_CSC1_COEF1_C1) +#define BP_PXP_CSC1_COEF1_RSVD0 11 +#define BM_PXP_CSC1_COEF1_RSVD0 0x0000F800 +#define BF_PXP_CSC1_COEF1_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC1_COEF1_RSVD0) +#define BP_PXP_CSC1_COEF1_C4 0 +#define BM_PXP_CSC1_COEF1_C4 0x000007FF +#define BF_PXP_CSC1_COEF1_C4(v) \ + (((v) << 0) & BM_PXP_CSC1_COEF1_C4) + +#define HW_PXP_CSC1_COEF2 (0x000001c0) + +#define BP_PXP_CSC1_COEF2_RSVD1 27 +#define BM_PXP_CSC1_COEF2_RSVD1 0xF8000000 +#define BF_PXP_CSC1_COEF2_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC1_COEF2_RSVD1) +#define BP_PXP_CSC1_COEF2_C2 16 +#define BM_PXP_CSC1_COEF2_C2 0x07FF0000 +#define BF_PXP_CSC1_COEF2_C2(v) \ + (((v) << 16) & BM_PXP_CSC1_COEF2_C2) +#define BP_PXP_CSC1_COEF2_RSVD0 11 +#define BM_PXP_CSC1_COEF2_RSVD0 0x0000F800 +#define BF_PXP_CSC1_COEF2_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC1_COEF2_RSVD0) +#define BP_PXP_CSC1_COEF2_C3 0 +#define BM_PXP_CSC1_COEF2_C3 0x000007FF +#define BF_PXP_CSC1_COEF2_C3(v) \ + (((v) << 0) & BM_PXP_CSC1_COEF2_C3) + +#define HW_PXP_CSC2_CTRL (0x000001d0) + +#define BP_PXP_CSC2_CTRL_RSVD 3 +#define BM_PXP_CSC2_CTRL_RSVD 0xFFFFFFF8 +#define BF_PXP_CSC2_CTRL_RSVD(v) \ + (((v) << 3) & BM_PXP_CSC2_CTRL_RSVD) +#define BP_PXP_CSC2_CTRL_CSC_MODE 1 +#define BM_PXP_CSC2_CTRL_CSC_MODE 0x00000006 +#define BF_PXP_CSC2_CTRL_CSC_MODE(v) \ + (((v) << 1) & BM_PXP_CSC2_CTRL_CSC_MODE) +#define BV_PXP_CSC2_CTRL_CSC_MODE__YUV2RGB 0x0 +#define BV_PXP_CSC2_CTRL_CSC_MODE__YCbCr2RGB 0x1 +#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YUV 0x2 +#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YCbCr 0x3 +#define BM_PXP_CSC2_CTRL_BYPASS 0x00000001 + +#define HW_PXP_CSC2_COEF0 (0x000001e0) + +#define BP_PXP_CSC2_COEF0_RSVD1 27 +#define BM_PXP_CSC2_COEF0_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF0_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF0_RSVD1) +#define BP_PXP_CSC2_COEF0_A2 16 +#define BM_PXP_CSC2_COEF0_A2 0x07FF0000 +#define BF_PXP_CSC2_COEF0_A2(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF0_A2) +#define BP_PXP_CSC2_COEF0_RSVD0 11 +#define BM_PXP_CSC2_COEF0_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF0_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF0_RSVD0) +#define BP_PXP_CSC2_COEF0_A1 0 +#define BM_PXP_CSC2_COEF0_A1 0x000007FF +#define BF_PXP_CSC2_COEF0_A1(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF0_A1) + +#define HW_PXP_CSC2_COEF1 (0x000001f0) + +#define BP_PXP_CSC2_COEF1_RSVD1 27 +#define BM_PXP_CSC2_COEF1_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF1_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF1_RSVD1) +#define BP_PXP_CSC2_COEF1_B1 16 +#define BM_PXP_CSC2_COEF1_B1 0x07FF0000 +#define BF_PXP_CSC2_COEF1_B1(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF1_B1) +#define BP_PXP_CSC2_COEF1_RSVD0 11 +#define BM_PXP_CSC2_COEF1_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF1_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF1_RSVD0) +#define BP_PXP_CSC2_COEF1_A3 0 +#define BM_PXP_CSC2_COEF1_A3 0x000007FF +#define BF_PXP_CSC2_COEF1_A3(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF1_A3) + +#define HW_PXP_CSC2_COEF2 (0x00000200) + +#define BP_PXP_CSC2_COEF2_RSVD1 27 +#define BM_PXP_CSC2_COEF2_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF2_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF2_RSVD1) +#define BP_PXP_CSC2_COEF2_B3 16 +#define BM_PXP_CSC2_COEF2_B3 0x07FF0000 +#define BF_PXP_CSC2_COEF2_B3(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF2_B3) +#define BP_PXP_CSC2_COEF2_RSVD0 11 +#define BM_PXP_CSC2_COEF2_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF2_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF2_RSVD0) +#define BP_PXP_CSC2_COEF2_B2 0 +#define BM_PXP_CSC2_COEF2_B2 0x000007FF +#define BF_PXP_CSC2_COEF2_B2(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF2_B2) + +#define HW_PXP_CSC2_COEF3 (0x00000210) + +#define BP_PXP_CSC2_COEF3_RSVD1 27 +#define BM_PXP_CSC2_COEF3_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF3_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF3_RSVD1) +#define BP_PXP_CSC2_COEF3_C2 16 +#define BM_PXP_CSC2_COEF3_C2 0x07FF0000 +#define BF_PXP_CSC2_COEF3_C2(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF3_C2) +#define BP_PXP_CSC2_COEF3_RSVD0 11 +#define BM_PXP_CSC2_COEF3_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF3_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF3_RSVD0) +#define BP_PXP_CSC2_COEF3_C1 0 +#define BM_PXP_CSC2_COEF3_C1 0x000007FF +#define BF_PXP_CSC2_COEF3_C1(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF3_C1) + +#define HW_PXP_CSC2_COEF4 (0x00000220) + +#define BP_PXP_CSC2_COEF4_RSVD1 25 +#define BM_PXP_CSC2_COEF4_RSVD1 0xFE000000 +#define BF_PXP_CSC2_COEF4_RSVD1(v) \ + (((v) << 25) & BM_PXP_CSC2_COEF4_RSVD1) +#define BP_PXP_CSC2_COEF4_D1 16 +#define BM_PXP_CSC2_COEF4_D1 0x01FF0000 +#define BF_PXP_CSC2_COEF4_D1(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF4_D1) +#define BP_PXP_CSC2_COEF4_RSVD0 11 +#define BM_PXP_CSC2_COEF4_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF4_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF4_RSVD0) +#define BP_PXP_CSC2_COEF4_C3 0 +#define BM_PXP_CSC2_COEF4_C3 0x000007FF +#define BF_PXP_CSC2_COEF4_C3(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF4_C3) + +#define HW_PXP_CSC2_COEF5 (0x00000230) + +#define BP_PXP_CSC2_COEF5_RSVD1 25 +#define BM_PXP_CSC2_COEF5_RSVD1 0xFE000000 +#define BF_PXP_CSC2_COEF5_RSVD1(v) \ + (((v) << 25) & BM_PXP_CSC2_COEF5_RSVD1) +#define BP_PXP_CSC2_COEF5_D3 16 +#define BM_PXP_CSC2_COEF5_D3 0x01FF0000 +#define BF_PXP_CSC2_COEF5_D3(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF5_D3) +#define BP_PXP_CSC2_COEF5_RSVD0 9 +#define BM_PXP_CSC2_COEF5_RSVD0 0x0000FE00 +#define BF_PXP_CSC2_COEF5_RSVD0(v) \ + (((v) << 9) & BM_PXP_CSC2_COEF5_RSVD0) +#define BP_PXP_CSC2_COEF5_D2 0 +#define BM_PXP_CSC2_COEF5_D2 0x000001FF +#define BF_PXP_CSC2_COEF5_D2(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF5_D2) + +#define HW_PXP_LUT_CTRL (0x00000240) + +#define BM_PXP_LUT_CTRL_BYPASS 0x80000000 +#define BP_PXP_LUT_CTRL_RSVD3 26 +#define BM_PXP_LUT_CTRL_RSVD3 0x7C000000 +#define BF_PXP_LUT_CTRL_RSVD3(v) \ + (((v) << 26) & BM_PXP_LUT_CTRL_RSVD3) +#define BP_PXP_LUT_CTRL_LOOKUP_MODE 24 +#define BM_PXP_LUT_CTRL_LOOKUP_MODE 0x03000000 +#define BF_PXP_LUT_CTRL_LOOKUP_MODE(v) \ + (((v) << 24) & BM_PXP_LUT_CTRL_LOOKUP_MODE) +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__CACHE_RGB565 0x0 +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8 0x1 +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB444 0x2 +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB454 0x3 +#define BP_PXP_LUT_CTRL_RSVD2 18 +#define BM_PXP_LUT_CTRL_RSVD2 0x00FC0000 +#define BF_PXP_LUT_CTRL_RSVD2(v) \ + (((v) << 18) & BM_PXP_LUT_CTRL_RSVD2) +#define BP_PXP_LUT_CTRL_OUT_MODE 16 +#define BM_PXP_LUT_CTRL_OUT_MODE 0x00030000 +#define BF_PXP_LUT_CTRL_OUT_MODE(v) \ + (((v) << 16) & BM_PXP_LUT_CTRL_OUT_MODE) +#define BV_PXP_LUT_CTRL_OUT_MODE__RESERVED 0x0 +#define BV_PXP_LUT_CTRL_OUT_MODE__Y8 0x1 +#define BV_PXP_LUT_CTRL_OUT_MODE__RGBW4444CFA 0x2 +#define BV_PXP_LUT_CTRL_OUT_MODE__RGB888 0x3 +#define BP_PXP_LUT_CTRL_RSVD1 11 +#define BM_PXP_LUT_CTRL_RSVD1 0x0000F800 +#define BF_PXP_LUT_CTRL_RSVD1(v) \ + (((v) << 11) & BM_PXP_LUT_CTRL_RSVD1) +#define BM_PXP_LUT_CTRL_SEL_8KB 0x00000400 +#define BM_PXP_LUT_CTRL_LRU_UPD 0x00000200 +#define BM_PXP_LUT_CTRL_INVALID 0x00000100 +#define BP_PXP_LUT_CTRL_RSVD0 1 +#define BM_PXP_LUT_CTRL_RSVD0 0x000000FE +#define BF_PXP_LUT_CTRL_RSVD0(v) \ + (((v) << 1) & BM_PXP_LUT_CTRL_RSVD0) +#define BM_PXP_LUT_CTRL_DMA_START 0x00000001 + +#define HW_PXP_LUT_ADDR (0x00000250) + +#define BM_PXP_LUT_ADDR_RSVD2 0x80000000 +#define BP_PXP_LUT_ADDR_NUM_BYTES 16 +#define BM_PXP_LUT_ADDR_NUM_BYTES 0x7FFF0000 +#define BF_PXP_LUT_ADDR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_LUT_ADDR_NUM_BYTES) +#define BP_PXP_LUT_ADDR_RSVD1 14 +#define BM_PXP_LUT_ADDR_RSVD1 0x0000C000 +#define BF_PXP_LUT_ADDR_RSVD1(v) \ + (((v) << 14) & BM_PXP_LUT_ADDR_RSVD1) +#define BP_PXP_LUT_ADDR_ADDR 0 +#define BM_PXP_LUT_ADDR_ADDR 0x00003FFF +#define BF_PXP_LUT_ADDR_ADDR(v) \ + (((v) << 0) & BM_PXP_LUT_ADDR_ADDR) + +#define HW_PXP_LUT_DATA (0x00000260) + +#define BP_PXP_LUT_DATA_DATA 0 +#define BM_PXP_LUT_DATA_DATA 0xFFFFFFFF +#define BF_PXP_LUT_DATA_DATA(v) (v) + +#define HW_PXP_LUT_EXTMEM (0x00000270) + +#define BP_PXP_LUT_EXTMEM_ADDR 0 +#define BM_PXP_LUT_EXTMEM_ADDR 0xFFFFFFFF +#define BF_PXP_LUT_EXTMEM_ADDR(v) (v) + +#define HW_PXP_CFA (0x00000280) + +#define BP_PXP_CFA_DATA 0 +#define BM_PXP_CFA_DATA 0xFFFFFFFF +#define BF_PXP_CFA_DATA(v) (v) + +#define HW_PXP_HIST_CTRL (0x00000290) + +#define BP_PXP_HIST_CTRL_RSVD 6 +#define BM_PXP_HIST_CTRL_RSVD 0xFFFFFFC0 +#define BF_PXP_HIST_CTRL_RSVD(v) \ + (((v) << 6) & BM_PXP_HIST_CTRL_RSVD) +#define BP_PXP_HIST_CTRL_PANEL_MODE 4 +#define BM_PXP_HIST_CTRL_PANEL_MODE 0x00000030 +#define BF_PXP_HIST_CTRL_PANEL_MODE(v) \ + (((v) << 4) & BM_PXP_HIST_CTRL_PANEL_MODE) +#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY4 0x0 +#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY8 0x1 +#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY16 0x2 +#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY32 0x3 +#define BP_PXP_HIST_CTRL_STATUS 0 +#define BM_PXP_HIST_CTRL_STATUS 0x0000000F +#define BF_PXP_HIST_CTRL_STATUS(v) \ + (((v) << 0) & BM_PXP_HIST_CTRL_STATUS) + +#define HW_PXP_HIST2_PARAM (0x000002a0) + +#define BP_PXP_HIST2_PARAM_RSVD 16 +#define BM_PXP_HIST2_PARAM_RSVD 0xFFFF0000 +#define BF_PXP_HIST2_PARAM_RSVD(v) \ + (((v) << 16) & BM_PXP_HIST2_PARAM_RSVD) +#define BP_PXP_HIST2_PARAM_RSVD1 13 +#define BM_PXP_HIST2_PARAM_RSVD1 0x0000E000 +#define BF_PXP_HIST2_PARAM_RSVD1(v) \ + (((v) << 13) & BM_PXP_HIST2_PARAM_RSVD1) +#define BP_PXP_HIST2_PARAM_VALUE1 8 +#define BM_PXP_HIST2_PARAM_VALUE1 0x00001F00 +#define BF_PXP_HIST2_PARAM_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST2_PARAM_VALUE1) +#define BP_PXP_HIST2_PARAM_RSVD0 5 +#define BM_PXP_HIST2_PARAM_RSVD0 0x000000E0 +#define BF_PXP_HIST2_PARAM_RSVD0(v) \ + (((v) << 5) & BM_PXP_HIST2_PARAM_RSVD0) +#define BP_PXP_HIST2_PARAM_VALUE0 0 +#define BM_PXP_HIST2_PARAM_VALUE0 0x0000001F +#define BF_PXP_HIST2_PARAM_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST2_PARAM_VALUE0) + +#define HW_PXP_HIST4_PARAM (0x000002b0) + +#define BP_PXP_HIST4_PARAM_RSVD3 29 +#define BM_PXP_HIST4_PARAM_RSVD3 0xE0000000 +#define BF_PXP_HIST4_PARAM_RSVD3(v) \ + (((v) << 29) & BM_PXP_HIST4_PARAM_RSVD3) +#define BP_PXP_HIST4_PARAM_VALUE3 24 +#define BM_PXP_HIST4_PARAM_VALUE3 0x1F000000 +#define BF_PXP_HIST4_PARAM_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST4_PARAM_VALUE3) +#define BP_PXP_HIST4_PARAM_RSVD2 21 +#define BM_PXP_HIST4_PARAM_RSVD2 0x00E00000 +#define BF_PXP_HIST4_PARAM_RSVD2(v) \ + (((v) << 21) & BM_PXP_HIST4_PARAM_RSVD2) +#define BP_PXP_HIST4_PARAM_VALUE2 16 +#define BM_PXP_HIST4_PARAM_VALUE2 0x001F0000 +#define BF_PXP_HIST4_PARAM_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST4_PARAM_VALUE2) +#define BP_PXP_HIST4_PARAM_RSVD1 13 +#define BM_PXP_HIST4_PARAM_RSVD1 0x0000E000 +#define BF_PXP_HIST4_PARAM_RSVD1(v) \ + (((v) << 13) & BM_PXP_HIST4_PARAM_RSVD1) +#define BP_PXP_HIST4_PARAM_VALUE1 8 +#define BM_PXP_HIST4_PARAM_VALUE1 0x00001F00 +#define BF_PXP_HIST4_PARAM_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST4_PARAM_VALUE1) +#define BP_PXP_HIST4_PARAM_RSVD0 5 +#define BM_PXP_HIST4_PARAM_RSVD0 0x000000E0 +#define BF_PXP_HIST4_PARAM_RSVD0(v) \ + (((v) << 5) & BM_PXP_HIST4_PARAM_RSVD0) +#define BP_PXP_HIST4_PARAM_VALUE0 0 +#define BM_PXP_HIST4_PARAM_VALUE0 0x0000001F +#define BF_PXP_HIST4_PARAM_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST4_PARAM_VALUE0) + +#define HW_PXP_HIST8_PARAM0 (0x000002c0) + +#define BP_PXP_HIST8_PARAM0_RSVD3 29 +#define BM_PXP_HIST8_PARAM0_RSVD3 0xE0000000 +#define BF_PXP_HIST8_PARAM0_RSVD3(v) \ + (((v) << 29) & BM_PXP_HIST8_PARAM0_RSVD3) +#define BP_PXP_HIST8_PARAM0_VALUE3 24 +#define BM_PXP_HIST8_PARAM0_VALUE3 0x1F000000 +#define BF_PXP_HIST8_PARAM0_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST8_PARAM0_VALUE3) +#define BP_PXP_HIST8_PARAM0_RSVD2 21 +#define BM_PXP_HIST8_PARAM0_RSVD2 0x00E00000 +#define BF_PXP_HIST8_PARAM0_RSVD2(v) \ + (((v) << 21) & BM_PXP_HIST8_PARAM0_RSVD2) +#define BP_PXP_HIST8_PARAM0_VALUE2 16 +#define BM_PXP_HIST8_PARAM0_VALUE2 0x001F0000 +#define BF_PXP_HIST8_PARAM0_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST8_PARAM0_VALUE2) +#define BP_PXP_HIST8_PARAM0_RSVD1 13 +#define BM_PXP_HIST8_PARAM0_RSVD1 0x0000E000 +#define BF_PXP_HIST8_PARAM0_RSVD1(v) \ + (((v) << 13) & BM_PXP_HIST8_PARAM0_RSVD1) +#define BP_PXP_HIST8_PARAM0_VALUE1 8 +#define BM_PXP_HIST8_PARAM0_VALUE1 0x00001F00 +#define BF_PXP_HIST8_PARAM0_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST8_PARAM0_VALUE1) +#define BP_PXP_HIST8_PARAM0_RSVD0 5 +#define BM_PXP_HIST8_PARAM0_RSVD0 0x000000E0 +#define BF_PXP_HIST8_PARAM0_RSVD0(v) \ + (((v) << 5) & BM_PXP_HIST8_PARAM0_RSVD0) +#define BP_PXP_HIST8_PARAM0_VALUE0 0 +#define BM_PXP_HIST8_PARAM0_VALUE0 0x0000001F +#define BF_PXP_HIST8_PARAM0_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST8_PARAM0_VALUE0) + +#define HW_PXP_HIST8_PARAM1 (0x000002d0) + +#define BP_PXP_HIST8_PARAM1_RSVD7 29 +#define BM_PXP_HIST8_PARAM1_RSVD7 0xE0000000 +#define BF_PXP_HIST8_PARAM1_RSVD7(v) \ + (((v) << 29) & BM_PXP_HIST8_PARAM1_RSVD7) +#define BP_PXP_HIST8_PARAM1_VALUE7 24 +#define BM_PXP_HIST8_PARAM1_VALUE7 0x1F000000 +#define BF_PXP_HIST8_PARAM1_VALUE7(v) \ + (((v) << 24) & BM_PXP_HIST8_PARAM1_VALUE7) +#define BP_PXP_HIST8_PARAM1_RSVD6 21 +#define BM_PXP_HIST8_PARAM1_RSVD6 0x00E00000 +#define BF_PXP_HIST8_PARAM1_RSVD6(v) \ + (((v) << 21) & BM_PXP_HIST8_PARAM1_RSVD6) +#define BP_PXP_HIST8_PARAM1_VALUE6 16 +#define BM_PXP_HIST8_PARAM1_VALUE6 0x001F0000 +#define BF_PXP_HIST8_PARAM1_VALUE6(v) \ + (((v) << 16) & BM_PXP_HIST8_PARAM1_VALUE6) +#define BP_PXP_HIST8_PARAM1_RSVD5 13 +#define BM_PXP_HIST8_PARAM1_RSVD5 0x0000E000 +#define BF_PXP_HIST8_PARAM1_RSVD5(v) \ + (((v) << 13) & BM_PXP_HIST8_PARAM1_RSVD5) +#define BP_PXP_HIST8_PARAM1_VALUE5 8 +#define BM_PXP_HIST8_PARAM1_VALUE5 0x00001F00 +#define BF_PXP_HIST8_PARAM1_VALUE5(v) \ + (((v) << 8) & BM_PXP_HIST8_PARAM1_VALUE5) +#define BP_PXP_HIST8_PARAM1_RSVD4 5 +#define BM_PXP_HIST8_PARAM1_RSVD4 0x000000E0 +#define BF_PXP_HIST8_PARAM1_RSVD4(v) \ + (((v) << 5) & BM_PXP_HIST8_PARAM1_RSVD4) +#define BP_PXP_HIST8_PARAM1_VALUE4 0 +#define BM_PXP_HIST8_PARAM1_VALUE4 0x0000001F +#define BF_PXP_HIST8_PARAM1_VALUE4(v) \ + (((v) << 0) & BM_PXP_HIST8_PARAM1_VALUE4) + +#define HW_PXP_HIST16_PARAM0 (0x000002e0) + +#define BP_PXP_HIST16_PARAM0_RSVD3 29 +#define BM_PXP_HIST16_PARAM0_RSVD3 0xE0000000 +#define BF_PXP_HIST16_PARAM0_RSVD3(v) \ + (((v) << 29) & BM_PXP_HIST16_PARAM0_RSVD3) +#define BP_PXP_HIST16_PARAM0_VALUE3 24 +#define BM_PXP_HIST16_PARAM0_VALUE3 0x1F000000 +#define BF_PXP_HIST16_PARAM0_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM0_VALUE3) +#define BP_PXP_HIST16_PARAM0_RSVD2 21 +#define BM_PXP_HIST16_PARAM0_RSVD2 0x00E00000 +#define BF_PXP_HIST16_PARAM0_RSVD2(v) \ + (((v) << 21) & BM_PXP_HIST16_PARAM0_RSVD2) +#define BP_PXP_HIST16_PARAM0_VALUE2 16 +#define BM_PXP_HIST16_PARAM0_VALUE2 0x001F0000 +#define BF_PXP_HIST16_PARAM0_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM0_VALUE2) +#define BP_PXP_HIST16_PARAM0_RSVD1 13 +#define BM_PXP_HIST16_PARAM0_RSVD1 0x0000E000 +#define BF_PXP_HIST16_PARAM0_RSVD1(v) \ + (((v) << 13) & BM_PXP_HIST16_PARAM0_RSVD1) +#define BP_PXP_HIST16_PARAM0_VALUE1 8 +#define BM_PXP_HIST16_PARAM0_VALUE1 0x00001F00 +#define BF_PXP_HIST16_PARAM0_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM0_VALUE1) +#define BP_PXP_HIST16_PARAM0_RSVD0 5 +#define BM_PXP_HIST16_PARAM0_RSVD0 0x000000E0 +#define BF_PXP_HIST16_PARAM0_RSVD0(v) \ + (((v) << 5) & BM_PXP_HIST16_PARAM0_RSVD0) +#define BP_PXP_HIST16_PARAM0_VALUE0 0 +#define BM_PXP_HIST16_PARAM0_VALUE0 0x0000001F +#define BF_PXP_HIST16_PARAM0_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM0_VALUE0) + +#define HW_PXP_HIST16_PARAM1 (0x000002f0) + +#define BP_PXP_HIST16_PARAM1_RSVD7 29 +#define BM_PXP_HIST16_PARAM1_RSVD7 0xE0000000 +#define BF_PXP_HIST16_PARAM1_RSVD7(v) \ + (((v) << 29) & BM_PXP_HIST16_PARAM1_RSVD7) +#define BP_PXP_HIST16_PARAM1_VALUE7 24 +#define BM_PXP_HIST16_PARAM1_VALUE7 0x1F000000 +#define BF_PXP_HIST16_PARAM1_VALUE7(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM1_VALUE7) +#define BP_PXP_HIST16_PARAM1_RSVD6 21 +#define BM_PXP_HIST16_PARAM1_RSVD6 0x00E00000 +#define BF_PXP_HIST16_PARAM1_RSVD6(v) \ + (((v) << 21) & BM_PXP_HIST16_PARAM1_RSVD6) +#define BP_PXP_HIST16_PARAM1_VALUE6 16 +#define BM_PXP_HIST16_PARAM1_VALUE6 0x001F0000 +#define BF_PXP_HIST16_PARAM1_VALUE6(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM1_VALUE6) +#define BP_PXP_HIST16_PARAM1_RSVD5 13 +#define BM_PXP_HIST16_PARAM1_RSVD5 0x0000E000 +#define BF_PXP_HIST16_PARAM1_RSVD5(v) \ + (((v) << 13) & BM_PXP_HIST16_PARAM1_RSVD5) +#define BP_PXP_HIST16_PARAM1_VALUE5 8 +#define BM_PXP_HIST16_PARAM1_VALUE5 0x00001F00 +#define BF_PXP_HIST16_PARAM1_VALUE5(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM1_VALUE5) +#define BP_PXP_HIST16_PARAM1_RSVD4 5 +#define BM_PXP_HIST16_PARAM1_RSVD4 0x000000E0 +#define BF_PXP_HIST16_PARAM1_RSVD4(v) \ + (((v) << 5) & BM_PXP_HIST16_PARAM1_RSVD4) +#define BP_PXP_HIST16_PARAM1_VALUE4 0 +#define BM_PXP_HIST16_PARAM1_VALUE4 0x0000001F +#define BF_PXP_HIST16_PARAM1_VALUE4(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM1_VALUE4) + +#define HW_PXP_HIST16_PARAM2 (0x00000300) + +#define BP_PXP_HIST16_PARAM2_RSVD11 29 +#define BM_PXP_HIST16_PARAM2_RSVD11 0xE0000000 +#define BF_PXP_HIST16_PARAM2_RSVD11(v) \ + (((v) << 29) & BM_PXP_HIST16_PARAM2_RSVD11) +#define BP_PXP_HIST16_PARAM2_VALUE11 24 +#define BM_PXP_HIST16_PARAM2_VALUE11 0x1F000000 +#define BF_PXP_HIST16_PARAM2_VALUE11(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM2_VALUE11) +#define BP_PXP_HIST16_PARAM2_RSVD10 21 +#define BM_PXP_HIST16_PARAM2_RSVD10 0x00E00000 +#define BF_PXP_HIST16_PARAM2_RSVD10(v) \ + (((v) << 21) & BM_PXP_HIST16_PARAM2_RSVD10) +#define BP_PXP_HIST16_PARAM2_VALUE10 16 +#define BM_PXP_HIST16_PARAM2_VALUE10 0x001F0000 +#define BF_PXP_HIST16_PARAM2_VALUE10(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM2_VALUE10) +#define BP_PXP_HIST16_PARAM2_RSVD9 13 +#define BM_PXP_HIST16_PARAM2_RSVD9 0x0000E000 +#define BF_PXP_HIST16_PARAM2_RSVD9(v) \ + (((v) << 13) & BM_PXP_HIST16_PARAM2_RSVD9) +#define BP_PXP_HIST16_PARAM2_VALUE9 8 +#define BM_PXP_HIST16_PARAM2_VALUE9 0x00001F00 +#define BF_PXP_HIST16_PARAM2_VALUE9(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM2_VALUE9) +#define BP_PXP_HIST16_PARAM2_RSVD8 5 +#define BM_PXP_HIST16_PARAM2_RSVD8 0x000000E0 +#define BF_PXP_HIST16_PARAM2_RSVD8(v) \ + (((v) << 5) & BM_PXP_HIST16_PARAM2_RSVD8) +#define BP_PXP_HIST16_PARAM2_VALUE8 0 +#define BM_PXP_HIST16_PARAM2_VALUE8 0x0000001F +#define BF_PXP_HIST16_PARAM2_VALUE8(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM2_VALUE8) + +#define HW_PXP_HIST16_PARAM3 (0x00000310) + +#define BP_PXP_HIST16_PARAM3_RSVD15 29 +#define BM_PXP_HIST16_PARAM3_RSVD15 0xE0000000 +#define BF_PXP_HIST16_PARAM3_RSVD15(v) \ + (((v) << 29) & BM_PXP_HIST16_PARAM3_RSVD15) +#define BP_PXP_HIST16_PARAM3_VALUE15 24 +#define BM_PXP_HIST16_PARAM3_VALUE15 0x1F000000 +#define BF_PXP_HIST16_PARAM3_VALUE15(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM3_VALUE15) +#define BP_PXP_HIST16_PARAM3_RSVD14 21 +#define BM_PXP_HIST16_PARAM3_RSVD14 0x00E00000 +#define BF_PXP_HIST16_PARAM3_RSVD14(v) \ + (((v) << 21) & BM_PXP_HIST16_PARAM3_RSVD14) +#define BP_PXP_HIST16_PARAM3_VALUE14 16 +#define BM_PXP_HIST16_PARAM3_VALUE14 0x001F0000 +#define BF_PXP_HIST16_PARAM3_VALUE14(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM3_VALUE14) +#define BP_PXP_HIST16_PARAM3_RSVD13 13 +#define BM_PXP_HIST16_PARAM3_RSVD13 0x0000E000 +#define BF_PXP_HIST16_PARAM3_RSVD13(v) \ + (((v) << 13) & BM_PXP_HIST16_PARAM3_RSVD13) +#define BP_PXP_HIST16_PARAM3_VALUE13 8 +#define BM_PXP_HIST16_PARAM3_VALUE13 0x00001F00 +#define BF_PXP_HIST16_PARAM3_VALUE13(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM3_VALUE13) +#define BP_PXP_HIST16_PARAM3_RSVD12 5 +#define BM_PXP_HIST16_PARAM3_RSVD12 0x000000E0 +#define BF_PXP_HIST16_PARAM3_RSVD12(v) \ + (((v) << 5) & BM_PXP_HIST16_PARAM3_RSVD12) +#define BP_PXP_HIST16_PARAM3_VALUE12 0 +#define BM_PXP_HIST16_PARAM3_VALUE12 0x0000001F +#define BF_PXP_HIST16_PARAM3_VALUE12(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM3_VALUE12) + +#define HW_PXP_POWER (0x00000320) + +#define BP_PXP_POWER_CTRL 12 +#define BM_PXP_POWER_CTRL 0xFFFFF000 +#define BF_PXP_POWER_CTRL(v) \ + (((v) << 12) & BM_PXP_POWER_CTRL) +#define BP_PXP_POWER_ROT_MEM_LP_STATE 9 +#define BM_PXP_POWER_ROT_MEM_LP_STATE 0x00000E00 +#define BF_PXP_POWER_ROT_MEM_LP_STATE(v) \ + (((v) << 9) & BM_PXP_POWER_ROT_MEM_LP_STATE) +#define BV_PXP_POWER_ROT_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_ROT_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_ROT_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_ROT_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_LUT_LP_STATE_WAY1_BANKN 6 +#define BM_PXP_POWER_LUT_LP_STATE_WAY1_BANKN 0x000001C0 +#define BF_PXP_POWER_LUT_LP_STATE_WAY1_BANKN(v) \ + (((v) << 6) & BM_PXP_POWER_LUT_LP_STATE_WAY1_BANKN) +#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__NONE 0x0 +#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__LS 0x1 +#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__DS 0x2 +#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__SD 0x4 +#define BP_PXP_POWER_LUT_LP_STATE_WAY0_BANKN 3 +#define BM_PXP_POWER_LUT_LP_STATE_WAY0_BANKN 0x00000038 +#define BF_PXP_POWER_LUT_LP_STATE_WAY0_BANKN(v) \ + (((v) << 3) & BM_PXP_POWER_LUT_LP_STATE_WAY0_BANKN) +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__NONE 0x0 +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__LS 0x1 +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__DS 0x2 +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__SD 0x4 +#define BP_PXP_POWER_LUT_LP_STATE_WAY0_BANK0 0 +#define BM_PXP_POWER_LUT_LP_STATE_WAY0_BANK0 0x00000007 +#define BF_PXP_POWER_LUT_LP_STATE_WAY0_BANK0(v) \ + (((v) << 0) & BM_PXP_POWER_LUT_LP_STATE_WAY0_BANK0) +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__NONE 0x0 +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__LS 0x1 +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__DS 0x2 +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__SD 0x4 + +#define HW_PXP_NEXT (0x00000400) + +#define BP_PXP_NEXT_POINTER 2 +#define BM_PXP_NEXT_POINTER 0xFFFFFFFC +#define BF_PXP_NEXT_POINTER(v) \ + (((v) << 2) & BM_PXP_NEXT_POINTER) +#define BM_PXP_NEXT_RSVD 0x00000002 +#define BM_PXP_NEXT_ENABLED 0x00000001 + +#define HW_PXP_DEBUGCTRL (0x00000410) + +#define BP_PXP_DEBUGCTRL_RSVD 12 +#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFF000 +#define BF_PXP_DEBUGCTRL_RSVD(v) \ + (((v) << 12) & BM_PXP_DEBUGCTRL_RSVD) +#define BP_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 8 +#define BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 0x00000F00 +#define BF_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT(v) \ + (((v) << 8) & BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT) +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__NONE 0x0 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MISS_CNT 0x1 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__HIT_CNT 0x2 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__LAT_CNT 0x4 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MAX_LAT 0x8 +#define BP_PXP_DEBUGCTRL_SELECT 0 +#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF +#define BF_PXP_DEBUGCTRL_SELECT(v) \ + (((v) << 0) & BM_PXP_DEBUGCTRL_SELECT) +#define BV_PXP_DEBUGCTRL_SELECT__NONE 0x0 +#define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x1 +#define BV_PXP_DEBUGCTRL_SELECT__PSBUF 0x2 +#define BV_PXP_DEBUGCTRL_SELECT__PSBAX 0x3 +#define BV_PXP_DEBUGCTRL_SELECT__PSBAY 0x4 +#define BV_PXP_DEBUGCTRL_SELECT__ASBUF 0x5 +#define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6 +#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF0 0x7 +#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF1 0x8 +#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF2 0x9 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_STAT 0x10 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_MISS 0x11 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_HIT 0x12 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_LAT 0x13 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_MAX_LAT 0x14 + +#define HW_PXP_DEBUG (0x00000420) + +#define BP_PXP_DEBUG_DATA 0 +#define BM_PXP_DEBUG_DATA 0xFFFFFFFF +#define BF_PXP_DEBUG_DATA(v) (v) + +#define HW_PXP_VERSION (0x00000430) + +#define BP_PXP_VERSION_MAJOR 24 +#define BM_PXP_VERSION_MAJOR 0xFF000000 +#define BF_PXP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_PXP_VERSION_MAJOR) +#define BP_PXP_VERSION_MINOR 16 +#define BM_PXP_VERSION_MINOR 0x00FF0000 +#define BF_PXP_VERSION_MINOR(v) \ + (((v) << 16) & BM_PXP_VERSION_MINOR) +#define BP_PXP_VERSION_STEP 0 +#define BM_PXP_VERSION_STEP 0x0000FFFF +#define BF_PXP_VERSION_STEP(v) \ + (((v) << 0) & BM_PXP_VERSION_STEP) +#endif /* __ARCH_ARM___PXP_H */ diff --git a/drivers/dma/pxp/regs-pxp_v3.h b/drivers/dma/pxp/regs-pxp_v3.h new file mode 100644 index 00000000000000..2fef8e9a169ad5 --- /dev/null +++ b/drivers/dma/pxp/regs-pxp_v3.h @@ -0,0 +1,26939 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Freescale PXP Register Definitions + * + * Copyright 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.77 + * Template revision: 1.3 + */ + +#ifndef __ARCH_ARM___PXP_H +#define __ARCH_ARM___PXP_H + + +#define HW_PXP_CTRL (0x00000000) +#define HW_PXP_CTRL_SET (0x00000004) +#define HW_PXP_CTRL_CLR (0x00000008) +#define HW_PXP_CTRL_TOG (0x0000000c) + +#define BM_PXP_CTRL_SFTRST 0x80000000 +#define BF_PXP_CTRL_SFTRST(v) \ + (((v) << 31) & BM_PXP_CTRL_SFTRST) +#define BM_PXP_CTRL_CLKGATE 0x40000000 +#define BF_PXP_CTRL_CLKGATE(v) \ + (((v) << 30) & BM_PXP_CTRL_CLKGATE) +#define BM_PXP_CTRL_RSVD4 0x20000000 +#define BF_PXP_CTRL_RSVD4(v) \ + (((v) << 29) & BM_PXP_CTRL_RSVD4) +#define BM_PXP_CTRL_EN_REPEAT 0x10000000 +#define BF_PXP_CTRL_EN_REPEAT(v) \ + (((v) << 28) & BM_PXP_CTRL_EN_REPEAT) +#define BM_PXP_CTRL_ENABLE_ROTATE1 0x08000000 +#define BF_PXP_CTRL_ENABLE_ROTATE1(v) \ + (((v) << 27) & BM_PXP_CTRL_ENABLE_ROTATE1) +#define BM_PXP_CTRL_ENABLE_ROTATE0 0x04000000 +#define BF_PXP_CTRL_ENABLE_ROTATE0(v) \ + (((v) << 26) & BM_PXP_CTRL_ENABLE_ROTATE0) +#define BM_PXP_CTRL_ENABLE_LUT 0x02000000 +#define BF_PXP_CTRL_ENABLE_LUT(v) \ + (((v) << 25) & BM_PXP_CTRL_ENABLE_LUT) +#define BM_PXP_CTRL_ENABLE_CSC2 0x01000000 +#define BF_PXP_CTRL_ENABLE_CSC2(v) \ + (((v) << 24) & BM_PXP_CTRL_ENABLE_CSC2) +#define BM_PXP_CTRL_BLOCK_SIZE 0x00800000 +#define BF_PXP_CTRL_BLOCK_SIZE(v) \ + (((v) << 23) & BM_PXP_CTRL_BLOCK_SIZE) +#define BV_PXP_CTRL_BLOCK_SIZE__8X8 0x0 +#define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x1 +#define BM_PXP_CTRL_RSVD1 0x00400000 +#define BF_PXP_CTRL_RSVD1(v) \ + (((v) << 22) & BM_PXP_CTRL_RSVD1) +#define BM_PXP_CTRL_ENABLE_ALPHA_B 0x00200000 +#define BF_PXP_CTRL_ENABLE_ALPHA_B(v) \ + (((v) << 21) & BM_PXP_CTRL_ENABLE_ALPHA_B) +#define BM_PXP_CTRL_ENABLE_INPUT_FETCH_STORE 0x00100000 +#define BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(v) \ + (((v) << 20) & BM_PXP_CTRL_ENABLE_INPUT_FETCH_STORE) +#define BM_PXP_CTRL_ENABLE_WFE_B 0x00080000 +#define BF_PXP_CTRL_ENABLE_WFE_B(v) \ + (((v) << 19) & BM_PXP_CTRL_ENABLE_WFE_B) +#define BM_PXP_CTRL_ENABLE_WFE_A 0x00040000 +#define BF_PXP_CTRL_ENABLE_WFE_A(v) \ + (((v) << 18) & BM_PXP_CTRL_ENABLE_WFE_A) +#define BM_PXP_CTRL_ENABLE_DITHER 0x00020000 +#define BF_PXP_CTRL_ENABLE_DITHER(v) \ + (((v) << 17) & BM_PXP_CTRL_ENABLE_DITHER) +#define BM_PXP_CTRL_ENABLE_PS_AS_OUT 0x00010000 +#define BF_PXP_CTRL_ENABLE_PS_AS_OUT(v) \ + (((v) << 16) & BM_PXP_CTRL_ENABLE_PS_AS_OUT) +#define BM_PXP_CTRL_VFLIP1 0x00008000 +#define BF_PXP_CTRL_VFLIP1(v) \ + (((v) << 15) & BM_PXP_CTRL_VFLIP1) +#define BM_PXP_CTRL_HFLIP1 0x00004000 +#define BF_PXP_CTRL_HFLIP1(v) \ + (((v) << 14) & BM_PXP_CTRL_HFLIP1) +#define BP_PXP_CTRL_ROTATE1 12 +#define BM_PXP_CTRL_ROTATE1 0x00003000 +#define BF_PXP_CTRL_ROTATE1(v) \ + (((v) << 12) & BM_PXP_CTRL_ROTATE1) +#define BV_PXP_CTRL_ROTATE1__ROT_0 0x0 +#define BV_PXP_CTRL_ROTATE1__ROT_90 0x1 +#define BV_PXP_CTRL_ROTATE1__ROT_180 0x2 +#define BV_PXP_CTRL_ROTATE1__ROT_270 0x3 +#define BM_PXP_CTRL_VFLIP0 0x00000800 +#define BF_PXP_CTRL_VFLIP0(v) \ + (((v) << 11) & BM_PXP_CTRL_VFLIP0) +#define BM_PXP_CTRL_HFLIP0 0x00000400 +#define BF_PXP_CTRL_HFLIP0(v) \ + (((v) << 10) & BM_PXP_CTRL_HFLIP0) +#define BP_PXP_CTRL_ROTATE0 8 +#define BM_PXP_CTRL_ROTATE0 0x00000300 +#define BF_PXP_CTRL_ROTATE0(v) \ + (((v) << 8) & BM_PXP_CTRL_ROTATE0) +#define BV_PXP_CTRL_ROTATE0__ROT_0 0x0 +#define BV_PXP_CTRL_ROTATE0__ROT_90 0x1 +#define BV_PXP_CTRL_ROTATE0__ROT_180 0x2 +#define BV_PXP_CTRL_ROTATE0__ROT_270 0x3 +#define BP_PXP_CTRL_RSVD0 6 +#define BM_PXP_CTRL_RSVD0 0x000000C0 +#define BF_PXP_CTRL_RSVD0(v) \ + (((v) << 6) & BM_PXP_CTRL_RSVD0) +#define BM_PXP_CTRL_HANDSHAKE_ABORT_SKIP 0x00000020 +#define BF_PXP_CTRL_HANDSHAKE_ABORT_SKIP(v) \ + (((v) << 5) & BM_PXP_CTRL_HANDSHAKE_ABORT_SKIP) +#define BM_PXP_CTRL_ENABLE_LCD0_HANDSHAKE 0x00000010 +#define BF_PXP_CTRL_ENABLE_LCD0_HANDSHAKE(v) \ + (((v) << 4) & BM_PXP_CTRL_ENABLE_LCD0_HANDSHAKE) +#define BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE 0x00000008 +#define BF_PXP_CTRL_LUT_DMA_IRQ_ENABLE(v) \ + (((v) << 3) & BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE) +#define BM_PXP_CTRL_NEXT_IRQ_ENABLE 0x00000004 +#define BF_PXP_CTRL_NEXT_IRQ_ENABLE(v) \ + (((v) << 2) & BM_PXP_CTRL_NEXT_IRQ_ENABLE) +#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 +#define BF_PXP_CTRL_IRQ_ENABLE(v) \ + (((v) << 1) & BM_PXP_CTRL_IRQ_ENABLE) +#define BM_PXP_CTRL_ENABLE 0x00000001 +#define BF_PXP_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_CTRL_ENABLE) + +#define HW_PXP_STAT (0x00000010) +#define HW_PXP_STAT_SET (0x00000014) +#define HW_PXP_STAT_CLR (0x00000018) +#define HW_PXP_STAT_TOG (0x0000001c) + +#define BP_PXP_STAT_BLOCKX 24 +#define BM_PXP_STAT_BLOCKX 0xFF000000 +#define BF_PXP_STAT_BLOCKX(v) \ + (((v) << 24) & BM_PXP_STAT_BLOCKX) +#define BP_PXP_STAT_BLOCKY 16 +#define BM_PXP_STAT_BLOCKY 0x00FF0000 +#define BF_PXP_STAT_BLOCKY(v) \ + (((v) << 16) & BM_PXP_STAT_BLOCKY) +#define BP_PXP_STAT_AXI_ERROR_ID_1 12 +#define BM_PXP_STAT_AXI_ERROR_ID_1 0x0000F000 +#define BF_PXP_STAT_AXI_ERROR_ID_1(v) \ + (((v) << 12) & BM_PXP_STAT_AXI_ERROR_ID_1) +#define BM_PXP_STAT_RSVD2 0x00000800 +#define BF_PXP_STAT_RSVD2(v) \ + (((v) << 11) & BM_PXP_STAT_RSVD2) +#define BM_PXP_STAT_AXI_READ_ERROR_1 0x00000400 +#define BF_PXP_STAT_AXI_READ_ERROR_1(v) \ + (((v) << 10) & BM_PXP_STAT_AXI_READ_ERROR_1) +#define BM_PXP_STAT_AXI_WRITE_ERROR_1 0x00000200 +#define BF_PXP_STAT_AXI_WRITE_ERROR_1(v) \ + (((v) << 9) & BM_PXP_STAT_AXI_WRITE_ERROR_1) +#define BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ 0x00000100 +#define BF_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(v) \ + (((v) << 8) & BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ) +#define BP_PXP_STAT_AXI_ERROR_ID_0 4 +#define BM_PXP_STAT_AXI_ERROR_ID_0 0x000000F0 +#define BF_PXP_STAT_AXI_ERROR_ID_0(v) \ + (((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID_0) +#define BM_PXP_STAT_NEXT_IRQ 0x00000008 +#define BF_PXP_STAT_NEXT_IRQ(v) \ + (((v) << 3) & BM_PXP_STAT_NEXT_IRQ) +#define BM_PXP_STAT_AXI_READ_ERROR_0 0x00000004 +#define BF_PXP_STAT_AXI_READ_ERROR_0(v) \ + (((v) << 2) & BM_PXP_STAT_AXI_READ_ERROR_0) +#define BM_PXP_STAT_AXI_WRITE_ERROR_0 0x00000002 +#define BF_PXP_STAT_AXI_WRITE_ERROR_0(v) \ + (((v) << 1) & BM_PXP_STAT_AXI_WRITE_ERROR_0) +#define BM_PXP_STAT_IRQ0 0x00000001 +#define BF_PXP_STAT_IRQ0(v) \ + (((v) << 0) & BM_PXP_STAT_IRQ0) + +#define HW_PXP_OUT_CTRL (0x00000020) +#define HW_PXP_OUT_CTRL_SET (0x00000024) +#define HW_PXP_OUT_CTRL_CLR (0x00000028) +#define HW_PXP_OUT_CTRL_TOG (0x0000002c) + +#define BP_PXP_OUT_CTRL_ALPHA 24 +#define BM_PXP_OUT_CTRL_ALPHA 0xFF000000 +#define BF_PXP_OUT_CTRL_ALPHA(v) \ + (((v) << 24) & BM_PXP_OUT_CTRL_ALPHA) +#define BM_PXP_OUT_CTRL_ALPHA_OUTPUT 0x00800000 +#define BF_PXP_OUT_CTRL_ALPHA_OUTPUT(v) \ + (((v) << 23) & BM_PXP_OUT_CTRL_ALPHA_OUTPUT) +#define BP_PXP_OUT_CTRL_RSVD1 10 +#define BM_PXP_OUT_CTRL_RSVD1 0x007FFC00 +#define BF_PXP_OUT_CTRL_RSVD1(v) \ + (((v) << 10) & BM_PXP_OUT_CTRL_RSVD1) +#define BP_PXP_OUT_CTRL_INTERLACED_OUTPUT 8 +#define BM_PXP_OUT_CTRL_INTERLACED_OUTPUT 0x00000300 +#define BF_PXP_OUT_CTRL_INTERLACED_OUTPUT(v) \ + (((v) << 8) & BM_PXP_OUT_CTRL_INTERLACED_OUTPUT) +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0 +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD0 0x1 +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD1 0x2 +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3 +#define BP_PXP_OUT_CTRL_RSVD0 5 +#define BM_PXP_OUT_CTRL_RSVD0 0x000000E0 +#define BF_PXP_OUT_CTRL_RSVD0(v) \ + (((v) << 5) & BM_PXP_OUT_CTRL_RSVD0) +#define BP_PXP_OUT_CTRL_FORMAT 0 +#define BM_PXP_OUT_CTRL_FORMAT 0x0000001F +#define BF_PXP_OUT_CTRL_FORMAT(v) \ + (((v) << 0) & BM_PXP_OUT_CTRL_FORMAT) +#define BV_PXP_OUT_CTRL_FORMAT__ARGB8888 0x0 +#define BV_PXP_OUT_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_OUT_CTRL_FORMAT__RGB888P 0x5 +#define BV_PXP_OUT_CTRL_FORMAT__ARGB1555 0x8 +#define BV_PXP_OUT_CTRL_FORMAT__ARGB4444 0x9 +#define BV_PXP_OUT_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_OUT_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_OUT_CTRL_FORMAT__RGB565 0xE +#define BV_PXP_OUT_CTRL_FORMAT__YUV1P444 0x10 +#define BV_PXP_OUT_CTRL_FORMAT__UYVY1P422 0x12 +#define BV_PXP_OUT_CTRL_FORMAT__VYUY1P422 0x13 +#define BV_PXP_OUT_CTRL_FORMAT__Y8 0x14 +#define BV_PXP_OUT_CTRL_FORMAT__Y4 0x15 +#define BV_PXP_OUT_CTRL_FORMAT__YUV2P422 0x18 +#define BV_PXP_OUT_CTRL_FORMAT__YUV2P420 0x19 +#define BV_PXP_OUT_CTRL_FORMAT__YVU2P422 0x1A +#define BV_PXP_OUT_CTRL_FORMAT__YVU2P420 0x1B + +#define HW_PXP_OUT_BUF (0x00000030) + +#define BP_PXP_OUT_BUF_ADDR 0 +#define BM_PXP_OUT_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_OUT_BUF_ADDR(v) (v) + +#define HW_PXP_OUT_BUF2 (0x00000040) + +#define BP_PXP_OUT_BUF2_ADDR 0 +#define BM_PXP_OUT_BUF2_ADDR 0xFFFFFFFF +#define BF_PXP_OUT_BUF2_ADDR(v) (v) + +#define HW_PXP_OUT_PITCH (0x00000050) + +#define BP_PXP_OUT_PITCH_RSVD 16 +#define BM_PXP_OUT_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_OUT_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_OUT_PITCH_RSVD) +#define BP_PXP_OUT_PITCH_PITCH 0 +#define BM_PXP_OUT_PITCH_PITCH 0x0000FFFF +#define BF_PXP_OUT_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_OUT_PITCH_PITCH) + +#define HW_PXP_OUT_LRC (0x00000060) + +#define BP_PXP_OUT_LRC_RSVD1 30 +#define BM_PXP_OUT_LRC_RSVD1 0xC0000000 +#define BF_PXP_OUT_LRC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_LRC_RSVD1) +#define BP_PXP_OUT_LRC_X 16 +#define BM_PXP_OUT_LRC_X 0x3FFF0000 +#define BF_PXP_OUT_LRC_X(v) \ + (((v) << 16) & BM_PXP_OUT_LRC_X) +#define BP_PXP_OUT_LRC_RSVD0 14 +#define BM_PXP_OUT_LRC_RSVD0 0x0000C000 +#define BF_PXP_OUT_LRC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_LRC_RSVD0) +#define BP_PXP_OUT_LRC_Y 0 +#define BM_PXP_OUT_LRC_Y 0x00003FFF +#define BF_PXP_OUT_LRC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_LRC_Y) + +#define HW_PXP_OUT_PS_ULC (0x00000070) + +#define BP_PXP_OUT_PS_ULC_RSVD1 30 +#define BM_PXP_OUT_PS_ULC_RSVD1 0xC0000000 +#define BF_PXP_OUT_PS_ULC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_PS_ULC_RSVD1) +#define BP_PXP_OUT_PS_ULC_X 16 +#define BM_PXP_OUT_PS_ULC_X 0x3FFF0000 +#define BF_PXP_OUT_PS_ULC_X(v) \ + (((v) << 16) & BM_PXP_OUT_PS_ULC_X) +#define BP_PXP_OUT_PS_ULC_RSVD0 14 +#define BM_PXP_OUT_PS_ULC_RSVD0 0x0000C000 +#define BF_PXP_OUT_PS_ULC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_PS_ULC_RSVD0) +#define BP_PXP_OUT_PS_ULC_Y 0 +#define BM_PXP_OUT_PS_ULC_Y 0x00003FFF +#define BF_PXP_OUT_PS_ULC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_PS_ULC_Y) + +#define HW_PXP_OUT_PS_LRC (0x00000080) + +#define BP_PXP_OUT_PS_LRC_RSVD1 30 +#define BM_PXP_OUT_PS_LRC_RSVD1 0xC0000000 +#define BF_PXP_OUT_PS_LRC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_PS_LRC_RSVD1) +#define BP_PXP_OUT_PS_LRC_X 16 +#define BM_PXP_OUT_PS_LRC_X 0x3FFF0000 +#define BF_PXP_OUT_PS_LRC_X(v) \ + (((v) << 16) & BM_PXP_OUT_PS_LRC_X) +#define BP_PXP_OUT_PS_LRC_RSVD0 14 +#define BM_PXP_OUT_PS_LRC_RSVD0 0x0000C000 +#define BF_PXP_OUT_PS_LRC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_PS_LRC_RSVD0) +#define BP_PXP_OUT_PS_LRC_Y 0 +#define BM_PXP_OUT_PS_LRC_Y 0x00003FFF +#define BF_PXP_OUT_PS_LRC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_PS_LRC_Y) + +#define HW_PXP_OUT_AS_ULC (0x00000090) + +#define BP_PXP_OUT_AS_ULC_RSVD1 30 +#define BM_PXP_OUT_AS_ULC_RSVD1 0xC0000000 +#define BF_PXP_OUT_AS_ULC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_AS_ULC_RSVD1) +#define BP_PXP_OUT_AS_ULC_X 16 +#define BM_PXP_OUT_AS_ULC_X 0x3FFF0000 +#define BF_PXP_OUT_AS_ULC_X(v) \ + (((v) << 16) & BM_PXP_OUT_AS_ULC_X) +#define BP_PXP_OUT_AS_ULC_RSVD0 14 +#define BM_PXP_OUT_AS_ULC_RSVD0 0x0000C000 +#define BF_PXP_OUT_AS_ULC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_AS_ULC_RSVD0) +#define BP_PXP_OUT_AS_ULC_Y 0 +#define BM_PXP_OUT_AS_ULC_Y 0x00003FFF +#define BF_PXP_OUT_AS_ULC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_AS_ULC_Y) + +#define HW_PXP_OUT_AS_LRC (0x000000a0) + +#define BP_PXP_OUT_AS_LRC_RSVD1 30 +#define BM_PXP_OUT_AS_LRC_RSVD1 0xC0000000 +#define BF_PXP_OUT_AS_LRC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_AS_LRC_RSVD1) +#define BP_PXP_OUT_AS_LRC_X 16 +#define BM_PXP_OUT_AS_LRC_X 0x3FFF0000 +#define BF_PXP_OUT_AS_LRC_X(v) \ + (((v) << 16) & BM_PXP_OUT_AS_LRC_X) +#define BP_PXP_OUT_AS_LRC_RSVD0 14 +#define BM_PXP_OUT_AS_LRC_RSVD0 0x0000C000 +#define BF_PXP_OUT_AS_LRC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_AS_LRC_RSVD0) +#define BP_PXP_OUT_AS_LRC_Y 0 +#define BM_PXP_OUT_AS_LRC_Y 0x00003FFF +#define BF_PXP_OUT_AS_LRC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_AS_LRC_Y) + +#define HW_PXP_PS_CTRL (0x000000b0) +#define HW_PXP_PS_CTRL_SET (0x000000b4) +#define HW_PXP_PS_CTRL_CLR (0x000000b8) +#define HW_PXP_PS_CTRL_TOG (0x000000bc) + +#define BP_PXP_PS_CTRL_RSVD1 12 +#define BM_PXP_PS_CTRL_RSVD1 0xFFFFF000 +#define BF_PXP_PS_CTRL_RSVD1(v) \ + (((v) << 12) & BM_PXP_PS_CTRL_RSVD1) +#define BP_PXP_PS_CTRL_DECX 10 +#define BM_PXP_PS_CTRL_DECX 0x00000C00 +#define BF_PXP_PS_CTRL_DECX(v) \ + (((v) << 10) & BM_PXP_PS_CTRL_DECX) +#define BV_PXP_PS_CTRL_DECX__DISABLE 0x0 +#define BV_PXP_PS_CTRL_DECX__DECX2 0x1 +#define BV_PXP_PS_CTRL_DECX__DECX4 0x2 +#define BV_PXP_PS_CTRL_DECX__DECX8 0x3 +#define BP_PXP_PS_CTRL_DECY 8 +#define BM_PXP_PS_CTRL_DECY 0x00000300 +#define BF_PXP_PS_CTRL_DECY(v) \ + (((v) << 8) & BM_PXP_PS_CTRL_DECY) +#define BV_PXP_PS_CTRL_DECY__DISABLE 0x0 +#define BV_PXP_PS_CTRL_DECY__DECY2 0x1 +#define BV_PXP_PS_CTRL_DECY__DECY4 0x2 +#define BV_PXP_PS_CTRL_DECY__DECY8 0x3 +#define BM_PXP_PS_CTRL_RSVD0 0x00000080 +#define BF_PXP_PS_CTRL_RSVD0(v) \ + (((v) << 7) & BM_PXP_PS_CTRL_RSVD0) +#define BM_PXP_PS_CTRL_WB_SWAP 0x00000040 +#define BF_PXP_PS_CTRL_WB_SWAP(v) \ + (((v) << 6) & BM_PXP_PS_CTRL_WB_SWAP) +#define BP_PXP_PS_CTRL_FORMAT 0 +#define BM_PXP_PS_CTRL_FORMAT 0x0000003F +#define BF_PXP_PS_CTRL_FORMAT(v) \ + (((v) << 0) & BM_PXP_PS_CTRL_FORMAT) +#define BV_PXP_PS_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_PS_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_PS_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_PS_CTRL_FORMAT__RGB565 0xE +#define BV_PXP_PS_CTRL_FORMAT__YUV1P444 0x10 +#define BV_PXP_PS_CTRL_FORMAT__UYVY1P422 0x12 +#define BV_PXP_PS_CTRL_FORMAT__VYUY1P422 0x13 +#define BV_PXP_PS_CTRL_FORMAT__Y8 0x14 +#define BV_PXP_PS_CTRL_FORMAT__Y4 0x15 +#define BV_PXP_PS_CTRL_FORMAT__YUV2P422 0x18 +#define BV_PXP_PS_CTRL_FORMAT__YUV2P420 0x19 +#define BV_PXP_PS_CTRL_FORMAT__YVU2P422 0x1A +#define BV_PXP_PS_CTRL_FORMAT__YVU2P420 0x1B +#define BV_PXP_PS_CTRL_FORMAT__YUV422 0x1E +#define BV_PXP_PS_CTRL_FORMAT__YUV420 0x1F +#define BV_PXP_PS_CTRL_FORMAT__RGBA888 0x24 + +#define HW_PXP_PS_BUF (0x000000c0) + +#define BP_PXP_PS_BUF_ADDR 0 +#define BM_PXP_PS_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_PS_BUF_ADDR(v) (v) + +#define HW_PXP_PS_UBUF (0x000000d0) + +#define BP_PXP_PS_UBUF_ADDR 0 +#define BM_PXP_PS_UBUF_ADDR 0xFFFFFFFF +#define BF_PXP_PS_UBUF_ADDR(v) (v) + +#define HW_PXP_PS_VBUF (0x000000e0) + +#define BP_PXP_PS_VBUF_ADDR 0 +#define BM_PXP_PS_VBUF_ADDR 0xFFFFFFFF +#define BF_PXP_PS_VBUF_ADDR(v) (v) + +#define HW_PXP_PS_PITCH (0x000000f0) + +#define BP_PXP_PS_PITCH_RSVD 16 +#define BM_PXP_PS_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_PS_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_PS_PITCH_RSVD) +#define BP_PXP_PS_PITCH_PITCH 0 +#define BM_PXP_PS_PITCH_PITCH 0x0000FFFF +#define BF_PXP_PS_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_PS_PITCH_PITCH) + +#define HW_PXP_PS_BACKGROUND_0 (0x00000100) + +#define BP_PXP_PS_BACKGROUND_0_RSVD 24 +#define BM_PXP_PS_BACKGROUND_0_RSVD 0xFF000000 +#define BF_PXP_PS_BACKGROUND_0_RSVD(v) \ + (((v) << 24) & BM_PXP_PS_BACKGROUND_0_RSVD) +#define BP_PXP_PS_BACKGROUND_0_COLOR 0 +#define BM_PXP_PS_BACKGROUND_0_COLOR 0x00FFFFFF +#define BF_PXP_PS_BACKGROUND_0_COLOR(v) \ + (((v) << 0) & BM_PXP_PS_BACKGROUND_0_COLOR) + +#define HW_PXP_PS_SCALE (0x00000110) + +#define BM_PXP_PS_SCALE_RSVD2 0x80000000 +#define BF_PXP_PS_SCALE_RSVD2(v) \ + (((v) << 31) & BM_PXP_PS_SCALE_RSVD2) +#define BP_PXP_PS_SCALE_YSCALE 16 +#define BM_PXP_PS_SCALE_YSCALE 0x7FFF0000 +#define BF_PXP_PS_SCALE_YSCALE(v) \ + (((v) << 16) & BM_PXP_PS_SCALE_YSCALE) +#define BM_PXP_PS_SCALE_RSVD1 0x00008000 +#define BF_PXP_PS_SCALE_RSVD1(v) \ + (((v) << 15) & BM_PXP_PS_SCALE_RSVD1) +#define BP_PXP_PS_SCALE_XSCALE 0 +#define BM_PXP_PS_SCALE_XSCALE 0x00007FFF +#define BF_PXP_PS_SCALE_XSCALE(v) \ + (((v) << 0) & BM_PXP_PS_SCALE_XSCALE) + +#define BP_PXP_PS_SCALE_OFFSET 12 + +#define HW_PXP_PS_OFFSET (0x00000120) + +#define BP_PXP_PS_OFFSET_RSVD2 28 +#define BM_PXP_PS_OFFSET_RSVD2 0xF0000000 +#define BF_PXP_PS_OFFSET_RSVD2(v) \ + (((v) << 28) & BM_PXP_PS_OFFSET_RSVD2) +#define BP_PXP_PS_OFFSET_YOFFSET 16 +#define BM_PXP_PS_OFFSET_YOFFSET 0x0FFF0000 +#define BF_PXP_PS_OFFSET_YOFFSET(v) \ + (((v) << 16) & BM_PXP_PS_OFFSET_YOFFSET) +#define BP_PXP_PS_OFFSET_RSVD1 12 +#define BM_PXP_PS_OFFSET_RSVD1 0x0000F000 +#define BF_PXP_PS_OFFSET_RSVD1(v) \ + (((v) << 12) & BM_PXP_PS_OFFSET_RSVD1) +#define BP_PXP_PS_OFFSET_XOFFSET 0 +#define BM_PXP_PS_OFFSET_XOFFSET 0x00000FFF +#define BF_PXP_PS_OFFSET_XOFFSET(v) \ + (((v) << 0) & BM_PXP_PS_OFFSET_XOFFSET) + +#define HW_PXP_PS_CLRKEYLOW_0 (0x00000130) + +#define BP_PXP_PS_CLRKEYLOW_0_RSVD1 24 +#define BM_PXP_PS_CLRKEYLOW_0_RSVD1 0xFF000000 +#define BF_PXP_PS_CLRKEYLOW_0_RSVD1(v) \ + (((v) << 24) & BM_PXP_PS_CLRKEYLOW_0_RSVD1) +#define BP_PXP_PS_CLRKEYLOW_0_PIXEL 0 +#define BM_PXP_PS_CLRKEYLOW_0_PIXEL 0x00FFFFFF +#define BF_PXP_PS_CLRKEYLOW_0_PIXEL(v) \ + (((v) << 0) & BM_PXP_PS_CLRKEYLOW_0_PIXEL) + +#define HW_PXP_PS_CLRKEYHIGH_0 (0x00000140) + +#define BP_PXP_PS_CLRKEYHIGH_0_RSVD1 24 +#define BM_PXP_PS_CLRKEYHIGH_0_RSVD1 0xFF000000 +#define BF_PXP_PS_CLRKEYHIGH_0_RSVD1(v) \ + (((v) << 24) & BM_PXP_PS_CLRKEYHIGH_0_RSVD1) +#define BP_PXP_PS_CLRKEYHIGH_0_PIXEL 0 +#define BM_PXP_PS_CLRKEYHIGH_0_PIXEL 0x00FFFFFF +#define BF_PXP_PS_CLRKEYHIGH_0_PIXEL(v) \ + (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_0_PIXEL) + +#define HW_PXP_AS_CTRL (0x00000150) + +#define BP_PXP_AS_CTRL_RSVD1 22 +#define BM_PXP_AS_CTRL_RSVD1 0xFFC00000 +#define BF_PXP_AS_CTRL_RSVD1(v) \ + (((v) << 22) & BM_PXP_AS_CTRL_RSVD1) +#define BM_PXP_AS_CTRL_ALPHA1_INVERT 0x00200000 +#define BF_PXP_AS_CTRL_ALPHA1_INVERT(v) \ + (((v) << 21) & BM_PXP_AS_CTRL_ALPHA1_INVERT) +#define BM_PXP_AS_CTRL_ALPHA0_INVERT 0x00100000 +#define BF_PXP_AS_CTRL_ALPHA0_INVERT(v) \ + (((v) << 20) & BM_PXP_AS_CTRL_ALPHA0_INVERT) +#define BP_PXP_AS_CTRL_ROP 16 +#define BM_PXP_AS_CTRL_ROP 0x000F0000 +#define BF_PXP_AS_CTRL_ROP(v) \ + (((v) << 16) & BM_PXP_AS_CTRL_ROP) +#define BV_PXP_AS_CTRL_ROP__MASKAS 0x0 +#define BV_PXP_AS_CTRL_ROP__MASKNOTAS 0x1 +#define BV_PXP_AS_CTRL_ROP__MASKASNOT 0x2 +#define BV_PXP_AS_CTRL_ROP__MERGEAS 0x3 +#define BV_PXP_AS_CTRL_ROP__MERGENOTAS 0x4 +#define BV_PXP_AS_CTRL_ROP__MERGEASNOT 0x5 +#define BV_PXP_AS_CTRL_ROP__NOTCOPYAS 0x6 +#define BV_PXP_AS_CTRL_ROP__NOT 0x7 +#define BV_PXP_AS_CTRL_ROP__NOTMASKAS 0x8 +#define BV_PXP_AS_CTRL_ROP__NOTMERGEAS 0x9 +#define BV_PXP_AS_CTRL_ROP__XORAS 0xA +#define BV_PXP_AS_CTRL_ROP__NOTXORAS 0xB +#define BP_PXP_AS_CTRL_ALPHA 8 +#define BM_PXP_AS_CTRL_ALPHA 0x0000FF00 +#define BF_PXP_AS_CTRL_ALPHA(v) \ + (((v) << 8) & BM_PXP_AS_CTRL_ALPHA) +#define BP_PXP_AS_CTRL_FORMAT 4 +#define BM_PXP_AS_CTRL_FORMAT 0x000000F0 +#define BF_PXP_AS_CTRL_FORMAT(v) \ + (((v) << 4) & BM_PXP_AS_CTRL_FORMAT) +#define BV_PXP_AS_CTRL_FORMAT__ARGB8888 0x0 +#define BV_PXP_AS_CTRL_FORMAT__RGBA8888 0x1 +#define BV_PXP_AS_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_AS_CTRL_FORMAT__ARGB1555 0x8 +#define BV_PXP_AS_CTRL_FORMAT__ARGB4444 0x9 +#define BV_PXP_AS_CTRL_FORMAT__RGBA5551 0xA +#define BV_PXP_AS_CTRL_FORMAT__RGBA4444 0xB +#define BV_PXP_AS_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_AS_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_AS_CTRL_FORMAT__RGB565 0xE +#define BM_PXP_AS_CTRL_ENABLE_COLORKEY 0x00000008 +#define BF_PXP_AS_CTRL_ENABLE_COLORKEY(v) \ + (((v) << 3) & BM_PXP_AS_CTRL_ENABLE_COLORKEY) +#define BP_PXP_AS_CTRL_ALPHA_CTRL 1 +#define BM_PXP_AS_CTRL_ALPHA_CTRL 0x00000006 +#define BF_PXP_AS_CTRL_ALPHA_CTRL(v) \ + (((v) << 1) & BM_PXP_AS_CTRL_ALPHA_CTRL) +#define BV_PXP_AS_CTRL_ALPHA_CTRL__Embedded 0x0 +#define BV_PXP_AS_CTRL_ALPHA_CTRL__Override 0x1 +#define BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply 0x2 +#define BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs 0x3 +#define BM_PXP_AS_CTRL_RSVD0 0x00000001 +#define BF_PXP_AS_CTRL_RSVD0(v) \ + (((v) << 0) & BM_PXP_AS_CTRL_RSVD0) + +#define HW_PXP_AS_BUF (0x00000160) + +#define BP_PXP_AS_BUF_ADDR 0 +#define BM_PXP_AS_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_AS_BUF_ADDR(v) (v) + +#define HW_PXP_AS_PITCH (0x00000170) + +#define BP_PXP_AS_PITCH_RSVD 16 +#define BM_PXP_AS_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_AS_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_AS_PITCH_RSVD) +#define BP_PXP_AS_PITCH_PITCH 0 +#define BM_PXP_AS_PITCH_PITCH 0x0000FFFF +#define BF_PXP_AS_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_AS_PITCH_PITCH) + +#define HW_PXP_AS_CLRKEYLOW_0 (0x00000180) + +#define BP_PXP_AS_CLRKEYLOW_0_RSVD1 24 +#define BM_PXP_AS_CLRKEYLOW_0_RSVD1 0xFF000000 +#define BF_PXP_AS_CLRKEYLOW_0_RSVD1(v) \ + (((v) << 24) & BM_PXP_AS_CLRKEYLOW_0_RSVD1) +#define BP_PXP_AS_CLRKEYLOW_0_PIXEL 0 +#define BM_PXP_AS_CLRKEYLOW_0_PIXEL 0x00FFFFFF +#define BF_PXP_AS_CLRKEYLOW_0_PIXEL(v) \ + (((v) << 0) & BM_PXP_AS_CLRKEYLOW_0_PIXEL) + +#define HW_PXP_AS_CLRKEYHIGH_0 (0x00000190) + +#define BP_PXP_AS_CLRKEYHIGH_0_RSVD1 24 +#define BM_PXP_AS_CLRKEYHIGH_0_RSVD1 0xFF000000 +#define BF_PXP_AS_CLRKEYHIGH_0_RSVD1(v) \ + (((v) << 24) & BM_PXP_AS_CLRKEYHIGH_0_RSVD1) +#define BP_PXP_AS_CLRKEYHIGH_0_PIXEL 0 +#define BM_PXP_AS_CLRKEYHIGH_0_PIXEL 0x00FFFFFF +#define BF_PXP_AS_CLRKEYHIGH_0_PIXEL(v) \ + (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_0_PIXEL) + +#define HW_PXP_CSC1_COEF0 (0x000001a0) + +#define BM_PXP_CSC1_COEF0_YCBCR_MODE 0x80000000 +#define BF_PXP_CSC1_COEF0_YCBCR_MODE(v) \ + (((v) << 31) & BM_PXP_CSC1_COEF0_YCBCR_MODE) +#define BM_PXP_CSC1_COEF0_BYPASS 0x40000000 +#define BF_PXP_CSC1_COEF0_BYPASS(v) \ + (((v) << 30) & BM_PXP_CSC1_COEF0_BYPASS) +#define BM_PXP_CSC1_COEF0_RSVD1 0x20000000 +#define BF_PXP_CSC1_COEF0_RSVD1(v) \ + (((v) << 29) & BM_PXP_CSC1_COEF0_RSVD1) +#define BP_PXP_CSC1_COEF0_C0 18 +#define BM_PXP_CSC1_COEF0_C0 0x1FFC0000 +#define BF_PXP_CSC1_COEF0_C0(v) \ + (((v) << 18) & BM_PXP_CSC1_COEF0_C0) +#define BP_PXP_CSC1_COEF0_UV_OFFSET 9 +#define BM_PXP_CSC1_COEF0_UV_OFFSET 0x0003FE00 +#define BF_PXP_CSC1_COEF0_UV_OFFSET(v) \ + (((v) << 9) & BM_PXP_CSC1_COEF0_UV_OFFSET) +#define BP_PXP_CSC1_COEF0_Y_OFFSET 0 +#define BM_PXP_CSC1_COEF0_Y_OFFSET 0x000001FF +#define BF_PXP_CSC1_COEF0_Y_OFFSET(v) \ + (((v) << 0) & BM_PXP_CSC1_COEF0_Y_OFFSET) + +#define HW_PXP_CSC1_COEF1 (0x000001b0) + +#define BP_PXP_CSC1_COEF1_RSVD1 27 +#define BM_PXP_CSC1_COEF1_RSVD1 0xF8000000 +#define BF_PXP_CSC1_COEF1_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC1_COEF1_RSVD1) +#define BP_PXP_CSC1_COEF1_C1 16 +#define BM_PXP_CSC1_COEF1_C1 0x07FF0000 +#define BF_PXP_CSC1_COEF1_C1(v) \ + (((v) << 16) & BM_PXP_CSC1_COEF1_C1) +#define BP_PXP_CSC1_COEF1_RSVD0 11 +#define BM_PXP_CSC1_COEF1_RSVD0 0x0000F800 +#define BF_PXP_CSC1_COEF1_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC1_COEF1_RSVD0) +#define BP_PXP_CSC1_COEF1_C4 0 +#define BM_PXP_CSC1_COEF1_C4 0x000007FF +#define BF_PXP_CSC1_COEF1_C4(v) \ + (((v) << 0) & BM_PXP_CSC1_COEF1_C4) + +#define HW_PXP_CSC1_COEF2 (0x000001c0) + +#define BP_PXP_CSC1_COEF2_RSVD1 27 +#define BM_PXP_CSC1_COEF2_RSVD1 0xF8000000 +#define BF_PXP_CSC1_COEF2_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC1_COEF2_RSVD1) +#define BP_PXP_CSC1_COEF2_C2 16 +#define BM_PXP_CSC1_COEF2_C2 0x07FF0000 +#define BF_PXP_CSC1_COEF2_C2(v) \ + (((v) << 16) & BM_PXP_CSC1_COEF2_C2) +#define BP_PXP_CSC1_COEF2_RSVD0 11 +#define BM_PXP_CSC1_COEF2_RSVD0 0x0000F800 +#define BF_PXP_CSC1_COEF2_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC1_COEF2_RSVD0) +#define BP_PXP_CSC1_COEF2_C3 0 +#define BM_PXP_CSC1_COEF2_C3 0x000007FF +#define BF_PXP_CSC1_COEF2_C3(v) \ + (((v) << 0) & BM_PXP_CSC1_COEF2_C3) + +#define HW_PXP_CSC2_CTRL (0x000001d0) + +#define BP_PXP_CSC2_CTRL_RSVD 3 +#define BM_PXP_CSC2_CTRL_RSVD 0xFFFFFFF8 +#define BF_PXP_CSC2_CTRL_RSVD(v) \ + (((v) << 3) & BM_PXP_CSC2_CTRL_RSVD) +#define BP_PXP_CSC2_CTRL_CSC_MODE 1 +#define BM_PXP_CSC2_CTRL_CSC_MODE 0x00000006 +#define BF_PXP_CSC2_CTRL_CSC_MODE(v) \ + (((v) << 1) & BM_PXP_CSC2_CTRL_CSC_MODE) +#define BV_PXP_CSC2_CTRL_CSC_MODE__YUV2RGB 0x0 +#define BV_PXP_CSC2_CTRL_CSC_MODE__YCbCr2RGB 0x1 +#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YUV 0x2 +#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YCbCr 0x3 +#define BM_PXP_CSC2_CTRL_BYPASS 0x00000001 +#define BF_PXP_CSC2_CTRL_BYPASS(v) \ + (((v) << 0) & BM_PXP_CSC2_CTRL_BYPASS) + +#define HW_PXP_CSC2_COEF0 (0x000001e0) + +#define BP_PXP_CSC2_COEF0_RSVD1 27 +#define BM_PXP_CSC2_COEF0_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF0_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF0_RSVD1) +#define BP_PXP_CSC2_COEF0_A2 16 +#define BM_PXP_CSC2_COEF0_A2 0x07FF0000 +#define BF_PXP_CSC2_COEF0_A2(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF0_A2) +#define BP_PXP_CSC2_COEF0_RSVD0 11 +#define BM_PXP_CSC2_COEF0_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF0_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF0_RSVD0) +#define BP_PXP_CSC2_COEF0_A1 0 +#define BM_PXP_CSC2_COEF0_A1 0x000007FF +#define BF_PXP_CSC2_COEF0_A1(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF0_A1) + +#define HW_PXP_CSC2_COEF1 (0x000001f0) + +#define BP_PXP_CSC2_COEF1_RSVD1 27 +#define BM_PXP_CSC2_COEF1_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF1_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF1_RSVD1) +#define BP_PXP_CSC2_COEF1_B1 16 +#define BM_PXP_CSC2_COEF1_B1 0x07FF0000 +#define BF_PXP_CSC2_COEF1_B1(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF1_B1) +#define BP_PXP_CSC2_COEF1_RSVD0 11 +#define BM_PXP_CSC2_COEF1_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF1_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF1_RSVD0) +#define BP_PXP_CSC2_COEF1_A3 0 +#define BM_PXP_CSC2_COEF1_A3 0x000007FF +#define BF_PXP_CSC2_COEF1_A3(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF1_A3) + +#define HW_PXP_CSC2_COEF2 (0x00000200) + +#define BP_PXP_CSC2_COEF2_RSVD1 27 +#define BM_PXP_CSC2_COEF2_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF2_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF2_RSVD1) +#define BP_PXP_CSC2_COEF2_B3 16 +#define BM_PXP_CSC2_COEF2_B3 0x07FF0000 +#define BF_PXP_CSC2_COEF2_B3(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF2_B3) +#define BP_PXP_CSC2_COEF2_RSVD0 11 +#define BM_PXP_CSC2_COEF2_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF2_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF2_RSVD0) +#define BP_PXP_CSC2_COEF2_B2 0 +#define BM_PXP_CSC2_COEF2_B2 0x000007FF +#define BF_PXP_CSC2_COEF2_B2(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF2_B2) + +#define HW_PXP_CSC2_COEF3 (0x00000210) + +#define BP_PXP_CSC2_COEF3_RSVD1 27 +#define BM_PXP_CSC2_COEF3_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF3_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF3_RSVD1) +#define BP_PXP_CSC2_COEF3_C2 16 +#define BM_PXP_CSC2_COEF3_C2 0x07FF0000 +#define BF_PXP_CSC2_COEF3_C2(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF3_C2) +#define BP_PXP_CSC2_COEF3_RSVD0 11 +#define BM_PXP_CSC2_COEF3_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF3_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF3_RSVD0) +#define BP_PXP_CSC2_COEF3_C1 0 +#define BM_PXP_CSC2_COEF3_C1 0x000007FF +#define BF_PXP_CSC2_COEF3_C1(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF3_C1) + +#define HW_PXP_CSC2_COEF4 (0x00000220) + +#define BP_PXP_CSC2_COEF4_RSVD1 25 +#define BM_PXP_CSC2_COEF4_RSVD1 0xFE000000 +#define BF_PXP_CSC2_COEF4_RSVD1(v) \ + (((v) << 25) & BM_PXP_CSC2_COEF4_RSVD1) +#define BP_PXP_CSC2_COEF4_D1 16 +#define BM_PXP_CSC2_COEF4_D1 0x01FF0000 +#define BF_PXP_CSC2_COEF4_D1(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF4_D1) +#define BP_PXP_CSC2_COEF4_RSVD0 11 +#define BM_PXP_CSC2_COEF4_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF4_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF4_RSVD0) +#define BP_PXP_CSC2_COEF4_C3 0 +#define BM_PXP_CSC2_COEF4_C3 0x000007FF +#define BF_PXP_CSC2_COEF4_C3(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF4_C3) + +#define HW_PXP_CSC2_COEF5 (0x00000230) + +#define BP_PXP_CSC2_COEF5_RSVD1 25 +#define BM_PXP_CSC2_COEF5_RSVD1 0xFE000000 +#define BF_PXP_CSC2_COEF5_RSVD1(v) \ + (((v) << 25) & BM_PXP_CSC2_COEF5_RSVD1) +#define BP_PXP_CSC2_COEF5_D3 16 +#define BM_PXP_CSC2_COEF5_D3 0x01FF0000 +#define BF_PXP_CSC2_COEF5_D3(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF5_D3) +#define BP_PXP_CSC2_COEF5_RSVD0 9 +#define BM_PXP_CSC2_COEF5_RSVD0 0x0000FE00 +#define BF_PXP_CSC2_COEF5_RSVD0(v) \ + (((v) << 9) & BM_PXP_CSC2_COEF5_RSVD0) +#define BP_PXP_CSC2_COEF5_D2 0 +#define BM_PXP_CSC2_COEF5_D2 0x000001FF +#define BF_PXP_CSC2_COEF5_D2(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF5_D2) + +#define HW_PXP_LUT_CTRL (0x00000240) + +#define BM_PXP_LUT_CTRL_BYPASS 0x80000000 +#define BF_PXP_LUT_CTRL_BYPASS(v) \ + (((v) << 31) & BM_PXP_LUT_CTRL_BYPASS) +#define BP_PXP_LUT_CTRL_RSVD3 26 +#define BM_PXP_LUT_CTRL_RSVD3 0x7C000000 +#define BF_PXP_LUT_CTRL_RSVD3(v) \ + (((v) << 26) & BM_PXP_LUT_CTRL_RSVD3) +#define BP_PXP_LUT_CTRL_LOOKUP_MODE 24 +#define BM_PXP_LUT_CTRL_LOOKUP_MODE 0x03000000 +#define BF_PXP_LUT_CTRL_LOOKUP_MODE(v) \ + (((v) << 24) & BM_PXP_LUT_CTRL_LOOKUP_MODE) +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__CACHE_RGB565 0x0 +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8 0x1 +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB444 0x2 +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB454 0x3 +#define BP_PXP_LUT_CTRL_RSVD2 18 +#define BM_PXP_LUT_CTRL_RSVD2 0x00FC0000 +#define BF_PXP_LUT_CTRL_RSVD2(v) \ + (((v) << 18) & BM_PXP_LUT_CTRL_RSVD2) +#define BP_PXP_LUT_CTRL_OUT_MODE 16 +#define BM_PXP_LUT_CTRL_OUT_MODE 0x00030000 +#define BF_PXP_LUT_CTRL_OUT_MODE(v) \ + (((v) << 16) & BM_PXP_LUT_CTRL_OUT_MODE) +#define BV_PXP_LUT_CTRL_OUT_MODE__RESERVED 0x0 +#define BV_PXP_LUT_CTRL_OUT_MODE__Y8 0x1 +#define BV_PXP_LUT_CTRL_OUT_MODE__RGBW4444CFA 0x2 +#define BV_PXP_LUT_CTRL_OUT_MODE__RGB888 0x3 +#define BP_PXP_LUT_CTRL_RSVD1 11 +#define BM_PXP_LUT_CTRL_RSVD1 0x0000F800 +#define BF_PXP_LUT_CTRL_RSVD1(v) \ + (((v) << 11) & BM_PXP_LUT_CTRL_RSVD1) +#define BM_PXP_LUT_CTRL_SEL_8KB 0x00000400 +#define BF_PXP_LUT_CTRL_SEL_8KB(v) \ + (((v) << 10) & BM_PXP_LUT_CTRL_SEL_8KB) +#define BM_PXP_LUT_CTRL_LRU_UPD 0x00000200 +#define BF_PXP_LUT_CTRL_LRU_UPD(v) \ + (((v) << 9) & BM_PXP_LUT_CTRL_LRU_UPD) +#define BM_PXP_LUT_CTRL_INVALID 0x00000100 +#define BF_PXP_LUT_CTRL_INVALID(v) \ + (((v) << 8) & BM_PXP_LUT_CTRL_INVALID) +#define BP_PXP_LUT_CTRL_RSVD0 1 +#define BM_PXP_LUT_CTRL_RSVD0 0x000000FE +#define BF_PXP_LUT_CTRL_RSVD0(v) \ + (((v) << 1) & BM_PXP_LUT_CTRL_RSVD0) +#define BM_PXP_LUT_CTRL_DMA_START 0x00000001 +#define BF_PXP_LUT_CTRL_DMA_START(v) \ + (((v) << 0) & BM_PXP_LUT_CTRL_DMA_START) + +#define HW_PXP_LUT_ADDR (0x00000250) + +#define BM_PXP_LUT_ADDR_RSVD2 0x80000000 +#define BF_PXP_LUT_ADDR_RSVD2(v) \ + (((v) << 31) & BM_PXP_LUT_ADDR_RSVD2) +#define BP_PXP_LUT_ADDR_NUM_BYTES 16 +#define BM_PXP_LUT_ADDR_NUM_BYTES 0x7FFF0000 +#define BF_PXP_LUT_ADDR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_LUT_ADDR_NUM_BYTES) +#define BP_PXP_LUT_ADDR_RSVD1 14 +#define BM_PXP_LUT_ADDR_RSVD1 0x0000C000 +#define BF_PXP_LUT_ADDR_RSVD1(v) \ + (((v) << 14) & BM_PXP_LUT_ADDR_RSVD1) +#define BP_PXP_LUT_ADDR_ADDR 0 +#define BM_PXP_LUT_ADDR_ADDR 0x00003FFF +#define BF_PXP_LUT_ADDR_ADDR(v) \ + (((v) << 0) & BM_PXP_LUT_ADDR_ADDR) + +#define HW_PXP_LUT_DATA (0x00000260) + +#define BP_PXP_LUT_DATA_DATA 0 +#define BM_PXP_LUT_DATA_DATA 0xFFFFFFFF +#define BF_PXP_LUT_DATA_DATA(v) (v) + +#define HW_PXP_LUT_EXTMEM (0x00000270) + +#define BP_PXP_LUT_EXTMEM_ADDR 0 +#define BM_PXP_LUT_EXTMEM_ADDR 0xFFFFFFFF +#define BF_PXP_LUT_EXTMEM_ADDR(v) (v) + +#define HW_PXP_CFA (0x00000280) + +#define BP_PXP_CFA_DATA 0 +#define BM_PXP_CFA_DATA 0xFFFFFFFF +#define BF_PXP_CFA_DATA(v) (v) + +#define HW_PXP_ALPHA_A_CTRL (0x00000290) + +#define BP_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA 24 +#define BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA 0xFF000000 +#define BF_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA(v) \ + (((v) << 24) & BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA) +#define BP_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA 16 +#define BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA 0x00FF0000 +#define BF_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA(v) \ + (((v) << 16) & BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA) +#define BP_PXP_ALPHA_A_CTRL_RSVD0 14 +#define BM_PXP_ALPHA_A_CTRL_RSVD0 0x0000C000 +#define BF_PXP_ALPHA_A_CTRL_RSVD0(v) \ + (((v) << 14) & BM_PXP_ALPHA_A_CTRL_RSVD0) +#define BM_PXP_ALPHA_A_CTRL_S1_COLOR_MODE 0x00002000 +#define BF_PXP_ALPHA_A_CTRL_S1_COLOR_MODE(v) \ + (((v) << 13) & BM_PXP_ALPHA_A_CTRL_S1_COLOR_MODE) +#define BV_PXP_ALPHA_A_CTRL_S1_COLOR_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S1_COLOR_MODE__1 0x1 +#define BM_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE 0x00001000 +#define BF_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE(v) \ + (((v) << 12) & BM_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE) +#define BV_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE__1 0x1 +#define BP_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE 10 +#define BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE 0x00000C00 +#define BF_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE(v) \ + (((v) << 10) & BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE) +#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__1 0x0 +#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__2 0x0 +#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__3 0x0 +#define BP_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE 8 +#define BM_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE 0x00000300 +#define BF_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE(v) \ + (((v) << 8) & BM_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE) +#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__1 0x1 +#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__2 0x2 +#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__3 0x3 +#define BM_PXP_ALPHA_A_CTRL_RSVD1 0x00000080 +#define BF_PXP_ALPHA_A_CTRL_RSVD1(v) \ + (((v) << 7) & BM_PXP_ALPHA_A_CTRL_RSVD1) +#define BM_PXP_ALPHA_A_CTRL_S0_COLOR_MODE 0x00000040 +#define BF_PXP_ALPHA_A_CTRL_S0_COLOR_MODE(v) \ + (((v) << 6) & BM_PXP_ALPHA_A_CTRL_S0_COLOR_MODE) +#define BV_PXP_ALPHA_A_CTRL_S0_COLOR_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S0_COLOR_MODE__1 0x1 +#define BM_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE 0x00000020 +#define BF_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE(v) \ + (((v) << 5) & BM_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE) +#define BV_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE__1 0x1 +#define BP_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE 3 +#define BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE 0x00000018 +#define BF_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE(v) \ + (((v) << 3) & BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE) +#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__1 0x1 +#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__2 0x2 +#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__3 0x3 +#define BP_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE 1 +#define BM_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE 0x00000006 +#define BF_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE(v) \ + (((v) << 1) & BM_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE) +#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__1 0x1 +#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__2 0x2 +#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__3 0x3 +#define BM_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE 0x00000001 +#define BF_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE(v) \ + (((v) << 0) & BM_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE) +#define BV_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE__1 0x1 + +#define HW_PXP_ALPHA_B_CTRL (0x000002a0) + +#define BP_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA 24 +#define BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA 0xFF000000 +#define BF_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA(v) \ + (((v) << 24) & BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA) +#define BP_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA 16 +#define BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA 0x00FF0000 +#define BF_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA(v) \ + (((v) << 16) & BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA) +#define BP_PXP_ALPHA_B_CTRL_RSVD0 14 +#define BM_PXP_ALPHA_B_CTRL_RSVD0 0x0000C000 +#define BF_PXP_ALPHA_B_CTRL_RSVD0(v) \ + (((v) << 14) & BM_PXP_ALPHA_B_CTRL_RSVD0) +#define BM_PXP_ALPHA_B_CTRL_S1_COLOR_MODE 0x00002000 +#define BF_PXP_ALPHA_B_CTRL_S1_COLOR_MODE(v) \ + (((v) << 13) & BM_PXP_ALPHA_B_CTRL_S1_COLOR_MODE) +#define BV_PXP_ALPHA_B_CTRL_S1_COLOR_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S1_COLOR_MODE__1 0x1 +#define BM_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE 0x00001000 +#define BF_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE(v) \ + (((v) << 12) & BM_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE) +#define BV_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE__1 0x1 +#define BP_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE 10 +#define BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE 0x00000C00 +#define BF_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE(v) \ + (((v) << 10) & BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE) +#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__1 0x1 +#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__2 0x2 +#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__3 0x3 +#define BP_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE 8 +#define BM_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE 0x00000300 +#define BF_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE(v) \ + (((v) << 8) & BM_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE) +#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__1 0x1 +#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__2 0x2 +#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__3 0x3 +#define BM_PXP_ALPHA_B_CTRL_RSVD1 0x00000080 +#define BF_PXP_ALPHA_B_CTRL_RSVD1(v) \ + (((v) << 7) & BM_PXP_ALPHA_B_CTRL_RSVD1) +#define BM_PXP_ALPHA_B_CTRL_S0_COLOR_MODE 0x00000040 +#define BF_PXP_ALPHA_B_CTRL_S0_COLOR_MODE(v) \ + (((v) << 6) & BM_PXP_ALPHA_B_CTRL_S0_COLOR_MODE) +#define BV_PXP_ALPHA_B_CTRL_S0_COLOR_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S0_COLOR_MODE__1 0x1 +#define BM_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE 0x00000020 +#define BF_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE(v) \ + (((v) << 5) & BM_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE) +#define BV_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE__1 0x1 +#define BP_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE 3 +#define BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE 0x00000018 +#define BF_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE(v) \ + (((v) << 3) & BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE) +#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__1 0x1 +#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__2 0x2 +#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__3 0x3 +#define BP_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE 1 +#define BM_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE 0x00000006 +#define BF_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE(v) \ + (((v) << 1) & BM_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE) +#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__1 0x1 +#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__2 0x2 +#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__3 0x3 +#define BM_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE 0x00000001 +#define BF_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE(v) \ + (((v) << 0) & BM_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE) +#define BV_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE__1 0x1 + +#define HW_PXP_ALPHA_B_CTRL_1 (0x000002b0) + +#define BP_PXP_ALPHA_B_CTRL_1_RSVD0 8 +#define BM_PXP_ALPHA_B_CTRL_1_RSVD0 0xFFFFFF00 +#define BF_PXP_ALPHA_B_CTRL_1_RSVD0(v) \ + (((v) << 8) & BM_PXP_ALPHA_B_CTRL_1_RSVD0) +#define BP_PXP_ALPHA_B_CTRL_1_ROP 4 +#define BM_PXP_ALPHA_B_CTRL_1_ROP 0x000000F0 +#define BF_PXP_ALPHA_B_CTRL_1_ROP(v) \ + (((v) << 4) & BM_PXP_ALPHA_B_CTRL_1_ROP) +#define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKAS 0x0 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKNOTAS 0x1 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKASNOT 0x2 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGEAS 0x3 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGENOTAS 0x4 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGEASNOT 0x5 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTCOPYAS 0x6 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOT 0x7 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTMASKAS 0x8 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTMERGEAS 0x9 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__XORAS 0xA +#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTXORAS 0xB +#define BP_PXP_ALPHA_B_CTRL_1_RSVD1 2 +#define BM_PXP_ALPHA_B_CTRL_1_RSVD1 0x0000000C +#define BF_PXP_ALPHA_B_CTRL_1_RSVD1(v) \ + (((v) << 2) & BM_PXP_ALPHA_B_CTRL_1_RSVD1) +#define BM_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE 0x00000002 +#define BF_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE(v) \ + (((v) << 1) & BM_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE) +#define BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE 0x00000001 +#define BF_PXP_ALPHA_B_CTRL_1_ROP_ENABLE(v) \ + (((v) << 0) & BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE) + +#define HW_PXP_PS_BACKGROUND_1 (0x000002c0) + +#define BP_PXP_PS_BACKGROUND_1_RSVD 24 +#define BM_PXP_PS_BACKGROUND_1_RSVD 0xFF000000 +#define BF_PXP_PS_BACKGROUND_1_RSVD(v) \ + (((v) << 24) & BM_PXP_PS_BACKGROUND_1_RSVD) +#define BP_PXP_PS_BACKGROUND_1_COLOR 0 +#define BM_PXP_PS_BACKGROUND_1_COLOR 0x00FFFFFF +#define BF_PXP_PS_BACKGROUND_1_COLOR(v) \ + (((v) << 0) & BM_PXP_PS_BACKGROUND_1_COLOR) + +#define HW_PXP_PS_CLRKEYLOW_1 (0x000002d0) + +#define BP_PXP_PS_CLRKEYLOW_1_RSVD1 24 +#define BM_PXP_PS_CLRKEYLOW_1_RSVD1 0xFF000000 +#define BF_PXP_PS_CLRKEYLOW_1_RSVD1(v) \ + (((v) << 24) & BM_PXP_PS_CLRKEYLOW_1_RSVD1) +#define BP_PXP_PS_CLRKEYLOW_1_PIXEL 0 +#define BM_PXP_PS_CLRKEYLOW_1_PIXEL 0x00FFFFFF +#define BF_PXP_PS_CLRKEYLOW_1_PIXEL(v) \ + (((v) << 0) & BM_PXP_PS_CLRKEYLOW_1_PIXEL) + +#define HW_PXP_PS_CLRKEYHIGH_1 (0x000002e0) + +#define BP_PXP_PS_CLRKEYHIGH_1_RSVD1 24 +#define BM_PXP_PS_CLRKEYHIGH_1_RSVD1 0xFF000000 +#define BF_PXP_PS_CLRKEYHIGH_1_RSVD1(v) \ + (((v) << 24) & BM_PXP_PS_CLRKEYHIGH_1_RSVD1) +#define BP_PXP_PS_CLRKEYHIGH_1_PIXEL 0 +#define BM_PXP_PS_CLRKEYHIGH_1_PIXEL 0x00FFFFFF +#define BF_PXP_PS_CLRKEYHIGH_1_PIXEL(v) \ + (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_1_PIXEL) + +#define HW_PXP_AS_CLRKEYLOW_1 (0x000002f0) + +#define BP_PXP_AS_CLRKEYLOW_1_RSVD1 24 +#define BM_PXP_AS_CLRKEYLOW_1_RSVD1 0xFF000000 +#define BF_PXP_AS_CLRKEYLOW_1_RSVD1(v) \ + (((v) << 24) & BM_PXP_AS_CLRKEYLOW_1_RSVD1) +#define BP_PXP_AS_CLRKEYLOW_1_PIXEL 0 +#define BM_PXP_AS_CLRKEYLOW_1_PIXEL 0x00FFFFFF +#define BF_PXP_AS_CLRKEYLOW_1_PIXEL(v) \ + (((v) << 0) & BM_PXP_AS_CLRKEYLOW_1_PIXEL) + +#define HW_PXP_AS_CLRKEYHIGH_1 (0x00000300) + +#define BP_PXP_AS_CLRKEYHIGH_1_RSVD1 24 +#define BM_PXP_AS_CLRKEYHIGH_1_RSVD1 0xFF000000 +#define BF_PXP_AS_CLRKEYHIGH_1_RSVD1(v) \ + (((v) << 24) & BM_PXP_AS_CLRKEYHIGH_1_RSVD1) +#define BP_PXP_AS_CLRKEYHIGH_1_PIXEL 0 +#define BM_PXP_AS_CLRKEYHIGH_1_PIXEL 0x00FFFFFF +#define BF_PXP_AS_CLRKEYHIGH_1_PIXEL(v) \ + (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_1_PIXEL) + +#define HW_PXP_CTRL2 (0x00000310) +#define HW_PXP_CTRL2_SET (0x00000314) +#define HW_PXP_CTRL2_CLR (0x00000318) +#define HW_PXP_CTRL2_TOG (0x0000031c) + +#define BP_PXP_CTRL2_RSVD3 28 +#define BM_PXP_CTRL2_RSVD3 0xF0000000 +#define BF_PXP_CTRL2_RSVD3(v) \ + (((v) << 28) & BM_PXP_CTRL2_RSVD3) +#define BM_PXP_CTRL2_ENABLE_ROTATE1 0x08000000 +#define BF_PXP_CTRL2_ENABLE_ROTATE1(v) \ + (((v) << 27) & BM_PXP_CTRL2_ENABLE_ROTATE1) +#define BM_PXP_CTRL2_ENABLE_ROTATE0 0x04000000 +#define BF_PXP_CTRL2_ENABLE_ROTATE0(v) \ + (((v) << 26) & BM_PXP_CTRL2_ENABLE_ROTATE0) +#define BM_PXP_CTRL2_ENABLE_LUT 0x02000000 +#define BF_PXP_CTRL2_ENABLE_LUT(v) \ + (((v) << 25) & BM_PXP_CTRL2_ENABLE_LUT) +#define BM_PXP_CTRL2_ENABLE_CSC2 0x01000000 +#define BF_PXP_CTRL2_ENABLE_CSC2(v) \ + (((v) << 24) & BM_PXP_CTRL2_ENABLE_CSC2) +#define BM_PXP_CTRL2_BLOCK_SIZE 0x00800000 +#define BF_PXP_CTRL2_BLOCK_SIZE(v) \ + (((v) << 23) & BM_PXP_CTRL2_BLOCK_SIZE) +#define BV_PXP_CTRL2_BLOCK_SIZE__8X8 0x0 +#define BV_PXP_CTRL2_BLOCK_SIZE__16X16 0x1 +#define BM_PXP_CTRL2_RSVD2 0x00400000 +#define BF_PXP_CTRL2_RSVD2(v) \ + (((v) << 22) & BM_PXP_CTRL2_RSVD2) +#define BM_PXP_CTRL2_ENABLE_ALPHA_B 0x00200000 +#define BF_PXP_CTRL2_ENABLE_ALPHA_B(v) \ + (((v) << 21) & BM_PXP_CTRL2_ENABLE_ALPHA_B) +#define BM_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE 0x00100000 +#define BF_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE(v) \ + (((v) << 20) & BM_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE) +#define BM_PXP_CTRL2_ENABLE_WFE_B 0x00080000 +#define BF_PXP_CTRL2_ENABLE_WFE_B(v) \ + (((v) << 19) & BM_PXP_CTRL2_ENABLE_WFE_B) +#define BM_PXP_CTRL2_ENABLE_WFE_A 0x00040000 +#define BF_PXP_CTRL2_ENABLE_WFE_A(v) \ + (((v) << 18) & BM_PXP_CTRL2_ENABLE_WFE_A) +#define BM_PXP_CTRL2_ENABLE_DITHER 0x00020000 +#define BF_PXP_CTRL2_ENABLE_DITHER(v) \ + (((v) << 17) & BM_PXP_CTRL2_ENABLE_DITHER) +#define BM_PXP_CTRL2_RSVD1 0x00010000 +#define BF_PXP_CTRL2_RSVD1(v) \ + (((v) << 16) & BM_PXP_CTRL2_RSVD1) +#define BM_PXP_CTRL2_VFLIP1 0x00008000 +#define BF_PXP_CTRL2_VFLIP1(v) \ + (((v) << 15) & BM_PXP_CTRL2_VFLIP1) +#define BM_PXP_CTRL2_HFLIP1 0x00004000 +#define BF_PXP_CTRL2_HFLIP1(v) \ + (((v) << 14) & BM_PXP_CTRL2_HFLIP1) +#define BP_PXP_CTRL2_ROTATE1 12 +#define BM_PXP_CTRL2_ROTATE1 0x00003000 +#define BF_PXP_CTRL2_ROTATE1(v) \ + (((v) << 12) & BM_PXP_CTRL2_ROTATE1) +#define BV_PXP_CTRL2_ROTATE1__ROT_0 0x0 +#define BV_PXP_CTRL2_ROTATE1__ROT_90 0x1 +#define BV_PXP_CTRL2_ROTATE1__ROT_180 0x2 +#define BV_PXP_CTRL2_ROTATE1__ROT_270 0x3 +#define BM_PXP_CTRL2_VFLIP0 0x00000800 +#define BF_PXP_CTRL2_VFLIP0(v) \ + (((v) << 11) & BM_PXP_CTRL2_VFLIP0) +#define BM_PXP_CTRL2_HFLIP0 0x00000400 +#define BF_PXP_CTRL2_HFLIP0(v) \ + (((v) << 10) & BM_PXP_CTRL2_HFLIP0) +#define BP_PXP_CTRL2_ROTATE0 8 +#define BM_PXP_CTRL2_ROTATE0 0x00000300 +#define BF_PXP_CTRL2_ROTATE0(v) \ + (((v) << 8) & BM_PXP_CTRL2_ROTATE0) +#define BV_PXP_CTRL2_ROTATE0__ROT_0 0x0 +#define BV_PXP_CTRL2_ROTATE0__ROT_90 0x1 +#define BV_PXP_CTRL2_ROTATE0__ROT_180 0x2 +#define BV_PXP_CTRL2_ROTATE0__ROT_270 0x3 +#define BP_PXP_CTRL2_RSVD0 1 +#define BM_PXP_CTRL2_RSVD0 0x000000FE +#define BF_PXP_CTRL2_RSVD0(v) \ + (((v) << 1) & BM_PXP_CTRL2_RSVD0) +#define BM_PXP_CTRL2_ENABLE 0x00000001 +#define BF_PXP_CTRL2_ENABLE(v) \ + (((v) << 0) & BM_PXP_CTRL2_ENABLE) + +#define HW_PXP_POWER_REG0 (0x00000320) + +#define BP_PXP_POWER_REG0_CTRL 12 +#define BM_PXP_POWER_REG0_CTRL 0xFFFFF000 +#define BF_PXP_POWER_REG0_CTRL(v) \ + (((v) << 12) & BM_PXP_POWER_REG0_CTRL) +#define BP_PXP_POWER_REG0_ROT0_MEM_LP_STATE 9 +#define BM_PXP_POWER_REG0_ROT0_MEM_LP_STATE 0x00000E00 +#define BF_PXP_POWER_REG0_ROT0_MEM_LP_STATE(v) \ + (((v) << 9) & BM_PXP_POWER_REG0_ROT0_MEM_LP_STATE) +#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN 6 +#define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN 0x000001C0 +#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN(v) \ + (((v) << 6) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN) +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__NONE 0x0 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__LS 0x1 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__DS 0x2 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__SD 0x4 +#define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN 3 +#define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN 0x00000038 +#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN(v) \ + (((v) << 3) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN) +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__NONE 0x0 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__LS 0x1 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__DS 0x2 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__SD 0x4 +#define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0 0 +#define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0 0x00000007 +#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0(v) \ + (((v) << 0) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0) +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__NONE 0x0 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__LS 0x1 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__DS 0x2 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__SD 0x4 + +#define HW_PXP_POWER_REG1 (0x00000330) + +#define BP_PXP_POWER_REG1_RSVD0 24 +#define BM_PXP_POWER_REG1_RSVD0 0xFF000000 +#define BF_PXP_POWER_REG1_RSVD0(v) \ + (((v) << 24) & BM_PXP_POWER_REG1_RSVD0) +#define BP_PXP_POWER_REG1_ALU_B_MEM_LP_STATE 21 +#define BM_PXP_POWER_REG1_ALU_B_MEM_LP_STATE 0x00E00000 +#define BF_PXP_POWER_REG1_ALU_B_MEM_LP_STATE(v) \ + (((v) << 21) & BM_PXP_POWER_REG1_ALU_B_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_ALU_A_MEM_LP_STATE 18 +#define BM_PXP_POWER_REG1_ALU_A_MEM_LP_STATE 0x001C0000 +#define BF_PXP_POWER_REG1_ALU_A_MEM_LP_STATE(v) \ + (((v) << 18) & BM_PXP_POWER_REG1_ALU_A_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE 15 +#define BM_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE 0x00038000 +#define BF_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE(v) \ + (((v) << 15) & BM_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE 12 +#define BM_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE 0x00007000 +#define BF_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE(v) \ + (((v) << 12) & BM_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE 9 +#define BM_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE 0x00000E00 +#define BF_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE(v) \ + (((v) << 9) & BM_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE 6 +#define BM_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE 0x000001C0 +#define BF_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE(v) \ + (((v) << 6) & BM_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE 3 +#define BM_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE 0x00000038 +#define BF_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE(v) \ + (((v) << 3) & BM_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_ROT1_MEM_LP_STATE 0 +#define BM_PXP_POWER_REG1_ROT1_MEM_LP_STATE 0x00000007 +#define BF_PXP_POWER_REG1_ROT1_MEM_LP_STATE(v) \ + (((v) << 0) & BM_PXP_POWER_REG1_ROT1_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__SD 0x4 + +#define HW_PXP_DATA_PATH_CTRL0 (0x00000340) +#define HW_PXP_DATA_PATH_CTRL0_SET (0x00000344) +#define HW_PXP_DATA_PATH_CTRL0_CLR (0x00000348) +#define HW_PXP_DATA_PATH_CTRL0_TOG (0x0000034c) + +#define BP_PXP_DATA_PATH_CTRL0_MUX15_SEL 30 +#define BM_PXP_DATA_PATH_CTRL0_MUX15_SEL 0xC0000000 +#define BF_PXP_DATA_PATH_CTRL0_MUX15_SEL(v) \ + (((v) << 30) & BM_PXP_DATA_PATH_CTRL0_MUX15_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX14_SEL 28 +#define BM_PXP_DATA_PATH_CTRL0_MUX14_SEL 0x30000000 +#define BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(v) \ + (((v) << 28) & BM_PXP_DATA_PATH_CTRL0_MUX14_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX13_SEL 26 +#define BM_PXP_DATA_PATH_CTRL0_MUX13_SEL 0x0C000000 +#define BF_PXP_DATA_PATH_CTRL0_MUX13_SEL(v) \ + (((v) << 26) & BM_PXP_DATA_PATH_CTRL0_MUX13_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX12_SEL 24 +#define BM_PXP_DATA_PATH_CTRL0_MUX12_SEL 0x03000000 +#define BF_PXP_DATA_PATH_CTRL0_MUX12_SEL(v) \ + (((v) << 24) & BM_PXP_DATA_PATH_CTRL0_MUX12_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX11_SEL 22 +#define BM_PXP_DATA_PATH_CTRL0_MUX11_SEL 0x00C00000 +#define BF_PXP_DATA_PATH_CTRL0_MUX11_SEL(v) \ + (((v) << 22) & BM_PXP_DATA_PATH_CTRL0_MUX11_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX10_SEL 20 +#define BM_PXP_DATA_PATH_CTRL0_MUX10_SEL 0x00300000 +#define BF_PXP_DATA_PATH_CTRL0_MUX10_SEL(v) \ + (((v) << 20) & BM_PXP_DATA_PATH_CTRL0_MUX10_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX9_SEL 18 +#define BM_PXP_DATA_PATH_CTRL0_MUX9_SEL 0x000C0000 +#define BF_PXP_DATA_PATH_CTRL0_MUX9_SEL(v) \ + (((v) << 18) & BM_PXP_DATA_PATH_CTRL0_MUX9_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX8_SEL 16 +#define BM_PXP_DATA_PATH_CTRL0_MUX8_SEL 0x00030000 +#define BF_PXP_DATA_PATH_CTRL0_MUX8_SEL(v) \ + (((v) << 16) & BM_PXP_DATA_PATH_CTRL0_MUX8_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX7_SEL 14 +#define BM_PXP_DATA_PATH_CTRL0_MUX7_SEL 0x0000C000 +#define BF_PXP_DATA_PATH_CTRL0_MUX7_SEL(v) \ + (((v) << 14) & BM_PXP_DATA_PATH_CTRL0_MUX7_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX6_SEL 12 +#define BM_PXP_DATA_PATH_CTRL0_MUX6_SEL 0x00003000 +#define BF_PXP_DATA_PATH_CTRL0_MUX6_SEL(v) \ + (((v) << 12) & BM_PXP_DATA_PATH_CTRL0_MUX6_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX5_SEL 10 +#define BM_PXP_DATA_PATH_CTRL0_MUX5_SEL 0x00000C00 +#define BF_PXP_DATA_PATH_CTRL0_MUX5_SEL(v) \ + (((v) << 10) & BM_PXP_DATA_PATH_CTRL0_MUX5_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX4_SEL 8 +#define BM_PXP_DATA_PATH_CTRL0_MUX4_SEL 0x00000300 +#define BF_PXP_DATA_PATH_CTRL0_MUX4_SEL(v) \ + (((v) << 8) & BM_PXP_DATA_PATH_CTRL0_MUX4_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX3_SEL 6 +#define BM_PXP_DATA_PATH_CTRL0_MUX3_SEL 0x000000C0 +#define BF_PXP_DATA_PATH_CTRL0_MUX3_SEL(v) \ + (((v) << 6) & BM_PXP_DATA_PATH_CTRL0_MUX3_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX2_SEL 4 +#define BM_PXP_DATA_PATH_CTRL0_MUX2_SEL 0x00000030 +#define BF_PXP_DATA_PATH_CTRL0_MUX2_SEL(v) \ + (((v) << 4) & BM_PXP_DATA_PATH_CTRL0_MUX2_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX1_SEL 2 +#define BM_PXP_DATA_PATH_CTRL0_MUX1_SEL 0x0000000C +#define BF_PXP_DATA_PATH_CTRL0_MUX1_SEL(v) \ + (((v) << 2) & BM_PXP_DATA_PATH_CTRL0_MUX1_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX0_SEL 0 +#define BM_PXP_DATA_PATH_CTRL0_MUX0_SEL 0x00000003 +#define BF_PXP_DATA_PATH_CTRL0_MUX0_SEL(v) \ + (((v) << 0) & BM_PXP_DATA_PATH_CTRL0_MUX0_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__3 0x3 + +#define HW_PXP_DATA_PATH_CTRL1 (0x00000350) +#define HW_PXP_DATA_PATH_CTRL1_SET (0x00000354) +#define HW_PXP_DATA_PATH_CTRL1_CLR (0x00000358) +#define HW_PXP_DATA_PATH_CTRL1_TOG (0x0000035c) + +#define BP_PXP_DATA_PATH_CTRL1_RSVD0 4 +#define BM_PXP_DATA_PATH_CTRL1_RSVD0 0xFFFFFFF0 +#define BF_PXP_DATA_PATH_CTRL1_RSVD0(v) \ + (((v) << 4) & BM_PXP_DATA_PATH_CTRL1_RSVD0) +#define BP_PXP_DATA_PATH_CTRL1_MUX17_SEL 2 +#define BM_PXP_DATA_PATH_CTRL1_MUX17_SEL 0x0000000C +#define BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(v) \ + (((v) << 2) & BM_PXP_DATA_PATH_CTRL1_MUX17_SEL) +#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL1_MUX16_SEL 0 +#define BM_PXP_DATA_PATH_CTRL1_MUX16_SEL 0x00000003 +#define BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(v) \ + (((v) << 0) & BM_PXP_DATA_PATH_CTRL1_MUX16_SEL) +#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__3 0x3 + +#define HW_PXP_INIT_MEM_CTRL (0x00000360) +#define HW_PXP_INIT_MEM_CTRL_SET (0x00000364) +#define HW_PXP_INIT_MEM_CTRL_CLR (0x00000368) +#define HW_PXP_INIT_MEM_CTRL_TOG (0x0000036c) + +#define BM_PXP_INIT_MEM_CTRL_START 0x80000000 +#define BF_PXP_INIT_MEM_CTRL_START(v) \ + (((v) << 31) & BM_PXP_INIT_MEM_CTRL_START) +#define BP_PXP_INIT_MEM_CTRL_SELECT 27 +#define BM_PXP_INIT_MEM_CTRL_SELECT 0x78000000 +#define BF_PXP_INIT_MEM_CTRL_SELECT(v) \ + (((v) << 27) & BM_PXP_INIT_MEM_CTRL_SELECT) +#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_LUT 0x0 +#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_ERR0 0x1 +#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_ERR1 0x2 +#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER1_LUT 0x3 +#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER2_LUT 0x4 +#define BV_PXP_INIT_MEM_CTRL_SELECT__ALU_A 0x5 +#define BV_PXP_INIT_MEM_CTRL_SELECT__ALU_B 0x6 +#define BV_PXP_INIT_MEM_CTRL_SELECT__WFE_A_FETCH 0x7 +#define BV_PXP_INIT_MEM_CTRL_SELECT__WFE_B_FETCH 0x8 +#define BV_PXP_INIT_MEM_CTRL_SELECT__RESERVED 0x15 +#define BP_PXP_INIT_MEM_CTRL_RSVD0 16 +#define BM_PXP_INIT_MEM_CTRL_RSVD0 0x07FF0000 +#define BF_PXP_INIT_MEM_CTRL_RSVD0(v) \ + (((v) << 16) & BM_PXP_INIT_MEM_CTRL_RSVD0) +#define BP_PXP_INIT_MEM_CTRL_ADDR 0 +#define BM_PXP_INIT_MEM_CTRL_ADDR 0x0000FFFF +#define BF_PXP_INIT_MEM_CTRL_ADDR(v) \ + (((v) << 0) & BM_PXP_INIT_MEM_CTRL_ADDR) + +#define HW_PXP_INIT_MEM_DATA (0x00000370) + +#define BP_PXP_INIT_MEM_DATA_DATA 0 +#define BM_PXP_INIT_MEM_DATA_DATA 0xFFFFFFFF +#define BF_PXP_INIT_MEM_DATA_DATA(v) (v) + +#define HW_PXP_INIT_MEM_DATA_HIGH (0x00000380) + +#define BP_PXP_INIT_MEM_DATA_HIGH_DATA 0 +#define BM_PXP_INIT_MEM_DATA_HIGH_DATA 0xFFFFFFFF +#define BF_PXP_INIT_MEM_DATA_HIGH_DATA(v) (v) + +#define HW_PXP_IRQ_MASK (0x00000390) +#define HW_PXP_IRQ_MASK_SET (0x00000394) +#define HW_PXP_IRQ_MASK_CLR (0x00000398) +#define HW_PXP_IRQ_MASK_TOG (0x0000039c) + +#define BM_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN 0x80000000 +#define BF_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN(v) \ + (((v) << 31) & BM_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN) +#define BP_PXP_IRQ_MASK_RSVD1 16 +#define BM_PXP_IRQ_MASK_RSVD1 0x7FFF0000 +#define BF_PXP_IRQ_MASK_RSVD1(v) \ + (((v) << 16) & BM_PXP_IRQ_MASK_RSVD1) +#define BM_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN 0x00008000 +#define BF_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN(v) \ + (((v) << 15) & BM_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN 0x00004000 +#define BF_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN(v) \ + (((v) << 14) & BM_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN 0x00002000 +#define BF_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN(v) \ + (((v) << 13) & BM_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN 0x00001000 +#define BF_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN(v) \ + (((v) << 12) & BM_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN 0x00000800 +#define BF_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN(v) \ + (((v) << 11) & BM_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN 0x00000400 +#define BF_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN(v) \ + (((v) << 10) & BM_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN 0x00000200 +#define BF_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN(v) \ + (((v) << 9) & BM_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN 0x00000100 +#define BF_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN(v) \ + (((v) << 8) & BM_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN 0x00000080 +#define BF_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN(v) \ + (((v) << 7) & BM_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN 0x00000040 +#define BF_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN(v) \ + (((v) << 6) & BM_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN 0x00000020 +#define BF_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN(v) \ + (((v) << 5) & BM_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN) +#define BM_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN 0x00000010 +#define BF_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN(v) \ + (((v) << 4) & BM_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN) +#define BM_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN 0x00000008 +#define BF_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN(v) \ + (((v) << 3) & BM_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN 0x00000004 +#define BF_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN(v) \ + (((v) << 2) & BM_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN 0x00000002 +#define BF_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN(v) \ + (((v) << 1) & BM_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN) +#define BM_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN 0x00000001 +#define BF_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN(v) \ + (((v) << 0) & BM_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN) + +#define HW_PXP_IRQ (0x000003a0) +#define HW_PXP_IRQ_SET (0x000003a4) +#define HW_PXP_IRQ_CLR (0x000003a8) +#define HW_PXP_IRQ_TOG (0x000003ac) + +#define BM_PXP_IRQ_COMPRESS_DONE_IRQ 0x80000000 +#define BF_PXP_IRQ_COMPRESS_DONE_IRQ(v) \ + (((v) << 31) & BM_PXP_IRQ_COMPRESS_DONE_IRQ) +#define BP_PXP_IRQ_RSVD1 16 +#define BM_PXP_IRQ_RSVD1 0x7FFF0000 +#define BF_PXP_IRQ_RSVD1(v) \ + (((v) << 16) & BM_PXP_IRQ_RSVD1) +#define BM_PXP_IRQ_WFE_B_STORE_IRQ 0x00008000 +#define BF_PXP_IRQ_WFE_B_STORE_IRQ(v) \ + (((v) << 15) & BM_PXP_IRQ_WFE_B_STORE_IRQ) +#define BM_PXP_IRQ_WFE_A_STORE_IRQ 0x00004000 +#define BF_PXP_IRQ_WFE_A_STORE_IRQ(v) \ + (((v) << 14) & BM_PXP_IRQ_WFE_A_STORE_IRQ) +#define BM_PXP_IRQ_DITHER_STORE_IRQ 0x00002000 +#define BF_PXP_IRQ_DITHER_STORE_IRQ(v) \ + (((v) << 13) & BM_PXP_IRQ_DITHER_STORE_IRQ) +#define BM_PXP_IRQ_FIRST_STORE_IRQ 0x00001000 +#define BF_PXP_IRQ_FIRST_STORE_IRQ(v) \ + (((v) << 12) & BM_PXP_IRQ_FIRST_STORE_IRQ) +#define BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ 0x00000800 +#define BF_PXP_IRQ_WFE_B_CH1_STORE_IRQ(v) \ + (((v) << 11) & BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ) +#define BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ 0x00000400 +#define BF_PXP_IRQ_WFE_B_CH0_STORE_IRQ(v) \ + (((v) << 10) & BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ) +#define BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ 0x00000200 +#define BF_PXP_IRQ_WFE_A_CH1_STORE_IRQ(v) \ + (((v) << 9) & BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ) +#define BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ 0x00000100 +#define BF_PXP_IRQ_WFE_A_CH0_STORE_IRQ(v) \ + (((v) << 8) & BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ) +#define BM_PXP_IRQ_DITHER_CH1_STORE_IRQ 0x00000080 +#define BF_PXP_IRQ_DITHER_CH1_STORE_IRQ(v) \ + (((v) << 7) & BM_PXP_IRQ_DITHER_CH1_STORE_IRQ) +#define BM_PXP_IRQ_DITHER_CH0_STORE_IRQ 0x00000040 +#define BF_PXP_IRQ_DITHER_CH0_STORE_IRQ(v) \ + (((v) << 6) & BM_PXP_IRQ_DITHER_CH0_STORE_IRQ) +#define BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ 0x00000020 +#define BF_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ(v) \ + (((v) << 5) & BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ) +#define BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ 0x00000010 +#define BF_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ(v) \ + (((v) << 4) & BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ) +#define BM_PXP_IRQ_FIRST_CH1_STORE_IRQ 0x00000008 +#define BF_PXP_IRQ_FIRST_CH1_STORE_IRQ(v) \ + (((v) << 3) & BM_PXP_IRQ_FIRST_CH1_STORE_IRQ) +#define BM_PXP_IRQ_FIRST_CH0_STORE_IRQ 0x00000004 +#define BF_PXP_IRQ_FIRST_CH0_STORE_IRQ(v) \ + (((v) << 2) & BM_PXP_IRQ_FIRST_CH0_STORE_IRQ) +#define BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ 0x00000002 +#define BF_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ(v) \ + (((v) << 1) & BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ) +#define BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ 0x00000001 +#define BF_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ(v) \ + (((v) << 0) & BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ) + +#define HW_PXP_NEXT (0x00000400) + +#define BP_PXP_NEXT_POINTER 2 +#define BM_PXP_NEXT_POINTER 0xFFFFFFFC +#define BF_PXP_NEXT_POINTER(v) \ + (((v) << 2) & BM_PXP_NEXT_POINTER) +#define BM_PXP_NEXT_RSVD 0x00000002 +#define BF_PXP_NEXT_RSVD(v) \ + (((v) << 1) & BM_PXP_NEXT_RSVD) +#define BM_PXP_NEXT_ENABLED 0x00000001 +#define BF_PXP_NEXT_ENABLED(v) \ + (((v) << 0) & BM_PXP_NEXT_ENABLED) + +#define HW_PXP_DEBUGCTRL (0x00000410) + +#define BP_PXP_DEBUGCTRL_RSVD 12 +#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFF000 +#define BF_PXP_DEBUGCTRL_RSVD(v) \ + (((v) << 12) & BM_PXP_DEBUGCTRL_RSVD) +#define BP_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 8 +#define BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 0x00000F00 +#define BF_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT(v) \ + (((v) << 8) & BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT) +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__NONE 0x0 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MISS_CNT 0x1 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__HIT_CNT 0x2 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__LAT_CNT 0x4 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MAX_LAT 0x8 +#define BP_PXP_DEBUGCTRL_SELECT 0 +#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF +#define BF_PXP_DEBUGCTRL_SELECT(v) \ + (((v) << 0) & BM_PXP_DEBUGCTRL_SELECT) +#define BV_PXP_DEBUGCTRL_SELECT__NONE 0x0 +#define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x1 +#define BV_PXP_DEBUGCTRL_SELECT__PSBUF 0x2 +#define BV_PXP_DEBUGCTRL_SELECT__PSBAX 0x3 +#define BV_PXP_DEBUGCTRL_SELECT__PSBAY 0x4 +#define BV_PXP_DEBUGCTRL_SELECT__ASBUF 0x5 +#define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6 +#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF0 0x7 +#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF1 0x8 +#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF2 0x9 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_STAT 0x10 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_MISS 0x11 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_HIT 0x12 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_LAT 0x13 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_MAX_LAT 0x14 + +#define HW_PXP_DEBUG (0x00000420) + +#define BP_PXP_DEBUG_DATA 0 +#define BM_PXP_DEBUG_DATA 0xFFFFFFFF +#define BF_PXP_DEBUG_DATA(v) (v) + +#define HW_PXP_VERSION (0x00000430) + +#define BP_PXP_VERSION_MAJOR 24 +#define BM_PXP_VERSION_MAJOR 0xFF000000 +#define BF_PXP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_PXP_VERSION_MAJOR) +#define BP_PXP_VERSION_MINOR 16 +#define BM_PXP_VERSION_MINOR 0x00FF0000 +#define BF_PXP_VERSION_MINOR(v) \ + (((v) << 16) & BM_PXP_VERSION_MINOR) +#define BP_PXP_VERSION_STEP 0 +#define BM_PXP_VERSION_STEP 0x0000FFFF +#define BF_PXP_VERSION_STEP(v) \ + (((v) << 0) & BM_PXP_VERSION_STEP) + +#define HW_PXP_INPUT_FETCH_CTRL_CH0 (0x00000450) +#define HW_PXP_INPUT_FETCH_CTRL_CH0_SET (0x00000454) +#define HW_PXP_INPUT_FETCH_CTRL_CH0_CLR (0x00000458) +#define HW_PXP_INPUT_FETCH_CTRL_CH0_TOG (0x0000045c) + +#define BM_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN 0x80000000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN(v) \ + (((v) << 31) & BM_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN__1 0x1 +#define BP_PXP_INPUT_FETCH_CTRL_CH0_RSVD0 26 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD0 0x7C000000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_RSVD0(v) \ + (((v) << 26) & BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD0) +#define BP_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM 24 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM 0x03000000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(v) \ + (((v) << 24) & BM_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__1 0x1 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__2 0x2 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__3 0x3 +#define BP_PXP_INPUT_FETCH_CTRL_CH0_RSVD1 18 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD1 0x00FC0000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_RSVD1(v) \ + (((v) << 18) & BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD1) +#define BP_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES 16 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES 0x00030000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_INPUT_FETCH_CTRL_CH0_RSVD2 14 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD2 0x0000C000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD2) +#define BP_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE 12 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE 0x00003000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE(v) \ + (((v) << 12) & BM_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_90 0x1 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_180 0x2 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_270 0x3 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD3 0x00000800 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_RSVD3(v) \ + (((v) << 11) & BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD3) +#define BM_PXP_INPUT_FETCH_CTRL_CH0_VFLIP 0x00000400 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_VFLIP(v) \ + (((v) << 10) & BM_PXP_INPUT_FETCH_CTRL_CH0_VFLIP) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_VFLIP__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_VFLIP__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_HFLIP 0x00000200 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_HFLIP(v) \ + (((v) << 9) & BM_PXP_INPUT_FETCH_CTRL_CH0_HFLIP) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HFLIP__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HFLIP__1 0x1 +#define BP_PXP_INPUT_FETCH_CTRL_CH0_RSVD4 6 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD4 0x000001C0 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_RSVD4(v) \ + (((v) << 6) & BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD4) +#define BM_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE 0x00000020 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE(v) \ + (((v) << 5) & BM_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN 0x00000010 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN(v) \ + (((v) << 4) & BM_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN 0x00000008 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16 0x00000004 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16__8x8 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16__16x16 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN 0x00000002 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_CH_EN 0x00000001 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_CH_EN(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_CTRL_CH0_CH_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_CH_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_CH_EN__1 0x1 + +#define HW_PXP_INPUT_FETCH_CTRL_CH1 (0x00000460) +#define HW_PXP_INPUT_FETCH_CTRL_CH1_SET (0x00000464) +#define HW_PXP_INPUT_FETCH_CTRL_CH1_CLR (0x00000468) +#define HW_PXP_INPUT_FETCH_CTRL_CH1_TOG (0x0000046c) + +#define BP_PXP_INPUT_FETCH_CTRL_CH1_RSVD0 26 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD0 0xFC000000 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_RSVD0(v) \ + (((v) << 26) & BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD0) +#define BP_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM 24 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM 0x03000000 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM(v) \ + (((v) << 24) & BM_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__1 0x1 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__2 0x2 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__3 0x3 +#define BP_PXP_INPUT_FETCH_CTRL_CH1_RSVD1 18 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD1 0x00FC0000 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_RSVD1(v) \ + (((v) << 18) & BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD1) +#define BP_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES 16 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES 0x00030000 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_INPUT_FETCH_CTRL_CH1_RSVD2 14 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD2 0x0000C000 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_RSVD2(v) \ + (((v) << 14) & BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD2) +#define BP_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE 12 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE 0x00003000 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE(v) \ + (((v) << 12) & BM_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_90 0x1 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_180 0x2 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_270 0x3 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD3 0x00000800 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_RSVD3(v) \ + (((v) << 11) & BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD3) +#define BM_PXP_INPUT_FETCH_CTRL_CH1_VFLIP 0x00000400 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_VFLIP(v) \ + (((v) << 10) & BM_PXP_INPUT_FETCH_CTRL_CH1_VFLIP) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_VFLIP__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_VFLIP__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_HFLIP 0x00000200 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_HFLIP(v) \ + (((v) << 9) & BM_PXP_INPUT_FETCH_CTRL_CH1_HFLIP) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HFLIP__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HFLIP__1 0x1 +#define BP_PXP_INPUT_FETCH_CTRL_CH1_RSVD4 5 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD4 0x000001E0 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_RSVD4(v) \ + (((v) << 5) & BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD4) +#define BM_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN 0x00000010 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN(v) \ + (((v) << 4) & BM_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN 0x00000008 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16 0x00000004 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16__8x8 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16__16x16 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN 0x00000002 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_CH_EN 0x00000001 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_CH_EN(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_CTRL_CH1_CH_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_CH_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_CH_EN__1 0x1 + +#define HW_PXP_INPUT_FETCH_STATUS_CH0 (0x00000470) + +#define BP_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y 16 +#define BM_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y) +#define BP_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X 0 +#define BM_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X 0x0000FFFF +#define BF_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X) + +#define HW_PXP_INPUT_FETCH_STATUS_CH1 (0x00000480) + +#define BP_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y 16 +#define BM_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y) +#define BP_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X 0 +#define BM_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X 0x0000FFFF +#define BF_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X) + +#define HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0 (0x00000490) + +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y 16 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y) +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X 0 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X 0x0000FFFF +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X) + +#define HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0 (0x000004a0) + +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y 16 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y) +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X 0 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X 0x0000FFFF +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X) + +#define HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1 (0x000004b0) + +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y 16 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y) +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X 0 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X 0x0000FFFF +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X) + +#define HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1 (0x000004c0) + +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y 16 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y) +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X 0 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X 0x0000FFFF +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X) + +#define HW_PXP_INPUT_FETCH_SIZE_CH0 (0x000004d0) + +#define BP_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT 16 +#define BM_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT) +#define BP_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH 0 +#define BM_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH 0x0000FFFF +#define BF_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH) + +#define HW_PXP_INPUT_FETCH_SIZE_CH1 (0x000004e0) + +#define BP_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT 16 +#define BM_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT) +#define BP_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH 0 +#define BM_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH 0x0000FFFF +#define BF_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH) + +#define HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0 (0x000004f0) + +#define BP_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR 0 +#define BM_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR 0xFFFFFFFF +#define BF_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR(v) (v) + +#define HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1 (0x00000500) + +#define BP_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR 0 +#define BM_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR 0xFFFFFFFF +#define BF_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR(v) (v) + +#define HW_PXP_INPUT_FETCH_PITCH (0x00000510) + +#define BP_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH 16 +#define BM_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH) +#define BP_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH 0 +#define BM_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH 0x0000FFFF +#define BF_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH) + +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0 (0x00000520) +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET (0x00000524) +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR (0x00000528) +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG (0x0000052c) + +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0 13 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0 0xFFFFE000 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0(v) \ + (((v) << 13) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0) +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00001000 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ + (((v) << 12) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN 0x00000800 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN(v) \ + (((v) << 11) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN__1 0x1 +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT 8 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT 0x00000700 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT(v) \ + (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__1 0x1 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__2 0x2 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__3 0x3 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__4 0x4 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__5 0x5 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__6 0x6 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__7 0x7 +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1 2 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1 0x000000FC +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1(v) \ + (((v) << 2) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1) +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP 0 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP 0x00000003 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__3 0x3 + +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1 (0x00000530) +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET (0x00000534) +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR (0x00000538) +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG (0x0000053c) + +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0 13 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0 0xFFFFE000 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0(v) \ + (((v) << 13) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0) +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS 0x00001000 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS(v) \ + (((v) << 12) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS__1 0x1 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN 0x00000800 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN(v) \ + (((v) << 11) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN__1 0x1 +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT 8 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT 0x00000700 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT(v) \ + (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__1 0x1 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__2 0x2 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__3 0x3 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__4 0x4 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__5 0x5 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__6 0x6 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__7 0x7 +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1 2 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1 0x000000FC +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1(v) \ + (((v) << 2) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1) +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP 0 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP 0x00000003 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__3 0x3 + +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0 (0x00000540) +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET (0x00000544) +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR (0x00000548) +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG (0x0000054c) + +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0 29 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0 0xE0000000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0(v) \ + (((v) << 29) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3 24 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3 0x1F000000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3(v) \ + (((v) << 24) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1 21 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1 0x00E00000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1(v) \ + (((v) << 21) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2 16 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2 0x001F0000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2 13 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2 0x0000E000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2(v) \ + (((v) << 13) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1 8 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1 0x00001F00 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1(v) \ + (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3 5 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3 0x000000E0 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3(v) \ + (((v) << 5) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0 0 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0 0x0000001F +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0) + +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1 (0x00000550) +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET (0x00000554) +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR (0x00000558) +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG (0x0000055c) + +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0 29 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0 0xE0000000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0(v) \ + (((v) << 29) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3 24 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3 0x1F000000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3(v) \ + (((v) << 24) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1 21 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1 0x00E00000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1(v) \ + (((v) << 21) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2 16 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2 0x001F0000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2 13 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2 0x0000E000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2(v) \ + (((v) << 13) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1 8 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1 0x00001F00 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1(v) \ + (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3 5 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3 0x000000E0 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3(v) \ + (((v) << 5) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0 0 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0 0x0000001F +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0) + +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0 (0x00000560) +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET (0x00000564) +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR (0x00000568) +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG (0x0000056c) + +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0 16 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3 12 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3 0x0000F000 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3(v) \ + (((v) << 12) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2 8 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2 0x00000F00 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2(v) \ + (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1 4 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1 0x000000F0 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1(v) \ + (((v) << 4) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0 0 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0 0x0000000F +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0) + +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1 (0x00000570) +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET (0x00000574) +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR (0x00000578) +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG (0x0000057c) + +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0 16 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3 12 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3 0x0000F000 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3(v) \ + (((v) << 12) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2 8 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2 0x00000F00 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2(v) \ + (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1 4 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1 0x000000F0 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1(v) \ + (((v) << 4) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0 0 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0 0x0000000F +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0) + +#define HW_PXP_INPUT_FETCH_ADDR_0_CH0 (0x00000580) + +#define BP_PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0 0 +#define BM_PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0(v) (v) + +#define HW_PXP_INPUT_FETCH_ADDR_1_CH0 (0x00000590) + +#define BP_PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1 0 +#define BM_PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1(v) (v) + +#define HW_PXP_INPUT_FETCH_ADDR_0_CH1 (0x000005a0) + +#define BP_PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0 0 +#define BM_PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0(v) (v) + +#define HW_PXP_INPUT_FETCH_ADDR_1_CH1 (0x000005b0) + +#define BP_PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1 0 +#define BM_PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1(v) (v) + +#define HW_PXP_INPUT_STORE_CTRL_CH0 (0x000005c0) +#define HW_PXP_INPUT_STORE_CTRL_CH0_SET (0x000005c4) +#define HW_PXP_INPUT_STORE_CTRL_CH0_CLR (0x000005c8) +#define HW_PXP_INPUT_STORE_CTRL_CH0_TOG (0x000005cc) + +#define BM_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN 0x80000000 +#define BF_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN(v) \ + (((v) << 31) & BM_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN__1 0x1 +#define BP_PXP_INPUT_STORE_CTRL_CH0_RSVD0 25 +#define BM_PXP_INPUT_STORE_CTRL_CH0_RSVD0 0x7E000000 +#define BF_PXP_INPUT_STORE_CTRL_CH0_RSVD0(v) \ + (((v) << 25) & BM_PXP_INPUT_STORE_CTRL_CH0_RSVD0) +#define BM_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL 0x01000000 +#define BF_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL) +#define BV_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL__1 0x1 +#define BP_PXP_INPUT_STORE_CTRL_CH0_RSVD1 18 +#define BM_PXP_INPUT_STORE_CTRL_CH0_RSVD1 0x00FC0000 +#define BF_PXP_INPUT_STORE_CTRL_CH0_RSVD1(v) \ + (((v) << 18) & BM_PXP_INPUT_STORE_CTRL_CH0_RSVD1) +#define BP_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES 16 +#define BM_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES 0x00030000 +#define BF_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES) +#define BV_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_INPUT_STORE_CTRL_CH0_RSVD2 12 +#define BM_PXP_INPUT_STORE_CTRL_CH0_RSVD2 0x0000F000 +#define BF_PXP_INPUT_STORE_CTRL_CH0_RSVD2(v) \ + (((v) << 12) & BM_PXP_INPUT_STORE_CTRL_CH0_RSVD2) +#define BM_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN 0x00000800 +#define BF_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN(v) \ + (((v) << 11) & BM_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL 0x00000400 +#define BF_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL) +#define BV_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_RSVD3 0x00000080 +#define BF_PXP_INPUT_STORE_CTRL_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_CTRL_CH0_RSVD3) +#define BP_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM 5 +#define BM_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM) +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN 0x00000010 +#define BF_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN 0x00000008 +#define BF_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16 0x00000004 +#define BF_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16) +#define BV_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16__8x8 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16__16x16 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN 0x00000002 +#define BF_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_CH_EN 0x00000001 +#define BF_PXP_INPUT_STORE_CTRL_CH0_CH_EN(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_CTRL_CH0_CH_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_CH_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_CH_EN__1 0x1 + +#define HW_PXP_INPUT_STORE_CTRL_CH1 (0x000005d0) +#define HW_PXP_INPUT_STORE_CTRL_CH1_SET (0x000005d4) +#define HW_PXP_INPUT_STORE_CTRL_CH1_CLR (0x000005d8) +#define HW_PXP_INPUT_STORE_CTRL_CH1_TOG (0x000005dc) + +#define BP_PXP_INPUT_STORE_CTRL_CH1_RSVD0 18 +#define BM_PXP_INPUT_STORE_CTRL_CH1_RSVD0 0xFFFC0000 +#define BF_PXP_INPUT_STORE_CTRL_CH1_RSVD0(v) \ + (((v) << 18) & BM_PXP_INPUT_STORE_CTRL_CH1_RSVD0) +#define BP_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES 16 +#define BM_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES 0x00030000 +#define BF_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES) +#define BV_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_INPUT_STORE_CTRL_CH1_RSVD1 11 +#define BM_PXP_INPUT_STORE_CTRL_CH1_RSVD1 0x0000F800 +#define BF_PXP_INPUT_STORE_CTRL_CH1_RSVD1(v) \ + (((v) << 11) & BM_PXP_INPUT_STORE_CTRL_CH1_RSVD1) +#define BM_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL 0x00000400 +#define BF_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL) +#define BV_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_RSVD3 0x00000080 +#define BF_PXP_INPUT_STORE_CTRL_CH1_RSVD3(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_CTRL_CH1_RSVD3) +#define BP_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM 5 +#define BM_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM) +#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN 0x00000010 +#define BF_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN 0x00000008 +#define BF_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16 0x00000004 +#define BF_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16) +#define BV_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16__8x8 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16__16x16 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN 0x00000002 +#define BF_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_CH_EN 0x00000001 +#define BF_PXP_INPUT_STORE_CTRL_CH1_CH_EN(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_CTRL_CH1_CH_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH1_CH_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_CH_EN__1 0x1 + +#define HW_PXP_INPUT_STORE_STATUS_CH0 (0x000005e0) + +#define BP_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y 16 +#define BM_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y) +#define BP_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X 0 +#define BM_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X) + +#define HW_PXP_INPUT_STORE_STATUS_CH1 (0x000005f0) + +#define BP_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y 16 +#define BM_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y) +#define BP_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X 0 +#define BM_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X) + +#define HW_PXP_INPUT_STORE_SIZE_CH0 (0x00000600) + +#define BP_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT 16 +#define BM_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT) +#define BP_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH 0 +#define BM_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH 0x0000FFFF +#define BF_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH) + +#define HW_PXP_INPUT_STORE_SIZE_CH1 (0x00000610) + +#define BP_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT 16 +#define BM_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT) +#define BP_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH 0 +#define BM_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH 0x0000FFFF +#define BF_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH) + +#define HW_PXP_INPUT_STORE_PITCH (0x00000620) + +#define BP_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH 16 +#define BM_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH 0xFFFF0000 +#define BF_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH) +#define BP_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH 0 +#define BM_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH 0x0000FFFF +#define BF_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH) + +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0 (0x00000630) +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET (0x00000634) +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR (0x00000638) +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG (0x0000063c) + +#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0 8 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0 0xFFFFFF00 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0) +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00000080 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD1 0x00000040 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD1(v) \ + (((v) << 6) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD1) +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2 0 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2 0x00000003 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2) + +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1 (0x00000640) +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET (0x00000644) +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR (0x00000648) +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG (0x0000064c) + +#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0 6 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0 0xFFFFFFC0 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0(v) \ + (((v) << 6) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0) +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2 0 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2 0x00000003 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2) + +#define HW_PXP_INPUT_STORE_ADDR_0_CH0 (0x00000690) + +#define BP_PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0 +#define BM_PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_INPUT_STORE_ADDR_1_CH0 (0x000006a0) + +#define BP_PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0 +#define BM_PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_INPUT_STORE_FILL_DATA_CH0 (0x000006b0) + +#define BP_PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0 +#define BM_PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_ADDR_0_CH1 (0x000006c0) + +#define BP_PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0 +#define BM_PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_INPUT_STORE_ADDR_1_CH1 (0x000006d0) + +#define BP_PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0 +#define BM_PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK0_H_CH0 (0x000006e0) + +#define BP_PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK0_L_CH0 (0x000006f0) + +#define BP_PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK1_H_CH0 (0x00000700) + +#define BP_PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK1_L_CH0 (0x00000710) + +#define BP_PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK2_H_CH0 (0x00000720) + +#define BP_PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK2_L_CH0 (0x00000730) + +#define BP_PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK3_H_CH0 (0x00000740) + +#define BP_PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK3_L_CH0 (0x00000750) + +#define BP_PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK4_H_CH0 (0x00000760) + +#define BP_PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK4_L_CH0 (0x00000770) + +#define BP_PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK5_H_CH0 (0x00000780) + +#define BP_PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK5_L_CH0 (0x00000790) + +#define BP_PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK6_H_CH0 (0x000007a0) + +#define BP_PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK6_L_CH0 (0x000007b0) + +#define BP_PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK7_H_CH0 (0x000007c0) + +#define BP_PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK7_L_CH0 (0x000007e0) + +#define BP_PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_SHIFT_L_CH0 (0x000007f0) + +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3 0x80000000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(v) \ + (((v) << 31) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD0 0x40000000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD0) +#define BP_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 24 +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2 0x00800000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(v) \ + (((v) << 23) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD1 0x00400000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD1) +#define BP_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 16 +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1 0x00008000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(v) \ + (((v) << 15) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD2 0x00004000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD2) +#define BP_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 8 +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0 0x00000080 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD3 0x00000040 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD3) +#define BP_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0 +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0) + +#define HW_PXP_INPUT_STORE_D_SHIFT_H_CH0 (0x00000800) + +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7 0x80000000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(v) \ + (((v) << 31) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD0 0x40000000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD0) +#define BP_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 24 +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6 0x00800000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(v) \ + (((v) << 23) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD1 0x00400000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD1) +#define BP_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 16 +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5 0x00008000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(v) \ + (((v) << 15) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD2 0x00004000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD2) +#define BP_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 8 +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4 0x00000080 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD3 0x00000040 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD3) +#define BP_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0 +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4) + +#define HW_PXP_INPUT_STORE_F_SHIFT_L_CH0 (0x00000810) + +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD0 0x80000000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD0) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3 0x40000000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(v) \ + (((v) << 30) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3) +#define BP_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 24 +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD1 0x00800000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD1) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2 0x00400000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(v) \ + (((v) << 22) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2) +#define BP_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 16 +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD2 0x00008000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD2) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1 0x00004000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(v) \ + (((v) << 14) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1) +#define BP_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 8 +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD3 0x00000080 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD3) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0 0x00000040 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(v) \ + (((v) << 6) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0) +#define BP_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0 +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0) + +#define HW_PXP_INPUT_STORE_F_SHIFT_H_CH0 (0x00000820) + +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD0 0x80000000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD0) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7 0x40000000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(v) \ + (((v) << 30) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7) +#define BP_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 24 +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD1 0x00800000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD1) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6 0x00400000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(v) \ + (((v) << 22) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6) +#define BP_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 16 +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD2 0x00008000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD2) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5 0x00004000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(v) \ + (((v) << 14) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5) +#define BP_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 8 +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD3 0x00000080 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD3) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4 0x00000040 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(v) \ + (((v) << 6) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4) +#define BP_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0 +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4) + +#define HW_PXP_INPUT_STORE_F_MASK_L_CH0 (0x00000830) + +#define BP_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3 24 +#define BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3 0xFF000000 +#define BF_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3) +#define BP_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2 16 +#define BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2 0x00FF0000 +#define BF_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2) +#define BP_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1 8 +#define BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1 0x0000FF00 +#define BF_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1) +#define BP_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0 0 +#define BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0 0x000000FF +#define BF_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0) + +#define HW_PXP_INPUT_STORE_F_MASK_H_CH0 (0x00000840) + +#define BP_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7 24 +#define BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7 0xFF000000 +#define BF_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7) +#define BP_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6 16 +#define BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6 0x00FF0000 +#define BF_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6) +#define BP_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5 8 +#define BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5 0x0000FF00 +#define BF_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5) +#define BP_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4 0 +#define BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4 0x000000FF +#define BF_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4) + +#define HW_PXP_DITHER_FETCH_CTRL_CH0 (0x00000850) +#define HW_PXP_DITHER_FETCH_CTRL_CH0_SET (0x00000854) +#define HW_PXP_DITHER_FETCH_CTRL_CH0_CLR (0x00000858) +#define HW_PXP_DITHER_FETCH_CTRL_CH0_TOG (0x0000085c) + +#define BM_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN 0x80000000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN(v) \ + (((v) << 31) & BM_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN__1 0x1 +#define BP_PXP_DITHER_FETCH_CTRL_CH0_RSVD0 26 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD0 0x7C000000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_RSVD0(v) \ + (((v) << 26) & BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD0) +#define BP_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM 24 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM 0x03000000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(v) \ + (((v) << 24) & BM_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__1 0x1 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__2 0x2 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__3 0x3 +#define BP_PXP_DITHER_FETCH_CTRL_CH0_RSVD1 18 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD1 0x00FC0000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_RSVD1(v) \ + (((v) << 18) & BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD1) +#define BP_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES 16 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES 0x00030000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_DITHER_FETCH_CTRL_CH0_RSVD2 14 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD2 0x0000C000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD2) +#define BP_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE 12 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE 0x00003000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE(v) \ + (((v) << 12) & BM_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_90 0x1 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_180 0x2 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_270 0x3 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD3 0x00000800 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_RSVD3(v) \ + (((v) << 11) & BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD3) +#define BM_PXP_DITHER_FETCH_CTRL_CH0_VFLIP 0x00000400 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_VFLIP(v) \ + (((v) << 10) & BM_PXP_DITHER_FETCH_CTRL_CH0_VFLIP) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_VFLIP__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_VFLIP__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_HFLIP 0x00000200 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_HFLIP(v) \ + (((v) << 9) & BM_PXP_DITHER_FETCH_CTRL_CH0_HFLIP) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HFLIP__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HFLIP__1 0x1 +#define BP_PXP_DITHER_FETCH_CTRL_CH0_RSVD4 6 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD4 0x000001C0 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_RSVD4(v) \ + (((v) << 6) & BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD4) +#define BM_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE 0x00000020 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE(v) \ + (((v) << 5) & BM_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN 0x00000010 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN(v) \ + (((v) << 4) & BM_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN 0x00000008 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16 0x00000004 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16__8x8 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16__16x16 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN 0x00000002 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_CH_EN 0x00000001 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_CH_EN(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_CTRL_CH0_CH_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_CH_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_CH_EN__1 0x1 + +#define HW_PXP_DITHER_FETCH_CTRL_CH1 (0x00000860) +#define HW_PXP_DITHER_FETCH_CTRL_CH1_SET (0x00000864) +#define HW_PXP_DITHER_FETCH_CTRL_CH1_CLR (0x00000868) +#define HW_PXP_DITHER_FETCH_CTRL_CH1_TOG (0x0000086c) + +#define BP_PXP_DITHER_FETCH_CTRL_CH1_RSVD0 26 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD0 0xFC000000 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_RSVD0(v) \ + (((v) << 26) & BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD0) +#define BP_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM 24 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM 0x03000000 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM(v) \ + (((v) << 24) & BM_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__1 0x1 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__2 0x2 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__3 0x3 +#define BP_PXP_DITHER_FETCH_CTRL_CH1_RSVD1 18 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD1 0x00FC0000 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_RSVD1(v) \ + (((v) << 18) & BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD1) +#define BP_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES 16 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES 0x00030000 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_DITHER_FETCH_CTRL_CH1_RSVD2 14 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD2 0x0000C000 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_RSVD2(v) \ + (((v) << 14) & BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD2) +#define BP_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE 12 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE 0x00003000 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE(v) \ + (((v) << 12) & BM_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_90 0x1 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_180 0x2 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_270 0x3 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD3 0x00000800 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_RSVD3(v) \ + (((v) << 11) & BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD3) +#define BM_PXP_DITHER_FETCH_CTRL_CH1_VFLIP 0x00000400 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_VFLIP(v) \ + (((v) << 10) & BM_PXP_DITHER_FETCH_CTRL_CH1_VFLIP) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_VFLIP__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_VFLIP__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_HFLIP 0x00000200 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_HFLIP(v) \ + (((v) << 9) & BM_PXP_DITHER_FETCH_CTRL_CH1_HFLIP) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HFLIP__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HFLIP__1 0x1 +#define BP_PXP_DITHER_FETCH_CTRL_CH1_RSVD4 5 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD4 0x000001E0 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_RSVD4(v) \ + (((v) << 5) & BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD4) +#define BM_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN 0x00000010 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN(v) \ + (((v) << 4) & BM_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN 0x00000008 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16 0x00000004 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16__8x8 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16__16x16 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN 0x00000002 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_CH_EN 0x00000001 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_CH_EN(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_CTRL_CH1_CH_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_CH_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_CH_EN__1 0x1 + +#define HW_PXP_DITHER_FETCH_STATUS_CH0 (0x00000870) + +#define BP_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y 16 +#define BM_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y) +#define BP_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X 0 +#define BM_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X 0x0000FFFF +#define BF_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X) + +#define HW_PXP_DITHER_FETCH_STATUS_CH1 (0x00000880) + +#define BP_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y 16 +#define BM_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y) +#define BP_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X 0 +#define BM_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X 0x0000FFFF +#define BF_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X) + +#define HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0 (0x00000890) + +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y 16 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y) +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X 0 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X 0x0000FFFF +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X) + +#define HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0 (0x000008a0) + +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y 16 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y) +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X 0 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X 0x0000FFFF +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X) + +#define HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1 (0x000008b0) + +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y 16 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y) +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X 0 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X 0x0000FFFF +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X) + +#define HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1 (0x000008c0) + +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y 16 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y) +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X 0 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X 0x0000FFFF +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X) + +#define HW_PXP_DITHER_FETCH_SIZE_CH0 (0x000008d0) + +#define BP_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT 16 +#define BM_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT) +#define BP_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH 0 +#define BM_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH 0x0000FFFF +#define BF_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH) + +#define HW_PXP_DITHER_FETCH_SIZE_CH1 (0x000008e0) + +#define BP_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT 16 +#define BM_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT) +#define BP_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH 0 +#define BM_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH 0x0000FFFF +#define BF_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH) + +#define HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0 (0x000008f0) + +#define BP_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR 0 +#define BM_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR 0xFFFFFFFF +#define BF_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR(v) (v) + +#define HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1 (0x00000900) + +#define BP_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR 0 +#define BM_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR 0xFFFFFFFF +#define BF_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR(v) (v) + +#define HW_PXP_DITHER_FETCH_PITCH (0x00000910) + +#define BP_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH 16 +#define BM_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH) +#define BP_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH 0 +#define BM_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH 0x0000FFFF +#define BF_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH) + +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0 (0x00000920) +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET (0x00000924) +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR (0x00000928) +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG (0x0000092c) + +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0 13 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0 0xFFFFE000 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0(v) \ + (((v) << 13) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0) +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00001000 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ + (((v) << 12) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN 0x00000800 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN(v) \ + (((v) << 11) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN__1 0x1 +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT 8 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT 0x00000700 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT(v) \ + (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__1 0x1 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__2 0x2 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__3 0x3 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__4 0x4 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__5 0x5 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__6 0x6 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__7 0x7 +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1 2 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1 0x000000FC +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1(v) \ + (((v) << 2) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1) +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP 0 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP 0x00000003 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__3 0x3 + +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1 (0x00000930) +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET (0x00000934) +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR (0x00000938) +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG (0x0000093c) + +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0 13 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0 0xFFFFE000 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0(v) \ + (((v) << 13) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0) +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS 0x00001000 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS(v) \ + (((v) << 12) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS__1 0x1 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN 0x00000800 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN(v) \ + (((v) << 11) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN__1 0x1 +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT 8 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT 0x00000700 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT(v) \ + (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__1 0x1 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__2 0x2 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__3 0x3 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__4 0x4 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__5 0x5 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__6 0x6 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__7 0x7 +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1 2 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1 0x000000FC +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1(v) \ + (((v) << 2) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1) +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP 0 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP 0x00000003 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__3 0x3 + +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0 (0x00000940) +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET (0x00000944) +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR (0x00000948) +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG (0x0000094c) + +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0 29 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0 0xE0000000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0(v) \ + (((v) << 29) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3 24 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3 0x1F000000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3(v) \ + (((v) << 24) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1 21 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1 0x00E00000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1(v) \ + (((v) << 21) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2 16 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2 0x001F0000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2 13 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2 0x0000E000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2(v) \ + (((v) << 13) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1 8 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1 0x00001F00 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1(v) \ + (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3 5 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3 0x000000E0 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3(v) \ + (((v) << 5) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0 0 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0 0x0000001F +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0) + +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1 (0x00000950) +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET (0x00000954) +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR (0x00000958) +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG (0x0000095c) + +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0 29 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0 0xE0000000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0(v) \ + (((v) << 29) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3 24 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3 0x1F000000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3(v) \ + (((v) << 24) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1 21 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1 0x00E00000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1(v) \ + (((v) << 21) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2 16 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2 0x001F0000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2 13 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2 0x0000E000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2(v) \ + (((v) << 13) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1 8 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1 0x00001F00 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1(v) \ + (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3 5 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3 0x000000E0 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3(v) \ + (((v) << 5) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0 0 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0 0x0000001F +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0) + +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0 (0x00000960) +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET (0x00000964) +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR (0x00000968) +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG (0x0000096c) + +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0 16 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3 12 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3 0x0000F000 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3(v) \ + (((v) << 12) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2 8 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2 0x00000F00 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2(v) \ + (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1 4 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1 0x000000F0 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1(v) \ + (((v) << 4) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0 0 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0 0x0000000F +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0) + +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1 (0x00000970) +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET (0x00000974) +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR (0x00000978) +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG (0x0000097c) + +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0 16 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3 12 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3 0x0000F000 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3(v) \ + (((v) << 12) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2 8 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2 0x00000F00 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2(v) \ + (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1 4 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1 0x000000F0 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1(v) \ + (((v) << 4) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0 0 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0 0x0000000F +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0) + +#define HW_PXP_DITHER_FETCH_ADDR_0_CH0 (0x00000980) + +#define BP_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0 0 +#define BM_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0(v) (v) + +#define HW_PXP_DITHER_FETCH_ADDR_1_CH0 (0x00000990) + +#define BP_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1 0 +#define BM_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1(v) (v) + +#define HW_PXP_DITHER_FETCH_ADDR_0_CH1 (0x000009a0) + +#define BP_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0 0 +#define BM_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0(v) (v) + +#define HW_PXP_DITHER_FETCH_ADDR_1_CH1 (0x000009b0) + +#define BP_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1 0 +#define BM_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1(v) (v) + +#define HW_PXP_DITHER_STORE_CTRL_CH0 (0x000009c0) +#define HW_PXP_DITHER_STORE_CTRL_CH0_SET (0x000009c4) +#define HW_PXP_DITHER_STORE_CTRL_CH0_CLR (0x000009c8) +#define HW_PXP_DITHER_STORE_CTRL_CH0_TOG (0x000009cc) + +#define BM_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN 0x80000000 +#define BF_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN(v) \ + (((v) << 31) & BM_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN__1 0x1 +#define BP_PXP_DITHER_STORE_CTRL_CH0_RSVD0 25 +#define BM_PXP_DITHER_STORE_CTRL_CH0_RSVD0 0x7E000000 +#define BF_PXP_DITHER_STORE_CTRL_CH0_RSVD0(v) \ + (((v) << 25) & BM_PXP_DITHER_STORE_CTRL_CH0_RSVD0) +#define BM_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL 0x01000000 +#define BF_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL) +#define BV_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL__1 0x1 +#define BP_PXP_DITHER_STORE_CTRL_CH0_RSVD1 18 +#define BM_PXP_DITHER_STORE_CTRL_CH0_RSVD1 0x00FC0000 +#define BF_PXP_DITHER_STORE_CTRL_CH0_RSVD1(v) \ + (((v) << 18) & BM_PXP_DITHER_STORE_CTRL_CH0_RSVD1) +#define BP_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES 16 +#define BM_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES 0x00030000 +#define BF_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES) +#define BV_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_DITHER_STORE_CTRL_CH0_RSVD2 12 +#define BM_PXP_DITHER_STORE_CTRL_CH0_RSVD2 0x0000F000 +#define BF_PXP_DITHER_STORE_CTRL_CH0_RSVD2(v) \ + (((v) << 12) & BM_PXP_DITHER_STORE_CTRL_CH0_RSVD2) +#define BM_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN 0x00000800 +#define BF_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN(v) \ + (((v) << 11) & BM_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL 0x00000400 +#define BF_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL) +#define BV_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_RSVD3 0x00000080 +#define BF_PXP_DITHER_STORE_CTRL_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_CTRL_CH0_RSVD3) +#define BP_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM 5 +#define BM_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM) +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN 0x00000010 +#define BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN 0x00000008 +#define BF_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16 0x00000004 +#define BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16) +#define BV_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16__8x8 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16__16x16 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN 0x00000002 +#define BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_CH_EN 0x00000001 +#define BF_PXP_DITHER_STORE_CTRL_CH0_CH_EN(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_CTRL_CH0_CH_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_CH_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_CH_EN__1 0x1 + +#define HW_PXP_DITHER_STORE_CTRL_CH1 (0x000009d0) +#define HW_PXP_DITHER_STORE_CTRL_CH1_SET (0x000009d4) +#define HW_PXP_DITHER_STORE_CTRL_CH1_CLR (0x000009d8) +#define HW_PXP_DITHER_STORE_CTRL_CH1_TOG (0x000009dc) + +#define BP_PXP_DITHER_STORE_CTRL_CH1_RSVD0 18 +#define BM_PXP_DITHER_STORE_CTRL_CH1_RSVD0 0xFFFC0000 +#define BF_PXP_DITHER_STORE_CTRL_CH1_RSVD0(v) \ + (((v) << 18) & BM_PXP_DITHER_STORE_CTRL_CH1_RSVD0) +#define BP_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES 16 +#define BM_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES 0x00030000 +#define BF_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES) +#define BV_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_DITHER_STORE_CTRL_CH1_RSVD1 11 +#define BM_PXP_DITHER_STORE_CTRL_CH1_RSVD1 0x0000F800 +#define BF_PXP_DITHER_STORE_CTRL_CH1_RSVD1(v) \ + (((v) << 11) & BM_PXP_DITHER_STORE_CTRL_CH1_RSVD1) +#define BM_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL 0x00000400 +#define BF_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL) +#define BV_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_RSVD3 0x00000080 +#define BF_PXP_DITHER_STORE_CTRL_CH1_RSVD3(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_CTRL_CH1_RSVD3) +#define BP_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM 5 +#define BM_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM) +#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN 0x00000010 +#define BF_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN 0x00000008 +#define BF_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16 0x00000004 +#define BF_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16) +#define BV_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16__8x8 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16__16x16 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN 0x00000002 +#define BF_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_CH_EN 0x00000001 +#define BF_PXP_DITHER_STORE_CTRL_CH1_CH_EN(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_CTRL_CH1_CH_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH1_CH_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_CH_EN__1 0x1 + +#define HW_PXP_DITHER_STORE_STATUS_CH0 (0x000009e0) + +#define BP_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y 16 +#define BM_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y) +#define BP_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X 0 +#define BM_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X) + +#define HW_PXP_DITHER_STORE_STATUS_CH1 (0x000009f0) + +#define BP_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y 16 +#define BM_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y) +#define BP_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X 0 +#define BM_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X) + +#define HW_PXP_DITHER_STORE_SIZE_CH0 (0x00000a00) + +#define BP_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT 16 +#define BM_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT) +#define BP_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH 0 +#define BM_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH 0x0000FFFF +#define BF_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH) + +#define HW_PXP_DITHER_STORE_SIZE_CH1 (0x00000a10) + +#define BP_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT 16 +#define BM_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT) +#define BP_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH 0 +#define BM_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH 0x0000FFFF +#define BF_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH) + +#define HW_PXP_DITHER_STORE_PITCH (0x00000a20) + +#define BP_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH 16 +#define BM_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH 0xFFFF0000 +#define BF_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH) +#define BP_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH 0 +#define BM_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH 0x0000FFFF +#define BF_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH) + +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0 (0x00000a30) +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET (0x00000a34) +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR (0x00000a38) +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG (0x00000a3c) + +#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0 8 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0 0xFFFFFF00 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0) +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00000080 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD1 0x00000040 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD1(v) \ + (((v) << 6) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD1) +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2 0 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2 0x00000003 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2) + +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1 (0x00000a40) +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET (0x00000a44) +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR (0x00000a48) +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG (0x00000a4c) + +#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0 6 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0 0xFFFFFFC0 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0(v) \ + (((v) << 6) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0) +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2 0 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2 0x00000003 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2) + +#define HW_PXP_DITHER_STORE_ADDR_0_CH0 (0x00000a90) + +#define BP_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0 +#define BM_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_DITHER_STORE_ADDR_1_CH0 (0x00000aa0) + +#define BP_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0 +#define BM_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_DITHER_STORE_FILL_DATA_CH0 (0x00000ab0) + +#define BP_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0 +#define BM_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_ADDR_0_CH1 (0x00000ac0) + +#define BP_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0 +#define BM_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_DITHER_STORE_ADDR_1_CH1 (0x00000ad0) + +#define BP_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0 +#define BM_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK0_H_CH0 (0x00000ae0) + +#define BP_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK0_L_CH0 (0x00000af0) + +#define BP_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK1_H_CH0 (0x00000b00) + +#define BP_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK1_L_CH0 (0x00000b10) + +#define BP_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK2_H_CH0 (0x00000b20) + +#define BP_PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK2_L_CH0 (0x00000b30) + +#define BP_PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK3_H_CH0 (0x00000b40) + +#define BP_PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK3_L_CH0 (0x00000b50) + +#define BP_PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK4_H_CH0 (0x00000b60) + +#define BP_PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK4_L_CH0 (0x00000b70) + +#define BP_PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK5_H_CH0 (0x00000b80) + +#define BP_PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK5_L_CH0 (0x00000b90) + +#define BP_PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK6_H_CH0 (0x00000ba0) + +#define BP_PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK6_L_CH0 (0x00000bb0) + +#define BP_PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK7_H_CH0 (0x00000bc0) + +#define BP_PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK7_L_CH0 (0x00000bd0) + +#define BP_PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_SHIFT_L_CH0 (0x00000be0) + +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3 0x80000000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(v) \ + (((v) << 31) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD0 0x40000000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD0) +#define BP_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 24 +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2 0x00800000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(v) \ + (((v) << 23) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD1 0x00400000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD1) +#define BP_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 16 +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1 0x00008000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(v) \ + (((v) << 15) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD2 0x00004000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD2) +#define BP_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 8 +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0 0x00000080 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD3 0x00000040 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD3) +#define BP_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0 +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0) + +#define HW_PXP_DITHER_STORE_D_SHIFT_H_CH0 (0x00000bf0) + +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7 0x80000000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(v) \ + (((v) << 31) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD0 0x40000000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD0) +#define BP_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 24 +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6 0x00800000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(v) \ + (((v) << 23) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD1 0x00400000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD1) +#define BP_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 16 +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5 0x00008000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(v) \ + (((v) << 15) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD2 0x00004000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD2) +#define BP_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 8 +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4 0x00000080 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD3 0x00000040 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD3) +#define BP_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0 +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4) + +#define HW_PXP_DITHER_STORE_F_SHIFT_L_CH0 (0x00000c00) + +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD0 0x80000000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD0) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3 0x40000000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(v) \ + (((v) << 30) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3) +#define BP_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 24 +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD1 0x00800000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD1) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2 0x00400000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(v) \ + (((v) << 22) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2) +#define BP_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 16 +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD2 0x00008000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD2) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1 0x00004000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(v) \ + (((v) << 14) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1) +#define BP_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 8 +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD3 0x00000080 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD3) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0 0x00000040 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(v) \ + (((v) << 6) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0) +#define BP_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0 +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0) + +#define HW_PXP_DITHER_STORE_F_SHIFT_H_CH0 (0x00000c10) + +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD0 0x80000000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD0) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7 0x40000000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(v) \ + (((v) << 30) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7) +#define BP_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 24 +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD1 0x00800000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD1) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6 0x00400000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(v) \ + (((v) << 22) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6) +#define BP_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 16 +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD2 0x00008000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD2) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5 0x00004000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(v) \ + (((v) << 14) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5) +#define BP_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 8 +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD3 0x00000080 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD3) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4 0x00000040 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(v) \ + (((v) << 6) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4) +#define BP_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0 +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4) + +#define HW_PXP_DITHER_STORE_F_MASK_L_CH0 (0x00000c20) + +#define BP_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3 24 +#define BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3 0xFF000000 +#define BF_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3) +#define BP_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2 16 +#define BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2 0x00FF0000 +#define BF_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2) +#define BP_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1 8 +#define BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1 0x0000FF00 +#define BF_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1) +#define BP_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0 0 +#define BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0 0x000000FF +#define BF_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0) + +#define HW_PXP_DITHER_STORE_F_MASK_H_CH0 (0x00000c30) + +#define BP_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7 24 +#define BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7 0xFF000000 +#define BF_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7) +#define BP_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6 16 +#define BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6 0x00FF0000 +#define BF_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6) +#define BP_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5 8 +#define BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5 0x0000FF00 +#define BF_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5) +#define BP_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4 0 +#define BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4 0x000000FF +#define BF_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4) + +#define HW_PXP_WFA_FETCH_CTRL (0x00000c40) +#define HW_PXP_WFA_FETCH_CTRL_SET (0x00000c44) +#define HW_PXP_WFA_FETCH_CTRL_CLR (0x00000c48) +#define HW_PXP_WFA_FETCH_CTRL_TOG (0x00000c4c) + +#define BM_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ_EN 0x80000000 +#define BF_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ_EN(v) \ + (((v) << 31) & BM_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ_EN) +#define BM_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ_EN 0x40000000 +#define BF_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ_EN(v) \ + (((v) << 30) & BM_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ_EN) +#define BM_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ 0x20000000 +#define BF_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ(v) \ + (((v) << 29) & BM_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ) +#define BM_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ 0x10000000 +#define BF_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ(v) \ + (((v) << 28) & BM_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ) +#define BP_PXP_WFA_FETCH_CTRL_RSVD0 24 +#define BM_PXP_WFA_FETCH_CTRL_RSVD0 0x0F000000 +#define BF_PXP_WFA_FETCH_CTRL_RSVD0(v) \ + (((v) << 24) & BM_PXP_WFA_FETCH_CTRL_RSVD0) +#define BP_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE 22 +#define BM_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE 0x00C00000 +#define BF_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE(v) \ + (((v) << 22) & BM_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE__1 0x1 +#define BV_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE__2 0x2 +#define BV_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE__3 0x3 +#define BP_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP 20 +#define BM_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP 0x00300000 +#define BF_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP(v) \ + (((v) << 20) & BM_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP) +#define BP_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE 18 +#define BM_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE 0x000C0000 +#define BF_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE(v) \ + (((v) << 18) & BM_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE__1 0x1 +#define BV_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE__2 0x2 +#define BV_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE__3 0x3 +#define BP_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP 16 +#define BM_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP 0x00030000 +#define BF_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP) +#define BP_PXP_WFA_FETCH_CTRL_RSVD1 14 +#define BM_PXP_WFA_FETCH_CTRL_RSVD1 0x0000C000 +#define BF_PXP_WFA_FETCH_CTRL_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFA_FETCH_CTRL_RSVD1) +#define BM_PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE 0x00002000 +#define BF_PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE(v) \ + (((v) << 13) & BM_PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN 0x00001000 +#define BF_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN(v) \ + (((v) << 12) & BM_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN) +#define BV_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE 0x00000800 +#define BF_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE(v) \ + (((v) << 11) & BM_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE 0x00000400 +#define BF_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE(v) \ + (((v) << 10) & BM_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF 0x00000200 +#define BF_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF(v) \ + (((v) << 9) & BM_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF) +#define BV_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF2_EN 0x00000100 +#define BF_PXP_WFA_FETCH_CTRL_BF2_EN(v) \ + (((v) << 8) & BM_PXP_WFA_FETCH_CTRL_BF2_EN) +#define BV_PXP_WFA_FETCH_CTRL_BF2_EN__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_EN__1 0x1 +#define BP_PXP_WFA_FETCH_CTRL_RSVD2 6 +#define BM_PXP_WFA_FETCH_CTRL_RSVD2 0x000000C0 +#define BF_PXP_WFA_FETCH_CTRL_RSVD2(v) \ + (((v) << 6) & BM_PXP_WFA_FETCH_CTRL_RSVD2) +#define BM_PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE 0x00000020 +#define BF_PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE(v) \ + (((v) << 5) & BM_PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN 0x00000010 +#define BF_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN(v) \ + (((v) << 4) & BM_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN) +#define BV_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE 0x00000008 +#define BF_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE(v) \ + (((v) << 3) & BM_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE 0x00000004 +#define BF_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE(v) \ + (((v) << 2) & BM_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF 0x00000002 +#define BF_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF(v) \ + (((v) << 1) & BM_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF) +#define BV_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF1_EN 0x00000001 +#define BF_PXP_WFA_FETCH_CTRL_BF1_EN(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_CTRL_BF1_EN) +#define BV_PXP_WFA_FETCH_CTRL_BF1_EN__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_EN__1 0x1 + +#define HW_PXP_WFA_FETCH_BUF1_ADDR (0x00000c50) + +#define BP_PXP_WFA_FETCH_BUF1_ADDR_BUF_ADDR 0 +#define BM_PXP_WFA_FETCH_BUF1_ADDR_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_WFA_FETCH_BUF1_ADDR_BUF_ADDR(v) (v) + +#define HW_PXP_WFA_FETCH_BUF1_PITCH (0x00000c60) + +#define BP_PXP_WFA_FETCH_BUF1_PITCH_RSVD 16 +#define BM_PXP_WFA_FETCH_BUF1_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_WFA_FETCH_BUF1_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_BUF1_PITCH_RSVD) +#define BP_PXP_WFA_FETCH_BUF1_PITCH_PITCH 0 +#define BM_PXP_WFA_FETCH_BUF1_PITCH_PITCH 0x0000FFFF +#define BF_PXP_WFA_FETCH_BUF1_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_BUF1_PITCH_PITCH) + +#define HW_PXP_WFA_FETCH_BUF1_SIZE (0x00000c70) + +#define BP_PXP_WFA_FETCH_BUF1_SIZE_RSVD0 30 +#define BM_PXP_WFA_FETCH_BUF1_SIZE_RSVD0 0xC0000000 +#define BF_PXP_WFA_FETCH_BUF1_SIZE_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_FETCH_BUF1_SIZE_RSVD0) +#define BP_PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT 16 +#define BM_PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT 0x3FFF0000 +#define BF_PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT) +#define BP_PXP_WFA_FETCH_BUF1_SIZE_RSVD1 14 +#define BM_PXP_WFA_FETCH_BUF1_SIZE_RSVD1 0x0000C000 +#define BF_PXP_WFA_FETCH_BUF1_SIZE_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFA_FETCH_BUF1_SIZE_RSVD1) +#define BP_PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH 0 +#define BM_PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH 0x00003FFF +#define BF_PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH) + +#define HW_PXP_WFA_FETCH_BUF2_ADDR (0x00000c80) + +#define BP_PXP_WFA_FETCH_BUF2_ADDR_BUF_ADDR 0 +#define BM_PXP_WFA_FETCH_BUF2_ADDR_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_WFA_FETCH_BUF2_ADDR_BUF_ADDR(v) (v) + +#define HW_PXP_WFA_FETCH_BUF2_PITCH (0x00000c90) + +#define BP_PXP_WFA_FETCH_BUF2_PITCH_RSVD 16 +#define BM_PXP_WFA_FETCH_BUF2_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_WFA_FETCH_BUF2_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_BUF2_PITCH_RSVD) +#define BP_PXP_WFA_FETCH_BUF2_PITCH_PITCH 0 +#define BM_PXP_WFA_FETCH_BUF2_PITCH_PITCH 0x0000FFFF +#define BF_PXP_WFA_FETCH_BUF2_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_BUF2_PITCH_PITCH) + +#define HW_PXP_WFA_FETCH_BUF2_SIZE (0x00000ca0) + +#define BP_PXP_WFA_FETCH_BUF2_SIZE_RSVD0 30 +#define BM_PXP_WFA_FETCH_BUF2_SIZE_RSVD0 0xC0000000 +#define BF_PXP_WFA_FETCH_BUF2_SIZE_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_FETCH_BUF2_SIZE_RSVD0) +#define BP_PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT 16 +#define BM_PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT 0x3FFF0000 +#define BF_PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT) +#define BP_PXP_WFA_FETCH_BUF2_SIZE_RSVD1 14 +#define BM_PXP_WFA_FETCH_BUF2_SIZE_RSVD1 0x0000C000 +#define BF_PXP_WFA_FETCH_BUF2_SIZE_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFA_FETCH_BUF2_SIZE_RSVD1) +#define BP_PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH 0 +#define BM_PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH 0x00003FFF +#define BF_PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH) + +#define HW_PXP_WFA_ARRAY_PIXEL0_MASK (0x00000cb0) + +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL1_MASK (0x00000cc0) + +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL2_MASK (0x00000cd0) + +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL3_MASK (0x00000ce0) + +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL4_MASK (0x00000cf0) + +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL5_MASK (0x00000d00) + +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL6_MASK (0x00000d10) + +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL7_MASK (0x00000d20) + +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG0_MASK (0x00000d30) + +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG1_MASK (0x00000d40) + +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG1_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG1_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG2_MASK (0x00000d50) + +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG2_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG2_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG3_MASK (0x00000d60) + +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG3_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG3_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG4_MASK (0x00000d70) + +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG4_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG4_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG5_MASK (0x00000d80) + +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG5_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG5_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG6_MASK (0x00000d90) + +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG6_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG6_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG7_MASK (0x00000da0) + +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG7_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG7_MASK_L_OFS) + +#define HW_PXP_WFA_FETCH_BUF1_CORD (0x00000db0) + +#define BP_PXP_WFA_FETCH_BUF1_CORD_RSVD0 30 +#define BM_PXP_WFA_FETCH_BUF1_CORD_RSVD0 0xC0000000 +#define BF_PXP_WFA_FETCH_BUF1_CORD_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_FETCH_BUF1_CORD_RSVD0) +#define BP_PXP_WFA_FETCH_BUF1_CORD_YCORD 16 +#define BM_PXP_WFA_FETCH_BUF1_CORD_YCORD 0x3FFF0000 +#define BF_PXP_WFA_FETCH_BUF1_CORD_YCORD(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_BUF1_CORD_YCORD) +#define BP_PXP_WFA_FETCH_BUF1_CORD_RSVD1 14 +#define BM_PXP_WFA_FETCH_BUF1_CORD_RSVD1 0x0000C000 +#define BF_PXP_WFA_FETCH_BUF1_CORD_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFA_FETCH_BUF1_CORD_RSVD1) +#define BP_PXP_WFA_FETCH_BUF1_CORD_XCORD 0 +#define BM_PXP_WFA_FETCH_BUF1_CORD_XCORD 0x00003FFF +#define BF_PXP_WFA_FETCH_BUF1_CORD_XCORD(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_BUF1_CORD_XCORD) + +#define HW_PXP_WFA_FETCH_BUF2_CORD (0x00000dc0) + +#define BP_PXP_WFA_FETCH_BUF2_CORD_RSVD0 30 +#define BM_PXP_WFA_FETCH_BUF2_CORD_RSVD0 0xC0000000 +#define BF_PXP_WFA_FETCH_BUF2_CORD_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_FETCH_BUF2_CORD_RSVD0) +#define BP_PXP_WFA_FETCH_BUF2_CORD_YCORD 16 +#define BM_PXP_WFA_FETCH_BUF2_CORD_YCORD 0x3FFF0000 +#define BF_PXP_WFA_FETCH_BUF2_CORD_YCORD(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_BUF2_CORD_YCORD) +#define BP_PXP_WFA_FETCH_BUF2_CORD_RSVD1 14 +#define BM_PXP_WFA_FETCH_BUF2_CORD_RSVD1 0x0000C000 +#define BF_PXP_WFA_FETCH_BUF2_CORD_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFA_FETCH_BUF2_CORD_RSVD1) +#define BP_PXP_WFA_FETCH_BUF2_CORD_XCORD 0 +#define BM_PXP_WFA_FETCH_BUF2_CORD_XCORD 0x00003FFF +#define BF_PXP_WFA_FETCH_BUF2_CORD_XCORD(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_BUF2_CORD_XCORD) + +#define HW_PXP_WFA_ARRAY_FLAG8_MASK (0x00000dd0) + +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG8_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG8_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG9_MASK (0x00000de0) + +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG9_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG9_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG10_MASK (0x00000df0) + +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG10_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG10_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG11_MASK (0x00000e00) + +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG11_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG11_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG12_MASK (0x00000e10) + +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG12_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG12_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG13_MASK (0x00000e20) + +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG13_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG13_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG14_MASK (0x00000e30) + +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG14_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG14_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG15_MASK (0x00000e40) + +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG15_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG15_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_REG0 (0x00000e50) + +#define BP_PXP_WFA_ARRAY_REG0_SW_PIXLE3 24 +#define BM_PXP_WFA_ARRAY_REG0_SW_PIXLE3 0xFF000000 +#define BF_PXP_WFA_ARRAY_REG0_SW_PIXLE3(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_REG0_SW_PIXLE3) +#define BP_PXP_WFA_ARRAY_REG0_SW_PIXLE2 16 +#define BM_PXP_WFA_ARRAY_REG0_SW_PIXLE2 0x00FF0000 +#define BF_PXP_WFA_ARRAY_REG0_SW_PIXLE2(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_REG0_SW_PIXLE2) +#define BP_PXP_WFA_ARRAY_REG0_SW_PIXLE1 8 +#define BM_PXP_WFA_ARRAY_REG0_SW_PIXLE1 0x0000FF00 +#define BF_PXP_WFA_ARRAY_REG0_SW_PIXLE1(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_REG0_SW_PIXLE1) +#define BP_PXP_WFA_ARRAY_REG0_SW_PIXLE0 0 +#define BM_PXP_WFA_ARRAY_REG0_SW_PIXLE0 0x000000FF +#define BF_PXP_WFA_ARRAY_REG0_SW_PIXLE0(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_REG0_SW_PIXLE0) + +#define HW_PXP_WFA_ARRAY_REG1 (0x00000e60) + +#define BP_PXP_WFA_ARRAY_REG1_SW_PIXLE7 24 +#define BM_PXP_WFA_ARRAY_REG1_SW_PIXLE7 0xFF000000 +#define BF_PXP_WFA_ARRAY_REG1_SW_PIXLE7(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_REG1_SW_PIXLE7) +#define BP_PXP_WFA_ARRAY_REG1_SW_PIXLE6 16 +#define BM_PXP_WFA_ARRAY_REG1_SW_PIXLE6 0x00FF0000 +#define BF_PXP_WFA_ARRAY_REG1_SW_PIXLE6(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_REG1_SW_PIXLE6) +#define BP_PXP_WFA_ARRAY_REG1_SW_PIXLE5 8 +#define BM_PXP_WFA_ARRAY_REG1_SW_PIXLE5 0x0000FF00 +#define BF_PXP_WFA_ARRAY_REG1_SW_PIXLE5(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_REG1_SW_PIXLE5) +#define BP_PXP_WFA_ARRAY_REG1_SW_PIXLE4 0 +#define BM_PXP_WFA_ARRAY_REG1_SW_PIXLE4 0x000000FF +#define BF_PXP_WFA_ARRAY_REG1_SW_PIXLE4(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_REG1_SW_PIXLE4) + +#define HW_PXP_WFA_ARRAY_REG2 (0x00000e70) + +#define BP_PXP_WFA_ARRAY_REG2_RSVD0 16 +#define BM_PXP_WFA_ARRAY_REG2_RSVD0 0xFFFF0000 +#define BF_PXP_WFA_ARRAY_REG2_RSVD0(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_REG2_RSVD0) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG15 0x00008000 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG15(v) \ + (((v) << 15) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG15) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG14 0x00004000 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG14(v) \ + (((v) << 14) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG14) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG13 0x00002000 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG13(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG13) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG12 0x00001000 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG12(v) \ + (((v) << 12) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG12) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG11 0x00000800 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG11(v) \ + (((v) << 11) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG11) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG10 0x00000400 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG10(v) \ + (((v) << 10) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG10) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG9 0x00000200 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG9(v) \ + (((v) << 9) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG9) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG8 0x00000100 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG8(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG8) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG7 0x00000080 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG7(v) \ + (((v) << 7) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG7) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG6 0x00000040 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG6(v) \ + (((v) << 6) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG6) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG5 0x00000020 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG5) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG4 0x00000010 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG4(v) \ + (((v) << 4) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG4) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG3 0x00000008 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG3(v) \ + (((v) << 3) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG3) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG2 0x00000004 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG2(v) \ + (((v) << 2) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG2) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG1 0x00000002 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG1(v) \ + (((v) << 1) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG1) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG0 0x00000001 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG0(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG0) + +#define HW_PXP_WFE_A_STORE_CTRL_CH0 (0x00000e80) +#define HW_PXP_WFE_A_STORE_CTRL_CH0_SET (0x00000e84) +#define HW_PXP_WFE_A_STORE_CTRL_CH0_CLR (0x00000e88) +#define HW_PXP_WFE_A_STORE_CTRL_CH0_TOG (0x00000e8c) + +#define BM_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN 0x80000000 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN(v) \ + (((v) << 31) & BM_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN__1 0x1 +#define BP_PXP_WFE_A_STORE_CTRL_CH0_RSVD0 25 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD0 0x7E000000 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_RSVD0(v) \ + (((v) << 25) & BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD0) +#define BM_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL 0x01000000 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL__1 0x1 +#define BP_PXP_WFE_A_STORE_CTRL_CH0_RSVD1 18 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD1 0x00FC0000 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_RSVD1(v) \ + (((v) << 18) & BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD1) +#define BP_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES 16 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES 0x00030000 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_WFE_A_STORE_CTRL_CH0_RSVD2 12 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD2 0x0000F000 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_RSVD2(v) \ + (((v) << 12) & BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD2) +#define BM_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN 0x00000800 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN(v) \ + (((v) << 11) & BM_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL 0x00000400 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD3 0x00000080 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD3) +#define BP_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM 5 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN 0x00000010 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN 0x00000008 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16 0x00000004 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16__8x8 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16__16x16 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN 0x00000002 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_CH_EN 0x00000001 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_CH_EN(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_CTRL_CH0_CH_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_CH_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_CH_EN__1 0x1 + +#define HW_PXP_WFE_A_STORE_CTRL_CH1 (0x00000e90) +#define HW_PXP_WFE_A_STORE_CTRL_CH1_SET (0x00000e94) +#define HW_PXP_WFE_A_STORE_CTRL_CH1_CLR (0x00000e98) +#define HW_PXP_WFE_A_STORE_CTRL_CH1_TOG (0x00000e9c) + +#define BP_PXP_WFE_A_STORE_CTRL_CH1_RSVD0 18 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD0 0xFFFC0000 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_RSVD0(v) \ + (((v) << 18) & BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD0) +#define BP_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES 16 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES 0x00030000 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_WFE_A_STORE_CTRL_CH1_RSVD1 11 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD1 0x0000F800 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_RSVD1(v) \ + (((v) << 11) & BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD1) +#define BM_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL 0x00000400 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD3 0x00000080 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD3) +#define BP_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM 5 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN 0x00000010 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN 0x00000008 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16 0x00000004 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16__8x8 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16__16x16 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN 0x00000002 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_CH_EN 0x00000001 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_CTRL_CH1_CH_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_CH_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_CH_EN__1 0x1 + +#define HW_PXP_WFE_A_STORE_STATUS_CH0 (0x00000ea0) + +#define BP_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_Y 16 +#define BM_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_Y) +#define BP_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_X 0 +#define BM_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_X) + +#define HW_PXP_WFE_A_STORE_STATUS_CH1 (0x00000eb0) + +#define BP_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_Y 16 +#define BM_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_Y) +#define BP_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_X 0 +#define BM_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_X) + +#define HW_PXP_WFE_A_STORE_SIZE_CH0 (0x00000ec0) + +#define BP_PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT 16 +#define BM_PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT) +#define BP_PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH 0 +#define BM_PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH 0x0000FFFF +#define BF_PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH) + +#define HW_PXP_WFE_A_STORE_SIZE_CH1 (0x00000ed0) + +#define BP_PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT 16 +#define BM_PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT) +#define BP_PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH 0 +#define BM_PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH 0x0000FFFF +#define BF_PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH) + +#define HW_PXP_WFE_A_STORE_PITCH (0x00000ee0) + +#define BP_PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH 16 +#define BM_PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH 0xFFFF0000 +#define BF_PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH) +#define BP_PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH 0 +#define BM_PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH 0x0000FFFF +#define BF_PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH) + +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH0 (0x00000ef0) +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET (0x00000ef4) +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR (0x00000ef8) +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG (0x00000efc) + +#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD0 8 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD0 0xFFFFFF00 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD0(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD0) +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00000080 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD1 0x00000040 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD1(v) \ + (((v) << 6) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD1) +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD2 0 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD2 0x00000003 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD2(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD2) + +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH1 (0x00000f00) +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET (0x00000f04) +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR (0x00000f08) +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG (0x00000f0c) + +#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD0 6 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD0 0xFFFFFFC0 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD0(v) \ + (((v) << 6) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD0) +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD2 0 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD2 0x00000003 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD2(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD2) + +#define HW_PXP_WFE_A_STORE_ADDR_0_CH0 (0x00000f50) + +#define BP_PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0 +#define BM_PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_WFE_A_STORE_ADDR_1_CH0 (0x00000f60) + +#define BP_PXP_WFE_A_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0 +#define BM_PXP_WFE_A_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_WFE_A_STORE_FILL_DATA_CH0 (0x00000f70) + +#define BP_PXP_WFE_A_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0 +#define BM_PXP_WFE_A_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_FILL_DATA_CH0_FILL_DATA_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_ADDR_0_CH1 (0x00000f80) + +#define BP_PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0 +#define BM_PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_WFE_A_STORE_ADDR_1_CH1 (0x00000f90) + +#define BP_PXP_WFE_A_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0 +#define BM_PXP_WFE_A_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK0_H_CH0 (0x00000fa0) + +#define BP_PXP_WFE_A_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK0_L_CH0 (0x00000fb0) + +#define BP_PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK1_H_CH0 (0x00000fc0) + +#define BP_PXP_WFE_A_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK1_L_CH0 (0x00000fd0) + +#define BP_PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK2_H_CH0 (0x00000fe0) + +#define BP_PXP_WFE_A_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK2_L_CH0 (0x00000ff0) + +#define BP_PXP_WFE_A_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK3_H_CH0 (0x00001000) + +#define BP_PXP_WFE_A_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK3_L_CH0 (0x00001010) + +#define BP_PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK4_H_CH0 (0x00001020) + +#define BP_PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK4_L_CH0 (0x00001030) + +#define BP_PXP_WFE_A_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK5_H_CH0 (0x00001040) + +#define BP_PXP_WFE_A_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK5_L_CH0 (0x00001050) + +#define BP_PXP_WFE_A_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK6_H_CH0 (0x00001060) + +#define BP_PXP_WFE_A_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK6_L_CH0 (0x00001070) + +#define BP_PXP_WFE_A_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK7_H_CH0 (0x00001080) + +#define BP_PXP_WFE_A_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK7_L_CH0 (0x00001090) + +#define BP_PXP_WFE_A_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_SHIFT_L_CH0 (0x000010a0) + +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3 0x80000000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(v) \ + (((v) << 31) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD0 0x40000000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD0) +#define BP_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 24 +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2 0x00800000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(v) \ + (((v) << 23) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD1 0x00400000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD1) +#define BP_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 16 +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1 0x00008000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(v) \ + (((v) << 15) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD2 0x00004000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD2) +#define BP_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 8 +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0 0x00000080 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD3 0x00000040 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD3) +#define BP_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0 +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0) + +#define HW_PXP_WFE_A_STORE_D_SHIFT_H_CH0 (0x000010b0) + +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7 0x80000000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(v) \ + (((v) << 31) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD0 0x40000000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD0) +#define BP_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 24 +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6 0x00800000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(v) \ + (((v) << 23) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD1 0x00400000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD1) +#define BP_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 16 +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5 0x00008000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(v) \ + (((v) << 15) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD2 0x00004000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD2) +#define BP_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 8 +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4 0x00000080 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD3 0x00000040 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD3) +#define BP_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0 +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4) + +#define HW_PXP_WFE_A_STORE_F_SHIFT_L_CH0 (0x000010c0) + +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD0 0x80000000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD0) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3 0x40000000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(v) \ + (((v) << 30) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3) +#define BP_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 24 +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD1 0x00800000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD1) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2 0x00400000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(v) \ + (((v) << 22) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2) +#define BP_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 16 +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD2 0x00008000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD2) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1 0x00004000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(v) \ + (((v) << 14) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1) +#define BP_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 8 +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD3 0x00000080 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD3) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0 0x00000040 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(v) \ + (((v) << 6) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0) +#define BP_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0 +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0) + +#define HW_PXP_WFE_A_STORE_F_SHIFT_H_CH0 (0x000010d0) + +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD0 0x80000000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD0) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7 0x40000000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(v) \ + (((v) << 30) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7) +#define BP_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 24 +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD1 0x00800000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD1) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6 0x00400000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(v) \ + (((v) << 22) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6) +#define BP_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 16 +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD2 0x00008000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD2) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5 0x00004000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(v) \ + (((v) << 14) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5) +#define BP_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 8 +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD3 0x00000080 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD3) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4 0x00000040 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(v) \ + (((v) << 6) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4) +#define BP_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0 +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4) + +#define HW_PXP_WFE_A_STORE_F_MASK_L_CH0 (0x000010e0) + +#define BP_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3 24 +#define BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3 0xFF000000 +#define BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3) +#define BP_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2 16 +#define BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2 0x00FF0000 +#define BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2) +#define BP_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1 8 +#define BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1 0x0000FF00 +#define BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1) +#define BP_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0 0 +#define BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0 0x000000FF +#define BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0) + +#define HW_PXP_WFE_A_STORE_F_MASK_H_CH0 (0x000010f0) + +#define BP_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7 24 +#define BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7 0xFF000000 +#define BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7) +#define BP_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6 16 +#define BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6 0x00FF0000 +#define BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6) +#define BP_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5 8 +#define BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5 0x0000FF00 +#define BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5) +#define BP_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4 0 +#define BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4 0x000000FF +#define BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4) + +#define HW_PXP_WFB_FETCH_CTRL (0x00001100) +#define HW_PXP_WFB_FETCH_CTRL_SET (0x00001104) +#define HW_PXP_WFB_FETCH_CTRL_CLR (0x00001108) +#define HW_PXP_WFB_FETCH_CTRL_TOG (0x0000110c) + +#define BM_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN 0x80000000 +#define BF_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN(v) \ + (((v) << 31) & BM_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN) +#define BM_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN 0x40000000 +#define BF_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN(v) \ + (((v) << 30) & BM_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN) +#define BM_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ 0x20000000 +#define BF_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ(v) \ + (((v) << 29) & BM_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ) +#define BM_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ 0x10000000 +#define BF_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ(v) \ + (((v) << 28) & BM_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ) +#define BP_PXP_WFB_FETCH_CTRL_RSVD0 24 +#define BM_PXP_WFB_FETCH_CTRL_RSVD0 0x0F000000 +#define BF_PXP_WFB_FETCH_CTRL_RSVD0(v) \ + (((v) << 24) & BM_PXP_WFB_FETCH_CTRL_RSVD0) +#define BP_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE 22 +#define BM_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE 0x00C00000 +#define BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(v) \ + (((v) << 22) & BM_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE__1 0x1 +#define BV_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE__2 0x2 +#define BV_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE__3 0x3 +#define BP_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP 20 +#define BM_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP 0x00300000 +#define BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(v) \ + (((v) << 20) & BM_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP) +#define BP_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE 18 +#define BM_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE 0x000C0000 +#define BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(v) \ + (((v) << 18) & BM_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE__1 0x1 +#define BV_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE__2 0x2 +#define BV_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE__3 0x3 +#define BP_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP 16 +#define BM_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP 0x00030000 +#define BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP) +#define BP_PXP_WFB_FETCH_CTRL_RSVD1 14 +#define BM_PXP_WFB_FETCH_CTRL_RSVD1 0x0000C000 +#define BF_PXP_WFB_FETCH_CTRL_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFB_FETCH_CTRL_RSVD1) +#define BM_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE 0x00002000 +#define BF_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(v) \ + (((v) << 13) & BM_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN 0x00001000 +#define BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(v) \ + (((v) << 12) & BM_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN) +#define BV_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE 0x00000800 +#define BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(v) \ + (((v) << 11) & BM_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE 0x00000400 +#define BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(v) \ + (((v) << 10) & BM_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF 0x00000200 +#define BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(v) \ + (((v) << 9) & BM_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF) +#define BV_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF2_EN 0x00000100 +#define BF_PXP_WFB_FETCH_CTRL_BF2_EN(v) \ + (((v) << 8) & BM_PXP_WFB_FETCH_CTRL_BF2_EN) +#define BV_PXP_WFB_FETCH_CTRL_BF2_EN__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_EN__1 0x1 +#define BP_PXP_WFB_FETCH_CTRL_RSVD2 6 +#define BM_PXP_WFB_FETCH_CTRL_RSVD2 0x000000C0 +#define BF_PXP_WFB_FETCH_CTRL_RSVD2(v) \ + (((v) << 6) & BM_PXP_WFB_FETCH_CTRL_RSVD2) +#define BM_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE 0x00000020 +#define BF_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(v) \ + (((v) << 5) & BM_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN 0x00000010 +#define BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(v) \ + (((v) << 4) & BM_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN) +#define BV_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE 0x00000008 +#define BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(v) \ + (((v) << 3) & BM_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE 0x00000004 +#define BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(v) \ + (((v) << 2) & BM_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF 0x00000002 +#define BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(v) \ + (((v) << 1) & BM_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF) +#define BV_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF1_EN 0x00000001 +#define BF_PXP_WFB_FETCH_CTRL_BF1_EN(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_CTRL_BF1_EN) +#define BV_PXP_WFB_FETCH_CTRL_BF1_EN__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_EN__1 0x1 + +#define HW_PXP_WFB_FETCH_BUF1_ADDR (0x00001110) + +#define BP_PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR 0 +#define BM_PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR(v) (v) + +#define HW_PXP_WFB_FETCH_BUF1_PITCH (0x00001120) + +#define BP_PXP_WFB_FETCH_BUF1_PITCH_RSVD 16 +#define BM_PXP_WFB_FETCH_BUF1_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_WFB_FETCH_BUF1_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_BUF1_PITCH_RSVD) +#define BP_PXP_WFB_FETCH_BUF1_PITCH_PITCH 0 +#define BM_PXP_WFB_FETCH_BUF1_PITCH_PITCH 0x0000FFFF +#define BF_PXP_WFB_FETCH_BUF1_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_BUF1_PITCH_PITCH) + +#define HW_PXP_WFB_FETCH_BUF1_SIZE (0x00001130) + +#define BP_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT 16 +#define BM_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT 0xFFFF0000 +#define BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT) +#define BP_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH 0 +#define BM_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH 0x0000FFFF +#define BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH) + +#define HW_PXP_WFB_FETCH_BUF2_ADDR (0x00001140) + +#define BP_PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR 0 +#define BM_PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR(v) (v) + +#define HW_PXP_WFB_FETCH_BUF2_PITCH (0x00001150) + +#define BP_PXP_WFB_FETCH_BUF2_PITCH_RSVD 16 +#define BM_PXP_WFB_FETCH_BUF2_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_WFB_FETCH_BUF2_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_BUF2_PITCH_RSVD) +#define BP_PXP_WFB_FETCH_BUF2_PITCH_PITCH 0 +#define BM_PXP_WFB_FETCH_BUF2_PITCH_PITCH 0x0000FFFF +#define BF_PXP_WFB_FETCH_BUF2_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_BUF2_PITCH_PITCH) + +#define HW_PXP_WFB_FETCH_BUF2_SIZE (0x00001160) + +#define BP_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT 16 +#define BM_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT 0xFFFF0000 +#define BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT) +#define BP_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH 0 +#define BM_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH 0x0000FFFF +#define BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH) + +#define HW_PXP_WFB_ARRAY_PIXEL0_MASK (0x00001170) + +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL1_MASK (0x00001180) + +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL2_MASK (0x00001190) + +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL3_MASK (0x000011a0) + +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL4_MASK (0x000011b0) + +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL5_MASK (0x000011c0) + +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL6_MASK (0x000011d0) + +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL7_MASK (0x000011e0) + +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG0_MASK (0x000011f0) + +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG1_MASK (0x00001200) + +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG1_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG1_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG2_MASK (0x00001210) + +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG2_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG2_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG3_MASK (0x00001220) + +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG3_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG3_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG4_MASK (0x00001230) + +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG4_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG4_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG5_MASK (0x00001240) + +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG5_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG5_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG6_MASK (0x00001250) + +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG6_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG6_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG7_MASK (0x00001260) + +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG7_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG7_MASK_L_OFS) + +#define HW_PXP_WFB_FETCH_BUF1_CORD (0x00001270) + +#define BP_PXP_WFB_FETCH_BUF1_CORD_RSVD0 30 +#define BM_PXP_WFB_FETCH_BUF1_CORD_RSVD0 0xC0000000 +#define BF_PXP_WFB_FETCH_BUF1_CORD_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_FETCH_BUF1_CORD_RSVD0) +#define BP_PXP_WFB_FETCH_BUF1_CORD_YCORD 16 +#define BM_PXP_WFB_FETCH_BUF1_CORD_YCORD 0x3FFF0000 +#define BF_PXP_WFB_FETCH_BUF1_CORD_YCORD(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_BUF1_CORD_YCORD) +#define BP_PXP_WFB_FETCH_BUF1_CORD_RSVD1 14 +#define BM_PXP_WFB_FETCH_BUF1_CORD_RSVD1 0x0000C000 +#define BF_PXP_WFB_FETCH_BUF1_CORD_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFB_FETCH_BUF1_CORD_RSVD1) +#define BP_PXP_WFB_FETCH_BUF1_CORD_XCORD 0 +#define BM_PXP_WFB_FETCH_BUF1_CORD_XCORD 0x00003FFF +#define BF_PXP_WFB_FETCH_BUF1_CORD_XCORD(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_BUF1_CORD_XCORD) + +#define HW_PXP_WFB_FETCH_BUF2_CORD (0x00001280) + +#define BP_PXP_WFB_FETCH_BUF2_CORD_RSVD0 30 +#define BM_PXP_WFB_FETCH_BUF2_CORD_RSVD0 0xC0000000 +#define BF_PXP_WFB_FETCH_BUF2_CORD_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_FETCH_BUF2_CORD_RSVD0) +#define BP_PXP_WFB_FETCH_BUF2_CORD_YCORD 16 +#define BM_PXP_WFB_FETCH_BUF2_CORD_YCORD 0x3FFF0000 +#define BF_PXP_WFB_FETCH_BUF2_CORD_YCORD(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_BUF2_CORD_YCORD) +#define BP_PXP_WFB_FETCH_BUF2_CORD_RSVD1 14 +#define BM_PXP_WFB_FETCH_BUF2_CORD_RSVD1 0x0000C000 +#define BF_PXP_WFB_FETCH_BUF2_CORD_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFB_FETCH_BUF2_CORD_RSVD1) +#define BP_PXP_WFB_FETCH_BUF2_CORD_XCORD 0 +#define BM_PXP_WFB_FETCH_BUF2_CORD_XCORD 0x00003FFF +#define BF_PXP_WFB_FETCH_BUF2_CORD_XCORD(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_BUF2_CORD_XCORD) + +#define HW_PXP_WFB_ARRAY_FLAG8_MASK (0x00001290) + +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG8_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG8_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG9_MASK (0x000012a0) + +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG9_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG9_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG10_MASK (0x000012b0) + +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG10_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG10_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG11_MASK (0x000012c0) + +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG11_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG11_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG12_MASK (0x000012d0) + +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG12_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG12_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG13_MASK (0x000012e0) + +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG13_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG13_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG14_MASK (0x000012f0) + +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG14_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG14_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG15_MASK (0x00001300) + +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG15_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG15_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_REG0 (0x00001310) + +#define BP_PXP_WFB_ARRAY_REG0_SW_PIXLE3 24 +#define BM_PXP_WFB_ARRAY_REG0_SW_PIXLE3 0xFF000000 +#define BF_PXP_WFB_ARRAY_REG0_SW_PIXLE3(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_REG0_SW_PIXLE3) +#define BP_PXP_WFB_ARRAY_REG0_SW_PIXLE2 16 +#define BM_PXP_WFB_ARRAY_REG0_SW_PIXLE2 0x00FF0000 +#define BF_PXP_WFB_ARRAY_REG0_SW_PIXLE2(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_REG0_SW_PIXLE2) +#define BP_PXP_WFB_ARRAY_REG0_SW_PIXLE1 8 +#define BM_PXP_WFB_ARRAY_REG0_SW_PIXLE1 0x0000FF00 +#define BF_PXP_WFB_ARRAY_REG0_SW_PIXLE1(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_REG0_SW_PIXLE1) +#define BP_PXP_WFB_ARRAY_REG0_SW_PIXLE0 0 +#define BM_PXP_WFB_ARRAY_REG0_SW_PIXLE0 0x000000FF +#define BF_PXP_WFB_ARRAY_REG0_SW_PIXLE0(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_REG0_SW_PIXLE0) + +#define HW_PXP_WFB_ARRAY_REG1 (0x00001320) + +#define BP_PXP_WFB_ARRAY_REG1_SW_PIXLE7 24 +#define BM_PXP_WFB_ARRAY_REG1_SW_PIXLE7 0xFF000000 +#define BF_PXP_WFB_ARRAY_REG1_SW_PIXLE7(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_REG1_SW_PIXLE7) +#define BP_PXP_WFB_ARRAY_REG1_SW_PIXLE6 16 +#define BM_PXP_WFB_ARRAY_REG1_SW_PIXLE6 0x00FF0000 +#define BF_PXP_WFB_ARRAY_REG1_SW_PIXLE6(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_REG1_SW_PIXLE6) +#define BP_PXP_WFB_ARRAY_REG1_SW_PIXLE5 8 +#define BM_PXP_WFB_ARRAY_REG1_SW_PIXLE5 0x0000FF00 +#define BF_PXP_WFB_ARRAY_REG1_SW_PIXLE5(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_REG1_SW_PIXLE5) +#define BP_PXP_WFB_ARRAY_REG1_SW_PIXLE4 0 +#define BM_PXP_WFB_ARRAY_REG1_SW_PIXLE4 0x000000FF +#define BF_PXP_WFB_ARRAY_REG1_SW_PIXLE4(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_REG1_SW_PIXLE4) + +#define HW_PXP_WFB_ARRAY_REG2 (0x00001330) + +#define BP_PXP_WFB_ARRAY_REG2_RSVD0 16 +#define BM_PXP_WFB_ARRAY_REG2_RSVD0 0xFFFF0000 +#define BF_PXP_WFB_ARRAY_REG2_RSVD0(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_REG2_RSVD0) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG15 0x00008000 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG15(v) \ + (((v) << 15) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG15) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG14 0x00004000 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG14(v) \ + (((v) << 14) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG14) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG13 0x00002000 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG13(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG13) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG12 0x00001000 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG12(v) \ + (((v) << 12) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG12) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG11 0x00000800 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG11(v) \ + (((v) << 11) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG11) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG10 0x00000400 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG10(v) \ + (((v) << 10) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG10) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG9 0x00000200 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG9(v) \ + (((v) << 9) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG9) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG8 0x00000100 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG8(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG8) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG7 0x00000080 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG7(v) \ + (((v) << 7) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG7) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG6 0x00000040 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG6(v) \ + (((v) << 6) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG6) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG5 0x00000020 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG5) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG4 0x00000010 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG4(v) \ + (((v) << 4) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG4) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG3 0x00000008 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG3(v) \ + (((v) << 3) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG3) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG2 0x00000004 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG2(v) \ + (((v) << 2) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG2) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG1 0x00000002 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG1(v) \ + (((v) << 1) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG1) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG0 0x00000001 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG0(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG0) + +#define HW_PXP_WFE_B_STORE_CTRL_CH0 (0x00001340) +#define HW_PXP_WFE_B_STORE_CTRL_CH0_SET (0x00001344) +#define HW_PXP_WFE_B_STORE_CTRL_CH0_CLR (0x00001348) +#define HW_PXP_WFE_B_STORE_CTRL_CH0_TOG (0x0000134c) + +#define BM_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN 0x80000000 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN(v) \ + (((v) << 31) & BM_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN__1 0x1 +#define BP_PXP_WFE_B_STORE_CTRL_CH0_RSVD0 25 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD0 0x7E000000 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_RSVD0(v) \ + (((v) << 25) & BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD0) +#define BM_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL 0x01000000 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL__1 0x1 +#define BP_PXP_WFE_B_STORE_CTRL_CH0_RSVD1 18 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD1 0x00FC0000 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_RSVD1(v) \ + (((v) << 18) & BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD1) +#define BP_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES 16 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES 0x00030000 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_WFE_B_STORE_CTRL_CH0_RSVD2 12 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD2 0x0000F000 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_RSVD2(v) \ + (((v) << 12) & BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD2) +#define BM_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN 0x00000800 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN(v) \ + (((v) << 11) & BM_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL 0x00000400 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD3 0x00000080 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD3) +#define BP_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM 5 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN 0x00000010 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN 0x00000008 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16 0x00000004 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16__8x8 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16__16x16 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN 0x00000002 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_CH_EN 0x00000001 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_CH_EN(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_CTRL_CH0_CH_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_CH_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_CH_EN__1 0x1 + +#define HW_PXP_WFE_B_STORE_CTRL_CH1 (0x00001350) +#define HW_PXP_WFE_B_STORE_CTRL_CH1_SET (0x00001354) +#define HW_PXP_WFE_B_STORE_CTRL_CH1_CLR (0x00001358) +#define HW_PXP_WFE_B_STORE_CTRL_CH1_TOG (0x0000135c) + +#define BP_PXP_WFE_B_STORE_CTRL_CH1_RSVD0 18 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD0 0xFFFC0000 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_RSVD0(v) \ + (((v) << 18) & BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD0) +#define BP_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES 16 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES 0x00030000 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_WFE_B_STORE_CTRL_CH1_RSVD1 11 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD1 0x0000F800 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_RSVD1(v) \ + (((v) << 11) & BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD1) +#define BM_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL 0x00000400 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD3 0x00000080 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD3) +#define BP_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM 5 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN 0x00000010 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN 0x00000008 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16 0x00000004 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16__8x8 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16__16x16 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN 0x00000002 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_CH_EN 0x00000001 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_CTRL_CH1_CH_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_CH_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_CH_EN__1 0x1 + +#define HW_PXP_WFE_B_STORE_STATUS_CH0 (0x00001360) + +#define BP_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y 16 +#define BM_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y) +#define BP_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X 0 +#define BM_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X) + +#define HW_PXP_WFE_B_STORE_STATUS_CH1 (0x00001370) + +#define BP_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y 16 +#define BM_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y) +#define BP_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X 0 +#define BM_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X) + +#define HW_PXP_WFE_B_STORE_SIZE_CH0 (0x00001380) + +#define BP_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT 16 +#define BM_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT) +#define BP_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH 0 +#define BM_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH 0x0000FFFF +#define BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH) + +#define HW_PXP_WFE_B_STORE_SIZE_CH1 (0x00001390) + +#define BP_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT 16 +#define BM_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT) +#define BP_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH 0 +#define BM_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH 0x0000FFFF +#define BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH) + +#define HW_PXP_WFE_B_STORE_PITCH (0x000013a0) + +#define BP_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH 16 +#define BM_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH 0xFFFF0000 +#define BF_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH) +#define BP_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH 0 +#define BM_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH 0x0000FFFF +#define BF_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH) + +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0 (0x000013b0) +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET (0x000013b4) +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR (0x000013b8) +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG (0x000013bc) + +#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD0 8 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD0 0xFFFFFF00 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD0(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD0) +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00000080 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD1 0x00000040 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD1(v) \ + (((v) << 6) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD1) +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD2 0 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD2 0x00000003 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD2(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD2) + +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1 (0x000013c0) +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET (0x000013c4) +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR (0x000013c8) +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG (0x000013cc) + +#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD0 6 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD0 0xFFFFFFC0 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD0(v) \ + (((v) << 6) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD0) +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD2 0 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD2 0x00000003 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD2(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD2) + +#define HW_PXP_WFE_B_STORE_ADDR_0_CH0 (0x00001410) + +#define BP_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0 +#define BM_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_WFE_B_STORE_ADDR_1_CH0 (0x00001420) + +#define BP_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0 +#define BM_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_WFE_B_STORE_FILL_DATA_CH0 (0x00001430) + +#define BP_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0 +#define BM_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_ADDR_0_CH1 (0x00001440) + +#define BP_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0 +#define BM_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_WFE_B_STORE_ADDR_1_CH1 (0x00001450) + +#define BP_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0 +#define BM_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK0_H_CH0 (0x00001460) + +#define BP_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK0_L_CH0 (0x00001470) + +#define BP_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK1_H_CH0 (0x00001480) + +#define BP_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK1_L_CH0 (0x00001490) + +#define BP_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK2_H_CH0 (0x000014a0) + +#define BP_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK2_L_CH0 (0x000014b0) + +#define BP_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK3_H_CH0 (0x000014c0) + +#define BP_PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK3_L_CH0 (0x000014d0) + +#define BP_PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK4_H_CH0 (0x000014e0) + +#define BP_PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK4_L_CH0 (0x000014f0) + +#define BP_PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK5_H_CH0 (0x00001500) + +#define BP_PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK5_L_CH0 (0x00001510) + +#define BP_PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK6_H_CH0 (0x00001520) + +#define BP_PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK6_L_CH0 (0x00001530) + +#define BP_PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK7_H_CH0 (0x00001540) + +#define BP_PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK7_L_CH0 (0x00001550) + +#define BP_PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_SHIFT_L_CH0 (0x00001560) + +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3 0x80000000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(v) \ + (((v) << 31) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD0 0x40000000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD0) +#define BP_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 24 +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2 0x00800000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(v) \ + (((v) << 23) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD1 0x00400000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD1) +#define BP_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 16 +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1 0x00008000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(v) \ + (((v) << 15) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD2 0x00004000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD2) +#define BP_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 8 +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0 0x00000080 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD3 0x00000040 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD3) +#define BP_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0 +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0) + +#define HW_PXP_WFE_B_STORE_D_SHIFT_H_CH0 (0x00001570) + +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7 0x80000000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(v) \ + (((v) << 31) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD0 0x40000000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD0) +#define BP_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 24 +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6 0x00800000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(v) \ + (((v) << 23) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD1 0x00400000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD1) +#define BP_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 16 +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5 0x00008000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(v) \ + (((v) << 15) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD2 0x00004000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD2) +#define BP_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 8 +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4 0x00000080 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD3 0x00000040 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD3) +#define BP_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0 +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4) + +#define HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0 (0x00001580) + +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD0 0x80000000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD0) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3 0x40000000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(v) \ + (((v) << 30) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3) +#define BP_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 24 +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD1 0x00800000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD1) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2 0x00400000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(v) \ + (((v) << 22) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2) +#define BP_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 16 +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD2 0x00008000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD2) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1 0x00004000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(v) \ + (((v) << 14) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1) +#define BP_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 8 +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD3 0x00000080 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD3) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0 0x00000040 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(v) \ + (((v) << 6) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0) +#define BP_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0 +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0) + +#define HW_PXP_WFE_B_STORE_F_SHIFT_H_CH0 (0x00001590) + +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD0 0x80000000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD0) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7 0x40000000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(v) \ + (((v) << 30) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7) +#define BP_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 24 +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD1 0x00800000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD1) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6 0x00400000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(v) \ + (((v) << 22) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6) +#define BP_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 16 +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD2 0x00008000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD2) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5 0x00004000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(v) \ + (((v) << 14) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5) +#define BP_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 8 +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD3 0x00000080 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD3) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4 0x00000040 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(v) \ + (((v) << 6) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4) +#define BP_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0 +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4) + +#define HW_PXP_WFE_B_STORE_F_MASK_L_CH0 (0x000015a0) + +#define BP_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3 24 +#define BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3 0xFF000000 +#define BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3) +#define BP_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2 16 +#define BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2 0x00FF0000 +#define BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2) +#define BP_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1 8 +#define BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1 0x0000FF00 +#define BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1) +#define BP_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0 0 +#define BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0 0x000000FF +#define BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0) + +#define HW_PXP_WFE_B_STORE_F_MASK_H_CH0 (0x000015b0) + +#define BP_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7 24 +#define BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7 0xFF000000 +#define BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7) +#define BP_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6 16 +#define BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6 0x00FF0000 +#define BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6) +#define BP_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5 8 +#define BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5 0x0000FF00 +#define BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5) +#define BP_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4 0 +#define BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4 0x000000FF +#define BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4) + +#define HW_PXP_FETCH_WFE_A_DEBUG (0x000015c0) + +#define BP_PXP_FETCH_WFE_A_DEBUG_RSVD 29 +#define BM_PXP_FETCH_WFE_A_DEBUG_RSVD 0xE0000000 +#define BF_PXP_FETCH_WFE_A_DEBUG_RSVD(v) \ + (((v) << 29) & BM_PXP_FETCH_WFE_A_DEBUG_RSVD) +#define BM_PXP_FETCH_WFE_A_DEBUG_BUF_SEL 0x10000000 +#define BF_PXP_FETCH_WFE_A_DEBUG_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_FETCH_WFE_A_DEBUG_BUF_SEL) +#define BV_PXP_FETCH_WFE_A_DEBUG_BUF_SEL__BF0 0x0 +#define BV_PXP_FETCH_WFE_A_DEBUG_BUF_SEL__BF1 0x1 +#define BP_PXP_FETCH_WFE_A_DEBUG_ITEM_SEL 24 +#define BM_PXP_FETCH_WFE_A_DEBUG_ITEM_SEL 0x0F000000 +#define BF_PXP_FETCH_WFE_A_DEBUG_ITEM_SEL(v) \ + (((v) << 24) & BM_PXP_FETCH_WFE_A_DEBUG_ITEM_SEL) +#define BP_PXP_FETCH_WFE_A_DEBUG_DEBUG_VALUE 0 +#define BM_PXP_FETCH_WFE_A_DEBUG_DEBUG_VALUE 0x00FFFFFF +#define BF_PXP_FETCH_WFE_A_DEBUG_DEBUG_VALUE(v) \ + (((v) << 0) & BM_PXP_FETCH_WFE_A_DEBUG_DEBUG_VALUE) + +#define HW_PXP_FETCH_WFE_B_DEBUG (0x000015d0) + +#define BP_PXP_FETCH_WFE_B_DEBUG_RSVD 29 +#define BM_PXP_FETCH_WFE_B_DEBUG_RSVD 0xE0000000 +#define BF_PXP_FETCH_WFE_B_DEBUG_RSVD(v) \ + (((v) << 29) & BM_PXP_FETCH_WFE_B_DEBUG_RSVD) +#define BM_PXP_FETCH_WFE_B_DEBUG_BUF_SEL 0x10000000 +#define BF_PXP_FETCH_WFE_B_DEBUG_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_FETCH_WFE_B_DEBUG_BUF_SEL) +#define BV_PXP_FETCH_WFE_B_DEBUG_BUF_SEL__BF0 0x0 +#define BV_PXP_FETCH_WFE_B_DEBUG_BUF_SEL__BF1 0x1 +#define BP_PXP_FETCH_WFE_B_DEBUG_ITEM_SEL 24 +#define BM_PXP_FETCH_WFE_B_DEBUG_ITEM_SEL 0x0F000000 +#define BF_PXP_FETCH_WFE_B_DEBUG_ITEM_SEL(v) \ + (((v) << 24) & BM_PXP_FETCH_WFE_B_DEBUG_ITEM_SEL) +#define BP_PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE 0 +#define BM_PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE 0x00FFFFFF +#define BF_PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE(v) \ + (((v) << 0) & BM_PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE) + +#define HW_PXP_DITHER_CTRL (0x00001670) +#define HW_PXP_DITHER_CTRL_SET (0x00001674) +#define HW_PXP_DITHER_CTRL_CLR (0x00001678) +#define HW_PXP_DITHER_CTRL_TOG (0x0000167c) + +#define BM_PXP_DITHER_CTRL_BUSY0 0x80000000 +#define BF_PXP_DITHER_CTRL_BUSY0(v) \ + (((v) << 31) & BM_PXP_DITHER_CTRL_BUSY0) +#define BM_PXP_DITHER_CTRL_BUSY1 0x40000000 +#define BF_PXP_DITHER_CTRL_BUSY1(v) \ + (((v) << 30) & BM_PXP_DITHER_CTRL_BUSY1) +#define BM_PXP_DITHER_CTRL_BUSY2 0x20000000 +#define BF_PXP_DITHER_CTRL_BUSY2(v) \ + (((v) << 29) & BM_PXP_DITHER_CTRL_BUSY2) +#define BP_PXP_DITHER_CTRL_RSVD0 25 +#define BM_PXP_DITHER_CTRL_RSVD0 0x1E000000 +#define BF_PXP_DITHER_CTRL_RSVD0(v) \ + (((v) << 25) & BM_PXP_DITHER_CTRL_RSVD0) +#define BM_PXP_DITHER_CTRL_ORDERED_ROUND_MODE 0x01000000 +#define BF_PXP_DITHER_CTRL_ORDERED_ROUND_MODE(v) \ + (((v) << 24) & BM_PXP_DITHER_CTRL_ORDERED_ROUND_MODE) +#define BV_PXP_DITHER_CTRL_ORDERED_ROUND_MODE__0 0x0 +#define BV_PXP_DITHER_CTRL_ORDERED_ROUND_MODE__1 0x1 +#define BM_PXP_DITHER_CTRL_FINAL_LUT_ENABLE 0x00800000 +#define BF_PXP_DITHER_CTRL_FINAL_LUT_ENABLE(v) \ + (((v) << 23) & BM_PXP_DITHER_CTRL_FINAL_LUT_ENABLE) +#define BV_PXP_DITHER_CTRL_FINAL_LUT_ENABLE__Disabled 0x0 +#define BV_PXP_DITHER_CTRL_FINAL_LUT_ENABLE__Enabled 0x1 +#define BP_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE 21 +#define BM_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE 0x00600000 +#define BF_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE(v) \ + (((v) << 21) & BM_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE) +#define BV_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE__0 0x0 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE__1 0x1 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE__2 0x2 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE__3 0x3 +#define BP_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE 19 +#define BM_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE 0x00180000 +#define BF_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE(v) \ + (((v) << 19) & BM_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE) +#define BV_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE__0 0x0 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE__1 0x1 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE__2 0x2 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE__3 0x3 +#define BP_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE 17 +#define BM_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE 0x00060000 +#define BF_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE(v) \ + (((v) << 17) & BM_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE) +#define BV_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE__0 0x0 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE__1 0x1 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE__2 0x2 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE__3 0x3 +#define BP_PXP_DITHER_CTRL_LUT_MODE 15 +#define BM_PXP_DITHER_CTRL_LUT_MODE 0x00018000 +#define BF_PXP_DITHER_CTRL_LUT_MODE(v) \ + (((v) << 15) & BM_PXP_DITHER_CTRL_LUT_MODE) +#define BV_PXP_DITHER_CTRL_LUT_MODE__0 0x0 +#define BV_PXP_DITHER_CTRL_LUT_MODE__1 0x1 +#define BV_PXP_DITHER_CTRL_LUT_MODE__2 0x2 +#define BV_PXP_DITHER_CTRL_LUT_MODE__3 0x3 +#define BP_PXP_DITHER_CTRL_NUM_QUANT_BIT 12 +#define BM_PXP_DITHER_CTRL_NUM_QUANT_BIT 0x00007000 +#define BF_PXP_DITHER_CTRL_NUM_QUANT_BIT(v) \ + (((v) << 12) & BM_PXP_DITHER_CTRL_NUM_QUANT_BIT) +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__0 0x0 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__1 0x1 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__2 0x2 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__3 0x3 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__4 0x4 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__5 0x5 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__6 0x6 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__7 0x7 +#define BP_PXP_DITHER_CTRL_DITHER_MODE2 9 +#define BM_PXP_DITHER_CTRL_DITHER_MODE2 0x00000E00 +#define BF_PXP_DITHER_CTRL_DITHER_MODE2(v) \ + (((v) << 9) & BM_PXP_DITHER_CTRL_DITHER_MODE2) +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__0 0x0 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__1 0x1 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__2 0x2 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__3 0x3 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__4 0x4 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__5 0x5 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__6 0x6 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__7 0x7 +#define BP_PXP_DITHER_CTRL_DITHER_MODE1 6 +#define BM_PXP_DITHER_CTRL_DITHER_MODE1 0x000001C0 +#define BF_PXP_DITHER_CTRL_DITHER_MODE1(v) \ + (((v) << 6) & BM_PXP_DITHER_CTRL_DITHER_MODE1) +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__0 0x0 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__1 0x1 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__2 0x2 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__3 0x3 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__4 0x4 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__5 0x5 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__6 0x6 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__7 0x7 +#define BP_PXP_DITHER_CTRL_DITHER_MODE0 3 +#define BM_PXP_DITHER_CTRL_DITHER_MODE0 0x00000038 +#define BF_PXP_DITHER_CTRL_DITHER_MODE0(v) \ + (((v) << 3) & BM_PXP_DITHER_CTRL_DITHER_MODE0) +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__0 0x0 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__1 0x1 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__2 0x2 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__3 0x3 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__4 0x4 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__5 0x5 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__6 0x6 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__7 0x7 +#define BM_PXP_DITHER_CTRL_ENABLE2 0x00000004 +#define BF_PXP_DITHER_CTRL_ENABLE2(v) \ + (((v) << 2) & BM_PXP_DITHER_CTRL_ENABLE2) +#define BV_PXP_DITHER_CTRL_ENABLE2__Disabled 0x0 +#define BV_PXP_DITHER_CTRL_ENABLE2__Enabled 0x1 +#define BM_PXP_DITHER_CTRL_ENABLE1 0x00000002 +#define BF_PXP_DITHER_CTRL_ENABLE1(v) \ + (((v) << 1) & BM_PXP_DITHER_CTRL_ENABLE1) +#define BV_PXP_DITHER_CTRL_ENABLE1__Disabled 0x0 +#define BV_PXP_DITHER_CTRL_ENABLE1__Enabled 0x1 +#define BM_PXP_DITHER_CTRL_ENABLE0 0x00000001 +#define BF_PXP_DITHER_CTRL_ENABLE0(v) \ + (((v) << 0) & BM_PXP_DITHER_CTRL_ENABLE0) +#define BV_PXP_DITHER_CTRL_ENABLE0__Disabled 0x0 +#define BV_PXP_DITHER_CTRL_ENABLE0__Enabled 0x1 + +#define HW_PXP_DITHER_FINAL_LUT_DATA0 (0x00001680) +#define HW_PXP_DITHER_FINAL_LUT_DATA0_SET (0x00001684) +#define HW_PXP_DITHER_FINAL_LUT_DATA0_CLR (0x00001688) +#define HW_PXP_DITHER_FINAL_LUT_DATA0_TOG (0x0000168c) + +#define BP_PXP_DITHER_FINAL_LUT_DATA0_DATA3 24 +#define BM_PXP_DITHER_FINAL_LUT_DATA0_DATA3 0xFF000000 +#define BF_PXP_DITHER_FINAL_LUT_DATA0_DATA3(v) \ + (((v) << 24) & BM_PXP_DITHER_FINAL_LUT_DATA0_DATA3) +#define BP_PXP_DITHER_FINAL_LUT_DATA0_DATA2 16 +#define BM_PXP_DITHER_FINAL_LUT_DATA0_DATA2 0x00FF0000 +#define BF_PXP_DITHER_FINAL_LUT_DATA0_DATA2(v) \ + (((v) << 16) & BM_PXP_DITHER_FINAL_LUT_DATA0_DATA2) +#define BP_PXP_DITHER_FINAL_LUT_DATA0_DATA1 8 +#define BM_PXP_DITHER_FINAL_LUT_DATA0_DATA1 0x0000FF00 +#define BF_PXP_DITHER_FINAL_LUT_DATA0_DATA1(v) \ + (((v) << 8) & BM_PXP_DITHER_FINAL_LUT_DATA0_DATA1) +#define BP_PXP_DITHER_FINAL_LUT_DATA0_DATA0 0 +#define BM_PXP_DITHER_FINAL_LUT_DATA0_DATA0 0x000000FF +#define BF_PXP_DITHER_FINAL_LUT_DATA0_DATA0(v) \ + (((v) << 0) & BM_PXP_DITHER_FINAL_LUT_DATA0_DATA0) + +#define HW_PXP_DITHER_FINAL_LUT_DATA1 (0x00001690) +#define HW_PXP_DITHER_FINAL_LUT_DATA1_SET (0x00001694) +#define HW_PXP_DITHER_FINAL_LUT_DATA1_CLR (0x00001698) +#define HW_PXP_DITHER_FINAL_LUT_DATA1_TOG (0x0000169c) + +#define BP_PXP_DITHER_FINAL_LUT_DATA1_DATA7 24 +#define BM_PXP_DITHER_FINAL_LUT_DATA1_DATA7 0xFF000000 +#define BF_PXP_DITHER_FINAL_LUT_DATA1_DATA7(v) \ + (((v) << 24) & BM_PXP_DITHER_FINAL_LUT_DATA1_DATA7) +#define BP_PXP_DITHER_FINAL_LUT_DATA1_DATA6 16 +#define BM_PXP_DITHER_FINAL_LUT_DATA1_DATA6 0x00FF0000 +#define BF_PXP_DITHER_FINAL_LUT_DATA1_DATA6(v) \ + (((v) << 16) & BM_PXP_DITHER_FINAL_LUT_DATA1_DATA6) +#define BP_PXP_DITHER_FINAL_LUT_DATA1_DATA5 8 +#define BM_PXP_DITHER_FINAL_LUT_DATA1_DATA5 0x0000FF00 +#define BF_PXP_DITHER_FINAL_LUT_DATA1_DATA5(v) \ + (((v) << 8) & BM_PXP_DITHER_FINAL_LUT_DATA1_DATA5) +#define BP_PXP_DITHER_FINAL_LUT_DATA1_DATA4 0 +#define BM_PXP_DITHER_FINAL_LUT_DATA1_DATA4 0x000000FF +#define BF_PXP_DITHER_FINAL_LUT_DATA1_DATA4(v) \ + (((v) << 0) & BM_PXP_DITHER_FINAL_LUT_DATA1_DATA4) + +#define HW_PXP_DITHER_FINAL_LUT_DATA2 (0x000016a0) +#define HW_PXP_DITHER_FINAL_LUT_DATA2_SET (0x000016a4) +#define HW_PXP_DITHER_FINAL_LUT_DATA2_CLR (0x000016a8) +#define HW_PXP_DITHER_FINAL_LUT_DATA2_TOG (0x000016ac) + +#define BP_PXP_DITHER_FINAL_LUT_DATA2_DATA11 24 +#define BM_PXP_DITHER_FINAL_LUT_DATA2_DATA11 0xFF000000 +#define BF_PXP_DITHER_FINAL_LUT_DATA2_DATA11(v) \ + (((v) << 24) & BM_PXP_DITHER_FINAL_LUT_DATA2_DATA11) +#define BP_PXP_DITHER_FINAL_LUT_DATA2_DATA10 16 +#define BM_PXP_DITHER_FINAL_LUT_DATA2_DATA10 0x00FF0000 +#define BF_PXP_DITHER_FINAL_LUT_DATA2_DATA10(v) \ + (((v) << 16) & BM_PXP_DITHER_FINAL_LUT_DATA2_DATA10) +#define BP_PXP_DITHER_FINAL_LUT_DATA2_DATA9 8 +#define BM_PXP_DITHER_FINAL_LUT_DATA2_DATA9 0x0000FF00 +#define BF_PXP_DITHER_FINAL_LUT_DATA2_DATA9(v) \ + (((v) << 8) & BM_PXP_DITHER_FINAL_LUT_DATA2_DATA9) +#define BP_PXP_DITHER_FINAL_LUT_DATA2_DATA8 0 +#define BM_PXP_DITHER_FINAL_LUT_DATA2_DATA8 0x000000FF +#define BF_PXP_DITHER_FINAL_LUT_DATA2_DATA8(v) \ + (((v) << 0) & BM_PXP_DITHER_FINAL_LUT_DATA2_DATA8) + +#define HW_PXP_DITHER_FINAL_LUT_DATA3 (0x000016b0) +#define HW_PXP_DITHER_FINAL_LUT_DATA3_SET (0x000016b4) +#define HW_PXP_DITHER_FINAL_LUT_DATA3_CLR (0x000016b8) +#define HW_PXP_DITHER_FINAL_LUT_DATA3_TOG (0x000016bc) + +#define BP_PXP_DITHER_FINAL_LUT_DATA3_DATA15 24 +#define BM_PXP_DITHER_FINAL_LUT_DATA3_DATA15 0xFF000000 +#define BF_PXP_DITHER_FINAL_LUT_DATA3_DATA15(v) \ + (((v) << 24) & BM_PXP_DITHER_FINAL_LUT_DATA3_DATA15) +#define BP_PXP_DITHER_FINAL_LUT_DATA3_DATA14 16 +#define BM_PXP_DITHER_FINAL_LUT_DATA3_DATA14 0x00FF0000 +#define BF_PXP_DITHER_FINAL_LUT_DATA3_DATA14(v) \ + (((v) << 16) & BM_PXP_DITHER_FINAL_LUT_DATA3_DATA14) +#define BP_PXP_DITHER_FINAL_LUT_DATA3_DATA13 8 +#define BM_PXP_DITHER_FINAL_LUT_DATA3_DATA13 0x0000FF00 +#define BF_PXP_DITHER_FINAL_LUT_DATA3_DATA13(v) \ + (((v) << 8) & BM_PXP_DITHER_FINAL_LUT_DATA3_DATA13) +#define BP_PXP_DITHER_FINAL_LUT_DATA3_DATA12 0 +#define BM_PXP_DITHER_FINAL_LUT_DATA3_DATA12 0x000000FF +#define BF_PXP_DITHER_FINAL_LUT_DATA3_DATA12(v) \ + (((v) << 0) & BM_PXP_DITHER_FINAL_LUT_DATA3_DATA12) + +#define HW_PXP_WFE_A_CTRL (0x000016c0) +#define HW_PXP_WFE_A_CTRL_SET (0x000016c4) +#define HW_PXP_WFE_A_CTRL_CLR (0x000016c8) +#define HW_PXP_WFE_A_CTRL_TOG (0x000016cc) + +#define BM_PXP_WFE_A_CTRL_DONE 0x80000000 +#define BF_PXP_WFE_A_CTRL_DONE(v) \ + (((v) << 31) & BM_PXP_WFE_A_CTRL_DONE) +#define BP_PXP_WFE_A_CTRL_RSVD0 3 +#define BM_PXP_WFE_A_CTRL_RSVD0 0x7FFFFFF8 +#define BF_PXP_WFE_A_CTRL_RSVD0(v) \ + (((v) << 3) & BM_PXP_WFE_A_CTRL_RSVD0) +#define BM_PXP_WFE_A_CTRL_SW_RESET 0x00000004 +#define BF_PXP_WFE_A_CTRL_SW_RESET(v) \ + (((v) << 2) & BM_PXP_WFE_A_CTRL_SW_RESET) +#define BM_PXP_WFE_A_CTRL_RSVD1 0x00000002 +#define BF_PXP_WFE_A_CTRL_RSVD1(v) \ + (((v) << 1) & BM_PXP_WFE_A_CTRL_RSVD1) +#define BM_PXP_WFE_A_CTRL_ENABLE 0x00000001 +#define BF_PXP_WFE_A_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_WFE_A_CTRL_ENABLE) +#define BV_PXP_WFE_A_CTRL_ENABLE__0 0x0 +#define BV_PXP_WFE_A_CTRL_ENABLE__1 0x1 + +#define HW_PXP_WFE_A_DIMENSIONS (0x000016d0) + +#define BP_PXP_WFE_A_DIMENSIONS_RSVD0 28 +#define BM_PXP_WFE_A_DIMENSIONS_RSVD0 0xF0000000 +#define BF_PXP_WFE_A_DIMENSIONS_RSVD0(v) \ + (((v) << 28) & BM_PXP_WFE_A_DIMENSIONS_RSVD0) +#define BP_PXP_WFE_A_DIMENSIONS_HEIGHT 16 +#define BM_PXP_WFE_A_DIMENSIONS_HEIGHT 0x0FFF0000 +#define BF_PXP_WFE_A_DIMENSIONS_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFE_A_DIMENSIONS_HEIGHT) +#define BP_PXP_WFE_A_DIMENSIONS_RSVD1 12 +#define BM_PXP_WFE_A_DIMENSIONS_RSVD1 0x0000F000 +#define BF_PXP_WFE_A_DIMENSIONS_RSVD1(v) \ + (((v) << 12) & BM_PXP_WFE_A_DIMENSIONS_RSVD1) +#define BP_PXP_WFE_A_DIMENSIONS_WIDTH 0 +#define BM_PXP_WFE_A_DIMENSIONS_WIDTH 0x00000FFF +#define BF_PXP_WFE_A_DIMENSIONS_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFE_A_DIMENSIONS_WIDTH) + +#define HW_PXP_WFE_A_OFFSET (0x000016e0) + +#define BP_PXP_WFE_A_OFFSET_RSVD0 28 +#define BM_PXP_WFE_A_OFFSET_RSVD0 0xF0000000 +#define BF_PXP_WFE_A_OFFSET_RSVD0(v) \ + (((v) << 28) & BM_PXP_WFE_A_OFFSET_RSVD0) +#define BP_PXP_WFE_A_OFFSET_Y_OFFSET 16 +#define BM_PXP_WFE_A_OFFSET_Y_OFFSET 0x0FFF0000 +#define BF_PXP_WFE_A_OFFSET_Y_OFFSET(v) \ + (((v) << 16) & BM_PXP_WFE_A_OFFSET_Y_OFFSET) +#define BP_PXP_WFE_A_OFFSET_RSVD1 12 +#define BM_PXP_WFE_A_OFFSET_RSVD1 0x0000F000 +#define BF_PXP_WFE_A_OFFSET_RSVD1(v) \ + (((v) << 12) & BM_PXP_WFE_A_OFFSET_RSVD1) +#define BP_PXP_WFE_A_OFFSET_X_OFFSET 0 +#define BM_PXP_WFE_A_OFFSET_X_OFFSET 0x00000FFF +#define BF_PXP_WFE_A_OFFSET_X_OFFSET(v) \ + (((v) << 0) & BM_PXP_WFE_A_OFFSET_X_OFFSET) + +#define HW_PXP_WFE_A_SW_DATA_REGS (0x000016f0) + +#define BP_PXP_WFE_A_SW_DATA_REGS_VAL3 24 +#define BM_PXP_WFE_A_SW_DATA_REGS_VAL3 0xFF000000 +#define BF_PXP_WFE_A_SW_DATA_REGS_VAL3(v) \ + (((v) << 24) & BM_PXP_WFE_A_SW_DATA_REGS_VAL3) +#define BP_PXP_WFE_A_SW_DATA_REGS_VAL2 16 +#define BM_PXP_WFE_A_SW_DATA_REGS_VAL2 0x00FF0000 +#define BF_PXP_WFE_A_SW_DATA_REGS_VAL2(v) \ + (((v) << 16) & BM_PXP_WFE_A_SW_DATA_REGS_VAL2) +#define BP_PXP_WFE_A_SW_DATA_REGS_VAL1 8 +#define BM_PXP_WFE_A_SW_DATA_REGS_VAL1 0x0000FF00 +#define BF_PXP_WFE_A_SW_DATA_REGS_VAL1(v) \ + (((v) << 8) & BM_PXP_WFE_A_SW_DATA_REGS_VAL1) +#define BP_PXP_WFE_A_SW_DATA_REGS_VAL0 0 +#define BM_PXP_WFE_A_SW_DATA_REGS_VAL0 0x000000FF +#define BF_PXP_WFE_A_SW_DATA_REGS_VAL0(v) \ + (((v) << 0) & BM_PXP_WFE_A_SW_DATA_REGS_VAL0) + +#define HW_PXP_WFE_A_SW_FLAG_REGS (0x00001700) + +#define BP_PXP_WFE_A_SW_FLAG_REGS_RSVD 4 +#define BM_PXP_WFE_A_SW_FLAG_REGS_RSVD 0xFFFFFFF0 +#define BF_PXP_WFE_A_SW_FLAG_REGS_RSVD(v) \ + (((v) << 4) & BM_PXP_WFE_A_SW_FLAG_REGS_RSVD) +#define BM_PXP_WFE_A_SW_FLAG_REGS_VAL3 0x00000008 +#define BF_PXP_WFE_A_SW_FLAG_REGS_VAL3(v) \ + (((v) << 3) & BM_PXP_WFE_A_SW_FLAG_REGS_VAL3) +#define BM_PXP_WFE_A_SW_FLAG_REGS_VAL2 0x00000004 +#define BF_PXP_WFE_A_SW_FLAG_REGS_VAL2(v) \ + (((v) << 2) & BM_PXP_WFE_A_SW_FLAG_REGS_VAL2) +#define BM_PXP_WFE_A_SW_FLAG_REGS_VAL1 0x00000002 +#define BF_PXP_WFE_A_SW_FLAG_REGS_VAL1(v) \ + (((v) << 1) & BM_PXP_WFE_A_SW_FLAG_REGS_VAL1) +#define BM_PXP_WFE_A_SW_FLAG_REGS_VAL0 0x00000001 +#define BF_PXP_WFE_A_SW_FLAG_REGS_VAL0(v) \ + (((v) << 0) & BM_PXP_WFE_A_SW_FLAG_REGS_VAL0) + +#define HW_PXP_WFE_A_STAGE1_MUX0 (0x00001710) +#define HW_PXP_WFE_A_STAGE1_MUX0_SET (0x00001714) +#define HW_PXP_WFE_A_STAGE1_MUX0_CLR (0x00001718) +#define HW_PXP_WFE_A_STAGE1_MUX0_TOG (0x0000171c) + +#define BP_PXP_WFE_A_STAGE1_MUX0_RSVD0 30 +#define BM_PXP_WFE_A_STAGE1_MUX0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE1_MUX0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE1_MUX0_RSVD0) +#define BP_PXP_WFE_A_STAGE1_MUX0_MUX3 24 +#define BM_PXP_WFE_A_STAGE1_MUX0_MUX3 0x3F000000 +#define BF_PXP_WFE_A_STAGE1_MUX0_MUX3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE1_MUX0_MUX3) +#define BP_PXP_WFE_A_STAGE1_MUX0_RSVD1 22 +#define BM_PXP_WFE_A_STAGE1_MUX0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE1_MUX0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE1_MUX0_RSVD1) +#define BP_PXP_WFE_A_STAGE1_MUX0_MUX2 16 +#define BM_PXP_WFE_A_STAGE1_MUX0_MUX2 0x003F0000 +#define BF_PXP_WFE_A_STAGE1_MUX0_MUX2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE1_MUX0_MUX2) +#define BP_PXP_WFE_A_STAGE1_MUX0_RSVD2 14 +#define BM_PXP_WFE_A_STAGE1_MUX0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE1_MUX0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE1_MUX0_RSVD2) +#define BP_PXP_WFE_A_STAGE1_MUX0_MUX1 8 +#define BM_PXP_WFE_A_STAGE1_MUX0_MUX1 0x00003F00 +#define BF_PXP_WFE_A_STAGE1_MUX0_MUX1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE1_MUX0_MUX1) +#define BP_PXP_WFE_A_STAGE1_MUX0_RSVD3 6 +#define BM_PXP_WFE_A_STAGE1_MUX0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE1_MUX0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE1_MUX0_RSVD3) +#define BP_PXP_WFE_A_STAGE1_MUX0_MUX0 0 +#define BM_PXP_WFE_A_STAGE1_MUX0_MUX0 0x0000003F +#define BF_PXP_WFE_A_STAGE1_MUX0_MUX0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE1_MUX0_MUX0) + +#define HW_PXP_WFE_A_STAGE1_MUX1 (0x00001720) +#define HW_PXP_WFE_A_STAGE1_MUX1_SET (0x00001724) +#define HW_PXP_WFE_A_STAGE1_MUX1_CLR (0x00001728) +#define HW_PXP_WFE_A_STAGE1_MUX1_TOG (0x0000172c) + +#define BP_PXP_WFE_A_STAGE1_MUX1_RSVD0 30 +#define BM_PXP_WFE_A_STAGE1_MUX1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE1_MUX1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE1_MUX1_RSVD0) +#define BP_PXP_WFE_A_STAGE1_MUX1_MUX7 24 +#define BM_PXP_WFE_A_STAGE1_MUX1_MUX7 0x3F000000 +#define BF_PXP_WFE_A_STAGE1_MUX1_MUX7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE1_MUX1_MUX7) +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__INC 0x0 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__DEC 0x1 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__ADD 0x2 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__MINUS 0x3 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__AND 0x4 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__OR 0x5 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__XOR 0x6 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__SHIFTLEFT 0x7 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__SHIFTRIGHT 0x8 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__BIT_AND 0x9 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__BIT_OR 0xa +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__BIT_CMP 0xb +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__NOP 0xc +#define BP_PXP_WFE_A_STAGE1_MUX1_RSVD1 22 +#define BM_PXP_WFE_A_STAGE1_MUX1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE1_MUX1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE1_MUX1_RSVD1) +#define BP_PXP_WFE_A_STAGE1_MUX1_MUX6 16 +#define BM_PXP_WFE_A_STAGE1_MUX1_MUX6 0x003F0000 +#define BF_PXP_WFE_A_STAGE1_MUX1_MUX6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE1_MUX1_MUX6) +#define BP_PXP_WFE_A_STAGE1_MUX1_RSVD2 14 +#define BM_PXP_WFE_A_STAGE1_MUX1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE1_MUX1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE1_MUX1_RSVD2) +#define BP_PXP_WFE_A_STAGE1_MUX1_MUX5 8 +#define BM_PXP_WFE_A_STAGE1_MUX1_MUX5 0x00003F00 +#define BF_PXP_WFE_A_STAGE1_MUX1_MUX5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE1_MUX1_MUX5) +#define BP_PXP_WFE_A_STAGE1_MUX1_RSVD3 6 +#define BM_PXP_WFE_A_STAGE1_MUX1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE1_MUX1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE1_MUX1_RSVD3) +#define BP_PXP_WFE_A_STAGE1_MUX1_MUX4 0 +#define BM_PXP_WFE_A_STAGE1_MUX1_MUX4 0x0000003F +#define BF_PXP_WFE_A_STAGE1_MUX1_MUX4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE1_MUX1_MUX4) +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__INC 0x0 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__DEC 0x1 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__ADD 0x2 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__MINUS 0x3 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__AND 0x4 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__OR 0x5 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__XOR 0x6 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__SHIFTLEFT 0x7 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__SHIFTRIGHT 0x8 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__BIT_AND 0x9 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__BIT_OR 0xa +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__BIT_CMP 0xb +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__NOP 0xc + +#define HW_PXP_WFE_A_STAGE1_MUX2 (0x00001730) +#define HW_PXP_WFE_A_STAGE1_MUX2_SET (0x00001734) +#define HW_PXP_WFE_A_STAGE1_MUX2_CLR (0x00001738) +#define HW_PXP_WFE_A_STAGE1_MUX2_TOG (0x0000173c) + +#define BP_PXP_WFE_A_STAGE1_MUX2_RSVD0 30 +#define BM_PXP_WFE_A_STAGE1_MUX2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE1_MUX2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE1_MUX2_RSVD0) +#define BP_PXP_WFE_A_STAGE1_MUX2_MUX11 24 +#define BM_PXP_WFE_A_STAGE1_MUX2_MUX11 0x3F000000 +#define BF_PXP_WFE_A_STAGE1_MUX2_MUX11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE1_MUX2_MUX11) +#define BP_PXP_WFE_A_STAGE1_MUX2_RSVD1 22 +#define BM_PXP_WFE_A_STAGE1_MUX2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE1_MUX2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE1_MUX2_RSVD1) +#define BP_PXP_WFE_A_STAGE1_MUX2_MUX10 16 +#define BM_PXP_WFE_A_STAGE1_MUX2_MUX10 0x003F0000 +#define BF_PXP_WFE_A_STAGE1_MUX2_MUX10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE1_MUX2_MUX10) +#define BP_PXP_WFE_A_STAGE1_MUX2_RSVD2 14 +#define BM_PXP_WFE_A_STAGE1_MUX2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE1_MUX2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE1_MUX2_RSVD2) +#define BP_PXP_WFE_A_STAGE1_MUX2_MUX9 8 +#define BM_PXP_WFE_A_STAGE1_MUX2_MUX9 0x00003F00 +#define BF_PXP_WFE_A_STAGE1_MUX2_MUX9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE1_MUX2_MUX9) +#define BP_PXP_WFE_A_STAGE1_MUX2_RSVD3 6 +#define BM_PXP_WFE_A_STAGE1_MUX2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE1_MUX2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE1_MUX2_RSVD3) +#define BP_PXP_WFE_A_STAGE1_MUX2_MUX8 0 +#define BM_PXP_WFE_A_STAGE1_MUX2_MUX8 0x0000003F +#define BF_PXP_WFE_A_STAGE1_MUX2_MUX8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE1_MUX2_MUX8) + +#define HW_PXP_WFE_A_STAGE1_MUX3 (0x00001740) +#define HW_PXP_WFE_A_STAGE1_MUX3_SET (0x00001744) +#define HW_PXP_WFE_A_STAGE1_MUX3_CLR (0x00001748) +#define HW_PXP_WFE_A_STAGE1_MUX3_TOG (0x0000174c) + +#define BP_PXP_WFE_A_STAGE1_MUX3_RSVD0 30 +#define BM_PXP_WFE_A_STAGE1_MUX3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE1_MUX3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE1_MUX3_RSVD0) +#define BP_PXP_WFE_A_STAGE1_MUX3_MUX15 24 +#define BM_PXP_WFE_A_STAGE1_MUX3_MUX15 0x3F000000 +#define BF_PXP_WFE_A_STAGE1_MUX3_MUX15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE1_MUX3_MUX15) +#define BP_PXP_WFE_A_STAGE1_MUX3_RSVD1 22 +#define BM_PXP_WFE_A_STAGE1_MUX3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE1_MUX3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE1_MUX3_RSVD1) +#define BP_PXP_WFE_A_STAGE1_MUX3_MUX14 16 +#define BM_PXP_WFE_A_STAGE1_MUX3_MUX14 0x003F0000 +#define BF_PXP_WFE_A_STAGE1_MUX3_MUX14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE1_MUX3_MUX14) +#define BP_PXP_WFE_A_STAGE1_MUX3_RSVD2 14 +#define BM_PXP_WFE_A_STAGE1_MUX3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE1_MUX3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE1_MUX3_RSVD2) +#define BP_PXP_WFE_A_STAGE1_MUX3_MUX13 8 +#define BM_PXP_WFE_A_STAGE1_MUX3_MUX13 0x00003F00 +#define BF_PXP_WFE_A_STAGE1_MUX3_MUX13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE1_MUX3_MUX13) +#define BP_PXP_WFE_A_STAGE1_MUX3_RSVD3 6 +#define BM_PXP_WFE_A_STAGE1_MUX3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE1_MUX3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE1_MUX3_RSVD3) +#define BP_PXP_WFE_A_STAGE1_MUX3_MUX12 0 +#define BM_PXP_WFE_A_STAGE1_MUX3_MUX12 0x0000003F +#define BF_PXP_WFE_A_STAGE1_MUX3_MUX12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE1_MUX3_MUX12) + +#define HW_PXP_WFE_A_STAGE1_MUX4 (0x00001750) +#define HW_PXP_WFE_A_STAGE1_MUX4_SET (0x00001754) +#define HW_PXP_WFE_A_STAGE1_MUX4_CLR (0x00001758) +#define HW_PXP_WFE_A_STAGE1_MUX4_TOG (0x0000175c) + +#define BP_PXP_WFE_A_STAGE1_MUX4_RSVD0 24 +#define BM_PXP_WFE_A_STAGE1_MUX4_RSVD0 0xFF000000 +#define BF_PXP_WFE_A_STAGE1_MUX4_RSVD0(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE1_MUX4_RSVD0) +#define BP_PXP_WFE_A_STAGE1_MUX4_RSVD1 16 +#define BM_PXP_WFE_A_STAGE1_MUX4_RSVD1 0x00FF0000 +#define BF_PXP_WFE_A_STAGE1_MUX4_RSVD1(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE1_MUX4_RSVD1) +#define BP_PXP_WFE_A_STAGE1_MUX4_RSVD2 14 +#define BM_PXP_WFE_A_STAGE1_MUX4_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE1_MUX4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE1_MUX4_RSVD2) +#define BP_PXP_WFE_A_STAGE1_MUX4_MUX17 8 +#define BM_PXP_WFE_A_STAGE1_MUX4_MUX17 0x00003F00 +#define BF_PXP_WFE_A_STAGE1_MUX4_MUX17(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE1_MUX4_MUX17) +#define BP_PXP_WFE_A_STAGE1_MUX4_RSVD3 6 +#define BM_PXP_WFE_A_STAGE1_MUX4_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE1_MUX4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE1_MUX4_RSVD3) +#define BP_PXP_WFE_A_STAGE1_MUX4_MUX16 0 +#define BM_PXP_WFE_A_STAGE1_MUX4_MUX16 0x0000003F +#define BF_PXP_WFE_A_STAGE1_MUX4_MUX16(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE1_MUX4_MUX16) + +#define HW_PXP_WFE_A_STAGE2_MUX0 (0x00001760) +#define HW_PXP_WFE_A_STAGE2_MUX0_SET (0x00001764) +#define HW_PXP_WFE_A_STAGE2_MUX0_CLR (0x00001768) +#define HW_PXP_WFE_A_STAGE2_MUX0_TOG (0x0000176c) + +#define BP_PXP_WFE_A_STAGE2_MUX0_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX0_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX0_MUX3 24 +#define BM_PXP_WFE_A_STAGE2_MUX0_MUX3 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX0_MUX3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX0_MUX3) +#define BP_PXP_WFE_A_STAGE2_MUX0_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX0_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX0_MUX2 16 +#define BM_PXP_WFE_A_STAGE2_MUX0_MUX2 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX0_MUX2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX0_MUX2) +#define BP_PXP_WFE_A_STAGE2_MUX0_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX0_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX0_MUX1 8 +#define BM_PXP_WFE_A_STAGE2_MUX0_MUX1 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX0_MUX1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX0_MUX1) +#define BP_PXP_WFE_A_STAGE2_MUX0_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX0_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX0_MUX0 0 +#define BM_PXP_WFE_A_STAGE2_MUX0_MUX0 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX0_MUX0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX0_MUX0) + +#define HW_PXP_WFE_A_STAGE2_MUX1 (0x00001770) +#define HW_PXP_WFE_A_STAGE2_MUX1_SET (0x00001774) +#define HW_PXP_WFE_A_STAGE2_MUX1_CLR (0x00001778) +#define HW_PXP_WFE_A_STAGE2_MUX1_TOG (0x0000177c) + +#define BP_PXP_WFE_A_STAGE2_MUX1_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX1_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX1_MUX7 24 +#define BM_PXP_WFE_A_STAGE2_MUX1_MUX7 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX1_MUX7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX1_MUX7) +#define BP_PXP_WFE_A_STAGE2_MUX1_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX1_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX1_MUX6 16 +#define BM_PXP_WFE_A_STAGE2_MUX1_MUX6 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX1_MUX6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX1_MUX6) +#define BP_PXP_WFE_A_STAGE2_MUX1_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX1_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX1_MUX5 8 +#define BM_PXP_WFE_A_STAGE2_MUX1_MUX5 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX1_MUX5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX1_MUX5) +#define BP_PXP_WFE_A_STAGE2_MUX1_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX1_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX1_MUX4 0 +#define BM_PXP_WFE_A_STAGE2_MUX1_MUX4 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX1_MUX4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX1_MUX4) + +#define HW_PXP_WFE_A_STAGE2_MUX2 (0x00001780) +#define HW_PXP_WFE_A_STAGE2_MUX2_SET (0x00001784) +#define HW_PXP_WFE_A_STAGE2_MUX2_CLR (0x00001788) +#define HW_PXP_WFE_A_STAGE2_MUX2_TOG (0x0000178c) + +#define BP_PXP_WFE_A_STAGE2_MUX2_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX2_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX2_MUX11 24 +#define BM_PXP_WFE_A_STAGE2_MUX2_MUX11 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX2_MUX11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX2_MUX11) +#define BP_PXP_WFE_A_STAGE2_MUX2_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX2_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX2_MUX10 16 +#define BM_PXP_WFE_A_STAGE2_MUX2_MUX10 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX2_MUX10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX2_MUX10) +#define BP_PXP_WFE_A_STAGE2_MUX2_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX2_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX2_MUX9 8 +#define BM_PXP_WFE_A_STAGE2_MUX2_MUX9 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX2_MUX9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX2_MUX9) +#define BP_PXP_WFE_A_STAGE2_MUX2_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX2_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX2_MUX8 0 +#define BM_PXP_WFE_A_STAGE2_MUX2_MUX8 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX2_MUX8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX2_MUX8) + +#define HW_PXP_WFE_A_STAGE2_MUX3 (0x00001790) +#define HW_PXP_WFE_A_STAGE2_MUX3_SET (0x00001794) +#define HW_PXP_WFE_A_STAGE2_MUX3_CLR (0x00001798) +#define HW_PXP_WFE_A_STAGE2_MUX3_TOG (0x0000179c) + +#define BP_PXP_WFE_A_STAGE2_MUX3_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX3_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX3_MUX15 24 +#define BM_PXP_WFE_A_STAGE2_MUX3_MUX15 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX3_MUX15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX3_MUX15) +#define BP_PXP_WFE_A_STAGE2_MUX3_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX3_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX3_MUX14 16 +#define BM_PXP_WFE_A_STAGE2_MUX3_MUX14 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX3_MUX14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX3_MUX14) +#define BP_PXP_WFE_A_STAGE2_MUX3_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX3_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX3_MUX13 8 +#define BM_PXP_WFE_A_STAGE2_MUX3_MUX13 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX3_MUX13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX3_MUX13) +#define BP_PXP_WFE_A_STAGE2_MUX3_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX3_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX3_MUX12 0 +#define BM_PXP_WFE_A_STAGE2_MUX3_MUX12 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX3_MUX12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX3_MUX12) + +#define HW_PXP_WFE_A_STAGE2_MUX4 (0x000017a0) +#define HW_PXP_WFE_A_STAGE2_MUX4_SET (0x000017a4) +#define HW_PXP_WFE_A_STAGE2_MUX4_CLR (0x000017a8) +#define HW_PXP_WFE_A_STAGE2_MUX4_TOG (0x000017ac) + +#define BP_PXP_WFE_A_STAGE2_MUX4_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX4_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX4_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX4_MUX19 24 +#define BM_PXP_WFE_A_STAGE2_MUX4_MUX19 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX4_MUX19(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX4_MUX19) +#define BP_PXP_WFE_A_STAGE2_MUX4_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX4_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX4_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX4_MUX18 16 +#define BM_PXP_WFE_A_STAGE2_MUX4_MUX18 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX4_MUX18(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX4_MUX18) +#define BP_PXP_WFE_A_STAGE2_MUX4_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX4_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX4_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX4_MUX17 8 +#define BM_PXP_WFE_A_STAGE2_MUX4_MUX17 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX4_MUX17(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX4_MUX17) +#define BP_PXP_WFE_A_STAGE2_MUX4_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX4_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX4_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX4_MUX16 0 +#define BM_PXP_WFE_A_STAGE2_MUX4_MUX16 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX4_MUX16(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX4_MUX16) + +#define HW_PXP_WFE_A_STAGE2_MUX5 (0x000017b0) +#define HW_PXP_WFE_A_STAGE2_MUX5_SET (0x000017b4) +#define HW_PXP_WFE_A_STAGE2_MUX5_CLR (0x000017b8) +#define HW_PXP_WFE_A_STAGE2_MUX5_TOG (0x000017bc) + +#define BP_PXP_WFE_A_STAGE2_MUX5_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX5_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX5_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX5_MUX23 24 +#define BM_PXP_WFE_A_STAGE2_MUX5_MUX23 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX5_MUX23(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX5_MUX23) +#define BP_PXP_WFE_A_STAGE2_MUX5_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX5_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX5_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX5_MUX22 16 +#define BM_PXP_WFE_A_STAGE2_MUX5_MUX22 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX5_MUX22(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX5_MUX22) +#define BP_PXP_WFE_A_STAGE2_MUX5_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX5_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX5_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX5_MUX21 8 +#define BM_PXP_WFE_A_STAGE2_MUX5_MUX21 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX5_MUX21(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX5_MUX21) +#define BP_PXP_WFE_A_STAGE2_MUX5_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX5_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX5_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX5_MUX20 0 +#define BM_PXP_WFE_A_STAGE2_MUX5_MUX20 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX5_MUX20(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX5_MUX20) + +#define HW_PXP_WFE_A_STAGE2_MUX6 (0x000017c0) +#define HW_PXP_WFE_A_STAGE2_MUX6_SET (0x000017c4) +#define HW_PXP_WFE_A_STAGE2_MUX6_CLR (0x000017c8) +#define HW_PXP_WFE_A_STAGE2_MUX6_TOG (0x000017cc) + +#define BP_PXP_WFE_A_STAGE2_MUX6_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX6_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX6_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX6_MUX27 24 +#define BM_PXP_WFE_A_STAGE2_MUX6_MUX27 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX6_MUX27(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX6_MUX27) +#define BP_PXP_WFE_A_STAGE2_MUX6_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX6_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX6_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX6_MUX26 16 +#define BM_PXP_WFE_A_STAGE2_MUX6_MUX26 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX6_MUX26(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX6_MUX26) +#define BP_PXP_WFE_A_STAGE2_MUX6_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX6_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX6_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX6_MUX25 8 +#define BM_PXP_WFE_A_STAGE2_MUX6_MUX25 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX6_MUX25(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX6_MUX25) +#define BP_PXP_WFE_A_STAGE2_MUX6_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX6_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX6_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX6_MUX24 0 +#define BM_PXP_WFE_A_STAGE2_MUX6_MUX24 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX6_MUX24(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX6_MUX24) + +#define HW_PXP_WFE_A_STAGE2_MUX7 (0x000017d0) +#define HW_PXP_WFE_A_STAGE2_MUX7_SET (0x000017d4) +#define HW_PXP_WFE_A_STAGE2_MUX7_CLR (0x000017d8) +#define HW_PXP_WFE_A_STAGE2_MUX7_TOG (0x000017dc) + +#define BP_PXP_WFE_A_STAGE2_MUX7_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX7_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX7_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX7_MUX31 24 +#define BM_PXP_WFE_A_STAGE2_MUX7_MUX31 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX7_MUX31(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX7_MUX31) +#define BP_PXP_WFE_A_STAGE2_MUX7_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX7_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX7_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX7_MUX30 16 +#define BM_PXP_WFE_A_STAGE2_MUX7_MUX30 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX7_MUX30(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX7_MUX30) +#define BP_PXP_WFE_A_STAGE2_MUX7_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX7_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX7_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX7_MUX29 8 +#define BM_PXP_WFE_A_STAGE2_MUX7_MUX29 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX7_MUX29(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX7_MUX29) +#define BP_PXP_WFE_A_STAGE2_MUX7_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX7_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX7_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX7_MUX28 0 +#define BM_PXP_WFE_A_STAGE2_MUX7_MUX28 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX7_MUX28(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX7_MUX28) + +#define HW_PXP_WFE_A_STAGE2_MUX8 (0x000017e0) +#define HW_PXP_WFE_A_STAGE2_MUX8_SET (0x000017e4) +#define HW_PXP_WFE_A_STAGE2_MUX8_CLR (0x000017e8) +#define HW_PXP_WFE_A_STAGE2_MUX8_TOG (0x000017ec) + +#define BP_PXP_WFE_A_STAGE2_MUX8_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX8_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX8_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX8_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX8_MUX35 24 +#define BM_PXP_WFE_A_STAGE2_MUX8_MUX35 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX8_MUX35(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX8_MUX35) +#define BP_PXP_WFE_A_STAGE2_MUX8_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX8_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX8_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX8_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX8_MUX34 16 +#define BM_PXP_WFE_A_STAGE2_MUX8_MUX34 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX8_MUX34(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX8_MUX34) +#define BP_PXP_WFE_A_STAGE2_MUX8_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX8_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX8_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX8_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX8_MUX33 8 +#define BM_PXP_WFE_A_STAGE2_MUX8_MUX33 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX8_MUX33(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX8_MUX33) +#define BP_PXP_WFE_A_STAGE2_MUX8_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX8_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX8_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX8_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX8_MUX32 0 +#define BM_PXP_WFE_A_STAGE2_MUX8_MUX32 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX8_MUX32(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX8_MUX32) + +#define HW_PXP_WFE_A_STAGE2_MUX9 (0x000017f0) +#define HW_PXP_WFE_A_STAGE2_MUX9_SET (0x000017f4) +#define HW_PXP_WFE_A_STAGE2_MUX9_CLR (0x000017f8) +#define HW_PXP_WFE_A_STAGE2_MUX9_TOG (0x000017fc) + +#define BP_PXP_WFE_A_STAGE2_MUX9_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX9_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX9_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX9_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX9_MUX39 24 +#define BM_PXP_WFE_A_STAGE2_MUX9_MUX39 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX9_MUX39(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX9_MUX39) +#define BP_PXP_WFE_A_STAGE2_MUX9_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX9_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX9_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX9_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX9_MUX38 16 +#define BM_PXP_WFE_A_STAGE2_MUX9_MUX38 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX9_MUX38(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX9_MUX38) +#define BP_PXP_WFE_A_STAGE2_MUX9_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX9_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX9_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX9_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX9_MUX37 8 +#define BM_PXP_WFE_A_STAGE2_MUX9_MUX37 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX9_MUX37(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX9_MUX37) +#define BP_PXP_WFE_A_STAGE2_MUX9_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX9_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX9_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX9_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX9_MUX36 0 +#define BM_PXP_WFE_A_STAGE2_MUX9_MUX36 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX9_MUX36(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX9_MUX36) + +#define HW_PXP_WFE_A_STAGE2_MUX10 (0x00001800) +#define HW_PXP_WFE_A_STAGE2_MUX10_SET (0x00001804) +#define HW_PXP_WFE_A_STAGE2_MUX10_CLR (0x00001808) +#define HW_PXP_WFE_A_STAGE2_MUX10_TOG (0x0000180c) + +#define BP_PXP_WFE_A_STAGE2_MUX10_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX10_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX10_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX10_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX10_MUX43 24 +#define BM_PXP_WFE_A_STAGE2_MUX10_MUX43 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX10_MUX43(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX10_MUX43) +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__INC 0x0 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__DEC 0x1 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__ADD 0x2 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__MINUS 0x3 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__AND 0x4 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__OR 0x5 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__XOR 0x6 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__SHIFTLEFT 0x7 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__SHIFTRIGHT 0x8 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__BIT_AND 0x9 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__BIT_OR 0xa +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__BIT_CMP 0xb +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__NOP 0xc +#define BP_PXP_WFE_A_STAGE2_MUX10_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX10_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX10_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX10_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX10_MUX42 16 +#define BM_PXP_WFE_A_STAGE2_MUX10_MUX42 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX10_MUX42(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX10_MUX42) +#define BP_PXP_WFE_A_STAGE2_MUX10_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX10_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX10_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX10_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX10_MUX41 8 +#define BM_PXP_WFE_A_STAGE2_MUX10_MUX41 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX10_MUX41(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX10_MUX41) +#define BP_PXP_WFE_A_STAGE2_MUX10_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX10_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX10_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX10_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX10_MUX40 0 +#define BM_PXP_WFE_A_STAGE2_MUX10_MUX40 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX10_MUX40(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX10_MUX40) +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__INC 0x0 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__DEC 0x1 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__ADD 0x2 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__MINUS 0x3 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__AND 0x4 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__OR 0x5 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__XOR 0x6 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__SHIFTLEFT 0x7 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__SHIFTRIGHT 0x8 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__BIT_AND 0x9 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__BIT_OR 0xa +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__BIT_CMP 0xb +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__NOP 0xc + +#define HW_PXP_WFE_A_STAGE2_MUX11 (0x00001810) +#define HW_PXP_WFE_A_STAGE2_MUX11_SET (0x00001814) +#define HW_PXP_WFE_A_STAGE2_MUX11_CLR (0x00001818) +#define HW_PXP_WFE_A_STAGE2_MUX11_TOG (0x0000181c) + +#define BP_PXP_WFE_A_STAGE2_MUX11_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX11_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX11_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX11_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX11_MUX47 24 +#define BM_PXP_WFE_A_STAGE2_MUX11_MUX47 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX11_MUX47(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX11_MUX47) +#define BP_PXP_WFE_A_STAGE2_MUX11_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX11_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX11_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX11_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX11_MUX46 16 +#define BM_PXP_WFE_A_STAGE2_MUX11_MUX46 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX11_MUX46(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX11_MUX46) +#define BP_PXP_WFE_A_STAGE2_MUX11_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX11_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX11_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX11_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX11_MUX45 8 +#define BM_PXP_WFE_A_STAGE2_MUX11_MUX45 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX11_MUX45(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX11_MUX45) +#define BP_PXP_WFE_A_STAGE2_MUX11_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX11_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX11_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX11_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX11_MUX44 0 +#define BM_PXP_WFE_A_STAGE2_MUX11_MUX44 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX11_MUX44(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX11_MUX44) + +#define HW_PXP_WFE_A_STAGE2_MUX12 (0x00001820) +#define HW_PXP_WFE_A_STAGE2_MUX12_SET (0x00001824) +#define HW_PXP_WFE_A_STAGE2_MUX12_CLR (0x00001828) +#define HW_PXP_WFE_A_STAGE2_MUX12_TOG (0x0000182c) + +#define BP_PXP_WFE_A_STAGE2_MUX12_RSVD0 14 +#define BM_PXP_WFE_A_STAGE2_MUX12_RSVD0 0xFFFFC000 +#define BF_PXP_WFE_A_STAGE2_MUX12_RSVD0(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX12_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX12_MUX49 8 +#define BM_PXP_WFE_A_STAGE2_MUX12_MUX49 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX12_MUX49(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX12_MUX49) +#define BP_PXP_WFE_A_STAGE2_MUX12_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX12_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX12_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX12_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX12_MUX48 0 +#define BM_PXP_WFE_A_STAGE2_MUX12_MUX48 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX12_MUX48(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX12_MUX48) + +#define HW_PXP_WFE_A_STAGE3_MUX0 (0x00001830) +#define HW_PXP_WFE_A_STAGE3_MUX0_SET (0x00001834) +#define HW_PXP_WFE_A_STAGE3_MUX0_CLR (0x00001838) +#define HW_PXP_WFE_A_STAGE3_MUX0_TOG (0x0000183c) + +#define BP_PXP_WFE_A_STAGE3_MUX0_RSVD0 30 +#define BM_PXP_WFE_A_STAGE3_MUX0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE3_MUX0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE3_MUX0_RSVD0) +#define BP_PXP_WFE_A_STAGE3_MUX0_MUX3 24 +#define BM_PXP_WFE_A_STAGE3_MUX0_MUX3 0x3F000000 +#define BF_PXP_WFE_A_STAGE3_MUX0_MUX3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE3_MUX0_MUX3) +#define BP_PXP_WFE_A_STAGE3_MUX0_RSVD1 22 +#define BM_PXP_WFE_A_STAGE3_MUX0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE3_MUX0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE3_MUX0_RSVD1) +#define BP_PXP_WFE_A_STAGE3_MUX0_MUX2 16 +#define BM_PXP_WFE_A_STAGE3_MUX0_MUX2 0x003F0000 +#define BF_PXP_WFE_A_STAGE3_MUX0_MUX2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE3_MUX0_MUX2) +#define BP_PXP_WFE_A_STAGE3_MUX0_RSVD2 14 +#define BM_PXP_WFE_A_STAGE3_MUX0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE3_MUX0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE3_MUX0_RSVD2) +#define BP_PXP_WFE_A_STAGE3_MUX0_MUX1 8 +#define BM_PXP_WFE_A_STAGE3_MUX0_MUX1 0x00003F00 +#define BF_PXP_WFE_A_STAGE3_MUX0_MUX1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE3_MUX0_MUX1) +#define BP_PXP_WFE_A_STAGE3_MUX0_RSVD3 6 +#define BM_PXP_WFE_A_STAGE3_MUX0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE3_MUX0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE3_MUX0_RSVD3) +#define BP_PXP_WFE_A_STAGE3_MUX0_MUX0 0 +#define BM_PXP_WFE_A_STAGE3_MUX0_MUX0 0x0000003F +#define BF_PXP_WFE_A_STAGE3_MUX0_MUX0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE3_MUX0_MUX0) + +#define HW_PXP_WFE_A_STAGE3_MUX1 (0x00001840) +#define HW_PXP_WFE_A_STAGE3_MUX1_SET (0x00001844) +#define HW_PXP_WFE_A_STAGE3_MUX1_CLR (0x00001848) +#define HW_PXP_WFE_A_STAGE3_MUX1_TOG (0x0000184c) + +#define BP_PXP_WFE_A_STAGE3_MUX1_RSVD0 30 +#define BM_PXP_WFE_A_STAGE3_MUX1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE3_MUX1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE3_MUX1_RSVD0) +#define BP_PXP_WFE_A_STAGE3_MUX1_MUX7 24 +#define BM_PXP_WFE_A_STAGE3_MUX1_MUX7 0x3F000000 +#define BF_PXP_WFE_A_STAGE3_MUX1_MUX7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE3_MUX1_MUX7) +#define BP_PXP_WFE_A_STAGE3_MUX1_RSVD1 22 +#define BM_PXP_WFE_A_STAGE3_MUX1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE3_MUX1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE3_MUX1_RSVD1) +#define BP_PXP_WFE_A_STAGE3_MUX1_MUX6 16 +#define BM_PXP_WFE_A_STAGE3_MUX1_MUX6 0x003F0000 +#define BF_PXP_WFE_A_STAGE3_MUX1_MUX6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE3_MUX1_MUX6) +#define BP_PXP_WFE_A_STAGE3_MUX1_RSVD2 14 +#define BM_PXP_WFE_A_STAGE3_MUX1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE3_MUX1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE3_MUX1_RSVD2) +#define BP_PXP_WFE_A_STAGE3_MUX1_MUX5 8 +#define BM_PXP_WFE_A_STAGE3_MUX1_MUX5 0x00003F00 +#define BF_PXP_WFE_A_STAGE3_MUX1_MUX5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE3_MUX1_MUX5) +#define BP_PXP_WFE_A_STAGE3_MUX1_RSVD3 6 +#define BM_PXP_WFE_A_STAGE3_MUX1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE3_MUX1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE3_MUX1_RSVD3) +#define BP_PXP_WFE_A_STAGE3_MUX1_MUX4 0 +#define BM_PXP_WFE_A_STAGE3_MUX1_MUX4 0x0000003F +#define BF_PXP_WFE_A_STAGE3_MUX1_MUX4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE3_MUX1_MUX4) + +#define HW_PXP_WFE_A_STAGE3_MUX2 (0x00001850) +#define HW_PXP_WFE_A_STAGE3_MUX2_SET (0x00001854) +#define HW_PXP_WFE_A_STAGE3_MUX2_CLR (0x00001858) +#define HW_PXP_WFE_A_STAGE3_MUX2_TOG (0x0000185c) + +#define BP_PXP_WFE_A_STAGE3_MUX2_RSVD0 30 +#define BM_PXP_WFE_A_STAGE3_MUX2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE3_MUX2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE3_MUX2_RSVD0) +#define BP_PXP_WFE_A_STAGE3_MUX2_MUX11 24 +#define BM_PXP_WFE_A_STAGE3_MUX2_MUX11 0x3F000000 +#define BF_PXP_WFE_A_STAGE3_MUX2_MUX11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE3_MUX2_MUX11) +#define BP_PXP_WFE_A_STAGE3_MUX2_RSVD1 22 +#define BM_PXP_WFE_A_STAGE3_MUX2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE3_MUX2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE3_MUX2_RSVD1) +#define BP_PXP_WFE_A_STAGE3_MUX2_MUX10 16 +#define BM_PXP_WFE_A_STAGE3_MUX2_MUX10 0x003F0000 +#define BF_PXP_WFE_A_STAGE3_MUX2_MUX10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE3_MUX2_MUX10) +#define BP_PXP_WFE_A_STAGE3_MUX2_RSVD2 14 +#define BM_PXP_WFE_A_STAGE3_MUX2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE3_MUX2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE3_MUX2_RSVD2) +#define BP_PXP_WFE_A_STAGE3_MUX2_MUX9 8 +#define BM_PXP_WFE_A_STAGE3_MUX2_MUX9 0x00003F00 +#define BF_PXP_WFE_A_STAGE3_MUX2_MUX9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE3_MUX2_MUX9) +#define BP_PXP_WFE_A_STAGE3_MUX2_RSVD3 6 +#define BM_PXP_WFE_A_STAGE3_MUX2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE3_MUX2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE3_MUX2_RSVD3) +#define BP_PXP_WFE_A_STAGE3_MUX2_MUX8 0 +#define BM_PXP_WFE_A_STAGE3_MUX2_MUX8 0x0000003F +#define BF_PXP_WFE_A_STAGE3_MUX2_MUX8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE3_MUX2_MUX8) + +#define HW_PXP_WFE_A_STAGE3_MUX3 (0x00001860) +#define HW_PXP_WFE_A_STAGE3_MUX3_SET (0x00001864) +#define HW_PXP_WFE_A_STAGE3_MUX3_CLR (0x00001868) +#define HW_PXP_WFE_A_STAGE3_MUX3_TOG (0x0000186c) + +#define BP_PXP_WFE_A_STAGE3_MUX3_RSVD0 30 +#define BM_PXP_WFE_A_STAGE3_MUX3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE3_MUX3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE3_MUX3_RSVD0) +#define BP_PXP_WFE_A_STAGE3_MUX3_MUX15 24 +#define BM_PXP_WFE_A_STAGE3_MUX3_MUX15 0x3F000000 +#define BF_PXP_WFE_A_STAGE3_MUX3_MUX15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE3_MUX3_MUX15) +#define BP_PXP_WFE_A_STAGE3_MUX3_RSVD1 22 +#define BM_PXP_WFE_A_STAGE3_MUX3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE3_MUX3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE3_MUX3_RSVD1) +#define BP_PXP_WFE_A_STAGE3_MUX3_MUX14 16 +#define BM_PXP_WFE_A_STAGE3_MUX3_MUX14 0x003F0000 +#define BF_PXP_WFE_A_STAGE3_MUX3_MUX14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE3_MUX3_MUX14) +#define BP_PXP_WFE_A_STAGE3_MUX3_RSVD2 14 +#define BM_PXP_WFE_A_STAGE3_MUX3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE3_MUX3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE3_MUX3_RSVD2) +#define BP_PXP_WFE_A_STAGE3_MUX3_MUX13 8 +#define BM_PXP_WFE_A_STAGE3_MUX3_MUX13 0x00003F00 +#define BF_PXP_WFE_A_STAGE3_MUX3_MUX13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE3_MUX3_MUX13) +#define BP_PXP_WFE_A_STAGE3_MUX3_RSVD3 6 +#define BM_PXP_WFE_A_STAGE3_MUX3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE3_MUX3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE3_MUX3_RSVD3) +#define BP_PXP_WFE_A_STAGE3_MUX3_MUX12 0 +#define BM_PXP_WFE_A_STAGE3_MUX3_MUX12 0x0000003F +#define BF_PXP_WFE_A_STAGE3_MUX3_MUX12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE3_MUX3_MUX12) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_0 (0x00001870) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT31) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT30) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT29) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT28) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT27) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT26) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT25) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT24) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT23) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT22) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT21) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT20) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT19) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT18) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT17) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT16) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT15) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT14) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT13) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT12) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT11) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT10) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT9) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT8) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT7) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT6) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT5) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT4) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT3) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT2) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT1) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_1 (0x00001880) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT63) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT62) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT61) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT60) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT59) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT58) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT57) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT56) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT55) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT54) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT53) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT52) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT51) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT50) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT49) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT48) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT47) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT46) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT45) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT44) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT43) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT42) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT41) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT40) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT39) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT38) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT37) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT36) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT35) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT34) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT33) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT32) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_2 (0x00001890) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT95) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT94) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT93) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT92) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT91) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT90) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT89) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT88) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT87) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT86) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT85) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT84) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT83) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT82) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT81) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT80) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT79) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT78) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT77) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT76) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT75) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT74) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT73) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT72) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT71) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT70) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT69) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT68) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT67) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT66) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT65) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT64) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_3 (0x000018a0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT127) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT126) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT125) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT124) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT123) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT122) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT121) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT120) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT119) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT118) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT117) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT116) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT115) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT114) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT113) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT112) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT111) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT110) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT109) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT108) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT107) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT106) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT105) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT104) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT103) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT102) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT101) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT100) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT99) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT98) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT97) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT96) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_4 (0x000018b0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT159) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT158) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT157) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT156) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT155) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT154) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT153) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT152) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT151) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT150) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT149) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT148) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT147) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT146) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT145) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT144) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT143) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT142) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT141) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT140) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT139) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT138) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT137) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT136) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT135) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT134) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT133) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT132) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT131) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT130) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT129) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT128) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_5 (0x000018c0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT191) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT190) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT189) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT188) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT187) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT186) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT185) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT184) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT183) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT182) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT181) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT180) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT179) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT178) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT177) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT176) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT175) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT174) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT173) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT172) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT171) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT170) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT169) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT168) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT167) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT166) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT165) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT164) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT163) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT162) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT161) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT160) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_6 (0x000018d0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT223) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT222) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT221) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT220) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT219) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT218) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT217) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT216) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT215) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT214) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT213) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT212) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT211) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT210) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT209) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT208) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT207) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT206) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT205) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT204) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT203) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT202) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT201) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT200) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT199) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT198) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT197) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT196) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT195) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT194) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT193) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT192) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_7 (0x000018e0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT255) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT254) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT253) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT252) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT251) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT250) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT249) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT248) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT247) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT246) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT245) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT244) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT243) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT242) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT241) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT240) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT239) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT238) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT237) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT236) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT235) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT234) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT233) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT232) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT231) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT230) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT229) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT228) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT227) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT226) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT225) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT224) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_0 (0x000018f0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT31) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT30) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT29) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT28) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT27) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT26) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT25) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT24) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT23) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT22) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT21) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT20) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT19) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT18) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT17) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT16) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT15) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT14) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT13) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT12) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT11) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT10) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT9) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT8) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT7) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT6) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT5) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT4) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT3) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT2) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT1) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_1 (0x00001900) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT63) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT62) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT61) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT60) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT59) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT58) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT57) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT56) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT55) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT54) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT53) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT52) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT51) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT50) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT49) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT48) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT47) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT46) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT45) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT44) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT43) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT42) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT41) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT40) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT39) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT38) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT37) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT36) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT35) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT34) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT33) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT32) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_2 (0x00001910) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT95) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT94) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT93) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT92) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT91) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT90) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT89) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT88) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT87) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT86) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT85) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT84) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT83) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT82) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT81) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT80) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT79) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT78) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT77) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT76) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT75) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT74) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT73) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT72) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT71) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT70) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT69) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT68) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT67) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT66) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT65) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT64) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_3 (0x00001920) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT127) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT126) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT125) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT124) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT123) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT122) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT121) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT120) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT119) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT118) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT117) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT116) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT115) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT114) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT113) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT112) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT111) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT110) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT109) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT108) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT107) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT106) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT105) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT104) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT103) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT102) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT101) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT100) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT99) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT98) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT97) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT96) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_4 (0x00001930) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT159) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT158) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT157) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT156) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT155) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT154) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT153) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT152) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT151) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT150) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT149) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT148) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT147) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT146) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT145) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT144) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT143) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT142) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT141) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT140) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT139) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT138) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT137) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT136) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT135) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT134) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT133) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT132) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT131) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT130) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT129) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT128) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_5 (0x00001940) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT191) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT190) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT189) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT188) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT187) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT186) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT185) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT184) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT183) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT182) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT181) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT180) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT179) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT178) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT177) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT176) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT175) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT174) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT173) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT172) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT171) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT170) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT169) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT168) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT167) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT166) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT165) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT164) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT163) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT162) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT161) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT160) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_6 (0x00001950) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT223) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT222) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT221) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT220) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT219) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT218) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT217) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT216) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT215) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT214) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT213) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT212) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT211) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT210) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT209) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT208) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT207) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT206) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT205) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT204) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT203) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT202) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT201) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT200) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT199) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT198) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT197) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT196) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT195) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT194) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT193) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT192) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_7 (0x00001960) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT255) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT254) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT253) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT252) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT251) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT250) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT249) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT248) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT247) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT246) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT245) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT244) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT243) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT242) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT241) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT240) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT239) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT238) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT237) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT236) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT235) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT234) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT233) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT232) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT231) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT230) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT229) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT228) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT227) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT226) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT225) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT224) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_0 (0x00001970) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT31) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT30) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT29) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT28) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT27) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT26) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT25) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT24) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT23) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT22) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT21) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT20) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT19) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT18) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT17) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT16) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT15) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT14) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT13) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT12) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT11) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT10) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT9) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT8) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT7) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT6) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT5) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT4) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT3) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT2) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT1) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_1 (0x00001980) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT63) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT62) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT61) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT60) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT59) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT58) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT57) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT56) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT55) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT54) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT53) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT52) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT51) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT50) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT49) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT48) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT47) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT46) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT45) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT44) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT43) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT42) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT41) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT40) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT39) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT38) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT37) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT36) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT35) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT34) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT33) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT32) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_2 (0x00001990) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT95) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT94) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT93) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT92) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT91) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT90) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT89) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT88) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT87) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT86) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT85) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT84) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT83) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT82) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT81) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT80) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT79) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT78) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT77) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT76) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT75) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT74) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT73) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT72) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT71) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT70) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT69) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT68) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT67) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT66) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT65) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT64) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_3 (0x000019a0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT127) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT126) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT125) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT124) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT123) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT122) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT121) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT120) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT119) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT118) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT117) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT116) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT115) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT114) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT113) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT112) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT111) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT110) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT109) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT108) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT107) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT106) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT105) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT104) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT103) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT102) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT101) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT100) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT99) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT98) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT97) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT96) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_4 (0x000019b0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT159) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT158) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT157) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT156) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT155) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT154) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT153) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT152) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT151) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT150) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT149) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT148) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT147) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT146) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT145) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT144) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT143) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT142) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT141) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT140) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT139) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT138) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT137) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT136) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT135) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT134) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT133) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT132) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT131) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT130) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT129) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT128) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_5 (0x000019c0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT191) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT190) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT189) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT188) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT187) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT186) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT185) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT184) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT183) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT182) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT181) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT180) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT179) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT178) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT177) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT176) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT175) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT174) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT173) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT172) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT171) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT170) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT169) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT168) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT167) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT166) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT165) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT164) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT163) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT162) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT161) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT160) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_6 (0x000019d0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT223) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT222) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT221) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT220) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT219) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT218) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT217) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT216) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT215) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT214) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT213) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT212) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT211) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT210) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT209) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT208) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT207) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT206) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT205) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT204) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT203) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT202) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT201) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT200) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT199) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT198) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT197) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT196) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT195) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT194) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT193) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT192) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_7 (0x000019e0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT255) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT254) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT253) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT252) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT251) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT250) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT249) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT248) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT247) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT246) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT245) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT244) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT243) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT242) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT241) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT240) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT239) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT238) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT237) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT236) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT235) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT234) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT233) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT232) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT231) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT230) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT229) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT228) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT227) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT226) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT225) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT224) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_0 (0x000019f0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT31) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT30) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT29) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT28) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT27) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT26) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT25) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT24) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT23) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT22) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT21) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT20) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT19) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT18) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT17) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT16) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT15) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT14) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT13) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT12) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT11) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT10) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT9) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT8) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT7) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT6) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT5) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT4) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT3) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT2) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT1) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_1 (0x00001a00) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT63) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT62) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT61) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT60) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT59) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT58) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT57) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT56) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT55) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT54) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT53) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT52) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT51) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT50) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT49) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT48) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT47) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT46) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT45) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT44) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT43) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT42) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT41) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT40) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT39) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT38) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT37) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT36) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT35) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT34) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT33) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT32) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_2 (0x00001a10) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT95) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT94) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT93) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT92) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT91) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT90) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT89) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT88) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT87) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT86) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT85) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT84) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT83) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT82) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT81) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT80) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT79) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT78) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT77) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT76) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT75) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT74) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT73) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT72) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT71) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT70) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT69) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT68) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT67) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT66) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT65) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT64) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_3 (0x00001a20) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT127) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT126) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT125) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT124) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT123) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT122) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT121) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT120) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT119) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT118) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT117) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT116) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT115) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT114) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT113) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT112) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT111) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT110) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT109) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT108) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT107) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT106) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT105) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT104) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT103) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT102) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT101) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT100) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT99) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT98) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT97) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT96) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_4 (0x00001a30) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT159) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT158) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT157) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT156) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT155) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT154) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT153) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT152) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT151) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT150) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT149) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT148) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT147) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT146) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT145) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT144) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT143) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT142) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT141) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT140) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT139) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT138) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT137) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT136) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT135) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT134) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT133) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT132) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT131) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT130) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT129) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT128) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_5 (0x00001a40) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT191) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT190) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT189) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT188) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT187) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT186) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT185) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT184) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT183) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT182) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT181) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT180) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT179) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT178) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT177) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT176) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT175) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT174) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT173) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT172) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT171) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT170) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT169) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT168) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT167) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT166) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT165) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT164) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT163) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT162) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT161) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT160) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_6 (0x00001a50) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT223) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT222) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT221) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT220) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT219) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT218) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT217) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT216) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT215) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT214) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT213) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT212) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT211) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT210) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT209) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT208) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT207) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT206) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT205) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT204) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT203) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT202) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT201) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT200) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT199) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT198) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT197) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT196) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT195) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT194) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT193) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT192) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_7 (0x00001a60) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT255) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT254) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT253) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT252) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT251) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT250) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT249) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT248) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT247) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT246) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT245) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT244) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT243) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT242) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT241) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT240) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT239) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT238) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT237) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT236) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT235) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT234) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT233) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT232) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT231) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT230) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT229) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT228) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT227) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT226) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT225) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT224) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_0 (0x00001a70) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT3 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT2 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT1 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT0 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_1 (0x00001a80) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT7 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT7) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT6 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT6) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT5 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT5) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT4 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT4) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_2 (0x00001a90) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT11 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT11) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT10 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT10) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT9 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT9) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT8 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT8) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_3 (0x00001aa0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT15 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT15) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT14 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT14) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT13 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT13) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT12 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT12) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_4 (0x00001ab0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT19 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT19) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT18 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT18) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT17 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT17) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT16 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT16) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_5 (0x00001ac0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT23 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT23) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT22 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT22) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT21 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT21) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT20 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT20) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_6 (0x00001ad0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT27 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT27) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT26 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT26) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT25 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT25) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT24 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT24) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_7 (0x00001ae0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT31 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT31) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT30 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT30) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT29 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT29) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT28 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT28) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_0 (0x00001af0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT3 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT2 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT1 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT0 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_1 (0x00001b00) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT7 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT7) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT6 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT6) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT5 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT5) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT4 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT4) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_2 (0x00001b10) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT11 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT11) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT10 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT10) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT9 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT9) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT8 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT8) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_3 (0x00001b20) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT15 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT15) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT14 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT14) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT13 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT13) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT12 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT12) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_4 (0x00001b30) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT19 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT19) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT18 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT18) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT17 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT17) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT16 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT16) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_5 (0x00001b40) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT23 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT23) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT22 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT22) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT21 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT21) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT20 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT20) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_6 (0x00001b50) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT27 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT27) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT26 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT26) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT25 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT25) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT24 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT24) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_7 (0x00001b60) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT31 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT31) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT30 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT30) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT29 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT29) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT28 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT28) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_0 (0x00001b70) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT3 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT2 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT1 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT0 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_1 (0x00001b80) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT7 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT7) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT6 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT6) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT5 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT5) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT4 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT4) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_2 (0x00001b90) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT11 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT11) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT10 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT10) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT9 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT9) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT8 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT8) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_3 (0x00001ba0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT15 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT15) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT14 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT14) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT13 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT13) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT12 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT12) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_4 (0x00001bb0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT19 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT19) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT18 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT18) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT17 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT17) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT16 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT16) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_5 (0x00001bc0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT23 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT23) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT22 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT22) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT21 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT21) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT20 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT20) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_6 (0x00001bd0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT27 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT27) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT26 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT26) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT25 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT25) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT24 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT24) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_7 (0x00001be0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT31 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT31) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT30 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT30) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT29 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT29) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT28 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT28) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_0 (0x00001bf0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT3 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT2 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT1 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT0 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_1 (0x00001c00) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT7 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT7) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT6 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT6) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT5 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT5) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT4 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT4) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_2 (0x00001c10) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT11 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT11) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT10 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT10) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT9 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT9) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT8 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT8) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_3 (0x00001c20) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT15 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT15) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT14 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT14) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT13 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT13) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT12 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT12) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_4 (0x00001c30) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT19 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT19) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT18 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT18) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT17 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT17) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT16 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT16) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_5 (0x00001c40) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT23 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT23) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT22 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT22) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT21 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT21) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT20 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT20) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_6 (0x00001c50) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT27 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT27) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT26 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT26) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT25 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT25) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT24 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT24) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_7 (0x00001c60) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT31 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT31) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT30 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT30) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT29 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT29) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT28 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT28) + +#define HW_PXP_WFE_A_STAGE2_5X6_MASKS_0 (0x00001c70) + +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD0 29 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD0 0xE0000000 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD0(v) \ + (((v) << 29) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD0) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK3 24 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK3 0x1F000000 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK3) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD1 21 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD1 0x00E00000 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD1(v) \ + (((v) << 21) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD1) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK2 16 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK2 0x001F0000 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK2) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD2 13 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD2 0x0000E000 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD2(v) \ + (((v) << 13) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD2) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK1 8 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK1 0x00001F00 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK1) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD3 5 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD3 0x000000E0 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD3(v) \ + (((v) << 5) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD3) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK0 0 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK0 0x0000001F +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK0) + +#define HW_PXP_WFE_A_STAGE2_5X6_ADDR_0 (0x00001c80) + +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD0) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR3 24 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR3 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR3) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD1) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR2 16 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR2 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR2) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD2) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR1 8 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR1 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR1) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD3) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR0 0 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR0 0x0000003F +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR0) + +#define HW_PXP_WFE_A_STG2_5X1_OUT0 (0x00001c90) + +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT31) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT30) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT29) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT28) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT27) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT26) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT25) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT24) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT23) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT22) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT21) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT20) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT19) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT18) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT17) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT16) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT15) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT14) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT13) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT12) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT11) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT10) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT9) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT8) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT7) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT6) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT5) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT4) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT3) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT2) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT1) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X1_OUT1 (0x00001ca0) + +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT31) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT30) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT29) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT28) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT27) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT26) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT25) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT24) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT23) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT22) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT21) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT20) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT19) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT18) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT17) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT16) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT15) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT14) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT13) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT12) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT11) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT10) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT9) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT8) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT7) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT6) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT5) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT4) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT3) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT2) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT1) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X1_OUT2 (0x00001cb0) + +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT31) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT30) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT29) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT28) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT27) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT26) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT25) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT24) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT23) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT22) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT21) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT20) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT19) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT18) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT17) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT16) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT15) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT14) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT13) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT12) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT11) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT10) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT9) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT8) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT7) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT6) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT5) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT4) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT3) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT2) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT1) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X1_OUT3 (0x00001cc0) + +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT31) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT30) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT29) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT28) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT27) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT26) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT25) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT24) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT23) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT22) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT21) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT20) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT19) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT18) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT17) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT16) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT15) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT14) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT13) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT12) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT11) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT10) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT9) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT8) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT7) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT6) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT5) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT4) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT3) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT2) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT1) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X1_MASKS (0x00001cd0) + +#define BP_PXP_WFE_A_STG2_5X1_MASKS_RSVD3 29 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD3 0xE0000000 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_RSVD3(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD3) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_MASK3 24 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_MASK3 0x1F000000 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X1_MASKS_MASK3) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_RSVD2 21 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD2 0x00E00000 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_RSVD2(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD2) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_MASK2 16 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_MASK2 0x001F0000 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X1_MASKS_MASK2) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_RSVD1 13 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD1 0x0000E000 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_RSVD1(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD1) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_MASK1 8 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_MASK1 0x00001F00 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X1_MASKS_MASK1) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_RSVD0 5 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD0 0x000000E0 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_RSVD0(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD0) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_MASK0 0 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_MASK0 0x0000001F +#define BF_PXP_WFE_A_STG2_5X1_MASKS_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X1_MASKS_MASK0) + +#define HW_PXP_WFE_B_CTRL (0x00001d00) +#define HW_PXP_WFE_B_CTRL_SET (0x00001d04) +#define HW_PXP_WFE_B_CTRL_CLR (0x00001d08) +#define HW_PXP_WFE_B_CTRL_TOG (0x00001d0c) + +#define BM_PXP_WFE_B_CTRL_DONE 0x80000000 +#define BF_PXP_WFE_B_CTRL_DONE(v) \ + (((v) << 31) & BM_PXP_WFE_B_CTRL_DONE) +#define BP_PXP_WFE_B_CTRL_RSVD0 3 +#define BM_PXP_WFE_B_CTRL_RSVD0 0x7FFFFFF8 +#define BF_PXP_WFE_B_CTRL_RSVD0(v) \ + (((v) << 3) & BM_PXP_WFE_B_CTRL_RSVD0) +#define BM_PXP_WFE_B_CTRL_SW_RESET 0x00000004 +#define BF_PXP_WFE_B_CTRL_SW_RESET(v) \ + (((v) << 2) & BM_PXP_WFE_B_CTRL_SW_RESET) +#define BM_PXP_WFE_B_CTRL_RSVD1 0x00000002 +#define BF_PXP_WFE_B_CTRL_RSVD1(v) \ + (((v) << 1) & BM_PXP_WFE_B_CTRL_RSVD1) +#define BM_PXP_WFE_B_CTRL_ENABLE 0x00000001 +#define BF_PXP_WFE_B_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_WFE_B_CTRL_ENABLE) +#define BV_PXP_WFE_B_CTRL_ENABLE__0 0x0 +#define BV_PXP_WFE_B_CTRL_ENABLE__1 0x1 + +#define HW_PXP_WFE_B_DIMENSIONS (0x00001d10) + +#define BP_PXP_WFE_B_DIMENSIONS_RSVD0 28 +#define BM_PXP_WFE_B_DIMENSIONS_RSVD0 0xF0000000 +#define BF_PXP_WFE_B_DIMENSIONS_RSVD0(v) \ + (((v) << 28) & BM_PXP_WFE_B_DIMENSIONS_RSVD0) +#define BP_PXP_WFE_B_DIMENSIONS_HEIGHT 16 +#define BM_PXP_WFE_B_DIMENSIONS_HEIGHT 0x0FFF0000 +#define BF_PXP_WFE_B_DIMENSIONS_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFE_B_DIMENSIONS_HEIGHT) +#define BP_PXP_WFE_B_DIMENSIONS_RSVD1 12 +#define BM_PXP_WFE_B_DIMENSIONS_RSVD1 0x0000F000 +#define BF_PXP_WFE_B_DIMENSIONS_RSVD1(v) \ + (((v) << 12) & BM_PXP_WFE_B_DIMENSIONS_RSVD1) +#define BP_PXP_WFE_B_DIMENSIONS_WIDTH 0 +#define BM_PXP_WFE_B_DIMENSIONS_WIDTH 0x00000FFF +#define BF_PXP_WFE_B_DIMENSIONS_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFE_B_DIMENSIONS_WIDTH) + +#define HW_PXP_WFE_B_OFFSET (0x00001d20) + +#define BP_PXP_WFE_B_OFFSET_RSVD0 28 +#define BM_PXP_WFE_B_OFFSET_RSVD0 0xF0000000 +#define BF_PXP_WFE_B_OFFSET_RSVD0(v) \ + (((v) << 28) & BM_PXP_WFE_B_OFFSET_RSVD0) +#define BP_PXP_WFE_B_OFFSET_Y_OFFSET 16 +#define BM_PXP_WFE_B_OFFSET_Y_OFFSET 0x0FFF0000 +#define BF_PXP_WFE_B_OFFSET_Y_OFFSET(v) \ + (((v) << 16) & BM_PXP_WFE_B_OFFSET_Y_OFFSET) +#define BP_PXP_WFE_B_OFFSET_RSVD1 12 +#define BM_PXP_WFE_B_OFFSET_RSVD1 0x0000F000 +#define BF_PXP_WFE_B_OFFSET_RSVD1(v) \ + (((v) << 12) & BM_PXP_WFE_B_OFFSET_RSVD1) +#define BP_PXP_WFE_B_OFFSET_X_OFFSET 0 +#define BM_PXP_WFE_B_OFFSET_X_OFFSET 0x00000FFF +#define BF_PXP_WFE_B_OFFSET_X_OFFSET(v) \ + (((v) << 0) & BM_PXP_WFE_B_OFFSET_X_OFFSET) + +#define HW_PXP_WFE_B_SW_DATA_REGS (0x00001d30) + +#define BP_PXP_WFE_B_SW_DATA_REGS_VAL3 24 +#define BM_PXP_WFE_B_SW_DATA_REGS_VAL3 0xFF000000 +#define BF_PXP_WFE_B_SW_DATA_REGS_VAL3(v) \ + (((v) << 24) & BM_PXP_WFE_B_SW_DATA_REGS_VAL3) +#define BP_PXP_WFE_B_SW_DATA_REGS_VAL2 16 +#define BM_PXP_WFE_B_SW_DATA_REGS_VAL2 0x00FF0000 +#define BF_PXP_WFE_B_SW_DATA_REGS_VAL2(v) \ + (((v) << 16) & BM_PXP_WFE_B_SW_DATA_REGS_VAL2) +#define BP_PXP_WFE_B_SW_DATA_REGS_VAL1 8 +#define BM_PXP_WFE_B_SW_DATA_REGS_VAL1 0x0000FF00 +#define BF_PXP_WFE_B_SW_DATA_REGS_VAL1(v) \ + (((v) << 8) & BM_PXP_WFE_B_SW_DATA_REGS_VAL1) +#define BP_PXP_WFE_B_SW_DATA_REGS_VAL0 0 +#define BM_PXP_WFE_B_SW_DATA_REGS_VAL0 0x000000FF +#define BF_PXP_WFE_B_SW_DATA_REGS_VAL0(v) \ + (((v) << 0) & BM_PXP_WFE_B_SW_DATA_REGS_VAL0) + +#define HW_PXP_WFE_B_SW_FLAG_REGS (0x00001d40) + +#define BP_PXP_WFE_B_SW_FLAG_REGS_RSVD 4 +#define BM_PXP_WFE_B_SW_FLAG_REGS_RSVD 0xFFFFFFF0 +#define BF_PXP_WFE_B_SW_FLAG_REGS_RSVD(v) \ + (((v) << 4) & BM_PXP_WFE_B_SW_FLAG_REGS_RSVD) +#define BM_PXP_WFE_B_SW_FLAG_REGS_VAL3 0x00000008 +#define BF_PXP_WFE_B_SW_FLAG_REGS_VAL3(v) \ + (((v) << 3) & BM_PXP_WFE_B_SW_FLAG_REGS_VAL3) +#define BM_PXP_WFE_B_SW_FLAG_REGS_VAL2 0x00000004 +#define BF_PXP_WFE_B_SW_FLAG_REGS_VAL2(v) \ + (((v) << 2) & BM_PXP_WFE_B_SW_FLAG_REGS_VAL2) +#define BM_PXP_WFE_B_SW_FLAG_REGS_VAL1 0x00000002 +#define BF_PXP_WFE_B_SW_FLAG_REGS_VAL1(v) \ + (((v) << 1) & BM_PXP_WFE_B_SW_FLAG_REGS_VAL1) +#define BM_PXP_WFE_B_SW_FLAG_REGS_VAL0 0x00000001 +#define BF_PXP_WFE_B_SW_FLAG_REGS_VAL0(v) \ + (((v) << 0) & BM_PXP_WFE_B_SW_FLAG_REGS_VAL0) + +#define HW_PXP_WFE_B_STAGE1_MUX0 (0x00001d50) +#define HW_PXP_WFE_B_STAGE1_MUX0_SET (0x00001d54) +#define HW_PXP_WFE_B_STAGE1_MUX0_CLR (0x00001d58) +#define HW_PXP_WFE_B_STAGE1_MUX0_TOG (0x00001d5c) + +#define BP_PXP_WFE_B_STAGE1_MUX0_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX0_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX0_MUX3 24 +#define BM_PXP_WFE_B_STAGE1_MUX0_MUX3 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX0_MUX3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX0_MUX3) +#define BP_PXP_WFE_B_STAGE1_MUX0_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX0_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX0_MUX2 16 +#define BM_PXP_WFE_B_STAGE1_MUX0_MUX2 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX0_MUX2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX0_MUX2) +#define BP_PXP_WFE_B_STAGE1_MUX0_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX0_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX0_MUX1 8 +#define BM_PXP_WFE_B_STAGE1_MUX0_MUX1 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX0_MUX1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX0_MUX1) +#define BP_PXP_WFE_B_STAGE1_MUX0_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX0_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX0_MUX0 0 +#define BM_PXP_WFE_B_STAGE1_MUX0_MUX0 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX0_MUX0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX0_MUX0) + +#define HW_PXP_WFE_B_STAGE1_MUX1 (0x00001d60) +#define HW_PXP_WFE_B_STAGE1_MUX1_SET (0x00001d64) +#define HW_PXP_WFE_B_STAGE1_MUX1_CLR (0x00001d68) +#define HW_PXP_WFE_B_STAGE1_MUX1_TOG (0x00001d6c) + +#define BP_PXP_WFE_B_STAGE1_MUX1_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX1_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX1_MUX7 24 +#define BM_PXP_WFE_B_STAGE1_MUX1_MUX7 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX1_MUX7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX1_MUX7) +#define BP_PXP_WFE_B_STAGE1_MUX1_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX1_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX1_MUX6 16 +#define BM_PXP_WFE_B_STAGE1_MUX1_MUX6 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX1_MUX6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX1_MUX6) +#define BP_PXP_WFE_B_STAGE1_MUX1_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX1_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX1_MUX5 8 +#define BM_PXP_WFE_B_STAGE1_MUX1_MUX5 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX1_MUX5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX1_MUX5) +#define BP_PXP_WFE_B_STAGE1_MUX1_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX1_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX1_MUX4 0 +#define BM_PXP_WFE_B_STAGE1_MUX1_MUX4 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX1_MUX4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX1_MUX4) + +#define HW_PXP_WFE_B_STAGE1_MUX2 (0x00001d70) +#define HW_PXP_WFE_B_STAGE1_MUX2_SET (0x00001d74) +#define HW_PXP_WFE_B_STAGE1_MUX2_CLR (0x00001d78) +#define HW_PXP_WFE_B_STAGE1_MUX2_TOG (0x00001d7c) + +#define BP_PXP_WFE_B_STAGE1_MUX2_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX2_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX2_MUX11 24 +#define BM_PXP_WFE_B_STAGE1_MUX2_MUX11 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX2_MUX11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX2_MUX11) +#define BP_PXP_WFE_B_STAGE1_MUX2_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX2_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX2_MUX10 16 +#define BM_PXP_WFE_B_STAGE1_MUX2_MUX10 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX2_MUX10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX2_MUX10) +#define BP_PXP_WFE_B_STAGE1_MUX2_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX2_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX2_MUX9 8 +#define BM_PXP_WFE_B_STAGE1_MUX2_MUX9 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX2_MUX9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX2_MUX9) +#define BP_PXP_WFE_B_STAGE1_MUX2_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX2_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX2_MUX8 0 +#define BM_PXP_WFE_B_STAGE1_MUX2_MUX8 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX2_MUX8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX2_MUX8) + +#define HW_PXP_WFE_B_STAGE1_MUX3 (0x00001d80) +#define HW_PXP_WFE_B_STAGE1_MUX3_SET (0x00001d84) +#define HW_PXP_WFE_B_STAGE1_MUX3_CLR (0x00001d88) +#define HW_PXP_WFE_B_STAGE1_MUX3_TOG (0x00001d8c) + +#define BP_PXP_WFE_B_STAGE1_MUX3_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX3_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX3_MUX15 24 +#define BM_PXP_WFE_B_STAGE1_MUX3_MUX15 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX3_MUX15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX3_MUX15) +#define BP_PXP_WFE_B_STAGE1_MUX3_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX3_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX3_MUX14 16 +#define BM_PXP_WFE_B_STAGE1_MUX3_MUX14 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX3_MUX14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX3_MUX14) +#define BP_PXP_WFE_B_STAGE1_MUX3_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX3_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX3_MUX13 8 +#define BM_PXP_WFE_B_STAGE1_MUX3_MUX13 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX3_MUX13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX3_MUX13) +#define BP_PXP_WFE_B_STAGE1_MUX3_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX3_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX3_MUX12 0 +#define BM_PXP_WFE_B_STAGE1_MUX3_MUX12 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX3_MUX12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX3_MUX12) + +#define HW_PXP_WFE_B_STAGE1_MUX4 (0x00001d90) +#define HW_PXP_WFE_B_STAGE1_MUX4_SET (0x00001d94) +#define HW_PXP_WFE_B_STAGE1_MUX4_CLR (0x00001d98) +#define HW_PXP_WFE_B_STAGE1_MUX4_TOG (0x00001d9c) + +#define BP_PXP_WFE_B_STAGE1_MUX4_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX4_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX4_MUX19 24 +#define BM_PXP_WFE_B_STAGE1_MUX4_MUX19 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX4_MUX19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX4_MUX19) +#define BP_PXP_WFE_B_STAGE1_MUX4_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX4_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX4_MUX18 16 +#define BM_PXP_WFE_B_STAGE1_MUX4_MUX18 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX4_MUX18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX4_MUX18) +#define BP_PXP_WFE_B_STAGE1_MUX4_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX4_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX4_MUX17 8 +#define BM_PXP_WFE_B_STAGE1_MUX4_MUX17 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX4_MUX17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX4_MUX17) +#define BP_PXP_WFE_B_STAGE1_MUX4_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX4_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX4_MUX16 0 +#define BM_PXP_WFE_B_STAGE1_MUX4_MUX16 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX4_MUX16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX4_MUX16) + +#define HW_PXP_WFE_B_STAGE1_MUX5 (0x00001da0) +#define HW_PXP_WFE_B_STAGE1_MUX5_SET (0x00001da4) +#define HW_PXP_WFE_B_STAGE1_MUX5_CLR (0x00001da8) +#define HW_PXP_WFE_B_STAGE1_MUX5_TOG (0x00001dac) + +#define BP_PXP_WFE_B_STAGE1_MUX5_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX5_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX5_MUX23 24 +#define BM_PXP_WFE_B_STAGE1_MUX5_MUX23 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX5_MUX23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX5_MUX23) +#define BP_PXP_WFE_B_STAGE1_MUX5_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX5_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX5_MUX22 16 +#define BM_PXP_WFE_B_STAGE1_MUX5_MUX22 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX5_MUX22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX5_MUX22) +#define BP_PXP_WFE_B_STAGE1_MUX5_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX5_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX5_MUX21 8 +#define BM_PXP_WFE_B_STAGE1_MUX5_MUX21 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX5_MUX21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX5_MUX21) +#define BP_PXP_WFE_B_STAGE1_MUX5_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX5_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX5_MUX20 0 +#define BM_PXP_WFE_B_STAGE1_MUX5_MUX20 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX5_MUX20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX5_MUX20) +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__INC 0x0 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__DEC 0x1 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__ADD 0x2 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__MINUS 0x3 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__AND 0x4 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__OR 0x5 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__XOR 0x6 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__SHIFTLEFT 0x7 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__SHIFTRIGHT 0x8 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__BIT_AND 0x9 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__BIT_OR 0xa +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__BIT_CMP 0xb +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__NOP 0xc + +#define HW_PXP_WFE_B_STAGE1_MUX6 (0x00001db0) +#define HW_PXP_WFE_B_STAGE1_MUX6_SET (0x00001db4) +#define HW_PXP_WFE_B_STAGE1_MUX6_CLR (0x00001db8) +#define HW_PXP_WFE_B_STAGE1_MUX6_TOG (0x00001dbc) + +#define BP_PXP_WFE_B_STAGE1_MUX6_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX6_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX6_MUX27 24 +#define BM_PXP_WFE_B_STAGE1_MUX6_MUX27 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX6_MUX27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX6_MUX27) +#define BP_PXP_WFE_B_STAGE1_MUX6_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX6_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX6_MUX26 16 +#define BM_PXP_WFE_B_STAGE1_MUX6_MUX26 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX6_MUX26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX6_MUX26) +#define BP_PXP_WFE_B_STAGE1_MUX6_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX6_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX6_MUX25 8 +#define BM_PXP_WFE_B_STAGE1_MUX6_MUX25 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX6_MUX25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX6_MUX25) +#define BP_PXP_WFE_B_STAGE1_MUX6_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX6_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX6_MUX24 0 +#define BM_PXP_WFE_B_STAGE1_MUX6_MUX24 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX6_MUX24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX6_MUX24) + +#define HW_PXP_WFE_B_STAGE1_MUX7 (0x00001dc0) +#define HW_PXP_WFE_B_STAGE1_MUX7_SET (0x00001dc4) +#define HW_PXP_WFE_B_STAGE1_MUX7_CLR (0x00001dc8) +#define HW_PXP_WFE_B_STAGE1_MUX7_TOG (0x00001dcc) + +#define BP_PXP_WFE_B_STAGE1_MUX7_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX7_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX7_MUX31 24 +#define BM_PXP_WFE_B_STAGE1_MUX7_MUX31 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX7_MUX31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX7_MUX31) +#define BP_PXP_WFE_B_STAGE1_MUX7_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX7_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX7_MUX30 16 +#define BM_PXP_WFE_B_STAGE1_MUX7_MUX30 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX7_MUX30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX7_MUX30) +#define BP_PXP_WFE_B_STAGE1_MUX7_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX7_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX7_MUX29 8 +#define BM_PXP_WFE_B_STAGE1_MUX7_MUX29 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX7_MUX29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX7_MUX29) +#define BP_PXP_WFE_B_STAGE1_MUX7_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX7_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX7_MUX28 0 +#define BM_PXP_WFE_B_STAGE1_MUX7_MUX28 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX7_MUX28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX7_MUX28) + +#define HW_PXP_WFE_B_STAGE1_MUX8 (0x00001dd0) +#define HW_PXP_WFE_B_STAGE1_MUX8_SET (0x00001dd4) +#define HW_PXP_WFE_B_STAGE1_MUX8_CLR (0x00001dd8) +#define HW_PXP_WFE_B_STAGE1_MUX8_TOG (0x00001ddc) + +#define BP_PXP_WFE_B_STAGE1_MUX8_RSVD0 6 +#define BM_PXP_WFE_B_STAGE1_MUX8_RSVD0 0xFFFFFFC0 +#define BF_PXP_WFE_B_STAGE1_MUX8_RSVD0(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX8_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX8_MUX32 0 +#define BM_PXP_WFE_B_STAGE1_MUX8_MUX32 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX8_MUX32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX8_MUX32) + +#define HW_PXP_WFE_B_STAGE2_MUX0 (0x00001de0) +#define HW_PXP_WFE_B_STAGE2_MUX0_SET (0x00001de4) +#define HW_PXP_WFE_B_STAGE2_MUX0_CLR (0x00001de8) +#define HW_PXP_WFE_B_STAGE2_MUX0_TOG (0x00001dec) + +#define BP_PXP_WFE_B_STAGE2_MUX0_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX0_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX0_MUX3 24 +#define BM_PXP_WFE_B_STAGE2_MUX0_MUX3 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX0_MUX3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX0_MUX3) +#define BP_PXP_WFE_B_STAGE2_MUX0_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX0_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX0_MUX2 16 +#define BM_PXP_WFE_B_STAGE2_MUX0_MUX2 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX0_MUX2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX0_MUX2) +#define BP_PXP_WFE_B_STAGE2_MUX0_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX0_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX0_MUX1 8 +#define BM_PXP_WFE_B_STAGE2_MUX0_MUX1 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX0_MUX1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX0_MUX1) +#define BP_PXP_WFE_B_STAGE2_MUX0_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX0_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX0_MUX0 0 +#define BM_PXP_WFE_B_STAGE2_MUX0_MUX0 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX0_MUX0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX0_MUX0) + +#define HW_PXP_WFE_B_STAGE2_MUX1 (0x00001df0) +#define HW_PXP_WFE_B_STAGE2_MUX1_SET (0x00001df4) +#define HW_PXP_WFE_B_STAGE2_MUX1_CLR (0x00001df8) +#define HW_PXP_WFE_B_STAGE2_MUX1_TOG (0x00001dfc) + +#define BP_PXP_WFE_B_STAGE2_MUX1_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX1_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX1_MUX7 24 +#define BM_PXP_WFE_B_STAGE2_MUX1_MUX7 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX1_MUX7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX1_MUX7) +#define BP_PXP_WFE_B_STAGE2_MUX1_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX1_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX1_MUX6 16 +#define BM_PXP_WFE_B_STAGE2_MUX1_MUX6 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX1_MUX6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX1_MUX6) +#define BP_PXP_WFE_B_STAGE2_MUX1_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX1_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX1_MUX5 8 +#define BM_PXP_WFE_B_STAGE2_MUX1_MUX5 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX1_MUX5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX1_MUX5) +#define BP_PXP_WFE_B_STAGE2_MUX1_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX1_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX1_MUX4 0 +#define BM_PXP_WFE_B_STAGE2_MUX1_MUX4 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX1_MUX4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX1_MUX4) + +#define HW_PXP_WFE_B_STAGE2_MUX2 (0x00001e00) +#define HW_PXP_WFE_B_STAGE2_MUX2_SET (0x00001e04) +#define HW_PXP_WFE_B_STAGE2_MUX2_CLR (0x00001e08) +#define HW_PXP_WFE_B_STAGE2_MUX2_TOG (0x00001e0c) + +#define BP_PXP_WFE_B_STAGE2_MUX2_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX2_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX2_MUX11 24 +#define BM_PXP_WFE_B_STAGE2_MUX2_MUX11 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX2_MUX11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX2_MUX11) +#define BP_PXP_WFE_B_STAGE2_MUX2_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX2_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX2_MUX10 16 +#define BM_PXP_WFE_B_STAGE2_MUX2_MUX10 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX2_MUX10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX2_MUX10) +#define BP_PXP_WFE_B_STAGE2_MUX2_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX2_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX2_MUX9 8 +#define BM_PXP_WFE_B_STAGE2_MUX2_MUX9 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX2_MUX9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX2_MUX9) +#define BP_PXP_WFE_B_STAGE2_MUX2_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX2_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX2_MUX8 0 +#define BM_PXP_WFE_B_STAGE2_MUX2_MUX8 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX2_MUX8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX2_MUX8) + +#define HW_PXP_WFE_B_STAGE2_MUX3 (0x00001e10) +#define HW_PXP_WFE_B_STAGE2_MUX3_SET (0x00001e14) +#define HW_PXP_WFE_B_STAGE2_MUX3_CLR (0x00001e18) +#define HW_PXP_WFE_B_STAGE2_MUX3_TOG (0x00001e1c) + +#define BP_PXP_WFE_B_STAGE2_MUX3_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX3_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX3_MUX15 24 +#define BM_PXP_WFE_B_STAGE2_MUX3_MUX15 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX3_MUX15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX3_MUX15) +#define BP_PXP_WFE_B_STAGE2_MUX3_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX3_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX3_MUX14 16 +#define BM_PXP_WFE_B_STAGE2_MUX3_MUX14 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX3_MUX14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX3_MUX14) +#define BP_PXP_WFE_B_STAGE2_MUX3_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX3_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX3_MUX13 8 +#define BM_PXP_WFE_B_STAGE2_MUX3_MUX13 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX3_MUX13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX3_MUX13) +#define BP_PXP_WFE_B_STAGE2_MUX3_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX3_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX3_MUX12 0 +#define BM_PXP_WFE_B_STAGE2_MUX3_MUX12 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX3_MUX12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX3_MUX12) + +#define HW_PXP_WFE_B_STAGE2_MUX4 (0x00001e20) +#define HW_PXP_WFE_B_STAGE2_MUX4_SET (0x00001e24) +#define HW_PXP_WFE_B_STAGE2_MUX4_CLR (0x00001e28) +#define HW_PXP_WFE_B_STAGE2_MUX4_TOG (0x00001e2c) + +#define BP_PXP_WFE_B_STAGE2_MUX4_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX4_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX4_MUX19 24 +#define BM_PXP_WFE_B_STAGE2_MUX4_MUX19 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX4_MUX19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX4_MUX19) +#define BP_PXP_WFE_B_STAGE2_MUX4_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX4_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX4_MUX18 16 +#define BM_PXP_WFE_B_STAGE2_MUX4_MUX18 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX4_MUX18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX4_MUX18) +#define BP_PXP_WFE_B_STAGE2_MUX4_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX4_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX4_MUX17 8 +#define BM_PXP_WFE_B_STAGE2_MUX4_MUX17 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX4_MUX17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX4_MUX17) +#define BP_PXP_WFE_B_STAGE2_MUX4_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX4_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX4_MUX16 0 +#define BM_PXP_WFE_B_STAGE2_MUX4_MUX16 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX4_MUX16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX4_MUX16) + +#define HW_PXP_WFE_B_STAGE2_MUX5 (0x00001e30) +#define HW_PXP_WFE_B_STAGE2_MUX5_SET (0x00001e34) +#define HW_PXP_WFE_B_STAGE2_MUX5_CLR (0x00001e38) +#define HW_PXP_WFE_B_STAGE2_MUX5_TOG (0x00001e3c) + +#define BP_PXP_WFE_B_STAGE2_MUX5_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX5_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX5_MUX23 24 +#define BM_PXP_WFE_B_STAGE2_MUX5_MUX23 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX5_MUX23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX5_MUX23) +#define BP_PXP_WFE_B_STAGE2_MUX5_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX5_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX5_MUX22 16 +#define BM_PXP_WFE_B_STAGE2_MUX5_MUX22 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX5_MUX22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX5_MUX22) +#define BP_PXP_WFE_B_STAGE2_MUX5_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX5_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX5_MUX21 8 +#define BM_PXP_WFE_B_STAGE2_MUX5_MUX21 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX5_MUX21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX5_MUX21) +#define BP_PXP_WFE_B_STAGE2_MUX5_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX5_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX5_MUX20 0 +#define BM_PXP_WFE_B_STAGE2_MUX5_MUX20 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX5_MUX20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX5_MUX20) + +#define HW_PXP_WFE_B_STAGE2_MUX6 (0x00001e40) +#define HW_PXP_WFE_B_STAGE2_MUX6_SET (0x00001e44) +#define HW_PXP_WFE_B_STAGE2_MUX6_CLR (0x00001e48) +#define HW_PXP_WFE_B_STAGE2_MUX6_TOG (0x00001e4c) + +#define BP_PXP_WFE_B_STAGE2_MUX6_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX6_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX6_MUX27 24 +#define BM_PXP_WFE_B_STAGE2_MUX6_MUX27 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX6_MUX27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX6_MUX27) +#define BP_PXP_WFE_B_STAGE2_MUX6_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX6_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX6_MUX26 16 +#define BM_PXP_WFE_B_STAGE2_MUX6_MUX26 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX6_MUX26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX6_MUX26) +#define BP_PXP_WFE_B_STAGE2_MUX6_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX6_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX6_MUX25 8 +#define BM_PXP_WFE_B_STAGE2_MUX6_MUX25 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX6_MUX25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX6_MUX25) +#define BP_PXP_WFE_B_STAGE2_MUX6_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX6_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX6_MUX24 0 +#define BM_PXP_WFE_B_STAGE2_MUX6_MUX24 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX6_MUX24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX6_MUX24) + +#define HW_PXP_WFE_B_STAGE2_MUX7 (0x00001e50) +#define HW_PXP_WFE_B_STAGE2_MUX7_SET (0x00001e54) +#define HW_PXP_WFE_B_STAGE2_MUX7_CLR (0x00001e58) +#define HW_PXP_WFE_B_STAGE2_MUX7_TOG (0x00001e5c) + +#define BP_PXP_WFE_B_STAGE2_MUX7_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX7_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX7_MUX31 24 +#define BM_PXP_WFE_B_STAGE2_MUX7_MUX31 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX7_MUX31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX7_MUX31) +#define BP_PXP_WFE_B_STAGE2_MUX7_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX7_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX7_MUX30 16 +#define BM_PXP_WFE_B_STAGE2_MUX7_MUX30 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX7_MUX30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX7_MUX30) +#define BP_PXP_WFE_B_STAGE2_MUX7_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX7_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX7_MUX29 8 +#define BM_PXP_WFE_B_STAGE2_MUX7_MUX29 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX7_MUX29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX7_MUX29) +#define BP_PXP_WFE_B_STAGE2_MUX7_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX7_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX7_MUX28 0 +#define BM_PXP_WFE_B_STAGE2_MUX7_MUX28 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX7_MUX28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX7_MUX28) + +#define HW_PXP_WFE_B_STAGE2_MUX8 (0x00001e60) +#define HW_PXP_WFE_B_STAGE2_MUX8_SET (0x00001e64) +#define HW_PXP_WFE_B_STAGE2_MUX8_CLR (0x00001e68) +#define HW_PXP_WFE_B_STAGE2_MUX8_TOG (0x00001e6c) + +#define BP_PXP_WFE_B_STAGE2_MUX8_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX8_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX8_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX8_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX8_MUX35 24 +#define BM_PXP_WFE_B_STAGE2_MUX8_MUX35 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX8_MUX35(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX8_MUX35) +#define BP_PXP_WFE_B_STAGE2_MUX8_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX8_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX8_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX8_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX8_MUX34 16 +#define BM_PXP_WFE_B_STAGE2_MUX8_MUX34 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX8_MUX34(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX8_MUX34) +#define BP_PXP_WFE_B_STAGE2_MUX8_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX8_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX8_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX8_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX8_MUX33 8 +#define BM_PXP_WFE_B_STAGE2_MUX8_MUX33 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX8_MUX33(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX8_MUX33) +#define BP_PXP_WFE_B_STAGE2_MUX8_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX8_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX8_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX8_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX8_MUX32 0 +#define BM_PXP_WFE_B_STAGE2_MUX8_MUX32 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX8_MUX32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX8_MUX32) + +#define HW_PXP_WFE_B_STAGE2_MUX9 (0x00001e70) +#define HW_PXP_WFE_B_STAGE2_MUX9_SET (0x00001e74) +#define HW_PXP_WFE_B_STAGE2_MUX9_CLR (0x00001e78) +#define HW_PXP_WFE_B_STAGE2_MUX9_TOG (0x00001e7c) + +#define BP_PXP_WFE_B_STAGE2_MUX9_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX9_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX9_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX9_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX9_MUX39 24 +#define BM_PXP_WFE_B_STAGE2_MUX9_MUX39 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX9_MUX39(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX9_MUX39) +#define BP_PXP_WFE_B_STAGE2_MUX9_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX9_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX9_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX9_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX9_MUX38 16 +#define BM_PXP_WFE_B_STAGE2_MUX9_MUX38 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX9_MUX38(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX9_MUX38) +#define BP_PXP_WFE_B_STAGE2_MUX9_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX9_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX9_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX9_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX9_MUX37 8 +#define BM_PXP_WFE_B_STAGE2_MUX9_MUX37 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX9_MUX37(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX9_MUX37) +#define BP_PXP_WFE_B_STAGE2_MUX9_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX9_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX9_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX9_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX9_MUX36 0 +#define BM_PXP_WFE_B_STAGE2_MUX9_MUX36 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX9_MUX36(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX9_MUX36) + +#define HW_PXP_WFE_B_STAGE2_MUX10 (0x00001e80) +#define HW_PXP_WFE_B_STAGE2_MUX10_SET (0x00001e84) +#define HW_PXP_WFE_B_STAGE2_MUX10_CLR (0x00001e88) +#define HW_PXP_WFE_B_STAGE2_MUX10_TOG (0x00001e8c) + +#define BP_PXP_WFE_B_STAGE2_MUX10_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX10_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX10_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX10_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX10_MUX43 24 +#define BM_PXP_WFE_B_STAGE2_MUX10_MUX43 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX10_MUX43(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX10_MUX43) +#define BP_PXP_WFE_B_STAGE2_MUX10_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX10_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX10_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX10_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX10_MUX42 16 +#define BM_PXP_WFE_B_STAGE2_MUX10_MUX42 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX10_MUX42(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX10_MUX42) +#define BP_PXP_WFE_B_STAGE2_MUX10_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX10_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX10_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX10_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX10_MUX41 8 +#define BM_PXP_WFE_B_STAGE2_MUX10_MUX41 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX10_MUX41(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX10_MUX41) +#define BP_PXP_WFE_B_STAGE2_MUX10_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX10_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX10_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX10_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX10_MUX40 0 +#define BM_PXP_WFE_B_STAGE2_MUX10_MUX40 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX10_MUX40(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX10_MUX40) +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__INC 0x0 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__DEC 0x1 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__ADD 0x2 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__MINUS 0x3 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__AND 0x4 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__OR 0x5 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__XOR 0x6 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__SHIFTLEFT 0x7 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__SHIFTRIGHT 0x8 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__BIT_AND 0x9 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__BIT_OR 0xa +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__BIT_CMP 0xb +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__NOP 0xc + +#define HW_PXP_WFE_B_STAGE2_MUX11 (0x00001e90) +#define HW_PXP_WFE_B_STAGE2_MUX11_SET (0x00001e94) +#define HW_PXP_WFE_B_STAGE2_MUX11_CLR (0x00001e98) +#define HW_PXP_WFE_B_STAGE2_MUX11_TOG (0x00001e9c) + +#define BP_PXP_WFE_B_STAGE2_MUX11_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX11_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX11_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX11_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX11_MUX47 24 +#define BM_PXP_WFE_B_STAGE2_MUX11_MUX47 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX11_MUX47(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX11_MUX47) +#define BP_PXP_WFE_B_STAGE2_MUX11_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX11_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX11_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX11_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX11_MUX46 16 +#define BM_PXP_WFE_B_STAGE2_MUX11_MUX46 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX11_MUX46(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX11_MUX46) +#define BP_PXP_WFE_B_STAGE2_MUX11_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX11_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX11_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX11_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX11_MUX45 8 +#define BM_PXP_WFE_B_STAGE2_MUX11_MUX45 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX11_MUX45(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX11_MUX45) +#define BP_PXP_WFE_B_STAGE2_MUX11_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX11_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX11_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX11_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX11_MUX44 0 +#define BM_PXP_WFE_B_STAGE2_MUX11_MUX44 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX11_MUX44(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX11_MUX44) + +#define HW_PXP_WFE_B_STAGE2_MUX12 (0x00001ea0) +#define HW_PXP_WFE_B_STAGE2_MUX12_SET (0x00001ea4) +#define HW_PXP_WFE_B_STAGE2_MUX12_CLR (0x00001ea8) +#define HW_PXP_WFE_B_STAGE2_MUX12_TOG (0x00001eac) + +#define BP_PXP_WFE_B_STAGE2_MUX12_RSVD0 6 +#define BM_PXP_WFE_B_STAGE2_MUX12_RSVD0 0xFFFFFFC0 +#define BF_PXP_WFE_B_STAGE2_MUX12_RSVD0(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX12_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX12_MUX48 0 +#define BM_PXP_WFE_B_STAGE2_MUX12_MUX48 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX12_MUX48(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX12_MUX48) + +#define HW_PXP_WFE_B_STAGE3_MUX0 (0x00001eb0) +#define HW_PXP_WFE_B_STAGE3_MUX0_SET (0x00001eb4) +#define HW_PXP_WFE_B_STAGE3_MUX0_CLR (0x00001eb8) +#define HW_PXP_WFE_B_STAGE3_MUX0_TOG (0x00001ebc) + +#define BP_PXP_WFE_B_STAGE3_MUX0_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX0_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX0_MUX3 24 +#define BM_PXP_WFE_B_STAGE3_MUX0_MUX3 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX0_MUX3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX0_MUX3) +#define BP_PXP_WFE_B_STAGE3_MUX0_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX0_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX0_MUX2 16 +#define BM_PXP_WFE_B_STAGE3_MUX0_MUX2 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX0_MUX2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX0_MUX2) +#define BP_PXP_WFE_B_STAGE3_MUX0_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX0_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX0_MUX1 8 +#define BM_PXP_WFE_B_STAGE3_MUX0_MUX1 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX0_MUX1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX0_MUX1) +#define BP_PXP_WFE_B_STAGE3_MUX0_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX0_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX0_MUX0 0 +#define BM_PXP_WFE_B_STAGE3_MUX0_MUX0 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX0_MUX0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX0_MUX0) + +#define HW_PXP_WFE_B_STAGE3_MUX1 (0x00001ec0) +#define HW_PXP_WFE_B_STAGE3_MUX1_SET (0x00001ec4) +#define HW_PXP_WFE_B_STAGE3_MUX1_CLR (0x00001ec8) +#define HW_PXP_WFE_B_STAGE3_MUX1_TOG (0x00001ecc) + +#define BP_PXP_WFE_B_STAGE3_MUX1_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX1_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX1_MUX7 24 +#define BM_PXP_WFE_B_STAGE3_MUX1_MUX7 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX1_MUX7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX1_MUX7) +#define BP_PXP_WFE_B_STAGE3_MUX1_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX1_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX1_MUX6 16 +#define BM_PXP_WFE_B_STAGE3_MUX1_MUX6 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX1_MUX6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX1_MUX6) +#define BP_PXP_WFE_B_STAGE3_MUX1_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX1_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX1_MUX5 8 +#define BM_PXP_WFE_B_STAGE3_MUX1_MUX5 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX1_MUX5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX1_MUX5) +#define BP_PXP_WFE_B_STAGE3_MUX1_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX1_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX1_MUX4 0 +#define BM_PXP_WFE_B_STAGE3_MUX1_MUX4 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX1_MUX4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX1_MUX4) + +#define HW_PXP_WFE_B_STAGE3_MUX2 (0x00001ed0) +#define HW_PXP_WFE_B_STAGE3_MUX2_SET (0x00001ed4) +#define HW_PXP_WFE_B_STAGE3_MUX2_CLR (0x00001ed8) +#define HW_PXP_WFE_B_STAGE3_MUX2_TOG (0x00001edc) + +#define BP_PXP_WFE_B_STAGE3_MUX2_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX2_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX2_MUX11 24 +#define BM_PXP_WFE_B_STAGE3_MUX2_MUX11 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX2_MUX11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX2_MUX11) +#define BP_PXP_WFE_B_STAGE3_MUX2_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX2_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX2_MUX10 16 +#define BM_PXP_WFE_B_STAGE3_MUX2_MUX10 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX2_MUX10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX2_MUX10) +#define BP_PXP_WFE_B_STAGE3_MUX2_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX2_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX2_MUX9 8 +#define BM_PXP_WFE_B_STAGE3_MUX2_MUX9 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX2_MUX9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX2_MUX9) +#define BP_PXP_WFE_B_STAGE3_MUX2_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX2_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX2_MUX8 0 +#define BM_PXP_WFE_B_STAGE3_MUX2_MUX8 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX2_MUX8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX2_MUX8) + +#define HW_PXP_WFE_B_STAGE3_MUX3 (0x00001ee0) +#define HW_PXP_WFE_B_STAGE3_MUX3_SET (0x00001ee4) +#define HW_PXP_WFE_B_STAGE3_MUX3_CLR (0x00001ee8) +#define HW_PXP_WFE_B_STAGE3_MUX3_TOG (0x00001eec) + +#define BP_PXP_WFE_B_STAGE3_MUX3_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX3_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX3_MUX15 24 +#define BM_PXP_WFE_B_STAGE3_MUX3_MUX15 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX3_MUX15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX3_MUX15) +#define BP_PXP_WFE_B_STAGE3_MUX3_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX3_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX3_MUX14 16 +#define BM_PXP_WFE_B_STAGE3_MUX3_MUX14 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX3_MUX14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX3_MUX14) +#define BP_PXP_WFE_B_STAGE3_MUX3_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX3_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX3_MUX13 8 +#define BM_PXP_WFE_B_STAGE3_MUX3_MUX13 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX3_MUX13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX3_MUX13) +#define BP_PXP_WFE_B_STAGE3_MUX3_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX3_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX3_MUX12 0 +#define BM_PXP_WFE_B_STAGE3_MUX3_MUX12 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX3_MUX12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX3_MUX12) + +#define HW_PXP_WFE_B_STAGE3_MUX4 (0x00001ef0) +#define HW_PXP_WFE_B_STAGE3_MUX4_SET (0x00001ef4) +#define HW_PXP_WFE_B_STAGE3_MUX4_CLR (0x00001ef8) +#define HW_PXP_WFE_B_STAGE3_MUX4_TOG (0x00001efc) + +#define BP_PXP_WFE_B_STAGE3_MUX4_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX4_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX4_MUX19 24 +#define BM_PXP_WFE_B_STAGE3_MUX4_MUX19 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX4_MUX19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX4_MUX19) +#define BP_PXP_WFE_B_STAGE3_MUX4_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX4_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX4_MUX18 16 +#define BM_PXP_WFE_B_STAGE3_MUX4_MUX18 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX4_MUX18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX4_MUX18) +#define BP_PXP_WFE_B_STAGE3_MUX4_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX4_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX4_MUX17 8 +#define BM_PXP_WFE_B_STAGE3_MUX4_MUX17 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX4_MUX17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX4_MUX17) +#define BP_PXP_WFE_B_STAGE3_MUX4_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX4_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX4_MUX16 0 +#define BM_PXP_WFE_B_STAGE3_MUX4_MUX16 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX4_MUX16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX4_MUX16) + +#define HW_PXP_WFE_B_STAGE3_MUX5 (0x00001f00) +#define HW_PXP_WFE_B_STAGE3_MUX5_SET (0x00001f04) +#define HW_PXP_WFE_B_STAGE3_MUX5_CLR (0x00001f08) +#define HW_PXP_WFE_B_STAGE3_MUX5_TOG (0x00001f0c) + +#define BP_PXP_WFE_B_STAGE3_MUX5_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX5_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX5_MUX23 24 +#define BM_PXP_WFE_B_STAGE3_MUX5_MUX23 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX5_MUX23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX5_MUX23) +#define BP_PXP_WFE_B_STAGE3_MUX5_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX5_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX5_MUX22 16 +#define BM_PXP_WFE_B_STAGE3_MUX5_MUX22 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX5_MUX22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX5_MUX22) +#define BP_PXP_WFE_B_STAGE3_MUX5_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX5_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX5_MUX21 8 +#define BM_PXP_WFE_B_STAGE3_MUX5_MUX21 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX5_MUX21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX5_MUX21) +#define BP_PXP_WFE_B_STAGE3_MUX5_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX5_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX5_MUX20 0 +#define BM_PXP_WFE_B_STAGE3_MUX5_MUX20 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX5_MUX20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX5_MUX20) + +#define HW_PXP_WFE_B_STAGE3_MUX6 (0x00001f10) +#define HW_PXP_WFE_B_STAGE3_MUX6_SET (0x00001f14) +#define HW_PXP_WFE_B_STAGE3_MUX6_CLR (0x00001f18) +#define HW_PXP_WFE_B_STAGE3_MUX6_TOG (0x00001f1c) + +#define BP_PXP_WFE_B_STAGE3_MUX6_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX6_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX6_MUX27 24 +#define BM_PXP_WFE_B_STAGE3_MUX6_MUX27 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX6_MUX27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX6_MUX27) +#define BP_PXP_WFE_B_STAGE3_MUX6_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX6_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX6_MUX26 16 +#define BM_PXP_WFE_B_STAGE3_MUX6_MUX26 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX6_MUX26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX6_MUX26) +#define BP_PXP_WFE_B_STAGE3_MUX6_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX6_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX6_MUX25 8 +#define BM_PXP_WFE_B_STAGE3_MUX6_MUX25 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX6_MUX25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX6_MUX25) +#define BP_PXP_WFE_B_STAGE3_MUX6_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX6_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX6_MUX24 0 +#define BM_PXP_WFE_B_STAGE3_MUX6_MUX24 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX6_MUX24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX6_MUX24) + +#define HW_PXP_WFE_B_STAGE3_MUX7 (0x00001f20) +#define HW_PXP_WFE_B_STAGE3_MUX7_SET (0x00001f24) +#define HW_PXP_WFE_B_STAGE3_MUX7_CLR (0x00001f28) +#define HW_PXP_WFE_B_STAGE3_MUX7_TOG (0x00001f2c) + +#define BP_PXP_WFE_B_STAGE3_MUX7_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX7_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX7_MUX31 24 +#define BM_PXP_WFE_B_STAGE3_MUX7_MUX31 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX7_MUX31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX7_MUX31) +#define BP_PXP_WFE_B_STAGE3_MUX7_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX7_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX7_MUX30 16 +#define BM_PXP_WFE_B_STAGE3_MUX7_MUX30 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX7_MUX30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX7_MUX30) +#define BP_PXP_WFE_B_STAGE3_MUX7_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX7_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX7_MUX29 8 +#define BM_PXP_WFE_B_STAGE3_MUX7_MUX29 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX7_MUX29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX7_MUX29) +#define BP_PXP_WFE_B_STAGE3_MUX7_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX7_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX7_MUX28 0 +#define BM_PXP_WFE_B_STAGE3_MUX7_MUX28 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX7_MUX28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX7_MUX28) + +#define HW_PXP_WFE_B_STAGE3_MUX8 (0x00001f30) +#define HW_PXP_WFE_B_STAGE3_MUX8_SET (0x00001f34) +#define HW_PXP_WFE_B_STAGE3_MUX8_CLR (0x00001f38) +#define HW_PXP_WFE_B_STAGE3_MUX8_TOG (0x00001f3c) + +#define BP_PXP_WFE_B_STAGE3_MUX8_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX8_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX8_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX8_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX8_MUX35 24 +#define BM_PXP_WFE_B_STAGE3_MUX8_MUX35 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX8_MUX35(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX8_MUX35) +#define BP_PXP_WFE_B_STAGE3_MUX8_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX8_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX8_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX8_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX8_MUX34 16 +#define BM_PXP_WFE_B_STAGE3_MUX8_MUX34 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX8_MUX34(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX8_MUX34) +#define BP_PXP_WFE_B_STAGE3_MUX8_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX8_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX8_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX8_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX8_MUX33 8 +#define BM_PXP_WFE_B_STAGE3_MUX8_MUX33 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX8_MUX33(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX8_MUX33) +#define BP_PXP_WFE_B_STAGE3_MUX8_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX8_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX8_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX8_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX8_MUX32 0 +#define BM_PXP_WFE_B_STAGE3_MUX8_MUX32 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX8_MUX32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX8_MUX32) + +#define HW_PXP_WFE_B_STAGE3_MUX9 (0x00001f40) +#define HW_PXP_WFE_B_STAGE3_MUX9_SET (0x00001f44) +#define HW_PXP_WFE_B_STAGE3_MUX9_CLR (0x00001f48) +#define HW_PXP_WFE_B_STAGE3_MUX9_TOG (0x00001f4c) + +#define BP_PXP_WFE_B_STAGE3_MUX9_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX9_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX9_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX9_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX9_MUX39 24 +#define BM_PXP_WFE_B_STAGE3_MUX9_MUX39 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX9_MUX39(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX9_MUX39) +#define BP_PXP_WFE_B_STAGE3_MUX9_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX9_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX9_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX9_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX9_MUX38 16 +#define BM_PXP_WFE_B_STAGE3_MUX9_MUX38 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX9_MUX38(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX9_MUX38) +#define BP_PXP_WFE_B_STAGE3_MUX9_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX9_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX9_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX9_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX9_MUX37 8 +#define BM_PXP_WFE_B_STAGE3_MUX9_MUX37 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX9_MUX37(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX9_MUX37) +#define BP_PXP_WFE_B_STAGE3_MUX9_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX9_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX9_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX9_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX9_MUX36 0 +#define BM_PXP_WFE_B_STAGE3_MUX9_MUX36 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX9_MUX36(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX9_MUX36) + +#define HW_PXP_WFE_B_STAGE3_MUX10 (0x00001f50) +#define HW_PXP_WFE_B_STAGE3_MUX10_SET (0x00001f54) +#define HW_PXP_WFE_B_STAGE3_MUX10_CLR (0x00001f58) +#define HW_PXP_WFE_B_STAGE3_MUX10_TOG (0x00001f5c) + +#define BP_PXP_WFE_B_STAGE3_MUX10_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX10_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX10_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX10_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX10_MUX43 24 +#define BM_PXP_WFE_B_STAGE3_MUX10_MUX43 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX10_MUX43(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX10_MUX43) +#define BP_PXP_WFE_B_STAGE3_MUX10_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX10_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX10_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX10_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX10_MUX42 16 +#define BM_PXP_WFE_B_STAGE3_MUX10_MUX42 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX10_MUX42(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX10_MUX42) +#define BP_PXP_WFE_B_STAGE3_MUX10_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX10_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX10_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX10_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX10_MUX41 8 +#define BM_PXP_WFE_B_STAGE3_MUX10_MUX41 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX10_MUX41(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX10_MUX41) +#define BP_PXP_WFE_B_STAGE3_MUX10_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX10_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX10_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX10_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX10_MUX40 0 +#define BM_PXP_WFE_B_STAGE3_MUX10_MUX40 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX10_MUX40(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX10_MUX40) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_0 (0x00001f60) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_1 (0x00001f70) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_2 (0x00001f80) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_3 (0x00001f90) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_4 (0x00001fa0) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_5 (0x00001fb0) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_6 (0x00001fc0) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_7 (0x00001fd0) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_0 (0x00001fe0) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_1 (0x00001ff0) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_2 (0x00002000) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_3 (0x00002010) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_4 (0x00002020) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_5 (0x00002030) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_6 (0x00002040) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_7 (0x00002050) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28) + +#define HW_PXP_WFE_B_STAGE1_5X8_MASKS_0 (0x00002060) + +#define BP_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD2 13 +#define BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD2 0xFFFFE000 +#define BF_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD2(v) \ + (((v) << 13) & BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD2) +#define BP_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1 8 +#define BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1 0x00001F00 +#define BF_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1) +#define BP_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD3 5 +#define BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD3 0x000000E0 +#define BF_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD3(v) \ + (((v) << 5) & BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD3) +#define BP_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0 0 +#define BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0 0x0000001F +#define BF_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0) + +#define HW_PXP_WFE_B_STG1_5X1_OUT0 (0x00002070) + +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_5X1_MASKS (0x00002080) + +#define BP_PXP_WFE_B_STG1_5X1_MASKS_RSVD0 5 +#define BM_PXP_WFE_B_STG1_5X1_MASKS_RSVD0 0xFFFFFFE0 +#define BF_PXP_WFE_B_STG1_5X1_MASKS_RSVD0(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_5X1_MASKS_RSVD0) +#define BP_PXP_WFE_B_STG1_5X1_MASKS_MASK0 0 +#define BM_PXP_WFE_B_STG1_5X1_MASKS_MASK0 0x0000001F +#define BF_PXP_WFE_B_STG1_5X1_MASKS_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X1_MASKS_MASK0) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_0 (0x00002090) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_1 (0x000020a0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_2 (0x000020b0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_3 (0x000020c0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_4 (0x000020d0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_5 (0x000020e0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_6 (0x000020f0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_7 (0x00002100) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_0 (0x00002110) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_1 (0x00002120) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_2 (0x00002130) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_3 (0x00002140) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_4 (0x00002150) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_5 (0x00002160) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_6 (0x00002170) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_7 (0x00002180) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_0 (0x00002190) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_1 (0x000021a0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_2 (0x000021b0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_3 (0x000021c0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_4 (0x000021d0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_5 (0x000021e0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_6 (0x000021f0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_7 (0x00002200) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_0 (0x00002210) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_1 (0x00002220) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_2 (0x00002230) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_3 (0x00002240) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_4 (0x00002250) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_5 (0x00002260) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_6 (0x00002270) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_7 (0x00002280) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_0 (0x00002290) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_1 (0x000022a0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_2 (0x000022b0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_3 (0x000022c0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_4 (0x000022d0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_5 (0x000022e0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_6 (0x000022f0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_7 (0x00002300) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_0 (0x00002310) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_1 (0x00002320) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_2 (0x00002330) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_3 (0x00002340) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_4 (0x00002350) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_5 (0x00002360) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_6 (0x00002370) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_7 (0x00002380) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_0 (0x00002390) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_1 (0x000023a0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_2 (0x000023b0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_3 (0x000023c0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_4 (0x000023d0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_5 (0x000023e0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_6 (0x000023f0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_7 (0x00002400) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_0 (0x00002410) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_1 (0x00002420) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_2 (0x00002430) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_3 (0x00002440) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_4 (0x00002450) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_5 (0x00002460) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_6 (0x00002470) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_7 (0x00002480) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_0 (0x00002490) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_1 (0x000024a0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_2 (0x000024b0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_3 (0x000024c0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_4 (0x000024e0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_5 (0x000024f0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_6 (0x00002500) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_7 (0x00002510) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28) + +#define HW_PXP_WFE_B_STAGE2_5X6_MASKS_0 (0x00002520) + +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD3 29 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD3 0xE0000000 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD3(v) \ + (((v) << 29) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD3) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3 24 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3 0x1F000000 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD2 21 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD2 0x00E00000 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD2(v) \ + (((v) << 21) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD2) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2 16 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2 0x001F0000 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD1 13 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD1 0x0000E000 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD1(v) \ + (((v) << 13) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD1) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1 8 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1 0x00001F00 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD0 5 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD0 0x000000E0 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD0(v) \ + (((v) << 5) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD0) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0 0 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0 0x0000001F +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0) + +#define HW_PXP_WFE_B_STAGE2_5X6_ADDR_0 (0x00002530) + +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD3 30 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD3 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD3(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD3) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3 24 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD2 22 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD2 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD2) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2 16 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD1 14 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD1 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD1) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1 8 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD0 6 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD0 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD0(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD0) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0 0 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0 0x0000003F +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0) + +#define HW_PXP_WFE_B_STG2_5X1_OUT0 (0x00002540) + +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X1_OUT1 (0x00002550) + +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X1_OUT2 (0x00002560) + +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X1_OUT3 (0x00002570) + +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X1_MASKS (0x00002580) + +#define BP_PXP_WFE_B_STG2_5X1_MASKS_RSVD3 29 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD3 0xE0000000 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_RSVD3(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD3) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_MASK3 24 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_MASK3 0x1F000000 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X1_MASKS_MASK3) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_RSVD2 21 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD2 0x00E00000 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_RSVD2(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD2) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_MASK2 16 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_MASK2 0x001F0000 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X1_MASKS_MASK2) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_RSVD1 13 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD1 0x0000E000 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_RSVD1(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD1) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_MASK1 8 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_MASK1 0x00001F00 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X1_MASKS_MASK1) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_RSVD0 5 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD0 0x000000E0 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_RSVD0(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD0) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_MASK0 0 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_MASK0 0x0000001F +#define BF_PXP_WFE_B_STG2_5X1_MASKS_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X1_MASKS_MASK0) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_0 (0x00002590) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_1 (0x000025a0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_2 (0x000025b0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_3 (0x000025c0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_4 (0x000025d0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_5 (0x000025e0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_6 (0x000025f0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_7 (0x00002600) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_0 (0x00002610) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_1 (0x00002620) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_2 (0x00002630) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_3 (0x00002640) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_4 (0x00002650) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_5 (0x00002660) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_6 (0x00002670) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_7 (0x00002680) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_0 (0x00002690) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_1 (0x000026a0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_2 (0x000026b0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_3 (0x000026c0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_4 (0x000026d0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_5 (0x000026e0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_6 (0x000026f0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_7 (0x00002700) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_0 (0x00002710) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_1 (0x00002720) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_2 (0x00002730) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_3 (0x00002740) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_4 (0x00002750) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_5 (0x00002760) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_6 (0x00002770) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_7 (0x00002780) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG3_F8X1_MASKS (0x00002790) + +#define BP_PXP_WFE_B_STG3_F8X1_MASKS_MASK3 24 +#define BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK3 0xFF000000 +#define BF_PXP_WFE_B_STG3_F8X1_MASKS_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK3) +#define BP_PXP_WFE_B_STG3_F8X1_MASKS_MASK2 16 +#define BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK2 0x00FF0000 +#define BF_PXP_WFE_B_STG3_F8X1_MASKS_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK2) +#define BP_PXP_WFE_B_STG3_F8X1_MASKS_MASK1 8 +#define BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK1 0x0000FF00 +#define BF_PXP_WFE_B_STG3_F8X1_MASKS_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK1) +#define BP_PXP_WFE_B_STG3_F8X1_MASKS_MASK0 0 +#define BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK0 0x000000FF +#define BF_PXP_WFE_B_STG3_F8X1_MASKS_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK0) + +#define HW_PXP_ALU_A_CTRL (0x00002810) +#define HW_PXP_ALU_A_CTRL_SET (0x00002814) +#define HW_PXP_ALU_A_CTRL_CLR (0x00002818) +#define HW_PXP_ALU_A_CTRL_TOG (0x0000281c) + +#define BP_PXP_ALU_A_CTRL_RSVD0 29 +#define BM_PXP_ALU_A_CTRL_RSVD0 0xE0000000 +#define BF_PXP_ALU_A_CTRL_RSVD0(v) \ + (((v) << 29) & BM_PXP_ALU_A_CTRL_RSVD0) +#define BM_PXP_ALU_A_CTRL_DONE 0x10000000 +#define BF_PXP_ALU_A_CTRL_DONE(v) \ + (((v) << 28) & BM_PXP_ALU_A_CTRL_DONE) +#define BP_PXP_ALU_A_CTRL_RSVD1 21 +#define BM_PXP_ALU_A_CTRL_RSVD1 0x0FE00000 +#define BF_PXP_ALU_A_CTRL_RSVD1(v) \ + (((v) << 21) & BM_PXP_ALU_A_CTRL_RSVD1) +#define BM_PXP_ALU_A_CTRL_DONE_IRQ_EN 0x00100000 +#define BF_PXP_ALU_A_CTRL_DONE_IRQ_EN(v) \ + (((v) << 20) & BM_PXP_ALU_A_CTRL_DONE_IRQ_EN) +#define BP_PXP_ALU_A_CTRL_RSVD2 17 +#define BM_PXP_ALU_A_CTRL_RSVD2 0x000E0000 +#define BF_PXP_ALU_A_CTRL_RSVD2(v) \ + (((v) << 17) & BM_PXP_ALU_A_CTRL_RSVD2) +#define BM_PXP_ALU_A_CTRL_DONE_IRQ_FLAG 0x00010000 +#define BF_PXP_ALU_A_CTRL_DONE_IRQ_FLAG(v) \ + (((v) << 16) & BM_PXP_ALU_A_CTRL_DONE_IRQ_FLAG) +#define BP_PXP_ALU_A_CTRL_RSVD3 13 +#define BM_PXP_ALU_A_CTRL_RSVD3 0x0000E000 +#define BF_PXP_ALU_A_CTRL_RSVD3(v) \ + (((v) << 13) & BM_PXP_ALU_A_CTRL_RSVD3) +#define BM_PXP_ALU_A_CTRL_BYPASS 0x00001000 +#define BF_PXP_ALU_A_CTRL_BYPASS(v) \ + (((v) << 12) & BM_PXP_ALU_A_CTRL_BYPASS) +#define BV_PXP_ALU_A_CTRL_BYPASS__0 0x0 +#define BV_PXP_ALU_A_CTRL_BYPASS__1 0x1 +#define BP_PXP_ALU_A_CTRL_RSVD4 9 +#define BM_PXP_ALU_A_CTRL_RSVD4 0x00000E00 +#define BF_PXP_ALU_A_CTRL_RSVD4(v) \ + (((v) << 9) & BM_PXP_ALU_A_CTRL_RSVD4) +#define BM_PXP_ALU_A_CTRL_SW_RESET 0x00000100 +#define BF_PXP_ALU_A_CTRL_SW_RESET(v) \ + (((v) << 8) & BM_PXP_ALU_A_CTRL_SW_RESET) +#define BP_PXP_ALU_A_CTRL_RSVD5 5 +#define BM_PXP_ALU_A_CTRL_RSVD5 0x000000E0 +#define BF_PXP_ALU_A_CTRL_RSVD5(v) \ + (((v) << 5) & BM_PXP_ALU_A_CTRL_RSVD5) +#define BM_PXP_ALU_A_CTRL_START 0x00000010 +#define BF_PXP_ALU_A_CTRL_START(v) \ + (((v) << 4) & BM_PXP_ALU_A_CTRL_START) +#define BP_PXP_ALU_A_CTRL_RSVD6 1 +#define BM_PXP_ALU_A_CTRL_RSVD6 0x0000000E +#define BF_PXP_ALU_A_CTRL_RSVD6(v) \ + (((v) << 1) & BM_PXP_ALU_A_CTRL_RSVD6) +#define BM_PXP_ALU_A_CTRL_ENABLE 0x00000001 +#define BF_PXP_ALU_A_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_ALU_A_CTRL_ENABLE) +#define BV_PXP_ALU_A_CTRL_ENABLE__0 0x0 +#define BV_PXP_ALU_A_CTRL_ENABLE__1 0x1 + +#define HW_PXP_ALU_A_BUF_SIZE (0x00002820) + +#define BP_PXP_ALU_A_BUF_SIZE_RSVD0 28 +#define BM_PXP_ALU_A_BUF_SIZE_RSVD0 0xF0000000 +#define BF_PXP_ALU_A_BUF_SIZE_RSVD0(v) \ + (((v) << 28) & BM_PXP_ALU_A_BUF_SIZE_RSVD0) +#define BP_PXP_ALU_A_BUF_SIZE_BUF_HEIGHT 16 +#define BM_PXP_ALU_A_BUF_SIZE_BUF_HEIGHT 0x0FFF0000 +#define BF_PXP_ALU_A_BUF_SIZE_BUF_HEIGHT(v) \ + (((v) << 16) & BM_PXP_ALU_A_BUF_SIZE_BUF_HEIGHT) +#define BP_PXP_ALU_A_BUF_SIZE_RSVD1 12 +#define BM_PXP_ALU_A_BUF_SIZE_RSVD1 0x0000F000 +#define BF_PXP_ALU_A_BUF_SIZE_RSVD1(v) \ + (((v) << 12) & BM_PXP_ALU_A_BUF_SIZE_RSVD1) +#define BP_PXP_ALU_A_BUF_SIZE_BUF_WIDTH 0 +#define BM_PXP_ALU_A_BUF_SIZE_BUF_WIDTH 0x00000FFF +#define BF_PXP_ALU_A_BUF_SIZE_BUF_WIDTH(v) \ + (((v) << 0) & BM_PXP_ALU_A_BUF_SIZE_BUF_WIDTH) + +#define HW_PXP_ALU_A_INST_ENTRY (0x00002830) + +#define BP_PXP_ALU_A_INST_ENTRY_RSVD0 16 +#define BM_PXP_ALU_A_INST_ENTRY_RSVD0 0xFFFF0000 +#define BF_PXP_ALU_A_INST_ENTRY_RSVD0(v) \ + (((v) << 16) & BM_PXP_ALU_A_INST_ENTRY_RSVD0) +#define BP_PXP_ALU_A_INST_ENTRY_ENTRY_ADDR 0 +#define BM_PXP_ALU_A_INST_ENTRY_ENTRY_ADDR 0x0000FFFF +#define BF_PXP_ALU_A_INST_ENTRY_ENTRY_ADDR(v) \ + (((v) << 0) & BM_PXP_ALU_A_INST_ENTRY_ENTRY_ADDR) + +#define HW_PXP_ALU_A_PARAM (0x00002840) + +#define BP_PXP_ALU_A_PARAM_RSVD0 16 +#define BM_PXP_ALU_A_PARAM_RSVD0 0xFFFF0000 +#define BF_PXP_ALU_A_PARAM_RSVD0(v) \ + (((v) << 16) & BM_PXP_ALU_A_PARAM_RSVD0) +#define BP_PXP_ALU_A_PARAM_PARAM1 8 +#define BM_PXP_ALU_A_PARAM_PARAM1 0x0000FF00 +#define BF_PXP_ALU_A_PARAM_PARAM1(v) \ + (((v) << 8) & BM_PXP_ALU_A_PARAM_PARAM1) +#define BP_PXP_ALU_A_PARAM_PARAM0 0 +#define BM_PXP_ALU_A_PARAM_PARAM0 0x000000FF +#define BF_PXP_ALU_A_PARAM_PARAM0(v) \ + (((v) << 0) & BM_PXP_ALU_A_PARAM_PARAM0) + +#define HW_PXP_ALU_A_CONFIG (0x00002850) + +#define BP_PXP_ALU_A_CONFIG_BUF_ADDR 0 +#define BM_PXP_ALU_A_CONFIG_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_ALU_A_CONFIG_BUF_ADDR(v) (v) + +#define HW_PXP_ALU_A_LUT_CONFIG (0x00002860) +#define HW_PXP_ALU_A_LUT_CONFIG_SET (0x00002864) +#define HW_PXP_ALU_A_LUT_CONFIG_CLR (0x00002868) +#define HW_PXP_ALU_A_LUT_CONFIG_TOG (0x0000286c) + +#define BP_PXP_ALU_A_LUT_CONFIG_RSVD0 6 +#define BM_PXP_ALU_A_LUT_CONFIG_RSVD0 0xFFFFFFC0 +#define BF_PXP_ALU_A_LUT_CONFIG_RSVD0(v) \ + (((v) << 6) & BM_PXP_ALU_A_LUT_CONFIG_RSVD0) +#define BP_PXP_ALU_A_LUT_CONFIG_MODE 4 +#define BM_PXP_ALU_A_LUT_CONFIG_MODE 0x00000030 +#define BF_PXP_ALU_A_LUT_CONFIG_MODE(v) \ + (((v) << 4) & BM_PXP_ALU_A_LUT_CONFIG_MODE) +#define BV_PXP_ALU_A_LUT_CONFIG_MODE__0 0x0 +#define BV_PXP_ALU_A_LUT_CONFIG_MODE__1 0x1 +#define BV_PXP_ALU_A_LUT_CONFIG_MODE__2 0x2 +#define BV_PXP_ALU_A_LUT_CONFIG_MODE__3 0x3 +#define BP_PXP_ALU_A_LUT_CONFIG_RSVD1 1 +#define BM_PXP_ALU_A_LUT_CONFIG_RSVD1 0x0000000E +#define BF_PXP_ALU_A_LUT_CONFIG_RSVD1(v) \ + (((v) << 1) & BM_PXP_ALU_A_LUT_CONFIG_RSVD1) +#define BM_PXP_ALU_A_LUT_CONFIG_EN 0x00000001 +#define BF_PXP_ALU_A_LUT_CONFIG_EN(v) \ + (((v) << 0) & BM_PXP_ALU_A_LUT_CONFIG_EN) + +#define HW_PXP_ALU_A_LUT_DATA0 (0x00002870) + +#define BP_PXP_ALU_A_LUT_DATA0_LUT_DATA_L 0 +#define BM_PXP_ALU_A_LUT_DATA0_LUT_DATA_L 0xFFFFFFFF +#define BF_PXP_ALU_A_LUT_DATA0_LUT_DATA_L(v) (v) + +#define HW_PXP_ALU_A_LUT_DATA1 (0x00002880) + +#define BP_PXP_ALU_A_LUT_DATA1_LUT_DATA_H 0 +#define BM_PXP_ALU_A_LUT_DATA1_LUT_DATA_H 0xFFFFFFFF +#define BF_PXP_ALU_A_LUT_DATA1_LUT_DATA_H(v) (v) + +#define HW_PXP_ALU_A_DBG (0x00002890) + +#define BP_PXP_ALU_A_DBG_DEBUG_SEL 24 +#define BM_PXP_ALU_A_DBG_DEBUG_SEL 0xFF000000 +#define BF_PXP_ALU_A_DBG_DEBUG_SEL(v) \ + (((v) << 24) & BM_PXP_ALU_A_DBG_DEBUG_SEL) +#define BP_PXP_ALU_A_DBG_DEBUG_VALUE 0 +#define BM_PXP_ALU_A_DBG_DEBUG_VALUE 0x00FFFFFF +#define BF_PXP_ALU_A_DBG_DEBUG_VALUE(v) \ + (((v) << 0) & BM_PXP_ALU_A_DBG_DEBUG_VALUE) + +#define HW_PXP_ALU_B_CTRL (0x000028a0) +#define HW_PXP_ALU_B_CTRL_SET (0x000028a4) +#define HW_PXP_ALU_B_CTRL_CLR (0x000028a8) +#define HW_PXP_ALU_B_CTRL_TOG (0x000028ac) + +#define BP_PXP_ALU_B_CTRL_RSVD0 29 +#define BM_PXP_ALU_B_CTRL_RSVD0 0xE0000000 +#define BF_PXP_ALU_B_CTRL_RSVD0(v) \ + (((v) << 29) & BM_PXP_ALU_B_CTRL_RSVD0) +#define BM_PXP_ALU_B_CTRL_DONE 0x10000000 +#define BF_PXP_ALU_B_CTRL_DONE(v) \ + (((v) << 28) & BM_PXP_ALU_B_CTRL_DONE) +#define BP_PXP_ALU_B_CTRL_RSVD1 21 +#define BM_PXP_ALU_B_CTRL_RSVD1 0x0FE00000 +#define BF_PXP_ALU_B_CTRL_RSVD1(v) \ + (((v) << 21) & BM_PXP_ALU_B_CTRL_RSVD1) +#define BM_PXP_ALU_B_CTRL_DONE_IRQ_EN 0x00100000 +#define BF_PXP_ALU_B_CTRL_DONE_IRQ_EN(v) \ + (((v) << 20) & BM_PXP_ALU_B_CTRL_DONE_IRQ_EN) +#define BP_PXP_ALU_B_CTRL_RSVD2 17 +#define BM_PXP_ALU_B_CTRL_RSVD2 0x000E0000 +#define BF_PXP_ALU_B_CTRL_RSVD2(v) \ + (((v) << 17) & BM_PXP_ALU_B_CTRL_RSVD2) +#define BM_PXP_ALU_B_CTRL_DONE_IRQ_FLAG 0x00010000 +#define BF_PXP_ALU_B_CTRL_DONE_IRQ_FLAG(v) \ + (((v) << 16) & BM_PXP_ALU_B_CTRL_DONE_IRQ_FLAG) +#define BP_PXP_ALU_B_CTRL_RSVD3 13 +#define BM_PXP_ALU_B_CTRL_RSVD3 0x0000E000 +#define BF_PXP_ALU_B_CTRL_RSVD3(v) \ + (((v) << 13) & BM_PXP_ALU_B_CTRL_RSVD3) +#define BM_PXP_ALU_B_CTRL_BYPASS 0x00001000 +#define BF_PXP_ALU_B_CTRL_BYPASS(v) \ + (((v) << 12) & BM_PXP_ALU_B_CTRL_BYPASS) +#define BV_PXP_ALU_B_CTRL_BYPASS__0 0x0 +#define BV_PXP_ALU_B_CTRL_BYPASS__1 0x1 +#define BP_PXP_ALU_B_CTRL_RSVD4 9 +#define BM_PXP_ALU_B_CTRL_RSVD4 0x00000E00 +#define BF_PXP_ALU_B_CTRL_RSVD4(v) \ + (((v) << 9) & BM_PXP_ALU_B_CTRL_RSVD4) +#define BM_PXP_ALU_B_CTRL_SW_RESET 0x00000100 +#define BF_PXP_ALU_B_CTRL_SW_RESET(v) \ + (((v) << 8) & BM_PXP_ALU_B_CTRL_SW_RESET) +#define BP_PXP_ALU_B_CTRL_RSVD5 5 +#define BM_PXP_ALU_B_CTRL_RSVD5 0x000000E0 +#define BF_PXP_ALU_B_CTRL_RSVD5(v) \ + (((v) << 5) & BM_PXP_ALU_B_CTRL_RSVD5) +#define BM_PXP_ALU_B_CTRL_START 0x00000010 +#define BF_PXP_ALU_B_CTRL_START(v) \ + (((v) << 4) & BM_PXP_ALU_B_CTRL_START) +#define BP_PXP_ALU_B_CTRL_RSVD6 1 +#define BM_PXP_ALU_B_CTRL_RSVD6 0x0000000E +#define BF_PXP_ALU_B_CTRL_RSVD6(v) \ + (((v) << 1) & BM_PXP_ALU_B_CTRL_RSVD6) +#define BM_PXP_ALU_B_CTRL_ENABLE 0x00000001 +#define BF_PXP_ALU_B_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_ALU_B_CTRL_ENABLE) +#define BV_PXP_ALU_B_CTRL_ENABLE__0 0x0 +#define BV_PXP_ALU_B_CTRL_ENABLE__1 0x1 + +#define HW_PXP_ALU_B_BUF_SIZE (0x000028b0) + +#define BP_PXP_ALU_B_BUF_SIZE_RSVD0 28 +#define BM_PXP_ALU_B_BUF_SIZE_RSVD0 0xF0000000 +#define BF_PXP_ALU_B_BUF_SIZE_RSVD0(v) \ + (((v) << 28) & BM_PXP_ALU_B_BUF_SIZE_RSVD0) +#define BP_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT 16 +#define BM_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT 0x0FFF0000 +#define BF_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT(v) \ + (((v) << 16) & BM_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT) +#define BP_PXP_ALU_B_BUF_SIZE_RSVD1 12 +#define BM_PXP_ALU_B_BUF_SIZE_RSVD1 0x0000F000 +#define BF_PXP_ALU_B_BUF_SIZE_RSVD1(v) \ + (((v) << 12) & BM_PXP_ALU_B_BUF_SIZE_RSVD1) +#define BP_PXP_ALU_B_BUF_SIZE_BUF_WIDTH 0 +#define BM_PXP_ALU_B_BUF_SIZE_BUF_WIDTH 0x00000FFF +#define BF_PXP_ALU_B_BUF_SIZE_BUF_WIDTH(v) \ + (((v) << 0) & BM_PXP_ALU_B_BUF_SIZE_BUF_WIDTH) + +#define HW_PXP_ALU_B_INST_ENTRY (0x000028c0) + +#define BP_PXP_ALU_B_INST_ENTRY_RSVD0 16 +#define BM_PXP_ALU_B_INST_ENTRY_RSVD0 0xFFFF0000 +#define BF_PXP_ALU_B_INST_ENTRY_RSVD0(v) \ + (((v) << 16) & BM_PXP_ALU_B_INST_ENTRY_RSVD0) +#define BP_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR 0 +#define BM_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR 0x0000FFFF +#define BF_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR(v) \ + (((v) << 0) & BM_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR) + +#define HW_PXP_ALU_B_PARAM (0x000028d0) + +#define BP_PXP_ALU_B_PARAM_RSVD0 16 +#define BM_PXP_ALU_B_PARAM_RSVD0 0xFFFF0000 +#define BF_PXP_ALU_B_PARAM_RSVD0(v) \ + (((v) << 16) & BM_PXP_ALU_B_PARAM_RSVD0) +#define BP_PXP_ALU_B_PARAM_PARAM1 8 +#define BM_PXP_ALU_B_PARAM_PARAM1 0x0000FF00 +#define BF_PXP_ALU_B_PARAM_PARAM1(v) \ + (((v) << 8) & BM_PXP_ALU_B_PARAM_PARAM1) +#define BP_PXP_ALU_B_PARAM_PARAM0 0 +#define BM_PXP_ALU_B_PARAM_PARAM0 0x000000FF +#define BF_PXP_ALU_B_PARAM_PARAM0(v) \ + (((v) << 0) & BM_PXP_ALU_B_PARAM_PARAM0) + +#define HW_PXP_ALU_B_CONFIG (0x000028e0) + +#define BP_PXP_ALU_B_CONFIG_BUF_ADDR 0 +#define BM_PXP_ALU_B_CONFIG_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_ALU_B_CONFIG_BUF_ADDR(v) (v) + +#define HW_PXP_ALU_B_LUT_CONFIG (0x000028f0) +#define HW_PXP_ALU_B_LUT_CONFIG_SET (0x000028f4) +#define HW_PXP_ALU_B_LUT_CONFIG_CLR (0x000028f8) +#define HW_PXP_ALU_B_LUT_CONFIG_TOG (0x000028fc) + +#define BP_PXP_ALU_B_LUT_CONFIG_RSVD0 6 +#define BM_PXP_ALU_B_LUT_CONFIG_RSVD0 0xFFFFFFC0 +#define BF_PXP_ALU_B_LUT_CONFIG_RSVD0(v) \ + (((v) << 6) & BM_PXP_ALU_B_LUT_CONFIG_RSVD0) +#define BP_PXP_ALU_B_LUT_CONFIG_MODE 4 +#define BM_PXP_ALU_B_LUT_CONFIG_MODE 0x00000030 +#define BF_PXP_ALU_B_LUT_CONFIG_MODE(v) \ + (((v) << 4) & BM_PXP_ALU_B_LUT_CONFIG_MODE) +#define BV_PXP_ALU_B_LUT_CONFIG_MODE__0 0x0 +#define BV_PXP_ALU_B_LUT_CONFIG_MODE__1 0x1 +#define BV_PXP_ALU_B_LUT_CONFIG_MODE__2 0x2 +#define BV_PXP_ALU_B_LUT_CONFIG_MODE__3 0x3 +#define BP_PXP_ALU_B_LUT_CONFIG_RSVD1 1 +#define BM_PXP_ALU_B_LUT_CONFIG_RSVD1 0x0000000E +#define BF_PXP_ALU_B_LUT_CONFIG_RSVD1(v) \ + (((v) << 1) & BM_PXP_ALU_B_LUT_CONFIG_RSVD1) +#define BM_PXP_ALU_B_LUT_CONFIG_EN 0x00000001 +#define BF_PXP_ALU_B_LUT_CONFIG_EN(v) \ + (((v) << 0) & BM_PXP_ALU_B_LUT_CONFIG_EN) + +#define HW_PXP_ALU_B_LUT_DATA0 (0x00002900) + +#define BP_PXP_ALU_B_LUT_DATA0_LUT_DATA_L 0 +#define BM_PXP_ALU_B_LUT_DATA0_LUT_DATA_L 0xFFFFFFFF +#define BF_PXP_ALU_B_LUT_DATA0_LUT_DATA_L(v) (v) + +#define HW_PXP_ALU_B_LUT_DATA1 (0x00002910) + +#define BP_PXP_ALU_B_LUT_DATA1_LUT_DATA_H 0 +#define BM_PXP_ALU_B_LUT_DATA1_LUT_DATA_H 0xFFFFFFFF +#define BF_PXP_ALU_B_LUT_DATA1_LUT_DATA_H(v) (v) + +#define HW_PXP_ALU_B_DBG (0x00002920) + +#define BP_PXP_ALU_B_DBG_DEBUG_SEL 24 +#define BM_PXP_ALU_B_DBG_DEBUG_SEL 0xFF000000 +#define BF_PXP_ALU_B_DBG_DEBUG_SEL(v) \ + (((v) << 24) & BM_PXP_ALU_B_DBG_DEBUG_SEL) +#define BP_PXP_ALU_B_DBG_DEBUG_VALUE 0 +#define BM_PXP_ALU_B_DBG_DEBUG_VALUE 0x00FFFFFF +#define BF_PXP_ALU_B_DBG_DEBUG_VALUE(v) \ + (((v) << 0) & BM_PXP_ALU_B_DBG_DEBUG_VALUE) + +#define HW_PXP_HIST_A_CTRL (0x00002a00) + +#define BP_PXP_HIST_A_CTRL_RSVD4 27 +#define BM_PXP_HIST_A_CTRL_RSVD4 0xF8000000 +#define BF_PXP_HIST_A_CTRL_RSVD4(v) \ + (((v) << 27) & BM_PXP_HIST_A_CTRL_RSVD4) +#define BP_PXP_HIST_A_CTRL_PIXEL_WIDTH 24 +#define BM_PXP_HIST_A_CTRL_PIXEL_WIDTH 0x07000000 +#define BF_PXP_HIST_A_CTRL_PIXEL_WIDTH(v) \ + (((v) << 24) & BM_PXP_HIST_A_CTRL_PIXEL_WIDTH) +#define BM_PXP_HIST_A_CTRL_RSVD3 0x00800000 +#define BF_PXP_HIST_A_CTRL_RSVD3(v) \ + (((v) << 23) & BM_PXP_HIST_A_CTRL_RSVD3) +#define BP_PXP_HIST_A_CTRL_PIXEL_OFFSET 16 +#define BM_PXP_HIST_A_CTRL_PIXEL_OFFSET 0x007F0000 +#define BF_PXP_HIST_A_CTRL_PIXEL_OFFSET(v) \ + (((v) << 16) & BM_PXP_HIST_A_CTRL_PIXEL_OFFSET) +#define BP_PXP_HIST_A_CTRL_RSVD2 13 +#define BM_PXP_HIST_A_CTRL_RSVD2 0x0000E000 +#define BF_PXP_HIST_A_CTRL_RSVD2(v) \ + (((v) << 13) & BM_PXP_HIST_A_CTRL_RSVD2) +#define BP_PXP_HIST_A_CTRL_STATUS 8 +#define BM_PXP_HIST_A_CTRL_STATUS 0x00001F00 +#define BF_PXP_HIST_A_CTRL_STATUS(v) \ + (((v) << 8) & BM_PXP_HIST_A_CTRL_STATUS) +#define BP_PXP_HIST_A_CTRL_RSVD1 5 +#define BM_PXP_HIST_A_CTRL_RSVD1 0x000000E0 +#define BF_PXP_HIST_A_CTRL_RSVD1(v) \ + (((v) << 5) & BM_PXP_HIST_A_CTRL_RSVD1) +#define BM_PXP_HIST_A_CTRL_CLEAR 0x00000010 +#define BF_PXP_HIST_A_CTRL_CLEAR(v) \ + (((v) << 4) & BM_PXP_HIST_A_CTRL_CLEAR) +#define BP_PXP_HIST_A_CTRL_RSVD0 1 +#define BM_PXP_HIST_A_CTRL_RSVD0 0x0000000E +#define BF_PXP_HIST_A_CTRL_RSVD0(v) \ + (((v) << 1) & BM_PXP_HIST_A_CTRL_RSVD0) +#define BM_PXP_HIST_A_CTRL_ENABLE 0x00000001 +#define BF_PXP_HIST_A_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_HIST_A_CTRL_ENABLE) + +#define HW_PXP_HIST_A_MASK (0x00002a10) + +#define BP_PXP_HIST_A_MASK_MASK_VALUE1 24 +#define BM_PXP_HIST_A_MASK_MASK_VALUE1 0xFF000000 +#define BF_PXP_HIST_A_MASK_MASK_VALUE1(v) \ + (((v) << 24) & BM_PXP_HIST_A_MASK_MASK_VALUE1) +#define BP_PXP_HIST_A_MASK_MASK_VALUE0 16 +#define BM_PXP_HIST_A_MASK_MASK_VALUE0 0x00FF0000 +#define BF_PXP_HIST_A_MASK_MASK_VALUE0(v) \ + (((v) << 16) & BM_PXP_HIST_A_MASK_MASK_VALUE0) +#define BP_PXP_HIST_A_MASK_MASK_WIDTH 13 +#define BM_PXP_HIST_A_MASK_MASK_WIDTH 0x0000E000 +#define BF_PXP_HIST_A_MASK_MASK_WIDTH(v) \ + (((v) << 13) & BM_PXP_HIST_A_MASK_MASK_WIDTH) +#define BP_PXP_HIST_A_MASK_MASK_OFFSET 6 +#define BM_PXP_HIST_A_MASK_MASK_OFFSET 0x00001FC0 +#define BF_PXP_HIST_A_MASK_MASK_OFFSET(v) \ + (((v) << 6) & BM_PXP_HIST_A_MASK_MASK_OFFSET) +#define BP_PXP_HIST_A_MASK_MASK_MODE 4 +#define BM_PXP_HIST_A_MASK_MASK_MODE 0x00000030 +#define BF_PXP_HIST_A_MASK_MASK_MODE(v) \ + (((v) << 4) & BM_PXP_HIST_A_MASK_MASK_MODE) +#define BV_PXP_HIST_A_MASK_MASK_MODE__EQUAL 0x0 +#define BV_PXP_HIST_A_MASK_MASK_MODE__NOT_EQUAL 0x1 +#define BV_PXP_HIST_A_MASK_MASK_MODE__INSIDE 0x2 +#define BV_PXP_HIST_A_MASK_MASK_MODE__OUTSIDE 0x3 +#define BP_PXP_HIST_A_MASK_RSVD0 1 +#define BM_PXP_HIST_A_MASK_RSVD0 0x0000000E +#define BF_PXP_HIST_A_MASK_RSVD0(v) \ + (((v) << 1) & BM_PXP_HIST_A_MASK_RSVD0) +#define BM_PXP_HIST_A_MASK_MASK_EN 0x00000001 +#define BF_PXP_HIST_A_MASK_MASK_EN(v) \ + (((v) << 0) & BM_PXP_HIST_A_MASK_MASK_EN) + +#define HW_PXP_HIST_A_BUF_SIZE (0x00002a20) + +#define BP_PXP_HIST_A_BUF_SIZE_RSVD0 28 +#define BM_PXP_HIST_A_BUF_SIZE_RSVD0 0xF0000000 +#define BF_PXP_HIST_A_BUF_SIZE_RSVD0(v) \ + (((v) << 28) & BM_PXP_HIST_A_BUF_SIZE_RSVD0) +#define BP_PXP_HIST_A_BUF_SIZE_HEIGHT 16 +#define BM_PXP_HIST_A_BUF_SIZE_HEIGHT 0x0FFF0000 +#define BF_PXP_HIST_A_BUF_SIZE_HEIGHT(v) \ + (((v) << 16) & BM_PXP_HIST_A_BUF_SIZE_HEIGHT) +#define BP_PXP_HIST_A_BUF_SIZE_RSVD1 12 +#define BM_PXP_HIST_A_BUF_SIZE_RSVD1 0x0000F000 +#define BF_PXP_HIST_A_BUF_SIZE_RSVD1(v) \ + (((v) << 12) & BM_PXP_HIST_A_BUF_SIZE_RSVD1) +#define BP_PXP_HIST_A_BUF_SIZE_WIDTH 0 +#define BM_PXP_HIST_A_BUF_SIZE_WIDTH 0x00000FFF +#define BF_PXP_HIST_A_BUF_SIZE_WIDTH(v) \ + (((v) << 0) & BM_PXP_HIST_A_BUF_SIZE_WIDTH) + +#define HW_PXP_HIST_A_TOTAL_PIXEL (0x00002a30) + +#define BP_PXP_HIST_A_TOTAL_PIXEL_RSVD0 24 +#define BM_PXP_HIST_A_TOTAL_PIXEL_RSVD0 0xFF000000 +#define BF_PXP_HIST_A_TOTAL_PIXEL_RSVD0(v) \ + (((v) << 24) & BM_PXP_HIST_A_TOTAL_PIXEL_RSVD0) +#define BP_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL 0 +#define BM_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL 0x00FFFFFF +#define BF_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL(v) \ + (((v) << 0) & BM_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL) + +#define HW_PXP_HIST_A_ACTIVE_AREA_X (0x00002a40) + +#define BP_PXP_HIST_A_ACTIVE_AREA_X_RSVD1 28 +#define BM_PXP_HIST_A_ACTIVE_AREA_X_RSVD1 0xF0000000 +#define BF_PXP_HIST_A_ACTIVE_AREA_X_RSVD1(v) \ + (((v) << 28) & BM_PXP_HIST_A_ACTIVE_AREA_X_RSVD1) +#define BP_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET 16 +#define BM_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET 0x0FFF0000 +#define BF_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET(v) \ + (((v) << 16) & BM_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET) +#define BP_PXP_HIST_A_ACTIVE_AREA_X_RSVD0 12 +#define BM_PXP_HIST_A_ACTIVE_AREA_X_RSVD0 0x0000F000 +#define BF_PXP_HIST_A_ACTIVE_AREA_X_RSVD0(v) \ + (((v) << 12) & BM_PXP_HIST_A_ACTIVE_AREA_X_RSVD0) +#define BP_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET 0 +#define BM_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET 0x00000FFF +#define BF_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET(v) \ + (((v) << 0) & BM_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET) + +#define HW_PXP_HIST_A_ACTIVE_AREA_Y (0x00002a50) + +#define BP_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1 28 +#define BM_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1 0xF0000000 +#define BF_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1(v) \ + (((v) << 28) & BM_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1) +#define BP_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET 16 +#define BM_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET 0x0FFF0000 +#define BF_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET(v) \ + (((v) << 16) & BM_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET) +#define BP_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0 12 +#define BM_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0 0x0000F000 +#define BF_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0(v) \ + (((v) << 12) & BM_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0) +#define BP_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET 0 +#define BM_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET 0x00000FFF +#define BF_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET(v) \ + (((v) << 0) & BM_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET) + +#define HW_PXP_HIST_A_RAW_STAT0 (0x00002a60) + +#define BP_PXP_HIST_A_RAW_STAT0_STAT0 0 +#define BM_PXP_HIST_A_RAW_STAT0_STAT0 0xFFFFFFFF +#define BF_PXP_HIST_A_RAW_STAT0_STAT0(v) (v) + +#define HW_PXP_HIST_A_RAW_STAT1 (0x00002a70) + +#define BP_PXP_HIST_A_RAW_STAT1_STAT1 0 +#define BM_PXP_HIST_A_RAW_STAT1_STAT1 0xFFFFFFFF +#define BF_PXP_HIST_A_RAW_STAT1_STAT1(v) (v) + +#define HW_PXP_HIST_B_CTRL (0x00002a80) + +#define BP_PXP_HIST_B_CTRL_RSVD4 27 +#define BM_PXP_HIST_B_CTRL_RSVD4 0xF8000000 +#define BF_PXP_HIST_B_CTRL_RSVD4(v) \ + (((v) << 27) & BM_PXP_HIST_B_CTRL_RSVD4) +#define BP_PXP_HIST_B_CTRL_PIXEL_WIDTH 24 +#define BM_PXP_HIST_B_CTRL_PIXEL_WIDTH 0x07000000 +#define BF_PXP_HIST_B_CTRL_PIXEL_WIDTH(v) \ + (((v) << 24) & BM_PXP_HIST_B_CTRL_PIXEL_WIDTH) +#define BM_PXP_HIST_B_CTRL_RSVD3 0x00800000 +#define BF_PXP_HIST_B_CTRL_RSVD3(v) \ + (((v) << 23) & BM_PXP_HIST_B_CTRL_RSVD3) +#define BP_PXP_HIST_B_CTRL_PIXEL_OFFSET 16 +#define BM_PXP_HIST_B_CTRL_PIXEL_OFFSET 0x007F0000 +#define BF_PXP_HIST_B_CTRL_PIXEL_OFFSET(v) \ + (((v) << 16) & BM_PXP_HIST_B_CTRL_PIXEL_OFFSET) +#define BP_PXP_HIST_B_CTRL_RSVD2 13 +#define BM_PXP_HIST_B_CTRL_RSVD2 0x0000E000 +#define BF_PXP_HIST_B_CTRL_RSVD2(v) \ + (((v) << 13) & BM_PXP_HIST_B_CTRL_RSVD2) +#define BP_PXP_HIST_B_CTRL_STATUS 8 +#define BM_PXP_HIST_B_CTRL_STATUS 0x00001F00 +#define BF_PXP_HIST_B_CTRL_STATUS(v) \ + (((v) << 8) & BM_PXP_HIST_B_CTRL_STATUS) +#define BP_PXP_HIST_B_CTRL_RSVD1 5 +#define BM_PXP_HIST_B_CTRL_RSVD1 0x000000E0 +#define BF_PXP_HIST_B_CTRL_RSVD1(v) \ + (((v) << 5) & BM_PXP_HIST_B_CTRL_RSVD1) +#define BM_PXP_HIST_B_CTRL_CLEAR 0x00000010 +#define BF_PXP_HIST_B_CTRL_CLEAR(v) \ + (((v) << 4) & BM_PXP_HIST_B_CTRL_CLEAR) +#define BP_PXP_HIST_B_CTRL_RSVD0 1 +#define BM_PXP_HIST_B_CTRL_RSVD0 0x0000000E +#define BF_PXP_HIST_B_CTRL_RSVD0(v) \ + (((v) << 1) & BM_PXP_HIST_B_CTRL_RSVD0) +#define BM_PXP_HIST_B_CTRL_ENABLE 0x00000001 +#define BF_PXP_HIST_B_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_HIST_B_CTRL_ENABLE) + +#define HW_PXP_HIST_B_MASK (0x00002a90) + +#define BP_PXP_HIST_B_MASK_MASK_VALUE1 24 +#define BM_PXP_HIST_B_MASK_MASK_VALUE1 0xFF000000 +#define BF_PXP_HIST_B_MASK_MASK_VALUE1(v) \ + (((v) << 24) & BM_PXP_HIST_B_MASK_MASK_VALUE1) +#define BP_PXP_HIST_B_MASK_MASK_VALUE0 16 +#define BM_PXP_HIST_B_MASK_MASK_VALUE0 0x00FF0000 +#define BF_PXP_HIST_B_MASK_MASK_VALUE0(v) \ + (((v) << 16) & BM_PXP_HIST_B_MASK_MASK_VALUE0) +#define BP_PXP_HIST_B_MASK_MASK_WIDTH 13 +#define BM_PXP_HIST_B_MASK_MASK_WIDTH 0x0000E000 +#define BF_PXP_HIST_B_MASK_MASK_WIDTH(v) \ + (((v) << 13) & BM_PXP_HIST_B_MASK_MASK_WIDTH) +#define BP_PXP_HIST_B_MASK_MASK_OFFSET 6 +#define BM_PXP_HIST_B_MASK_MASK_OFFSET 0x00001FC0 +#define BF_PXP_HIST_B_MASK_MASK_OFFSET(v) \ + (((v) << 6) & BM_PXP_HIST_B_MASK_MASK_OFFSET) +#define BP_PXP_HIST_B_MASK_MASK_MODE 4 +#define BM_PXP_HIST_B_MASK_MASK_MODE 0x00000030 +#define BF_PXP_HIST_B_MASK_MASK_MODE(v) \ + (((v) << 4) & BM_PXP_HIST_B_MASK_MASK_MODE) +#define BV_PXP_HIST_B_MASK_MASK_MODE__EQUAL 0x0 +#define BV_PXP_HIST_B_MASK_MASK_MODE__NOT_EQUAL 0x1 +#define BV_PXP_HIST_B_MASK_MASK_MODE__INSIDE 0x2 +#define BV_PXP_HIST_B_MASK_MASK_MODE__OUTSIDE 0x3 +#define BP_PXP_HIST_B_MASK_RSVD0 1 +#define BM_PXP_HIST_B_MASK_RSVD0 0x0000000E +#define BF_PXP_HIST_B_MASK_RSVD0(v) \ + (((v) << 1) & BM_PXP_HIST_B_MASK_RSVD0) +#define BM_PXP_HIST_B_MASK_MASK_EN 0x00000001 +#define BF_PXP_HIST_B_MASK_MASK_EN(v) \ + (((v) << 0) & BM_PXP_HIST_B_MASK_MASK_EN) + +#define HW_PXP_HIST_B_BUF_SIZE (0x00002aa0) + +#define BP_PXP_HIST_B_BUF_SIZE_RSVD0 28 +#define BM_PXP_HIST_B_BUF_SIZE_RSVD0 0xF0000000 +#define BF_PXP_HIST_B_BUF_SIZE_RSVD0(v) \ + (((v) << 28) & BM_PXP_HIST_B_BUF_SIZE_RSVD0) +#define BP_PXP_HIST_B_BUF_SIZE_HEIGHT 16 +#define BM_PXP_HIST_B_BUF_SIZE_HEIGHT 0x0FFF0000 +#define BF_PXP_HIST_B_BUF_SIZE_HEIGHT(v) \ + (((v) << 16) & BM_PXP_HIST_B_BUF_SIZE_HEIGHT) +#define BP_PXP_HIST_B_BUF_SIZE_RSVD1 12 +#define BM_PXP_HIST_B_BUF_SIZE_RSVD1 0x0000F000 +#define BF_PXP_HIST_B_BUF_SIZE_RSVD1(v) \ + (((v) << 12) & BM_PXP_HIST_B_BUF_SIZE_RSVD1) +#define BP_PXP_HIST_B_BUF_SIZE_WIDTH 0 +#define BM_PXP_HIST_B_BUF_SIZE_WIDTH 0x00000FFF +#define BF_PXP_HIST_B_BUF_SIZE_WIDTH(v) \ + (((v) << 0) & BM_PXP_HIST_B_BUF_SIZE_WIDTH) + +#define HW_PXP_HIST_B_TOTAL_PIXEL (0x00002ab0) + +#define BP_PXP_HIST_B_TOTAL_PIXEL_RSVD0 24 +#define BM_PXP_HIST_B_TOTAL_PIXEL_RSVD0 0xFF000000 +#define BF_PXP_HIST_B_TOTAL_PIXEL_RSVD0(v) \ + (((v) << 24) & BM_PXP_HIST_B_TOTAL_PIXEL_RSVD0) +#define BP_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL 0 +#define BM_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL 0x00FFFFFF +#define BF_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL(v) \ + (((v) << 0) & BM_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL) + +#define HW_PXP_HIST_B_ACTIVE_AREA_X (0x00002ac0) + +#define BP_PXP_HIST_B_ACTIVE_AREA_X_RSVD1 28 +#define BM_PXP_HIST_B_ACTIVE_AREA_X_RSVD1 0xF0000000 +#define BF_PXP_HIST_B_ACTIVE_AREA_X_RSVD1(v) \ + (((v) << 28) & BM_PXP_HIST_B_ACTIVE_AREA_X_RSVD1) +#define BP_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET 16 +#define BM_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET 0x0FFF0000 +#define BF_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET(v) \ + (((v) << 16) & BM_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET) +#define BP_PXP_HIST_B_ACTIVE_AREA_X_RSVD0 12 +#define BM_PXP_HIST_B_ACTIVE_AREA_X_RSVD0 0x0000F000 +#define BF_PXP_HIST_B_ACTIVE_AREA_X_RSVD0(v) \ + (((v) << 12) & BM_PXP_HIST_B_ACTIVE_AREA_X_RSVD0) +#define BP_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET 0 +#define BM_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET 0x00000FFF +#define BF_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET(v) \ + (((v) << 0) & BM_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET) + +#define HW_PXP_HIST_B_ACTIVE_AREA_Y (0x00002ad0) + +#define BP_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1 28 +#define BM_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1 0xF0000000 +#define BF_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1(v) \ + (((v) << 28) & BM_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1) +#define BP_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET 16 +#define BM_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET 0x0FFF0000 +#define BF_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET(v) \ + (((v) << 16) & BM_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET) +#define BP_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0 12 +#define BM_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0 0x0000F000 +#define BF_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0(v) \ + (((v) << 12) & BM_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0) +#define BP_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET 0 +#define BM_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET 0x00000FFF +#define BF_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET(v) \ + (((v) << 0) & BM_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET) + +#define HW_PXP_HIST_B_RAW_STAT0 (0x00002ae0) + +#define BP_PXP_HIST_B_RAW_STAT0_STAT0 0 +#define BM_PXP_HIST_B_RAW_STAT0_STAT0 0xFFFFFFFF +#define BF_PXP_HIST_B_RAW_STAT0_STAT0(v) (v) + +#define HW_PXP_HIST_B_RAW_STAT1 (0x00002af0) + +#define BP_PXP_HIST_B_RAW_STAT1_STAT1 0 +#define BM_PXP_HIST_B_RAW_STAT1_STAT1 0xFFFFFFFF +#define BF_PXP_HIST_B_RAW_STAT1_STAT1(v) (v) + +#define HW_PXP_HIST2_PARAM (0x00002b00) + +#define BP_PXP_HIST2_PARAM_RSVD 16 +#define BM_PXP_HIST2_PARAM_RSVD 0xFFFF0000 +#define BF_PXP_HIST2_PARAM_RSVD(v) \ + (((v) << 16) & BM_PXP_HIST2_PARAM_RSVD) +#define BP_PXP_HIST2_PARAM_RSVD1 14 +#define BM_PXP_HIST2_PARAM_RSVD1 0x0000C000 +#define BF_PXP_HIST2_PARAM_RSVD1(v) \ + (((v) << 14) & BM_PXP_HIST2_PARAM_RSVD1) +#define BP_PXP_HIST2_PARAM_VALUE1 8 +#define BM_PXP_HIST2_PARAM_VALUE1 0x00003F00 +#define BF_PXP_HIST2_PARAM_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST2_PARAM_VALUE1) +#define BP_PXP_HIST2_PARAM_RSVD0 6 +#define BM_PXP_HIST2_PARAM_RSVD0 0x000000C0 +#define BF_PXP_HIST2_PARAM_RSVD0(v) \ + (((v) << 6) & BM_PXP_HIST2_PARAM_RSVD0) +#define BP_PXP_HIST2_PARAM_VALUE0 0 +#define BM_PXP_HIST2_PARAM_VALUE0 0x0000003F +#define BF_PXP_HIST2_PARAM_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST2_PARAM_VALUE0) + +#define HW_PXP_HIST4_PARAM (0x00002b10) + +#define BP_PXP_HIST4_PARAM_RSVD3 30 +#define BM_PXP_HIST4_PARAM_RSVD3 0xC0000000 +#define BF_PXP_HIST4_PARAM_RSVD3(v) \ + (((v) << 30) & BM_PXP_HIST4_PARAM_RSVD3) +#define BP_PXP_HIST4_PARAM_VALUE3 24 +#define BM_PXP_HIST4_PARAM_VALUE3 0x3F000000 +#define BF_PXP_HIST4_PARAM_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST4_PARAM_VALUE3) +#define BP_PXP_HIST4_PARAM_RSVD2 22 +#define BM_PXP_HIST4_PARAM_RSVD2 0x00C00000 +#define BF_PXP_HIST4_PARAM_RSVD2(v) \ + (((v) << 22) & BM_PXP_HIST4_PARAM_RSVD2) +#define BP_PXP_HIST4_PARAM_VALUE2 16 +#define BM_PXP_HIST4_PARAM_VALUE2 0x003F0000 +#define BF_PXP_HIST4_PARAM_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST4_PARAM_VALUE2) +#define BP_PXP_HIST4_PARAM_RSVD1 14 +#define BM_PXP_HIST4_PARAM_RSVD1 0x0000C000 +#define BF_PXP_HIST4_PARAM_RSVD1(v) \ + (((v) << 14) & BM_PXP_HIST4_PARAM_RSVD1) +#define BP_PXP_HIST4_PARAM_VALUE1 8 +#define BM_PXP_HIST4_PARAM_VALUE1 0x00003F00 +#define BF_PXP_HIST4_PARAM_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST4_PARAM_VALUE1) +#define BP_PXP_HIST4_PARAM_RSVD0 6 +#define BM_PXP_HIST4_PARAM_RSVD0 0x000000C0 +#define BF_PXP_HIST4_PARAM_RSVD0(v) \ + (((v) << 6) & BM_PXP_HIST4_PARAM_RSVD0) +#define BP_PXP_HIST4_PARAM_VALUE0 0 +#define BM_PXP_HIST4_PARAM_VALUE0 0x0000003F +#define BF_PXP_HIST4_PARAM_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST4_PARAM_VALUE0) + +#define HW_PXP_HIST8_PARAM0 (0x00002b20) + +#define BP_PXP_HIST8_PARAM0_RSVD3 30 +#define BM_PXP_HIST8_PARAM0_RSVD3 0xC0000000 +#define BF_PXP_HIST8_PARAM0_RSVD3(v) \ + (((v) << 30) & BM_PXP_HIST8_PARAM0_RSVD3) +#define BP_PXP_HIST8_PARAM0_VALUE3 24 +#define BM_PXP_HIST8_PARAM0_VALUE3 0x3F000000 +#define BF_PXP_HIST8_PARAM0_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST8_PARAM0_VALUE3) +#define BP_PXP_HIST8_PARAM0_RSVD2 22 +#define BM_PXP_HIST8_PARAM0_RSVD2 0x00C00000 +#define BF_PXP_HIST8_PARAM0_RSVD2(v) \ + (((v) << 22) & BM_PXP_HIST8_PARAM0_RSVD2) +#define BP_PXP_HIST8_PARAM0_VALUE2 16 +#define BM_PXP_HIST8_PARAM0_VALUE2 0x003F0000 +#define BF_PXP_HIST8_PARAM0_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST8_PARAM0_VALUE2) +#define BP_PXP_HIST8_PARAM0_RSVD1 14 +#define BM_PXP_HIST8_PARAM0_RSVD1 0x0000C000 +#define BF_PXP_HIST8_PARAM0_RSVD1(v) \ + (((v) << 14) & BM_PXP_HIST8_PARAM0_RSVD1) +#define BP_PXP_HIST8_PARAM0_VALUE1 8 +#define BM_PXP_HIST8_PARAM0_VALUE1 0x00003F00 +#define BF_PXP_HIST8_PARAM0_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST8_PARAM0_VALUE1) +#define BP_PXP_HIST8_PARAM0_RSVD0 6 +#define BM_PXP_HIST8_PARAM0_RSVD0 0x000000C0 +#define BF_PXP_HIST8_PARAM0_RSVD0(v) \ + (((v) << 6) & BM_PXP_HIST8_PARAM0_RSVD0) +#define BP_PXP_HIST8_PARAM0_VALUE0 0 +#define BM_PXP_HIST8_PARAM0_VALUE0 0x0000003F +#define BF_PXP_HIST8_PARAM0_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST8_PARAM0_VALUE0) + +#define HW_PXP_HIST8_PARAM1 (0x00002b30) + +#define BP_PXP_HIST8_PARAM1_RSVD7 30 +#define BM_PXP_HIST8_PARAM1_RSVD7 0xC0000000 +#define BF_PXP_HIST8_PARAM1_RSVD7(v) \ + (((v) << 30) & BM_PXP_HIST8_PARAM1_RSVD7) +#define BP_PXP_HIST8_PARAM1_VALUE7 24 +#define BM_PXP_HIST8_PARAM1_VALUE7 0x3F000000 +#define BF_PXP_HIST8_PARAM1_VALUE7(v) \ + (((v) << 24) & BM_PXP_HIST8_PARAM1_VALUE7) +#define BP_PXP_HIST8_PARAM1_RSVD6 22 +#define BM_PXP_HIST8_PARAM1_RSVD6 0x00C00000 +#define BF_PXP_HIST8_PARAM1_RSVD6(v) \ + (((v) << 22) & BM_PXP_HIST8_PARAM1_RSVD6) +#define BP_PXP_HIST8_PARAM1_VALUE6 16 +#define BM_PXP_HIST8_PARAM1_VALUE6 0x003F0000 +#define BF_PXP_HIST8_PARAM1_VALUE6(v) \ + (((v) << 16) & BM_PXP_HIST8_PARAM1_VALUE6) +#define BP_PXP_HIST8_PARAM1_RSVD5 14 +#define BM_PXP_HIST8_PARAM1_RSVD5 0x0000C000 +#define BF_PXP_HIST8_PARAM1_RSVD5(v) \ + (((v) << 14) & BM_PXP_HIST8_PARAM1_RSVD5) +#define BP_PXP_HIST8_PARAM1_VALUE5 8 +#define BM_PXP_HIST8_PARAM1_VALUE5 0x00003F00 +#define BF_PXP_HIST8_PARAM1_VALUE5(v) \ + (((v) << 8) & BM_PXP_HIST8_PARAM1_VALUE5) +#define BP_PXP_HIST8_PARAM1_RSVD4 6 +#define BM_PXP_HIST8_PARAM1_RSVD4 0x000000C0 +#define BF_PXP_HIST8_PARAM1_RSVD4(v) \ + (((v) << 6) & BM_PXP_HIST8_PARAM1_RSVD4) +#define BP_PXP_HIST8_PARAM1_VALUE4 0 +#define BM_PXP_HIST8_PARAM1_VALUE4 0x0000003F +#define BF_PXP_HIST8_PARAM1_VALUE4(v) \ + (((v) << 0) & BM_PXP_HIST8_PARAM1_VALUE4) + +#define HW_PXP_HIST16_PARAM0 (0x00002b40) + +#define BP_PXP_HIST16_PARAM0_RSVD3 30 +#define BM_PXP_HIST16_PARAM0_RSVD3 0xC0000000 +#define BF_PXP_HIST16_PARAM0_RSVD3(v) \ + (((v) << 30) & BM_PXP_HIST16_PARAM0_RSVD3) +#define BP_PXP_HIST16_PARAM0_VALUE3 24 +#define BM_PXP_HIST16_PARAM0_VALUE3 0x3F000000 +#define BF_PXP_HIST16_PARAM0_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM0_VALUE3) +#define BP_PXP_HIST16_PARAM0_RSVD2 22 +#define BM_PXP_HIST16_PARAM0_RSVD2 0x00C00000 +#define BF_PXP_HIST16_PARAM0_RSVD2(v) \ + (((v) << 22) & BM_PXP_HIST16_PARAM0_RSVD2) +#define BP_PXP_HIST16_PARAM0_VALUE2 16 +#define BM_PXP_HIST16_PARAM0_VALUE2 0x003F0000 +#define BF_PXP_HIST16_PARAM0_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM0_VALUE2) +#define BP_PXP_HIST16_PARAM0_RSVD1 14 +#define BM_PXP_HIST16_PARAM0_RSVD1 0x0000C000 +#define BF_PXP_HIST16_PARAM0_RSVD1(v) \ + (((v) << 14) & BM_PXP_HIST16_PARAM0_RSVD1) +#define BP_PXP_HIST16_PARAM0_VALUE1 8 +#define BM_PXP_HIST16_PARAM0_VALUE1 0x00003F00 +#define BF_PXP_HIST16_PARAM0_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM0_VALUE1) +#define BP_PXP_HIST16_PARAM0_RSVD0 6 +#define BM_PXP_HIST16_PARAM0_RSVD0 0x000000C0 +#define BF_PXP_HIST16_PARAM0_RSVD0(v) \ + (((v) << 6) & BM_PXP_HIST16_PARAM0_RSVD0) +#define BP_PXP_HIST16_PARAM0_VALUE0 0 +#define BM_PXP_HIST16_PARAM0_VALUE0 0x0000003F +#define BF_PXP_HIST16_PARAM0_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM0_VALUE0) + +#define HW_PXP_HIST16_PARAM1 (0x00002b50) + +#define BP_PXP_HIST16_PARAM1_RSVD7 30 +#define BM_PXP_HIST16_PARAM1_RSVD7 0xC0000000 +#define BF_PXP_HIST16_PARAM1_RSVD7(v) \ + (((v) << 30) & BM_PXP_HIST16_PARAM1_RSVD7) +#define BP_PXP_HIST16_PARAM1_VALUE7 24 +#define BM_PXP_HIST16_PARAM1_VALUE7 0x3F000000 +#define BF_PXP_HIST16_PARAM1_VALUE7(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM1_VALUE7) +#define BP_PXP_HIST16_PARAM1_RSVD6 22 +#define BM_PXP_HIST16_PARAM1_RSVD6 0x00C00000 +#define BF_PXP_HIST16_PARAM1_RSVD6(v) \ + (((v) << 22) & BM_PXP_HIST16_PARAM1_RSVD6) +#define BP_PXP_HIST16_PARAM1_VALUE6 16 +#define BM_PXP_HIST16_PARAM1_VALUE6 0x003F0000 +#define BF_PXP_HIST16_PARAM1_VALUE6(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM1_VALUE6) +#define BP_PXP_HIST16_PARAM1_RSVD5 14 +#define BM_PXP_HIST16_PARAM1_RSVD5 0x0000C000 +#define BF_PXP_HIST16_PARAM1_RSVD5(v) \ + (((v) << 14) & BM_PXP_HIST16_PARAM1_RSVD5) +#define BP_PXP_HIST16_PARAM1_VALUE5 8 +#define BM_PXP_HIST16_PARAM1_VALUE5 0x00003F00 +#define BF_PXP_HIST16_PARAM1_VALUE5(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM1_VALUE5) +#define BP_PXP_HIST16_PARAM1_RSVD4 6 +#define BM_PXP_HIST16_PARAM1_RSVD4 0x000000C0 +#define BF_PXP_HIST16_PARAM1_RSVD4(v) \ + (((v) << 6) & BM_PXP_HIST16_PARAM1_RSVD4) +#define BP_PXP_HIST16_PARAM1_VALUE4 0 +#define BM_PXP_HIST16_PARAM1_VALUE4 0x0000003F +#define BF_PXP_HIST16_PARAM1_VALUE4(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM1_VALUE4) + +#define HW_PXP_HIST16_PARAM2 (0x00002b60) + +#define BP_PXP_HIST16_PARAM2_RSVD11 30 +#define BM_PXP_HIST16_PARAM2_RSVD11 0xC0000000 +#define BF_PXP_HIST16_PARAM2_RSVD11(v) \ + (((v) << 30) & BM_PXP_HIST16_PARAM2_RSVD11) +#define BP_PXP_HIST16_PARAM2_VALUE11 24 +#define BM_PXP_HIST16_PARAM2_VALUE11 0x3F000000 +#define BF_PXP_HIST16_PARAM2_VALUE11(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM2_VALUE11) +#define BP_PXP_HIST16_PARAM2_RSVD10 22 +#define BM_PXP_HIST16_PARAM2_RSVD10 0x00C00000 +#define BF_PXP_HIST16_PARAM2_RSVD10(v) \ + (((v) << 22) & BM_PXP_HIST16_PARAM2_RSVD10) +#define BP_PXP_HIST16_PARAM2_VALUE10 16 +#define BM_PXP_HIST16_PARAM2_VALUE10 0x003F0000 +#define BF_PXP_HIST16_PARAM2_VALUE10(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM2_VALUE10) +#define BP_PXP_HIST16_PARAM2_RSVD9 14 +#define BM_PXP_HIST16_PARAM2_RSVD9 0x0000C000 +#define BF_PXP_HIST16_PARAM2_RSVD9(v) \ + (((v) << 14) & BM_PXP_HIST16_PARAM2_RSVD9) +#define BP_PXP_HIST16_PARAM2_VALUE9 8 +#define BM_PXP_HIST16_PARAM2_VALUE9 0x00003F00 +#define BF_PXP_HIST16_PARAM2_VALUE9(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM2_VALUE9) +#define BP_PXP_HIST16_PARAM2_RSVD8 6 +#define BM_PXP_HIST16_PARAM2_RSVD8 0x000000C0 +#define BF_PXP_HIST16_PARAM2_RSVD8(v) \ + (((v) << 6) & BM_PXP_HIST16_PARAM2_RSVD8) +#define BP_PXP_HIST16_PARAM2_VALUE8 0 +#define BM_PXP_HIST16_PARAM2_VALUE8 0x0000003F +#define BF_PXP_HIST16_PARAM2_VALUE8(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM2_VALUE8) + +#define HW_PXP_HIST16_PARAM3 (0x00002b70) + +#define BP_PXP_HIST16_PARAM3_RSVD15 30 +#define BM_PXP_HIST16_PARAM3_RSVD15 0xC0000000 +#define BF_PXP_HIST16_PARAM3_RSVD15(v) \ + (((v) << 30) & BM_PXP_HIST16_PARAM3_RSVD15) +#define BP_PXP_HIST16_PARAM3_VALUE15 24 +#define BM_PXP_HIST16_PARAM3_VALUE15 0x3F000000 +#define BF_PXP_HIST16_PARAM3_VALUE15(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM3_VALUE15) +#define BP_PXP_HIST16_PARAM3_RSVD14 22 +#define BM_PXP_HIST16_PARAM3_RSVD14 0x00C00000 +#define BF_PXP_HIST16_PARAM3_RSVD14(v) \ + (((v) << 22) & BM_PXP_HIST16_PARAM3_RSVD14) +#define BP_PXP_HIST16_PARAM3_VALUE14 16 +#define BM_PXP_HIST16_PARAM3_VALUE14 0x003F0000 +#define BF_PXP_HIST16_PARAM3_VALUE14(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM3_VALUE14) +#define BP_PXP_HIST16_PARAM3_RSVD13 14 +#define BM_PXP_HIST16_PARAM3_RSVD13 0x0000C000 +#define BF_PXP_HIST16_PARAM3_RSVD13(v) \ + (((v) << 14) & BM_PXP_HIST16_PARAM3_RSVD13) +#define BP_PXP_HIST16_PARAM3_VALUE13 8 +#define BM_PXP_HIST16_PARAM3_VALUE13 0x00003F00 +#define BF_PXP_HIST16_PARAM3_VALUE13(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM3_VALUE13) +#define BP_PXP_HIST16_PARAM3_RSVD12 6 +#define BM_PXP_HIST16_PARAM3_RSVD12 0x000000C0 +#define BF_PXP_HIST16_PARAM3_RSVD12(v) \ + (((v) << 6) & BM_PXP_HIST16_PARAM3_RSVD12) +#define BP_PXP_HIST16_PARAM3_VALUE12 0 +#define BM_PXP_HIST16_PARAM3_VALUE12 0x0000003F +#define BF_PXP_HIST16_PARAM3_VALUE12(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM3_VALUE12) + +#define HW_PXP_HIST32_PARAM0 (0x00002b80) + +#define BP_PXP_HIST32_PARAM0_RSVD3 30 +#define BM_PXP_HIST32_PARAM0_RSVD3 0xC0000000 +#define BF_PXP_HIST32_PARAM0_RSVD3(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM0_RSVD3) +#define BP_PXP_HIST32_PARAM0_VALUE3 24 +#define BM_PXP_HIST32_PARAM0_VALUE3 0x3F000000 +#define BF_PXP_HIST32_PARAM0_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM0_VALUE3) +#define BP_PXP_HIST32_PARAM0_RSVD2 22 +#define BM_PXP_HIST32_PARAM0_RSVD2 0x00C00000 +#define BF_PXP_HIST32_PARAM0_RSVD2(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM0_RSVD2) +#define BP_PXP_HIST32_PARAM0_VALUE2 16 +#define BM_PXP_HIST32_PARAM0_VALUE2 0x003F0000 +#define BF_PXP_HIST32_PARAM0_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM0_VALUE2) +#define BP_PXP_HIST32_PARAM0_RSVD1 14 +#define BM_PXP_HIST32_PARAM0_RSVD1 0x0000C000 +#define BF_PXP_HIST32_PARAM0_RSVD1(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM0_RSVD1) +#define BP_PXP_HIST32_PARAM0_VALUE1 8 +#define BM_PXP_HIST32_PARAM0_VALUE1 0x00003F00 +#define BF_PXP_HIST32_PARAM0_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM0_VALUE1) +#define BP_PXP_HIST32_PARAM0_RSVD0 6 +#define BM_PXP_HIST32_PARAM0_RSVD0 0x000000C0 +#define BF_PXP_HIST32_PARAM0_RSVD0(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM0_RSVD0) +#define BP_PXP_HIST32_PARAM0_VALUE0 0 +#define BM_PXP_HIST32_PARAM0_VALUE0 0x0000003F +#define BF_PXP_HIST32_PARAM0_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM0_VALUE0) + +#define HW_PXP_HIST32_PARAM1 (0x00002b90) + +#define BP_PXP_HIST32_PARAM1_RSVD7 30 +#define BM_PXP_HIST32_PARAM1_RSVD7 0xC0000000 +#define BF_PXP_HIST32_PARAM1_RSVD7(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM1_RSVD7) +#define BP_PXP_HIST32_PARAM1_VALUE7 24 +#define BM_PXP_HIST32_PARAM1_VALUE7 0x3F000000 +#define BF_PXP_HIST32_PARAM1_VALUE7(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM1_VALUE7) +#define BP_PXP_HIST32_PARAM1_RSVD6 22 +#define BM_PXP_HIST32_PARAM1_RSVD6 0x00C00000 +#define BF_PXP_HIST32_PARAM1_RSVD6(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM1_RSVD6) +#define BP_PXP_HIST32_PARAM1_VALUE6 16 +#define BM_PXP_HIST32_PARAM1_VALUE6 0x003F0000 +#define BF_PXP_HIST32_PARAM1_VALUE6(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM1_VALUE6) +#define BP_PXP_HIST32_PARAM1_RSVD5 14 +#define BM_PXP_HIST32_PARAM1_RSVD5 0x0000C000 +#define BF_PXP_HIST32_PARAM1_RSVD5(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM1_RSVD5) +#define BP_PXP_HIST32_PARAM1_VALUE5 8 +#define BM_PXP_HIST32_PARAM1_VALUE5 0x00003F00 +#define BF_PXP_HIST32_PARAM1_VALUE5(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM1_VALUE5) +#define BP_PXP_HIST32_PARAM1_RSVD4 6 +#define BM_PXP_HIST32_PARAM1_RSVD4 0x000000C0 +#define BF_PXP_HIST32_PARAM1_RSVD4(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM1_RSVD4) +#define BP_PXP_HIST32_PARAM1_VALUE4 0 +#define BM_PXP_HIST32_PARAM1_VALUE4 0x0000003F +#define BF_PXP_HIST32_PARAM1_VALUE4(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM1_VALUE4) + +#define HW_PXP_HIST32_PARAM2 (0x00002ba0) + +#define BP_PXP_HIST32_PARAM2_RSVD11 30 +#define BM_PXP_HIST32_PARAM2_RSVD11 0xC0000000 +#define BF_PXP_HIST32_PARAM2_RSVD11(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM2_RSVD11) +#define BP_PXP_HIST32_PARAM2_VALUE11 24 +#define BM_PXP_HIST32_PARAM2_VALUE11 0x3F000000 +#define BF_PXP_HIST32_PARAM2_VALUE11(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM2_VALUE11) +#define BP_PXP_HIST32_PARAM2_RSVD10 22 +#define BM_PXP_HIST32_PARAM2_RSVD10 0x00C00000 +#define BF_PXP_HIST32_PARAM2_RSVD10(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM2_RSVD10) +#define BP_PXP_HIST32_PARAM2_VALUE10 16 +#define BM_PXP_HIST32_PARAM2_VALUE10 0x003F0000 +#define BF_PXP_HIST32_PARAM2_VALUE10(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM2_VALUE10) +#define BP_PXP_HIST32_PARAM2_RSVD9 14 +#define BM_PXP_HIST32_PARAM2_RSVD9 0x0000C000 +#define BF_PXP_HIST32_PARAM2_RSVD9(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM2_RSVD9) +#define BP_PXP_HIST32_PARAM2_VALUE9 8 +#define BM_PXP_HIST32_PARAM2_VALUE9 0x00003F00 +#define BF_PXP_HIST32_PARAM2_VALUE9(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM2_VALUE9) +#define BP_PXP_HIST32_PARAM2_RSVD8 6 +#define BM_PXP_HIST32_PARAM2_RSVD8 0x000000C0 +#define BF_PXP_HIST32_PARAM2_RSVD8(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM2_RSVD8) +#define BP_PXP_HIST32_PARAM2_VALUE8 0 +#define BM_PXP_HIST32_PARAM2_VALUE8 0x0000003F +#define BF_PXP_HIST32_PARAM2_VALUE8(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM2_VALUE8) + +#define HW_PXP_HIST32_PARAM3 (0x00002bb0) + +#define BP_PXP_HIST32_PARAM3_RSVD15 30 +#define BM_PXP_HIST32_PARAM3_RSVD15 0xC0000000 +#define BF_PXP_HIST32_PARAM3_RSVD15(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM3_RSVD15) +#define BP_PXP_HIST32_PARAM3_VALUE15 24 +#define BM_PXP_HIST32_PARAM3_VALUE15 0x3F000000 +#define BF_PXP_HIST32_PARAM3_VALUE15(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM3_VALUE15) +#define BP_PXP_HIST32_PARAM3_RSVD14 22 +#define BM_PXP_HIST32_PARAM3_RSVD14 0x00C00000 +#define BF_PXP_HIST32_PARAM3_RSVD14(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM3_RSVD14) +#define BP_PXP_HIST32_PARAM3_VALUE14 16 +#define BM_PXP_HIST32_PARAM3_VALUE14 0x003F0000 +#define BF_PXP_HIST32_PARAM3_VALUE14(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM3_VALUE14) +#define BP_PXP_HIST32_PARAM3_RSVD13 14 +#define BM_PXP_HIST32_PARAM3_RSVD13 0x0000C000 +#define BF_PXP_HIST32_PARAM3_RSVD13(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM3_RSVD13) +#define BP_PXP_HIST32_PARAM3_VALUE13 8 +#define BM_PXP_HIST32_PARAM3_VALUE13 0x00003F00 +#define BF_PXP_HIST32_PARAM3_VALUE13(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM3_VALUE13) +#define BP_PXP_HIST32_PARAM3_RSVD12 6 +#define BM_PXP_HIST32_PARAM3_RSVD12 0x000000C0 +#define BF_PXP_HIST32_PARAM3_RSVD12(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM3_RSVD12) +#define BP_PXP_HIST32_PARAM3_VALUE12 0 +#define BM_PXP_HIST32_PARAM3_VALUE12 0x0000003F +#define BF_PXP_HIST32_PARAM3_VALUE12(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM3_VALUE12) + +#define HW_PXP_HIST32_PARAM4 (0x00002bc0) + +#define BP_PXP_HIST32_PARAM4_RSVD3 30 +#define BM_PXP_HIST32_PARAM4_RSVD3 0xC0000000 +#define BF_PXP_HIST32_PARAM4_RSVD3(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM4_RSVD3) +#define BP_PXP_HIST32_PARAM4_VALUE19 24 +#define BM_PXP_HIST32_PARAM4_VALUE19 0x3F000000 +#define BF_PXP_HIST32_PARAM4_VALUE19(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM4_VALUE19) +#define BP_PXP_HIST32_PARAM4_RSVD2 22 +#define BM_PXP_HIST32_PARAM4_RSVD2 0x00C00000 +#define BF_PXP_HIST32_PARAM4_RSVD2(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM4_RSVD2) +#define BP_PXP_HIST32_PARAM4_VALUE18 16 +#define BM_PXP_HIST32_PARAM4_VALUE18 0x003F0000 +#define BF_PXP_HIST32_PARAM4_VALUE18(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM4_VALUE18) +#define BP_PXP_HIST32_PARAM4_RSVD1 14 +#define BM_PXP_HIST32_PARAM4_RSVD1 0x0000C000 +#define BF_PXP_HIST32_PARAM4_RSVD1(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM4_RSVD1) +#define BP_PXP_HIST32_PARAM4_VALUE17 8 +#define BM_PXP_HIST32_PARAM4_VALUE17 0x00003F00 +#define BF_PXP_HIST32_PARAM4_VALUE17(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM4_VALUE17) +#define BP_PXP_HIST32_PARAM4_RSVD0 6 +#define BM_PXP_HIST32_PARAM4_RSVD0 0x000000C0 +#define BF_PXP_HIST32_PARAM4_RSVD0(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM4_RSVD0) +#define BP_PXP_HIST32_PARAM4_VALUE16 0 +#define BM_PXP_HIST32_PARAM4_VALUE16 0x0000003F +#define BF_PXP_HIST32_PARAM4_VALUE16(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM4_VALUE16) + +#define HW_PXP_HIST32_PARAM5 (0x00002bd0) + +#define BP_PXP_HIST32_PARAM5_RSVD7 30 +#define BM_PXP_HIST32_PARAM5_RSVD7 0xC0000000 +#define BF_PXP_HIST32_PARAM5_RSVD7(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM5_RSVD7) +#define BP_PXP_HIST32_PARAM5_VALUE23 24 +#define BM_PXP_HIST32_PARAM5_VALUE23 0x3F000000 +#define BF_PXP_HIST32_PARAM5_VALUE23(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM5_VALUE23) +#define BP_PXP_HIST32_PARAM5_RSVD6 22 +#define BM_PXP_HIST32_PARAM5_RSVD6 0x00C00000 +#define BF_PXP_HIST32_PARAM5_RSVD6(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM5_RSVD6) +#define BP_PXP_HIST32_PARAM5_VALUE22 16 +#define BM_PXP_HIST32_PARAM5_VALUE22 0x003F0000 +#define BF_PXP_HIST32_PARAM5_VALUE22(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM5_VALUE22) +#define BP_PXP_HIST32_PARAM5_RSVD5 14 +#define BM_PXP_HIST32_PARAM5_RSVD5 0x0000C000 +#define BF_PXP_HIST32_PARAM5_RSVD5(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM5_RSVD5) +#define BP_PXP_HIST32_PARAM5_VALUE21 8 +#define BM_PXP_HIST32_PARAM5_VALUE21 0x00003F00 +#define BF_PXP_HIST32_PARAM5_VALUE21(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM5_VALUE21) +#define BP_PXP_HIST32_PARAM5_RSVD4 6 +#define BM_PXP_HIST32_PARAM5_RSVD4 0x000000C0 +#define BF_PXP_HIST32_PARAM5_RSVD4(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM5_RSVD4) +#define BP_PXP_HIST32_PARAM5_VALUE20 0 +#define BM_PXP_HIST32_PARAM5_VALUE20 0x0000003F +#define BF_PXP_HIST32_PARAM5_VALUE20(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM5_VALUE20) + +#define HW_PXP_HIST32_PARAM6 (0x00002be0) + +#define BP_PXP_HIST32_PARAM6_RSVD11 30 +#define BM_PXP_HIST32_PARAM6_RSVD11 0xC0000000 +#define BF_PXP_HIST32_PARAM6_RSVD11(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM6_RSVD11) +#define BP_PXP_HIST32_PARAM6_VALUE27 24 +#define BM_PXP_HIST32_PARAM6_VALUE27 0x3F000000 +#define BF_PXP_HIST32_PARAM6_VALUE27(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM6_VALUE27) +#define BP_PXP_HIST32_PARAM6_RSVD10 22 +#define BM_PXP_HIST32_PARAM6_RSVD10 0x00C00000 +#define BF_PXP_HIST32_PARAM6_RSVD10(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM6_RSVD10) +#define BP_PXP_HIST32_PARAM6_VALUE26 16 +#define BM_PXP_HIST32_PARAM6_VALUE26 0x003F0000 +#define BF_PXP_HIST32_PARAM6_VALUE26(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM6_VALUE26) +#define BP_PXP_HIST32_PARAM6_RSVD9 14 +#define BM_PXP_HIST32_PARAM6_RSVD9 0x0000C000 +#define BF_PXP_HIST32_PARAM6_RSVD9(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM6_RSVD9) +#define BP_PXP_HIST32_PARAM6_VALUE25 8 +#define BM_PXP_HIST32_PARAM6_VALUE25 0x00003F00 +#define BF_PXP_HIST32_PARAM6_VALUE25(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM6_VALUE25) +#define BP_PXP_HIST32_PARAM6_RSVD8 6 +#define BM_PXP_HIST32_PARAM6_RSVD8 0x000000C0 +#define BF_PXP_HIST32_PARAM6_RSVD8(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM6_RSVD8) +#define BP_PXP_HIST32_PARAM6_VALUE24 0 +#define BM_PXP_HIST32_PARAM6_VALUE24 0x0000003F +#define BF_PXP_HIST32_PARAM6_VALUE24(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM6_VALUE24) + +#define HW_PXP_HIST32_PARAM7 (0x00002bf0) + +#define BP_PXP_HIST32_PARAM7_RSVD15 30 +#define BM_PXP_HIST32_PARAM7_RSVD15 0xC0000000 +#define BF_PXP_HIST32_PARAM7_RSVD15(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM7_RSVD15) +#define BP_PXP_HIST32_PARAM7_VALUE31 24 +#define BM_PXP_HIST32_PARAM7_VALUE31 0x3F000000 +#define BF_PXP_HIST32_PARAM7_VALUE31(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM7_VALUE31) +#define BP_PXP_HIST32_PARAM7_RSVD14 22 +#define BM_PXP_HIST32_PARAM7_RSVD14 0x00C00000 +#define BF_PXP_HIST32_PARAM7_RSVD14(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM7_RSVD14) +#define BP_PXP_HIST32_PARAM7_VALUE30 16 +#define BM_PXP_HIST32_PARAM7_VALUE30 0x003F0000 +#define BF_PXP_HIST32_PARAM7_VALUE30(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM7_VALUE30) +#define BP_PXP_HIST32_PARAM7_RSVD13 14 +#define BM_PXP_HIST32_PARAM7_RSVD13 0x0000C000 +#define BF_PXP_HIST32_PARAM7_RSVD13(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM7_RSVD13) +#define BP_PXP_HIST32_PARAM7_VALUE29 8 +#define BM_PXP_HIST32_PARAM7_VALUE29 0x00003F00 +#define BF_PXP_HIST32_PARAM7_VALUE29(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM7_VALUE29) +#define BP_PXP_HIST32_PARAM7_RSVD2 6 +#define BM_PXP_HIST32_PARAM7_RSVD2 0x000000C0 +#define BF_PXP_HIST32_PARAM7_RSVD2(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM7_RSVD2) +#define BP_PXP_HIST32_PARAM7_VALUE28 0 +#define BM_PXP_HIST32_PARAM7_VALUE28 0x0000003F +#define BF_PXP_HIST32_PARAM7_VALUE28(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM7_VALUE28) + +#define HW_PXP_COMP_CTRL (0x00002c00) +#define HW_PXP_COMP_CTRL_SET (0x00002c04) +#define HW_PXP_COMP_CTRL_CLR (0x00002c08) +#define HW_PXP_COMP_CTRL_TOG (0x00002c0c) + +#define BP_PXP_COMP_CTRL_RSVD0 9 +#define BM_PXP_COMP_CTRL_RSVD0 0xFFFFFE00 +#define BF_PXP_COMP_CTRL_RSVD0(v) \ + (((v) << 9) & BM_PXP_COMP_CTRL_RSVD0) +#define BM_PXP_COMP_CTRL_SW_RESET 0x00000100 +#define BF_PXP_COMP_CTRL_SW_RESET(v) \ + (((v) << 8) & BM_PXP_COMP_CTRL_SW_RESET) +#define BP_PXP_COMP_CTRL_RSVD1 1 +#define BM_PXP_COMP_CTRL_RSVD1 0x000000FE +#define BF_PXP_COMP_CTRL_RSVD1(v) \ + (((v) << 1) & BM_PXP_COMP_CTRL_RSVD1) +#define BM_PXP_COMP_CTRL_START 0x00000001 +#define BF_PXP_COMP_CTRL_START(v) \ + (((v) << 0) & BM_PXP_COMP_CTRL_START) + +#define HW_PXP_COMP_FORMAT0 (0x00002c10) +#define HW_PXP_COMP_FORMAT0_SET (0x00002c14) +#define HW_PXP_COMP_FORMAT0_CLR (0x00002c18) +#define HW_PXP_COMP_FORMAT0_TOG (0x00002c1c) + +#define BP_PXP_COMP_FORMAT0_RSVD0 28 +#define BM_PXP_COMP_FORMAT0_RSVD0 0xF0000000 +#define BF_PXP_COMP_FORMAT0_RSVD0(v) \ + (((v) << 28) & BM_PXP_COMP_FORMAT0_RSVD0) +#define BP_PXP_COMP_FORMAT0_PIXEL_PITCH_64B 16 +#define BM_PXP_COMP_FORMAT0_PIXEL_PITCH_64B 0x0FFF0000 +#define BF_PXP_COMP_FORMAT0_PIXEL_PITCH_64B(v) \ + (((v) << 16) & BM_PXP_COMP_FORMAT0_PIXEL_PITCH_64B) +#define BP_PXP_COMP_FORMAT0_RSVD1 10 +#define BM_PXP_COMP_FORMAT0_RSVD1 0x0000FC00 +#define BF_PXP_COMP_FORMAT0_RSVD1(v) \ + (((v) << 10) & BM_PXP_COMP_FORMAT0_RSVD1) +#define BP_PXP_COMP_FORMAT0_MASK_INDEX 8 +#define BM_PXP_COMP_FORMAT0_MASK_INDEX 0x00000300 +#define BF_PXP_COMP_FORMAT0_MASK_INDEX(v) \ + (((v) << 8) & BM_PXP_COMP_FORMAT0_MASK_INDEX) +#define BP_PXP_COMP_FORMAT0_RSVD2 6 +#define BM_PXP_COMP_FORMAT0_RSVD2 0x000000C0 +#define BF_PXP_COMP_FORMAT0_RSVD2(v) \ + (((v) << 6) & BM_PXP_COMP_FORMAT0_RSVD2) +#define BP_PXP_COMP_FORMAT0_FIELD_NUM 4 +#define BM_PXP_COMP_FORMAT0_FIELD_NUM 0x00000030 +#define BF_PXP_COMP_FORMAT0_FIELD_NUM(v) \ + (((v) << 4) & BM_PXP_COMP_FORMAT0_FIELD_NUM) +#define BP_PXP_COMP_FORMAT0_RSVD3 1 +#define BM_PXP_COMP_FORMAT0_RSVD3 0x0000000E +#define BF_PXP_COMP_FORMAT0_RSVD3(v) \ + (((v) << 1) & BM_PXP_COMP_FORMAT0_RSVD3) +#define BM_PXP_COMP_FORMAT0_FLAG_32B 0x00000001 +#define BF_PXP_COMP_FORMAT0_FLAG_32B(v) \ + (((v) << 0) & BM_PXP_COMP_FORMAT0_FLAG_32B) + +#define HW_PXP_COMP_FORMAT1 (0x00002c20) + +#define BP_PXP_COMP_FORMAT1_D_LEN 29 +#define BM_PXP_COMP_FORMAT1_D_LEN 0xE0000000 +#define BF_PXP_COMP_FORMAT1_D_LEN(v) \ + (((v) << 29) & BM_PXP_COMP_FORMAT1_D_LEN) +#define BP_PXP_COMP_FORMAT1_D_OFFSET 24 +#define BM_PXP_COMP_FORMAT1_D_OFFSET 0x1F000000 +#define BF_PXP_COMP_FORMAT1_D_OFFSET(v) \ + (((v) << 24) & BM_PXP_COMP_FORMAT1_D_OFFSET) +#define BP_PXP_COMP_FORMAT1_C_LEN 21 +#define BM_PXP_COMP_FORMAT1_C_LEN 0x00E00000 +#define BF_PXP_COMP_FORMAT1_C_LEN(v) \ + (((v) << 21) & BM_PXP_COMP_FORMAT1_C_LEN) +#define BP_PXP_COMP_FORMAT1_C_OFFSET 16 +#define BM_PXP_COMP_FORMAT1_C_OFFSET 0x001F0000 +#define BF_PXP_COMP_FORMAT1_C_OFFSET(v) \ + (((v) << 16) & BM_PXP_COMP_FORMAT1_C_OFFSET) +#define BP_PXP_COMP_FORMAT1_B_LEN 13 +#define BM_PXP_COMP_FORMAT1_B_LEN 0x0000E000 +#define BF_PXP_COMP_FORMAT1_B_LEN(v) \ + (((v) << 13) & BM_PXP_COMP_FORMAT1_B_LEN) +#define BP_PXP_COMP_FORMAT1_B_OFFSET 8 +#define BM_PXP_COMP_FORMAT1_B_OFFSET 0x00001F00 +#define BF_PXP_COMP_FORMAT1_B_OFFSET(v) \ + (((v) << 8) & BM_PXP_COMP_FORMAT1_B_OFFSET) +#define BP_PXP_COMP_FORMAT1_A_LEN 5 +#define BM_PXP_COMP_FORMAT1_A_LEN 0x000000E0 +#define BF_PXP_COMP_FORMAT1_A_LEN(v) \ + (((v) << 5) & BM_PXP_COMP_FORMAT1_A_LEN) +#define BP_PXP_COMP_FORMAT1_A_OFFSET 0 +#define BM_PXP_COMP_FORMAT1_A_OFFSET 0x0000001F +#define BF_PXP_COMP_FORMAT1_A_OFFSET(v) \ + (((v) << 0) & BM_PXP_COMP_FORMAT1_A_OFFSET) + +#define HW_PXP_COMP_FORMAT2 (0x00002c30) + +#define BP_PXP_COMP_FORMAT2_RSVD 16 +#define BM_PXP_COMP_FORMAT2_RSVD 0xFFFF0000 +#define BF_PXP_COMP_FORMAT2_RSVD(v) \ + (((v) << 16) & BM_PXP_COMP_FORMAT2_RSVD) +#define BP_PXP_COMP_FORMAT2_D_RUNLEN 12 +#define BM_PXP_COMP_FORMAT2_D_RUNLEN 0x0000F000 +#define BF_PXP_COMP_FORMAT2_D_RUNLEN(v) \ + (((v) << 12) & BM_PXP_COMP_FORMAT2_D_RUNLEN) +#define BP_PXP_COMP_FORMAT2_C_RUNLEN 8 +#define BM_PXP_COMP_FORMAT2_C_RUNLEN 0x00000F00 +#define BF_PXP_COMP_FORMAT2_C_RUNLEN(v) \ + (((v) << 8) & BM_PXP_COMP_FORMAT2_C_RUNLEN) +#define BP_PXP_COMP_FORMAT2_B_RUNLEN 4 +#define BM_PXP_COMP_FORMAT2_B_RUNLEN 0x000000F0 +#define BF_PXP_COMP_FORMAT2_B_RUNLEN(v) \ + (((v) << 4) & BM_PXP_COMP_FORMAT2_B_RUNLEN) +#define BP_PXP_COMP_FORMAT2_A_RUNLEN 0 +#define BM_PXP_COMP_FORMAT2_A_RUNLEN 0x0000000F +#define BF_PXP_COMP_FORMAT2_A_RUNLEN(v) \ + (((v) << 0) & BM_PXP_COMP_FORMAT2_A_RUNLEN) + +#define HW_PXP_COMP_MASK0 (0x00002c40) + +#define BP_PXP_COMP_MASK0_VLD_MASK_LOW 0 +#define BM_PXP_COMP_MASK0_VLD_MASK_LOW 0xFFFFFFFF +#define BF_PXP_COMP_MASK0_VLD_MASK_LOW(v) (v) + +#define HW_PXP_COMP_MASK1 (0x00002c50) + +#define BP_PXP_COMP_MASK1_VLD_MASK_HIGH 0 +#define BM_PXP_COMP_MASK1_VLD_MASK_HIGH 0xFFFFFFFF +#define BF_PXP_COMP_MASK1_VLD_MASK_HIGH(v) (v) + +#define HW_PXP_COMP_BUFFER_SIZE (0x00002c60) + +#define BP_PXP_COMP_BUFFER_SIZE_RSVD0 29 +#define BM_PXP_COMP_BUFFER_SIZE_RSVD0 0xE0000000 +#define BF_PXP_COMP_BUFFER_SIZE_RSVD0(v) \ + (((v) << 29) & BM_PXP_COMP_BUFFER_SIZE_RSVD0) +#define BP_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH 16 +#define BM_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH 0x1FFF0000 +#define BF_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH(v) \ + (((v) << 16) & BM_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH) +#define BP_PXP_COMP_BUFFER_SIZE_RSVD1 13 +#define BM_PXP_COMP_BUFFER_SIZE_RSVD1 0x0000E000 +#define BF_PXP_COMP_BUFFER_SIZE_RSVD1(v) \ + (((v) << 13) & BM_PXP_COMP_BUFFER_SIZE_RSVD1) +#define BP_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH 0 +#define BM_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH 0x00001FFF +#define BF_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH(v) \ + (((v) << 0) & BM_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH) + +#define HW_PXP_COMP_SOURCE (0x00002c70) + +#define BP_PXP_COMP_SOURCE_SOURCE_ADDR 0 +#define BM_PXP_COMP_SOURCE_SOURCE_ADDR 0xFFFFFFFF +#define BF_PXP_COMP_SOURCE_SOURCE_ADDR(v) (v) + +#define HW_PXP_COMP_TARGET (0x00002c80) + +#define BP_PXP_COMP_TARGET_TARGET_ADDR 0 +#define BM_PXP_COMP_TARGET_TARGET_ADDR 0xFFFFFFFF +#define BF_PXP_COMP_TARGET_TARGET_ADDR(v) (v) + +#define HW_PXP_COMP_BUFFER_A (0x00002c90) + +#define BP_PXP_COMP_BUFFER_A_A_SRAM_ADDR 0 +#define BM_PXP_COMP_BUFFER_A_A_SRAM_ADDR 0xFFFFFFFF +#define BF_PXP_COMP_BUFFER_A_A_SRAM_ADDR(v) (v) + +#define HW_PXP_COMP_BUFFER_B (0x00002ca0) + +#define BP_PXP_COMP_BUFFER_B_B_SRAM_ADDR 0 +#define BM_PXP_COMP_BUFFER_B_B_SRAM_ADDR 0xFFFFFFFF +#define BF_PXP_COMP_BUFFER_B_B_SRAM_ADDR(v) (v) + +#define HW_PXP_COMP_BUFFER_C (0x00002cb0) + +#define BP_PXP_COMP_BUFFER_C_C_SRAM_ADDR 0 +#define BM_PXP_COMP_BUFFER_C_C_SRAM_ADDR 0xFFFFFFFF +#define BF_PXP_COMP_BUFFER_C_C_SRAM_ADDR(v) (v) + +#define HW_PXP_COMP_BUFFER_D (0x00002cc0) + +#define BP_PXP_COMP_BUFFER_D_D_SRAM_ADDR 0 +#define BM_PXP_COMP_BUFFER_D_D_SRAM_ADDR 0xFFFFFFFF +#define BF_PXP_COMP_BUFFER_D_D_SRAM_ADDR(v) (v) + +#define HW_PXP_COMP_DEBUG (0x00002cd0) + +#define BP_PXP_COMP_DEBUG_DEBUG_VALUE 8 +#define BM_PXP_COMP_DEBUG_DEBUG_VALUE 0xFFFFFF00 +#define BF_PXP_COMP_DEBUG_DEBUG_VALUE(v) \ + (((v) << 8) & BM_PXP_COMP_DEBUG_DEBUG_VALUE) +#define BP_PXP_COMP_DEBUG_DEBUG_SEL 0 +#define BM_PXP_COMP_DEBUG_DEBUG_SEL 0x000000FF +#define BF_PXP_COMP_DEBUG_DEBUG_SEL(v) \ + (((v) << 0) & BM_PXP_COMP_DEBUG_DEBUG_SEL) + +#define HW_PXP_BUS_MUX (0x00002ce0) + +#define BP_PXP_BUS_MUX_RSVD1 24 +#define BM_PXP_BUS_MUX_RSVD1 0xFF000000 +#define BF_PXP_BUS_MUX_RSVD1(v) \ + (((v) << 24) & BM_PXP_BUS_MUX_RSVD1) +#define BP_PXP_BUS_MUX_WR_SEL 16 +#define BM_PXP_BUS_MUX_WR_SEL 0x00FF0000 +#define BF_PXP_BUS_MUX_WR_SEL(v) \ + (((v) << 16) & BM_PXP_BUS_MUX_WR_SEL) +#define BP_PXP_BUS_MUX_RSVD0 8 +#define BM_PXP_BUS_MUX_RSVD0 0x0000FF00 +#define BF_PXP_BUS_MUX_RSVD0(v) \ + (((v) << 8) & BM_PXP_BUS_MUX_RSVD0) +#define BP_PXP_BUS_MUX_RD_SEL 0 +#define BM_PXP_BUS_MUX_RD_SEL 0x000000FF +#define BF_PXP_BUS_MUX_RD_SEL(v) \ + (((v) << 0) & BM_PXP_BUS_MUX_RD_SEL) + +#define HW_PXP_HANDSHAKE_READY_MUX0 (0x00002cf0) + +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK7 28 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK7 0xF0000000 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK7(v) \ + (((v) << 28) & BM_PXP_HANDSHAKE_READY_MUX0_HSK7) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK6 24 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK6 0x0F000000 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK6(v) \ + (((v) << 24) & BM_PXP_HANDSHAKE_READY_MUX0_HSK6) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK5 20 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK5 0x00F00000 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK5(v) \ + (((v) << 20) & BM_PXP_HANDSHAKE_READY_MUX0_HSK5) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK4 16 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK4 0x000F0000 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK4(v) \ + (((v) << 16) & BM_PXP_HANDSHAKE_READY_MUX0_HSK4) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK3 12 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK3 0x0000F000 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK3(v) \ + (((v) << 12) & BM_PXP_HANDSHAKE_READY_MUX0_HSK3) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK2 8 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK2 0x00000F00 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK2(v) \ + (((v) << 8) & BM_PXP_HANDSHAKE_READY_MUX0_HSK2) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK1 4 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK1 0x000000F0 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK1(v) \ + (((v) << 4) & BM_PXP_HANDSHAKE_READY_MUX0_HSK1) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK0 0 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK0 0x0000000F +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK0(v) \ + (((v) << 0) & BM_PXP_HANDSHAKE_READY_MUX0_HSK0) + +#define HW_PXP_HANDSHAKE_READY_MUX1 (0x00002d00) + +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK15 28 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK15 0xF0000000 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK15(v) \ + (((v) << 28) & BM_PXP_HANDSHAKE_READY_MUX1_HSK15) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK14 24 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK14 0x0F000000 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK14(v) \ + (((v) << 24) & BM_PXP_HANDSHAKE_READY_MUX1_HSK14) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK13 20 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK13 0x00F00000 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK13(v) \ + (((v) << 20) & BM_PXP_HANDSHAKE_READY_MUX1_HSK13) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK12 16 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK12 0x000F0000 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK12(v) \ + (((v) << 16) & BM_PXP_HANDSHAKE_READY_MUX1_HSK12) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK11 12 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK11 0x0000F000 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK11(v) \ + (((v) << 12) & BM_PXP_HANDSHAKE_READY_MUX1_HSK11) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK10 8 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK10 0x00000F00 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK10(v) \ + (((v) << 8) & BM_PXP_HANDSHAKE_READY_MUX1_HSK10) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK9 4 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK9 0x000000F0 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK9(v) \ + (((v) << 4) & BM_PXP_HANDSHAKE_READY_MUX1_HSK9) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK8 0 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK8 0x0000000F +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK8(v) \ + (((v) << 0) & BM_PXP_HANDSHAKE_READY_MUX1_HSK8) + +#define HW_PXP_HANDSHAKE_DONE_MUX0 (0x00002d10) + +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK7 28 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK7 0xF0000000 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK7(v) \ + (((v) << 28) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK7) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK6 24 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK6 0x0F000000 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK6(v) \ + (((v) << 24) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK6) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK5 20 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK5 0x00F00000 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK5(v) \ + (((v) << 20) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK5) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK4 16 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK4 0x000F0000 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK4(v) \ + (((v) << 16) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK4) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK3 12 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK3 0x0000F000 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK3(v) \ + (((v) << 12) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK3) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK2 8 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK2 0x00000F00 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK2(v) \ + (((v) << 8) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK2) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK1 4 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK1 0x000000F0 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK1(v) \ + (((v) << 4) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK1) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK0 0 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK0 0x0000000F +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK0(v) \ + (((v) << 0) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK0) + +#define HW_PXP_HANDSHAKE_DONE_MUX1 (0x00002d20) + +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK15 28 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK15 0xF0000000 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK15(v) \ + (((v) << 28) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK15) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK14 24 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK14 0x0F000000 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK14(v) \ + (((v) << 24) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK14) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK13 20 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK13 0x00F00000 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK13(v) \ + (((v) << 20) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK13) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK12 16 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK12 0x000F0000 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK12(v) \ + (((v) << 16) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK12) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK11 12 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK11 0x0000F000 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK11(v) \ + (((v) << 12) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK11) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK10 8 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK10 0x00000F00 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK10(v) \ + (((v) << 8) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK10) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK9 4 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK9 0x000000F0 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK9(v) \ + (((v) << 4) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK9) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK8 0 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK8 0x0000000F +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK8(v) \ + (((v) << 0) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK8) + +#define HW_PXP_HANDSHAKE_CPU_FETCH (0x00002d30) +#define HW_PXP_HANDSHAKE_CPU_FETCH_SET (0x00002d34) +#define HW_PXP_HANDSHAKE_CPU_FETCH_CLR (0x00002d38) +#define HW_PXP_HANDSHAKE_CPU_FETCH_TOG (0x00002d3c) + +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_HSK_EN 0x80000000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_HSK_EN(v) \ + (((v) << 31) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_HSK_EN) +#define BP_PXP_HANDSHAKE_CPU_FETCH_RSVD1 22 +#define BM_PXP_HANDSHAKE_CPU_FETCH_RSVD1 0x7FC00000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_RSVD1(v) \ + (((v) << 22) & BM_PXP_HANDSHAKE_CPU_FETCH_RSVD1) +#define BP_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES 20 +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES 0x00300000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES(v) \ + (((v) << 20) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES) +#define BV_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES__LINE_4 0x0 +#define BV_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES__LINE_8 0x1 +#define BV_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES__LINE_16 0x2 +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_DONE 0x00080000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_DONE(v) \ + (((v) << 19) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_DONE) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_DONE 0x00040000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_DONE(v) \ + (((v) << 18) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_DONE) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_READY 0x00020000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_READY(v) \ + (((v) << 17) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_READY) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_READY 0x00010000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_READY(v) \ + (((v) << 16) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_READY) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_HSK_EN 0x00008000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_HSK_EN(v) \ + (((v) << 15) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_HSK_EN) +#define BP_PXP_HANDSHAKE_CPU_FETCH_RSVD0 6 +#define BM_PXP_HANDSHAKE_CPU_FETCH_RSVD0 0x00007FC0 +#define BF_PXP_HANDSHAKE_CPU_FETCH_RSVD0(v) \ + (((v) << 6) & BM_PXP_HANDSHAKE_CPU_FETCH_RSVD0) +#define BP_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES 4 +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES 0x00000030 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES(v) \ + (((v) << 4) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES) +#define BV_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES__LINE_4 0x0 +#define BV_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES__LINE_8 0x1 +#define BV_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES__LINE_16 0x2 +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_DONE 0x00000008 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_DONE(v) \ + (((v) << 3) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_DONE) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_DONE 0x00000004 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_DONE(v) \ + (((v) << 2) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_DONE) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_READY 0x00000002 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_READY(v) \ + (((v) << 1) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_READY) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_READY 0x00000001 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_READY(v) \ + (((v) << 0) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_READY) + +#define HW_PXP_HANDSHAKE_CPU_STORE (0x00002d40) +#define HW_PXP_HANDSHAKE_CPU_STORE_SET (0x00002d44) +#define HW_PXP_HANDSHAKE_CPU_STORE_CLR (0x00002d48) +#define HW_PXP_HANDSHAKE_CPU_STORE_TOG (0x00002d4c) + +#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_HSK_EN 0x80000000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_HSK_EN(v) \ + (((v) << 31) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_HSK_EN) +#define BP_PXP_HANDSHAKE_CPU_STORE_RSVD1 22 +#define BM_PXP_HANDSHAKE_CPU_STORE_RSVD1 0x7FC00000 +#define BF_PXP_HANDSHAKE_CPU_STORE_RSVD1(v) \ + (((v) << 22) & BM_PXP_HANDSHAKE_CPU_STORE_RSVD1) +#define BP_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES 20 +#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES 0x00300000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES(v) \ + (((v) << 20) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES) +#define BV_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES__LINE_4 0x0 +#define BV_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES__LINE_8 0x1 +#define BV_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES__LINE_16 0x2 +#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_B1_DONE 0x00080000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_B1_DONE(v) \ + (((v) << 19) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_B1_DONE) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_B0_DONE 0x00040000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_B0_DONE(v) \ + (((v) << 18) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_B0_DONE) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_B1_READY 0x00020000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_B1_READY(v) \ + (((v) << 17) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_B1_READY) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_B0_READY 0x00010000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_B0_READY(v) \ + (((v) << 16) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_B0_READY) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_HSK_EN 0x00008000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_HSK_EN(v) \ + (((v) << 15) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_HSK_EN) +#define BP_PXP_HANDSHAKE_CPU_STORE_RSVD0 6 +#define BM_PXP_HANDSHAKE_CPU_STORE_RSVD0 0x00007FC0 +#define BF_PXP_HANDSHAKE_CPU_STORE_RSVD0(v) \ + (((v) << 6) & BM_PXP_HANDSHAKE_CPU_STORE_RSVD0) +#define BP_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES 4 +#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES 0x00000030 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES(v) \ + (((v) << 4) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES) +#define BV_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES__LINE_4 0x0 +#define BV_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES__LINE_8 0x1 +#define BV_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES__LINE_16 0x2 +#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_B1_DONE 0x00000008 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_B1_DONE(v) \ + (((v) << 3) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_B1_DONE) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_B0_DONE 0x00000004 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_B0_DONE(v) \ + (((v) << 2) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_B0_DONE) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_B1_READY 0x00000002 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_B1_READY(v) \ + (((v) << 1) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_B1_READY) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY 0x00000001 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY(v) \ + (((v) << 0) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY) +#endif /* __ARCH_ARM___PXP_H */ diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 417dad63552689..96f71a502d58ef 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -475,7 +475,7 @@ config EDAC_ARMADA_XP config EDAC_SYNOPSYS tristate "Synopsys DDR Memory Controller" - depends on ARCH_ZYNQ || ARCH_ZYNQMP + depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_MXC help Support for error detection and correction on the Synopsys DDR memory controller. diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index 880ffd83371871..b9939a2ba7627c 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -101,6 +101,7 @@ /* DDR ECC Quirks */ #define DDR_ECC_INTR_SUPPORT BIT(0) #define DDR_ECC_DATA_POISON_SUPPORT BIT(1) +#define DDR_ECC_IMX8MP BIT(2) /* ZynqMP Enhanced DDR memory controller registers that are relevant to ECC */ /* ECC Configuration Registers */ @@ -266,6 +267,11 @@ #define RANK_B0_BASE 6 +/* ECCCTL UE/CE Interrupt enable/disable for IMX8MP*/ +#define DDR_CE_INTR_EN_MASK 0x100 +#define DDR_UE_INTR_EN_MASK 0x200 +#define ECC_INTR_MASK 0x10100 + /** * struct ecc_error_info - ECC error log information. * @row: Row number. @@ -281,9 +287,11 @@ struct ecc_error_info { u32 col; u32 bank; u32 bitpos; - u32 data; + u32 data_low; + u32 data_high; u32 bankgrpnr; u32 blknr; + u32 syndrome; }; /** @@ -348,6 +356,70 @@ struct synps_platform_data { int quirks; }; +/** + * zynq_get_dtype - Return the controller memory width. + * @base: DDR memory controller base address. + * + * Get the EDAC device type width appropriate for the current controller + * configuration. + * + * Return: a device type width enumeration. + */ +static enum dev_type zynq_get_dtype(const void __iomem *base) +{ + enum dev_type dt; + u32 width; + + width = readl(base + CTRL_OFST); + width = (width & CTRL_BW_MASK) >> CTRL_BW_SHIFT; + + switch (width) { + case DDRCTL_WDTH_16: + dt = DEV_X2; + break; + case DDRCTL_WDTH_32: + dt = DEV_X4; + break; + default: + dt = DEV_UNKNOWN; + } + + return dt; +} + +/** + * zynqmp_get_dtype - Return the controller memory width. + * @base: DDR memory controller base address. + * + * Get the EDAC device type width appropriate for the current controller + * configuration. + * + * Return: a device type width enumeration. + */ +static enum dev_type zynqmp_get_dtype(const void __iomem *base) +{ + enum dev_type dt; + u32 width; + + width = readl(base + CTRL_OFST); + width = (width & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT; + switch (width) { + case DDRCTL_EWDTH_16: + dt = DEV_X2; + break; + case DDRCTL_EWDTH_32: + dt = DEV_X4; + break; + case DDRCTL_EWDTH_64: + dt = DEV_X8; + break; + default: + dt = DEV_UNKNOWN; + } + + return dt; +} + /** * zynq_get_error_info - Get the current ECC error info. * @priv: DDR memory controller private instance data. @@ -379,9 +451,9 @@ static int zynq_get_error_info(struct synps_edac_priv *priv) p->ceinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; p->ceinfo.col = regval & ADDR_COL_MASK; p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; - p->ceinfo.data = readl(base + CE_DATA_31_0_OFST); + p->ceinfo.data_low = readl(base + CE_DATA_31_0_OFST); edac_dbg(3, "CE bit position: %d data: %d\n", p->ceinfo.bitpos, - p->ceinfo.data); + p->ceinfo.data_low); clearval = ECC_CTRL_CLR_CE_ERR; ue_err: @@ -393,7 +465,7 @@ static int zynq_get_error_info(struct synps_edac_priv *priv) p->ueinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; p->ueinfo.col = regval & ADDR_COL_MASK; p->ueinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; - p->ueinfo.data = readl(base + UE_DATA_31_0_OFST); + p->ueinfo.data_low = readl(base + UE_DATA_31_0_OFST); clearval |= ECC_CTRL_CLR_UE_ERR; out: @@ -437,10 +509,13 @@ static int zynqmp_get_error_info(struct synps_edac_priv *priv) p->ceinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >> ECC_CEADDR1_BNKGRP_SHIFT; p->ceinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK); - p->ceinfo.data = readl(base + ECC_CSYND0_OFST); - edac_dbg(2, "ECCCSYN0: 0x%08X ECCCSYN1: 0x%08X ECCCSYN2: 0x%08X\n", - readl(base + ECC_CSYND0_OFST), readl(base + ECC_CSYND1_OFST), - readl(base + ECC_CSYND2_OFST)); + p->ceinfo.data_low = readl(base + ECC_CSYND0_OFST); + if (zynqmp_get_dtype(base) == DEV_X8) { + p->ceinfo.data_high = readl(base + ECC_CSYND1_OFST); + p->ceinfo.syndrome = readl(base + ECC_CSYND2_OFST); + edac_dbg(2, "ECCCSYN0: 0x%08X ECCCSYN1: 0x%08X ECCCSYN2: 0x%08X\n", + p->ceinfo.data_low, p->ceinfo.data_high, p->ceinfo.syndrome); + } ue_err: if (!p->ue_cnt) goto out; @@ -453,7 +528,11 @@ static int zynqmp_get_error_info(struct synps_edac_priv *priv) p->ueinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> ECC_CEADDR1_BNKNR_SHIFT; p->ueinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK); - p->ueinfo.data = readl(base + ECC_UESYND0_OFST); + p->ueinfo.data_low = readl(base + ECC_UESYND0_OFST); + if (zynqmp_get_dtype(base) == DEV_X8) { + p->ueinfo.data_high = readl(base + ECC_UESYND1_OFST); + p->ueinfo.syndrome = readl(base + ECC_UESYND2_OFST); + } out: clearval = ECC_CTRL_CLR_CE_ERR | ECC_CTRL_CLR_CE_ERRCNT; clearval |= ECC_CTRL_CLR_UE_ERR | ECC_CTRL_CLR_UE_ERRCNT; @@ -479,15 +558,28 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p) pinf = &p->ceinfo; if (!priv->p_data->quirks) { snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, - "DDR ECC error type:%s Row %d Bank %d Col %d Bit Position: %d Data: 0x%08x", + "DDR ECC error type:%s Row %d Bank %d Col %d " + "Bit Position: %d Data: 0x%08x", "CE", pinf->row, pinf->bank, pinf->col, - pinf->bitpos, pinf->data); + pinf->bitpos, pinf->data_low); } else { - snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, - "DDR ECC error type:%s Row %d Bank %d Col %d BankGroup Number %d Block Number %d Bit Position: %d Data: 0x%08x", - "CE", pinf->row, pinf->bank, pinf->col, - pinf->bankgrpnr, pinf->blknr, - pinf->bitpos, pinf->data); + if (zynqmp_get_dtype(priv->baseaddr) == DEV_X8) { + snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, + "DDR ECC error type:%s Row %d Bank %d " + "BankGroup Number %d Block Number %d " + "Bit Position: %d Data_low: 0x%08x " + "Data_high: 0x%08x Syndrome: 0x%08x", + "CE", pinf->row, pinf->bank, pinf->bankgrpnr, + pinf->blknr, pinf->bitpos, pinf->data_low, + pinf->data_high, pinf->syndrome); + } else { + snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, + "DDR ECC error type:%s Row %d Bank %d " + "BankGroup Number %d Block Number %d " + "Bit Position: %d Data: 0x%08x", + "CE", pinf->row, pinf->bank, pinf->bankgrpnr, + pinf->blknr, pinf->bitpos, pinf->data_low); + } } edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, @@ -503,9 +595,10 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p) "UE", pinf->row, pinf->bank, pinf->col); } else { snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, - "DDR ECC error type :%s Row %d Bank %d Col %d BankGroup Number %d Block Number %d", - "UE", pinf->row, pinf->bank, pinf->col, - pinf->bankgrpnr, pinf->blknr); + "DDR ECC error type :%s Row %d Bank %d " + "BankGroup Number %d Block Number %d", + "UE", pinf->row, pinf->bank, pinf->bankgrpnr, + pinf->blknr); } edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, @@ -516,6 +609,45 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p) memset(p, 0, sizeof(*p)); } +static void enable_intr_imx8mp(struct synps_edac_priv *priv) +{ + int regval; + + regval = readl(priv->baseaddr + ECC_CLR_OFST); + regval |= (DDR_CE_INTR_EN_MASK | DDR_UE_INTR_EN_MASK); + writel(regval, priv->baseaddr + ECC_CLR_OFST); +} + +/* Interrupt Handler for ECC interrupts on imx8mp platform. */ +static irqreturn_t intr_handler_imx8mp(int irq, void *dev_id) +{ + const struct synps_platform_data *p_data; + struct mem_ctl_info *mci = dev_id; + struct synps_edac_priv *priv; + int status, regval; + + priv = mci->pvt_info; + p_data = priv->p_data; + + regval = readl(priv->baseaddr + ECC_STAT_OFST); + if (!(regval & ECC_INTR_MASK)) + return IRQ_NONE; + + status = p_data->get_error_info(priv); + if (status) + return IRQ_NONE; + + priv->ce_cnt += priv->stat.ce_cnt; + priv->ue_cnt += priv->stat.ue_cnt; + handle_error(mci, &priv->stat); + + edac_dbg(3, "Total error count CE %d UE %d\n", + priv->ce_cnt, priv->ue_cnt); + enable_intr_imx8mp(priv); + + return IRQ_HANDLED; +} + /** * intr_handler - Interrupt Handler for ECC interrupts. * @irq: IRQ number. @@ -533,6 +665,9 @@ static irqreturn_t intr_handler(int irq, void *dev_id) priv = mci->pvt_info; p_data = priv->p_data; + if (p_data->quirks & DDR_ECC_IMX8MP) + return intr_handler_imx8mp(irq, dev_id); + regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); regval &= (DDR_QOSCE_MASK | DDR_QOSUE_MASK); if (!(regval & ECC_CE_UE_INTR_MASK)) @@ -579,70 +714,6 @@ static void check_errors(struct mem_ctl_info *mci) priv->ce_cnt, priv->ue_cnt); } -/** - * zynq_get_dtype - Return the controller memory width. - * @base: DDR memory controller base address. - * - * Get the EDAC device type width appropriate for the current controller - * configuration. - * - * Return: a device type width enumeration. - */ -static enum dev_type zynq_get_dtype(const void __iomem *base) -{ - enum dev_type dt; - u32 width; - - width = readl(base + CTRL_OFST); - width = (width & CTRL_BW_MASK) >> CTRL_BW_SHIFT; - - switch (width) { - case DDRCTL_WDTH_16: - dt = DEV_X2; - break; - case DDRCTL_WDTH_32: - dt = DEV_X4; - break; - default: - dt = DEV_UNKNOWN; - } - - return dt; -} - -/** - * zynqmp_get_dtype - Return the controller memory width. - * @base: DDR memory controller base address. - * - * Get the EDAC device type width appropriate for the current controller - * configuration. - * - * Return: a device type width enumeration. - */ -static enum dev_type zynqmp_get_dtype(const void __iomem *base) -{ - enum dev_type dt; - u32 width; - - width = readl(base + CTRL_OFST); - width = (width & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT; - switch (width) { - case DDRCTL_EWDTH_16: - dt = DEV_X2; - break; - case DDRCTL_EWDTH_32: - dt = DEV_X4; - break; - case DDRCTL_EWDTH_64: - dt = DEV_X8; - break; - default: - dt = DEV_UNKNOWN; - } - - return dt; -} - /** * zynq_get_ecc_state - Return the controller ECC enable/disable status. * @base: DDR memory controller base address. @@ -809,7 +880,8 @@ static void mc_init(struct mem_ctl_info *mci, struct platform_device *pdev) platform_set_drvdata(pdev, mci); /* Initialize controller capabilities and configuration */ - mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2; + mci->mtype_cap = MEM_FLAG_LRDDR4 | MEM_FLAG_DDR4 | + MEM_FLAG_DDR3 | MEM_FLAG_DDR2; mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; mci->scrub_cap = SCRUB_HW_SRC; mci->scrub_mode = SCRUB_NONE; @@ -831,9 +903,21 @@ static void mc_init(struct mem_ctl_info *mci, struct platform_device *pdev) init_csrows(mci); } +static void disable_intr_imx8mp(struct synps_edac_priv *priv) +{ + int regval; + + regval = readl(priv->baseaddr + ECC_CLR_OFST); + regval &= ~(DDR_CE_INTR_EN_MASK | DDR_UE_INTR_EN_MASK); + writel(regval, priv->baseaddr + ECC_CLR_OFST); +} + static void enable_intr(struct synps_edac_priv *priv) { /* Enable UE/CE Interrupts */ + if (priv->p_data->quirks & DDR_ECC_IMX8MP) + return enable_intr_imx8mp(priv); + writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK, priv->baseaddr + DDR_QOS_IRQ_EN_OFST); } @@ -841,6 +925,9 @@ static void enable_intr(struct synps_edac_priv *priv) static void disable_intr(struct synps_edac_priv *priv) { /* Disable UE/CE Interrupts */ + if (priv->p_data->quirks & DDR_ECC_IMX8MP) + return disable_intr_imx8mp(priv); + writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK, priv->baseaddr + DDR_QOS_IRQ_DB_OFST); } @@ -890,6 +977,14 @@ static const struct synps_platform_data zynqmp_edac_def = { ), }; +static const struct synps_platform_data imx8mp_edac_def = { + .get_error_info = zynqmp_get_error_info, + .get_mtype = zynqmp_get_mtype, + .get_dtype = zynqmp_get_dtype, + .get_ecc_state = zynqmp_get_ecc_state, + .quirks = (DDR_ECC_INTR_SUPPORT | DDR_ECC_IMX8MP), +}; + static const struct of_device_id synps_edac_match[] = { { .compatible = "xlnx,zynq-ddrc-a05", @@ -899,6 +994,10 @@ static const struct of_device_id synps_edac_match[] = { .compatible = "xlnx,zynqmp-ddrc-2.40a", .data = (void *)&zynqmp_edac_def }, + { + .compatible = "fsl,imx8mp-ddrc", + .data = (void *)&imx8mp_edac_def + }, { /* end of table */ } diff --git a/drivers/firmware/imx/Kconfig b/drivers/firmware/imx/Kconfig index 0dbee32da4c6d5..c3b90d354b39c9 100644 --- a/drivers/firmware/imx/Kconfig +++ b/drivers/firmware/imx/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only config IMX_DSP - bool "IMX DSP Protocol driver" + tristate "IMX DSP Protocol driver" depends on IMX_MBOX help This enables DSP IPC protocol between host AP (Linux) @@ -27,3 +27,13 @@ config IMX_SCU_PD depends on IMX_SCU help The System Controller Firmware (SCFW) based power domain driver. + +config IMX_SECO_MU + tristate "i.MX Security Controller (SECO) support" + depends on IMX_SCU && IMX_MBOX && MAILBOX + + help + It is possible to use APIs exposed by the SECO like HSM and SHE using the + SAB protocol via the shared Messaging Unit. This driver exposes these + interfaces via a set of file descriptors allowing to configure shared + memory, send and receive messages. diff --git a/drivers/firmware/imx/Makefile b/drivers/firmware/imx/Makefile index 08bc9ddfbdfb51..9b369250ef677f 100644 --- a/drivers/firmware/imx/Makefile +++ b/drivers/firmware/imx/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_IMX_DSP) += imx-dsp.o -obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o imx-scu-irq.o +obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o imx-scu-irq.o rm.o seco.o obj-$(CONFIG_IMX_SCU_PD) += scu-pd.o +obj-${CONFIG_IMX_SECO_MU} += seco_mu.o diff --git a/drivers/firmware/imx/imx-scu-irq.c b/drivers/firmware/imx/imx-scu-irq.c index 687121f8c4d5eb..369621c14105e4 100644 --- a/drivers/firmware/imx/imx-scu-irq.c +++ b/drivers/firmware/imx/imx-scu-irq.c @@ -1,18 +1,19 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2019 NXP + * Copyright 2019-2020 NXP * * Implementation of the SCU IRQ functions using MU. * */ #include -#include +#include #include +#include #define IMX_SC_IRQ_FUNC_ENABLE 1 #define IMX_SC_IRQ_FUNC_STATUS 2 -#define IMX_SC_IRQ_NUM_GROUP 4 +#define IMX_SC_IRQ_NUM_GROUP 7 static u32 mu_resource_id; @@ -40,60 +41,75 @@ struct imx_sc_msg_irq_enable { static struct imx_sc_ipc *imx_sc_irq_ipc_handle; static struct work_struct imx_sc_irq_work; -static ATOMIC_NOTIFIER_HEAD(imx_scu_irq_notifier_chain); +static BLOCKING_NOTIFIER_HEAD(imx_scu_irq_notifier_chain); int imx_scu_irq_register_notifier(struct notifier_block *nb) { - return atomic_notifier_chain_register( + return blocking_notifier_chain_register( &imx_scu_irq_notifier_chain, nb); } EXPORT_SYMBOL(imx_scu_irq_register_notifier); int imx_scu_irq_unregister_notifier(struct notifier_block *nb) { - return atomic_notifier_chain_unregister( + return blocking_notifier_chain_unregister( &imx_scu_irq_notifier_chain, nb); } EXPORT_SYMBOL(imx_scu_irq_unregister_notifier); static int imx_scu_irq_notifier_call_chain(unsigned long status, u8 *group) { - return atomic_notifier_call_chain(&imx_scu_irq_notifier_chain, + return blocking_notifier_call_chain(&imx_scu_irq_notifier_chain, status, (void *)group); } static void imx_scu_irq_work_handler(struct work_struct *work) { - struct imx_sc_msg_irq_get_status msg; - struct imx_sc_rpc_msg *hdr = &msg.hdr; u32 irq_status; int ret; u8 i; for (i = 0; i < IMX_SC_IRQ_NUM_GROUP; i++) { - hdr->ver = IMX_SC_RPC_VERSION; - hdr->svc = IMX_SC_RPC_SVC_IRQ; - hdr->func = IMX_SC_IRQ_FUNC_STATUS; - hdr->size = 2; - - msg.data.req.resource = mu_resource_id; - msg.data.req.group = i; - - ret = imx_scu_call_rpc(imx_sc_irq_ipc_handle, &msg, true); + ret = imx_scu_irq_get_status(i, &irq_status); if (ret) { pr_err("get irq group %d status failed, ret %d\n", i, ret); return; } - irq_status = msg.data.resp.status; if (!irq_status) continue; + pm_system_wakeup(); imx_scu_irq_notifier_call_chain(irq_status, &i); } } +int imx_scu_irq_get_status(u8 group, u32 *irq_status) +{ + struct imx_sc_msg_irq_get_status msg; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + int ret; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_IRQ; + hdr->func = IMX_SC_IRQ_FUNC_STATUS; + hdr->size = 2; + + msg.data.req.resource = mu_resource_id; + msg.data.req.group = group; + + ret = imx_scu_call_rpc(imx_sc_irq_ipc_handle, &msg, true); + if (ret) + return ret; + + if (irq_status) + *irq_status = msg.data.resp.status; + + return 0; +} +EXPORT_SYMBOL(imx_scu_irq_get_status); + int imx_scu_irq_group_enable(u8 group, u32 mask, u8 enable) { struct imx_sc_msg_irq_enable msg; diff --git a/drivers/firmware/imx/imx-scu.c b/drivers/firmware/imx/imx-scu.c index a3b11bc71dcb86..be6da8773ecee7 100644 --- a/drivers/firmware/imx/imx-scu.c +++ b/drivers/firmware/imx/imx-scu.c @@ -7,8 +7,8 @@ * */ +#include #include -#include #include #include #include @@ -20,8 +20,11 @@ #include #include +#include + +#define FSL_HVC_SC 0xC6000000 #define SCU_MU_CHAN_NUM 8 -#define MAX_RX_TIMEOUT (msecs_to_jiffies(30)) +#define MAX_RX_TIMEOUT (msecs_to_jiffies(3000)) struct imx_sc_chan { struct imx_sc_ipc *sc_ipc; @@ -30,6 +33,7 @@ struct imx_sc_chan { struct mbox_chan *ch; int idx; struct completion tx_done; + u8 rx_pos; }; struct imx_sc_ipc { @@ -38,7 +42,6 @@ struct imx_sc_ipc { struct device *dev; struct mutex lock; struct completion done; - bool fast_ipc; /* temporarily store the SCU msg */ u32 *msg; @@ -116,43 +119,44 @@ static void imx_scu_rx_callback(struct mbox_client *c, void *msg) struct imx_sc_ipc *sc_ipc = sc_chan->sc_ipc; struct imx_sc_rpc_msg *hdr; u32 *data = msg; - int i; - if (!sc_ipc->msg) { - dev_warn(sc_ipc->dev, "unexpected rx idx %d 0x%08x, ignore!\n", - sc_chan->idx, *data); - return; - } - - if (sc_ipc->fast_ipc) { + if (sc_chan->rx_pos == 0) { hdr = msg; sc_ipc->rx_size = hdr->size; - sc_ipc->msg[0] = *data++; + dev_dbg(sc_ipc->dev, "msg rx size %u\n", sc_ipc->rx_size); + } - for (i = 1; i < sc_ipc->rx_size; i++) - sc_ipc->msg[i] = *data++; + sc_ipc->msg[sc_chan->rx_pos] = *data; + sc_chan->rx_pos += 4; + sc_ipc->count++; + dev_dbg(sc_ipc->dev, "mu %u msg %u 0x%x\n", sc_chan->idx, + sc_ipc->count, *data); + + if (sc_ipc->count == sc_ipc->rx_size) complete(&sc_ipc->done); +} - return; - } +static void imx_scu_big_rx_callback(struct mbox_client *c, void *msg) +{ + struct imx_sc_chan *sc_chan = container_of(c, struct imx_sc_chan, cl); + struct imx_sc_ipc *sc_ipc = sc_chan->sc_ipc; + struct imx_sc_rpc_msg *hdr; + u32 *data = msg; - if (sc_chan->idx == 0) { + if (sc_ipc->count == 0) { hdr = msg; sc_ipc->rx_size = hdr->size; dev_dbg(sc_ipc->dev, "msg rx size %u\n", sc_ipc->rx_size); - if (sc_ipc->rx_size > 4) - dev_warn(sc_ipc->dev, "RPC does not support receiving over 4 words: %u\n", - sc_ipc->rx_size); } - sc_ipc->msg[sc_chan->idx] = *data; + sc_ipc->msg[sc_ipc->count] = *data; sc_ipc->count++; dev_dbg(sc_ipc->dev, "mu %u msg %u 0x%x\n", sc_chan->idx, sc_ipc->count, *data); - if ((sc_ipc->rx_size != 0) && (sc_ipc->count == sc_ipc->rx_size)) + if (sc_ipc->count == sc_ipc->rx_size) complete(&sc_ipc->done); } @@ -162,7 +166,6 @@ static int imx_scu_ipc_write(struct imx_sc_ipc *sc_ipc, void *msg) struct imx_sc_chan *sc_chan; u32 *data = msg; int ret; - int size; int i; /* Check size */ @@ -172,8 +175,7 @@ static int imx_scu_ipc_write(struct imx_sc_ipc *sc_ipc, void *msg) dev_dbg(sc_ipc->dev, "RPC SVC %u FUNC %u SIZE %u\n", hdr.svc, hdr.func, hdr.size); - size = sc_ipc->fast_ipc ? 1 : hdr.size; - for (i = 0; i < size; i++) { + for (i = 0; i < hdr.size; i++) { sc_chan = &sc_ipc->chans[i % 4]; /* @@ -185,10 +187,8 @@ static int imx_scu_ipc_write(struct imx_sc_ipc *sc_ipc, void *msg) * Wait for tx_done before every send to ensure that no * queueing happens at the mailbox channel level. */ - if (!sc_ipc->fast_ipc) { - wait_for_completion(&sc_chan->tx_done); - reinit_completion(&sc_chan->tx_done); - } + wait_for_completion(&sc_chan->tx_done); + reinit_completion(&sc_chan->tx_done); ret = mbox_send_message(sc_chan->ch, &data[i]); if (ret < 0) @@ -204,38 +204,57 @@ static int imx_scu_ipc_write(struct imx_sc_ipc *sc_ipc, void *msg) int imx_scu_call_rpc(struct imx_sc_ipc *sc_ipc, void *msg, bool have_resp) { struct imx_sc_rpc_msg *hdr; + struct arm_smccc_res res; int ret; + int i; if (WARN_ON(!sc_ipc || !msg)) return -EINVAL; mutex_lock(&sc_ipc->lock); + + for (i = 4; i < 8; i++) { + struct imx_sc_chan *sc_chan = &sc_ipc->chans[i]; + + sc_chan->rx_pos = sc_chan->idx; + } + reinit_completion(&sc_ipc->done); - if (have_resp) - sc_ipc->msg = msg; + sc_ipc->msg = msg; sc_ipc->count = 0; - ret = imx_scu_ipc_write(sc_ipc, msg); - if (ret < 0) { - dev_err(sc_ipc->dev, "RPC send msg failed: %d\n", ret); - goto out; - } + sc_ipc->rx_size = 0; + + if (xen_initial_domain()) { + arm_smccc_hvc(FSL_HVC_SC, (uint64_t)msg, !have_resp, 0, 0, 0, + 0, 0, &res); + if (res.a0) + printk("Error FSL_HVC_SC %ld\n", res.a0); - if (have_resp) { - if (!wait_for_completion_timeout(&sc_ipc->done, - MAX_RX_TIMEOUT)) { - dev_err(sc_ipc->dev, "RPC send msg timeout\n"); - mutex_unlock(&sc_ipc->lock); - return -ETIMEDOUT; + ret = res.a0; + + } else { + ret = imx_scu_ipc_write(sc_ipc, msg); + if (ret < 0) { + dev_err(sc_ipc->dev, "RPC send msg failed: %d\n", ret); + goto out; } - /* response status is stored in hdr->func field */ - hdr = msg; - ret = hdr->func; + if (have_resp) { + if (!wait_for_completion_timeout(&sc_ipc->done, + MAX_RX_TIMEOUT)) { + dev_err(sc_ipc->dev, "RPC send msg timeout\n"); + mutex_unlock(&sc_ipc->lock); + return -ETIMEDOUT; + } + + /* response status is stored in hdr->func field */ + hdr = msg; + ret = hdr->func; + } } out: - sc_ipc->msg = NULL; mutex_unlock(&sc_ipc->lock); dev_dbg(sc_ipc->dev, "RPC SVC done\n"); @@ -244,6 +263,71 @@ int imx_scu_call_rpc(struct imx_sc_ipc *sc_ipc, void *msg, bool have_resp) } EXPORT_SYMBOL(imx_scu_call_rpc); +int imx_scu_call_big_rpc(struct imx_sc_ipc *sc_ipc, void *msg, bool have_resp) +{ + struct imx_sc_rpc_msg *hdr; + struct arm_smccc_res res; + int ret; + int i; + + if (WARN_ON(!sc_ipc || !msg)) + return -EINVAL; + + mutex_lock(&sc_ipc->lock); + for (i = 4; i < 8; i++) { + struct mbox_client *cl = &sc_ipc->chans[i].cl; + + cl->rx_callback = imx_scu_big_rx_callback; + } + + reinit_completion(&sc_ipc->done); + + sc_ipc->msg = msg; + sc_ipc->count = 0; + sc_ipc->rx_size = 0; + if (xen_initial_domain()) { + arm_smccc_hvc(FSL_HVC_SC, (uint64_t)msg, !have_resp, 0, 0, 0, + 0, 0, &res); + if (res.a0) + printk("Error FSL_HVC_SC %ld\n", res.a0); + + ret = res.a0; + + } else { + ret = imx_scu_ipc_write(sc_ipc, msg); + if (ret < 0) { + dev_err(sc_ipc->dev, "RPC send msg failed: %d\n", ret); + goto out; + } + + if (have_resp) { + if (!wait_for_completion_timeout(&sc_ipc->done, + MAX_RX_TIMEOUT)) { + dev_err(sc_ipc->dev, "RPC send msg timeout\n"); + mutex_unlock(&sc_ipc->lock); + return -ETIMEDOUT; + } + + /* response status is stored in hdr->func field */ + hdr = msg; + ret = hdr->func; + } + } + +out: + for (i = 4; i < 8; i++) { + struct mbox_client *cl = &sc_ipc->chans[i].cl; + + cl->rx_callback = imx_scu_rx_callback; + } + mutex_unlock(&sc_ipc->lock); + + dev_dbg(sc_ipc->dev, "RPC SVC done\n"); + + return imx_sc_to_linux_errno(ret); +} +EXPORT_SYMBOL(imx_scu_call_big_rpc); + static int imx_scu_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -251,8 +335,6 @@ static int imx_scu_probe(struct platform_device *pdev) struct imx_sc_chan *sc_chan; struct mbox_client *cl; char *chan_name; - struct of_phandle_args args; - int num_channel; int ret; int i; @@ -260,20 +342,11 @@ static int imx_scu_probe(struct platform_device *pdev) if (!sc_ipc) return -ENOMEM; - ret = of_parse_phandle_with_args(pdev->dev.of_node, "mboxes", - "#mbox-cells", 0, &args); - if (ret) - return ret; - - sc_ipc->fast_ipc = of_device_is_compatible(args.np, "fsl,imx8-mu-scu"); - - num_channel = sc_ipc->fast_ipc ? 2 : SCU_MU_CHAN_NUM; - for (i = 0; i < num_channel; i++) { - if (i < num_channel / 2) + for (i = 0; i < SCU_MU_CHAN_NUM; i++) { + if (i < 4) chan_name = kasprintf(GFP_KERNEL, "tx%d", i); else - chan_name = kasprintf(GFP_KERNEL, "rx%d", - i - num_channel / 2); + chan_name = kasprintf(GFP_KERNEL, "rx%d", i - 4); if (!chan_name) return -ENOMEM; @@ -285,15 +358,13 @@ static int imx_scu_probe(struct platform_device *pdev) cl->knows_txdone = true; cl->rx_callback = imx_scu_rx_callback; - if (!sc_ipc->fast_ipc) { - /* Initial tx_done completion as "done" */ - cl->tx_done = imx_scu_tx_done; - init_completion(&sc_chan->tx_done); - complete(&sc_chan->tx_done); - } + /* Initial tx_done completion as "done" */ + cl->tx_done = imx_scu_tx_done; + init_completion(&sc_chan->tx_done); + complete(&sc_chan->tx_done); sc_chan->sc_ipc = sc_ipc; - sc_chan->idx = i % (num_channel / 2); + sc_chan->idx = i % 4; sc_chan->ch = mbox_request_channel_byname(cl, chan_name); if (IS_ERR(sc_chan->ch)) { ret = PTR_ERR(sc_chan->ch); @@ -337,7 +408,12 @@ static struct platform_driver imx_scu_driver = { }, .probe = imx_scu_probe, }; -builtin_platform_driver(imx_scu_driver); + +static int __init imx_scu_driver_init(void) +{ + return platform_driver_register(&imx_scu_driver); +} +subsys_initcall_sync(imx_scu_driver_init); MODULE_AUTHOR("Dong Aisheng "); MODULE_DESCRIPTION("IMX SCU firmware protocol driver"); diff --git a/drivers/firmware/imx/rm.c b/drivers/firmware/imx/rm.c new file mode 100644 index 00000000000000..abf36c1c2509fb --- /dev/null +++ b/drivers/firmware/imx/rm.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017~2020 NXP + * + * File containing client-side RPC functions for the RM service. These + * function are ported to clients that communicate to the SC. + */ + +#include + +struct imx_sc_msg_rm_rsrc_owned { + struct imx_sc_rpc_msg hdr; + u16 resource; +} __packed __aligned(4); + +/* + * This function check @resource is owned by current partition or not + * + * @param[in] ipc IPC handle + * @param[in] resource resource the control is associated with + * + * @return Returns 0 for success and < 0 for errors. + */ +bool imx_sc_rm_is_resource_owned(struct imx_sc_ipc *ipc, u16 resource) +{ + struct imx_sc_msg_rm_rsrc_owned msg; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_RM; + hdr->func = IMX_SC_RM_FUNC_IS_RESOURCE_OWNED; + hdr->size = 2; + + msg.resource = resource; + + imx_scu_call_rpc(ipc, &msg, true); + + return hdr->func; +} +EXPORT_SYMBOL(imx_sc_rm_is_resource_owned); + +struct imx_sc_msg_misc_find_memreg { + struct imx_sc_rpc_msg hdr; + union { + struct { + u32 add_start_hi; + u32 add_start_lo; + u32 add_end_hi; + u32 add_end_lo; + } req; + struct { + u8 val; + } resp; + } data; +}; + +int imx_sc_rm_find_memreg(struct imx_sc_ipc *ipc, u8 *mr, u64 addr_start, + u64 addr_end) +{ + struct imx_sc_msg_misc_find_memreg msg; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + int ret; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_RM; + hdr->func = IMX_SC_RM_FUNC_FIND_MEMREG; + hdr->size = 5; + + msg.data.req.add_start_hi = addr_start >> 32; + msg.data.req.add_start_lo = addr_start; + msg.data.req.add_end_hi = addr_end >> 32; + msg.data.req.add_end_lo = addr_end; + + ret = imx_scu_call_rpc(ipc, &msg, true); + if (ret) + return ret; + + if (mr) + *mr = msg.data.resp.val; + + return 0; +} +EXPORT_SYMBOL(imx_sc_rm_find_memreg); + +struct imx_sc_msg_misc_get_resource_owner { + struct imx_sc_rpc_msg hdr; + union { + struct { + u16 resource; + } req; + struct { + u8 val; + } resp; + } data; +}; + +int imx_sc_rm_get_resource_owner(struct imx_sc_ipc *ipc, u16 resource, u8 *pt) +{ + struct imx_sc_msg_misc_get_resource_owner msg; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + int ret; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_RM; + hdr->func = IMX_SC_RM_FUNC_GET_RESOURCE_OWNER; + hdr->size = 2; + + msg.data.req.resource = resource; + + ret = imx_scu_call_rpc(ipc, &msg, true); + if (ret) + return ret; + + if (pt) + *pt = msg.data.resp.val; + + return 0; +} +EXPORT_SYMBOL(imx_sc_rm_get_resource_owner); + +struct imx_sc_msg_set_memreg_permissions { + struct imx_sc_rpc_msg hdr; + u8 mr; + u8 pt; + u8 perm; +} __packed __aligned(4); + +int imx_sc_rm_set_memreg_permissions(struct imx_sc_ipc *ipc, u8 mr, + u8 pt, u8 perm) +{ + struct imx_sc_msg_set_memreg_permissions msg; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_RM; + hdr->func = IMX_SC_RM_FUNC_SET_MEMREG_PERMISSIONS; + hdr->size = 2; + + msg.mr = mr; + msg.pt = pt; + msg.perm = perm; + + return imx_scu_call_rpc(ipc, &msg, true); +} +EXPORT_SYMBOL(imx_sc_rm_set_memreg_permissions); + +int imx_sc_rm_get_did(struct imx_sc_ipc *ipc, u8 *did) +{ + struct imx_sc_rpc_msg msg; + struct imx_sc_rpc_msg *hdr = &msg; + int ret; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_RM; + hdr->func = IMX_SC_RM_FUNC_GET_DID; + hdr->size = 1; + + ret = imx_scu_call_rpc(ipc, &msg, true); + if (ret < 0) + return ret; + + if (did) + *did = msg.func; + + return 0; +} +EXPORT_SYMBOL(imx_sc_rm_get_did); diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c old mode 100644 new mode 100755 index af3ae0087de4e7..e737f2540bedbd --- a/drivers/firmware/imx/scu-pd.c +++ b/drivers/firmware/imx/scu-pd.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP + * Copyright 2017-2018,2020 NXP * Dong Aisheng * * Implementation of the SCU based Power Domains @@ -44,9 +44,13 @@ * */ +#include #include +#include #include +#include #include +#include #include #include #include @@ -55,6 +59,17 @@ #include #include #include +#include + +#define IMX_WU_MAX_IRQS (((IMX_SC_R_LAST + 31) / 32 ) * 32 ) + +#define IMX_SIP_WAKEUP_SRC 0xc2000009 +#define IMX_SIP_WAKEUP_SRC_SCU 0x1 +#define IMX_SIP_WAKEUP_SRC_IRQSTEER 0x2 + +static u32 wu[IMX_WU_MAX_IRQS]; +static int wu_num; +static void __iomem *gic_dist_base; /* SCU Power Mode Protocol definition */ struct imx_sc_msg_req_set_resource_power_mode { @@ -85,6 +100,8 @@ struct imx_sc_pd_soc { u8 num_ranges; }; +int imx_con_rsrc; + static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { /* LSIO SS */ { "pwm", IMX_SC_R_PWM_0, 8, true, 0 }, @@ -98,6 +115,7 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { /* CONN SS */ { "usb", IMX_SC_R_USB_0, 2, true, 0 }, { "usb0phy", IMX_SC_R_USB_0_PHY, 1, false, 0 }, + { "usb1phy", IMX_SC_R_USB_1_PHY, 1, false, 0}, { "usb2", IMX_SC_R_USB_2, 1, false, 0 }, { "usb2phy", IMX_SC_R_USB_2_PHY, 1, false, 0 }, { "sdhc", IMX_SC_R_SDHC_0, 3, true, 0 }, @@ -109,14 +127,26 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "audio-pll0", IMX_SC_R_AUDIO_PLL_0, 1, false, 0 }, { "audio-pll1", IMX_SC_R_AUDIO_PLL_1, 1, false, 0 }, { "audio-clk-0", IMX_SC_R_AUDIO_CLK_0, 1, false, 0 }, - { "dma0-ch", IMX_SC_R_DMA_0_CH0, 16, true, 0 }, + { "audio-clk-1", IMX_SC_R_AUDIO_CLK_1, 1, false, 0 }, + { "mclk-out-0", IMX_SC_R_MCLK_OUT_0, 1, false, 0 }, + { "mclk-out-1", IMX_SC_R_MCLK_OUT_1, 1, false, 0 }, + { "dma0-ch", IMX_SC_R_DMA_0_CH0, 32, true, 0 }, { "dma1-ch", IMX_SC_R_DMA_1_CH0, 16, true, 0 }, - { "dma2-ch", IMX_SC_R_DMA_2_CH0, 5, true, 0 }, + { "dma2-ch-0", IMX_SC_R_DMA_2_CH0, 5, true, 0 }, + { "dma2-ch-1", IMX_SC_R_DMA_2_CH5, 27, true, 0 }, + { "dma3-ch", IMX_SC_R_DMA_3_CH0, 32, true, 0 }, { "asrc0", IMX_SC_R_ASRC_0, 1, false, 0 }, { "asrc1", IMX_SC_R_ASRC_1, 1, false, 0 }, { "esai0", IMX_SC_R_ESAI_0, 1, false, 0 }, + { "esai1", IMX_SC_R_ESAI_1, 1, false, 0 }, { "spdif0", IMX_SC_R_SPDIF_0, 1, false, 0 }, + { "spdif1", IMX_SC_R_SPDIF_1, 1, false, 0 }, { "sai", IMX_SC_R_SAI_0, 3, true, 0 }, + { "sai3", IMX_SC_R_SAI_3, 1, false, 0 }, + { "sai4", IMX_SC_R_SAI_4, 1, false, 0 }, + { "sai5", IMX_SC_R_SAI_5, 1, false, 0 }, + { "sai6", IMX_SC_R_SAI_6, 1, false, 0 }, + { "sai7", IMX_SC_R_SAI_7, 1, false, 0 }, { "amix", IMX_SC_R_AMIX, 1, false, 0 }, { "mqs0", IMX_SC_R_MQS_0, 1, false, 0 }, { "dsp", IMX_SC_R_DSP, 1, false, 0 }, @@ -130,6 +160,7 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "lcd", IMX_SC_R_LCD_0, 1, true, 0 }, { "lcd0-pwm", IMX_SC_R_LCD_0_PWM_0, 1, true, 0 }, { "lpuart", IMX_SC_R_UART_0, 4, true, 0 }, + { "sim", IMX_SC_R_EMVSIM_0, 2, true, 0 }, { "lpspi", IMX_SC_R_SPI_0, 4, true, 0 }, { "irqstr_dsp", IMX_SC_R_IRQSTR_DSP, 1, false, 0 }, @@ -138,13 +169,24 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "vpu-pid", IMX_SC_R_VPU_PID0, 8, true, 0 }, { "vpu-dec0", IMX_SC_R_VPU_DEC_0, 1, false, 0 }, { "vpu-enc0", IMX_SC_R_VPU_ENC_0, 1, false, 0 }, + { "vpu-enc1", IMX_SC_R_VPU_ENC_1, 1, false, 0 }, + { "vpu-ts0", IMX_SC_R_VPU_TS_0, 1, false, 0 }, + { "vpu-mu0", IMX_SC_R_VPU_MU_0, 1, false, 0 }, + { "vpu-mu1", IMX_SC_R_VPU_MU_1, 1, false, 0 }, + { "vpu-mu2", IMX_SC_R_VPU_MU_2, 1, false, 0 }, + { "vpu-mu3", IMX_SC_R_VPU_MU_3, 1, false, 0 }, /* GPU SS */ { "gpu0-pid", IMX_SC_R_GPU_0_PID0, 4, true, 0 }, + { "gpu1-pid", IMX_SC_R_GPU_1_PID0, 4, true, 0 }, + /* HSIO SS */ + { "pcie-a", IMX_SC_R_PCIE_A, 1, false, 0 }, + { "serdes-0", IMX_SC_R_SERDES_0, 1, false, 0 }, { "pcie-b", IMX_SC_R_PCIE_B, 1, false, 0 }, { "serdes-1", IMX_SC_R_SERDES_1, 1, false, 0 }, + { "sata-0", IMX_SC_R_SATA_0, 1, false, 0 }, { "hsio-gpio", IMX_SC_R_HSIO_GPIO, 1, false, 0 }, /* MIPI SS */ @@ -152,12 +194,85 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "mipi0-pwm0", IMX_SC_R_MIPI_0_PWM_0, 1, false, 0 }, { "mipi0-i2c", IMX_SC_R_MIPI_0_I2C_0, 2, true, 0 }, + { "mipi1", IMX_SC_R_MIPI_1, 1, 0 }, + { "mipi1-pwm0", IMX_SC_R_MIPI_1_PWM_0, 1, 0 }, + { "mipi1-i2c", IMX_SC_R_MIPI_1_I2C_0, 2, 1 }, + /* LVDS SS */ { "lvds0", IMX_SC_R_LVDS_0, 1, false, 0 }, + { "lvds0-i2c0", IMX_SC_R_LVDS_0_I2C_0, 1, false, 0 }, + { "lvds0-pwm0", IMX_SC_R_LVDS_0_PWM_0, 1, false, 0 }, + + { "lvds1", IMX_SC_R_LVDS_1, 1, false, 0 }, + { "lvds1-i2c0", IMX_SC_R_LVDS_1_I2C_0, 1, false, 0 }, + { "lvds1-pwm0", IMX_SC_R_LVDS_1_PWM_0, 1, false, 0 }, + + { "mipi1", IMX_SC_R_MIPI_1, 1, 0 }, + { "mipi1-pwm0", IMX_SC_R_MIPI_1_PWM_0, 1, 0 }, + { "mipi1-i2c", IMX_SC_R_MIPI_1_I2C_0, 2, 1 }, + { "lvds1", IMX_SC_R_LVDS_1, 1, 0 }, /* DC SS */ { "dc0", IMX_SC_R_DC_0, 1, false, 0 }, { "dc0-pll", IMX_SC_R_DC_0_PLL_0, 2, true, 0 }, + { "dc0-video", IMX_SC_R_DC_0_VIDEO0, 2, true, 0 }, + + { "dc1", IMX_SC_R_DC_1, 1, false, 0 }, + { "dc1-pll", IMX_SC_R_DC_1_PLL_0, 2, true, 0 }, + { "dc1-video", IMX_SC_R_DC_1_VIDEO0, 2, true, 0 }, + + /* CM40 SS */ + { "cm40_i2c", IMX_SC_R_M4_0_I2C, 1, false, 0 }, + { "cm40_intmux", IMX_SC_R_M4_0_INTMUX, 1, false, 0 }, + { "cm40_pid", IMX_SC_R_M4_0_PID0, 5, true, 0}, + { "cm40_mu1a", IMX_SC_R_M4_0_MU_1A, 1, false, 0}, + + /* CM41 SS */ + { "cm41_i2c", IMX_SC_R_M4_1_I2C, 1, false, 0 }, + { "cm41_intmux", IMX_SC_R_M4_1_INTMUX, 1, false, 0 }, + { "cm41_pid", IMX_SC_R_M4_1_PID0, 5, true, 0}, + { "cm41_mu1a", IMX_SC_R_M4_1_MU_1A, 1, false, 0}, + + /* IMAGE SS */ + { "img-pdma", IMX_SC_R_ISI_CH0, 8, true, 0 }, + { "img-csi0", IMX_SC_R_CSI_0, 1, false, 0 }, + { "img-csi0-i2c0", IMX_SC_R_CSI_0_I2C_0, 1, false, 0 }, + { "img-csi0-pwm0", IMX_SC_R_CSI_0_PWM_0, 1, false, 0 }, + { "img-csi1", IMX_SC_R_CSI_1, 1, false, 0 }, + { "img-csi1-i2c0", IMX_SC_R_CSI_1_I2C_0, 1, false, 0 }, + { "img-csi1-pwm0", IMX_SC_R_CSI_1_PWM_0, 1, false, 0 }, + { "img-parallel", IMX_SC_R_PI_0, 1, false, 0 }, + { "img-parallel-i2c0", IMX_SC_R_PI_0_I2C_0, 1, false, 0 }, + { "img-parallel-pwm0", IMX_SC_R_PI_0_PWM_0, 2, true, 0 }, + { "img-parallel-pll", IMX_SC_R_PI_0_PLL, 1, false, 0 }, + { "img-jpegdec-mp", IMX_SC_R_MJPEG_DEC_MP, 1, false, 0 }, + { "img-jpegdec-s0", IMX_SC_R_MJPEG_DEC_S0, 4, true, 0 }, + { "img-jpegenc-mp", IMX_SC_R_MJPEG_ENC_MP, 1, false, 0 }, + { "img-jpegenc-s0", IMX_SC_R_MJPEG_ENC_S0, 4, true, 0 }, + + /* HDMI TX SS */ + { "hdmi-tx", IMX_SC_R_HDMI, 1, false, 0}, + { "hdmi-tx-i2s", IMX_SC_R_HDMI_I2S, 1, false, 0}, + { "hdmi-tx-i2c0", IMX_SC_R_HDMI_I2C_0, 1, false, 0}, + { "hdmi-tx-pll0", IMX_SC_R_HDMI_PLL_0, 1, false, 0}, + { "hdmi-tx-pll1", IMX_SC_R_HDMI_PLL_1, 1, false, 0}, + + /* SECURITY SS */ + { "sec-jr", IMX_SC_R_CAAM_JR2, 2, true, 2}, + + /* BOARD SS */ + { "board", IMX_SC_R_BOARD_R0, 8, true, 0}, + + /* SECO SS */ + { "seco_mu", IMX_SC_R_SECO_MU_2, 3, true, 2}, + + /* V2X SS */ + { "v2x_mu", IMX_SC_R_V2X_MU_0, 2, true, 0}, + { "v2x_mu", IMX_SC_R_V2X_MU_2, 1, true, 2}, + { "v2x_mu", IMX_SC_R_V2X_MU_3, 2, true, 3}, + + /* DB SS */ + { "perf", IMX_SC_R_PERF, 1, false, 0}, }; static const struct imx_sc_pd_soc imx8qxp_scu_pd = { @@ -173,6 +288,73 @@ to_imx_sc_pd(struct generic_pm_domain *genpd) return container_of(genpd, struct imx_sc_pm_domain, pd); } +static int imx_pm_domains_suspend(void) +{ + struct arm_smccc_res res; + u32 offset; + int i; + + for (i = 0; i < wu_num; i++) { + offset = GICD_ISENABLER + ((wu[i] + 32) / 32) * 4; + if (BIT(wu[i] % 32) & readl_relaxed(gic_dist_base + offset)) { + arm_smccc_smc(IMX_SIP_WAKEUP_SRC, + IMX_SIP_WAKEUP_SRC_IRQSTEER, + 0, 0, 0, 0, 0, 0, &res); + return 0; + } + } + + arm_smccc_smc(IMX_SIP_WAKEUP_SRC, + IMX_SIP_WAKEUP_SRC_SCU, + 0, 0, 0, 0, 0, 0, &res); + + return 0; +} + +struct syscore_ops imx_pm_domains_syscore_ops = { + .suspend = imx_pm_domains_suspend, +}; + +static void imx_sc_pd_enable_irqsteer_wakeup(struct device_node *np) +{ + struct device_node *gic_node; + unsigned int i; + + wu_num = of_property_count_u32_elems(np, "wakeup-irq"); + if (wu_num <= 0) { + pr_warn("no irqsteer wakeup source supported!\n"); + return; + } + + gic_node = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); + WARN_ON(!gic_node); + + gic_dist_base = of_iomap(gic_node, 0); + WARN_ON(!gic_dist_base); + + for (i = 0; i < wu_num; i++) + WARN_ON(of_property_read_u32_index(np, "wakeup-irq", i, &wu[i])); + + register_syscore_ops(&imx_pm_domains_syscore_ops); +} + +static void imx_sc_pd_get_console_rsrc(void) +{ + struct of_phandle_args specs; + int ret; + + if (!of_stdout) + return; + + ret = of_parse_phandle_with_args(of_stdout, "power-domains", + "#power-domain-cells", + 0, &specs); + if (ret) + return; + + imx_con_rsrc = specs.args[0]; +} + static int imx_sc_pd_power(struct generic_pm_domain *domain, bool power_on) { struct imx_sc_msg_req_set_resource_power_mode msg; @@ -188,7 +370,12 @@ static int imx_sc_pd_power(struct generic_pm_domain *domain, bool power_on) hdr->size = 2; msg.resource = pd->rsrc; - msg.mode = power_on ? IMX_SC_PM_PW_MODE_ON : IMX_SC_PM_PW_MODE_LP; + msg.mode = power_on ? IMX_SC_PM_PW_MODE_ON : pd->pd.state_idx ? + IMX_SC_PM_PW_MODE_OFF : IMX_SC_PM_PW_MODE_LP; + + /* keep uart console power on for no_console_suspend */ + if (imx_con_rsrc == pd->rsrc && !console_suspend_enabled && !power_on) + return 0; ret = imx_scu_call_rpc(pm_ipc_handle, &msg, true); if (ret) @@ -233,15 +420,34 @@ imx_scu_add_pm_domain(struct device *dev, int idx, const struct imx_sc_pd_range *pd_ranges) { struct imx_sc_pm_domain *sc_pd; + struct genpd_power_state *states; + bool is_off = true; int ret; + if (!imx_sc_rm_is_resource_owned(pm_ipc_handle, pd_ranges->rsrc + idx)) + return NULL; + sc_pd = devm_kzalloc(dev, sizeof(*sc_pd), GFP_KERNEL); if (!sc_pd) return ERR_PTR(-ENOMEM); + states = devm_kcalloc(dev, 2, sizeof(*states), GFP_KERNEL); + if (!states) { + devm_kfree(dev, sc_pd); + return ERR_PTR(-ENOMEM); + } + sc_pd->rsrc = pd_ranges->rsrc + idx; sc_pd->pd.power_off = imx_sc_pd_power_off; sc_pd->pd.power_on = imx_sc_pd_power_on; + sc_pd->pd.flags |= GENPD_FLAG_ACTIVE_WAKEUP; + states[0].power_off_latency_ns = 25000; + states[0].power_on_latency_ns = 25000; + states[1].power_off_latency_ns = 2500000; + states[1].power_on_latency_ns = 2500000; + + sc_pd->pd.states = states; + sc_pd->pd.state_count = 2; if (pd_ranges->postfix) snprintf(sc_pd->name, sizeof(sc_pd->name), @@ -251,20 +457,26 @@ imx_scu_add_pm_domain(struct device *dev, int idx, "%s", pd_ranges->name); sc_pd->pd.name = sc_pd->name; + if (imx_con_rsrc == sc_pd->rsrc) { + sc_pd->pd.flags |= GENPD_FLAG_RPM_ALWAYS_ON; + is_off = false; + } if (sc_pd->rsrc >= IMX_SC_R_LAST) { dev_warn(dev, "invalid pd %s rsrc id %d found", sc_pd->name, sc_pd->rsrc); devm_kfree(dev, sc_pd); + devm_kfree(dev, states); return NULL; } - ret = pm_genpd_init(&sc_pd->pd, NULL, true); + ret = pm_genpd_init(&sc_pd->pd, NULL, is_off); if (ret) { dev_warn(dev, "failed to init pd %s rsrc id %d", sc_pd->name, sc_pd->rsrc); devm_kfree(dev, sc_pd); + devm_kfree(dev, states); return NULL; } @@ -326,6 +538,9 @@ static int imx_sc_pd_probe(struct platform_device *pdev) if (!pd_soc) return -ENODEV; + imx_sc_pd_get_console_rsrc(); + imx_sc_pd_enable_irqsteer_wakeup(pdev->dev.of_node); + return imx_scu_init_pm_domains(&pdev->dev, pd_soc); } @@ -342,7 +557,12 @@ static struct platform_driver imx_sc_pd_driver = { }, .probe = imx_sc_pd_probe, }; -builtin_platform_driver(imx_sc_pd_driver); + +static int __init imx_sc_pd_driver_init(void) +{ + return platform_driver_register(&imx_sc_pd_driver); +} +subsys_initcall(imx_sc_pd_driver_init); MODULE_AUTHOR("Dong Aisheng "); MODULE_DESCRIPTION("IMX SCU Power Domain driver"); diff --git a/drivers/firmware/imx/seco.c b/drivers/firmware/imx/seco.c new file mode 100644 index 00000000000000..7f71b1d7f0224c --- /dev/null +++ b/drivers/firmware/imx/seco.c @@ -0,0 +1,249 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + * + * File containing client-side RPC functions for the SECO service. These + * function are ported to clients that communicate to the SC. + */ + +#include + +struct imx_sc_msg_seco_get_build_id { + struct imx_sc_rpc_msg hdr; + u32 version; + u32 commit; +}; + +int imx_sc_seco_build_info(struct imx_sc_ipc *ipc, uint32_t *version, + uint32_t *commit) +{ + struct imx_sc_msg_seco_get_build_id msg = {0}; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_SECO; + hdr->func = IMX_SC_SECO_FUNC_BUILD_INFO; + hdr->size = 1; + + imx_scu_call_rpc(ipc, &msg, true); + + if (version) + *version = msg.version; + if (commit) + *commit = msg.commit; + + return 0; +} +EXPORT_SYMBOL(imx_sc_seco_build_info); + +struct imx_sc_msg_seco_sab_msg { + struct imx_sc_rpc_msg hdr; + u32 smsg_addr_hi; + u32 smsg_addr_lo; +}; + +int imx_sc_seco_sab_msg(struct imx_sc_ipc *ipc, u64 smsg_addr) +{ + struct imx_sc_msg_seco_sab_msg msg; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + int ret; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_SECO; + hdr->func = IMX_SC_SECO_FUNC_SAB_MSG; + hdr->size = 3; + + msg.smsg_addr_hi = smsg_addr >> 32; + msg.smsg_addr_lo = smsg_addr; + + ret = imx_scu_call_rpc(ipc, &msg, true); + return ret; +} +EXPORT_SYMBOL(imx_sc_seco_sab_msg); + +int imx_sc_seco_secvio_enable(struct imx_sc_ipc *ipc) +{ + struct imx_sc_rpc_msg msg; + struct imx_sc_rpc_msg *hdr = &msg; + int ret; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = (uint8_t)IMX_SC_RPC_SVC_SECO; + hdr->func = (uint8_t)IMX_SC_SECO_FUNC_SECVIO_ENABLE; + hdr->size = 1; + + ret = imx_scu_call_rpc(ipc, &msg, true); + if (ret) + return ret; + + return 0; +} +EXPORT_SYMBOL(imx_sc_seco_secvio_enable); + +struct imx_sc_msg_req_seco_config { + struct imx_sc_rpc_msg hdr; + u32 data0; + u32 data1; + u32 data2; + u32 data3; + u32 data4; + u8 id; + u8 access; + u8 size; +} __packed __aligned(4); + +struct imx_sc_msg_resp_seco_config { + struct imx_sc_rpc_msg hdr; + u32 data0; + u32 data1; + u32 data2; + u32 data3; + u32 data4; +} __packed; + +int imx_sc_seco_secvio_config(struct imx_sc_ipc *ipc, u8 id, u8 access, + u32 *data0, u32 *data1, u32 *data2, u32 *data3, + u32 *data4, u8 size) +{ + struct imx_sc_msg_req_seco_config msg; + struct imx_sc_msg_resp_seco_config *resp; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + int ret; + + if (!ipc) + return -EINVAL; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = (uint8_t)IMX_SC_RPC_SVC_SECO; + hdr->func = (uint8_t)IMX_SC_SECO_FUNC_SECVIO_CONFIG; + hdr->size = 7; + + /* Check the pointers on data are valid and set it if doing a write */ + switch (size) { + case 5: + if (data4) { + if (access) + msg.data4 = *data4; + } else { + return -EINVAL; + } + /* fallthrough */ + case 4: + if (data3) { + if (access) + msg.data3 = *data3; + } else { + return -EINVAL; + } + /* fallthrough */ + case 3: + if (data2) { + if (access) + msg.data2 = *data2; + } else { + return -EINVAL; + } + /* fallthrough */ + case 2: + if (data1) { + if (access) + msg.data1 = *data1; + } else { + return -EINVAL; + } + /* fallthrough */ + case 1: + if (data0) { + if (access) + msg.data0 = *data0; + } else { + return -EINVAL; + } + break; + default: + return -EINVAL; + } + + msg.id = id; + msg.access = access; + msg.size = size; + + ret = imx_scu_call_big_rpc(ipc, &msg, true); + if (ret) + return ret; + + resp = (struct imx_sc_msg_resp_seco_config *)&msg; + + /* Pointers already checked so we just copy the data if reading */ + if (!access) + switch (size) { + case 5: + *data4 = resp->data4; + /* fallthrough */ + case 4: + *data3 = resp->data3; + /* fallthrough */ + case 3: + *data2 = resp->data2; + /* fallthrough */ + case 2: + *data1 = resp->data1; + /* fallthrough */ + case 1: + *data0 = resp->data0; + } + + return 0; +} +EXPORT_SYMBOL(imx_sc_seco_secvio_config); + +struct imx_sc_msg_req_seco_dgo_config { + struct imx_sc_rpc_msg hdr; + u32 data; + u8 id; + u8 access; +} __packed __aligned(4); + +struct imx_sc_msg_resp_seco_dgo_config { + struct imx_sc_rpc_msg hdr; + u32 data; +} __packed; + +int imx_sc_seco_secvio_dgo_config(struct imx_sc_ipc *ipc, u8 id, u8 access, + u32 *data) +{ + struct imx_sc_msg_req_seco_dgo_config msg; + struct imx_sc_msg_resp_seco_dgo_config *resp; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + int ret; + + if (!ipc) + return -EINVAL; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = (uint8_t)IMX_SC_RPC_SVC_SECO; + hdr->func = (uint8_t)IMX_SC_SECO_FUNC_SECVIO_DGO_CONFIG; + hdr->size = 3; + + if (access) { + if (data) + msg.data = *data; + else + return -EINVAL; + } + + msg.access = access; + msg.id = id; + + ret = imx_scu_call_rpc(ipc, &msg, true); + if (ret) + return ret; + + resp = (struct imx_sc_msg_resp_seco_dgo_config *)&msg; + + if (!access && data) + *data = resp->data; + + return 0; +} +EXPORT_SYMBOL(imx_sc_seco_secvio_dgo_config); diff --git a/drivers/firmware/imx/seco_mu.c b/drivers/firmware/imx/seco_mu.c new file mode 100644 index 00000000000000..dafb277b4da10d --- /dev/null +++ b/drivers/firmware/imx/seco_mu.c @@ -0,0 +1,1166 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Copyright 2019-2020 NXP + */ + +/* + * This driver allows to send messages to the SECO using a shared mailbox. The + * messages must follow the protocol defined. + */ + +/* + * Architecture of the driver: + * + * Non-Secure + Secure + * | + * | + * +---------+ +-------------+ | + * |seco_mu.c+<---->+imx-mailbox.c| | + * | | | mailbox.c +<-->+------+ +------+ + * +---+-----+ +-------------+ | MU X +<-->+ SECO | + * | +------+ +------+ + * +----------------+ | + * | | | + * v v | + * logical logical | + * receiver waiter | + * + + | + * | | | + * | | | + * | +----+------+ | + * | | | | + * | | | | + * device_ctx device_ctx device_ctx | + * | + * User 0 User 1 User Y | + * +------+ +------+ +------+ | + * |misc.c| |misc.c| |misc.c| | + * kernel space +------+ +------+ +------+ | + * | + * +------------------------------------------------------ | + * | | | | + * userspace /dev/seco_muXch0 | | | + * /dev/seco_muXch1 | | + * /dev/seco_muXchY | + * | + * + * When a user sends a command to the seco, it registers its device_ctx as + * waiter of a response from SECO + * + * A user can be registered as receiver of command by the SECO. + * + * When a message is received, the driver select the device_ctx receiving the + * message depending on the tag in the message. It selects the device_ctx + * accordingly. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_RECV_SIZE 31 +#define MAX_RECV_SIZE_BYTES (MAX_RECV_SIZE * sizeof(u32)) +#define MAX_MESSAGE_SIZE 31 +#define MAX_MESSAGE_SIZE_BYTES (MAX_MESSAGE_SIZE * sizeof(u32)) +#define MESSAGE_SIZE(hdr) (((struct she_mu_hdr *)(&(hdr)))->size) +#define MESSAGE_TAG(hdr) (((struct she_mu_hdr *)(&(hdr)))->tag) + +#define DEFAULT_MESSAGING_TAG_COMMAND (0x17u) +#define DEFAULT_MESSAGING_TAG_RESPONSE (0xe1u) + +#define SECURE_RAM_BASE_ADDRESS (0x31800000ULL) +#define SECURE_RAM_BASE_ADDRESS_SCU (0x20800000u) +#define SECURE_RAM_SIZE (0x10000ULL) + +#define SECO_MU_DEFAULT_MAX_USERS 4 + +#define SECO_MU_INTERRUPT_INDEX (0u) +#define SECO_DEFAULT_MU_INDEX (1u) +#define SECO_DEFAULT_TZ (0u) +#define DEFAULT_DID (0u) + +#define MAX_DATA_SIZE_PER_USER (65 * 1024) + +/* Header of the messages exchange with the SECO */ +struct she_mu_hdr { + u8 ver; + u8 size; + u8 command; + u8 tag; +} __packed; + +/* Status of a char device */ +enum mu_device_status_t { + MU_FREE, + MU_OPENED +}; + +struct seco_shared_mem { + dma_addr_t dma_addr; + u32 size; + u32 pos; + u8 *ptr; +}; + +struct seco_out_buffer_desc { + u8 *out_ptr; + u8 *out_usr_ptr; + u32 out_size; + struct list_head link; +}; + +/* Private struct for each char device instance. */ +struct seco_mu_device_ctx { + struct device *dev; + struct seco_mu_priv *mu_priv; + struct miscdevice miscdev; + + enum mu_device_status_t status; + wait_queue_head_t wq; + struct semaphore fops_lock; + + u32 pending_hdr; + struct list_head pending_out; + + struct seco_shared_mem secure_mem; + struct seco_shared_mem non_secure_mem; + + u32 temp_cmd[MAX_MESSAGE_SIZE]; + u32 temp_resp[MAX_RECV_SIZE]; + u32 temp_resp_size; +}; + +/* Private struct for seco MU driver. */ +struct seco_mu_priv { + struct seco_mu_device_ctx *cmd_receiver_dev; + struct seco_mu_device_ctx *waiting_rsp_dev; + /* + * prevent parallel access to the MU registers + * e.g. a user trying to send a command while the other one is + * sending a response. + */ + struct mutex mu_lock; + /* + * prevent a command to be sent on the MU while another one is still + * processing. (response to a command is allowed) + */ + struct mutex mu_cmd_lock; + struct device *dev; + u32 seco_mu_id; + u8 cmd_tag; + u8 rsp_tag; + + struct mbox_client cl; + struct mbox_chan *tx_chan; + struct mbox_chan *rx_chan; + + struct imx_sc_ipc *ipc_scu; + u8 seco_part_owner; +}; + +/* macro to log operation of a misc device */ +#define miscdev_dbg(p_miscdev, fmt, va_args...) \ + ({ \ + struct miscdevice *_p_miscdev = p_miscdev; \ + dev_dbg((_p_miscdev)->parent, "%s: " fmt, (_p_miscdev)->name, \ + ##va_args); \ + }) + +#define miscdev_info(p_miscdev, fmt, va_args...) \ + ({ \ + struct miscdevice *_p_miscdev = p_miscdev; \ + dev_info((_p_miscdev)->parent, "%s: " fmt, (_p_miscdev)->name, \ + ##va_args); \ + }) + +#define miscdev_err(p_miscdev, fmt, va_args...) \ + ({ \ + struct miscdevice *_p_miscdev = p_miscdev; \ + dev_err((_p_miscdev)->parent, "%s: " fmt, (_p_miscdev)->name, \ + ##va_args); \ + }) + +/* macro to log operation of a device context */ +#define devctx_dbg(p_devctx, fmt, va_args...) \ + miscdev_dbg(&((p_devctx)->miscdev), fmt, ##va_args) +#define devctx_info(p_devctx, fmt, va_args...) \ + miscdev_info(&((p_devctx)->miscdev), fmt, ##va_args) +#define devctx_err(p_devctx, fmt, va_args...) \ + miscdev_err((&(p_devctx)->miscdev), fmt, ##va_args) + +#define IMX_SC_RM_PERM_FULL 7U /* Full access */ + +/* Give access to SECU to the memory we want to share */ +static int seco_mu_setup_seco_memory_access(struct seco_mu_device_ctx *dev_ctx, + u64 addr, u32 len) +{ + struct seco_mu_priv *priv = dev_get_drvdata(dev_ctx->dev); + int ret; + u8 mr; + + ret = imx_sc_rm_find_memreg(priv->ipc_scu, &mr, addr, addr + len); + if (ret) { + devctx_err(dev_ctx, "Fail find memreg\n"); + goto exit; + } + + ret = imx_sc_rm_set_memreg_permissions(priv->ipc_scu, mr, + priv->seco_part_owner, + IMX_SC_RM_PERM_FULL); + if (ret) { + devctx_err(dev_ctx, "Fail set permission for resource\n"); + goto exit; + } + +exit: + return ret; +} + +/* + * File operations for user-space + */ +/* Open a char device. */ +static int seco_mu_fops_open(struct inode *nd, struct file *fp) +{ + struct seco_mu_device_ctx *dev_ctx = container_of(fp->private_data, + struct seco_mu_device_ctx, miscdev); + int err; + + /* Avoid race if opened at the same time */ + if (down_trylock(&dev_ctx->fops_lock)) + return -EBUSY; + + /* Authorize only 1 instance. */ + if (dev_ctx->status != MU_FREE) { + err = -EBUSY; + goto exit; + } + + /* + * Allocate some memory for data exchanges with SECO. + * This will be used for data not requiring secure memory. + */ + dev_ctx->non_secure_mem.ptr = dmam_alloc_coherent(dev_ctx->dev, + MAX_DATA_SIZE_PER_USER, + &dev_ctx->non_secure_mem.dma_addr, + GFP_KERNEL); + if (!dev_ctx->non_secure_mem.ptr) { + err = -ENOMEM; + devctx_err(dev_ctx, "Failed to map shared memory with SECO\n"); + goto exit; + } + + err = seco_mu_setup_seco_memory_access(dev_ctx, + dev_ctx->non_secure_mem.dma_addr, + MAX_DATA_SIZE_PER_USER); + if (err) { + err = -EPERM; + devctx_err(dev_ctx, + "Failed to share access to shared memory\n"); + goto free_coherent; + } + + dev_ctx->non_secure_mem.size = MAX_DATA_SIZE_PER_USER; + dev_ctx->non_secure_mem.pos = 0; + dev_ctx->status = MU_OPENED; + + dev_ctx->pending_hdr = 0; + + goto exit; + +free_coherent: + dmam_free_coherent(dev_ctx->mu_priv->dev, MAX_DATA_SIZE_PER_USER, + dev_ctx->non_secure_mem.ptr, + dev_ctx->non_secure_mem.dma_addr); + +exit: + up(&dev_ctx->fops_lock); + return err; +} + +/* Close a char device. */ +static int seco_mu_fops_close(struct inode *nd, struct file *fp) +{ + struct seco_mu_device_ctx *dev_ctx = container_of(fp->private_data, + struct seco_mu_device_ctx, miscdev); + struct seco_mu_priv *mu_priv = dev_ctx->mu_priv; + struct seco_out_buffer_desc *out_buf_desc; + + /* Avoid race if closed at the same time */ + if (down_trylock(&dev_ctx->fops_lock)) + return -EBUSY; + + /* The device context has not been opened */ + if (dev_ctx->status != MU_OPENED) + goto exit; + + /* check if this device was registered as command receiver. */ + if (mu_priv->cmd_receiver_dev == dev_ctx) + mu_priv->cmd_receiver_dev = NULL; + + /* check if this device was registered as waiting response. */ + if (mu_priv->waiting_rsp_dev == dev_ctx) { + mu_priv->waiting_rsp_dev = NULL; + mutex_unlock(&mu_priv->mu_cmd_lock); + } + + /* Unmap secure memory shared buffer. */ + if (dev_ctx->secure_mem.ptr) + devm_iounmap(dev_ctx->dev, dev_ctx->secure_mem.ptr); + + dev_ctx->secure_mem.ptr = NULL; + dev_ctx->secure_mem.dma_addr = 0; + dev_ctx->secure_mem.size = 0; + dev_ctx->secure_mem.pos = 0; + + /* Free non-secure shared buffer. */ + dmam_free_coherent(dev_ctx->mu_priv->dev, MAX_DATA_SIZE_PER_USER, + dev_ctx->non_secure_mem.ptr, + dev_ctx->non_secure_mem.dma_addr); + + dev_ctx->non_secure_mem.ptr = NULL; + dev_ctx->non_secure_mem.dma_addr = 0; + dev_ctx->non_secure_mem.size = 0; + dev_ctx->non_secure_mem.pos = 0; + + while (!list_empty(&dev_ctx->pending_out)) { + out_buf_desc = list_first_entry_or_null(&dev_ctx->pending_out, + struct seco_out_buffer_desc, + link); + __list_del_entry(&out_buf_desc->link); + devm_kfree(dev_ctx->dev, out_buf_desc); + } + + dev_ctx->status = MU_FREE; + +exit: + up(&dev_ctx->fops_lock); + return 0; +} + +/* Write a message to the MU. */ +static ssize_t seco_mu_fops_write(struct file *fp, const char __user *buf, + size_t size, loff_t *ppos) +{ + struct seco_mu_device_ctx *dev_ctx = container_of(fp->private_data, + struct seco_mu_device_ctx, miscdev); + struct seco_mu_priv *mu_priv = dev_ctx->mu_priv; + u32 nb_words = 0, header; + int err; + + devctx_dbg(dev_ctx, "write from buf (%p)%ld, ppos=%lld\n", buf, size, + ((ppos) ? *ppos : 0)); + + if (down_interruptible(&dev_ctx->fops_lock)) + return -EBUSY; + + if (dev_ctx->status != MU_OPENED) { + err = -EINVAL; + goto exit; + } + + if (size < sizeof(struct she_mu_hdr)) { + devctx_err(dev_ctx, "User buffer too small(%ld < %lu)\n", size, + sizeof(struct she_mu_hdr)); + err = -ENOSPC; + goto exit; + } + + if (size > MAX_MESSAGE_SIZE_BYTES) { + devctx_err(dev_ctx, "User buffer too big(%ld > %lu)\n", size, + MAX_MESSAGE_SIZE_BYTES); + err = -ENOSPC; + goto exit; + } + + /* Copy data to buffer */ + err = (int)copy_from_user(dev_ctx->temp_cmd, buf, size); + if (err) { + err = -EFAULT; + devctx_err(dev_ctx, "Fail copy message from user\n"); + goto exit; + } + + print_hex_dump_debug("from user ", DUMP_PREFIX_OFFSET, 4, 4, + dev_ctx->temp_cmd, size, false); + + header = dev_ctx->temp_cmd[0]; + + /* Check the message is valid according to tags */ + if (MESSAGE_TAG(header) == mu_priv->cmd_tag) { + /* + * unlocked in seco_mu_receive_work_handler when the + * response to this command is received. + */ + mutex_lock(&mu_priv->mu_cmd_lock); + mu_priv->waiting_rsp_dev = dev_ctx; + } else if (MESSAGE_TAG(header) == mu_priv->rsp_tag) { + /* Check the device context can send the command */ + if (dev_ctx != mu_priv->cmd_receiver_dev) { + devctx_err(dev_ctx, + "This channel is not configured to send response to SECO\n"); + err = -EPERM; + goto exit; + } + } else { + devctx_err(dev_ctx, "The message does not have a valid TAG\n"); + err = -EINVAL; + goto exit; + } + + /* + * Check that the size passed as argument matches the size + * carried in the message. + */ + nb_words = MESSAGE_SIZE(header); + if (nb_words * sizeof(u32) > size) { + devctx_err(dev_ctx, "User buffer too small\n"); + goto exit; + } + + mutex_lock(&mu_priv->mu_lock); + + /* Send message */ + devctx_dbg(dev_ctx, "sending message\n"); + err = mbox_send_message(mu_priv->tx_chan, dev_ctx->temp_cmd); + if (err < 0) { + devctx_err(dev_ctx, "Failed to send message\n"); + goto unlock; + } + + err = nb_words * (u32)sizeof(u32); + +unlock: + mutex_unlock(&mu_priv->mu_lock); + +exit: + up(&dev_ctx->fops_lock); + return err; +} + +/* + * Read a message from the MU. + * Blocking until a message is available. + */ +static ssize_t seco_mu_fops_read(struct file *fp, char __user *buf, + size_t size, loff_t *ppos) +{ + struct seco_mu_device_ctx *dev_ctx = container_of(fp->private_data, + struct seco_mu_device_ctx, miscdev); + u32 data_size = 0, size_to_copy = 0; + struct seco_out_buffer_desc *b_desc; + int err; + + devctx_dbg(dev_ctx, "read to buf %p(%ld), ppos=%lld\n", buf, size, + ((ppos) ? *ppos : 0)); + + if (down_interruptible(&dev_ctx->fops_lock)) + return -EBUSY; + + if (dev_ctx->status != MU_OPENED) { + err = -EINVAL; + goto exit; + } + + /* Wait until the complete message is received on the MU. */ + err = wait_event_interruptible(dev_ctx->wq, dev_ctx->pending_hdr != 0); + if (err) { + devctx_err(dev_ctx, "Interrupted by signal\n"); + goto exit; + } + + devctx_dbg(dev_ctx, "%s %s\n", __func__, + "message received, start transmit to user"); + + /* Check that the size passed as argument is larger than + * the one carried in the message. + */ + data_size = dev_ctx->temp_resp_size * sizeof(u32); + size_to_copy = data_size; + if (size_to_copy > size) { + devctx_dbg(dev_ctx, "User buffer too small (%ld < %d)\n", + size, size_to_copy); + size_to_copy = size; + } + + /* We may need to copy the output data to user before + * delivering the completion message. + */ + while (!list_empty(&dev_ctx->pending_out)) { + b_desc = list_first_entry_or_null(&dev_ctx->pending_out, + struct seco_out_buffer_desc, + link); + if (b_desc->out_usr_ptr && b_desc->out_ptr) { + devctx_dbg(dev_ctx, "Copy output data to user\n"); + err = (int)copy_to_user(b_desc->out_usr_ptr, + b_desc->out_ptr, + b_desc->out_size); + if (err) { + devctx_err(dev_ctx, + "Failed to copy output data to user\n"); + err = -EFAULT; + goto exit; + } + } + __list_del_entry(&b_desc->link); + devm_kfree(dev_ctx->dev, b_desc); + } + + /* Copy data from the buffer */ + print_hex_dump_debug("to user ", DUMP_PREFIX_OFFSET, 4, 4, + dev_ctx->temp_resp, size_to_copy, false); + err = (int)copy_to_user(buf, dev_ctx->temp_resp, size_to_copy); + if (err) { + devctx_err(dev_ctx, "Failed to copy to user\n"); + err = -EFAULT; + goto exit; + } + + err = size_to_copy; + + /* free memory allocated on the shared buffers. */ + dev_ctx->secure_mem.pos = 0; + dev_ctx->non_secure_mem.pos = 0; + + dev_ctx->pending_hdr = 0; + +exit: + up(&dev_ctx->fops_lock); + return err; +} + +/* Configure the shared memory according to user config */ +static int +seco_mu_ioctl_shared_mem_cfg_handler(struct seco_mu_device_ctx *dev_ctx, + unsigned long arg) +{ + struct seco_mu_ioctl_shared_mem_cfg cfg; + int err = -EINVAL; + u64 high_boundary; + + /* Check if not already configured. */ + if (dev_ctx->secure_mem.dma_addr != 0u) { + devctx_err(dev_ctx, "Shared memory not configured\n"); + goto exit; + } + + err = (int)copy_from_user(&cfg, (u8 *)arg, + sizeof(cfg)); + if (err) { + devctx_err(dev_ctx, "Fail copy shared memory config to user\n"); + err = -EFAULT; + goto exit; + } + + devctx_dbg(dev_ctx, "cfg offset: %u(%d)\n", cfg.base_offset, cfg.size); + + high_boundary = cfg.base_offset; + if (high_boundary > SECURE_RAM_SIZE) { + devctx_err(dev_ctx, "base offset is over secure memory\n"); + err = -ENOMEM; + goto exit; + } + + high_boundary += cfg.size; + if (high_boundary > SECURE_RAM_SIZE) { + devctx_err(dev_ctx, "total memory is over secure memory\n"); + err = -ENOMEM; + goto exit; + } + + dev_ctx->secure_mem.dma_addr = (dma_addr_t)cfg.base_offset; + dev_ctx->secure_mem.size = cfg.size; + dev_ctx->secure_mem.pos = 0; + dev_ctx->secure_mem.ptr = devm_ioremap(dev_ctx->dev, + (phys_addr_t)(SECURE_RAM_BASE_ADDRESS + + (u64)dev_ctx->secure_mem.dma_addr), + dev_ctx->secure_mem.size); + if (!dev_ctx->secure_mem.ptr) { + devctx_err(dev_ctx, "Failed to map secure memory\n"); + err = -ENOMEM; + goto exit; + } + +exit: + return err; +} + +/* + * Copy a buffer of daa to/from the user and return the address to use in + * messages + */ +static int seco_mu_ioctl_setup_iobuf_handler(struct seco_mu_device_ctx *dev_ctx, + unsigned long arg) +{ + struct seco_out_buffer_desc *out_buf_desc; + struct seco_mu_ioctl_setup_iobuf io; + struct seco_shared_mem *shared_mem; + int err = -EINVAL; + u32 pos; + + err = (int)copy_from_user(&io, + (u8 *)arg, + sizeof(io)); + if (err) { + devctx_err(dev_ctx, "Failed copy iobuf config from user\n"); + err = -EFAULT; + goto exit; + } + + devctx_dbg(dev_ctx, "io [buf: %p(%d) flag: %x]\n", + io.user_buf, io.length, io.flags); + + if (io.length == 0 || !io.user_buf) { + /* + * Accept NULL pointers since some buffers are optional + * in SECO commands. In this case we should return 0 as + * pointer to be embedded into the message. + * Skip all data copy part of code below. + */ + io.seco_addr = 0; + goto copy; + } + + /* Select the shared memory to be used for this buffer. */ + if (io.flags & SECO_MU_IO_FLAGS_USE_SEC_MEM) { + /* App requires to use secure memory for this buffer.*/ + shared_mem = &dev_ctx->secure_mem; + } else { + /* No specific requirement for this buffer. */ + shared_mem = &dev_ctx->non_secure_mem; + } + + /* Check there is enough space in the shared memory. */ + if (io.length >= shared_mem->size - shared_mem->pos) { + devctx_err(dev_ctx, "Not enough space in shared memory\n"); + err = -ENOMEM; + goto exit; + } + + /* Allocate space in shared memory. 8 bytes aligned. */ + pos = shared_mem->pos; + shared_mem->pos += round_up(io.length, 8u); + io.seco_addr = (u64)shared_mem->dma_addr + pos; + + if ((io.flags & SECO_MU_IO_FLAGS_USE_SEC_MEM) && + !(io.flags & SECO_MU_IO_FLAGS_USE_SHORT_ADDR)) + /*Add base address to get full address.*/ + io.seco_addr += SECURE_RAM_BASE_ADDRESS_SCU; + + if (io.flags & SECO_MU_IO_FLAGS_IS_INPUT) { + /* + * buffer is input: + * copy data from user space to this allocated buffer. + */ + err = (int)copy_from_user(shared_mem->ptr + pos, io.user_buf, + io.length); + if (err) { + devctx_err(dev_ctx, + "Failed copy data to shared memory\n"); + err = -EFAULT; + goto exit; + } + } else { + /* + * buffer is output: + * add an entry in the "pending buffers" list so data + * can be copied to user space when receiving SECO + * response. + */ + out_buf_desc = devm_kmalloc(dev_ctx->dev, sizeof(*out_buf_desc), + GFP_KERNEL); + if (!out_buf_desc) { + err = -ENOMEM; + devctx_err(dev_ctx, + "Failed allocating mem for pending buffer\n" + ); + goto exit; + } + + out_buf_desc->out_ptr = shared_mem->ptr + pos; + out_buf_desc->out_usr_ptr = io.user_buf; + out_buf_desc->out_size = io.length; + list_add_tail(&out_buf_desc->link, &dev_ctx->pending_out); + } + +copy: + /* Provide the seco address to user space only if success. */ + err = (int)copy_to_user((u8 *)arg, &io, + sizeof(io)); + if (err) { + devctx_err(dev_ctx, "Failed to copy iobuff setup to user\n"); + err = -EFAULT; + goto exit; + } + +exit: + return err; +} + +/* Retrieve info about the MU */ +static int seco_mu_ioctl_get_mu_info_handler(struct seco_mu_device_ctx *dev_ctx, + unsigned long arg) +{ + struct seco_mu_priv *priv = dev_get_drvdata(dev_ctx->dev); + struct seco_mu_ioctl_get_mu_info info; + int err = -EINVAL; + + info.seco_mu_idx = (u8)priv->seco_mu_id; + info.interrupt_idx = SECO_MU_INTERRUPT_INDEX; + info.tz = SECO_DEFAULT_TZ; + + err = imx_sc_rm_get_did(priv->ipc_scu, &info.did); + if (err) { + devctx_err(dev_ctx, "Get did failed\n"); + goto exit; + } + + devctx_dbg(dev_ctx, + "info [mu_idx: %d, irq_idx: %d, tz: 0x%x, did: 0x%x]\n", + info.seco_mu_idx, info.interrupt_idx, info.tz, info.did); + + err = (int)copy_to_user((u8 *)arg, &info, + sizeof(info)); + if (err) { + devctx_err(dev_ctx, "Failed to copy mu info to user\n"); + err = -EFAULT; + goto exit; + } + +exit: + return err; +} + +static int seco_mu_ioctl_signed_msg_handler(struct seco_mu_device_ctx *dev_ctx, + unsigned long arg) +{ + struct seco_shared_mem *shared_mem = &dev_ctx->non_secure_mem; + struct seco_mu_priv *priv = dev_get_drvdata(dev_ctx->dev); + struct seco_mu_ioctl_signed_message msg; + int err = -EINVAL; + u64 addr; + u32 pos; + + err = (int)copy_from_user(&msg, + (u8 *)arg, + sizeof(msg)); + if (err) { + devctx_err(dev_ctx, "Failed to copy from user: %d\n", err); + err = -EFAULT; + goto exit; + } + + /* Check there is enough space in the shared memory. */ + if (msg.msg_size >= shared_mem->size - shared_mem->pos) { + devctx_err(dev_ctx, "Not enough mem: %d left, %d required\n", + shared_mem->size - shared_mem->pos, msg.msg_size); + err = -ENOMEM; + goto exit; + } + + /* Allocate space in shared memory. 8 bytes aligned. */ + pos = shared_mem->pos; + + /* get physical address from the pos */ + addr = (u64)shared_mem->dma_addr + pos; + + /* copy signed message from user space to this allocated buffer */ + err = (int)copy_from_user(shared_mem->ptr + pos, msg.message, + msg.msg_size); + if (err) { + devctx_err(dev_ctx, "Failed to signed message from user: %d\n", + err); + err = -EFAULT; + goto exit; + } + + /* Send the message to SECO through SCU */ + msg.error_code = imx_sc_seco_sab_msg(priv->ipc_scu, addr); + + err = (int)copy_to_user((u8 *)arg, &msg, + sizeof(msg)); + if (err) { + devctx_err(dev_ctx, "Failed to copy to user: %d\n", err); + err = -EFAULT; + goto exit; + } + +exit: + return err; +} + +/* IOCTL entry point of a char device */ +static long seco_mu_ioctl(struct file *fp, unsigned int cmd, unsigned long arg) +{ + struct seco_mu_device_ctx *dev_ctx = container_of(fp->private_data, + struct seco_mu_device_ctx, miscdev); + struct seco_mu_priv *mu_priv = dev_ctx->mu_priv; + int err = -EINVAL; + + /* Prevent race during change of device context */ + if (down_interruptible(&dev_ctx->fops_lock)) + return -EBUSY; + + switch (cmd) { + case SECO_MU_IOCTL_ENABLE_CMD_RCV: + if (!mu_priv->cmd_receiver_dev) { + devctx_dbg(dev_ctx, "setting as receiver\n"); + mu_priv->cmd_receiver_dev = dev_ctx; + err = 0; + }; + break; + case SECO_MU_IOCTL_SHARED_BUF_CFG: + err = seco_mu_ioctl_shared_mem_cfg_handler(dev_ctx, arg); + break; + case SECO_MU_IOCTL_SETUP_IOBUF: + err = seco_mu_ioctl_setup_iobuf_handler(dev_ctx, arg); + break; + case SECO_MU_IOCTL_GET_MU_INFO: + err = seco_mu_ioctl_get_mu_info_handler(dev_ctx, arg); + break; + case SECO_MU_IOCTL_SIGNED_MESSAGE: + err = seco_mu_ioctl_signed_msg_handler(dev_ctx, arg); + break; + default: + err = -EINVAL; + devctx_dbg(dev_ctx, "IOCTL %.8x not supported\n", cmd); + } + + up(&dev_ctx->fops_lock); + return (long)err; +} + +/* + * Callback called by mailbox FW when data are received + */ +static void seco_mu_rx_callback(struct mbox_client *c, void *msg) +{ + struct device *dev = c->dev; + struct seco_mu_priv *priv = dev_get_drvdata(dev); + struct seco_mu_device_ctx *dev_ctx; + bool is_response = false; + int msg_size; + u32 header; + + dev_dbg(dev, "Message received on mailbox\n"); + + /* The function can be called with NULL msg */ + if (!msg) { + dev_err(dev, "Message is invalid\n"); + return; + } + + if (IS_ERR(msg)) { + dev_err(dev, "Error during reception of message: %ld\n", + PTR_ERR(msg)); + return; + } + + header = *(u32 *)msg; + + dev_dbg(dev, "Selecting device\n"); + + /* Incoming command: wake up the receiver if any. */ + if (MESSAGE_TAG(header) == priv->cmd_tag) { + dev_dbg(dev, "Selecting cmd receiver\n"); + dev_ctx = priv->cmd_receiver_dev; + } else if (MESSAGE_TAG(header) == priv->rsp_tag) { + dev_dbg(dev, "Selecting rsp waiter\n"); + dev_ctx = priv->waiting_rsp_dev; + is_response = true; + } else { + dev_err(dev, "Failed to select a device for message: %.8x\n", + header); + return; + } + + if (!dev_ctx) { + dev_err(dev, "No device context selected for message: %.8x\n", + header); + return; + } + + /* Init reception */ + msg_size = MESSAGE_SIZE(header); + if (msg_size > MAX_RECV_SIZE) { + devctx_err(dev_ctx, "Message is too big (%d > %d)", msg_size, + MAX_RECV_SIZE); + return; + } + + memcpy(dev_ctx->temp_resp, msg, msg_size * sizeof(u32)); + dev_ctx->temp_resp_size = msg_size; + + /* Allow user to read */ + dev_ctx->pending_hdr = dev_ctx->temp_resp[0]; + wake_up_interruptible(&dev_ctx->wq); + + if (is_response) { + /* Allow user to send new command */ + mutex_unlock(&priv->mu_cmd_lock); + } +} + +#define SECO_FW_VER_FEAT_MASK (0x0000FFF0u) +#define SECO_FW_VER_FEAT_SHIFT (0x04u) +#define SECO_FW_VER_FEAT_MIN_ALL_MU (0x04u) + +/* + * Get SECO FW version and check if it supports receiving commands on all MUs + * The version is retrieved through SCU since this is the only communication + * channel to SECO always present. + */ +static int seco_mu_check_all_mu_supported(struct device *dev) +{ + struct seco_mu_priv *priv = dev_get_drvdata(dev); + u32 seco_ver; + int ret; + + ret = imx_sc_seco_build_info(priv->ipc_scu, &seco_ver, NULL); + if (ret) { + dev_err(dev, "failed to retrieve SECO build info\n"); + goto exit; + } + + if (((seco_ver & SECO_FW_VER_FEAT_MASK) >> SECO_FW_VER_FEAT_SHIFT) + < SECO_FW_VER_FEAT_MIN_ALL_MU) { + dev_err(dev, "current SECO FW do not support MU with Linux\n"); + ret = -ENOTSUPP; + goto exit; + } + +exit: + return ret; +} + +/* Char driver setup */ +static const struct file_operations seco_mu_fops = { + .open = seco_mu_fops_open, + .owner = THIS_MODULE, + .read = seco_mu_fops_read, + .release = seco_mu_fops_close, + .write = seco_mu_fops_write, + .unlocked_ioctl = seco_mu_ioctl, +}; + +/* interface for managed res to free a mailbox channel */ +static void if_mbox_free_channel(void *mbox_chan) +{ + mbox_free_channel(mbox_chan); +} + +/* interface for managed res to unregister a char device */ +static void if_misc_deregister(void *miscdevice) +{ + misc_deregister(miscdevice); +} + +static int seco_mu_request_channel(struct device *dev, + struct mbox_chan **chan, + const char *name) +{ + struct seco_mu_priv *priv = dev_get_drvdata(dev); + struct mbox_chan *t_chan; + int ret = 0; + + t_chan = mbox_request_channel_byname(&priv->cl, name); + if (IS_ERR(t_chan)) { + ret = PTR_ERR(t_chan); + if (ret != -EPROBE_DEFER) + dev_err(dev, + "Failed to request chan %s ret %d\n", name, + ret); + goto exit; + } + + ret = devm_add_action(dev, if_mbox_free_channel, t_chan); + if (ret) { + dev_err(dev, "failed to add devm removal of mbox %s\n", name); + goto exit; + } + + *chan = t_chan; + +exit: + return ret; +} + +/* Driver probe.*/ +static int seco_mu_probe(struct platform_device *pdev) +{ + struct seco_mu_device_ctx *dev_ctx; + struct device *dev = &pdev->dev; + struct seco_mu_priv *priv; + struct device_node *np; + int max_nb_users = 0; + char *devname; + int ret; + int i; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) { + ret = -ENOMEM; + dev_err(dev, "Fail allocate mem for private data\n"); + goto exit; + } + priv->dev = dev; + dev_set_drvdata(dev, priv); + + /* + * Get the address of MU to be used for communication with the SCU + */ + np = pdev->dev.of_node; + if (!np) { + dev_err(dev, "Cannot find MU User entry in device tree\n"); + ret = -ENOTSUPP; + goto exit; + } + + ret = imx_scu_get_handle(&priv->ipc_scu); + if (ret) { + dev_err(dev, "Fail to retrieve IPC handle\n"); + goto exit; + } + + ret = imx_sc_rm_get_resource_owner(priv->ipc_scu, IMX_SC_R_SECO, + &priv->seco_part_owner); + if (ret) { + dev_err(dev, "Fail get owner of SECO resource\n"); + goto exit; + } + + ret = seco_mu_check_all_mu_supported(dev); + if (ret) { + dev_err(dev, "Fail seco_mu_check_all_mu_supported\n"); + goto exit; + } + + /* Initialize the mutex. */ + mutex_init(&priv->mu_cmd_lock); + mutex_init(&priv->mu_lock); + + priv->cmd_receiver_dev = NULL; + priv->waiting_rsp_dev = NULL; + + ret = of_property_read_u32(np, "fsl,seco_mu_id", &priv->seco_mu_id); + if (ret) { + dev_warn(dev, "%s: Not able to read mu_id", __func__); + priv->seco_mu_id = SECO_DEFAULT_MU_INDEX; + } + + ret = of_property_read_u32(np, "fsl,seco_max_users", &max_nb_users); + if (ret) { + dev_warn(dev, "%s: Not able to read mu_max_user", __func__); + max_nb_users = SECO_MU_DEFAULT_MAX_USERS; + } + + ret = of_property_read_u8(np, "fsl,cmd_tag", &priv->cmd_tag); + if (ret) + priv->cmd_tag = DEFAULT_MESSAGING_TAG_COMMAND; + + ret = of_property_read_u8(np, "fsl,rsp_tag", &priv->rsp_tag); + if (ret) + priv->rsp_tag = DEFAULT_MESSAGING_TAG_RESPONSE; + + /* Mailbox client configuration */ + priv->cl.dev = dev; + priv->cl.knows_txdone = true; + priv->cl.rx_callback = seco_mu_rx_callback; + + ret = seco_mu_request_channel(dev, &priv->tx_chan, "txdb"); + if (ret) { + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to request txdb channel\n"); + + goto exit; + } + + ret = seco_mu_request_channel(dev, &priv->rx_chan, "rxdb"); + if (ret) { + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to request rxdb channel\n"); + + goto exit; + } + + /* Create users */ + for (i = 0; i < max_nb_users; i++) { + dev_ctx = devm_kzalloc(dev, sizeof(*dev_ctx), GFP_KERNEL); + if (!dev_ctx) { + ret = -ENOMEM; + dev_err(dev, + "Fail to allocate memory for device context\n"); + goto exit; + } + + dev_ctx->dev = dev; + dev_ctx->status = MU_FREE; + dev_ctx->mu_priv = priv; + /* Default value invalid for an header. */ + init_waitqueue_head(&dev_ctx->wq); + + INIT_LIST_HEAD(&dev_ctx->pending_out); + sema_init(&dev_ctx->fops_lock, 1); + + devname = devm_kasprintf(dev, GFP_KERNEL, "seco_mu%d_ch%d", + priv->seco_mu_id, i); + if (!devname) { + ret = -ENOMEM; + dev_err(dev, + "Fail to allocate memory for misc dev name\n"); + goto exit; + } + + dev_ctx->miscdev.name = devname; + dev_ctx->miscdev.minor = MISC_DYNAMIC_MINOR; + dev_ctx->miscdev.fops = &seco_mu_fops; + dev_ctx->miscdev.parent = dev; + ret = misc_register(&dev_ctx->miscdev); + if (ret) { + dev_err(dev, "failed to register misc device %d\n", + ret); + goto exit; + } + + ret = devm_add_action(dev, if_misc_deregister, + &dev_ctx->miscdev); + if (ret) + dev_warn(dev, + "failed to add managed removal of miscdev\n"); + } + +exit: + return ret; +} + +static const struct of_device_id seco_mu_match[] = { + { + .compatible = "fsl,imx-seco-mu", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, seco_mu_match); + +static struct platform_driver seco_mu_driver = { + .driver = { + .name = "seco_mu", + .of_match_table = seco_mu_match, + }, + .probe = seco_mu_probe, +}; + +module_platform_driver(seco_mu_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("IMX Seco MU"); +MODULE_AUTHOR("NXP"); diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index f9263426af0309..b7176ce6f7e0e6 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -389,6 +389,13 @@ config GPIO_MXS select GPIO_GENERIC select GENERIC_IRQ_CHIP +config GPIO_MXC_PAD_WAKEUP + def_bool y + depends on IMX_SCU + select GPIO_MXC + help + Say Y here to enable the imx8 gpio pad wakeup + config GPIO_OCTEON tristate "Cavium OCTEON GPIO" depends on GPIOLIB && CAVIUM_OCTEON_SOC @@ -567,6 +574,18 @@ config GPIO_VF610 help Say yes here to support Vybrid vf610 GPIOs. +config GPIO_IMX_RPMSG + bool "NXP i.MX7ULP RPMSG GPIO support" + depends on ARCH_MXC && RPMSG && GPIOLIB + help + This driver support i.MX7ULP RPMSG virtual GPIOs. + +config GPIO_IMX_RPMSG + bool "NXP i.MX7ULP RPMSG GPIO support" + depends on ARCH_MXC && RPMSG && GPIOLIB + help + This driver support i.MX7ULP RPMSG virtual GPIOs. + config GPIO_VR41XX tristate "NEC VR4100 series General-purpose I/O Uint support" depends on CPU_VR41XX diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index d2fd19c15bae3f..30e93c76995d1c 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -151,6 +151,7 @@ obj-$(CONFIG_GPIO_TWL6040) += gpio-twl6040.o obj-$(CONFIG_GPIO_UCB1400) += gpio-ucb1400.o obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o obj-$(CONFIG_GPIO_VF610) += gpio-vf610.o +obj-$(CONFIG_GPIO_IMX_RPMSG) += gpio-imx-rpmsg.o obj-$(CONFIG_GPIO_VIPERBOARD) += gpio-viperboard.o obj-$(CONFIG_GPIO_VR41XX) += gpio-vr41xx.o obj-$(CONFIG_GPIO_VX855) += gpio-vx855.o diff --git a/drivers/gpio/gpio-74x164.c b/drivers/gpio/gpio-74x164.c index e81307f9754e38..c884fadce0e9df 100644 --- a/drivers/gpio/gpio-74x164.c +++ b/drivers/gpio/gpio-74x164.c @@ -142,6 +142,9 @@ static int gen_74x164_probe(struct spi_device *spi) chip->registers = nregs; chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers; + of_property_read_u8_array(spi->dev.of_node, "registers-default", + chip->buffer, chip->registers); + chip->gpio_chip.can_sleep = true; chip->gpio_chip.parent = &spi->dev; chip->gpio_chip.owner = THIS_MODULE; diff --git a/drivers/gpio/gpio-imx-rpmsg.c b/drivers/gpio/gpio-imx-rpmsg.c new file mode 100644 index 00000000000000..418455fe525070 --- /dev/null +++ b/drivers/gpio/gpio-imx-rpmsg.c @@ -0,0 +1,424 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IMX_RPMSG_GPIO_PER_PORT 32 +#define RPMSG_TIMEOUT 1000 + +enum gpio_input_trigger_type { + GPIO_RPMSG_TRI_IGNORE, + GPIO_RPMSG_TRI_RISING, + GPIO_RPMSG_TRI_FALLING, + GPIO_RPMSG_TRI_BOTH_EDGE, + GPIO_RPMSG_TRI_LOW_LEVEL, + GPIO_RPMSG_TRI_HIGH_LEVEL, +}; + +enum gpio_rpmsg_header_type { + GPIO_RPMSG_SETUP, + GPIO_RPMSG_REPLY, + GPIO_RPMSG_NOTIFY, +}; + +enum gpio_rpmsg_header_cmd { + GPIO_RPMSG_INPUT_INIT, + GPIO_RPMSG_OUTPUT_INIT, + GPIO_RPMSG_INPUT_GET, +}; + +struct gpio_rpmsg_data { + struct imx_rpmsg_head header; + u8 pin_idx; + u8 port_idx; + union { + u8 event; + u8 retcode; + u8 value; + } out; + union { + u8 wakeup; + u8 value; + } in; +} __packed __aligned(8); + +struct imx_rpmsg_gpio_port { + struct gpio_chip gc; + struct irq_chip chip; + struct irq_domain *domain; + struct gpio_rpmsg_data msg; + u32 irq_type[IMX_RPMSG_GPIO_PER_PORT]; + int idx; +}; + +struct imx_gpio_rpmsg_info { + struct rpmsg_device *rpdev; + struct gpio_rpmsg_data *notify_msg; + struct gpio_rpmsg_data *reply_msg; + struct pm_qos_request pm_qos_req; + struct completion cmd_complete; + struct mutex lock; +}; + +static struct imx_gpio_rpmsg_info gpio_rpmsg; + +static int gpio_send_message(struct imx_rpmsg_gpio_port *port, + struct gpio_rpmsg_data *msg, + struct imx_gpio_rpmsg_info *info, + bool sync) +{ + int err; + + if (!info->rpdev) { + dev_dbg(&info->rpdev->dev, + "rpmsg channel not ready, m4 image ready?\n"); + return -EINVAL; + } + + mutex_lock(&info->lock); + pm_qos_add_request(&info->pm_qos_req, + PM_QOS_CPU_DMA_LATENCY, 0); + + reinit_completion(&info->cmd_complete); + + err = rpmsg_send(info->rpdev->ept, (void *)msg, + sizeof(struct gpio_rpmsg_data)); + + if (err) { + dev_err(&info->rpdev->dev, "rpmsg_send failed: %d\n", err); + goto err_out; + } + + if (sync) { + err = wait_for_completion_timeout(&info->cmd_complete, + msecs_to_jiffies(RPMSG_TIMEOUT)); + if (!err) { + dev_err(&info->rpdev->dev, "rpmsg_send timeout!\n"); + err = -ETIMEDOUT; + goto err_out; + } + + if (info->reply_msg->out.retcode != 0) { + dev_err(&info->rpdev->dev, "rpmsg not ack %d!\n", + info->reply_msg->out.retcode); + err = -EINVAL; + goto err_out; + } + + /* copy the reply message */ + memcpy(&port->msg, info->reply_msg, sizeof(*info->reply_msg)); + + err = 0; + } + +err_out: + pm_qos_remove_request(&info->pm_qos_req); + mutex_unlock(&info->lock); + + return err; +} + +static int gpio_rpmsg_cb(struct rpmsg_device *rpdev, + void *data, int len, void *priv, u32 src) +{ + struct gpio_rpmsg_data *msg = (struct gpio_rpmsg_data *)data; + + if (msg->header.type == GPIO_RPMSG_REPLY) { + gpio_rpmsg.reply_msg = msg; + complete(&gpio_rpmsg.cmd_complete); + } else if (msg->header.type == GPIO_RPMSG_NOTIFY) { + gpio_rpmsg.notify_msg = msg; + /* TBD for interrupt handler */ + } else + dev_err(&gpio_rpmsg.rpdev->dev, "wrong command type!\n"); + + return 0; +} + +static int imx_rpmsg_gpio_get(struct gpio_chip *gc, unsigned int gpio) +{ + struct imx_rpmsg_gpio_port *port = gpiochip_get_data(gc); + struct gpio_rpmsg_data msg; + int ret; + + memset(&msg, 0, sizeof(struct gpio_rpmsg_data)); + msg.header.cate = IMX_RPMSG_GPIO; + msg.header.major = IMX_RMPSG_MAJOR; + msg.header.minor = IMX_RMPSG_MINOR; + msg.header.type = GPIO_RPMSG_SETUP; + msg.header.cmd = GPIO_RPMSG_INPUT_GET; + msg.pin_idx = gpio; + msg.port_idx = port->idx; + + ret = gpio_send_message(port, &msg, &gpio_rpmsg, true); + if (!ret) + return !!port->msg.in.value; + + return ret; +} + +static int imx_rpmsg_gpio_direction_input(struct gpio_chip *gc, + unsigned int gpio) +{ + struct imx_rpmsg_gpio_port *port = gpiochip_get_data(gc); + struct gpio_rpmsg_data msg; + + memset(&msg, 0, sizeof(struct gpio_rpmsg_data)); + msg.header.cate = IMX_RPMSG_GPIO; + msg.header.major = IMX_RMPSG_MAJOR; + msg.header.minor = IMX_RMPSG_MINOR; + msg.header.type = GPIO_RPMSG_SETUP; + msg.header.cmd = GPIO_RPMSG_INPUT_INIT; + msg.pin_idx = gpio; + msg.port_idx = port->idx; + + /* TBD: get event trigger and wakeup from GPIO descriptor */ + msg.out.event = GPIO_RPMSG_TRI_IGNORE; + msg.in.wakeup = 0; + + return gpio_send_message(port, &msg, &gpio_rpmsg, true); +} + +static inline void imx_rpmsg_gpio_direction_output_init(struct gpio_chip *gc, + unsigned int gpio, int val, struct gpio_rpmsg_data *msg) +{ + struct imx_rpmsg_gpio_port *port = gpiochip_get_data(gc); + + msg->header.cate = IMX_RPMSG_GPIO; + msg->header.major = IMX_RMPSG_MAJOR; + msg->header.minor = IMX_RMPSG_MINOR; + msg->header.type = GPIO_RPMSG_SETUP; + msg->header.cmd = GPIO_RPMSG_OUTPUT_INIT; + msg->pin_idx = gpio; + msg->port_idx = port->idx; + msg->out.value = val; +} + +static void imx_rpmsg_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) +{ + struct imx_rpmsg_gpio_port *port = gpiochip_get_data(gc); + struct gpio_rpmsg_data msg; + + memset(&msg, 0, sizeof(struct gpio_rpmsg_data)); + imx_rpmsg_gpio_direction_output_init(gc, gpio, val, &msg); + gpio_send_message(port, &msg, &gpio_rpmsg, true); +} + +static int imx_rpmsg_gpio_direction_output(struct gpio_chip *gc, + unsigned int gpio, int val) +{ + struct imx_rpmsg_gpio_port *port = gpiochip_get_data(gc); + struct gpio_rpmsg_data msg; + + memset(&msg, 0, sizeof(struct gpio_rpmsg_data)); + imx_rpmsg_gpio_direction_output_init(gc, gpio, val, &msg); + return gpio_send_message(port, &msg, &gpio_rpmsg, true); +} + +static int imx_rpmsg_irq_set_type(struct irq_data *d, u32 type) +{ + struct imx_rpmsg_gpio_port *port = irq_data_get_irq_chip_data(d); + u32 gpio_idx = d->hwirq; + int edge = 0; + int ret = 0; + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + edge = GPIO_RPMSG_TRI_RISING; + break; + case IRQ_TYPE_EDGE_FALLING: + edge = GPIO_RPMSG_TRI_FALLING; + break; + case IRQ_TYPE_EDGE_BOTH: + edge = GPIO_RPMSG_TRI_BOTH_EDGE; + break; + case IRQ_TYPE_LEVEL_LOW: + edge = GPIO_RPMSG_TRI_LOW_LEVEL; + break; + case IRQ_TYPE_LEVEL_HIGH: + edge = GPIO_RPMSG_TRI_HIGH_LEVEL; + break; + default: + ret = -EINVAL; + break; + } + + port->irq_type[gpio_idx] = edge; + return ret; +} + +static int imx_rpmsg_irq_set_wake(struct irq_data *d, u32 enable) +{ + struct imx_rpmsg_gpio_port *port = irq_data_get_irq_chip_data(d); + struct gpio_rpmsg_data msg; + u32 gpio_idx = d->hwirq; + + memset(&msg, 0, sizeof(struct gpio_rpmsg_data)); + msg.header.cate = IMX_RPMSG_GPIO; + msg.header.major = IMX_RMPSG_MAJOR; + msg.header.minor = IMX_RMPSG_MINOR; + msg.header.type = GPIO_RPMSG_SETUP; + msg.header.cmd = GPIO_RPMSG_INPUT_INIT; + msg.pin_idx = gpio_idx; + msg.port_idx = port->idx; + + /* set wakeup trigger source, + * if not set irq type, then use high level as trigger type + */ + msg.out.event = port->irq_type[gpio_idx]; + if (!msg.out.event) + msg.out.event = GPIO_RPMSG_TRI_HIGH_LEVEL; + + msg.in.wakeup = enable; + + /* here should be atomic context */ + gpio_send_message(port, &msg, &gpio_rpmsg, false); + + return 0; +} + +static void imx_rpmsg_unmask_irq(struct irq_data *d) +{ + /* No need to implement the callback */ +} + +static void imx_rpmsg_mask_irq(struct irq_data *d) +{ + /* No need to implement the callback */ +} + +static struct irq_chip imx_rpmsg_irq_chip = { + .irq_mask = imx_rpmsg_mask_irq, + .irq_unmask = imx_rpmsg_unmask_irq, + .irq_set_wake = imx_rpmsg_irq_set_wake, + .irq_set_type = imx_rpmsg_irq_set_type, +}; + +static int imx_rpmsg_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct imx_rpmsg_gpio_port *port; + struct gpio_chip *gc; + int i, irq_base; + int ret; + + port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); + if (!port) + return -ENOMEM; + + ret = of_property_read_u32(np, "port_idx", &port->idx); + if (ret) + return ret; + + gc = &port->gc; + gc->of_node = np; + gc->parent = dev; + gc->label = "imx-rpmsg-gpio"; + gc->ngpio = IMX_RPMSG_GPIO_PER_PORT; + gc->base = of_alias_get_id(np, "gpio") * IMX_RPMSG_GPIO_PER_PORT; + + gc->direction_input = imx_rpmsg_gpio_direction_input; + gc->direction_output = imx_rpmsg_gpio_direction_output; + gc->get = imx_rpmsg_gpio_get; + gc->set = imx_rpmsg_gpio_set; + + platform_set_drvdata(pdev, port); + + ret = devm_gpiochip_add_data(dev, gc, port); + if (ret < 0) + return ret; + + /* generate one new irq domain */ + port->chip = imx_rpmsg_irq_chip; + port->chip.name = kasprintf(GFP_KERNEL, "rpmsg-irq-port-%d", port->idx); + port->chip.parent_device = NULL; + + irq_base = irq_alloc_descs(-1, 0, IMX_RPMSG_GPIO_PER_PORT, + numa_node_id()); + WARN_ON(irq_base < 0); + + port->domain = irq_domain_add_legacy(np, IMX_RPMSG_GPIO_PER_PORT, + irq_base, 0, + &irq_domain_simple_ops, port); + WARN_ON(!port->domain); + for (i = irq_base; i < irq_base + IMX_RPMSG_GPIO_PER_PORT; i++) { + irq_set_chip_and_handler(i, &port->chip, handle_level_irq); + irq_set_chip_data(i, port); + irq_clear_status_flags(i, IRQ_NOREQUEST); + irq_set_probe(i); + } + + return 0; +} +static const struct of_device_id imx_rpmsg_gpio_dt_ids[] = { + { .compatible = "fsl,imx-rpmsg-gpio" }, + { /* sentinel */ } +}; + +static struct platform_driver imx_rpmsg_gpio_driver = { + .driver = { + .name = "gpio-imx-rpmsg", + .of_match_table = imx_rpmsg_gpio_dt_ids, + }, + .probe = imx_rpmsg_gpio_probe, +}; + +static int gpio_rpmsg_probe(struct rpmsg_device *rpdev) +{ + gpio_rpmsg.rpdev = rpdev; + dev_info(&rpdev->dev, "new channel: 0x%x -> 0x%x!\n", + rpdev->src, rpdev->dst); + + init_completion(&gpio_rpmsg.cmd_complete); + mutex_init(&gpio_rpmsg.lock); + + return platform_driver_register(&imx_rpmsg_gpio_driver); +} + +static struct rpmsg_device_id gpio_rpmsg_id_table[] = { + { .name = "rpmsg-io-channel" }, + {}, +}; + +static struct rpmsg_driver gpio_rpmsg_driver = { + .drv.name = "gpio_rpmsg", + .drv.owner = THIS_MODULE, + .id_table = gpio_rpmsg_id_table, + .probe = gpio_rpmsg_probe, + .callback = gpio_rpmsg_cb, +}; + + +static int __init gpio_imx_rpmsg_init(void) +{ + return register_rpmsg_driver(&gpio_rpmsg_driver); +} +device_initcall(gpio_imx_rpmsg_init); + +MODULE_AUTHOR("NXP Semiconductor"); +MODULE_DESCRIPTION("NXP i.MX7ULP rpmsg gpio driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/gpio/gpio-max732x.c b/drivers/gpio/gpio-max732x.c index 5fb0bcf311421d..3c72ae0bcec984 100644 --- a/drivers/gpio/gpio-max732x.c +++ b/drivers/gpio/gpio-max732x.c @@ -19,6 +19,7 @@ #include #include #include +#include /* @@ -76,6 +77,12 @@ #define INT_CAPS(x) (((uint64_t)(x)) << 32) +enum { + OUTPUT_MASK, + OUTPUT_VAL, + OUTPUT_NUM, +}; + enum { MAX7319, MAX7320, @@ -622,6 +629,8 @@ static int max732x_probe(struct i2c_client *client, struct i2c_client *c; uint16_t addr_a, addr_b; int ret, nr_port; + u16 out_set[OUTPUT_NUM]; + unsigned long mask, val; pdata = dev_get_platdata(&client->dev); node = client->dev.of_node; @@ -639,6 +648,10 @@ static int max732x_probe(struct i2c_client *client, return -ENOMEM; chip->client = client; + ret = device_reset(&client->dev); + if (ret == -EPROBE_DEFER) + return ret; + nr_port = max732x_setup_gpio(chip, id, pdata->gpio_base); chip->gpio_chip.parent = &client->dev; @@ -711,6 +724,15 @@ static int max732x_probe(struct i2c_client *client, } i2c_set_clientdata(client, chip); + + /* set the output IO default voltage */ + if (!of_property_read_u16_array(node, "out-default", out_set, + ARRAY_SIZE(out_set))) { + mask = out_set[OUTPUT_MASK] & chip->dir_output; + val = out_set[OUTPUT_VAL]; + max732x_gpio_set_multiple(&chip->gpio_chip, &mask, &val); + } + return 0; } diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c index d72a3a5507b012..604dfec353a157 100644 --- a/drivers/gpio/gpio-mpc8xxx.c +++ b/drivers/gpio/gpio-mpc8xxx.c @@ -22,6 +22,7 @@ #include #include #include +#include #define MPC8XXX_GPIO_PINS 32 @@ -127,20 +128,19 @@ static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset) return -ENXIO; } -static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc) +static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data) { - struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc); - struct irq_chip *chip = irq_desc_get_chip(desc); + struct mpc8xxx_gpio_chip *mpc8xxx_gc = data; struct gpio_chip *gc = &mpc8xxx_gc->gc; - unsigned int mask; + unsigned long mask; + int i; mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER) & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR); - if (mask) - generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, - 32 - ffs(mask))); - if (chip->irq_eoi) - chip->irq_eoi(&desc->irq_data); + for_each_set_bit(i, &mask, 32) + generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 31 - i)); + + return IRQ_HANDLED; } static void mpc8xxx_irq_unmask(struct irq_data *d) @@ -296,6 +296,7 @@ static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = { static const struct mpc8xxx_gpio_devtype ls1028a_gpio_devtype = { .gpio_dir_in_init = ls1028a_gpio_dir_in_init, + .irq_set_type = mpc8xxx_irq_set_type, }; static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = { @@ -414,8 +415,16 @@ static int mpc8xxx_probe(struct platform_device *pdev) if (devtype->gpio_dir_in_init) devtype->gpio_dir_in_init(gc); - irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, - mpc8xxx_gpio_irq_cascade, mpc8xxx_gc); + ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn, + mpc8xxx_gpio_irq_cascade, + IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade", + mpc8xxx_gc); + if (ret) { + dev_err(&pdev->dev, "%s: failed to devm_request_irq(%d), ret = %d\n", + np->full_name, mpc8xxx_gc->irqn, ret); + goto err; + } + return 0; err: iounmap(mpc8xxx_gc->regs); diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index c77d474185f315..8beb0bdb4b38bc 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -16,12 +16,21 @@ #include #include #include +#include #include #include #include #include #include #include +#ifdef CONFIG_GPIO_MXC_PAD_WAKEUP +#include + +#define IMX_SC_PAD_FUNC_GET_WAKEUP 9 +#define IMX_SC_PAD_FUNC_SET_WAKEUP 4 +#define IMX_SC_PAD_WAKEUP_OFF 0 +#define IMX_SC_IRQ_PAD (1 << 1) +#endif enum mxc_gpio_hwtype { IMX1_GPIO, /* runs on i.mx1 */ @@ -30,6 +39,33 @@ enum mxc_gpio_hwtype { IMX35_GPIO, /* runs on all other i.mx */ }; +#ifdef CONFIG_GPIO_MXC_PAD_WAKEUP +struct mxc_gpio_pad_wakeup { + u32 pin_id; + u32 type; + u32 line; +}; + +struct imx_sc_msg_gpio_get_pad_wakeup { + struct imx_sc_rpc_msg hdr; + union { + struct req_pad { + u16 pad; + } __packed req; + struct resp_wakeup { + u8 wakeup; + } resp; + } data; +} __packed; + +struct imx_sc_msg_gpio_set_pad_wakeup { + struct imx_sc_rpc_msg hdr; + u16 pad; + u8 wakeup; +} __packed; + +#endif + /* device type dependent stuff */ struct mxc_gpio_hwdata { unsigned dr_reg; @@ -67,8 +103,17 @@ struct mxc_gpio_port { u32 both_edges; struct mxc_gpio_reg_saved gpio_saved_reg; bool power_off; + bool gpio_ranges; +#ifdef CONFIG_GPIO_MXC_PAD_WAKEUP + u32 pad_wakeup_num; + struct mxc_gpio_pad_wakeup pad_wakeup[32]; +#endif }; +#ifdef CONFIG_GPIO_MXC_PAD_WAKEUP +static struct imx_sc_ipc *gpio_ipc_handle; +#endif + static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = { .dr_reg = 0x1c, .gdir_reg = 0x00, @@ -310,6 +355,85 @@ static void mx2_gpio_irq_handler(struct irq_desc *desc) chained_irq_exit(chip, desc); } +#ifdef CONFIG_GPIO_MXC_PAD_WAKEUP +static int mxc_gpio_get_pad_wakeup(struct mxc_gpio_port *port) +{ + struct imx_sc_msg_gpio_get_pad_wakeup msg; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + u8 wakeup_type; + int ret; + int i; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_PAD; + hdr->func = IMX_SC_PAD_FUNC_GET_WAKEUP; + hdr->size = 2; + + for (i = 0; i < port->pad_wakeup_num; i++) { + /* get original pad type */ + wakeup_type = port->pad_wakeup[i].type; + msg.data.req.pad = port->pad_wakeup[i].pin_id; + ret = imx_scu_call_rpc(gpio_ipc_handle, &msg, true); + if (ret) { + dev_err(port->gc.parent, "get pad wakeup failed, ret %d\n", ret); + return ret; + } + wakeup_type = msg.data.resp.wakeup; + /* return wakeup gpio pin's line */ + if (wakeup_type != port->pad_wakeup[i].type) + return port->pad_wakeup[i].line; + } + + return -EINVAL; +} + +static void mxc_gpio_set_pad_wakeup(struct mxc_gpio_port *port, bool enable) +{ + struct imx_sc_msg_gpio_set_pad_wakeup msg; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + int ret; + int i; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_PAD; + hdr->func = IMX_SC_PAD_FUNC_SET_WAKEUP; + hdr->size = 2; + + for (i = 0; i < port->pad_wakeup_num; i++) { + msg.pad = port->pad_wakeup[i].pin_id; + msg.wakeup = enable ? port->pad_wakeup[i].type : IMX_SC_PAD_WAKEUP_OFF; + ret = imx_scu_call_rpc(gpio_ipc_handle, &msg, true); + if (ret) { + dev_err(port->gc.parent, "set pad wakeup failed, ret %d\n", ret); + return; + } + } +} + +static void mxc_gpio_handle_pad_wakeup(struct mxc_gpio_port *port, int line) +{ + struct irq_desc *desc = irq_to_desc(port->irq); + struct irq_chip *chip = irq_desc_get_chip(desc); + u32 irq_stat; + + /* skip invalid line */ + if (line > 31) { + dev_err(port->gc.parent, "invalid wakeup line %d\n", line); + return; + } + + dev_info(port->gc.parent, "wakeup by pad, line %d\n", line); + + chained_irq_enter(chip, desc); + + irq_stat = (1 << line); + + mxc_gpio_irq_handler(port, irq_stat); + + chained_irq_exit(chip, desc); +} +#endif + /* * Set interrupt number "irq" in the GPIO as a wake-up source. * While system is running, all registered GPIO interrupts need to have @@ -341,7 +465,32 @@ static int gpio_set_wake_irq(struct irq_data *d, u32 enable) return ret; } -static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base) +static int mxc_gpio_irq_reqres(struct irq_data *d) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct mxc_gpio_port *port = gc->private; + + if (gpiochip_lock_as_irq(&port->gc, d->hwirq)) { + dev_err(port->gc.parent, + "unable to lock HW IRQ %lu for IRQ\n", + d->hwirq); + return -EINVAL; + } + + return irq_chip_pm_get(d); +} + +static void mxc_gpio_irq_relres(struct irq_data *d) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct mxc_gpio_port *port = gc->private; + + gpiochip_unlock_as_irq(&port->gc, d->hwirq); + irq_chip_pm_put(d); +} + +static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base, + struct device *dev) { struct irq_chip_generic *gc; struct irq_chip_type *ct; @@ -354,11 +503,14 @@ static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base) gc->private = port; ct = gc->chip_types; + ct->chip.parent_device = dev; ct->chip.irq_ack = irq_gc_ack_set_bit; ct->chip.irq_mask = irq_gc_mask_clr_bit; ct->chip.irq_unmask = irq_gc_mask_set_bit; ct->chip.irq_set_type = gpio_set_irq_type; ct->chip.irq_set_wake = gpio_set_wake_irq; + ct->chip.irq_request_resources = mxc_gpio_irq_reqres; + ct->chip.irq_release_resources = mxc_gpio_irq_relres, ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND; ct->regs.ack = GPIO_ISR; ct->regs.mask = GPIO_IMR; @@ -407,13 +559,40 @@ static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset) return irq_find_mapping(port->domain, offset); } +static int mxc_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + struct mxc_gpio_port *port = gpiochip_get_data(chip); + int ret; + + if (port->gpio_ranges) { + ret = gpiochip_generic_request(chip, offset); + if (ret) + return ret; + } + + ret = pm_runtime_get_sync(chip->parent); + return ret < 0 ? ret : 0; +} + +static void mxc_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + struct mxc_gpio_port *port = gpiochip_get_data(chip); + + if (port->gpio_ranges) + gpiochip_generic_free(chip, offset); + pm_runtime_put(chip->parent); +} + static int mxc_gpio_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; struct mxc_gpio_port *port; int irq_count; - int irq_base; + int irq_base = 0; int err; +#ifdef CONFIG_GPIO_MXC_PAD_WAKEUP + int i; +#endif mxc_gpio_get_hw(pdev); @@ -452,9 +631,44 @@ static int mxc_gpio_probe(struct platform_device *pdev) return err; } +#ifdef CONFIG_GPIO_MXC_PAD_WAKEUP + /* + * parse pad wakeup info from dtb, each pad has to provide + * , these info should be put in each + * gpio node and with a "pad-wakeup-num" to indicate the + * total lines are with pad wakeup enabled. + */ + if (!of_property_read_u32(np, "pad-wakeup-num", &port->pad_wakeup_num)) { + if (port->pad_wakeup_num != 0) { + if (!gpio_ipc_handle) { + err = imx_scu_get_handle(&gpio_ipc_handle); + if (err) + return err; + } + for (i = 0; i < port->pad_wakeup_num; i++) { + of_property_read_u32_index(np, "pad-wakeup", + i * 3 + 0, &port->pad_wakeup[i].pin_id); + of_property_read_u32_index(np, "pad-wakeup", + i * 3 + 1, &port->pad_wakeup[i].type); + of_property_read_u32_index(np, "pad-wakeup", + i * 3 + 2, &port->pad_wakeup[i].line); + } + err = imx_scu_irq_group_enable(IMX_SC_IRQ_GROUP_WAKE, IMX_SC_IRQ_PAD, true); + if (err) + dev_warn(&pdev->dev, "Enable irq failed, GPIO pad wakeup NOT supported\n"); + } + } +#endif + if (of_device_is_compatible(np, "fsl,imx7d-gpio")) port->power_off = true; + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + err = pm_runtime_get_sync(&pdev->dev); + if (err < 0) + goto out_pm_dis; + /* disable the interrupt and clear the status */ writel(0, port->base + GPIO_IMR); writel(~0, port->base + GPIO_ISR); @@ -490,6 +704,14 @@ static int mxc_gpio_probe(struct platform_device *pdev) port->gc.free = gpiochip_generic_free; } + if (of_property_read_bool(np, "gpio_ranges")) + port->gpio_ranges = true; + else + port->gpio_ranges = false; + + port->gc.request = mxc_gpio_request; + port->gc.free = mxc_gpio_free; + port->gc.parent = &pdev->dev; port->gc.to_irq = mxc_gpio_to_irq; port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 : pdev->id * 32; @@ -512,16 +734,20 @@ static int mxc_gpio_probe(struct platform_device *pdev) } /* gpio-mxc can be a generic irq chip */ - err = mxc_gpio_init_gc(port, irq_base); + err = mxc_gpio_init_gc(port, irq_base, &pdev->dev); if (err < 0) goto out_irqdomain_remove; list_add_tail(&port->node, &mxc_gpio_ports); platform_set_drvdata(pdev, port); + pm_runtime_put(&pdev->dev); return 0; +out_pm_dis: + pm_runtime_disable(&pdev->dev); + clk_disable_unprepare(port->clk); out_irqdomain_remove: irq_domain_remove(port->domain); out_bgio: @@ -556,12 +782,73 @@ static void mxc_gpio_restore_regs(struct mxc_gpio_port *port) writel(port->gpio_saved_reg.dr, port->base + GPIO_DR); } +static int __maybe_unused mxc_gpio_runtime_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct mxc_gpio_port *port = platform_get_drvdata(pdev); + + mxc_gpio_save_regs(port); + clk_disable_unprepare(port->clk); + + return 0; +} + +static int __maybe_unused mxc_gpio_runtime_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct mxc_gpio_port *port = platform_get_drvdata(pdev); + int ret; + + ret = clk_prepare_enable(port->clk); + if (ret) + return ret; + + mxc_gpio_restore_regs(port); + + return 0; +} + +static int __maybe_unused mxc_gpio_noirq_suspend(struct device *dev) +{ +#ifdef CONFIG_GPIO_MXC_PAD_WAKEUP + struct platform_device *pdev = to_platform_device(dev); + struct mxc_gpio_port *port = platform_get_drvdata(pdev); + + mxc_gpio_set_pad_wakeup(port, true); +#endif + return 0; +} + +static int __maybe_unused mxc_gpio_noirq_resume(struct device *dev) +{ +#ifdef CONFIG_GPIO_MXC_PAD_WAKEUP + struct platform_device *pdev = to_platform_device(dev); + struct mxc_gpio_port *port = platform_get_drvdata(pdev); + int wakeup_line = mxc_gpio_get_pad_wakeup(port); + + mxc_gpio_set_pad_wakeup(port, false); + + if (wakeup_line >= 0) + mxc_gpio_handle_pad_wakeup(port, wakeup_line); +#endif + return 0; +} + +static const struct dev_pm_ops mxc_gpio_dev_pm_ops = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mxc_gpio_noirq_suspend, mxc_gpio_noirq_resume) + SET_RUNTIME_PM_OPS(mxc_gpio_runtime_suspend, mxc_gpio_runtime_resume, NULL) +}; + static int mxc_gpio_syscore_suspend(void) { struct mxc_gpio_port *port; + int ret; /* walk through all ports */ list_for_each_entry(port, &mxc_gpio_ports, node) { + ret = clk_prepare_enable(port->clk); + if (ret) + return ret; mxc_gpio_save_regs(port); clk_disable_unprepare(port->clk); } @@ -582,6 +869,7 @@ static void mxc_gpio_syscore_resume(void) return; } mxc_gpio_restore_regs(port); + clk_disable_unprepare(port->clk); } } @@ -595,6 +883,7 @@ static struct platform_driver mxc_gpio_driver = { .name = "gpio-mxc", .of_match_table = mxc_gpio_dt_ids, .suppress_bind_attrs = true, + .pm = &mxc_gpio_dev_pm_ops, }, .probe = mxc_gpio_probe, .id_table = mxc_gpio_devtype, diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c index 9a24dce3c26283..effcafbc09bfbb 100644 --- a/drivers/gpio/gpio-pca953x.c +++ b/drivers/gpio/gpio-pca953x.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -1018,17 +1019,21 @@ static int pca953x_probe(struct i2c_client *client, chip->client = client; - reg = devm_regulator_get(&client->dev, "vcc"); + reg = devm_regulator_get_optional(&client->dev, "vcc"); if (IS_ERR(reg)) { ret = PTR_ERR(reg); - if (ret != -EPROBE_DEFER) - dev_err(&client->dev, "reg get err: %d\n", ret); - return ret; + if (ret == -EPROBE_DEFER) + return ret; + dev_dbg(&client->dev, "reg get err: %d\n", ret); + reg = NULL; } - ret = regulator_enable(reg); - if (ret) { - dev_err(&client->dev, "reg en err: %d\n", ret); - return ret; + + if (reg) { + ret = regulator_enable(reg); + if (ret) { + dev_err(&client->dev, "reg en err: %d\n", ret); + return ret; + } } chip->regulator = reg; @@ -1086,6 +1091,10 @@ static int pca953x_probe(struct i2c_client *client, lockdep_set_subclass(&chip->i2c_lock, i2c_adapter_depth(client->adapter)); + ret = device_reset(&client->dev); + if (ret == -EPROBE_DEFER) + return -EPROBE_DEFER; + /* initialize cached registers from their original values. * we can't share this chip with another i2c master. */ @@ -1118,7 +1127,8 @@ static int pca953x_probe(struct i2c_client *client, return 0; err_exit: - regulator_disable(chip->regulator); + if (chip->regulator) + regulator_disable(chip->regulator); return ret; } @@ -1137,7 +1147,8 @@ static int pca953x_remove(struct i2c_client *client) ret = 0; } - regulator_disable(chip->regulator); + if (chip->regulator) + regulator_disable(chip->regulator); return ret; } @@ -1198,7 +1209,8 @@ static int pca953x_suspend(struct device *dev) if (atomic_read(&chip->wakeup_path)) device_set_wakeup_path(dev); else - regulator_disable(chip->regulator); + if (chip->regulator) + regulator_disable(chip->regulator); return 0; } @@ -1208,15 +1220,20 @@ static int pca953x_resume(struct device *dev) struct pca953x_chip *chip = dev_get_drvdata(dev); int ret; + regcache_cache_only(chip->regmap, false); + if (!atomic_read(&chip->wakeup_path)) { - ret = regulator_enable(chip->regulator); - if (ret) { - dev_err(dev, "Failed to enable regulator: %d\n", ret); + if (chip->regulator) { + ret = regulator_enable(chip->regulator); + if (ret) { + dev_err(dev, "Failed to enable regulator: %d\n", ret); + return 0; + } + } else { return 0; } } - regcache_cache_only(chip->regmap, false); regcache_mark_dirty(chip->regmap); ret = pca953x_regcache_sync(dev); if (ret) diff --git a/drivers/gpu/Makefile b/drivers/gpu/Makefile index f17d01f076c796..a6ac74a9f4b1eb 100644 --- a/drivers/gpu/Makefile +++ b/drivers/gpu/Makefile @@ -3,5 +3,5 @@ # taken to initialize them in the correct order. Link order is the only way # to ensure this currently. obj-$(CONFIG_TEGRA_HOST1X) += host1x/ +obj-y += imx/ obj-y += drm/ vga/ -obj-$(CONFIG_IMX_IPUV3_CORE) += ipu-v3/ diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 82ff826b33ccd1..a6191f8d58fa51 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -98,7 +98,7 @@ obj-$(CONFIG_DRM_MSM) += msm/ obj-$(CONFIG_DRM_TEGRA) += tegra/ obj-$(CONFIG_DRM_STM) += stm/ obj-$(CONFIG_DRM_STI) += sti/ -obj-$(CONFIG_DRM_IMX) += imx/ +obj-y += imx/ obj-$(CONFIG_DRM_INGENIC) += ingenic/ obj-$(CONFIG_DRM_MEDIATEK) += mediatek/ obj-$(CONFIG_DRM_MESON) += meson/ diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c index 333b88a5efb076..8a76315aaa0fd3 100644 --- a/drivers/gpu/drm/arm/malidp_drv.c +++ b/drivers/gpu/drm/arm/malidp_drv.c @@ -817,6 +817,12 @@ static int malidp_bind(struct device *dev) malidp->core_id = version; + ret = of_property_read_u32(dev->of_node, + "arm,malidp-arqos-value", + &hwdev->arqos_value); + if (ret) + hwdev->arqos_value = 0x0; + /* set the number of lines used for output of RGB data */ ret = of_property_read_u8_array(dev->of_node, "arm,malidp-output-port-lines", diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_hw.c index bd8265f02e0b32..ca570b1354787a 100644 --- a/drivers/gpu/drm/arm/malidp_hw.c +++ b/drivers/gpu/drm/arm/malidp_hw.c @@ -379,6 +379,15 @@ static void malidp500_modeset(struct malidp_hw_device *hwdev, struct videomode * malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC); else malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC); + + /* + * Program the RQoS register to avoid high resolutions flicker + * issue on the LS1028A. + */ + if (hwdev->arqos_value) { + val = hwdev->arqos_value; + malidp_hw_setbits(hwdev, val, MALIDP500_RQOS_QUALITY); + } } int malidp_format_get_bpp(u32 fmt) diff --git a/drivers/gpu/drm/arm/malidp_hw.h b/drivers/gpu/drm/arm/malidp_hw.h index 968a65eed3717f..e4c36bc90bdab3 100644 --- a/drivers/gpu/drm/arm/malidp_hw.h +++ b/drivers/gpu/drm/arm/malidp_hw.h @@ -251,6 +251,9 @@ struct malidp_hw_device { /* size of memory used for rotating layers, up to two banks available */ u32 rotation_memory[2]; + + /* priority level of RQOS register used for driven the ARQOS signal */ + u32 arqos_value; }; static inline u32 malidp_hw_read(struct malidp_hw_device *hwdev, u32 reg) diff --git a/drivers/gpu/drm/arm/malidp_regs.h b/drivers/gpu/drm/arm/malidp_regs.h index 993031542fa12f..514c50dcb74ddd 100644 --- a/drivers/gpu/drm/arm/malidp_regs.h +++ b/drivers/gpu/drm/arm/malidp_regs.h @@ -210,6 +210,16 @@ #define MALIDP500_CONFIG_VALID 0x00f00 #define MALIDP500_CONFIG_ID 0x00fd4 +/* + * The quality of service (QoS) register on the DP500. RQOS register values + * are driven by the ARQOS signal, using AXI transacations, dependent on the + * FIFO input level. + * The RQOS register can also set QoS levels for: + * - RED_ARQOS @ A 4-bit signal value for close to underflow conditions + * - GREEN_ARQOS @ A 4-bit signal value for normal conditions + */ +#define MALIDP500_RQOS_QUALITY 0x00500 + /* register offsets and bits specific to DP550/DP650 */ #define MALIDP550_ADDR_SPACE_SIZE 0x10000 #define MALIDP550_DE_CONTROL 0x00010 diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 1cc9f502c1f277..8b2e5d97559087 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -45,6 +45,15 @@ config DRM_DUMB_VGA_DAC Support for non-programmable RGB to VGA DAC bridges, such as ADI ADV7123, TI THS8134 and THS8135 or passive resistor ladder DACs. +config DRM_FSL_IMX_LVDS_BRIDGE + tristate "Freescale i.MX LVDS display bridge" + depends on MFD_SYSCON + depends on OF + select DRM_PANEL_BRIDGE + help + Support Freescale i.MX parallel to LVDS Display Bridge (LDB). + This bridge is embedded in a SoC. + config DRM_LVDS_ENCODER tristate "Transparent parallel to LVDS encoder support" depends on OF @@ -65,6 +74,15 @@ config DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW to DP++. This is used with the i.MX6 imx-ldb driver. You are likely to say N here. +config DRM_SEC_MIPI_DSIM + tristate "Samsung MIPI DSIM Bridge" + depends on OF + select DRM_KMS_HELPER + select DRM_MIPI_DSI + select DRM_PANEL + help + The Samsung MPI DSIM Bridge driver. + config DRM_NXP_PTN3460 tristate "NXP PTN3460 DP/LVDS bridge" depends on OF @@ -154,6 +172,18 @@ source "drivers/gpu/drm/bridge/analogix/Kconfig" source "drivers/gpu/drm/bridge/adv7511/Kconfig" +source "drivers/gpu/drm/bridge/nwl-dsi/Kconfig" + +source "drivers/gpu/drm/bridge/cadence/Kconfig" + source "drivers/gpu/drm/bridge/synopsys/Kconfig" +config DRM_ITE_IT6263 + tristate "ITE IT6263 LVDS/HDMI bridge" + depends on OF + select DRM_KMS_HELPER + select REGMAP_I2C + ---help--- + ITE IT6263 bridge chip driver. + endmenu diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index 4934fcf5a6f82a..7c755b93a3c51d 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_DRM_ANALOGIX_ANX78XX) += analogix-anx78xx.o obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o obj-$(CONFIG_DRM_DUMB_VGA_DAC) += dumb-vga-dac.o +obj-$(CONFIG_DRM_FSL_IMX_LVDS_BRIDGE) += fsl-imx-ldb.o obj-$(CONFIG_DRM_LVDS_ENCODER) += lvds-encoder.o obj-$(CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW) += megachips-stdpxxxx-ge-b850v3-fw.o obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o @@ -16,4 +17,8 @@ obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/ obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/ obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o +obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi/ +obj-y += cadence/ obj-y += synopsys/ +obj-$(CONFIG_DRM_ITE_IT6263) += it6263.o +obj-$(CONFIG_DRM_SEC_MIPI_DSIM) += sec-dsim.o diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511.h b/drivers/gpu/drm/bridge/adv7511/adv7511.h index 52b2adfdc8773d..f1f6a7674d36f8 100644 --- a/drivers/gpu/drm/bridge/adv7511/adv7511.h +++ b/drivers/gpu/drm/bridge/adv7511/adv7511.h @@ -219,6 +219,9 @@ #define ADV7511_REG_CEC_SOFT_RESET 0x50 #define ADV7533_REG_CEC_OFFSET 0x70 +#define FORMAT_RATIO(x, y) (((x) * 100) / (y)) +#define RATIO_16_9 FORMAT_RATIO(16, 9) +#define RATIO_4_3 FORMAT_RATIO(4, 3) enum adv7511_input_clock { ADV7511_INPUT_CLOCK_1X, @@ -320,6 +323,7 @@ struct adv7511_video_config { enum adv7511_type { ADV7511, ADV7533, + ADV7535, }; #define ADV7511_MAX_ADDRS 3 @@ -330,6 +334,10 @@ struct adv7511 { struct i2c_client *i2c_packet; struct i2c_client *i2c_cec; + u32 addr_cec; + u32 addr_edid; + u32 addr_pkt; + struct regmap *regmap; struct regmap *regmap_cec; enum drm_connector_status status; @@ -365,6 +373,7 @@ struct adv7511 { struct device_node *host_node; struct mipi_dsi_device *dsi; u8 num_dsi_lanes; + u8 channel_id; bool use_timing_gen; enum adv7511_type type; @@ -396,7 +405,6 @@ static inline int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511) #ifdef CONFIG_DRM_I2C_ADV7533 void adv7533_dsi_power_on(struct adv7511 *adv); void adv7533_dsi_power_off(struct adv7511 *adv); -void adv7533_mode_set(struct adv7511 *adv, const struct drm_display_mode *mode); int adv7533_patch_registers(struct adv7511 *adv); int adv7533_patch_cec_registers(struct adv7511 *adv); int adv7533_attach_dsi(struct adv7511 *adv); diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c b/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c index a20a45c0b353f1..366d9bdc960bd7 100644 --- a/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c +++ b/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c @@ -302,7 +302,8 @@ static int adv7511_cec_parse_dt(struct device *dev, struct adv7511 *adv7511) int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511) { - unsigned int offset = adv7511->type == ADV7533 ? + unsigned int offset = (adv7511->type == ADV7533 || + adv7511->type == ADV7535) ? ADV7533_REG_CEC_OFFSET : 0; int ret = adv7511_cec_parse_dt(dev, adv7511); diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c index 9e13e466e72c09..1877668be1e603 100644 --- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c +++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c @@ -9,7 +9,9 @@ #include #include #include +#include #include +#include #include #include @@ -74,6 +76,26 @@ static const uint8_t adv7511_register_defaults[] = { 0x00, 0x7c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; +/* + * TODO: Currently, filter-out unsupported modes by their clocks. + * Need to find a better way to do this. + * These are the pixel clocks that the converter can handle successfully. + */ + +static const int valid_clocks[] = { + 148500, + 135000, + 132000, + 119000, + 108000, + 78750, + 74250, + 65000, + 49500, + 40000, + 31500, +}; + static bool adv7511_register_volatile(struct device *dev, unsigned int reg) { switch (reg) { @@ -329,6 +351,7 @@ static void __adv7511_power_on(struct adv7511 *adv7511) { adv7511->current_edid_segment = -1; + /* 01-02 Power */ regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER, ADV7511_POWER_POWER_DOWN, 0); if (adv7511->i2c_main->irq) { @@ -346,6 +369,7 @@ static void __adv7511_power_on(struct adv7511 *adv7511) } /* + * 01-01 HPD Manual Override * Per spec it is allowed to pulse the HPD signal to indicate that the * EDID information has changed. Some monitors do this when they wakeup * from standby or are enabled. When the HPD goes low the adv7511 is @@ -367,7 +391,7 @@ static void adv7511_power_on(struct adv7511 *adv7511) */ regcache_sync(adv7511->regmap); - if (adv7511->type == ADV7533) + if (adv7511->type == ADV7533 || adv7511->type == ADV7535) adv7533_dsi_power_on(adv7511); adv7511->powered = true; } @@ -387,7 +411,7 @@ static void __adv7511_power_off(struct adv7511 *adv7511) static void adv7511_power_off(struct adv7511 *adv7511) { __adv7511_power_off(adv7511); - if (adv7511->type == ADV7533) + if (adv7511->type == ADV7533 || adv7511->type == ADV7535) adv7533_dsi_power_off(adv7511); adv7511->powered = false; } @@ -417,17 +441,16 @@ static bool adv7511_hpd(struct adv7511 *adv7511) static void adv7511_hpd_work(struct work_struct *work) { struct adv7511 *adv7511 = container_of(work, struct adv7511, hpd_work); - enum drm_connector_status status; + enum drm_connector_status status = connector_status_disconnected; unsigned int val; int ret; ret = regmap_read(adv7511->regmap, ADV7511_REG_STATUS, &val); - if (ret < 0) - status = connector_status_disconnected; - else if (val & ADV7511_STATUS_HPD) + if (ret >= 0 && (val & ADV7511_STATUS_HPD)) status = connector_status_connected; - else - status = connector_status_disconnected; + + DRM_DEV_DEBUG_DRIVER(adv7511->connector.kdev, "HDMI HPD event: %s\n", + drm_get_connector_status_name(status)); /* * The bridge resets its registers on unplug. So when we get a plug @@ -594,6 +617,8 @@ static int adv7511_get_modes(struct adv7511 *adv7511, { struct edid *edid; unsigned int count; + u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24; + int ret; /* Reading the EDID only works if the device is powered */ if (!adv7511->powered) { @@ -623,6 +648,14 @@ static int adv7511_get_modes(struct adv7511 *adv7511, kfree(edid); + connector->display_info.bus_flags = DRM_BUS_FLAG_DE_LOW | + DRM_BUS_FLAG_PIXDATA_NEGEDGE; + + ret = drm_display_info_set_bus_formats(&connector->display_info, + &bus_format, 1); + if (ret) + return ret; + return count; } @@ -669,9 +702,21 @@ adv7511_detect(struct adv7511 *adv7511, struct drm_connector *connector) static enum drm_mode_status adv7511_mode_valid(struct adv7511 *adv7511, struct drm_display_mode *mode) { + size_t i, num_modes = ARRAY_SIZE(valid_clocks); + bool clock_ok = false; + if (mode->clock > 165000) return MODE_CLOCK_HIGH; + for (i = 0; i < num_modes; i++) + if (mode->clock == valid_clocks[i]) { + clock_ok = true; + break; + } + + if (!clock_ok) + return MODE_NOCLOCK; + return MODE_OK; } @@ -756,14 +801,16 @@ static void adv7511_mode_set(struct adv7511 *adv7511, else low_refresh_rate = ADV7511_LOW_REFRESH_RATE_NONE; - regmap_update_bits(adv7511->regmap, 0xfb, - 0x6, low_refresh_rate << 1); + if (adv7511->type == ADV7535) + regmap_update_bits(adv7511->regmap, 0x4a, + 0xc, low_refresh_rate << 2); + else + regmap_update_bits(adv7511->regmap, 0xfb, + 0x6, low_refresh_rate << 1); + regmap_update_bits(adv7511->regmap, 0x17, 0x60, (vsync_polarity << 6) | (hsync_polarity << 5)); - if (adv7511->type == ADV7533) - adv7533_mode_set(adv7511, adj_mode); - drm_mode_copy(&adv7511->curr_mode, adj_mode); /* @@ -874,7 +921,7 @@ static int adv7511_bridge_attach(struct drm_bridge *bridge) &adv7511_connector_helper_funcs); drm_connector_attach_encoder(&adv->connector, bridge->encoder); - if (adv->type == ADV7533) + if (adv->type == ADV7533 || adv->type == ADV7535) ret = adv7533_attach_dsi(adv); if (adv->i2c_main->irq) @@ -982,7 +1029,7 @@ static int adv7511_init_cec_regmap(struct adv7511 *adv) int ret; adv->i2c_cec = i2c_new_ancillary_device(adv->i2c_main, "cec", - ADV7511_CEC_I2C_ADDR_DEFAULT); + adv->addr_cec); if (IS_ERR(adv->i2c_cec)) return PTR_ERR(adv->i2c_cec); i2c_set_clientdata(adv->i2c_cec, adv); @@ -994,7 +1041,7 @@ static int adv7511_init_cec_regmap(struct adv7511 *adv) goto err; } - if (adv->type == ADV7533) { + if (adv->type == ADV7533 || adv->type == ADV7535) { ret = adv7533_patch_cec_registers(adv); if (ret) goto err; @@ -1094,6 +1141,14 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id) struct adv7511_link_config link_config; struct adv7511 *adv7511; struct device *dev = &i2c->dev; +#if IS_ENABLED(CONFIG_OF_DYNAMIC) + struct device_node *remote_node = NULL, *endpoint = NULL; + struct of_changeset ocs; +#endif + unsigned int main_i2c_addr = i2c->addr << 1; + unsigned int edid_i2c_addr = main_i2c_addr + 4; + unsigned int cec_i2c_addr = main_i2c_addr - 2; + unsigned int pkt_i2c_addr = main_i2c_addr - 0xa; unsigned int val; int ret; @@ -1128,6 +1183,21 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id) return ret; } + if (adv7511->addr_cec != 0) + cec_i2c_addr = adv7511->addr_cec << 1; + else + adv7511->addr_cec = cec_i2c_addr >> 1; + + if (adv7511->addr_edid != 0) + edid_i2c_addr = adv7511->addr_edid << 1; + else + adv7511->addr_edid = edid_i2c_addr >> 1; + + if (adv7511->addr_pkt != 0) + pkt_i2c_addr = adv7511->addr_pkt << 1; + else + adv7511->addr_pkt = pkt_i2c_addr >> 1; + /* * The power down GPIO is optional. If present, toggle it from active to * inactive to wake up the encoder. @@ -1165,33 +1235,33 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id) adv7511_packet_disable(adv7511, 0xffff); + regmap_write(adv7511->regmap, ADV7511_REG_EDID_I2C_ADDR, + edid_i2c_addr); + adv7511->i2c_edid = i2c_new_ancillary_device(i2c, "edid", - ADV7511_EDID_I2C_ADDR_DEFAULT); + adv7511->addr_edid); if (IS_ERR(adv7511->i2c_edid)) { ret = PTR_ERR(adv7511->i2c_edid); goto uninit_regulators; } - regmap_write(adv7511->regmap, ADV7511_REG_EDID_I2C_ADDR, - adv7511->i2c_edid->addr << 1); + regmap_write(adv7511->regmap, ADV7511_REG_PACKET_I2C_ADDR, + pkt_i2c_addr); adv7511->i2c_packet = i2c_new_ancillary_device(i2c, "packet", - ADV7511_PACKET_I2C_ADDR_DEFAULT); + adv7511->addr_pkt); if (IS_ERR(adv7511->i2c_packet)) { ret = PTR_ERR(adv7511->i2c_packet); goto err_i2c_unregister_edid; } - regmap_write(adv7511->regmap, ADV7511_REG_PACKET_I2C_ADDR, - adv7511->i2c_packet->addr << 1); + regmap_write(adv7511->regmap, ADV7511_REG_CEC_I2C_ADDR, + cec_i2c_addr); ret = adv7511_init_cec_regmap(adv7511); if (ret) goto err_i2c_unregister_packet; - regmap_write(adv7511->regmap, ADV7511_REG_CEC_I2C_ADDR, - adv7511->i2c_cec->addr << 1); - INIT_WORK(&adv7511->hpd_work, adv7511_hpd_work); if (i2c->irq) { @@ -1234,6 +1304,37 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id) i2c_unregister_device(adv7511->i2c_edid); uninit_regulators: adv7511_uninit_regulators(adv7511); +#if IS_ENABLED(CONFIG_OF_DYNAMIC) + endpoint = of_graph_get_next_endpoint(dev->of_node, NULL); + if (endpoint) + remote_node = of_graph_get_remote_port_parent(endpoint); + + if (!remote_node) + return ret; + + /* Find remote's endpoint connected to us and detach it */ + endpoint = NULL; + while ((endpoint = of_graph_get_next_endpoint(remote_node, + endpoint))) { + struct device_node *us; + + us = of_graph_get_remote_port_parent(endpoint); + if (us == dev->of_node) + break; + } + of_node_put(remote_node); + + if (!endpoint) + return ret; + + of_changeset_init(&ocs); + of_changeset_detach_node(&ocs, endpoint); + ret = of_changeset_apply(&ocs); + if (!ret) + dev_warn(dev, + "Probe failed. Remote port '%s' disabled\n", + remote_node->full_name); +#endif return ret; } @@ -1242,7 +1343,7 @@ static int adv7511_remove(struct i2c_client *i2c) { struct adv7511 *adv7511 = i2c_get_clientdata(i2c); - if (adv7511->type == ADV7533) + if (adv7511->type == ADV7533 || adv7511->type == ADV7535) adv7533_detach_dsi(adv7511); i2c_unregister_device(adv7511->i2c_cec); if (adv7511->cec_clk) @@ -1268,6 +1369,7 @@ static const struct i2c_device_id adv7511_i2c_ids[] = { { "adv7513", ADV7511 }, #ifdef CONFIG_DRM_I2C_ADV7533 { "adv7533", ADV7533 }, + { "adv7535", ADV7535 }, #endif { } }; @@ -1279,6 +1381,7 @@ static const struct of_device_id adv7511_of_ids[] = { { .compatible = "adi,adv7513", .data = (void *)ADV7511 }, #ifdef CONFIG_DRM_I2C_ADV7533 { .compatible = "adi,adv7533", .data = (void *)ADV7533 }, + { .compatible = "adi,adv7535", .data = (void *)ADV7535 }, #endif { } }; diff --git a/drivers/gpu/drm/bridge/adv7511/adv7533.c b/drivers/gpu/drm/bridge/adv7511/adv7533.c index aa19d5a40e319e..27d63b804f318c 100644 --- a/drivers/gpu/drm/bridge/adv7511/adv7533.c +++ b/drivers/gpu/drm/bridge/adv7511/adv7533.c @@ -26,10 +26,8 @@ static const struct reg_sequence adv7533_cec_fixed_registers[] = { static void adv7511_dsi_config_timing_gen(struct adv7511 *adv) { - struct mipi_dsi_device *dsi = adv->dsi; struct drm_display_mode *mode = &adv->curr_mode; unsigned int hsw, hfp, hbp, vsw, vfp, vbp; - u8 clock_div_by_lanes[] = { 6, 4, 3 }; /* 2, 3, 4 lanes */ hsw = mode->hsync_end - mode->hsync_start; hfp = mode->hsync_start - mode->hdisplay; @@ -38,9 +36,10 @@ static void adv7511_dsi_config_timing_gen(struct adv7511 *adv) vfp = mode->vsync_start - mode->vdisplay; vbp = mode->vtotal - mode->vsync_end; - /* set pixel clock divider mode */ - regmap_write(adv->regmap_cec, 0x16, - clock_div_by_lanes[dsi->lanes - 2] << 3); + /* 03-01 Enable Internal Timing Generator */ + regmap_write(adv->regmap_cec, 0x27, 0xcb); + + /* 03-08 Timing Configuration */ /* horizontal porch params */ regmap_write(adv->regmap_cec, 0x28, mode->htotal >> 4); @@ -61,35 +60,66 @@ static void adv7511_dsi_config_timing_gen(struct adv7511 *adv) regmap_write(adv->regmap_cec, 0x35, (vfp << 4) & 0xff); regmap_write(adv->regmap_cec, 0x36, vbp >> 4); regmap_write(adv->regmap_cec, 0x37, (vbp << 4) & 0xff); + + /* 03-03 Reset Internal Timing Generator */ + regmap_write(adv->regmap_cec, 0x27, 0xcb); + regmap_write(adv->regmap_cec, 0x27, 0x8b); + regmap_write(adv->regmap_cec, 0x27, 0xcb); + } void adv7533_dsi_power_on(struct adv7511 *adv) { struct mipi_dsi_device *dsi = adv->dsi; + struct drm_display_mode *mode = &adv->curr_mode; + u8 clock_div_by_lanes[] = { 6, 4, 3 }; /* 2, 3, 4 lanes */ - if (adv->use_timing_gen) - adv7511_dsi_config_timing_gen(adv); + /* Gate DSI LP Oscillator */ + regmap_update_bits(adv->regmap_cec, 0x03, 0x02, 0x00); - /* set number of dsi lanes */ + /* 01-03 Initialisation (Fixed) Registers */ + regmap_register_patch(adv->regmap_cec, adv7533_cec_fixed_registers, + ARRAY_SIZE(adv7533_cec_fixed_registers)); + + /* 02-04 DSI Lanes */ regmap_write(adv->regmap_cec, 0x1c, dsi->lanes << 4); - if (adv->use_timing_gen) { - /* reset internal timing generator */ - regmap_write(adv->regmap_cec, 0x27, 0xcb); - regmap_write(adv->regmap_cec, 0x27, 0x8b); - regmap_write(adv->regmap_cec, 0x27, 0xcb); - } else { - /* disable internal timing generator */ + /* 02-05 DSI Pixel Clock Divider */ + regmap_write(adv->regmap_cec, 0x16, + clock_div_by_lanes[dsi->lanes - 2] << 3); + + if (adv->use_timing_gen) + adv7511_dsi_config_timing_gen(adv); + else regmap_write(adv->regmap_cec, 0x27, 0x0b); - } - /* enable hdmi */ + /* 04-01 HDMI Output */ + regmap_write(adv->regmap, 0xaf, 0x16); + + /* 09-03 AVI Infoframe - RGB - 16-9 Aspect Ratio */ + regmap_write(adv->regmap, ADV7511_REG_AVI_INFOFRAME(0), 0x10); + if (FORMAT_RATIO(mode->hdisplay, mode->vdisplay) == RATIO_16_9) + regmap_write(adv->regmap, ADV7511_REG_AVI_INFOFRAME(1), 0x28); + else if (FORMAT_RATIO(mode->hdisplay, mode->vdisplay) == RATIO_4_3) + regmap_write(adv->regmap, ADV7511_REG_AVI_INFOFRAME(1), 0x18); + + /* 04-04 GC Packet Enable */ + regmap_write(adv->regmap, ADV7511_REG_PACKET_ENABLE0, 0x80); + + /* 04-06 GC Colour Depth - 24 Bit */ + regmap_write(adv->regmap, 0x4c, 0x04); + + /* 04-09 Down Dither Output Colour Depth - 8 Bit (default) */ + regmap_write(adv->regmap, 0x49, 0x00); + + /* 07-01 CEC Power Mode - Always Active */ + regmap_write(adv->regmap_cec, 0xbe, 0x3d); + + /* 04-03 HDMI Output Enable */ regmap_write(adv->regmap_cec, 0x03, 0x89); /* disable test mode */ regmap_write(adv->regmap_cec, 0x55, 0x00); - regmap_register_patch(adv->regmap_cec, adv7533_cec_fixed_registers, - ARRAY_SIZE(adv7533_cec_fixed_registers)); } void adv7533_dsi_power_off(struct adv7511 *adv) @@ -100,28 +130,6 @@ void adv7533_dsi_power_off(struct adv7511 *adv) regmap_write(adv->regmap_cec, 0x27, 0x0b); } -void adv7533_mode_set(struct adv7511 *adv, const struct drm_display_mode *mode) -{ - struct mipi_dsi_device *dsi = adv->dsi; - int lanes, ret; - - if (adv->num_dsi_lanes != 4) - return; - - if (mode->clock > 80000) - lanes = 4; - else - lanes = 3; - - if (lanes != dsi->lanes) { - mipi_dsi_detach(dsi); - dsi->lanes = lanes; - ret = mipi_dsi_attach(dsi); - if (ret) - dev_err(&dsi->dev, "failed to change host lanes\n"); - } -} - int adv7533_patch_registers(struct adv7511 *adv) { return regmap_register_patch(adv->regmap, @@ -143,7 +151,7 @@ int adv7533_attach_dsi(struct adv7511 *adv) struct mipi_dsi_device *dsi; int ret = 0; const struct mipi_dsi_device_info info = { .type = "adv7533", - .channel = 0, + .channel = adv->channel_id, .node = NULL, }; @@ -189,14 +197,24 @@ void adv7533_detach_dsi(struct adv7511 *adv) int adv7533_parse_dt(struct device_node *np, struct adv7511 *adv) { - u32 num_lanes; + struct device *dev = &adv->i2c_main->dev; + u32 num_lanes = 0, channel_id = 0; + of_property_read_u32(np, "adi,dsi-channel", &channel_id); of_property_read_u32(np, "adi,dsi-lanes", &num_lanes); - if (num_lanes < 1 || num_lanes > 4) + if (num_lanes < 1 || num_lanes > 4) { + dev_err(dev, "Invalid dsi-lanes: %d\n", num_lanes); return -EINVAL; + } + + if (channel_id > 3) { + dev_err(dev, "Invalid dsi-channel: %d\n", channel_id); + return -EINVAL; + } adv->num_dsi_lanes = num_lanes; + adv->channel_id = channel_id; adv->host_node = of_graph_get_remote_node(np, 0, 0); if (!adv->host_node) @@ -207,6 +225,10 @@ int adv7533_parse_dt(struct device_node *np, struct adv7511 *adv) adv->use_timing_gen = !of_property_read_bool(np, "adi,disable-timing-generator"); + of_property_read_u32(np, "adi,addr-cec", &adv->addr_cec); + of_property_read_u32(np, "adi,addr-edid", &adv->addr_edid); + of_property_read_u32(np, "adi,addr-pkt", &adv->addr_pkt); + /* TODO: Check if these need to be parsed by DT or not */ adv->rgb = true; adv->embedded_sync = false; diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig b/drivers/gpu/drm/bridge/cadence/Kconfig new file mode 100644 index 00000000000000..962de96c0b6d11 --- /dev/null +++ b/drivers/gpu/drm/bridge/cadence/Kconfig @@ -0,0 +1,25 @@ +config DRM_CDNS_MHDP + tristate "Cadence MHDP COMMON API driver" + select DRM_KMS_HELPER + select DRM_PANEL_BRIDGE + depends on OF + help + Support Cadence MHDP API library. + +config DRM_CDNS_HDMI + tristate "Cadence HDMI DRM driver" + depends on DRM_CDNS_MHDP + +config DRM_CDNS_DP + tristate "Cadence DP DRM driver" + depends on DRM_CDNS_MHDP + +config DRM_CDNS_AUDIO + tristate "Cadence MHDP Audio driver" + depends on DRM_CDNS_MHDP + +config DRM_CDNS_HDMI_CEC + tristate "Cadence MHDP HDMI CEC driver" + depends on DRM_CDNS_HDMI + select CEC_CORE + select CEC_NOTIFIER diff --git a/drivers/gpu/drm/bridge/cadence/Makefile b/drivers/gpu/drm/bridge/cadence/Makefile new file mode 100644 index 00000000000000..990794d3699964 --- /dev/null +++ b/drivers/gpu/drm/bridge/cadence/Makefile @@ -0,0 +1,9 @@ + +cdns_mhdp_drmcore-y := cdns-mhdp-common.o cdns-mhdp-hdmi.o + +cdns_mhdp_drmcore-$(CONFIG_DRM_CDNS_HDMI) += cdns-hdmi-core.o +cdns_mhdp_drmcore-$(CONFIG_DRM_CDNS_DP) += cdns-dp-core.o +cdns_mhdp_drmcore-$(CONFIG_DRM_CDNS_AUDIO) += cdns-mhdp-audio.o +cdns_mhdp_drmcore-$(CONFIG_DRM_CDNS_HDMI_CEC) += cdns-mhdp-cec.o + +obj-$(CONFIG_DRM_CDNS_MHDP) += cdns_mhdp_drmcore.o diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c new file mode 100644 index 00000000000000..17deef45f50992 --- /dev/null +++ b/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c @@ -0,0 +1,591 @@ +/* + * Cadence Display Port Interface (DP) driver + * + * Copyright (C) 2019 NXP Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * This function only implements native DPDC reads and writes + */ +static ssize_t dp_aux_transfer(struct drm_dp_aux *aux, + struct drm_dp_aux_msg *msg) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(aux->dev); + bool native = msg->request & (DP_AUX_NATIVE_WRITE & DP_AUX_NATIVE_READ); + int ret; + + /* Ignore address only message */ + if ((msg->size == 0) || (msg->buffer == NULL)) { + msg->reply = native ? + DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK; + return msg->size; + } + + if (!native) { + dev_err(mhdp->dev, "%s: only native messages supported\n", __func__); + return -EINVAL; + } + + /* msg sanity check */ + if (msg->size > DP_AUX_MAX_PAYLOAD_BYTES) { + dev_err(mhdp->dev, "%s: invalid msg: size(%zu), request(%x)\n", + __func__, msg->size, (unsigned int)msg->request); + return -EINVAL; + } + + if (msg->request == DP_AUX_NATIVE_WRITE) { + const u8 *buf = msg->buffer; + int i; + for (i = 0; i < msg->size; ++i) { + ret = cdns_mhdp_dpcd_write(mhdp, + msg->address + i, buf[i]); + if (!ret) + continue; + + DRM_DEV_ERROR(mhdp->dev, "Failed to write DPCD\n"); + + return ret; + } + } + + if (msg->request == DP_AUX_NATIVE_READ) { + ret = cdns_mhdp_dpcd_read(mhdp, msg->address, msg->buffer, msg->size); + if (ret < 0) + return -EIO; + msg->reply = DP_AUX_NATIVE_REPLY_ACK; + return msg->size; + } + return 0; +} + +static int dp_aux_init(struct cdns_mhdp_device *mhdp, + struct device *dev) +{ + int ret; + + mhdp->dp.aux.name = "imx_dp_aux"; + mhdp->dp.aux.dev = dev; + mhdp->dp.aux.transfer = dp_aux_transfer; + + ret = drm_dp_aux_register(&mhdp->dp.aux); + + return ret; +} + +static int dp_aux_destroy(struct cdns_mhdp_device *mhdp) +{ + drm_dp_aux_unregister(&mhdp->dp.aux); + return 0; +} + +static void dp_pixel_clk_reset(struct cdns_mhdp_device *mhdp) +{ + u32 val; + + /* reset pixel clk */ + val = cdns_mhdp_reg_read(mhdp, SOURCE_HDTX_CAR); + cdns_mhdp_reg_write(mhdp, SOURCE_HDTX_CAR, val & 0xFD); + cdns_mhdp_reg_write(mhdp, SOURCE_HDTX_CAR, val); +} + +static void cdns_dp_mode_set(struct cdns_mhdp_device *mhdp) +{ + u32 lane_mapping = mhdp->lane_mapping; + struct drm_dp_link *link = &mhdp->dp.link; + char linkid[6]; + int ret; + + cdns_mhdp_plat_call(mhdp, pclk_rate); + + /* delay for DP FW stable after pixel clock relock */ + msleep(50); + + dp_pixel_clk_reset(mhdp); + + ret = drm_dp_downstream_id(&mhdp->dp.aux, linkid); + if (ret < 0) { + DRM_INFO("Failed to Get DP link ID: %d\n", ret); + return; + } + DRM_INFO("DP link id: %s, 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + linkid, linkid[0], linkid[1], linkid[2], linkid[3], linkid[4], + linkid[5]); + + /* Check dp link */ + ret = drm_dp_link_probe(&mhdp->dp.aux, link); + if (ret < 0) { + DRM_INFO("Failed to probe DP link: %d\n", ret); + return; + } + DRM_INFO("DP revision: 0x%x\n", link->revision); + DRM_INFO("DP rate: %d Mbps\n", link->rate); + DRM_INFO("DP number of lanes: %d\n", link->num_lanes); + DRM_INFO("DP capabilities: 0x%lx\n", link->capabilities); + + /* check the max link rate */ + if (link->rate > CDNS_DP_MAX_LINK_RATE) + link->rate = CDNS_DP_MAX_LINK_RATE; + + drm_dp_link_power_up(&mhdp->dp.aux, link); + if (ret < 0) { + DRM_INFO("Failed to power DP link: %d\n", ret); + return; + } + + /* Initialize link rate/num_lanes as panel max link rate/max_num_lanes */ + cdns_mhdp_plat_call(mhdp, phy_set); + + /* Video off */ + ret = cdns_mhdp_set_video_status(mhdp, CONTROL_VIDEO_IDLE); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "Failed to valid video %d\n", ret); + return; + } + + /* Line swaping */ + cdns_mhdp_reg_write(mhdp, LANES_CONFIG, 0x00400000 | lane_mapping); + + /* Set DP host capability */ + ret = cdns_mhdp_set_host_cap(mhdp, false); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "Failed to set host cap %d\n", ret); + return; + } + + ret = cdns_mhdp_config_video(mhdp); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "Failed to config video %d\n", ret); + return; + } + + return; +} + +/* ----------------------------------------------------------------------------- + * dp TX Setup + */ +static enum drm_connector_status +cdns_dp_connector_detect(struct drm_connector *connector, bool force) +{ + struct cdns_mhdp_device *mhdp = container_of(connector, + struct cdns_mhdp_device, connector.base); + u8 hpd = 0xf; + + hpd = cdns_mhdp_read_hpd(mhdp); + if (hpd == 1) + /* Cable Connected */ + return connector_status_connected; + else if (hpd == 0) + /* Cable Disconnedted */ + return connector_status_disconnected; + else { + /* Cable status unknown */ + DRM_INFO("Unknow cable status, hdp=%u\n", hpd); + return connector_status_unknown; + } +} + +static int cdns_dp_connector_get_modes(struct drm_connector *connector) +{ + struct cdns_mhdp_device *mhdp = container_of(connector, + struct cdns_mhdp_device, connector.base); + int num_modes = 0; + struct edid *edid; + + edid = drm_do_get_edid(&mhdp->connector.base, + cdns_mhdp_get_edid_block, mhdp); + if (edid) { + dev_info(mhdp->dev, "%x,%x,%x,%x,%x,%x,%x,%x\n", + edid->header[0], edid->header[1], + edid->header[2], edid->header[3], + edid->header[4], edid->header[5], + edid->header[6], edid->header[7]); + drm_connector_update_edid_property(connector, edid); + num_modes = drm_add_edid_modes(connector, edid); + kfree(edid); + } + + if (num_modes == 0) + DRM_ERROR("Invalid edid\n"); + return num_modes; +} + +static const struct drm_connector_funcs cdns_dp_connector_funcs = { + .fill_modes = drm_helper_probe_single_connector_modes, + .detect = cdns_dp_connector_detect, + .destroy = drm_connector_cleanup, + .reset = drm_atomic_helper_connector_reset, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +static const struct drm_connector_helper_funcs cdns_dp_connector_helper_funcs = { + .get_modes = cdns_dp_connector_get_modes, +}; + +static int cdns_dp_bridge_attach(struct drm_bridge *bridge) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + struct drm_encoder *encoder = bridge->encoder; + struct drm_connector *connector = &mhdp->connector.base; + + connector->interlace_allowed = 1; + + if (mhdp->is_hpd) + connector->polled = DRM_CONNECTOR_POLL_HPD; + else + connector->polled = DRM_CONNECTOR_POLL_CONNECT | + DRM_CONNECTOR_POLL_DISCONNECT; + + drm_connector_helper_add(connector, &cdns_dp_connector_helper_funcs); + + drm_connector_init(bridge->dev, connector, &cdns_dp_connector_funcs, + DRM_MODE_CONNECTOR_DisplayPort); + + drm_connector_attach_encoder(connector, encoder); + + return 0; +} + +static enum drm_mode_status +cdns_dp_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_mode *mode) +{ + enum drm_mode_status mode_status = MODE_OK; + + /* We don't support double-clocked modes */ + if (mode->flags & DRM_MODE_FLAG_DBLCLK || + mode->flags & DRM_MODE_FLAG_INTERLACE) + return MODE_BAD; + + /* MAX support pixel clock rate 594MHz */ + if (mode->clock > 594000) + return MODE_CLOCK_HIGH; + + /* 4096x2160 is not supported now */ + if (mode->hdisplay > 3840) + return MODE_BAD_HVALUE; + + if (mode->vdisplay > 2160) + return MODE_BAD_VVALUE; + + return mode_status; +} + +static void cdns_dp_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *orig_mode, + const struct drm_display_mode *mode) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + struct drm_display_info *display_info = &mhdp->connector.base.display_info; + struct video_info *video = &mhdp->video_info; + + switch (display_info->bpc) { + case 10: + video->color_depth = 10; + break; + case 6: + video->color_depth = 6; + break; + default: + video->color_depth = 8; + break; + } + + video->color_fmt = PXL_RGB; + video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); + video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); + + DRM_INFO("Mode: %dx%dp%d\n", mode->hdisplay, mode->vdisplay, mode->clock); + memcpy(&mhdp->mode, mode, sizeof(struct drm_display_mode)); + + mutex_lock(&mhdp->lock); + cdns_dp_mode_set(mhdp); + mutex_unlock(&mhdp->lock); + + /* reset force mode set flag */ + mhdp->force_mode_set = false; +} + +static void cdn_dp_bridge_enable(struct drm_bridge *bridge) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + int ret; + + drm_dp_link_power_up(&mhdp->dp.aux, &mhdp->dp.link); + + /* Link trainning */ + ret = cdns_mhdp_train_link(mhdp); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "Failed link train %d\n", ret); + return; + } + + ret = cdns_mhdp_set_video_status(mhdp, CONTROL_VIDEO_VALID); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "Failed to valid video %d\n", ret); + return; + } +} + +static void cdn_dp_bridge_disable(struct drm_bridge *bridge) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + + cdns_mhdp_set_video_status(mhdp, CONTROL_VIDEO_IDLE); +} + +static const struct drm_bridge_funcs cdns_dp_bridge_funcs = { + .attach = cdns_dp_bridge_attach, + .enable = cdn_dp_bridge_enable, + .disable = cdn_dp_bridge_disable, + .mode_set = cdns_dp_bridge_mode_set, + .mode_valid = cdns_dp_bridge_mode_valid, +}; + +static void hotplug_work_func(struct work_struct *work) +{ + struct cdns_mhdp_device *mhdp = container_of(work, + struct cdns_mhdp_device, hotplug_work.work); + struct drm_connector *connector = &mhdp->connector.base; + + drm_helper_hpd_irq_event(connector->dev); + + if (connector->status == connector_status_connected) { + /* Cable connedted */ + DRM_INFO("HDMI/DP Cable Plug In\n"); + /* force mode set to recovery weston DP video display */ + mhdp->force_mode_set = true; + enable_irq(mhdp->irq[IRQ_OUT]); + } else if (connector->status == connector_status_disconnected) { + /* Cable Disconnedted */ + DRM_INFO("HDMI/DP Cable Plug Out\n"); + enable_irq(mhdp->irq[IRQ_IN]); + } +} + +static irqreturn_t cdns_dp_irq_thread(int irq, void *data) +{ + struct cdns_mhdp_device *mhdp = data; + + disable_irq_nosync(irq); + + mod_delayed_work(system_wq, &mhdp->hotplug_work, + msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS)); + + return IRQ_HANDLED; +} + +static void cdns_dp_parse_dt(struct cdns_mhdp_device *mhdp) +{ + struct device_node *of_node = mhdp->dev->of_node; + int ret; + + ret = of_property_read_u32(of_node, "lane-mapping", + &mhdp->lane_mapping); + if (ret) { + mhdp->lane_mapping = 0xc6; + dev_warn(mhdp->dev, "Failed to get lane_mapping - using default 0xc6\n"); + } + dev_info(mhdp->dev, "lane-mapping 0x%02x\n", mhdp->lane_mapping); +} + +static int __cdns_dp_probe(struct platform_device *pdev, + struct cdns_mhdp_device *mhdp) +{ + struct device *dev = &pdev->dev; + struct resource *iores = NULL; + int ret; + + mutex_init(&mhdp->lock); + mutex_init(&mhdp->iolock); + + INIT_DELAYED_WORK(&mhdp->hotplug_work, hotplug_work_func); + + iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (iores) { + mhdp->regs_base = devm_ioremap(dev, iores->start, + resource_size(iores)); + if (IS_ERR(mhdp->regs_base)) + return -ENOMEM; + } + + iores = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (iores) { + mhdp->regs_sec = devm_ioremap(dev, iores->start, + resource_size(iores)); + if (IS_ERR(mhdp->regs_sec)) + return -ENOMEM; + } + + mhdp->is_hpd = true; + mhdp->is_ls1028a = false; + + mhdp->irq[IRQ_IN] = platform_get_irq_byname(pdev, "plug_in"); + if (mhdp->irq[IRQ_IN] < 0) { + mhdp->is_hpd = false; + dev_info(dev, "No plug_in irq number\n"); + } + + mhdp->irq[IRQ_OUT] = platform_get_irq_byname(pdev, "plug_out"); + if (mhdp->irq[IRQ_OUT] < 0) { + mhdp->is_hpd = false; + dev_info(dev, "No plug_out irq number\n"); + } + + cdns_dp_parse_dt(mhdp); + + if (of_device_is_compatible(dev->of_node, "cdn,ls1028a-dp")) + mhdp->is_ls1028a = true; + + cdns_mhdp_plat_call(mhdp, power_on); + + cdns_mhdp_plat_call(mhdp, firmware_init); + + /* DP FW alive check */ + ret = cdns_mhdp_check_alive(mhdp); + if (ret == false) { + DRM_ERROR("NO dp FW running\n"); + return -ENXIO; + } + + /* DP PHY init before AUX init */ + cdns_mhdp_plat_call(mhdp, phy_set); + + /* Enable Hotplug Detect IRQ thread */ + if (mhdp->is_hpd) { + irq_set_status_flags(mhdp->irq[IRQ_IN], IRQ_NOAUTOEN); + ret = devm_request_threaded_irq(dev, mhdp->irq[IRQ_IN], + NULL, cdns_dp_irq_thread, + IRQF_ONESHOT, dev_name(dev), + mhdp); + + if (ret) { + dev_err(dev, "can't claim irq %d\n", + mhdp->irq[IRQ_IN]); + return -EINVAL; + } + + irq_set_status_flags(mhdp->irq[IRQ_OUT], IRQ_NOAUTOEN); + ret = devm_request_threaded_irq(dev, mhdp->irq[IRQ_OUT], + NULL, cdns_dp_irq_thread, + IRQF_ONESHOT, dev_name(dev), + mhdp); + + if (ret) { + dev_err(dev, "can't claim irq %d\n", + mhdp->irq[IRQ_OUT]); + return -EINVAL; + } + + if (cdns_mhdp_read_hpd(mhdp)) + enable_irq(mhdp->irq[IRQ_OUT]); + else + enable_irq(mhdp->irq[IRQ_IN]); + } + + mhdp->bridge.base.driver_private = mhdp; + mhdp->bridge.base.funcs = &cdns_dp_bridge_funcs; +#ifdef CONFIG_OF + mhdp->bridge.base.of_node = dev->of_node; +#endif + + dev_set_drvdata(dev, mhdp); + + /* register audio driver */ + cdns_mhdp_register_audio_driver(dev); + + dp_aux_init(mhdp, dev); + + return 0; +} + +static void __cdns_dp_remove(struct cdns_mhdp_device *mhdp) +{ + dp_aux_destroy(mhdp); + cdns_mhdp_unregister_audio_driver(mhdp->dev); +} + +/* ----------------------------------------------------------------------------- + * Probe/remove API, used from platforms based on the DRM bridge API. + */ +int cdns_dp_probe(struct platform_device *pdev, + struct cdns_mhdp_device *mhdp) +{ + int ret; + + ret = __cdns_dp_probe(pdev, mhdp); + if (ret) + return ret; + + drm_bridge_add(&mhdp->bridge.base); + + return 0; +} +EXPORT_SYMBOL_GPL(cdns_dp_probe); + +void cdns_dp_remove(struct platform_device *pdev) +{ + struct cdns_mhdp_device *mhdp = platform_get_drvdata(pdev); + + drm_bridge_remove(&mhdp->bridge.base); + + __cdns_dp_remove(mhdp); +} +EXPORT_SYMBOL_GPL(cdns_dp_remove); + +/* ----------------------------------------------------------------------------- + * Bind/unbind API, used from platforms based on the component framework. + */ +int cdns_dp_bind(struct platform_device *pdev, struct drm_encoder *encoder, + struct cdns_mhdp_device *mhdp) +{ + int ret; + + ret = __cdns_dp_probe(pdev, mhdp); + if (ret < 0) + return ret; + + ret = drm_bridge_attach(encoder, &mhdp->bridge.base, NULL); + if (ret) { + cdns_dp_remove(pdev); + DRM_ERROR("Failed to initialize bridge with drm\n"); + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(cdns_dp_bind); + +void cdns_dp_unbind(struct device *dev) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + + __cdns_dp_remove(mhdp); +} +EXPORT_SYMBOL_GPL(cdns_dp_unbind); + +MODULE_AUTHOR("Sandor Yu "); +MODULE_DESCRIPTION("Cadence Display Port transmitter driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:cdn-dp"); diff --git a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file mode 100644 index 00000000000000..73a7d0a04f21b4 --- /dev/null +++ b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c @@ -0,0 +1,692 @@ +/* + * Cadence High-Definition Multimedia Interface (HDMI) driver + * + * Copyright (C) 2019 NXP Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void hdmi_sink_config(struct cdns_mhdp_device *mhdp) +{ + struct drm_scdc *scdc = &mhdp->connector.base.display_info.hdmi.scdc; + u8 buff = 0; + + /* Default work in HDMI1.4 */ + mhdp->hdmi.hdmi_type = MODE_HDMI_1_4; + + /* check sink support SCDC or not */ + if (scdc->supported != true) { + DRM_INFO("Sink Not Support SCDC\n"); + return; + } + + if (mhdp->hdmi.char_rate > 340000) { + /* + * TMDS Character Rate above 340MHz should working in HDMI2.0 + * Enable scrambling and TMDS_Bit_Clock_Ratio + */ + buff = SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE; + mhdp->hdmi.hdmi_type = MODE_HDMI_2_0; + } else if (scdc->scrambling.low_rates) { + /* + * Enable scrambling and HDMI2.0 when scrambling capability of sink + * be indicated in the HF-VSDB LTE_340Mcsc_scramble bit + */ + buff = SCDC_SCRAMBLING_ENABLE; + mhdp->hdmi.hdmi_type = MODE_HDMI_2_0; + } + + /* TMDS config */ + cdns_hdmi_scdc_write(mhdp, 0x20, buff); +} + +static void hdmi_lanes_config(struct cdns_mhdp_device *mhdp) +{ + /* Line swaping */ + cdns_mhdp_reg_write(mhdp, LANES_CONFIG, 0x00400000 | mhdp->lane_mapping); +} + +static int hdmi_avi_info_set(struct cdns_mhdp_device *mhdp, + struct drm_display_mode *mode) +{ + struct hdmi_avi_infoframe frame; + int format = mhdp->video_info.color_fmt; + struct drm_connector_state *conn_state = mhdp->connector.base.state; + struct drm_display_mode *adj_mode; + enum hdmi_quantization_range qr; + u8 buf[32]; + int ret; + + /* Initialise info frame from DRM mode */ + drm_hdmi_avi_infoframe_from_display_mode(&frame, &mhdp->connector.base, + mode); + + switch (format) { + case YCBCR_4_4_4: + frame.colorspace = HDMI_COLORSPACE_YUV444; + break; + case YCBCR_4_2_2: + frame.colorspace = HDMI_COLORSPACE_YUV422; + break; + case YCBCR_4_2_0: + frame.colorspace = HDMI_COLORSPACE_YUV420; + break; + default: + frame.colorspace = HDMI_COLORSPACE_RGB; + break; + } + + drm_hdmi_avi_infoframe_colorspace(&frame, conn_state); + + adj_mode = &mhdp->bridge.base.encoder->crtc->state->adjusted_mode; + + qr = drm_default_rgb_quant_range(adj_mode); + + drm_hdmi_avi_infoframe_quant_range(&frame, &mhdp->connector.base, + adj_mode, qr); + + ret = hdmi_avi_infoframe_check(&frame); + if (WARN_ON(ret)) + return false; + + ret = hdmi_avi_infoframe_pack(&frame, buf + 1, sizeof(buf) - 1); + if (ret < 0) { + DRM_ERROR("failed to pack AVI infoframe: %d\n", ret); + return -1; + } + + buf[0] = 0; + cdns_mhdp_infoframe_set(mhdp, 0, sizeof(buf), buf, HDMI_INFOFRAME_TYPE_AVI); + return 0; +} + +static void hdmi_vendor_info_set(struct cdns_mhdp_device *mhdp, + struct drm_display_mode *mode) +{ + struct hdmi_vendor_infoframe frame; + u8 buf[32]; + int ret; + + /* Initialise vendor frame from DRM mode */ + ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame, &mhdp->connector.base, mode); + if (ret < 0) { + DRM_INFO("No vendor infoframe\n"); + return; + } + + ret = hdmi_vendor_infoframe_pack(&frame, buf + 1, sizeof(buf) - 1); + if (ret < 0) { + DRM_WARN("Unable to pack vendor infoframe: %d\n", ret); + return; + } + + buf[0] = 0; + cdns_mhdp_infoframe_set(mhdp, 3, sizeof(buf), buf, HDMI_INFOFRAME_TYPE_VENDOR); +} + +static void hdmi_drm_info_set(struct cdns_mhdp_device *mhdp) +{ + struct drm_connector_state *conn_state; + struct hdmi_drm_infoframe frame; + u8 buf[32]; + int ret; + + conn_state = mhdp->connector.base.state; + + if (!conn_state->hdr_output_metadata) + return; + + ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state); + if (ret < 0) { + DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n"); + return; + } + + ret = hdmi_drm_infoframe_pack(&frame, buf + 1, sizeof(buf) - 1); + if (ret < 0) { + DRM_DEBUG_KMS("couldn't pack HDR infoframe\n"); + return; + } + + buf[0] = 0; + cdns_mhdp_infoframe_set(mhdp, 3, sizeof(buf), + buf, HDMI_INFOFRAME_TYPE_DRM); +} + +void cdns_hdmi_mode_set(struct cdns_mhdp_device *mhdp) +{ + struct drm_display_mode *mode = &mhdp->mode; + int ret; + + /* video mode valid check */ + if (mode->clock == 0 || mode->hdisplay == 0 || mode->vdisplay == 0) + return; + + hdmi_lanes_config(mhdp); + + cdns_mhdp_plat_call(mhdp, pclk_rate); + + /* delay for HDMI FW stable after pixel clock relock */ + msleep(20); + + cdns_mhdp_plat_call(mhdp, phy_set); + + hdmi_sink_config(mhdp); + + ret = cdns_hdmi_ctrl_init(mhdp, mhdp->hdmi.hdmi_type, mhdp->hdmi.char_rate); + if (ret < 0) { + DRM_ERROR("%s, ret = %d\n", __func__, ret); + return; + } + + /* Config GCP */ + if (mhdp->video_info.color_depth == 8) + cdns_hdmi_disable_gcp(mhdp); + else + cdns_hdmi_enable_gcp(mhdp); + + ret = hdmi_avi_info_set(mhdp, mode); + if (ret < 0) { + DRM_ERROR("%s ret = %d\n", __func__, ret); + return; + } + + /* vendor info frame is enable only when HDMI1.4 4K mode */ + hdmi_vendor_info_set(mhdp, mode); + + hdmi_drm_info_set(mhdp); + + ret = cdns_hdmi_mode_config(mhdp, mode, &mhdp->video_info); + if (ret < 0) { + DRM_ERROR("CDN_API_HDMITX_SetVic_blocking ret = %d\n", ret); + return; + } +} + +static enum drm_connector_status +cdns_hdmi_connector_detect(struct drm_connector *connector, bool force) +{ + struct cdns_mhdp_device *mhdp = + container_of(connector, struct cdns_mhdp_device, connector.base); + + u8 hpd = 0xf; + + hpd = cdns_mhdp_read_hpd(mhdp); + + if (hpd == 1) + /* Cable Connected */ + return connector_status_connected; + else if (hpd == 0) + /* Cable Disconnedted */ + return connector_status_disconnected; + else { + /* Cable status unknown */ + DRM_INFO("Unknow cable status, hdp=%u\n", hpd); + return connector_status_unknown; + } +} + +static int cdns_hdmi_connector_get_modes(struct drm_connector *connector) +{ + struct cdns_mhdp_device *mhdp = + container_of(connector, struct cdns_mhdp_device, connector.base); + int num_modes = 0; + struct edid *edid; + + edid = drm_do_get_edid(&mhdp->connector.base, + cdns_hdmi_get_edid_block, mhdp); + if (edid) { + dev_info(mhdp->dev, "%x,%x,%x,%x,%x,%x,%x,%x\n", + edid->header[0], edid->header[1], + edid->header[2], edid->header[3], + edid->header[4], edid->header[5], + edid->header[6], edid->header[7]); + drm_connector_update_edid_property(connector, edid); + num_modes = drm_add_edid_modes(connector, edid); + kfree(edid); + } + + if (num_modes == 0) + DRM_ERROR("Invalid edid\n"); + return num_modes; +} + +static bool blob_equal(const struct drm_property_blob *a, + const struct drm_property_blob *b) +{ + if (a && b) + return a->length == b->length && + !memcmp(a->data, b->data, a->length); + + return !a == !b; +} + +static int cdns_hdmi_connector_atomic_check(struct drm_connector *connector, + struct drm_atomic_state *state) +{ + struct drm_connector_state *new_con_state = + drm_atomic_get_new_connector_state(state, connector); + struct drm_connector_state *old_con_state = + drm_atomic_get_old_connector_state(state, connector); + struct drm_crtc *crtc = new_con_state->crtc; + struct drm_crtc_state *new_crtc_state; + + if (!blob_equal(new_con_state->hdr_output_metadata, + old_con_state->hdr_output_metadata) || + new_con_state->colorspace != old_con_state->colorspace) { + new_crtc_state = drm_atomic_get_crtc_state(state, crtc); + if (IS_ERR(new_crtc_state)) + return PTR_ERR(new_crtc_state); + + new_crtc_state->mode_changed = + !new_con_state->hdr_output_metadata || + !old_con_state->hdr_output_metadata || + new_con_state->colorspace != old_con_state->colorspace; + } + + return 0; +} + +static const struct drm_connector_funcs cdns_hdmi_connector_funcs = { + .fill_modes = drm_helper_probe_single_connector_modes, + .detect = cdns_hdmi_connector_detect, + .destroy = drm_connector_cleanup, + .reset = drm_atomic_helper_connector_reset, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +static const struct drm_connector_helper_funcs cdns_hdmi_connector_helper_funcs = { + .get_modes = cdns_hdmi_connector_get_modes, + .atomic_check = cdns_hdmi_connector_atomic_check, +}; + +static int cdns_hdmi_bridge_attach(struct drm_bridge *bridge) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + struct drm_mode_config *config = &bridge->dev->mode_config; + struct drm_encoder *encoder = bridge->encoder; + struct drm_connector *connector = &mhdp->connector.base; + + connector->interlace_allowed = 1; + connector->polled = DRM_CONNECTOR_POLL_HPD; + + drm_connector_helper_add(connector, &cdns_hdmi_connector_helper_funcs); + + drm_connector_init(bridge->dev, connector, &cdns_hdmi_connector_funcs, + DRM_MODE_CONNECTOR_HDMIA); + + if (!strncmp("imx8mq-hdmi", mhdp->plat_data->plat_name, 11)) { + drm_object_attach_property(&connector->base, + config->hdr_output_metadata_property, + 0); + + if (!drm_mode_create_colorspace_property(connector)) + drm_object_attach_property(&connector->base, + connector->colorspace_property, + 0); + } + + drm_connector_attach_encoder(connector, encoder); + + return 0; +} + +static enum drm_mode_status +cdns_hdmi_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_mode *mode) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + enum drm_mode_status mode_status = MODE_OK; + u32 vic; + int ret; + + /* We don't support double-clocked and Interlaced modes */ + if (mode->flags & DRM_MODE_FLAG_DBLCLK || + mode->flags & DRM_MODE_FLAG_INTERLACE) + return MODE_BAD; + + /* MAX support pixel clock rate 594MHz */ + if (mode->clock > 594000) + return MODE_CLOCK_HIGH; + + /* 4096x2160 is not supported */ + if (mode->hdisplay > 3840 || mode->vdisplay > 2160) + return MODE_BAD_HVALUE; + + vic = drm_match_cea_mode(mode); + if (vic == 0) + return MODE_BAD; + + mhdp->valid_mode = mode; + ret = cdns_mhdp_plat_call(mhdp, phy_video_valid); + if (ret == false) + return MODE_CLOCK_RANGE; + + return mode_status; +} + +static void cdns_hdmi_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *orig_mode, + const struct drm_display_mode *mode) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + struct video_info *video = &mhdp->video_info; + + video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); + video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); + + DRM_INFO("Mode: %dx%dp%d\n", mode->hdisplay, mode->vdisplay, mode->clock); + memcpy(&mhdp->mode, mode, sizeof(struct drm_display_mode)); + + mutex_lock(&mhdp->lock); + cdns_hdmi_mode_set(mhdp); + mutex_unlock(&mhdp->lock); + /* reset force mode set flag */ + mhdp->force_mode_set = false; +} + +bool cdns_hdmi_bridge_mode_fixup(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + struct drm_display_info *di = &mhdp->connector.base.display_info; + struct video_info *video = &mhdp->video_info; + int vic = drm_match_cea_mode(mode); + + video->color_depth = 8; + video->color_fmt = PXL_RGB; + + /* for all other platforms, other than imx8mq */ + if (strncmp("imx8mq-hdmi", mhdp->plat_data->plat_name, 11)) { + if (di->bpc == 10 || di->bpc == 6) + video->color_depth = di->bpc; + + return true; + } + + /* imx8mq */ + if (vic == 97 || vic == 96) { + if (di->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) + video->color_depth = 12; + else if (di->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) + video->color_depth = 10; + + if (drm_mode_is_420_only(di, mode) || + (drm_mode_is_420_also(di, mode) && + video->color_depth > 8)) { + video->color_fmt = YCBCR_4_2_0; + + adjusted_mode->private_flags = 1; + return true; + } + + video->color_depth = 8; + return true; + } + + /* Any defined maximum tmds clock limit we must not exceed*/ + if ((di->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36) && + (mode->clock * 3 / 2 <= di->max_tmds_clock)) + video->color_depth = 12; + else if ((di->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && + (mode->clock * 5 / 4 <= di->max_tmds_clock)) + video->color_depth = 10; + + /* 10-bit color depth for the following modes is not supported */ + if ((vic == 95 || vic == 94 || vic == 93) && video->color_depth == 10) + video->color_depth = 8; + + return true; +} + +static const struct drm_bridge_funcs cdns_hdmi_bridge_funcs = { + .attach = cdns_hdmi_bridge_attach, + .mode_set = cdns_hdmi_bridge_mode_set, + .mode_valid = cdns_hdmi_bridge_mode_valid, + .mode_fixup = cdns_hdmi_bridge_mode_fixup, +}; + +static void hotplug_work_func(struct work_struct *work) +{ + struct cdns_mhdp_device *mhdp = container_of(work, + struct cdns_mhdp_device, hotplug_work.work); + struct drm_connector *connector = &mhdp->connector.base; + + drm_helper_hpd_irq_event(connector->dev); + + if (connector->status == connector_status_connected) { + DRM_INFO("HDMI Cable Plug In\n"); + /* force mode set to recovery weston HDMI2.0 video modes */ + mhdp->force_mode_set = true; + enable_irq(mhdp->irq[IRQ_OUT]); + } else if (connector->status == connector_status_disconnected) { + /* Cable Disconnedted */ + DRM_INFO("HDMI Cable Plug Out\n"); + enable_irq(mhdp->irq[IRQ_IN]); + } +} + +static irqreturn_t cdns_hdmi_irq_thread(int irq, void *data) +{ + struct cdns_mhdp_device *mhdp = data; + + disable_irq_nosync(irq); + + mod_delayed_work(system_wq, &mhdp->hotplug_work, + msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS)); + + return IRQ_HANDLED; +} + +static void cdns_hdmi_parse_dt(struct cdns_mhdp_device *mhdp) +{ + struct device_node *of_node = mhdp->dev->of_node; + int ret; + + ret = of_property_read_u32(of_node, "lane-mapping", &mhdp->lane_mapping); + if (ret) { + mhdp->lane_mapping = 0xc6; + dev_warn(mhdp->dev, "Failed to get lane_mapping - using default 0xc6\n"); + } + dev_info(mhdp->dev, "lane-mapping 0x%02x\n", mhdp->lane_mapping); +} + +static int __cdns_hdmi_probe(struct platform_device *pdev, + struct cdns_mhdp_device *mhdp) +{ + struct device *dev = &pdev->dev; + struct platform_device_info pdevinfo; + struct resource *iores = NULL; + int ret; + + mutex_init(&mhdp->lock); + mutex_init(&mhdp->iolock); + + INIT_DELAYED_WORK(&mhdp->hotplug_work, hotplug_work_func); + + iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mhdp->regs_base = devm_ioremap(dev, iores->start, resource_size(iores)); + if (IS_ERR(mhdp->regs_base)) { + dev_err(dev, "No regs_base memory\n"); + return -ENOMEM; + } + + /* sec register base */ + iores = platform_get_resource(pdev, IORESOURCE_MEM, 1); + mhdp->regs_sec = devm_ioremap(dev, iores->start, resource_size(iores)); + if (IS_ERR(mhdp->regs_sec)) { + dev_err(dev, "No regs_sec memory\n"); + return -ENOMEM; + } + + mhdp->irq[IRQ_IN] = platform_get_irq_byname(pdev, "plug_in"); + if (mhdp->irq[IRQ_IN] < 0) { + dev_info(dev, "No plug_in irq number\n"); + return -EPROBE_DEFER; + } + + mhdp->irq[IRQ_OUT] = platform_get_irq_byname(pdev, "plug_out"); + if (mhdp->irq[IRQ_OUT] < 0) { + dev_info(dev, "No plug_out irq number\n"); + return -EPROBE_DEFER; + } + + cdns_mhdp_plat_call(mhdp, power_on); + + /* Initialize FW */ + cdns_mhdp_plat_call(mhdp, firmware_init); + + /* HDMI FW alive check */ + ret = cdns_mhdp_check_alive(mhdp); + if (ret == false) { + dev_err(dev, "NO HDMI FW running\n"); + return -ENXIO; + } + + /* Enable Hotplug Detect thread */ + irq_set_status_flags(mhdp->irq[IRQ_IN], IRQ_NOAUTOEN); + ret = devm_request_threaded_irq(dev, mhdp->irq[IRQ_IN], + NULL, cdns_hdmi_irq_thread, + IRQF_ONESHOT, dev_name(dev), + mhdp); + if (ret < 0) { + dev_err(dev, "can't claim irq %d\n", + mhdp->irq[IRQ_IN]); + return -EINVAL; + } + + irq_set_status_flags(mhdp->irq[IRQ_OUT], IRQ_NOAUTOEN); + ret = devm_request_threaded_irq(dev, mhdp->irq[IRQ_OUT], + NULL, cdns_hdmi_irq_thread, + IRQF_ONESHOT, dev_name(dev), + mhdp); + if (ret < 0) { + dev_err(dev, "can't claim irq %d\n", + mhdp->irq[IRQ_OUT]); + return -EINVAL; + } + + cdns_hdmi_parse_dt(mhdp); + + if (cdns_mhdp_read_hpd(mhdp)) + enable_irq(mhdp->irq[IRQ_OUT]); + else + enable_irq(mhdp->irq[IRQ_IN]); + + mhdp->bridge.base.driver_private = mhdp; + mhdp->bridge.base.funcs = &cdns_hdmi_bridge_funcs; +#ifdef CONFIG_OF + mhdp->bridge.base.of_node = dev->of_node; +#endif + + memset(&pdevinfo, 0, sizeof(pdevinfo)); + pdevinfo.parent = dev; + pdevinfo.id = PLATFORM_DEVID_AUTO; + + dev_set_drvdata(dev, mhdp); + + /* register audio driver */ + cdns_mhdp_register_audio_driver(dev); + + /* register cec driver */ +#ifdef CONFIG_DRM_CDNS_HDMI_CEC + cdns_mhdp_register_cec_driver(dev); +#endif + + return 0; +} + +static void __cdns_hdmi_remove(struct cdns_mhdp_device *mhdp) +{ + /* unregister cec driver */ +#ifdef CONFIG_DRM_CDNS_HDMI_CEC + cdns_mhdp_unregister_cec_driver(mhdp->dev); +#endif + cdns_mhdp_unregister_audio_driver(mhdp->dev); +} + +/* ----------------------------------------------------------------------------- + * Probe/remove API, used from platforms based on the DRM bridge API. + */ +int cdns_hdmi_probe(struct platform_device *pdev, + struct cdns_mhdp_device *mhdp) +{ + int ret; + + ret = __cdns_hdmi_probe(pdev, mhdp); + if (ret < 0) + return ret; + + drm_bridge_add(&mhdp->bridge.base); + + return 0; +} +EXPORT_SYMBOL_GPL(cdns_hdmi_probe); + +void cdns_hdmi_remove(struct platform_device *pdev) +{ + struct cdns_mhdp_device *mhdp = platform_get_drvdata(pdev); + + drm_bridge_remove(&mhdp->bridge.base); + + __cdns_hdmi_remove(mhdp); +} +EXPORT_SYMBOL_GPL(cdns_hdmi_remove); + +/* ----------------------------------------------------------------------------- + * Bind/unbind API, used from platforms based on the component framework. + */ +int cdns_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder, + struct cdns_mhdp_device *mhdp) +{ + int ret; + + ret = __cdns_hdmi_probe(pdev, mhdp); + if (ret) + return ret; + + ret = drm_bridge_attach(encoder, &mhdp->bridge.base, NULL); + if (ret) { + cdns_hdmi_remove(pdev); + DRM_ERROR("Failed to initialize bridge with drm\n"); + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(cdns_hdmi_bind); + +void cdns_hdmi_unbind(struct device *dev) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + + __cdns_hdmi_remove(mhdp); +} +EXPORT_SYMBOL_GPL(cdns_hdmi_unbind); + +MODULE_AUTHOR("Sandor Yu "); +MODULE_DESCRIPTION("Cadence HDMI transmitter driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:cdn-hdmi"); diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c new file mode 100644 index 00000000000000..716806c75cfac0 --- /dev/null +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c @@ -0,0 +1,411 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd + * Author: Chris Zhong + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include + +#define CDNS_DP_SPDIF_CLK 200000000 + +static u32 TMDS_rate_table[7] = { + 25200, 27000, 54000, 74250, 148500, 297000, 594000, +}; + +static u32 N_table_32k[7] = { +/* 25200/27000/54000/74250/148500/297000/594000 */ + 4096, 4096, 4096, 4096, 4096, 3072, 3072, +}; + +static u32 N_table_44k[7] = { + 6272, 6272, 6272, 6272, 6272, 4704, 9408, +}; + +static u32 N_table_48k[7] = { + 6144, 6144, 6144, 6144, 6144, 5120, 6144, +}; + +static int select_N_index(u32 pclk) +{ + int num = sizeof(TMDS_rate_table)/sizeof(int); + int i = 0; + + for (i = 0; i < num ; i++) + if (pclk == TMDS_rate_table[i]) + break; + + if (i == num) { + DRM_WARN("pclkc %d is not supported!\n", pclk); + return num-1; + } + + return i; +} + +static void hdmi_audio_avi_set(struct cdns_mhdp_device *mhdp, + u32 channels) +{ + struct hdmi_audio_infoframe frame; + u8 buf[32]; + int ret; + + hdmi_audio_infoframe_init(&frame); + + frame.channels = channels; + frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; + + if (channels == 2) + frame.channel_allocation = 0; + else if (channels == 4) + frame.channel_allocation = 0x3; + else if (channels == 6) + frame.channel_allocation = 0xB; + else if (channels == 8) + frame.channel_allocation = 0x13; + + ret = hdmi_audio_infoframe_pack(&frame, buf + 1, sizeof(buf) - 1); + if (ret < 0) { + DRM_ERROR("failed to pack audio infoframe: %d\n", ret); + return; + } + + buf[0] = 0; + + cdns_mhdp_infoframe_set(mhdp, 1, sizeof(buf), buf, HDMI_INFOFRAME_TYPE_AUDIO); +} + +int cdns_mhdp_audio_stop(struct cdns_mhdp_device *mhdp, + struct audio_info *audio) +{ + int ret; + + if (audio->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { + ret = cdns_mhdp_reg_write(mhdp, AUDIO_PACK_CONTROL, 0); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "audio stop failed: %d\n", ret); + return ret; + } + } + + cdns_mhdp_bus_write(0, mhdp, SPDIF_CTRL_ADDR); + + /* clearn the audio config and reset */ + cdns_mhdp_bus_write(0, mhdp, AUDIO_SRC_CNTL); + cdns_mhdp_bus_write(0, mhdp, AUDIO_SRC_CNFG); + cdns_mhdp_bus_write(AUDIO_SW_RST, mhdp, AUDIO_SRC_CNTL); + cdns_mhdp_bus_write(0, mhdp, AUDIO_SRC_CNTL); + + /* reset smpl2pckt component */ + cdns_mhdp_bus_write(0, mhdp, SMPL2PKT_CNTL); + cdns_mhdp_bus_write(AUDIO_SW_RST, mhdp, SMPL2PKT_CNTL); + cdns_mhdp_bus_write(0, mhdp, SMPL2PKT_CNTL); + + /* reset FIFO */ + cdns_mhdp_bus_write(AUDIO_SW_RST, mhdp, FIFO_CNTL); + cdns_mhdp_bus_write(0, mhdp, FIFO_CNTL); + + if (audio->format == AFMT_SPDIF_INT) + clk_disable_unprepare(mhdp->spdif_clk); + + return 0; +} +EXPORT_SYMBOL(cdns_mhdp_audio_stop); + +int cdns_mhdp_audio_mute(struct cdns_mhdp_device *mhdp, bool enable) +{ + struct audio_info *audio = &mhdp->audio_info; + int ret = true; + + if (audio->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { + ret = cdns_mhdp_reg_write_bit(mhdp, DP_VB_ID, 4, 1, enable); + if (ret) + DRM_DEV_ERROR(mhdp->dev, "audio mute failed: %d\n", ret); + } + + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_audio_mute); + +static void cdns_mhdp_audio_config_i2s(struct cdns_mhdp_device *mhdp, + struct audio_info *audio) +{ + int sub_pckt_num = 1, i2s_port_en_val = 0xf, i; + int idx = select_N_index(mhdp->mode.clock); + int numofchannels = audio->channels; + u32 val, ncts; + u32 disable_port3 = 0; + u32 audio_type = 0x2; /* L-PCM */ + u32 transmission_type = 0; /* not required for L-PCM */ + + if (numofchannels == 2) { + if (mhdp->dp.link.num_lanes == 1) + sub_pckt_num = 2; + else + sub_pckt_num = 4; + + i2s_port_en_val = 1; + } else if (numofchannels == 4) { + i2s_port_en_val = 3; + } else if (numofchannels == 6) { + numofchannels = 8; + disable_port3 = 1; + } else if ((numofchannels == 8) && (audio->non_pcm)) { + audio_type = 0x9; /* HBR packet type */ + transmission_type = 0x9; /* HBR packet type */ + } + + cdns_mhdp_bus_write(0x0, mhdp, SPDIF_CTRL_ADDR); + + val = SYNC_WR_TO_CH_ZERO; + val |= disable_port3 << 4; + cdns_mhdp_bus_write(val, mhdp, FIFO_CNTL); + + val = MAX_NUM_CH(numofchannels); + val |= NUM_OF_I2S_PORTS(numofchannels); + val |= audio_type << 7; + val |= CFG_SUB_PCKT_NUM(sub_pckt_num); + cdns_mhdp_bus_write(val, mhdp, SMPL2PKT_CNFG); + + if (audio->sample_width == 16) + val = 0; + else if (audio->sample_width == 24) + val = 1 << 9; + else + val = 2 << 9; + + val |= AUDIO_CH_NUM(numofchannels); + val |= I2S_DEC_PORT_EN(i2s_port_en_val); + val |= TRANS_SMPL_WIDTH_32; + val |= transmission_type << 13; + cdns_mhdp_bus_write(val, mhdp, AUDIO_SRC_CNFG); + + for (i = 0; i < (numofchannels + 1) / 2; i++) { + if (audio->sample_width == 16) + val = (0x02 << 8) | (0x02 << 20); + else if (audio->sample_width == 24) + val = (0x0b << 8) | (0x0b << 20); + + val |= ((2 * i) << 4) | ((2 * i + 1) << 16); + cdns_mhdp_bus_write(val, mhdp, STTS_BIT_CH(i)); + } + + switch (audio->sample_rate) { + case 32000: + val = SAMPLING_FREQ(3) | + ORIGINAL_SAMP_FREQ(0xc); + ncts = N_table_32k[idx]; + break; + case 44100: + val = SAMPLING_FREQ(0) | + ORIGINAL_SAMP_FREQ(0xf); + ncts = N_table_44k[idx]; + break; + case 48000: + val = SAMPLING_FREQ(2) | + ORIGINAL_SAMP_FREQ(0xd); + ncts = N_table_48k[idx]; + break; + case 88200: + val = SAMPLING_FREQ(8) | + ORIGINAL_SAMP_FREQ(0x7); + ncts = N_table_44k[idx] * 2; + break; + case 96000: + val = SAMPLING_FREQ(0xa) | + ORIGINAL_SAMP_FREQ(5); + ncts = N_table_48k[idx] * 2; + break; + case 176400: + val = SAMPLING_FREQ(0xc) | + ORIGINAL_SAMP_FREQ(3); + ncts = N_table_44k[idx] * 4; + break; + case 192000: + default: + val = SAMPLING_FREQ(0xe) | + ORIGINAL_SAMP_FREQ(1); + ncts = N_table_48k[idx] * 4; + break; + } + val |= 4; + cdns_mhdp_bus_write(val, mhdp, COM_CH_STTS_BITS); + + if (audio->connector_type == DRM_MODE_CONNECTOR_HDMIA) + cdns_mhdp_reg_write(mhdp, CM_I2S_CTRL, ncts | 0x4000000); + + cdns_mhdp_bus_write(SMPL2PKT_EN, mhdp, SMPL2PKT_CNTL); + cdns_mhdp_bus_write(I2S_DEC_START, mhdp, AUDIO_SRC_CNTL); +} + +static void cdns_mhdp_audio_config_spdif(struct cdns_mhdp_device *mhdp) +{ + u32 val; + + cdns_mhdp_bus_write(SYNC_WR_TO_CH_ZERO, mhdp, FIFO_CNTL); + + val = MAX_NUM_CH(2) | AUDIO_TYPE_LPCM | CFG_SUB_PCKT_NUM(4); + cdns_mhdp_bus_write(val, mhdp, SMPL2PKT_CNFG); + cdns_mhdp_bus_write(SMPL2PKT_EN, mhdp, SMPL2PKT_CNTL); + + val = SPDIF_ENABLE | SPDIF_AVG_SEL | SPDIF_JITTER_BYPASS; + cdns_mhdp_bus_write(val, mhdp, SPDIF_CTRL_ADDR); + + clk_prepare_enable(mhdp->spdif_clk); + clk_set_rate(mhdp->spdif_clk, CDNS_DP_SPDIF_CLK); +} + +int cdns_mhdp_audio_config(struct cdns_mhdp_device *mhdp, + struct audio_info *audio) +{ + int ret; + + /* reset the spdif clk before config */ + if (audio->format == AFMT_SPDIF_INT) { + reset_control_assert(mhdp->spdif_rst); + reset_control_deassert(mhdp->spdif_rst); + } + + if (audio->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { + ret = cdns_mhdp_reg_write(mhdp, CM_LANE_CTRL, LANE_REF_CYC); + if (ret) + goto err_audio_config; + + ret = cdns_mhdp_reg_write(mhdp, CM_CTRL, 0); + if (ret) + goto err_audio_config; + } else { + /* HDMI Mode */ + ret = cdns_mhdp_reg_write(mhdp, CM_CTRL, 8); + if (ret) + goto err_audio_config; + } + + if (audio->format == AFMT_I2S) + cdns_mhdp_audio_config_i2s(mhdp, audio); + else if (audio->format == AFMT_SPDIF_INT) + cdns_mhdp_audio_config_spdif(mhdp); + + if (audio->connector_type == DRM_MODE_CONNECTOR_DisplayPort) + ret = cdns_mhdp_reg_write(mhdp, AUDIO_PACK_CONTROL, AUDIO_PACK_EN); + + if (audio->connector_type == DRM_MODE_CONNECTOR_HDMIA) + hdmi_audio_avi_set(mhdp, audio->channels); + +err_audio_config: + if (ret) + DRM_DEV_ERROR(mhdp->dev, "audio config failed: %d\n", ret); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_audio_config); + +static int audio_hw_params(struct device *dev, void *data, + struct hdmi_codec_daifmt *daifmt, + struct hdmi_codec_params *params) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + struct audio_info audio = { + .sample_width = params->sample_width, + .sample_rate = params->sample_rate, + .channels = params->channels, + .connector_type = mhdp->connector.base.connector_type, + }; + int ret; + + switch (daifmt->fmt) { + case HDMI_I2S: + audio.format = AFMT_I2S; + break; + case HDMI_SPDIF: + audio.format = AFMT_SPDIF_EXT; + break; + default: + DRM_DEV_ERROR(dev, "Invalid format %d\n", daifmt->fmt); + ret = -EINVAL; + goto out; + } + + audio.non_pcm = params->iec.status[0] & IEC958_AES0_NONAUDIO; + + ret = cdns_mhdp_audio_config(mhdp, &audio); + if (!ret) + mhdp->audio_info = audio; + +out: + return ret; +} + +static void audio_shutdown(struct device *dev, void *data) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + int ret; + + ret = cdns_mhdp_audio_stop(mhdp, &mhdp->audio_info); + if (!ret) + mhdp->audio_info.format = AFMT_UNUSED; +} + +static int audio_digital_mute(struct device *dev, void *data, + bool enable) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + int ret; + + ret = cdns_mhdp_audio_mute(mhdp, enable); + + return ret; +} + +static int audio_get_eld(struct device *dev, void *data, + u8 *buf, size_t len) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + + memcpy(buf, mhdp->connector.base.eld, + min(sizeof(mhdp->connector.base.eld), len)); + + return 0; +} + +static const struct hdmi_codec_ops audio_codec_ops = { + .hw_params = audio_hw_params, + .audio_shutdown = audio_shutdown, + .digital_mute = audio_digital_mute, + .get_eld = audio_get_eld, +}; + +int cdns_mhdp_register_audio_driver(struct device *dev) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + struct hdmi_codec_pdata codec_data = { + .i2s = 1, + .spdif = 1, + .ops = &audio_codec_ops, + .max_i2s_channels = 8, + }; + + mhdp->audio_pdev = platform_device_register_data( + dev, HDMI_CODEC_DRV_NAME, 1, + &codec_data, sizeof(codec_data)); + + return PTR_ERR_OR_ZERO(mhdp->audio_pdev); +} + +void cdns_mhdp_unregister_audio_driver(struct device *dev) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + + platform_device_unregister(mhdp->audio_pdev); +} diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c new file mode 100644 index 00000000000000..af8506444f6e3c --- /dev/null +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c @@ -0,0 +1,341 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include + +#define CEC_NAME "cdns-mhdp-cec" + +#define REG_ADDR_OFF 4 + +/* regsiter define */ +#define TX_MSG_HEADER 0x33800 +#define TX_MSG_LENGTH 0x33840 +#define TX_MSG_CMD 0x33844 +#define RX_MSG_CMD 0x33850 +#define RX_CLEAR_BUF 0x33854 +#define LOGICAL_ADDRESS_LA0 0x33858 + +#define CLK_DIV_MSB 0x3386c +#define CLK_DIV_LSB 0x33870 +#define RX_MSG_DATA1 0x33900 +#define RX_MSG_LENGTH 0x33940 +#define RX_MSG_STATUS 0x33944 +#define NUM_OF_MSG_RX_BUF 0x33948 +#define TX_MSG_STATUS 0x3394c +#define DB_L_TIMER 0x33980 + +/** + * CEC Transceiver operation. + */ +enum { + CEC_TX_STOP, + CEC_TX_TRANSMIT, + CEC_TX_ABORT, + CEC_TX_ABORT_AND_TRANSMIT +}; + +/** + * CEC Transceiver status. + */ +enum { + CEC_STS_IDLE, + CEC_STS_BUSY, + CEC_STS_SUCCESS, + CEC_STS_ERROR +}; + +/** + * CEC Receiver operation. + */ +enum { + CEC_RX_STOP, + CEC_RX_READ, + CEC_RX_DISABLE, + CEC_RX_ABORT_AND_CLR_FIFO +}; +/** + * Maximum number of Messages in the RX Buffers. + */ +#define CEC_MAX_RX_MSGS 2 + +static u32 mhdp_cec_read(struct cdns_mhdp_cec *cec, u32 offset) +{ + struct cdns_mhdp_device *mhdp = + container_of(cec, struct cdns_mhdp_device, hdmi.cec); + return cdns_mhdp_bus_read(mhdp, offset); +} + +static void mhdp_cec_write(struct cdns_mhdp_cec *cec, u32 offset, u32 val) +{ + struct cdns_mhdp_device *mhdp = + container_of(cec, struct cdns_mhdp_device, hdmi.cec); + cdns_mhdp_bus_write(val, mhdp, offset); +} + +static void mhdp_cec_clear_rx_buffer(struct cdns_mhdp_cec *cec) +{ + mhdp_cec_write(cec, RX_CLEAR_BUF, 1); + mhdp_cec_write(cec, RX_CLEAR_BUF, 0); +} + +static void mhdp_cec_set_divider(struct cdns_mhdp_cec *cec) +{ + struct cdns_mhdp_device *mhdp = + container_of(cec, struct cdns_mhdp_device, hdmi.cec); + u32 clk_div; + + /* Set clock divider */ + clk_div = cdns_mhdp_get_fw_clk(mhdp) * 10; + + mhdp_cec_write(cec, CLK_DIV_MSB, + (clk_div >> 8) & 0xFF); + mhdp_cec_write(cec, CLK_DIV_LSB, clk_div & 0xFF); +} + +static u32 mhdp_cec_read_message(struct cdns_mhdp_cec *cec) +{ + struct cec_msg *msg = &cec->msg; + int len; + int i; + + mhdp_cec_write(cec, RX_MSG_CMD, CEC_RX_READ); + + len = mhdp_cec_read(cec, RX_MSG_LENGTH); + msg->len = len + 1; + dev_dbg(cec->dev, "RX MSG len =%d\n", len); + + /* Read RX MSG bytes */ + for (i = 0; i < msg->len; ++i) { + msg->msg[i] = (u8) mhdp_cec_read(cec, RX_MSG_DATA1 + (i * REG_ADDR_OFF)); + dev_dbg(cec->dev, "RX MSG[%d]=0x%x\n", i, msg->msg[i]); + } + + mhdp_cec_write(cec, RX_MSG_CMD, CEC_RX_STOP); + + return true; +} + +static u32 mhdp_cec_write_message(struct cdns_mhdp_cec *cec, struct cec_msg *msg) +{ + u8 i; + + mhdp_cec_write(cec, TX_MSG_CMD, CEC_TX_STOP); + + if (msg->len > CEC_MAX_MSG_SIZE) { + dev_err(cec->dev, "Invalid MSG size!\n"); + return -EINVAL; + } + + for (i = 0; i < msg->len; ++i) + printk("msg[%d]=0x%x\n",i, msg->msg[i]); + + /* Write Message to register */ + for (i = 0; i < msg->len; ++i) { + mhdp_cec_write(cec, TX_MSG_HEADER + (i * REG_ADDR_OFF), + msg->msg[i]); + } + /* Write Message Length (payload + opcode) */ + mhdp_cec_write(cec, TX_MSG_LENGTH, msg->len - 1); + + mhdp_cec_write(cec, TX_MSG_CMD, CEC_TX_TRANSMIT); + + return true; +} + +static int mhdp_cec_set_logical_addr(struct cdns_mhdp_cec *cec, u32 la) +{ + u8 la_reg; + u8 i; + + if (la == CEC_LOG_ADDR_INVALID) + /* invalid all LA address */ + for (i = 0; i < CEC_MAX_LOG_ADDRS; ++i) { + mhdp_cec_write(cec, LOGICAL_ADDRESS_LA0 + (i * REG_ADDR_OFF), 0); + return 0; + } + + /* In fact cdns mhdp cec could support max 5 La address */ + for (i = 0; i < CEC_MAX_LOG_ADDRS; ++i) { + la_reg = mhdp_cec_read(cec, LOGICAL_ADDRESS_LA0 + (i * REG_ADDR_OFF)); + /* Check LA already used */ + if (la_reg & 0x10) + continue; + + if ((la_reg & 0xF) == la) { + dev_warn(cec->dev, "Warning. LA already in use.\n"); + return 0; + } + + la = (la & 0xF) | (1 << 4); + + mhdp_cec_write(cec, LOGICAL_ADDRESS_LA0 + (i * REG_ADDR_OFF), la); + return 0; + } + + dev_warn(cec->dev, "All LA in use\n"); + + return -ENXIO; +} + +static int mhdp_cec_poll_worker(void *_cec) +{ + struct cdns_mhdp_cec *cec = (struct cdns_mhdp_cec *)_cec; + int num_rx_msgs, i; + int sts; + + set_freezable(); + + for (;;) { + if (kthread_freezable_should_stop(NULL)) + break; + + /* Check TX State */ + sts = mhdp_cec_read(cec, TX_MSG_STATUS); + switch (sts) { + case CEC_STS_SUCCESS: + cec_transmit_done(cec->adap, CEC_TX_STATUS_OK, 0, 0, 0, + 0); + mhdp_cec_write(cec, TX_MSG_CMD, CEC_TX_STOP); + break; + case CEC_STS_ERROR: + mhdp_cec_write(cec, TX_MSG_CMD, CEC_TX_STOP); + cec_transmit_done(cec->adap, + CEC_TX_STATUS_MAX_RETRIES | + CEC_TX_STATUS_NACK, 0, 1, 0, 0); + break; + case CEC_STS_BUSY: + default: + break; + } + + /* Check RX State */ + sts = mhdp_cec_read(cec, RX_MSG_STATUS); + num_rx_msgs = mhdp_cec_read(cec, NUM_OF_MSG_RX_BUF); + switch (sts) { + case CEC_STS_SUCCESS: + if (num_rx_msgs == 0xf) + num_rx_msgs = CEC_MAX_RX_MSGS; + + if (num_rx_msgs > CEC_MAX_RX_MSGS) { + dev_err(cec->dev, "Error rx msg num %d\n", + num_rx_msgs); + mhdp_cec_clear_rx_buffer(cec); + break; + } + + /* Rx FIFO Depth 2 RX MSG */ + for (i = 0; i < num_rx_msgs; i++) { + mhdp_cec_read_message(cec); + cec->msg.rx_status = CEC_RX_STATUS_OK; + cec_received_msg(cec->adap, &cec->msg); + } + break; + default: + break; + } + + if (!kthread_should_stop()) + schedule_timeout_idle(20); + } + + return 0; +} + +static int mhdp_cec_adap_enable(struct cec_adapter *adap, bool enable) +{ + struct cdns_mhdp_cec *cec = cec_get_drvdata(adap); + + if (enable) { + mhdp_cec_write(cec, DB_L_TIMER, 0x10); + mhdp_cec_set_divider(cec); + } else + mhdp_cec_set_divider(cec); + + return 0; +} + +static int mhdp_cec_adap_log_addr(struct cec_adapter *adap, u8 addr) +{ + struct cdns_mhdp_cec *cec = cec_get_drvdata(adap); + + return mhdp_cec_set_logical_addr(cec, addr); +} + +static int mhdp_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, + u32 signal_free_time, struct cec_msg *msg) +{ + struct cdns_mhdp_cec *cec = cec_get_drvdata(adap); + + mhdp_cec_write_message(cec, msg); + + return 0; +} + +static const struct cec_adap_ops cdns_mhdp_cec_adap_ops = { + .adap_enable = mhdp_cec_adap_enable, + .adap_log_addr = mhdp_cec_adap_log_addr, + .adap_transmit = mhdp_cec_adap_transmit, +}; + +int cdns_mhdp_register_cec_driver(struct device *dev) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + struct cdns_mhdp_cec *cec = &mhdp->hdmi.cec; + int ret; + + cec->adap = cec_allocate_adapter(&cdns_mhdp_cec_adap_ops, cec, + CEC_NAME, + CEC_CAP_PHYS_ADDR | CEC_CAP_LOG_ADDRS | + CEC_CAP_TRANSMIT | CEC_CAP_PASSTHROUGH + | CEC_CAP_RC, CEC_MAX_LOG_ADDRS); + ret = PTR_ERR_OR_ZERO(cec->adap); + if (ret) + return ret; + ret = cec_register_adapter(cec->adap, dev); + if (ret) { + cec_delete_adapter(cec->adap); + return ret; + } + + cec->dev = dev; + + cec->cec_worker = kthread_create(mhdp_cec_poll_worker, cec, "cdns-mhdp-cec"); + if (IS_ERR(cec->cec_worker)) + dev_err(cec->dev, "failed create hdp cec thread\n"); + + wake_up_process(cec->cec_worker); + + dev_dbg(dev, "CEC successfuly probed\n"); + return 0; +} + +int cdns_mhdp_unregister_cec_driver(struct device *dev) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + struct cdns_mhdp_cec *cec = &mhdp->hdmi.cec; + + if (cec->cec_worker) { + kthread_stop(cec->cec_worker); + cec->cec_worker = NULL; + } + cec_unregister_adapter(cec->adap); + return 0; +} + +MODULE_AUTHOR("Sandor.Yu@NXP.com"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("NXP CDNS MHDP HDMI CEC driver"); diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c new file mode 100644 index 00000000000000..e286044a906085 --- /dev/null +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c @@ -0,0 +1,1056 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd + * Author: Chris Zhong + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#define CDNS_DP_SPDIF_CLK 200000000 +#define FW_ALIVE_TIMEOUT_US 1000000 +#define MAILBOX_RETRY_US 1000 +#define MAILBOX_TIMEOUT_US 5000000 +#define LINK_TRAINING_RETRY_MS 20 +#define LINK_TRAINING_TIMEOUT_MS 500 + +#define mhdp_readx_poll_timeout(op, addr, offset, val, cond, sleep_us, timeout_us) \ +({ \ + u64 __timeout_us = (timeout_us); \ + unsigned long __sleep_us = (sleep_us); \ + ktime_t __timeout = ktime_add_us(ktime_get(), __timeout_us); \ + might_sleep_if((__sleep_us) != 0); \ + for (;;) { \ + (val) = op(addr, offset); \ + if (cond) \ + break; \ + if (__timeout_us && \ + ktime_compare(ktime_get(), __timeout) > 0) { \ + (val) = op(addr, offset); \ + break; \ + } \ + if (__sleep_us) \ + usleep_range((__sleep_us >> 2) + 1, __sleep_us); \ + } \ + (cond) ? 0 : -ETIMEDOUT; \ +}) + +static inline u32 get_unaligned_be24(const void *p) +{ + const u8 *_p = p; + + return _p[0] << 16 | _p[1] << 8 | _p[2]; +} + +static inline void put_unaligned_be24(u32 val, void *p) +{ + u8 *_p = p; + + _p[0] = val >> 16; + _p[1] = val >> 8; + _p[2] = val; +} + +u32 cdns_mhdp_bus_read(struct cdns_mhdp_device *mhdp, u32 offset) +{ + u32 val; + + mutex_lock(&mhdp->iolock); + + if (mhdp->bus_type == BUS_TYPE_LOW4K_SAPB) { + /* Remap address to low 4K SAPB bus */ + writel(offset >> 12, mhdp->regs_sec + 0xc); + val = readl((offset & 0xfff) + mhdp->regs_base); + } else if (mhdp->bus_type == BUS_TYPE_LOW4K_APB) { + /* Remap address to low 4K memory */ + writel(offset >> 12, mhdp->regs_sec + 8); + val = readl((offset & 0xfff) + mhdp->regs_base); + } else if (mhdp->bus_type == BUS_TYPE_NORMAL_SAPB) + val = readl(mhdp->regs_sec + offset); + else + val = readl(mhdp->regs_base + offset); + + mutex_unlock(&mhdp->iolock); + + return val; +} +EXPORT_SYMBOL(cdns_mhdp_bus_read); + +void cdns_mhdp_bus_write(u32 val, struct cdns_mhdp_device *mhdp, u32 offset) +{ + mutex_lock(&mhdp->iolock); + + if (mhdp->bus_type == BUS_TYPE_LOW4K_SAPB) { + /* Remap address to low 4K SAPB bus */ + writel(offset >> 12, mhdp->regs_sec + 0xc); + writel(val, (offset & 0xfff) + mhdp->regs_base); + } else if (mhdp->bus_type == BUS_TYPE_LOW4K_APB) { + /* Remap address to low 4K memory */ + writel(offset >> 12, mhdp->regs_sec + 8); + writel(val, (offset & 0xfff) + mhdp->regs_base); + } else if (mhdp->bus_type == BUS_TYPE_NORMAL_SAPB) + writel(val, mhdp->regs_sec + offset); + else + writel(val, mhdp->regs_base + offset); + + mutex_unlock(&mhdp->iolock); +} +EXPORT_SYMBOL(cdns_mhdp_bus_write); + +u32 cdns_mhdp_get_fw_clk(struct cdns_mhdp_device *mhdp) +{ + return cdns_mhdp_bus_read(mhdp, SW_CLK_H); +} +EXPORT_SYMBOL(cdns_mhdp_get_fw_clk); + +void cdns_mhdp_set_fw_clk(struct cdns_mhdp_device *mhdp, unsigned long clk) +{ + cdns_mhdp_bus_write(clk / 1000000, mhdp, SW_CLK_H); +} +EXPORT_SYMBOL(cdns_mhdp_set_fw_clk); + +void cdns_mhdp_clock_reset(struct cdns_mhdp_device *mhdp) +{ + u32 val; + + val = DPTX_FRMR_DATA_CLK_RSTN_EN | + DPTX_FRMR_DATA_CLK_EN | + DPTX_PHY_DATA_RSTN_EN | + DPTX_PHY_DATA_CLK_EN | + DPTX_PHY_CHAR_RSTN_EN | + DPTX_PHY_CHAR_CLK_EN | + SOURCE_AUX_SYS_CLK_RSTN_EN | + SOURCE_AUX_SYS_CLK_EN | + DPTX_SYS_CLK_RSTN_EN | + DPTX_SYS_CLK_EN | + CFG_DPTX_VIF_CLK_RSTN_EN | + CFG_DPTX_VIF_CLK_EN; + cdns_mhdp_bus_write(val, mhdp, SOURCE_DPTX_CAR); + + val = SOURCE_PHY_RSTN_EN | SOURCE_PHY_CLK_EN; + cdns_mhdp_bus_write(val, mhdp, SOURCE_PHY_CAR); + + val = SOURCE_PKT_SYS_RSTN_EN | + SOURCE_PKT_SYS_CLK_EN | + SOURCE_PKT_DATA_RSTN_EN | + SOURCE_PKT_DATA_CLK_EN; + cdns_mhdp_bus_write(val, mhdp, SOURCE_PKT_CAR); + + val = SPDIF_CDR_CLK_RSTN_EN | + SPDIF_CDR_CLK_EN | + SOURCE_AIF_SYS_RSTN_EN | + SOURCE_AIF_SYS_CLK_EN | + SOURCE_AIF_CLK_RSTN_EN | + SOURCE_AIF_CLK_EN; + cdns_mhdp_bus_write(val, mhdp, SOURCE_AIF_CAR); + + val = SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN | + SOURCE_CIPHER_SYS_CLK_EN | + SOURCE_CIPHER_CHAR_CLK_RSTN_EN | + SOURCE_CIPHER_CHAR_CLK_EN; + cdns_mhdp_bus_write(val, mhdp, SOURCE_CIPHER_CAR); + + val = SOURCE_CRYPTO_SYS_CLK_RSTN_EN | + SOURCE_CRYPTO_SYS_CLK_EN; + cdns_mhdp_bus_write(val, mhdp, SOURCE_CRYPTO_CAR); + + /* enable Mailbox and PIF interrupt */ + cdns_mhdp_bus_write(0, mhdp, APB_INT_MASK); +} +EXPORT_SYMBOL(cdns_mhdp_clock_reset); + +int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp) +{ + int val, ret; + + ret = mhdp_readx_poll_timeout(cdns_mhdp_bus_read, mhdp, MAILBOX_EMPTY_ADDR, + val, !val, MAILBOX_RETRY_US, + MAILBOX_TIMEOUT_US); + if (ret < 0) + return ret; + + return cdns_mhdp_bus_read(mhdp, MAILBOX0_RD_DATA) & 0xff; +} +EXPORT_SYMBOL(cdns_mhdp_mailbox_read); + +static int cdp_dp_mailbox_write(struct cdns_mhdp_device *mhdp, u8 val) +{ + int ret, full; + + ret = mhdp_readx_poll_timeout(cdns_mhdp_bus_read, mhdp, MAILBOX_FULL_ADDR, + full, !full, MAILBOX_RETRY_US, + MAILBOX_TIMEOUT_US); + if (ret < 0) + return ret; + + cdns_mhdp_bus_write(val, mhdp, MAILBOX0_WR_DATA); + + return 0; +} + +int cdns_mhdp_mailbox_validate_receive(struct cdns_mhdp_device *mhdp, + u8 module_id, u8 opcode, + u16 req_size) +{ + u32 mbox_size, i; + u8 header[4]; + int ret; + + /* read the header of the message */ + for (i = 0; i < 4; i++) { + ret = cdns_mhdp_mailbox_read(mhdp); + if (ret < 0) + return ret; + + header[i] = ret; + } + + mbox_size = get_unaligned_be16(header + 2); + + if (opcode != header[0] || module_id != header[1] || + req_size != mbox_size) { + /* + * If the message in mailbox is not what we want, we need to + * clear the mailbox by reading its contents. + */ + for (i = 0; i < mbox_size; i++) + if (cdns_mhdp_mailbox_read(mhdp) < 0) + break; + + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL(cdns_mhdp_mailbox_validate_receive); + +int cdns_mhdp_mailbox_read_receive(struct cdns_mhdp_device *mhdp, + u8 *buff, u16 buff_size) +{ + u32 i; + int ret; + + for (i = 0; i < buff_size; i++) { + ret = cdns_mhdp_mailbox_read(mhdp); + if (ret < 0) + return ret; + + buff[i] = ret; + } + + return 0; +} +EXPORT_SYMBOL(cdns_mhdp_mailbox_read_receive); + +int cdns_mhdp_mailbox_send(struct cdns_mhdp_device *mhdp, u8 module_id, + u8 opcode, u16 size, u8 *message) +{ + u8 header[4]; + int ret, i; + + header[0] = opcode; + header[1] = module_id; + put_unaligned_be16(size, header + 2); + + for (i = 0; i < 4; i++) { + ret = cdp_dp_mailbox_write(mhdp, header[i]); + if (ret) + return ret; + } + + for (i = 0; i < size; i++) { + ret = cdp_dp_mailbox_write(mhdp, message[i]); + if (ret) + return ret; + } + + return 0; +} +EXPORT_SYMBOL(cdns_mhdp_mailbox_send); + +int cdns_mhdp_reg_read(struct cdns_mhdp_device *mhdp, u32 addr) +{ + u8 msg[4], resp[8]; + u32 val; + int ret; + + if (addr == 0) { + ret = -EINVAL; + goto err_reg_read; + } + + put_unaligned_be32(addr, msg); + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL, + GENERAL_READ_REGISTER, + sizeof(msg), msg); + if (ret) + goto err_reg_read; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_GENERAL, + GENERAL_READ_REGISTER, + sizeof(resp)); + if (ret) + goto err_reg_read; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, resp, sizeof(resp)); + if (ret) + goto err_reg_read; + + /* Returned address value should be the same as requested */ + if (memcmp(msg, resp, sizeof(msg))) { + ret = -EINVAL; + goto err_reg_read; + } + + val = get_unaligned_be32(resp + 4); + + return val; +err_reg_read: + DRM_DEV_ERROR(mhdp->dev, "Failed to read register.\n"); + + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_reg_read); + +int cdns_mhdp_reg_write(struct cdns_mhdp_device *mhdp, u32 addr, u32 val) +{ + u8 msg[8]; + + put_unaligned_be32(addr, msg); + put_unaligned_be32(val, msg + 4); + + return cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL, + GENERAL_WRITE_REGISTER, sizeof(msg), msg); +} +EXPORT_SYMBOL(cdns_mhdp_reg_write); + +int cdns_mhdp_reg_write_bit(struct cdns_mhdp_device *mhdp, u16 addr, + u8 start_bit, u8 bits_no, u32 val) +{ + u8 field[8]; + + put_unaligned_be16(addr, field); + field[2] = start_bit; + field[3] = bits_no; + put_unaligned_be32(val, field + 4); + + return cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_WRITE_FIELD, sizeof(field), field); +} +EXPORT_SYMBOL(cdns_mhdp_reg_write_bit); + +int cdns_mhdp_dpcd_read(struct cdns_mhdp_device *mhdp, + u32 addr, u8 *data, u16 len) +{ + u8 msg[5], reg[5]; + int ret; + + put_unaligned_be16(len, msg); + put_unaligned_be24(addr, msg + 2); + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_READ_DPCD, sizeof(msg), msg); + if (ret) + goto err_dpcd_read; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, + DPTX_READ_DPCD, + sizeof(reg) + len); + if (ret) + goto err_dpcd_read; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); + if (ret) + goto err_dpcd_read; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, data, len); + +err_dpcd_read: + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_dpcd_read); + +int cdns_mhdp_dpcd_write(struct cdns_mhdp_device *mhdp, u32 addr, u8 value) +{ + u8 msg[6], reg[5]; + int ret; + + put_unaligned_be16(1, msg); + put_unaligned_be24(addr, msg + 2); + msg[5] = value; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_WRITE_DPCD, sizeof(msg), msg); + if (ret) + goto err_dpcd_write; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, + DPTX_WRITE_DPCD, sizeof(reg)); + if (ret) + goto err_dpcd_write; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); + if (ret) + goto err_dpcd_write; + + if (addr != get_unaligned_be24(reg + 2)) + ret = -EINVAL; + +err_dpcd_write: + if (ret) + DRM_DEV_ERROR(mhdp->dev, "dpcd write failed: %d\n", ret); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_dpcd_write); + +int cdns_mhdp_load_firmware(struct cdns_mhdp_device *mhdp, const u32 *i_mem, + u32 i_size, const u32 *d_mem, u32 d_size) +{ + u32 reg; + int i, ret; + + /* reset ucpu before load firmware*/ + cdns_mhdp_bus_write(APB_IRAM_PATH | APB_DRAM_PATH | APB_XT_RESET, + mhdp, APB_CTRL); + + for (i = 0; i < i_size; i += 4) + cdns_mhdp_bus_write(*i_mem++, mhdp, ADDR_IMEM + i); + + for (i = 0; i < d_size; i += 4) + cdns_mhdp_bus_write(*d_mem++, mhdp, ADDR_DMEM + i); + + /* un-reset ucpu */ + cdns_mhdp_bus_write(0, mhdp, APB_CTRL); + + /* check the keep alive register to make sure fw working */ + ret = mhdp_readx_poll_timeout(cdns_mhdp_bus_read, mhdp, KEEP_ALIVE, + reg, reg, 2000, FW_ALIVE_TIMEOUT_US); + if (ret < 0) { + DRM_DEV_ERROR(mhdp->dev, "failed to loaded the FW reg = %x\n", + reg); + return -EINVAL; + } + + reg = cdns_mhdp_bus_read(mhdp, VER_L) & 0xff; + mhdp->fw_version = reg; + reg = cdns_mhdp_bus_read(mhdp, VER_H) & 0xff; + mhdp->fw_version |= reg << 8; + reg = cdns_mhdp_bus_read(mhdp, VER_LIB_L_ADDR) & 0xff; + mhdp->fw_version |= reg << 16; + reg = cdns_mhdp_bus_read(mhdp, VER_LIB_H_ADDR) & 0xff; + mhdp->fw_version |= reg << 24; + + DRM_DEV_DEBUG(mhdp->dev, "firmware version: %x\n", mhdp->fw_version); + + return 0; +} +EXPORT_SYMBOL(cdns_mhdp_load_firmware); + +int cdns_mhdp_set_firmware_active(struct cdns_mhdp_device *mhdp, bool enable) +{ + u8 msg[5]; + int ret, i; + + msg[0] = GENERAL_MAIN_CONTROL; + msg[1] = MB_MODULE_ID_GENERAL; + msg[2] = 0; + msg[3] = 1; + msg[4] = enable ? FW_ACTIVE : FW_STANDBY; + + for (i = 0; i < sizeof(msg); i++) { + ret = cdp_dp_mailbox_write(mhdp, msg[i]); + if (ret) + goto err_set_firmware_active; + } + + /* read the firmware state */ + for (i = 0; i < sizeof(msg); i++) { + ret = cdns_mhdp_mailbox_read(mhdp); + if (ret < 0) + goto err_set_firmware_active; + + msg[i] = ret; + } + + ret = 0; + +err_set_firmware_active: + if (ret < 0) + DRM_DEV_ERROR(mhdp->dev, "set firmware active failed\n"); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_set_firmware_active); + +int cdns_mhdp_set_host_cap(struct cdns_mhdp_device *mhdp, bool flip) +{ + u8 msg[8]; + int ret; + + msg[0] = drm_dp_link_rate_to_bw_code(mhdp->dp.link.rate); + msg[1] = mhdp->dp.link.num_lanes | SCRAMBLER_EN; + msg[2] = VOLTAGE_LEVEL_2; + msg[3] = PRE_EMPHASIS_LEVEL_3; + msg[4] = PTS1 | PTS2 | PTS3 | PTS4; + msg[5] = FAST_LT_NOT_SUPPORT; + msg[6] = flip ? LANE_MAPPING_FLIPPED : LANE_MAPPING_NORMAL; + msg[7] = ENHANCED; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_SET_HOST_CAPABILITIES, + sizeof(msg), msg); + if (ret) + goto err_set_host_cap; + +/* TODO Sandor */ +// ret = cdns_mhdp_reg_write(mhdp, DP_AUX_SWAP_INVERSION_CONTROL, +// AUX_HOST_INVERT); + +err_set_host_cap: + if (ret) + DRM_DEV_ERROR(mhdp->dev, "set host cap failed: %d\n", ret); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_set_host_cap); + +int cdns_mhdp_event_config(struct cdns_mhdp_device *mhdp) +{ + u8 msg[5]; + int ret; + + memset(msg, 0, sizeof(msg)); + + msg[0] = MHDP_EVENT_ENABLE_HPD | MHDP_EVENT_ENABLE_TRAINING; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_ENABLE_EVENT, sizeof(msg), msg); + if (ret) + DRM_DEV_ERROR(mhdp->dev, "set event config failed: %d\n", ret); + + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_event_config); + +u32 cdns_mhdp_get_event(struct cdns_mhdp_device *mhdp) +{ + return cdns_mhdp_bus_read(mhdp, SW_EVENTS0); +} +EXPORT_SYMBOL(cdns_mhdp_get_event); + +int cdns_mhdp_get_hpd_status(struct cdns_mhdp_device *mhdp) +{ + u8 status; + int ret; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_HPD_STATE, 0, NULL); + if (ret) + goto err_get_hpd; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, + DPTX_HPD_STATE, + sizeof(status)); + if (ret) + goto err_get_hpd; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, &status, sizeof(status)); + if (ret) + goto err_get_hpd; + + return status; + +err_get_hpd: + DRM_DEV_ERROR(mhdp->dev, "get hpd status failed: %d\n", ret); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_get_hpd_status); + +int cdns_mhdp_get_edid_block(void *data, u8 *edid, + unsigned int block, size_t length) +{ + struct cdns_mhdp_device *mhdp = data; + u8 msg[2], reg[2], i; + int ret; + + for (i = 0; i < 4; i++) { + msg[0] = block / 2; + msg[1] = block % 2; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_GET_EDID, sizeof(msg), msg); + if (ret) + continue; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, + MB_MODULE_ID_DP_TX, + DPTX_GET_EDID, + sizeof(reg) + length); + if (ret) + continue; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); + if (ret) + continue; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, edid, length); + if (ret) + continue; + + if (reg[0] == length && reg[1] == block / 2) + break; + } + + if (ret) + DRM_DEV_ERROR(mhdp->dev, "get block[%d] edid failed: %d\n", + block, ret); + + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_get_edid_block); + +static int cdns_mhdp_training_start(struct cdns_mhdp_device *mhdp) +{ + unsigned long timeout; + u8 msg, event[2]; + int ret; + + msg = LINK_TRAINING_RUN; + + /* start training */ + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_TRAINING_CONTROL, sizeof(msg), &msg); + if (ret) + goto err_training_start; + + timeout = jiffies + msecs_to_jiffies(LINK_TRAINING_TIMEOUT_MS); + while (time_before(jiffies, timeout)) { + msleep(LINK_TRAINING_RETRY_MS); + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_READ_EVENT, 0, NULL); + if (ret) + goto err_training_start; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, + MB_MODULE_ID_DP_TX, + DPTX_READ_EVENT, + sizeof(event)); + if (ret) + goto err_training_start; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, event, + sizeof(event)); + if (ret) + goto err_training_start; + + if (event[1] & EQ_PHASE_FINISHED) + return 0; + } + + ret = -ETIMEDOUT; + +err_training_start: + DRM_DEV_ERROR(mhdp->dev, "training failed: %d\n", ret); + return ret; +} + +static int cdns_mhdp_get_training_status(struct cdns_mhdp_device *mhdp) +{ + u8 status[10]; + int ret; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_READ_LINK_STAT, 0, NULL); + if (ret) + goto err_get_training_status; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, + DPTX_READ_LINK_STAT, + sizeof(status)); + if (ret) + goto err_get_training_status; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, status, sizeof(status)); + if (ret) + goto err_get_training_status; + + mhdp->dp.link.rate = drm_dp_bw_code_to_link_rate(status[0]); + mhdp->dp.link.num_lanes = status[1]; + +err_get_training_status: + if (ret) + DRM_DEV_ERROR(mhdp->dev, "get training status failed: %d\n", + ret); + return ret; +} + +int cdns_mhdp_train_link(struct cdns_mhdp_device *mhdp) +{ + int ret; + + ret = cdns_mhdp_training_start(mhdp); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "Failed to start training %d\n", + ret); + return ret; + } + + ret = cdns_mhdp_get_training_status(mhdp); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "Failed to get training stat %d\n", + ret); + return ret; + } + + DRM_DEV_DEBUG_KMS(mhdp->dev, "rate:0x%x, lanes:%d\n", mhdp->dp.link.rate, + mhdp->dp.link.num_lanes); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_train_link); + +int cdns_mhdp_set_video_status(struct cdns_mhdp_device *mhdp, int active) +{ + u8 msg; + int ret; + + msg = !!active; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_SET_VIDEO, sizeof(msg), &msg); + if (ret) + DRM_DEV_ERROR(mhdp->dev, "set video status failed: %d\n", ret); + + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_set_video_status); + +static int cdns_mhdp_get_msa_misc(struct video_info *video, + struct drm_display_mode *mode) +{ + u32 msa_misc; + u8 val[2] = {0}; + + switch (video->color_fmt) { + case PXL_RGB: + case Y_ONLY: + val[0] = 0; + break; + /* set YUV default color space conversion to BT601 */ + case YCBCR_4_4_4: + val[0] = 6 + BT_601 * 8; + break; + case YCBCR_4_2_2: + val[0] = 5 + BT_601 * 8; + break; + case YCBCR_4_2_0: + val[0] = 5; + break; + }; + + switch (video->color_depth) { + case 6: + val[1] = 0; + break; + case 8: + val[1] = 1; + break; + case 10: + val[1] = 2; + break; + case 12: + val[1] = 3; + break; + case 16: + val[1] = 4; + break; + }; + + msa_misc = 2 * val[0] + 32 * val[1] + + ((video->color_fmt == Y_ONLY) ? (1 << 14) : 0); + + return msa_misc; +} + +int cdns_mhdp_config_video(struct cdns_mhdp_device *mhdp) +{ + struct video_info *video = &mhdp->video_info; + struct drm_display_mode *mode = &mhdp->mode; + u64 symbol; + u32 val, link_rate, rem; + u8 bit_per_pix, tu_size_reg = TU_SIZE; + int ret; + + bit_per_pix = (video->color_fmt == YCBCR_4_2_2) ? + (video->color_depth * 2) : (video->color_depth * 3); + + link_rate = mhdp->dp.link.rate / 1000; + + ret = cdns_mhdp_reg_write(mhdp, BND_HSYNC2VSYNC, VIF_BYPASS_INTERLACE); + if (ret) + goto err_config_video; + + ret = cdns_mhdp_reg_write(mhdp, HSYNC2VSYNC_POL_CTRL, 0); + if (ret) + goto err_config_video; + + /* + * get a best tu_size and valid symbol: + * 1. chose Lclk freq(162Mhz, 270Mhz, 540Mhz), set TU to 32 + * 2. calculate VS(valid symbol) = TU * Pclk * Bpp / (Lclk * Lanes) + * 3. if VS > *.85 or VS < *.1 or VS < 2 or TU < VS + 4, then set + * TU += 2 and repeat 2nd step. + */ + do { + tu_size_reg += 2; + symbol = tu_size_reg * mode->clock * bit_per_pix; + do_div(symbol, mhdp->dp.link.num_lanes * link_rate * 8); + rem = do_div(symbol, 1000); + if (tu_size_reg > 64) { + ret = -EINVAL; + DRM_DEV_ERROR(mhdp->dev, + "tu error, clk:%d, lanes:%d, rate:%d\n", + mode->clock, mhdp->dp.link.num_lanes, + link_rate); + goto err_config_video; + } + } while ((symbol <= 1) || (tu_size_reg - symbol < 4) || + (rem > 850) || (rem < 100)); + + val = symbol + (tu_size_reg << 8); + val |= TU_CNT_RST_EN; + ret = cdns_mhdp_reg_write(mhdp, DP_FRAMER_TU, val); + if (ret) + goto err_config_video; + + /* set the FIFO Buffer size */ + val = div_u64(mode->clock * (symbol + 1), 1000) + link_rate; + val /= (mhdp->dp.link.num_lanes * link_rate); + val = div_u64(8 * (symbol + 1), bit_per_pix) - val; + val += 2; + ret = cdns_mhdp_reg_write(mhdp, DP_VC_TABLE(15), val); + + switch (video->color_depth) { + case 6: + val = BCS_6; + break; + case 8: + val = BCS_8; + break; + case 10: + val = BCS_10; + break; + case 12: + val = BCS_12; + break; + case 16: + val = BCS_16; + break; + }; + + val += video->color_fmt << 8; + ret = cdns_mhdp_reg_write(mhdp, DP_FRAMER_PXL_REPR, val); + if (ret) + goto err_config_video; + + val = video->h_sync_polarity ? DP_FRAMER_SP_HSP : 0; + val |= video->v_sync_polarity ? DP_FRAMER_SP_VSP : 0; + ret = cdns_mhdp_reg_write(mhdp, DP_FRAMER_SP, val); + if (ret) + goto err_config_video; + + val = (mode->hsync_start - mode->hdisplay) << 16; + val |= mode->htotal - mode->hsync_end; + ret = cdns_mhdp_reg_write(mhdp, DP_FRONT_BACK_PORCH, val); + if (ret) + goto err_config_video; + + val = mode->hdisplay * bit_per_pix / 8; + ret = cdns_mhdp_reg_write(mhdp, DP_BYTE_COUNT, val); + if (ret) + goto err_config_video; + + val = mode->htotal | ((mode->htotal - mode->hsync_start) << 16); + ret = cdns_mhdp_reg_write(mhdp, MSA_HORIZONTAL_0, val); + if (ret) + goto err_config_video; + + val = mode->hsync_end - mode->hsync_start; + val |= (mode->hdisplay << 16) | (video->h_sync_polarity << 15); + ret = cdns_mhdp_reg_write(mhdp, MSA_HORIZONTAL_1, val); + if (ret) + goto err_config_video; + + val = mode->vtotal; + val |= (mode->vtotal - mode->vsync_start) << 16; + ret = cdns_mhdp_reg_write(mhdp, MSA_VERTICAL_0, val); + if (ret) + goto err_config_video; + + val = mode->vsync_end - mode->vsync_start; + val |= (mode->vdisplay << 16) | (video->v_sync_polarity << 15); + ret = cdns_mhdp_reg_write(mhdp, MSA_VERTICAL_1, val); + if (ret) + goto err_config_video; + + val = cdns_mhdp_get_msa_misc(video, mode); + ret = cdns_mhdp_reg_write(mhdp, MSA_MISC, val); + if (ret) + goto err_config_video; + + ret = cdns_mhdp_reg_write(mhdp, STREAM_CONFIG, 1); + if (ret) + goto err_config_video; + + val = mode->hsync_end - mode->hsync_start; + val |= mode->hdisplay << 16; + ret = cdns_mhdp_reg_write(mhdp, DP_HORIZONTAL, val); + if (ret) + goto err_config_video; + + val = mode->vdisplay; + val |= (mode->vtotal - mode->vsync_start) << 16; + ret = cdns_mhdp_reg_write(mhdp, DP_VERTICAL_0, val); + if (ret) + goto err_config_video; + + val = mode->vtotal; + ret = cdns_mhdp_reg_write(mhdp, DP_VERTICAL_1, val); + if (ret) + goto err_config_video; + + ret = cdns_mhdp_reg_write_bit(mhdp, DP_VB_ID, 2, 1, 0); + +err_config_video: + if (ret) + DRM_DEV_ERROR(mhdp->dev, "config video failed: %d\n", ret); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_config_video); + +int cdns_mhdp_adjust_lt(struct cdns_mhdp_device *mhdp, + u8 nlanes, u16 udelay, u8 *lanes_data, u8 *dpcd) +{ + u8 payload[7]; + u8 hdr[5]; /* For DPCD read response header */ + u32 addr; + u8 const nregs = 6; /* Registers 0x202-0x207 */ + int ret; + + if (nlanes != 4 && nlanes != 2 && nlanes != 1) { + DRM_DEV_ERROR(mhdp->dev, "invalid number of lanes: %d\n", + nlanes); + ret = -EINVAL; + goto err_adjust_lt; + } + + payload[0] = nlanes; + put_unaligned_be16(udelay, payload + 1); + memcpy(payload + 3, lanes_data, nlanes); + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_ADJUST_LT, + sizeof(payload), payload); + if (ret) + goto err_adjust_lt; + + /* Yes, read the DPCD read command response */ + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, + DPTX_READ_DPCD, + sizeof(hdr) + nregs); + if (ret) + goto err_adjust_lt; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, hdr, sizeof(hdr)); + if (ret) + goto err_adjust_lt; + + addr = get_unaligned_be24(hdr + 2); + if (addr != DP_LANE0_1_STATUS) + goto err_adjust_lt; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, dpcd, nregs); + +err_adjust_lt: + if (ret) + DRM_DEV_ERROR(mhdp->dev, "Failed to adjust Link Training.\n"); + + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_adjust_lt); + +int cdns_phy_reg_write(struct cdns_mhdp_device *mhdp, u32 addr, u32 val) +{ + return cdns_mhdp_reg_write(mhdp, ADDR_PHY_AFE + (addr << 2), val); +} +EXPORT_SYMBOL(cdns_phy_reg_write); + +u32 cdns_phy_reg_read(struct cdns_mhdp_device *mhdp, u32 addr) +{ + return cdns_mhdp_reg_read(mhdp, ADDR_PHY_AFE + (addr << 2)); +} +EXPORT_SYMBOL(cdns_phy_reg_read); + +int cdns_mhdp_read_hpd(struct cdns_mhdp_device *mhdp) +{ + u8 status; + int ret; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL, GENERAL_GET_HPD_STATE, + 0, NULL); + if (ret) + goto err_get_hpd; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_GENERAL, + GENERAL_GET_HPD_STATE, sizeof(status)); + if (ret) + goto err_get_hpd; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, &status, sizeof(status)); + if (ret) + goto err_get_hpd; + + return status; + +err_get_hpd: + DRM_ERROR("read hpd failed: %d\n", ret); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_read_hpd); + +bool cdns_mhdp_check_alive(struct cdns_mhdp_device *mhdp) +{ + u32 alive, newalive; + u8 retries_left = 50; + + alive = cdns_mhdp_bus_read(mhdp, KEEP_ALIVE); + + while (retries_left--) { + udelay(2); + + newalive = cdns_mhdp_bus_read(mhdp, KEEP_ALIVE); + if (alive == newalive) + continue; + return true; + } + return false; +} +EXPORT_SYMBOL(cdns_mhdp_check_alive); diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c new file mode 100644 index 00000000000000..62adb1f526328c --- /dev/null +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c @@ -0,0 +1,331 @@ +/* + * Copyright (C) 2019 NXP Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include + +void cdns_mhdp_infoframe_set(struct cdns_mhdp_device *mhdp, + u8 entry_id, u8 packet_len, u8 *packet, u8 packet_type) +{ + u32 *packet32, len32; + u32 val, i; + + /* invalidate entry */ + val = F_ACTIVE_IDLE_TYPE(1) | F_PKT_ALLOC_ADDRESS(entry_id); + cdns_mhdp_bus_write(val, mhdp, SOURCE_PIF_PKT_ALLOC_REG); + cdns_mhdp_bus_write(F_PKT_ALLOC_WR_EN(1), mhdp, SOURCE_PIF_PKT_ALLOC_WR_EN); + + /* flush fifo 1 */ + cdns_mhdp_bus_write(F_FIFO1_FLUSH(1), mhdp, SOURCE_PIF_FIFO1_FLUSH); + + /* write packet into memory */ + packet32 = (u32 *)packet; + len32 = packet_len / 4; + for (i = 0; i < len32; i++) + cdns_mhdp_bus_write(F_DATA_WR(packet32[i]), mhdp, SOURCE_PIF_DATA_WR); + + /* write entry id */ + cdns_mhdp_bus_write(F_WR_ADDR(entry_id), mhdp, SOURCE_PIF_WR_ADDR); + + /* write request */ + cdns_mhdp_bus_write(F_HOST_WR(1), mhdp, SOURCE_PIF_WR_REQ); + + /* update entry */ + val = F_ACTIVE_IDLE_TYPE(1) | F_TYPE_VALID(1) | + F_PACKET_TYPE(packet_type) | F_PKT_ALLOC_ADDRESS(entry_id); + cdns_mhdp_bus_write(val, mhdp, SOURCE_PIF_PKT_ALLOC_REG); + + cdns_mhdp_bus_write(F_PKT_ALLOC_WR_EN(1), mhdp, SOURCE_PIF_PKT_ALLOC_WR_EN); +} + +int cdns_hdmi_get_edid_block(void *data, u8 *edid, + u32 block, size_t length) +{ + struct cdns_mhdp_device *mhdp = data; + u8 msg[2], reg[5], i; + int ret; + + for (i = 0; i < 4; i++) { + msg[0] = block / 2; + msg[1] = block % 2; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_HDMI_TX, HDMI_TX_EDID, + sizeof(msg), msg); + if (ret) + continue; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_HDMI_TX, + HDMI_TX_EDID, sizeof(reg) + length); + if (ret) + continue; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); + if (ret) + continue; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, edid, length); + if (ret) + continue; + + if ((reg[3] << 8 | reg[4]) == length) + break; + } + + if (ret) + DRM_ERROR("get block[%d] edid failed: %d\n", block, ret); + return ret; +} + +int cdns_hdmi_scdc_read(struct cdns_mhdp_device *mhdp, u8 addr, u8 *data) +{ + u8 msg[4], reg[6]; + int ret; + + msg[0] = 0x54; + msg[1] = addr; + msg[2] = 0; + msg[3] = 1; + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_HDMI_TX, HDMI_TX_READ, + sizeof(msg), msg); + if (ret) + goto err_scdc_read; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_HDMI_TX, + HDMI_TX_READ, sizeof(reg)); + if (ret) + goto err_scdc_read; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); + if (ret) + goto err_scdc_read; + + *data = reg[5]; + +err_scdc_read: + if (ret) + DRM_ERROR("scdc read failed: %d\n", ret); + return ret; +} + +int cdns_hdmi_scdc_write(struct cdns_mhdp_device *mhdp, u8 addr, u8 value) +{ + u8 msg[5], reg[5]; + int ret; + + msg[0] = 0x54; + msg[1] = addr; + msg[2] = 0; + msg[3] = 1; + msg[4] = value; + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_HDMI_TX, HDMI_TX_WRITE, + sizeof(msg), msg); + if (ret) + goto err_scdc_write; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_HDMI_TX, + HDMI_TX_WRITE, sizeof(reg)); + if (ret) + goto err_scdc_write; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); + if (ret) + goto err_scdc_write; + + if (reg[0] != 0) + ret = -EINVAL; + +err_scdc_write: + if (ret) + DRM_ERROR("scdc write failed: %d\n", ret); + return ret; +} + +int cdns_hdmi_ctrl_init(struct cdns_mhdp_device *mhdp, + int protocol, + u32 char_rate) +{ + u32 reg0; + u32 reg1; + u32 val; + int ret; + + /* Set PHY to HDMI data */ + ret = cdns_mhdp_reg_write(mhdp, PHY_DATA_SEL, F_SOURCE_PHY_MHDP_SEL(1)); + if (ret < 0) + return ret; + + ret = cdns_mhdp_reg_write(mhdp, HDTX_HPD, + F_HPD_VALID_WIDTH(4) | F_HPD_GLITCH_WIDTH(0)); + if (ret < 0) + return ret; + + /* open CARS */ + ret = cdns_mhdp_reg_write(mhdp, SOURCE_PHY_CAR, 0xF); + if (ret < 0) + return ret; + ret = cdns_mhdp_reg_write(mhdp, SOURCE_HDTX_CAR, 0xFF); + if (ret < 0) + return ret; + ret = cdns_mhdp_reg_write(mhdp, SOURCE_PKT_CAR, 0xF); + if (ret < 0) + return ret; + ret = cdns_mhdp_reg_write(mhdp, SOURCE_AIF_CAR, 0xF); + if (ret < 0) + return ret; + ret = cdns_mhdp_reg_write(mhdp, SOURCE_CIPHER_CAR, 0xF); + if (ret < 0) + return ret; + ret = cdns_mhdp_reg_write(mhdp, SOURCE_CRYPTO_CAR, 0xF); + if (ret < 0) + return ret; + ret = cdns_mhdp_reg_write(mhdp, SOURCE_CEC_CAR, 3); + if (ret < 0) + return ret; + + reg0 = reg1 = 0x7c1f; + if (protocol == MODE_HDMI_2_0 && char_rate >= 340000) { + reg0 = 0; + reg1 = 0xFFFFF; + } + ret = cdns_mhdp_reg_write(mhdp, HDTX_CLOCK_REG_0, reg0); + if (ret < 0) + return ret; + ret = cdns_mhdp_reg_write(mhdp, HDTX_CLOCK_REG_1, reg1); + if (ret < 0) + return ret; + + /* set hdmi mode and preemble mode data enable */ + val = F_HDMI_MODE(protocol) | F_HDMI2_PREAMBLE_EN(1) | F_DATA_EN(1) | + F_HDMI2_CTRL_IL_MODE(1) | F_BCH_EN(1) | F_PIC_3D(0XF); + ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); + + return ret; +} + +int cdns_hdmi_mode_config(struct cdns_mhdp_device *mhdp, + struct drm_display_mode *mode, + struct video_info *video_info) +{ + int ret; + u32 val; + u32 vsync_lines = mode->vsync_end - mode->vsync_start; + u32 eof_lines = mode->vsync_start - mode->vdisplay; + u32 sof_lines = mode->vtotal - mode->vsync_end; + u32 hblank = mode->htotal - mode->hdisplay; + u32 hactive = mode->hdisplay; + u32 vblank = mode->vtotal - mode->vdisplay; + u32 vactive = mode->vdisplay; + u32 hfront = mode->hsync_start - mode->hdisplay; + u32 hback = mode->htotal - mode->hsync_end; + u32 vfront = eof_lines; + u32 hsync = hblank - hfront - hback; + u32 vsync = vsync_lines; + u32 vback = sof_lines; + u32 v_h_polarity = ((mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1) + + ((mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : 2); + + ret = cdns_mhdp_reg_write(mhdp, SCHEDULER_H_SIZE, (hactive << 16) + hblank); + if (ret < 0) + return ret; + + ret = cdns_mhdp_reg_write(mhdp, SCHEDULER_V_SIZE, (vactive << 16) + vblank); + if (ret < 0) + return ret; + + ret = cdns_mhdp_reg_write(mhdp, HDTX_SIGNAL_FRONT_WIDTH, (vfront << 16) + hfront); + if (ret < 0) + return ret; + + ret = cdns_mhdp_reg_write(mhdp, HDTX_SIGNAL_SYNC_WIDTH, (vsync << 16) + hsync); + if (ret < 0) + return ret; + + ret = cdns_mhdp_reg_write(mhdp, HDTX_SIGNAL_BACK_WIDTH, (vback << 16) + hback); + if (ret < 0) + return ret; + + ret = cdns_mhdp_reg_write(mhdp, HSYNC2VSYNC_POL_CTRL, v_h_polarity); + if (ret < 0) + return ret; + + /* Reset Data Enable */ + val = cdns_mhdp_reg_read(mhdp, HDTX_CONTROLLER); + val &= ~F_DATA_EN(1); + ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); + if (ret < 0) + return ret; + + /* Set bpc */ + val &= ~F_VIF_DATA_WIDTH(3); + switch (video_info->color_depth) { + case 10: + val |= F_VIF_DATA_WIDTH(1); + break; + case 12: + val |= F_VIF_DATA_WIDTH(2); + break; + case 16: + val |= F_VIF_DATA_WIDTH(3); + break; + case 8: + default: + val |= F_VIF_DATA_WIDTH(0); + break; + } + + /* select color encoding */ + val &= ~F_HDMI_ENCODING(3); + switch (video_info->color_fmt) { + case YCBCR_4_4_4: + val |= F_HDMI_ENCODING(2); + break; + case YCBCR_4_2_2: + val |= F_HDMI_ENCODING(1); + break; + case YCBCR_4_2_0: + val |= F_HDMI_ENCODING(3); + break; + case PXL_RGB: + default: + val |= F_HDMI_ENCODING(0); + break; + } + + ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); + if (ret < 0) + return ret; + + /* set data enable */ + val |= F_DATA_EN(1); + ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); + + return ret; +} + +int cdns_hdmi_disable_gcp(struct cdns_mhdp_device *mhdp) +{ + u32 val; + + val = cdns_mhdp_reg_read(mhdp, HDTX_CONTROLLER); + val &= ~F_GCP_EN(1); + + return cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); +} + +int cdns_hdmi_enable_gcp(struct cdns_mhdp_device *mhdp) +{ + u32 val; + + val = cdns_mhdp_reg_read(mhdp, HDTX_CONTROLLER); + val |= F_GCP_EN(1); + + return cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); +} diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp.h b/drivers/gpu/drm/bridge/cadence/cdns-mhdp.h new file mode 100644 index 00000000000000..399c3f6f86ad05 --- /dev/null +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp.h @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Cadence MHDP DP MST bridge driver. + * + * Copyright: 2018 Cadence Design Systems, Inc. + * + * Author: Quentin Schulz + */ + + +#ifndef CDNS_MHDP_H +#define CDNS_MHDP_H + +#include + +#define CDNS_APB_CFG 0x00000 +#define CDNS_APB_CTRL (CDNS_APB_CFG + 0x00) +#define CDNS_MAILBOX_FULL (CDNS_APB_CFG + 0x08) +#define CDNS_MAILBOX_EMPTY (CDNS_APB_CFG + 0x0c) +#define CDNS_MAILBOX_TX_DATA (CDNS_APB_CFG + 0x10) +#define CDNS_MAILBOX_RX_DATA (CDNS_APB_CFG + 0x14) +#define CDNS_KEEP_ALIVE (CDNS_APB_CFG + 0x18) +#define CDNS_KEEP_ALIVE_MASK GENMASK(7, 0) + +#define CDNS_MB_INT_MASK (CDNS_APB_CFG + 0x34) + +#define CDNS_SW_CLK_L (CDNS_APB_CFG + 0x3c) +#define CDNS_SW_CLK_H (CDNS_APB_CFG + 0x40) +#define CDNS_SW_EVENT0 (CDNS_APB_CFG + 0x44) +#define CDNS_DPTX_HPD BIT(0) + +#define CDNS_SW_EVENT1 (CDNS_APB_CFG + 0x48) +#define CDNS_SW_EVENT2 (CDNS_APB_CFG + 0x4c) +#define CDNS_SW_EVENT3 (CDNS_APB_CFG + 0x50) + +#define CDNS_APB_INT_MASK (CDNS_APB_CFG + 0x6C) +#define CDNS_APB_INT_MASK_MAILBOX_INT BIT(0) +#define CDNS_APB_INT_MASK_SW_EVENT_INT BIT(1) + +#define CDNS_DPTX_CAR (CDNS_APB_CFG + 0x904) +#define CDNS_VIF_CLK_EN BIT(0) +#define CDNS_VIF_CLK_RSTN BIT(1) + +#define CDNS_SOURCE_VIDEO_IF(s) (0x00b00 + (s * 0x20)) +#define CDNS_BND_HSYNC2VSYNC(s) (CDNS_SOURCE_VIDEO_IF(s) + \ + 0x00) +#define CDNS_IP_DTCT_WIN GENMASK(11, 0) +#define CDNS_IP_DET_INTERLACE_FORMAT BIT(12) +#define CDNS_IP_BYPASS_V_INTERFACE BIT(13) + +#define CDNS_HSYNC2VSYNC_POL_CTRL(s) (CDNS_SOURCE_VIDEO_IF(s) + \ + 0x10) +#define CDNS_H2V_HSYNC_POL_ACTIVE_LOW BIT(1) +#define CDNS_H2V_VSYNC_POL_ACTIVE_LOW BIT(2) + +#define CDNS_DPTX_PHY_CONFIG 0x02000 +#define CDNS_PHY_TRAINING_EN BIT(0) +#define CDNS_PHY_TRAINING_TYPE(x) (((x) & GENMASK(3, 0)) << 1) +#define CDNS_PHY_SCRAMBLER_BYPASS BIT(5) +#define CDNS_PHY_ENCODER_BYPASS BIT(6) +#define CDNS_PHY_SKEW_BYPASS BIT(7) +#define CDNS_PHY_TRAINING_AUTO BIT(8) +#define CDNS_PHY_LANE0_SKEW(x) (((x) & GENMASK(2, 0)) << 9) +#define CDNS_PHY_LANE1_SKEW(x) (((x) & GENMASK(2, 0)) << 12) +#define CDNS_PHY_LANE2_SKEW(x) (((x) & GENMASK(2, 0)) << 15) +#define CDNS_PHY_LANE3_SKEW(x) (((x) & GENMASK(2, 0)) << 18) +#define CDNS_PHY_COMMON_CONFIG (CDNS_PHY_LANE1_SKEW(1) | \ + CDNS_PHY_LANE2_SKEW(2) | \ + CDNS_PHY_LANE3_SKEW(3)) +#define CDNS_PHY_10BIT_EN BIT(21) + +#define CDNS_DPTX_FRAMER 0x02200 +#define CDNS_DP_FRAMER_GLOBAL_CONFIG (CDNS_DPTX_FRAMER + 0x00) +#define CDNS_DP_NUM_LANES(x) (x - 1) +#define CDNS_DP_MST_EN BIT(2) +#define CDNS_DP_FRAMER_EN BIT(3) +#define CDNS_DP_RATE_GOVERNOR_EN BIT(4) +#define CDNS_DP_NO_VIDEO_MODE BIT(5) +#define CDNS_DP_DISABLE_PHY_RST BIT(6) +#define CDNS_DP_WR_FAILING_EDGE_VSYNC BIT(7) + +#define CDNS_DP_SW_RESET (CDNS_DPTX_FRAMER + 0x04) +#define CDNS_DP_FRAMER_TU (CDNS_DPTX_FRAMER + 0x08) +#define CDNS_DP_FRAMER_TU_SIZE(x) (((x) & GENMASK(6, 0)) << 8) +#define CDNS_DP_FRAMER_TU_VS(x) ((x) & GENMASK(5, 0)) +#define CDNS_DP_FRAMER_TU_CNT_RST_EN BIT(15) + +#define CDNS_DPTX_STREAM(s) (0x03000 + s * 0x80) +#define CDNS_DP_MSA_HORIZONTAL_0(s) (CDNS_DPTX_STREAM(s) + 0x00) +#define CDNS_DP_MSAH0_H_TOTAL(x) (x) +#define CDNS_DP_MSAH0_HSYNC_START(x) ((x) << 16) + +#define CDNS_DP_MSA_HORIZONTAL_1(s) (CDNS_DPTX_STREAM(s) + 0x04) +#define CDNS_DP_MSAH1_HSYNC_WIDTH(x) (x) +#define CDNS_DP_MSAH1_HSYNC_POL_LOW BIT(15) +#define CDNS_DP_MSAH1_HDISP_WIDTH(x) ((x) << 16) + +#define CDNS_DP_MSA_VERTICAL_0(s) (CDNS_DPTX_STREAM(s) + 0x08) +#define CDNS_DP_MSAV0_V_TOTAL(x) (x) +#define CDNS_DP_MSAV0_VSYNC_START(x) ((x) << 16) + +#define CDNS_DP_MSA_VERTICAL_1(s) (CDNS_DPTX_STREAM(s) + 0x0c) +#define CDNS_DP_MSAV1_VSYNC_WIDTH(x) (x) +#define CDNS_DP_MSAV1_VSYNC_POL_LOW BIT(15) +#define CDNS_DP_MSAV1_VDISP_WIDTH(x) ((x) << 16) + +#define CDNS_DP_MSA_MISC(s) (CDNS_DPTX_STREAM(s) + 0x10) +#define CDNS_DP_STREAM_CONFIGs(s) (CDNS_DPTX_STREAM(s) + 0x14) +#define CDNS_DP_STREAM_CONFIG_2(s) (CDNS_DPTX_STREAM(s) + 0x2c) +#define CDNS_DP_SC2_TU_VS_DIFF(x) ((x) << 8) + +#define CDNS_DP_HORIZONTAL(s) (CDNS_DPTX_STREAM(s) + 0x30) +#define CDNS_DP_H_HSYNC_WIDTH(x) (x) +#define CDNS_DP_H_H_TOTAL(x) ((x) << 16) + +#define CDNS_DP_VERTICAL_0(s) (CDNS_DPTX_STREAM(s) + 0x34) +#define CDNS_DP_V0_VHEIGHT(x) (x) +#define CDNS_DP_V0_VSTART(x) ((x) << 16) + +#define CDNS_DP_VERTICAL_1(s) (CDNS_DPTX_STREAM(s) + 0x38) +#define CDNS_DP_V1_VTOTAL(x) (x) +#define CDNS_DP_V1_VTOTAL_EVEN BIT(16) + +#define CDNS_DP_FRAMER_PXL_REPR(s) (CDNS_DPTX_STREAM(s) + 0x4c) +#define CDNS_DP_FRAMER_6_BPC BIT(0) +#define CDNS_DP_FRAMER_8_BPC BIT(1) +#define CDNS_DP_FRAMER_10_BPC BIT(2) +#define CDNS_DP_FRAMER_12_BPC BIT(3) +#define CDNS_DP_FRAMER_16_BPC BIT(4) +#define CDNS_DP_FRAMER_PXL_FORMAT 0x8 +#define CDNS_DP_FRAMER_RGB BIT(0) +#define CDNS_DP_FRAMER_YCBCR444 BIT(1) +#define CDNS_DP_FRAMER_YCBCR422 BIT(2) +#define CDNS_DP_FRAMER_YCBCR420 BIT(3) +#define CDNS_DP_FRAMER_Y_ONLY BIT(4) + +#define CDNS_DP_FRAMER_SP(s) (CDNS_DPTX_STREAM(s) + 0x10) +#define CDNS_DP_FRAMER_VSYNC_POL_LOW BIT(0) +#define CDNS_DP_FRAMER_HSYNC_POL_LOW BIT(1) +#define CDNS_DP_FRAMER_INTERLACE BIT(2) + +#define CDNS_DP_LINE_THRESH(s) (CDNS_DPTX_STREAM(s) + 0x64) +#define CDNS_DP_ACTIVE_LINE_THRESH(x) (x) + +#define CDNS_DP_VB_ID(s) (CDNS_DPTX_STREAM(s) + 0x68) +#define CDNS_DP_VB_ID_INTERLACED BIT(2) +#define CDNS_DP_VB_ID_COMPRESSED BIT(6) + +#define CDNS_DP_FRONT_BACK_PORCH(s) (CDNS_DPTX_STREAM(s) + 0x78) +#define CDNS_DP_BACK_PORCH(x) (x) +#define CDNS_DP_FRONT_PORCH(x) ((x) << 16) + +#define CDNS_DP_BYTE_COUNT(s) (CDNS_DPTX_STREAM(s) + 0x7c) +#define CDNS_DP_BYTE_COUNT_BYTES_IN_CHUNK_SHIFT 16 + +#define CDNS_DP_MST_STREAM_CONFIG(s) (CDNS_DPTX_STREAM(s) + 0x14) +#define CDNS_DP_MST_STRM_CFG_STREAM_EN BIT(0) +#define CDNS_DP_MST_STRM_CFG_NO_VIDEO BIT(1) + +#define CDNS_DP_MST_SLOT_ALLOCATE(s) (CDNS_DPTX_STREAM(s) + 0x44) +#define CDNS_DP_S_ALLOC_START_SLOT(x) (x) +#define CDNS_DP_S_ALLOC_END_SLOT(x) ((x) << 8) + +#define CDNS_DP_RATE_GOVERNING(s) (CDNS_DPTX_STREAM(s) + 0x48) +#define CDNS_DP_RG_TARG_AV_SLOTS_Y(x) (x) +#define CDNS_DP_RG_TARG_AV_SLOTS_X(x) (x << 4) +#define CDNS_DP_RG_ENABLE BIT(10) + +#define CDNS_DP_MTPH_CONTROL 0x2264 +#define CDNS_DP_MTPH_ECF_EN BIT(0) +#define CDNS_DP_MTPH_ACT_EN BIT(1) +#define CDNS_DP_MTPH_LVP_EN BIT(2) + +#define CDNS_DP_MTPH_STATUS 0x226C +#define CDNS_DP_MTPH_ACT_STATUS BIT(0) + + +#define CDNS_DPTX_GLOBAL 0x02300 +#define CDNS_DP_LANE_EN (CDNS_DPTX_GLOBAL + 0x00) +#define CDNS_DP_LANE_EN_LANES(x) GENMASK(x - 1, 0) +#define CDNS_DP_ENHNCD (CDNS_DPTX_GLOBAL + 0x04) + + +#define to_mhdp_connector(x) container_of(x, struct cdns_mhdp_connector, base) +#define to_mhdp_bridge(x) container_of(x, struct cdns_mhdp_bridge, base) +#define mgr_to_mhdp(x) container_of(x, struct cdns_mhdp_device, mst_mgr) + +#define CDNS_MHDP_MAX_STREAMS 4 + +enum pixel_format { + PIXEL_FORMAT_RGB = 1, + PIXEL_FORMAT_YCBCR_444 = 2, + PIXEL_FORMAT_YCBCR_422 = 4, + PIXEL_FORMAT_YCBCR_420 = 8, + PIXEL_FORMAT_Y_ONLY = 16, +}; + + +int cdns_mhdp_mst_init(struct cdns_mhdp_device *mhdp); +void cdns_mhdp_mst_deinit(struct cdns_mhdp_device *mhdp); +bool cdns_mhdp_mst_probe(struct cdns_mhdp_device *mhdp); +enum pixel_format cdns_mhdp_get_pxlfmt(u32 color_formats); +u32 cdns_mhdp_get_bpp(u32 bpc, u32 color_formats); +void cdns_mhdp_configure_video(struct drm_bridge *bridge); +void cdns_mhdp_mst_enable(struct drm_bridge *bridge); +void cdns_mhdp_mst_disable(struct drm_bridge *bridge); +void cdns_mhdp_enable(struct drm_bridge *bridge); + +#endif diff --git a/drivers/gpu/drm/bridge/fsl-imx-ldb.c b/drivers/gpu/drm/bridge/fsl-imx-ldb.c new file mode 100644 index 00000000000000..513a8b8c740aa4 --- /dev/null +++ b/drivers/gpu/drm/bridge/fsl-imx-ldb.c @@ -0,0 +1,283 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2012 Sascha Hauer, Pengutronix + * Copyright 2020 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LDB_CH0_MODE_EN_TO_DI0 (1 << 0) +#define LDB_CH0_MODE_EN_TO_DI1 (3 << 0) +#define LDB_CH0_MODE_EN_MASK (3 << 0) +#define LDB_CH1_MODE_EN_TO_DI0 (1 << 2) +#define LDB_CH1_MODE_EN_TO_DI1 (3 << 2) +#define LDB_CH1_MODE_EN_MASK (3 << 2) +#define LDB_SPLIT_MODE_EN (1 << 4) +#define LDB_DATA_WIDTH_CH0_24 (1 << 5) +#define LDB_BIT_MAP_CH0_JEIDA (1 << 6) +#define LDB_DATA_WIDTH_CH1_24 (1 << 7) +#define LDB_BIT_MAP_CH1_JEIDA (1 << 8) +#define LDB_DI0_VS_POL_ACT_LOW (1 << 9) +#define LDB_DI1_VS_POL_ACT_LOW (1 << 10) + +struct ldb_bit_mapping { + u32 bus_format; + u32 datawidth; + const char * const mapping; +}; + +static const struct ldb_bit_mapping ldb_bit_mappings[] = { + { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, "spwg" }, + { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, "spwg" }, + { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, "jeida" }, +}; + +static u32 of_get_bus_format(struct device *dev, struct device_node *np) +{ + const char *bm; + u32 datawidth = 0; + int ret, i; + + ret = of_property_read_string(np, "fsl,data-mapping", &bm); + if (ret < 0) + return ret; + + of_property_read_u32(np, "fsl,data-width", &datawidth); + + for (i = 0; i < ARRAY_SIZE(ldb_bit_mappings); i++) { + if (!strcasecmp(bm, ldb_bit_mappings[i].mapping) && + datawidth == ldb_bit_mappings[i].datawidth) + return ldb_bit_mappings[i].bus_format; + } + + dev_err(dev, "invalid data mapping: %d-bit \"%s\"\n", datawidth, bm); + + return -ENOENT; +} + +static inline struct ldb_channel *bridge_to_ldb_ch(struct drm_bridge *b) +{ + return container_of(b, struct ldb_channel, bridge); +} + +static void ldb_ch_set_bus_format(struct ldb_channel *ldb_ch, u32 bus_format) +{ + struct ldb *ldb = ldb_ch->ldb; + + switch (bus_format) { + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: + break; + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: + if (ldb_ch->chno == 0 || ldb->dual) + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24; + if (ldb_ch->chno == 1 || ldb->dual) + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24; + break; + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: + if (ldb_ch->chno == 0 || ldb->dual) + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 | + LDB_BIT_MAP_CH0_JEIDA; + if (ldb_ch->chno == 1 || ldb->dual) + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 | + LDB_BIT_MAP_CH1_JEIDA; + break; + } +} + +static void ldb_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode) +{ + struct ldb_channel *ldb_ch = bridge_to_ldb_ch(bridge); + struct ldb *ldb = ldb_ch->ldb; + + /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */ + if (ldb_ch == ldb->channel[0] || ldb->dual) { + if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) + ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW; + else if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) + ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW; + } + if (ldb_ch == ldb->channel[1] || ldb->dual) { + if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) + ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW; + else if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) + ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW; + } + + ldb_ch_set_bus_format(ldb_ch, ldb_ch->bus_format); +} + +static void ldb_bridge_enable(struct drm_bridge *bridge) +{ + struct ldb_channel *ldb_ch = bridge_to_ldb_ch(bridge); + struct ldb *ldb = ldb_ch->ldb; + + if (pm_runtime_enabled(ldb->dev)) + pm_runtime_get_sync(ldb->dev); + + regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl); +} + +static void ldb_bridge_disable(struct drm_bridge *bridge) +{ + struct ldb_channel *ldb_ch = bridge_to_ldb_ch(bridge); + struct ldb *ldb = ldb_ch->ldb; + + if (ldb_ch == ldb->channel[0] || ldb->dual) + ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; + if (ldb_ch == ldb->channel[1] || ldb->dual) + ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; + + regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl); + + if (pm_runtime_enabled(ldb->dev)) + pm_runtime_put(ldb->dev); +} + +static int ldb_bridge_attach(struct drm_bridge *bridge) +{ + struct ldb_channel *ldb_ch = bridge_to_ldb_ch(bridge); + struct ldb *ldb = ldb_ch->ldb; + + if (!bridge->encoder) { + dev_err(ldb->dev, "failed to find encoder object\n"); + return -ENODEV; + } + + if (!ldb_ch->next_bridge) + return 0; + + return drm_bridge_attach(bridge->encoder, + ldb_ch->next_bridge, &ldb_ch->bridge); +} + +static const struct drm_bridge_funcs ldb_bridge_funcs = { + .mode_set = ldb_bridge_mode_set, + .enable = ldb_bridge_enable, + .disable = ldb_bridge_disable, + .attach = ldb_bridge_attach, +}; + +int ldb_bind(struct ldb *ldb, struct drm_encoder **encoder) +{ + struct device *dev = ldb->dev; + struct device_node *np = dev->of_node; + struct device_node *child; + int ret = 0; + int i; + + ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr"); + if (IS_ERR(ldb->regmap)) { + dev_err(dev, "failed to get parent regmap\n"); + return PTR_ERR(ldb->regmap); + } + + if (pm_runtime_enabled(dev)) + pm_runtime_get_sync(dev); + + /* disable LDB by resetting the control register to POR default */ + regmap_write(ldb->regmap, ldb->ctrl_reg, 0); + + if (pm_runtime_enabled(dev)) + pm_runtime_put(dev); + + ldb->dual = of_property_read_bool(np, "fsl,dual-channel"); + if (ldb->dual) + ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN; + + for_each_child_of_node(np, child) { + struct ldb_channel *ldb_ch; + int bus_format; + + ret = of_property_read_u32(child, "reg", &i); + if (ret || i < 0 || i > 1) { + ret = -EINVAL; + goto free_child; + } + + if (!of_device_is_available(child)) + continue; + + if (ldb->dual && i > 0) { + dev_warn(dev, "dual-channel mode, ignoring second output\n"); + continue; + } + + ldb_ch = ldb->channel[i]; + ldb_ch->ldb = ldb; + ldb_ch->chno = i; + ldb_ch->is_valid = false; + + ret = drm_of_find_panel_or_bridge(child, + ldb->output_port, 0, + &ldb_ch->panel, + &ldb_ch->next_bridge); + if (ret && ret != -ENODEV) + goto free_child; + + bus_format = of_get_bus_format(dev, child); + if (bus_format == -EINVAL) { + /* + * If no bus format was specified in the device tree, + * we can still get it from the connected panel later. + */ + if (ldb_ch->panel && ldb_ch->panel->funcs && + ldb_ch->panel->funcs->get_modes) + bus_format = 0; + } + if (bus_format < 0) { + dev_err(dev, "could not determine data mapping: %d\n", + bus_format); + ret = bus_format; + goto free_child; + } + ldb_ch->bus_format = bus_format; + ldb_ch->child = child; + + if (ldb_ch->panel) { + ldb_ch->next_bridge = + devm_drm_panel_bridge_add(dev, + ldb_ch->panel, + DRM_MODE_CONNECTOR_LVDS); + if (IS_ERR(ldb_ch->next_bridge)) { + ret = PTR_ERR(ldb_ch->next_bridge); + goto free_child; + } + } + + ldb_ch->bridge.driver_private = ldb_ch; + ldb_ch->bridge.funcs = &ldb_bridge_funcs; + ldb_ch->bridge.of_node = child; + + ret = drm_bridge_attach(encoder[i], &ldb_ch->bridge, NULL); + if (ret) { + dev_err(dev, + "failed to attach bridge with encoder: %d\n", + ret); + goto free_child; + } + + ldb_ch->is_valid = true; + } + + return 0; + +free_child: + of_node_put(child); + return ret; +} +EXPORT_SYMBOL_GPL(ldb_bind); + +MODULE_DESCRIPTION("Freescale i.MX LVDS display bridge driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform: fsl-imx-ldb"); diff --git a/drivers/gpu/drm/bridge/it6263.c b/drivers/gpu/drm/bridge/it6263.c new file mode 100644 index 00000000000000..6047ec84221f12 --- /dev/null +++ b/drivers/gpu/drm/bridge/it6263.c @@ -0,0 +1,1031 @@ +/* + * Copyright 2017-2019 NXP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define REG_VENDOR_ID(n) (0x00 + (n)) /* n: 0/1 */ +#define REG_DEVICE_ID(n) (0x02 + (n)) /* n: 0/1 */ +#define LVDS_VENDER_ID_LOW 0x15 +#define LVDS_VENDER_ID_HIGH 0xCA +#define LVDS_DEVICE_ID_LOW 0x61 +#define LVDS_DEVICE_ID_HIGH 0x62 +#define HDMI_VENDER_ID_LOW 0x01 +#define HDMI_VENDER_ID_HIGH 0xCA +#define HDMI_DEVICE_ID_LOW 0x13 +#define HDMI_DEVICE_ID_HIGH 0x76 + +/* LVDS registers */ +#define LVDS_REG_SW_RST 0x05 +#define SOFT_REFCLK_DM_RST BIT(0) +#define SOFT_PCLK_DM_RST BIT(1) + +#define LVDS_REG_MODE 0x2C +#define LVDS_COLOR_DEPTH 0x3 +enum { + LVDS_COLOR_DEPTH_18, + LVDS_COLOR_DEPTH_24, + LVDS_COLOR_DEPTH_30, + LVDS_COLOR_DEPTH_36, +}; +#define LVDS_OUT_MAP BIT(4) +#define VESA BIT(4) +#define JEIDA 0 +#define DMODE BIT(7) +#define SPLIT_MODE BIT(7) +#define SINGLE_MODE 0 + +#define LVDS_REG_STABLE 0x30 +#define VIDEO_STABLE BIT(0) +#define PCLK_LOCK BIT(1) + +#define LVDS_REG_39 0x39 + +#define LVDS_REG_PLL 0x3C +#define LVDS_REG_AFE_3E 0x3E +#define LVDS_REG_AFE_3F 0x3F +#define LVDS_REG_AFE_47 0x47 +#define LVDS_REG_AFE_48 0x48 +#define LVDS_REG_AFE_4F 0x4F +#define LVDS_REG_52 0x52 +#define LVDS_REG_PCLK_CNT_HIGH 0x57 +#define LVDS_REG_PCLK_CNT_LOW 0x58 + +/* + * HDMI registers + * + * Registers are separated into three banks: + * 1) common bank: 0x00 ~ 0x2F + * 2) bank0: 0x30 ~ 0xFF + * 3) bank1: 0x130 ~ 0x1FF (HDMI packet registers) + * + * Use register HDMI_REG_BANK_CTRL @ 0x0F[1:0] to select bank0/1: + * 2b'00 - bank0 + * 2b'01 - bank1 + */ + +/******************************/ +/* HDMI register common bank */ +/******************************/ + +/* HDMI genernal registers */ +#define HDMI_REG_SW_RST 0x04 +#define SOFTREF_RST BIT(5) +#define SOFTA_RST BIT(4) +#define SOFTV_RST BIT(3) +#define AUD_RST BIT(2) +#define HDCP_RST BIT(0) +#define HDMI_RST_ALL (SOFTREF_RST | SOFTA_RST | SOFTV_RST | \ + AUD_RST | HDCP_RST) + +#define HDMI_REG_INT_CTRL 0x05 +#define INTPOL_ACTH BIT(7) +#define INTPOL_ACTL 0 +#define INTIOMODE_OPENDRAIN BIT(6) +#define INTIOMODE_PUSHPULL 0 +#define SELXTAL BIT(5) /* REFCLK <= XTALCLK */ +#define SELXTAL_QUARTER 0 /* REFCLK <= OSCCLK/4 */ +#define PDREFCNT(n) (((n) >> 2) << 2) /* REFCLK Div(n) */ +#define PDREFCLK BIT(1) +#define PDTXCLK_GATED BIT(0) +#define PDTXCLK_ACTIVE 0 + +#define HDMI_REG_INT_STAT(n) (0x05 + (n)) /* n: 1/2/3 */ +#define HDMI_REG_INT_MASK(n) (0x08 + (n)) /* n: 1/2/3 */ + +/* INT1 */ +#define INT_AUD_OVERFLOW BIT(7) +#define INT_RDDC_NOACK BIT(5) +#define INT_DDCFIFO_ERR BIT(4) +#define INT_DDC_BUS_HANG BIT(2) +#define INT_RX_SENSE BIT(1) +#define INT_HPD BIT(0) + +/* INT2 */ +#define INT_VID_UNSTABLE BIT(6) +#define INT_PKTACP BIT(5) +#define INT_PKTNULL BIT(4) +#define INT_PKTGEN BIT(3) +#define INT_KSVLIST_CHK BIT(2) +#define INT_AUTH_DONE BIT(1) +#define INT_AUTH_FAIL BIT(0) + +/* INT3 */ +#define INT_AUD_CTS BIT(6) +#define INT_VSYNC BIT(5) +#define INT_VIDSTABLE BIT(4) +#define INT_PKTMPG BIT(3) +#define INT_PKTGBD BIT(2) +#define INT_PKTAUD BIT(1) +#define INT_PKTAVI BIT(0) + +#define INT_MASK_AUD_CTS BIT(5) +#define INT_MASK_VSYNC BIT(4) +#define INT_MASK_VIDSTABLE BIT(3) +#define INT_MASK_PKTMPG BIT(2) +#define INT_MASK_PKTGBD BIT(1) +#define INT_MASK_PKTAUD BIT(0) + +#define HDMI_REG_INT_CLR(n) (0x0C + (n)) /* n: 0/1 */ + +/* CLR0 */ +#define INT_CLR_PKTACP BIT(7) +#define INT_CLR_PKTNULL BIT(6) +#define INT_CLR_PKTGEN BIT(5) +#define INT_CLR_KSVLIST_CHK BIT(4) +#define INT_CLR_AUTH_DONE BIT(3) +#define INT_CLR_AUTH_FAIL BIT(2) +#define INT_CLR_RXSENSE BIT(1) +#define INT_CLR_HPD BIT(0) + +/* CLR1 */ +#define INT_CLR_VSYNC BIT(7) +#define INT_CLR_VIDSTABLE BIT(6) +#define INT_CLR_PKTMPG BIT(5) +#define INT_CLR_PKTGBD BIT(4) +#define INT_CLR_PKTAUD BIT(3) +#define INT_CLR_PKTAVI BIT(2) +#define INT_CLR_VID_UNSTABLE BIT(0) + +#define HDMI_REG_SYS_STATUS 0x0E +#define INT_ACTIVE BIT(7) +#define HPDETECT BIT(6) +#define RXSENDETECT BIT(5) +#define TXVIDSTABLE BIT(4) +#define CTSINTSTEP 0xC +#define CLR_AUD_CTS BIT(1) +#define INTACTDONE BIT(0) + +#define HDMI_REG_BANK_CTRL 0x0F +#define BANK_SEL(n) ((n) ? 1 : 0) + +/* HDMI System DDC control registers */ +#define HDMI_REG_DDC_MASTER_CTRL 0x10 +#define MASTER_SEL_HOST BIT(0) +#define MASTER_SEL_HDCP 0 + +#define HDMI_REG_DDC_HEADER 0x11 +#define DDC_HDCP_ADDRESS 0x74 + +#define HDMI_REG_DDC_REQOFF 0x12 +#define HDMI_REG_DDC_REQCOUNT 0x13 +#define HDMI_REG_DDC_EDIDSEG 0x14 + +#define HDMI_REG_DDC_CMD 0x15 +#define DDC_CMD_SEQ_BURSTREAD 0x0 +#define DDC_CMD_LINK_CHKREAD 0x2 +#define DDC_CMD_EDID_READ 0x3 +#define DDC_CMD_FIFO_CLR 0x9 +#define DDC_CMD_GEN_SCLCLK 0xA +#define DDC_CMD_ABORT 0xF + +#define HDMI_REG_DDC_STATUS 0x16 +#define DDC_DONE BIT(7) +#define DDC_ACT BIT(6) +#define DDC_NOACK BIT(5) +#define DDC_WAITBUS BIT(4) +#define DDC_ARBILOSE BIT(3) +#define DDC_ERROR (DDC_NOACK | DDC_WAITBUS | DDC_ARBILOSE) +#define DDC_FIFOFULL BIT(2) +#define DDC_FIFOEMPTY BIT(1) + +#define HDMI_DDC_FIFO_SIZE 32 /* bytes */ +#define HDMI_REG_DDC_READFIFO 0x17 +#define HDMI_REG_ROM_STAT 0x1C +#define HDMI_REG_LVDS_PORT 0x1D /* LVDS input ctrl i2c addr */ +#define HDMI_REG_LVDS_PORT_EN 0x1E /* and to enable */ +#define LVDS_INPUT_CTRL_I2C_ADDR 0x33 + +/***********************/ +/* HDMI register bank0 */ +/***********************/ + +/* HDMI clock control registers */ +#define HDMI_REG_CLK_CTRL1 0x59 +#define EN_TXCLK_COUNT BIT(5) +#define VDO_LATCH_EDGE BIT(3) + +/* HDMI AFE registers */ +#define HDMI_REG_AFE_DRV_CTRL 0x61 +#define AFE_DRV_PWD BIT(5) +#define AFE_DRV_RST BIT(4) +#define AFE_DRV_PDRXDET BIT(2) +#define AFE_DRV_TERMON BIT(1) +#define AFE_DRV_ENCAL BIT(0) + +#define HDMI_REG_AFE_XP_CTRL 0x62 +#define AFE_XP_GAINBIT BIT(7) +#define AFE_XP_PWDPLL BIT(6) +#define AFE_XP_ENI BIT(5) +#define AFE_XP_ER0 BIT(4) +#define AFE_XP_RESETB BIT(3) +#define AFE_XP_PWDI BIT(2) +#define AFE_XP_DEI BIT(1) +#define AFE_XP_DER BIT(0) + +#define HDMI_REG_AFE_ISW_CTRL 0x63 +#define AFE_RTERM_SEL BIT(7) +#define AFE_IP_BYPASS BIT(6) +#define AFE_DRV_ISW 0x38 +#define AFE_DRV_ISWK 7 + +#define HDMI_REG_AFE_IP_CTRL 0x64 +#define AFE_IP_GAINBIT BIT(7) +#define AFE_IP_PWDPLL BIT(6) +#define AFE_IP_CKSEL 0x30 +#define AFE_IP_ER0 BIT(3) +#define AFE_IP_RESETB BIT(2) +#define AFE_IP_ENC BIT(1) +#define AFE_IP_EC1 BIT(0) + +/* HDMI input data format registers */ +#define HDMI_REG_INPUT_MODE 0x70 +#define IN_RGB 0x00 +#define IN_YUV422 0x40 +#define IN_YUV444 0x80 + +#define HDMI_REG_TXFIFO_RST 0x71 +#define ENAVMUTERST BIT(0) +#define TXFFRST BIT(1) + +/* HDMI pattern generation SYNC/DE registers */ +#define HDMI_REG_9X(n) (0x90 + (n)) /* n: 0x0 ~ 0xF */ +#define HDMI_REG_AX(n) (0xA0 + (n)) /* n: 0x0 ~ 0xF */ +#define HDMI_REG_B0 0xB0 + +/* HDMI general control registers */ +#define HDMI_REG_HDMI_MODE 0xC0 +#define TX_HDMI_MODE 1 +#define TX_DVI_MODE 0 + +#define HDMI_REG_GCP 0xC1 +#define AVMUTE BIT(0) +#define BLUE_SCR_MUTE BIT(1) +#define NODEF_PHASE BIT(2) +#define PHASE_RESYNC BIT(3) +#define HDMI_COLOR_DEPTH 0x70 +enum { + HDMI_COLOR_DEPTH_DEF = 0x0, /* default as 24bit */ + HDMI_COLOR_DEPTH_24 = 0x40, + HDMI_COLOR_DEPTH_30 = 0x50, + HDMI_COLOR_DEPTH_36 = 0x60, + HDMI_COLOR_DEPTH_48 = 0x70, +}; + +#define HDMI_REG_OESS_CYCLE 0xC3 +#define HDMI_REG_ENCRYPTION 0xC4 /* HDCP */ + +#define HDMI_REG_PKT_SINGLE_CTRL 0xC5 +#define SINGLE_PKT BIT(0) +#define BURST_PKT 0 + +#define HDMI_REG_PKT_GENERAL_CTRL 0xC6 +#define HDMI_REG_NULL_CTRL 0xC9 +#define HDMI_REG_ACP_CTRL 0xCA +#define HDMI_REG_ISRC1_CTRL 0xCB +#define HDMI_REG_ISRC2_CTRL 0xCC +#define HDMI_REG_AVI_INFOFRM_CTRL 0xCD +#define HDMI_REG_AUD_INFOFRM_CTRL 0xCE +#define HDMI_REG_SPD_INFOFRM_CTRL 0xCF +#define HDMI_REG_MPG_INFOFRM_CTRL 0xD0 +#define ENABLE_PKT BIT(0) +#define REPEAT_PKT BIT(1) + +/***********************/ +/* HDMI register bank1 */ +/***********************/ + +/* AVI packet registers */ +#define HDMI_REG_AVI_DB1 0x58 +#define AVI_DB1_COLOR_SPACE 0x60 +enum { + AVI_COLOR_SPACE_RGB = 0x00, + AVI_COLOR_SPACE_YUV422 = 0x20, + AVI_COLOR_SPACE_YUV444 = 0x40, +}; + +struct it6263 { + struct i2c_client *hdmi_i2c; + struct i2c_client *lvds_i2c; + struct regmap *hdmi_regmap; + struct regmap *lvds_regmap; + struct drm_bridge bridge; + struct drm_connector connector; + struct gpio_desc *reset_gpio; + bool is_hdmi; + bool split_mode; +}; + +struct it6263_minimode { + int hdisplay; + int vdisplay; + int vrefresh; +}; + +static const struct it6263_minimode it6263_bad_mode_db[] = { + {1600, 900, 60}, + {1280, 1024, 60}, + {1280, 720, 30}, + {1280, 720, 25}, + {1280, 720, 24}, + {1152, 864, 75}, +}; + +static inline struct it6263 *bridge_to_it6263(struct drm_bridge *bridge) +{ + return container_of(bridge, struct it6263, bridge); +} + +static inline struct it6263 *connector_to_it6263(struct drm_connector *con) +{ + return container_of(con, struct it6263, connector); +} + +static inline void lvds_update_bits(struct it6263 *it6263, unsigned int reg, + unsigned int mask, unsigned int val) +{ + regmap_update_bits(it6263->lvds_regmap, reg, mask, val); +} + +static inline void hdmi_update_bits(struct it6263 *it6263, unsigned int reg, + unsigned int mask, unsigned int val) +{ + regmap_update_bits(it6263->hdmi_regmap, reg, mask, val); +} + +static void it6263_reset(struct it6263 *it6263) +{ + if (!it6263->reset_gpio) + return; + + gpiod_set_value_cansleep(it6263->reset_gpio, 0); + + usleep_range(1000, 2000); + + gpiod_set_value_cansleep(it6263->reset_gpio, 1); + + /* + * The chip maker says the low pulse should be at least 40ms, + * so 41ms is sure to be enough. + */ + usleep_range(41000, 45000); + + gpiod_set_value_cansleep(it6263->reset_gpio, 0); + + /* somehow, addtional time to wait the high voltage to be stable */ + usleep_range(5000, 6000); +} + +static void it6263_lvds_reset(struct it6263 *it6263) +{ + /* AFE PLL reset */ + lvds_update_bits(it6263, LVDS_REG_PLL, 0x1, 0x0); + usleep_range(1000, 2000); + lvds_update_bits(it6263, LVDS_REG_PLL, 0x1, 0x1); + + /* pclk reset */ + lvds_update_bits(it6263, LVDS_REG_SW_RST, + SOFT_PCLK_DM_RST, SOFT_PCLK_DM_RST); + usleep_range(1000, 2000); + lvds_update_bits(it6263, LVDS_REG_SW_RST, SOFT_PCLK_DM_RST, 0x0); + + usleep_range(1000, 2000); +} + +static void it6263_lvds_set_interface(struct it6263 *it6263) +{ + /* color depth */ + lvds_update_bits(it6263, LVDS_REG_MODE, LVDS_COLOR_DEPTH, + LVDS_COLOR_DEPTH_24); + + /* jeida mapping */ + lvds_update_bits(it6263, LVDS_REG_MODE, LVDS_OUT_MAP, JEIDA); + + if (it6263->split_mode) { + lvds_update_bits(it6263, LVDS_REG_MODE, DMODE, SPLIT_MODE); + lvds_update_bits(it6263, LVDS_REG_52, BIT(1), BIT(1)); + } else { + lvds_update_bits(it6263, LVDS_REG_MODE, DMODE, SINGLE_MODE); + lvds_update_bits(it6263, LVDS_REG_52, BIT(1), 0); + } +} + +static void it6263_lvds_set_afe(struct it6263 *it6263) +{ + struct regmap *regmap = it6263->lvds_regmap; + + regmap_write(regmap, LVDS_REG_AFE_3E, 0xaa); + regmap_write(regmap, LVDS_REG_AFE_3F, 0x02); + regmap_write(regmap, LVDS_REG_AFE_47, 0xaa); + regmap_write(regmap, LVDS_REG_AFE_48, 0x02); + regmap_write(regmap, LVDS_REG_AFE_4F, 0x11); + + lvds_update_bits(it6263, LVDS_REG_PLL, 0x07, 0); +} + +static void it6263_lvds_config(struct it6263 *it6263) +{ + it6263_lvds_reset(it6263); + it6263_lvds_set_interface(it6263); + it6263_lvds_set_afe(it6263); +} + +static void it6263_hdmi_config(struct it6263 *it6263) +{ + regmap_write(it6263->hdmi_regmap, HDMI_REG_INPUT_MODE, IN_RGB); + + hdmi_update_bits(it6263, HDMI_REG_GCP, HDMI_COLOR_DEPTH, + HDMI_COLOR_DEPTH_24); +} + +static bool it6263_hpd_is_connected(struct it6263 *it6263) +{ + unsigned int status; + + regmap_read(it6263->hdmi_regmap, HDMI_REG_SYS_STATUS, &status); + + return !!(status & HPDETECT); +} + +static enum drm_connector_status +it6263_connector_detect(struct drm_connector *connector, bool force) +{ + struct it6263 *it6263 = connector_to_it6263(connector); + int i; + + if (force) { + /* + * FIXME: We read status tens of times to workaround + * cable detection failure issue at boot time on some + * platforms. + * Spin on this for up to one second. + */ + for (i = 0; i < 100; i++) { + if (it6263_hpd_is_connected(it6263)) + return connector_status_connected; + usleep_range(5000, 10000); + } + } else { + if (it6263_hpd_is_connected(it6263)) + return connector_status_connected; + } + + return connector_status_disconnected; +} + +static const struct drm_connector_funcs it6263_connector_funcs = { + .detect = it6263_connector_detect, + .fill_modes = drm_helper_probe_single_connector_modes, + .destroy = drm_connector_cleanup, + .reset = drm_atomic_helper_connector_reset, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +static int +it6263_read_edid(void *data, u8 *buf, unsigned int block, size_t len) +{ + struct it6263 *it6263 = data; + struct regmap *regmap = it6263->hdmi_regmap; + unsigned long timeout; + unsigned int status, count, val; + unsigned int segment = block >> 1; + unsigned int start = (block % 2) * EDID_LENGTH; + + regmap_write(regmap, HDMI_REG_DDC_MASTER_CTRL, MASTER_SEL_HOST); + regmap_write(regmap, HDMI_REG_DDC_HEADER, DDC_ADDR << 1); + regmap_write(regmap, HDMI_REG_DDC_EDIDSEG, segment); + + while (len) { + /* clear DDC FIFO */ + regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_FIFO_CLR); + + timeout = jiffies + msecs_to_jiffies(10); + do { + regmap_read(regmap, HDMI_REG_DDC_STATUS, &status); + } while (!(status & DDC_DONE) && time_before(jiffies, timeout)); + + if (!(status & DDC_DONE)) { + dev_err(&it6263->hdmi_i2c->dev, + "failed to clear DDC FIFO\n"); + return -ETIMEDOUT; + } + + count = len > HDMI_DDC_FIFO_SIZE ? HDMI_DDC_FIFO_SIZE : len; + + /* fire the read command */ + regmap_write(regmap, HDMI_REG_DDC_REQOFF, start); + regmap_write(regmap, HDMI_REG_DDC_REQCOUNT, count); + regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_EDID_READ); + + start += count; + len -= count; + + /* wait for reading done */ + timeout = jiffies + msecs_to_jiffies(250); + do { + regmap_read(regmap, HDMI_REG_DDC_STATUS, &status); + if (status & DDC_ERROR) { + dev_err(&it6263->hdmi_i2c->dev, "DDC error\n"); + return -EIO; + } + } while (!(status & DDC_DONE) && time_before(jiffies, timeout)); + + if (!(status & DDC_DONE)) { + dev_err(&it6263->hdmi_i2c->dev, + "failed to read EDID\n"); + return -ETIMEDOUT; + } + + /* cache to buffer */ + for (; count > 0; count--) { + regmap_read(regmap, HDMI_REG_DDC_READFIFO, &val); + *(buf++) = val; + } + } + + return 0; +} + +static int it6263_get_modes(struct drm_connector *connector) +{ + struct it6263 *it6263 = connector_to_it6263(connector); + u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24; + struct edid *edid; + int num = 0; + int ret; + + edid = drm_do_get_edid(connector, it6263_read_edid, it6263); + drm_connector_update_edid_property(connector, edid); + if (edid) { + num = drm_add_edid_modes(connector, edid); + it6263->is_hdmi = drm_detect_hdmi_monitor(edid); + kfree(edid); + } + + ret = drm_display_info_set_bus_formats(&connector->display_info, + &bus_format, 1); + if (ret) + dev_dbg(&it6263->hdmi_i2c->dev, + "failed to set the supported bus format %d\n", ret); + + return num; +} + +static enum drm_mode_status it6263_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + const struct it6263_minimode *m; + int i, vrefresh = drm_mode_vrefresh(mode); + + if (mode->clock > 150000) + return MODE_CLOCK_HIGH; + + for (i = 0; i < ARRAY_SIZE(it6263_bad_mode_db); i++) { + m = &it6263_bad_mode_db[i]; + if ((mode->hdisplay == m->hdisplay) && + (mode->vdisplay == m->vdisplay) && + (vrefresh == m->vrefresh)) + return MODE_BAD; + } + + return MODE_OK; +} + +static const struct drm_connector_helper_funcs it6263_connector_helper_funcs = { + .get_modes = it6263_get_modes, + .mode_valid = it6263_mode_valid, +}; + +static void it6263_bridge_disable(struct drm_bridge *bridge) +{ + struct it6263 *it6263 = bridge_to_it6263(bridge); + struct regmap *regmap = it6263->hdmi_regmap; + + /* AV mute */ + hdmi_update_bits(it6263, HDMI_REG_GCP, AVMUTE, AVMUTE); + + if (it6263->is_hdmi) + regmap_write(regmap, HDMI_REG_PKT_GENERAL_CTRL, 0); + + hdmi_update_bits(it6263, HDMI_REG_SW_RST, SOFTV_RST, SOFTV_RST); + regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, AFE_DRV_RST | AFE_DRV_PWD); +} + +static void it6263_bridge_enable(struct drm_bridge *bridge) +{ + struct it6263 *it6263 = bridge_to_it6263(bridge); + struct regmap *regmap = it6263->hdmi_regmap; + unsigned long timeout; + unsigned int status; + bool is_stable = false; + int i; + + regmap_write(it6263->hdmi_regmap, HDMI_REG_BANK_CTRL, BANK_SEL(1)); + /* set the color space to RGB in the AVI packet */ + hdmi_update_bits(it6263, HDMI_REG_AVI_DB1, AVI_DB1_COLOR_SPACE, + AVI_COLOR_SPACE_RGB); + regmap_write(it6263->hdmi_regmap, HDMI_REG_BANK_CTRL, BANK_SEL(0)); + + /* software video reset */ + hdmi_update_bits(it6263, HDMI_REG_SW_RST, SOFTV_RST, SOFTV_RST); + usleep_range(1000, 2000); + hdmi_update_bits(it6263, HDMI_REG_SW_RST, SOFTV_RST, 0); + + /* reconfigure LVDS and retry several times in case video is instable */ + for (i = 0; i < 3; i++) { + timeout = jiffies + msecs_to_jiffies(500); + do { + regmap_read(regmap, HDMI_REG_SYS_STATUS, &status); + } while (!(status & TXVIDSTABLE) && + time_before(jiffies, timeout)); + + if (status & TXVIDSTABLE) { + is_stable = true; + break; + } + + it6263_lvds_config(it6263); + + dev_dbg(&it6263->hdmi_i2c->dev, + "retry to lock input video %d\n", i); + } + + if (!is_stable) + dev_warn(&it6263->hdmi_i2c->dev, + "failed to wait for video stable\n"); + + regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, 0); + + /* AV unmute */ + hdmi_update_bits(it6263, HDMI_REG_GCP, AVMUTE, 0); + + if (it6263->is_hdmi) + regmap_write(regmap, HDMI_REG_PKT_GENERAL_CTRL, + ENABLE_PKT | REPEAT_PKT); +} + +static void it6263_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adj) +{ + struct it6263 *it6263 = bridge_to_it6263(bridge); + struct regmap *regmap = it6263->hdmi_regmap; + bool pclk_high = adj->clock > 80000 ? true : false; + + regmap_write(regmap, HDMI_REG_HDMI_MODE, + it6263->is_hdmi ? TX_HDMI_MODE : TX_DVI_MODE); + + dev_dbg(&it6263->hdmi_i2c->dev, "%s mode\n", + it6263->is_hdmi ? "HDMI" : "DVI"); + + /* setup AFE */ + regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, AFE_DRV_RST); + if (pclk_high) + regmap_write(regmap, HDMI_REG_AFE_XP_CTRL, + AFE_XP_GAINBIT | AFE_XP_RESETB); + else + regmap_write(regmap, HDMI_REG_AFE_XP_CTRL, + AFE_XP_ER0 | AFE_XP_RESETB); + regmap_write(regmap, HDMI_REG_AFE_ISW_CTRL, 0x10); + if (pclk_high) + regmap_write(regmap, HDMI_REG_AFE_IP_CTRL, + AFE_IP_GAINBIT | AFE_IP_RESETB); + else + regmap_write(regmap, HDMI_REG_AFE_IP_CTRL, + AFE_IP_ER0 | AFE_IP_RESETB); +} + +static int it6263_bridge_attach(struct drm_bridge *bridge) +{ + struct it6263 *it6263 = bridge_to_it6263(bridge); + struct drm_device *drm = bridge->dev; + int ret; + + if (!drm_core_check_feature(drm, DRIVER_ATOMIC)) { + dev_err(&it6263->hdmi_i2c->dev, + "it6263 driver only copes with atomic updates\n"); + return -ENOTSUPP; + } + + it6263->connector.polled = DRM_CONNECTOR_POLL_CONNECT | + DRM_CONNECTOR_POLL_DISCONNECT; + ret = drm_connector_init(drm, &it6263->connector, + &it6263_connector_funcs, + DRM_MODE_CONNECTOR_HDMIA); + if (ret) { + dev_err(&it6263->hdmi_i2c->dev, + "Failed to initialize connector with drm\n"); + return ret; + } + + drm_connector_helper_add(&it6263->connector, + &it6263_connector_helper_funcs); + drm_connector_attach_encoder(&it6263->connector, bridge->encoder); + + return ret; +} + +static const struct drm_bridge_funcs it6263_bridge_funcs = { + .attach = it6263_bridge_attach, + .mode_set = it6263_bridge_mode_set, + .disable = it6263_bridge_disable, + .enable = it6263_bridge_enable, +}; + +static int it6263_check_chipid(struct it6263 *it6263) +{ + struct device *dev = &it6263->hdmi_i2c->dev; + u8 vendor_id[2], device_id[2]; + int ret; + + ret = regmap_bulk_read(it6263->hdmi_regmap, REG_VENDOR_ID(0), + &vendor_id, 2); + if (ret) { + dev_err(dev, "regmap_bulk_read failed %d\n", ret); + return ret; + } + + if (vendor_id[0] != HDMI_VENDER_ID_LOW || + vendor_id[1] != HDMI_VENDER_ID_HIGH) { + dev_err(dev, + "Invalid hdmi vendor id %02x %02x(expect 0x01 0xca)\n", + vendor_id[0], vendor_id[1]); + return -EINVAL; + } + + ret = regmap_bulk_read(it6263->hdmi_regmap, REG_DEVICE_ID(0), + &device_id, 2); + if (ret) { + dev_err(dev, "regmap_bulk_read failed %d\n", ret); + return ret; + } + + if (device_id[0] != HDMI_DEVICE_ID_LOW || + device_id[1] != HDMI_DEVICE_ID_HIGH) { + dev_err(dev, + "Invalid hdmi device id %02x %02x(expect 0x13 0x76)\n", + device_id[0], device_id[1]); + return -EINVAL; + } + + ret = regmap_bulk_read(it6263->lvds_regmap, REG_VENDOR_ID(0), + &vendor_id, 2); + if (ret) { + dev_err(dev, "regmap_bulk_read failed %d\n", ret); + return ret; + } + + if (vendor_id[0] != LVDS_VENDER_ID_LOW || + vendor_id[1] != LVDS_VENDER_ID_HIGH) { + dev_err(dev, + "Invalid lvds vendor id %02x %02x(expect 0x15 0xca)\n", + vendor_id[0], vendor_id[1]); + return -EINVAL; + } + + ret = regmap_bulk_read(it6263->lvds_regmap, REG_DEVICE_ID(0), + &device_id, 2); + if (ret) { + dev_err(dev, "regmap_bulk_read failed %d\n", ret); + return ret; + } + + if (device_id[0] != LVDS_DEVICE_ID_LOW || + device_id[1] != LVDS_DEVICE_ID_HIGH) { + dev_err(dev, + "Invalid lvds device id %02x %02x(expect 0x61 0x62)\n", + device_id[0], device_id[1]); + return -EINVAL; + } + + return ret; +} + +static const struct regmap_range it6263_hdmi_volatile_ranges[] = { + { .range_min = 0, .range_max = 0x1ff }, +}; + +static const struct regmap_access_table it6263_hdmi_volatile_table = { + .yes_ranges = it6263_hdmi_volatile_ranges, + .n_yes_ranges = ARRAY_SIZE(it6263_hdmi_volatile_ranges), +}; + +static const struct regmap_config it6263_hdmi_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .volatile_table = &it6263_hdmi_volatile_table, + .cache_type = REGCACHE_NONE, +}; + +static const struct regmap_range it6263_lvds_volatile_ranges[] = { + { .range_min = 0, .range_max = 0xff }, +}; + +static const struct regmap_access_table it6263_lvds_volatile_table = { + .yes_ranges = it6263_lvds_volatile_ranges, + .n_yes_ranges = ARRAY_SIZE(it6263_lvds_volatile_ranges), +}; + +static const struct regmap_config it6263_lvds_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .volatile_table = &it6263_lvds_volatile_table, + .cache_type = REGCACHE_NONE, +}; + +static int it6263_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + struct device_node *np = dev->of_node; +#if IS_ENABLED(CONFIG_OF_DYNAMIC) + struct device_node *remote_node = NULL, *endpoint = NULL; + struct of_changeset ocs; + struct property *prop; +#endif + struct it6263 *it6263; + int ret; + + it6263 = devm_kzalloc(dev, sizeof(*it6263), GFP_KERNEL); + if (!it6263) + return -ENOMEM; + + it6263->split_mode = of_property_read_bool(np, "split-mode"); + + it6263->hdmi_i2c = client; + it6263->lvds_i2c = i2c_new_dummy(client->adapter, + LVDS_INPUT_CTRL_I2C_ADDR); + if (!it6263->lvds_i2c) { + ret = -ENODEV; + goto of_reconfig; + } + + it6263->hdmi_regmap = devm_regmap_init_i2c(client, + &it6263_hdmi_regmap_config); + if (IS_ERR(it6263->hdmi_regmap)) { + ret = PTR_ERR(it6263->hdmi_regmap); + goto unregister_lvds_i2c; + } + + it6263->lvds_regmap = devm_regmap_init_i2c(it6263->lvds_i2c, + &it6263_lvds_regmap_config); + if (IS_ERR(it6263->lvds_regmap)) { + ret = PTR_ERR(it6263->lvds_regmap); + goto unregister_lvds_i2c; + } + + it6263->reset_gpio = devm_gpiod_get_optional(dev, "reset", + GPIOD_OUT_LOW); + if (IS_ERR(it6263->reset_gpio)) { + ret = PTR_ERR(it6263->reset_gpio); + + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get reset gpio: %d\n", ret); + + goto unregister_lvds_i2c; + } + + it6263_reset(it6263); + + ret = regmap_write(it6263->hdmi_regmap, HDMI_REG_SW_RST, HDMI_RST_ALL); + if (ret) + goto unregister_lvds_i2c; + + usleep_range(1000, 2000); + + ret = regmap_write(it6263->hdmi_regmap, HDMI_REG_LVDS_PORT, + LVDS_INPUT_CTRL_I2C_ADDR << 1); + if (ret) + goto unregister_lvds_i2c; + + ret = regmap_write(it6263->hdmi_regmap, HDMI_REG_LVDS_PORT_EN, 0x01); + if (ret) + goto unregister_lvds_i2c; + + /* select HDMI bank0 */ + ret = regmap_write(it6263->hdmi_regmap, HDMI_REG_BANK_CTRL, + BANK_SEL(0)); + if (ret) + goto unregister_lvds_i2c; + + ret = it6263_check_chipid(it6263); + if (ret) + goto unregister_lvds_i2c; + + it6263_lvds_config(it6263); + it6263_hdmi_config(it6263); + + it6263->bridge.funcs = &it6263_bridge_funcs; + it6263->bridge.of_node = np; + drm_bridge_add(&it6263->bridge); + + i2c_set_clientdata(client, it6263); + + return ret; + +unregister_lvds_i2c: + i2c_unregister_device(it6263->lvds_i2c); + if (ret == -EPROBE_DEFER) + return ret; + +of_reconfig: +#if IS_ENABLED(CONFIG_OF_DYNAMIC) + endpoint = of_graph_get_next_endpoint(dev->of_node, NULL); + if (endpoint) + remote_node = of_graph_get_remote_port_parent(endpoint); + + if (remote_node) { + int num_endpoints = 0; + + /* + * Remote node should have two endpoints (input and output: us) + * If remote node has more than two endpoints, probably that it + * has more outputs, so there is no need to disable it. + */ + endpoint = NULL; + while ((endpoint = of_graph_get_next_endpoint(remote_node, + endpoint))) + num_endpoints++; + + if (num_endpoints > 2) { + of_node_put(remote_node); + return ret; + } + + prop = devm_kzalloc(dev, sizeof(*prop), GFP_KERNEL); + prop->name = devm_kstrdup(dev, "status", GFP_KERNEL); + prop->value = devm_kstrdup(dev, "disabled", GFP_KERNEL); + prop->length = 9; + of_changeset_init(&ocs); + of_changeset_update_property(&ocs, remote_node, prop); + ret = of_changeset_apply(&ocs); + if (!ret) + dev_warn(dev, + "Probe failed. Remote port '%s' disabled\n", + remote_node->full_name); + + of_node_put(remote_node); + }; +#endif + + return ret; +} + +static int it6263_remove(struct i2c_client *client) + +{ + struct it6263 *it6263 = i2c_get_clientdata(client); + + drm_bridge_remove(&it6263->bridge); + i2c_unregister_device(it6263->lvds_i2c); + + return 0; +} + +static const struct of_device_id it6263_dt_ids[] = { + { .compatible = "ite,it6263", }, + { } +}; +MODULE_DEVICE_TABLE(of, it6263_dt_ids); + +static const struct i2c_device_id it6263_i2c_ids[] = { + { "it6263", 0 }, + { }, +}; +MODULE_DEVICE_TABLE(i2c, it6263_i2c_ids); + +static struct i2c_driver it6263_driver = { + .probe = it6263_probe, + .remove = it6263_remove, + .driver = { + .name = "it6263", + .of_match_table = it6263_dt_ids, + }, + .id_table = it6263_i2c_ids, +}; +module_i2c_driver(it6263_driver); + +MODULE_AUTHOR("NXP Semiconductor"); +MODULE_DESCRIPTION("ITE Tech. Inc. IT6263 LVDS->HDMI bridge"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/bridge/nwl-dsi/Kconfig b/drivers/gpu/drm/bridge/nwl-dsi/Kconfig new file mode 100644 index 00000000000000..3b157a9f2229d4 --- /dev/null +++ b/drivers/gpu/drm/bridge/nwl-dsi/Kconfig @@ -0,0 +1,16 @@ +config DRM_NWL_MIPI_DSI + tristate "Support for Northwest Logic MIPI DSI Host controller" + depends on DRM + depends on COMMON_CLK + depends on OF && HAS_IOMEM + select DRM_KMS_HELPER + select DRM_MIPI_DSI + select DRM_PANEL_BRIDGE + select GENERIC_PHY_MIPI_DPHY + select MFD_SYSCON + select MULTIPLEXER + select REGMAP_MMIO + help + This enables the Northwest Logic MIPI DSI Host controller as + for example found on NXP's i.MX8 Processors. + diff --git a/drivers/gpu/drm/bridge/nwl-dsi/Makefile b/drivers/gpu/drm/bridge/nwl-dsi/Makefile new file mode 100644 index 00000000000000..804baf2f1916bf --- /dev/null +++ b/drivers/gpu/drm/bridge/nwl-dsi/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +nwl-mipi-dsi-y := nwl-drv.o nwl-dsi.o +obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-mipi-dsi.o +header-test-y += nwl-drv.h nwl-dsi.h diff --git a/drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.c b/drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.c new file mode 100644 index 00000000000000..55ff2b3c1a58b8 --- /dev/null +++ b/drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.c @@ -0,0 +1,1283 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * i.MX8 NWL MIPI DSI host driver + * + * Copyright (C) 2017 NXP + * Copyright (C) 2019 Purism SPC + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + + +#include "nwl-drv.h" +#include "nwl-dsi.h" + +#define DRV_NAME "nwl-dsi" + +/* Possible platform specific clocks */ +#define NWL_DSI_CLK_CORE "core" +#define NWL_DSI_CLK_BYPASS "bypass" +#define NWL_DSI_CLK_PIXEL "pixel" + +/* Maximum Video PLL frequency */ +#define MAX_PLL_FREQ 1200000000 + +#define MBPS(x) ((x) * 1000000) +#define MIN_PHY_RATE MBPS(24) +#define MAX_PHY_RATE MBPS(30) + +#define DC_ID(x) IMX_SC_R_DC_ ## x +#define MIPI_ID(x) IMX_SC_R_MIPI_ ## x +#define SYNC_CTRL(x) IMX_SC_C_SYNC_CTRL ## x +#define PXL_VLD(x) IMX_SC_C_PXL_LINK_MST ## x ## _VLD +#define PXL_ADDR(x) IMX_SC_C_PXL_LINK_MST ## x ## _ADDR + +/* Possible valid PHY reference clock rates*/ +static u32 phyref_rates[] = { + 27000000, + 25000000, + 24000000, +}; + +/* + * TODO: find a better way to access imx_crtc_state + */ +struct imx_crtc_state { + struct drm_crtc_state base; + u32 bus_format; + u32 bus_flags; + int di_hsync_pin; + int di_vsync_pin; +}; + +static inline struct imx_crtc_state *to_imx_crtc_state(struct drm_crtc_state *s) +{ + return container_of(s, struct imx_crtc_state, base); +} + +enum nwl_dsi_ext_regs { + NWL_DSI_IMX_REG_GPR = BIT(1), +}; + +static const struct regmap_config nwl_dsi_regmap_config = { + .reg_bits = 16, + .val_bits = 32, + .reg_stride = 4, + .max_register = NWL_DSI_IRQ_MASK2, + .name = DRV_NAME, +}; + +struct nwl_dsi_platform_data { + int (*pclk_reset)(struct nwl_dsi *dsi, bool reset); + int (*mipi_reset)(struct nwl_dsi *dsi, bool reset); + int (*dpi_reset)(struct nwl_dsi *dsi, bool reset); + int (*select_input)(struct nwl_dsi *dsi); + int (*deselect_input)(struct nwl_dsi *dsi); + struct nwl_dsi_plat_clk_config clk_config[NWL_DSI_MAX_PLATFORM_CLOCKS]; + u32 reg_tx_ulps; + u32 reg_pxl2dpi; + u32 max_instances; + u32 tx_clk_rate; + u32 rx_clk_rate; + bool mux_present; + bool shared_phy; +}; + +static inline struct nwl_dsi *bridge_to_dsi(struct drm_bridge *bridge) +{ + return container_of(bridge, struct nwl_dsi, bridge); +} + +static unsigned long nwl_dsi_get_bit_clock(struct nwl_dsi *dsi, + unsigned long pixclock, u32 lanes) +{ + int bpp; + + if (lanes < 1 || lanes > 4) + return 0; + + bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); + + return (pixclock * bpp) / lanes; +} + +/* + * Utility function to calculate least commom multiple, using an improved + * version of the Euclidean algorithm for greatest common factor. + */ +static unsigned long nwl_dsi_get_lcm(unsigned long a, unsigned long b) +{ + u32 gcf = 0; /* greatest common factor */ + unsigned long tmp_a = a; + unsigned long tmp_b = b; + + if (!a || !b) + return 0; + + while (tmp_a % tmp_b) { + gcf = tmp_a % tmp_b; + tmp_a = tmp_b; + tmp_b = gcf; + } + + if (!gcf) + return a; + + return ((unsigned long long)a * b) / gcf; +} + +/* + * This function tries to adjust the crtc_clock for a DSI device in such a way + * that the video pll will be able to satisfy both Display Controller pixel + * clock (feeding out DPI interface) and our input phy_ref clock. + * Also, the DC pixel clock must be lower than the actual clock in order to + * have enough blanking space to send DSI commands, if the device is a panel. + */ +static void nwl_dsi_setup_pll_config(struct mode_config *config, u32 lvl) +{ + unsigned long pll_rate; + int div; + size_t i, num_rates = ARRAY_SIZE(config->phy_rates); + + config->crtc_clock = 0; + + for (i = 0; i < num_rates; i++) { + int crtc_clock; + + if (!config->phy_rates[i]) + break; + /* + * First, we need to check if phy_ref can actually be obtained + * from pixel clock. To do this, we check their lowest common + * multiple, which has to be in PLL range. + */ + pll_rate = nwl_dsi_get_lcm(config->clock, config->phy_rates[i]); + if (pll_rate > MAX_PLL_FREQ) { + /* Drop pll_rate to a realistic value */ + while (pll_rate > MAX_PLL_FREQ) + pll_rate >>= 1; + /* Make sure pll_rate can provide phy_ref rate */ + div = DIV_ROUND_UP(pll_rate, config->phy_rates[i]); + pll_rate = config->phy_rates[i] * div; + } else { + /* + * Increase the pll rate to highest possible rate for + * better accuracy. + */ + while (pll_rate <= MAX_PLL_FREQ) + pll_rate <<= 1; + pll_rate >>= 1; + } + + /* + * Next, we need to tweak the pll_rate to a value that can also + * satisfy the crtc_clock. + */ + div = DIV_ROUND_CLOSEST(pll_rate, config->clock); + if (lvl) + pll_rate -= config->phy_rates[i] * lvl; + crtc_clock = pll_rate / div; + config->pll_rates[i] = pll_rate; + + /* + * Pick a crtc_clock which is closest to pixel clock. + * Also, make sure that the pixel clock is a multiply of + * 50Hz. + */ + if (!(crtc_clock % 50) && + abs(config->clock - crtc_clock) < + abs(config->clock - config->crtc_clock)) { + config->crtc_clock = crtc_clock; + config->phy_rate_idx = i; + } + } +} + +/* + * This function will try the required phy speed for current mode + * If the phy speed can be achieved, the phy will save the speed + * configuration + */ +static struct mode_config *nwl_dsi_mode_probe(struct nwl_dsi *dsi, + const struct drm_display_mode *mode) +{ + struct device *dev = dsi->dev; + struct mode_config *config; + union phy_configure_opts phy_opts; + unsigned long clock = mode->clock * 1000; + unsigned long bit_clk = 0; + unsigned long phy_rates[3] = {0}; + int match_rates = 0; + u32 lanes = dsi->lanes; + size_t i = 0, num_rates = ARRAY_SIZE(phyref_rates); + + list_for_each_entry(config, &dsi->valid_modes, list) + if (config->clock == clock) + return config; + + phy_mipi_dphy_get_default_config(clock, + mipi_dsi_pixel_format_to_bpp(dsi->format), + lanes, &phy_opts.mipi_dphy); + phy_opts.mipi_dphy.lp_clk_rate = clk_get_rate(dsi->tx_esc_clk); + + while (i < num_rates) { + int ret; + + bit_clk = nwl_dsi_get_bit_clock(dsi, clock, lanes); + + clk_set_rate(dsi->pll_clk, phyref_rates[i] * 32); + clk_set_rate(dsi->phy_ref_clk, phyref_rates[i]); + ret = phy_validate(dsi->phy, PHY_MODE_MIPI_DPHY, 0, &phy_opts); + + /* Pick the non-failing rate, and search for more */ + if (!ret) { + phy_rates[match_rates++] = phyref_rates[i++]; + continue; + } + + if (match_rates) + break; + + /* Reached the end of phyref_rates, try another lane config */ + if ((i++ == num_rates - 1) && (--lanes > 2)) { + i = 0; + continue; + } + } + + /* + * Try swinging between min and max pll rates and see what rate (in terms + * of kHz) we can custom use to get the required bit-clock. + */ + if (!match_rates) { + int min_div, max_div; + int bit_clk_khz; + + lanes = dsi->lanes; + bit_clk = nwl_dsi_get_bit_clock(dsi, clock, lanes); + + min_div = DIV_ROUND_UP(bit_clk, MAX_PHY_RATE); + max_div = DIV_ROUND_DOWN_ULL(bit_clk, MIN_PHY_RATE); + bit_clk_khz = bit_clk / 1000; + + for (i = max_div; i > min_div; i--) { + if (!(bit_clk_khz % i)) { + phy_rates[0] = bit_clk / i; + match_rates = 1; + break; + } + } + } + + if (!match_rates) { + DRM_DEV_DEBUG_DRIVER(dev, + "Cannot setup PHY for mode: %ux%u @%d kHz\n", + mode->hdisplay, + mode->vdisplay, + mode->clock); + + return NULL; + } + + config = devm_kzalloc(dsi->dev, sizeof(struct mode_config), GFP_KERNEL); + config->clock = clock; + config->lanes = lanes; + config->bitclock = bit_clk; + memcpy(&config->phy_rates, &phy_rates, sizeof(phy_rates)); + list_add(&config->list, &dsi->valid_modes); + + return config; +} + +static int nwl_dsi_set_platform_clocks(struct nwl_dsi *dsi, bool enable) +{ + struct device *dev = dsi->dev; + const char *id; + struct clk *clk; + size_t i; + unsigned long rate; + int ret, result = 0; + + DRM_DEV_DEBUG_DRIVER(dev, "%s platform clocks\n", + enable ? "enabling" : "disabling"); + for (i = 0; i < ARRAY_SIZE(dsi->pdata->clk_config); i++) { + if (!dsi->clk_config[i].present) + continue; + id = dsi->clk_config[i].id; + clk = dsi->clk_config[i].clk; + + if (enable) { + ret = clk_prepare_enable(clk); + if (ret < 0) { + DRM_DEV_ERROR(dev, + "Failed to enable %s clk: %d\n", + id, ret); + result = result ?: ret; + } + rate = clk_get_rate(clk); + DRM_DEV_DEBUG_DRIVER(dev, "Enabled %s clk @%lu Hz\n", + id, rate); + } else { + clk_disable_unprepare(clk); + DRM_DEV_DEBUG_DRIVER(dev, "Disabled %s clk\n", id); + } + } + + return result; +} + +static void nwl_dsi_bridge_pre_enable(struct drm_bridge *bridge) +{ + struct nwl_dsi *dsi = bridge_to_dsi(bridge); + int ret; + + pm_runtime_get_sync(dsi->dev); + + dsi->pdata->dpi_reset(dsi, true); + dsi->pdata->mipi_reset(dsi, true); + dsi->pdata->pclk_reset(dsi, true); + + if (dsi->lcdif_clk) + clk_prepare_enable(dsi->lcdif_clk); + + if (nwl_dsi_set_platform_clocks(dsi, true) < 0) + return; + + /* Perform Step 1 from DSI reset-out instructions */ + ret = dsi->pdata->pclk_reset(dsi, false); + if (ret < 0) { + DRM_DEV_ERROR(dsi->dev, "Failed to deassert PCLK: %d\n", ret); + return; + } + + /* Perform Step 2 from DSI reset-out instructions */ + nwl_dsi_enable(dsi); + + /* Perform Step 3 from DSI reset-out instructions */ + ret = dsi->pdata->mipi_reset(dsi, false); + if (ret < 0) { + DRM_DEV_ERROR(dsi->dev, "Failed to deassert MIPI: %d\n", ret); + return; + } + + /* + * We need to force call enable for the panel here, in order to + * make the panel initialization execute before our call to + * bridge_enable, where we will enable the DPI and start streaming + * pixels on the data lanes. + */ + drm_bridge_enable(dsi->panel_bridge); +} + +static void nwl_dsi_bridge_enable(struct drm_bridge *bridge) +{ + struct nwl_dsi *dsi = bridge_to_dsi(bridge); + int ret; + + /* Perform Step 5 from DSI reset-out instructions */ + ret = dsi->pdata->dpi_reset(dsi, false); + if (ret < 0) + DRM_DEV_ERROR(dsi->dev, "Failed to deassert DPI: %d\n", ret); + +} + +static void nwl_dsi_bridge_disable(struct drm_bridge *bridge) +{ + struct nwl_dsi *dsi = bridge_to_dsi(bridge); + + nwl_dsi_disable(dsi); + + dsi->pdata->dpi_reset(dsi, true); + dsi->pdata->mipi_reset(dsi, true); + dsi->pdata->pclk_reset(dsi, true); + + nwl_dsi_set_platform_clocks(dsi, false); + + if (dsi->lcdif_clk) + clk_disable_unprepare(dsi->lcdif_clk); + + pm_runtime_put(dsi->dev); +} + +static int nwl_dsi_get_dphy_params(struct nwl_dsi *dsi, + const struct drm_display_mode *mode, + union phy_configure_opts *phy_opts) +{ + unsigned long rate; + int ret; + + if (dsi->lanes < 1 || dsi->lanes > 4) + return -EINVAL; + + /* + * So far the DPHY spec minimal timings work for both mixel + * dphy and nwl dsi host + */ + ret = phy_mipi_dphy_get_default_config( + mode->clock * 1000, + mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes, + &phy_opts->mipi_dphy); + if (ret < 0) + return ret; + + rate = clk_get_rate(dsi->tx_esc_clk); + DRM_DEV_DEBUG_DRIVER(dsi->dev, "LP clk is @%lu Hz\n", rate); + phy_opts->mipi_dphy.lp_clk_rate = rate; + + return 0; +} + +static bool nwl_dsi_bridge_mode_fixup(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted) +{ + struct nwl_dsi *dsi = bridge_to_dsi(bridge); + struct mode_config *config; + unsigned long pll_rate; + + DRM_DEV_DEBUG_DRIVER(dsi->dev, "Fixup mode:\n"); + drm_mode_debug_printmodeline(adjusted); + + config = nwl_dsi_mode_probe(dsi, adjusted); + if (!config) + return false; + + DRM_DEV_DEBUG_DRIVER(dsi->dev, "lanes=%u, data_rate=%lu\n", + config->lanes, config->bitclock); + if (config->lanes < 2 || config->lanes > 4) + return false; + + /* Max data rate for this controller is 1.5Gbps */ + if (config->bitclock > 1500000000) + return false; + + pll_rate = config->pll_rates[config->phy_rate_idx]; + if (dsi->pll_clk && pll_rate) { + clk_set_rate(dsi->pll_clk, pll_rate); + DRM_DEV_DEBUG_DRIVER(dsi->dev, + "Video pll rate: %lu (actual: %lu)", + pll_rate, clk_get_rate(dsi->pll_clk)); + } + /* Update the crtc_clock to be used by display controller */ + if (config->crtc_clock) + adjusted->crtc_clock = config->crtc_clock / 1000; + else if (dsi->clk_drop_lvl) { + int div; + unsigned long phy_ref_rate; + + phy_ref_rate = config->phy_rates[config->phy_rate_idx]; + pll_rate = config->bitclock; + div = DIV_ROUND_CLOSEST(pll_rate, config->clock); + pll_rate -= phy_ref_rate * dsi->clk_drop_lvl; + adjusted->crtc_clock = (pll_rate / div) / 1000; + } + + if (!dsi->use_dcss) { + /* LCDIF + NWL needs active high sync */ + adjusted->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); + adjusted->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); + } else { + adjusted->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); + adjusted->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); + } + + return true; +} + +static enum drm_mode_status +nwl_dsi_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_mode *mode) +{ + struct nwl_dsi *dsi = bridge_to_dsi(bridge); + struct mode_config *config; + unsigned long pll_rate; + int bit_rate; + + bit_rate = nwl_dsi_get_bit_clock(dsi, mode->clock * 1000, dsi->lanes); + + DRM_DEV_DEBUG_DRIVER(dsi->dev, "Validating mode:"); + drm_mode_debug_printmodeline(mode); + + if (bit_rate > MBPS(1500)) + return MODE_CLOCK_HIGH; + + if (bit_rate < MBPS(80)) + return MODE_CLOCK_LOW; + + config = nwl_dsi_mode_probe(dsi, mode); + if (!config) + return MODE_NOCLOCK; + + pll_rate = config->pll_rates[config->phy_rate_idx]; + if (dsi->pll_clk && !pll_rate) + nwl_dsi_setup_pll_config(config, dsi->clk_drop_lvl); + + return MODE_OK; +} + +static void +nwl_dsi_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted) +{ + struct nwl_dsi *dsi = bridge_to_dsi(bridge); + struct device *dev = dsi->dev; + union phy_configure_opts new_cfg; + unsigned long phy_ref_rate; + struct mode_config *config; + size_t i; + const char *id; + struct clk *clk; + int ret; + + DRM_DEV_DEBUG_DRIVER(dsi->dev, "Setting mode:\n"); + drm_mode_debug_printmodeline(adjusted); + + config = nwl_dsi_mode_probe(dsi, adjusted); + /* New mode? This should NOT happen */ + if (!config) { + DRM_DEV_ERROR(dsi->dev, "Unsupported mode provided:\n"); + drm_mode_debug_printmodeline(adjusted); + return; + } + + for (i = 0; i < ARRAY_SIZE(dsi->pdata->clk_config); i++) { + if (!dsi->clk_config[i].present) + continue; + id = dsi->clk_config[i].id; + clk = dsi->clk_config[i].clk; + + /* Set bypass and pixel clocks to mode clock rate */ + if (!strcmp(id, NWL_DSI_CLK_BYPASS) || + !strcmp(id, NWL_DSI_CLK_PIXEL)) + clk_set_rate(clk, adjusted->crtc_clock * 1000); + } + + memcpy(&dsi->mode, adjusted, sizeof(dsi->mode)); + + phy_ref_rate = config->phy_rates[config->phy_rate_idx]; + clk_set_rate(dsi->phy_ref_clk, phy_ref_rate); + ret = nwl_dsi_get_dphy_params(dsi, adjusted, &new_cfg); + if (ret < 0) + return; + + /* + * If hs clock is unchanged, we're all good - all parameters are + * derived from it atm. + */ + if (new_cfg.mipi_dphy.hs_clk_rate == dsi->phy_cfg.mipi_dphy.hs_clk_rate) + return; + + DRM_DEV_DEBUG_DRIVER(dev, + "PHY at ref rate: %lu (actual: %lu)\n", + phy_ref_rate, clk_get_rate(dsi->phy_ref_clk)); + /* Save the new desired phy config */ + memcpy(&dsi->phy_cfg, &new_cfg, sizeof(new_cfg)); + +} + +static int nwl_dsi_bridge_attach(struct drm_bridge *bridge) +{ + struct nwl_dsi *dsi = bridge->driver_private; + struct drm_bridge *panel_bridge; + struct drm_panel *panel; + struct clk *phy_parent; + int ret; + + ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 1, 0, &panel, + &panel_bridge); + if (ret) + return ret; + + if (panel) { + panel_bridge = drm_panel_bridge_add(panel, + DRM_MODE_CONNECTOR_DSI); + if (IS_ERR(panel_bridge)) + return PTR_ERR(panel_bridge); + } + + dsi->panel_bridge = panel_bridge; + + if (!dsi->panel_bridge) + return -EPROBE_DEFER; + + phy_parent = devm_clk_get(dsi->dev, "phy_parent"); + if (!IS_ERR_OR_NULL(phy_parent)) { + ret = clk_set_parent(dsi->phy_ref_clk, phy_parent); + ret |= clk_set_parent(dsi->tx_esc_clk, phy_parent); + ret |= clk_set_parent(dsi->rx_esc_clk, phy_parent); + + if (ret) { + dev_err(dsi->dev, + "Error re-parenting phy/tx/rx clocks: %d", + ret); + + return ret; + } + + if (dsi->pdata->tx_clk_rate) + clk_set_rate(dsi->tx_esc_clk, dsi->pdata->tx_clk_rate); + + if (dsi->pdata->rx_clk_rate) + clk_set_rate(dsi->rx_esc_clk, dsi->pdata->rx_clk_rate); + } + + return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge); +} + +static void nwl_dsi_bridge_detach(struct drm_bridge *bridge) +{ + struct nwl_dsi *dsi = bridge->driver_private; + + drm_of_panel_bridge_remove(dsi->dev->of_node, 1, 0); +} + +static const struct drm_bridge_funcs nwl_dsi_bridge_funcs = { + .pre_enable = nwl_dsi_bridge_pre_enable, + .enable = nwl_dsi_bridge_enable, + .disable = nwl_dsi_bridge_disable, + .mode_fixup = nwl_dsi_bridge_mode_fixup, + .mode_set = nwl_dsi_bridge_mode_set, + .mode_valid = nwl_dsi_bridge_mode_valid, + .attach = nwl_dsi_bridge_attach, + .detach = nwl_dsi_bridge_detach, +}; + +static void nwl_dsi_encoder_destroy(struct drm_encoder *encoder) +{ + drm_encoder_cleanup(encoder); +} + +static const struct drm_encoder_funcs nwl_dsi_encoder_funcs = { + .destroy = nwl_dsi_encoder_destroy, +}; + +static int nwl_dsi_parse_dt(struct nwl_dsi *dsi) +{ + struct device_node *np = dsi->dev->of_node; + struct platform_device *pdev = to_platform_device(dsi->dev); + struct clk *clk; + const char *clk_id; + void __iomem *base; + int i, ret, id; + + dsi->phy = devm_phy_get(dsi->dev, "dphy"); + if (IS_ERR(dsi->phy)) { + ret = PTR_ERR(dsi->phy); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dsi->dev, "Could not get PHY: %d\n", ret); + return ret; + } + + id = of_alias_get_id(np, "mipi_dsi"); + if (id > 0) { + if (id > dsi->pdata->max_instances - 1) { + dev_err(dsi->dev, + "Too many instances! (cur: %d, max: %d)\n", + id, dsi->pdata->max_instances); + return -ENODEV; + } + dsi->instance = id; + } + + /* Platform dependent clocks */ + memcpy(dsi->clk_config, dsi->pdata->clk_config, + sizeof(dsi->pdata->clk_config)); + + for (i = 0; i < ARRAY_SIZE(dsi->pdata->clk_config); i++) { + if (!dsi->clk_config[i].present) + continue; + + clk_id = dsi->clk_config[i].id; + clk = devm_clk_get(dsi->dev, clk_id); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + DRM_DEV_ERROR(dsi->dev, "Failed to get %s clock: %d\n", + clk_id, ret); + return ret; + } + DRM_DEV_DEBUG_DRIVER(dsi->dev, "Setup clk %s (rate: %lu)\n", + clk_id, clk_get_rate(clk)); + dsi->clk_config[i].clk = clk; + } + + /* DSI clocks */ + clk = devm_clk_get(dsi->dev, "phy_ref"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + DRM_DEV_ERROR(dsi->dev, "Failed to get phy_ref clock: %d\n", + ret); + return ret; + } + dsi->phy_ref_clk = clk; + + clk = devm_clk_get(dsi->dev, "rx_esc"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + DRM_DEV_ERROR(dsi->dev, "Failed to get rx_esc clock: %d\n", + ret); + return ret; + } + dsi->rx_esc_clk = clk; + + clk = devm_clk_get(dsi->dev, "tx_esc"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + DRM_DEV_ERROR(dsi->dev, "Failed to get tx_esc clock: %d\n", + ret); + return ret; + } + dsi->tx_esc_clk = clk; + + /* The video_pll clock is optional */ + clk = devm_clk_get(dsi->dev, "video_pll"); + if (!IS_ERR(clk)) + dsi->pll_clk = clk; + + /* + * Usually, we don't need this clock here, but due to a design issue, + * the MIPI Reset Synchronizer block depends on this clock. So, we will + * use this clock when we need to reset (or take out of reset) MIPI PHY + */ + dsi->lcdif_clk = devm_clk_get(dsi->dev, "lcdif"); + if (IS_ERR(dsi->lcdif_clk)) + dsi->lcdif_clk = NULL; + + if (dsi->pdata->mux_present) { + dsi->mux = devm_mux_control_get(dsi->dev, NULL); + if (IS_ERR(dsi->mux)) { + ret = PTR_ERR(dsi->mux); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dsi->dev, + "Failed to get mux: %d\n", ret); + return ret; + } + } + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + dsi->regmap = + devm_regmap_init_mmio(dsi->dev, base, &nwl_dsi_regmap_config); + if (IS_ERR(dsi->regmap)) { + ret = PTR_ERR(dsi->regmap); + DRM_DEV_ERROR(dsi->dev, "Failed to create NWL DSI regmap: %d\n", + ret); + return ret; + } + + /* For these two regs we need a mapping to MIPI-DSI CSR */ + if (dsi->pdata->reg_tx_ulps || dsi->pdata->reg_pxl2dpi) { + dsi->csr = syscon_regmap_lookup_by_phandle(np, "csr"); + if (IS_ERR(dsi->csr)) { + ret = PTR_ERR(dsi->csr); + dev_err(dsi->dev, + "Failed to get CSR regmap: %d\n", ret); + return ret; + } + } + + dsi->irq = platform_get_irq(pdev, 0); + if (dsi->irq < 0) { + if (dsi->irq != -EPROBE_DEFER) + DRM_DEV_ERROR(dsi->dev, + "Failed to get device IRQ: %d\n", + dsi->irq); + return dsi->irq; + } + + /* + * Wee need to manage individual resets, since the order of their usage + * really matters to DSI Host Controller. The order of operation, + * should be like this: + * 1. Deassert pclk reset (this is needed to have access to DSI regs) + * 2. Configure DSI Host and DPHY and enable DPHY + * 3. Deassert ESC and BYTE resets (needed for Host TX operations) + * 4. Send DSI cmds (if the DSI peripheral needs configuration) + * 5. Deassert DPI reset (deasserting DPI reset, enables DPI to receive + * DPI pixels and start streamming DSI data) + */ + dsi->rst_pclk = __devm_reset_control_get(dsi->dev, + "pclk", 0, false, true, true); + if (IS_ERR(dsi->rst_pclk)) { + DRM_DEV_ERROR(dsi->dev, "Failed to get pclk reset: %ld\n", + PTR_ERR(dsi->rst_pclk)); + return PTR_ERR(dsi->rst_pclk); + } + dsi->rst_byte = __devm_reset_control_get(dsi->dev, + "byte", 0, false, true, true); + if (IS_ERR(dsi->rst_byte)) { + DRM_DEV_ERROR(dsi->dev, "Failed to get byte reset: %ld\n", + PTR_ERR(dsi->rst_byte)); + return PTR_ERR(dsi->rst_byte); + } + dsi->rst_esc = __devm_reset_control_get(dsi->dev, + "esc", 0, false, true, true); + if (IS_ERR(dsi->rst_esc)) { + DRM_DEV_ERROR(dsi->dev, "Failed to get esc reset: %ld\n", + PTR_ERR(dsi->rst_esc)); + return PTR_ERR(dsi->rst_esc); + } + dsi->rst_dpi = __devm_reset_control_get(dsi->dev, + "dpi", 0, false, true, true); + if (IS_ERR(dsi->rst_dpi)) { + DRM_DEV_ERROR(dsi->dev, "Failed to get dpi reset: %ld\n", + PTR_ERR(dsi->rst_dpi)); + return PTR_ERR(dsi->rst_dpi); + } + + of_property_read_u32(np, "fsl,clock-drop-level", &dsi->clk_drop_lvl); + + return 0; +} + +static int imx8mq_dsi_pclk_reset(struct nwl_dsi *dsi, bool reset) +{ + int ret = 0; + + if (dsi->rst_pclk) { + if (reset) + ret = reset_control_assert(dsi->rst_pclk); + else + ret = reset_control_deassert(dsi->rst_pclk); + } + + return ret; + +} + +static int imx8mq_dsi_mipi_reset(struct nwl_dsi *dsi, bool reset) +{ + int ret = 0; + + if (dsi->rst_esc) { + if (reset) + ret = reset_control_assert(dsi->rst_esc); + else + ret = reset_control_deassert(dsi->rst_esc); + } + + if (dsi->rst_byte) { + if (reset) + ret = reset_control_assert(dsi->rst_byte); + else + ret = reset_control_deassert(dsi->rst_byte); + } + + return ret; + +} + +static int imx8mq_dsi_dpi_reset(struct nwl_dsi *dsi, bool reset) +{ + int ret = 0; + + if (dsi->rst_dpi) { + if (reset) + ret = reset_control_assert(dsi->rst_dpi); + else + ret = reset_control_deassert(dsi->rst_dpi); + } + + return ret; + +} + +static int imx8mq_dsi_select_input(struct nwl_dsi *dsi) +{ + struct device_node *remote; + u32 use_dcss = 1; + int ret; + + remote = of_graph_get_remote_node(dsi->dev->of_node, 0, 0); + if (strcmp(remote->name, "lcdif") == 0) + use_dcss = 0; + + DRM_DEV_INFO(dsi->dev, "Using %s as input source\n", + (use_dcss) ? "DCSS" : "LCDIF"); + + ret = mux_control_try_select(dsi->mux, use_dcss); + if (ret < 0) + DRM_DEV_ERROR(dsi->dev, "Failed to select input: %d\n", ret); + + of_node_put(remote); + + dsi->use_dcss = use_dcss; + + return ret; +} + +static int imx8mq_dsi_deselect_input(struct nwl_dsi *dsi) +{ + int ret; + + ret = mux_control_deselect(dsi->mux); + if (ret < 0) + DRM_DEV_ERROR(dsi->dev, "Failed to deselect input: %d\n", ret); + + return ret; +} + +static int imx8q_dsi_pclk_reset(struct nwl_dsi *dsi, bool reset) +{ + struct imx_sc_ipc *handle; + u32 mipi_id, dc_id; + u8 ctrl; + bool shared_phy = dsi->pdata->shared_phy; + int ret = 0; + + ret = imx_scu_get_handle(&handle); + if (ret) { + DRM_DEV_ERROR(dsi->dev, + "Failed to get scu ipc handle (%d)\n", ret); + return ret; + } + + mipi_id = (dsi->instance)?MIPI_ID(1):MIPI_ID(0); + dc_id = (!shared_phy && dsi->instance)?DC_ID(1):DC_ID(0); + DRM_DEV_DEBUG_DRIVER(dsi->dev, + "Power %s PCLK MIPI:%u DC:%u\n", + (reset)?"OFF":"ON", mipi_id, dc_id); + + if (shared_phy) { + ret |= imx_sc_misc_set_control(handle, + mipi_id, IMX_SC_C_MODE, reset); + ret |= imx_sc_misc_set_control(handle, + mipi_id, IMX_SC_C_DUAL_MODE, reset); + ret |= imx_sc_misc_set_control(handle, + mipi_id, IMX_SC_C_PXL_LINK_SEL, reset); + } + + /* Initialize Pixel Link */ + ctrl = (shared_phy && dsi->instance)?PXL_ADDR(2):PXL_ADDR(1); + ret |= imx_sc_misc_set_control(handle, dc_id, ctrl, reset); + + ctrl = (shared_phy && dsi->instance)?PXL_VLD(2):PXL_VLD(1); + ret |= imx_sc_misc_set_control(handle, dc_id, ctrl, !reset); + + ctrl = (shared_phy && dsi->instance)?SYNC_CTRL(1):SYNC_CTRL(0); + ret |= imx_sc_misc_set_control(handle, dc_id, ctrl, !reset); + + return ret; +} + +static int imx8q_dsi_mipi_reset(struct nwl_dsi *dsi, bool reset) +{ + struct imx_sc_ipc *handle; + u32 mipi_id; + int ret = 0; + + ret = imx_scu_get_handle(&handle); + if (ret) { + DRM_DEV_ERROR(dsi->dev, + "Failed to get scu ipc handle (%d)\n", ret); + return ret; + } + + mipi_id = (dsi->instance)?MIPI_ID(1):MIPI_ID(0); + DRM_DEV_DEBUG_DRIVER(dsi->dev, + "Power %s HOST MIPI:%u\n", + (reset)?"OFF":"ON", mipi_id); + + ret |= imx_sc_misc_set_control(handle, mipi_id, + IMX_SC_C_PHY_RESET, !reset); + ret |= imx_sc_misc_set_control(handle, mipi_id, + IMX_SC_C_MIPI_RESET, !reset); + + return ret; +} + +static int imx8q_dsi_dpi_reset(struct nwl_dsi *dsi, bool reset) +{ + struct imx_sc_ipc *handle; + u32 mipi_id; + int ret = 0; + + ret = imx_scu_get_handle(&handle); + if (ret) { + DRM_DEV_ERROR(dsi->dev, + "Failed to get scu ipc handle (%d)\n", ret); + return ret; + } + + mipi_id = (dsi->instance)?MIPI_ID(1):MIPI_ID(0); + DRM_DEV_DEBUG_DRIVER(dsi->dev, + "Power %s DPI MIPI:%u\n", + (reset)?"OFF":"ON", mipi_id); + + regmap_write(dsi->csr, dsi->pdata->reg_tx_ulps, 0); + regmap_write(dsi->csr, dsi->pdata->reg_pxl2dpi, NWL_DSI_DPI_24_BIT); + + ret |= imx_sc_misc_set_control(handle, mipi_id, + IMX_SC_C_DPI_RESET, !reset); + + return ret; +} + +static const struct drm_bridge_timings nwl_dsi_timings = { + .input_bus_flags = DRM_BUS_FLAG_DE_LOW, +}; + +static const struct nwl_dsi_platform_data imx8mq_dev = { + .pclk_reset = &imx8mq_dsi_pclk_reset, + .mipi_reset = &imx8mq_dsi_mipi_reset, + .dpi_reset = &imx8mq_dsi_dpi_reset, + .select_input = &imx8mq_dsi_select_input, + .deselect_input = &imx8mq_dsi_deselect_input, + .clk_config = { + { .id = NWL_DSI_CLK_CORE, .present = true }, + }, + .mux_present = true, +}; + +static const struct nwl_dsi_platform_data imx8qm_dev = { + .pclk_reset = &imx8q_dsi_pclk_reset, + .mipi_reset = &imx8q_dsi_mipi_reset, + .dpi_reset = &imx8q_dsi_dpi_reset, + .clk_config = { + { .id = NWL_DSI_CLK_BYPASS, .present = true }, + { .id = NWL_DSI_CLK_PIXEL, .present = true }, + }, + .reg_tx_ulps = 0x00, + .reg_pxl2dpi = 0x04, + .max_instances = 2, + .tx_clk_rate = 18000000, + .rx_clk_rate = 72000000, + .shared_phy = false, +}; + +static const struct nwl_dsi_platform_data imx8qx_dev = { + .pclk_reset = &imx8q_dsi_pclk_reset, + .mipi_reset = &imx8q_dsi_mipi_reset, + .dpi_reset = &imx8q_dsi_dpi_reset, + .clk_config = { + { .id = NWL_DSI_CLK_BYPASS, .present = true }, + { .id = NWL_DSI_CLK_PIXEL, .present = true }, + }, + .reg_tx_ulps = 0x30, + .reg_pxl2dpi = 0x40, + .max_instances = 2, + .tx_clk_rate = 18000000, + .rx_clk_rate = 72000000, + .shared_phy = true, +}; + +static const struct of_device_id nwl_dsi_dt_ids[] = { + { .compatible = "fsl,imx8mq-nwl-dsi", .data = &imx8mq_dev, }, + { .compatible = "fsl,imx8qm-nwl-dsi", .data = &imx8qm_dev, }, + { .compatible = "fsl,imx8qx-nwl-dsi", .data = &imx8qx_dev, }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, nwl_dsi_dt_ids); + +static const struct soc_device_attribute nwl_dsi_quirks_match[] = { + { .soc_id = "i.MX8MQ", .revision = "2.0", + .data = (void *)(E11418_HS_MODE_QUIRK | SRC_RESET_QUIRK) }, + { /* sentinel. */ }, +}; + +static int nwl_dsi_encoder_atomic_check(struct drm_encoder *encoder, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state); + + imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB101010_1X30; + + return 0; +} + +static const struct drm_encoder_helper_funcs nwl_dsi_encoder_helper_funcs = { + .atomic_check = nwl_dsi_encoder_atomic_check, +}; + +static int nwl_dsi_bind(struct device *dev, + struct device *master, + void *data) +{ + struct drm_device *drm = data; + uint32_t crtc_mask; + struct nwl_dsi *dsi = dev_get_drvdata(dev); + int ret = 0; + + crtc_mask = drm_of_find_possible_crtcs(drm, dev->of_node); + /* + * If we failed to find the CRTC(s) which this encoder is + * supposed to be connected to, it's because the CRTC has + * not been registered yet. Defer probing, and hope that + * the required CRTC is added later. + */ + if (crtc_mask == 0) + return -EPROBE_DEFER; + + DRM_DEV_DEBUG_DRIVER(dev, "id = %s\n", (dsi->instance)?"DSI1":"DSI0"); + + dsi->encoder.possible_crtcs = crtc_mask; + dsi->encoder.possible_clones = ~0; + + drm_encoder_helper_add(&dsi->encoder, + &nwl_dsi_encoder_helper_funcs); + ret = drm_encoder_init(drm, + &dsi->encoder, + &nwl_dsi_encoder_funcs, + DRM_MODE_ENCODER_DSI, + NULL); + if (ret) { + DRM_DEV_ERROR(dev, "failed to init DSI encoder (%d)\n", ret); + return ret; + } + + ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL); + if (ret) + drm_encoder_cleanup(&dsi->encoder); + + /* + * -ENODEV is returned when there is no node connected to us. Since + * it might be disabled because the device is not actually connected, + * just cleanup and return 0. + */ + if (ret == -ENODEV) + return 0; + + return ret; +} + +static void nwl_dsi_unbind(struct device *dev, + struct device *master, + void *data) +{ + struct nwl_dsi *dsi = dev_get_drvdata(dev); + + DRM_DEV_DEBUG_DRIVER(dev, "id = %s\n", (dsi->instance)?"DSI1":"DSI0"); + + if (dsi->encoder.dev) + drm_encoder_cleanup(&dsi->encoder); +} + +static const struct component_ops nwl_dsi_component_ops = { + .bind = nwl_dsi_bind, + .unbind = nwl_dsi_unbind, +}; + +static int nwl_dsi_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct of_device_id *of_id = of_match_device(nwl_dsi_dt_ids, dev); + const struct nwl_dsi_platform_data *pdata = of_id->data; + const struct soc_device_attribute *attr; + struct nwl_dsi *dsi; + int ret; + + dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); + if (!dsi) + return -ENOMEM; + + dsi->dev = dev; + dsi->pdata = pdata; + + attr = soc_device_match(nwl_dsi_quirks_match); + if (attr) + dsi->quirks = (uintptr_t)attr->data; + + ret = nwl_dsi_parse_dt(dsi); + if (ret) + return ret; + + ret = devm_request_irq(dev, dsi->irq, nwl_dsi_irq_handler, 0, + dev_name(dev), dsi); + if (ret < 0) { + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, "Failed to request IRQ %d: %d\n", + dsi->irq, ret); + return ret; + } + + dsi->dsi_host.ops = &nwl_dsi_host_ops; + dsi->dsi_host.dev = dev; + ret = mipi_dsi_host_register(&dsi->dsi_host); + if (ret) { + DRM_DEV_ERROR(dev, "Failed to register MIPI host: %d\n", ret); + return ret; + } + + dsi->bridge.driver_private = dsi; + dsi->bridge.funcs = &nwl_dsi_bridge_funcs; + dsi->bridge.of_node = dev->of_node; + dsi->bridge.timings = &nwl_dsi_timings; + + if (dsi->pdata->select_input) + dsi->pdata->select_input(dsi); + + drm_bridge_add(&dsi->bridge); + + INIT_LIST_HEAD(&dsi->valid_modes); + + dev_set_drvdata(dev, dsi); + pm_runtime_enable(dev); + + if (of_property_read_bool(dev->of_node, "use-disp-ss")) + ret = component_add(&pdev->dev, &nwl_dsi_component_ops); + + if (ret) { + pm_runtime_disable(dev); + drm_bridge_remove(&dsi->bridge); + mipi_dsi_host_unregister(&dsi->dsi_host); + return ret; + } + + return ret; +} + +static int nwl_dsi_remove(struct platform_device *pdev) +{ + struct nwl_dsi *dsi = platform_get_drvdata(pdev); + struct mode_config *config; + struct list_head *pos, *tmp; + + list_for_each_safe(pos, tmp, &dsi->valid_modes) { + config = list_entry(pos, struct mode_config, list); + list_del(pos); + devm_kfree(dsi->dev, config); + } + + pm_runtime_disable(&pdev->dev); + drm_bridge_remove(&dsi->bridge); + mipi_dsi_host_unregister(&dsi->dsi_host); + + return 0; +} + +static struct platform_driver nwl_dsi_driver = { + .probe = nwl_dsi_probe, + .remove = nwl_dsi_remove, + .driver = { + .of_match_table = nwl_dsi_dt_ids, + .name = DRV_NAME, + }, +}; + +module_platform_driver(nwl_dsi_driver); + +MODULE_AUTHOR("NXP Semiconductor"); +MODULE_AUTHOR("Purism SPC"); +MODULE_DESCRIPTION("Northwest Logic MIPI-DSI driver"); +MODULE_LICENSE("GPL"); /* GPLv2 or later */ diff --git a/drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.h b/drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.h new file mode 100644 index 00000000000000..8c9cd107471008 --- /dev/null +++ b/drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * NWL MIPI DSI host driver + * + * Copyright (C) 2017 NXP + * Copyright (C) 2019 Purism SPC + */ + +#ifndef __NWL_DRV_H__ +#define __NWL_DRV_H__ + +#include +#include + +#include +#include + +struct nwl_dsi_platform_data; + +/* i.MX8 NWL quirks */ +/* i.MX8MQ errata E11418 */ +#define E11418_HS_MODE_QUIRK BIT(0) +/* Skip DSI bits in SRC on disable to avoid blank display on enable */ +#define SRC_RESET_QUIRK BIT(1) + +/* * DPI color coding */ +#define NWL_DSI_DPI_16_BIT_565_PACKED 0 +#define NWL_DSI_DPI_16_BIT_565_ALIGNED 1 +#define NWL_DSI_DPI_16_BIT_565_SHIFTED 2 +#define NWL_DSI_DPI_18_BIT_PACKED 3 +#define NWL_DSI_DPI_18_BIT_ALIGNED 4 +#define NWL_DSI_DPI_24_BIT 5 + + +#define NWL_DSI_MAX_PLATFORM_CLOCKS 2 +struct nwl_dsi_plat_clk_config { + const char *id; + struct clk *clk; + bool present; +}; + +struct mode_config { + int clock; + int crtc_clock; + unsigned int lanes; + unsigned long bitclock; + unsigned long phy_rates[3]; + unsigned long pll_rates[3]; + int phy_rate_idx; + struct list_head list; +}; + +struct nwl_dsi { + struct drm_encoder encoder; + struct drm_bridge bridge; + struct mipi_dsi_host dsi_host; + struct drm_bridge *panel_bridge; + struct device *dev; + struct phy *phy; + union phy_configure_opts phy_cfg; + unsigned int quirks; + unsigned int instance; + + struct regmap *regmap; + struct regmap *csr; + int irq; + struct reset_control *rst_byte; + struct reset_control *rst_esc; + struct reset_control *rst_dpi; + struct reset_control *rst_pclk; + struct mux_control *mux; + + /* DSI clocks */ + struct clk *phy_ref_clk; + struct clk *rx_esc_clk; + struct clk *tx_esc_clk; + struct clk *pll_clk; + struct clk *lcdif_clk; + /* Platform dependent clocks */ + struct nwl_dsi_plat_clk_config clk_config[NWL_DSI_MAX_PLATFORM_CLOCKS]; + + struct list_head valid_modes; + /* dsi lanes */ + u32 lanes; + u32 clk_drop_lvl; + enum mipi_dsi_pixel_format format; + struct drm_display_mode mode; + unsigned long dsi_mode_flags; + + struct nwl_dsi_transfer *xfer; + + const struct nwl_dsi_platform_data *pdata; + + bool use_dcss; +}; + +#endif /* __NWL_DRV_H__ */ diff --git a/drivers/gpu/drm/bridge/nwl-dsi/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi/nwl-dsi.c new file mode 100644 index 00000000000000..b8aa539a0473d6 --- /dev/null +++ b/drivers/gpu/drm/bridge/nwl-dsi/nwl-dsi.c @@ -0,0 +1,684 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NWL MIPI DSI host driver + * + * Copyright (C) 2017 NXP + * Copyright (C) 2019 Purism SPC + */ + +#include +#include +#include +#include +#include + +#include