diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index 09326ffaee5216..8a4edaf2cee1f6 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -51,6 +51,9 @@ Optional properties: The regulator will be enabled when initializing the PCIe host and disabled either as part of the init process or when shutting down the host. +- vph-supply: Should specify the regulator in charge of VPH one of the three + PCIe PHY powers. This regulator can be supplied by both 1.8v and 3.3v voltage + supplies. Might be used to distinguish different HW board designs. - ext_osc: use the external oscillator as ref clock( 1: external OSC is used, 0 internal PLL is used). - hard_wired: the PCIe port is hard wired to the EP device(0: one slot @@ -60,6 +63,9 @@ Optional properties: - interrupt-names: Optional include the following entries: - "dma": The interrupt that is asserted when an DMA interrupter is received +- l1ss-disabled: Force to disable L1SS or not. If present then the L1 + substate would be force disabled although it might be supported by the + chip. Additional required properties for imx6sx-pcie: - clock names: Must include the following additional entries: @@ -83,6 +89,11 @@ Additional required properties for imx8mq-pcie: - clock-names: Must include the following additional entries: - "pcie_aux" +Additional required properties to enable L1sub for imx8mq-pcie, imx8mm-pcie +and imx8mp-pcie: +- reset-names: Must contain the following entries: + - "clkreq" + Additional required properties for imx8 pcie: - hsio-cfg: hsio configration mode when the pcie node is supported. mode 1: pciea 2 lanes and one sata ahci port. diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 27d3bbdc67489f..3e9642a8514f51 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -72,7 +72,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb imx8mp-evk-root.dtb imx8mp-evk-inmate.d imx8mp-evk-jdi-wuxga-lvds-panel.dtb imx8mp-ab2.dtb imx8mp-evk-sof-wm8960.dtb \ imx8mp-evk-dsp.dtb imx8mp-evk-ov2775.dtb imx8mp-evk-basler.dtb imx8mp-evk-pcie-ep.dtb \ imx8mp-evk-spdif-lb.dtb imx8mp-evk-dsp-lpa.dtb imx8mp-evk-ov2775-ov5640.dtb \ - imx8mp-evk-basler-ov5640.dtb imx8mp-evk-dual-ov2775.dtb + imx8mp-evk-basler-ov5640.dtb imx8mp-evk-dual-ov2775.dtb \ + imx8mp-evk-basler-ov2775.dtb imx8mp-evk-dual-basler.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb imx8mq-evk-rpmsg.dtb imx8mq-evk-pcie1-m2.dtb imx8mq-evk-usd-wifi.dtb \ imx8mq-evk-usdhc2-m2.dtb imx8mq-evk-pcie-ep.dtb @@ -97,6 +98,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb imx8qm-mek-ov5640.dtb \ imx8qm-mek-jdi-wuxga-lvds1-panel.dtb \ imx8qm-mek-jdi-wuxga-lvds1-panel-rpmsg.dtb \ imx8qm-mek-usdhc3-m2.dtb imx8qm-mek-usd-wifi.dtb \ + imx8qm-mek-dp.dtb \ imx8qm-lpddr4-val.dtb imx8qm-lpddr4-val-mqs.dtb \ imx8qm-lpddr4-val-spdif.dtb imx8qm-mek-ca53.dtb \ imx8qm-mek-ca72.dtb imx8qm-lpddr4-val-ca53.dtb \ diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index 9d06d25a2d8fad..2df401327313de 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -343,6 +343,7 @@ reg = <0x20>; gpio-controller; #gpio-cells = <2>; + power-domains = <&pd IMX_SC_R_BOARD_R1>; }; pca6416_2: gpio@21 { @@ -350,6 +351,7 @@ reg = <0x21>; gpio-controller; #gpio-cells = <2>; + power-domains = <&pd IMX_SC_R_BOARD_R2>; }; pca9548_1: pca9548@70 { @@ -357,6 +359,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x70>; + power-domains = <&pd IMX_SC_R_BOARD_R0>; i2c@0 { #address-cells = <1>; @@ -467,6 +470,7 @@ #gpio-cells = <2>; interrupt-parent = <&lsio_gpio2>; interrupts = <5 IRQ_TYPE_EDGE_RISING>; + power-domains = <&pd IMX_SC_R_BOARD_R4>; }; pca9548_2: pca9548@70 { @@ -474,6 +478,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x70>; + power-domains = <&pd IMX_SC_R_BOARD_R3>; i2c@0 { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts index 08bfdda7cdba02..d767cc4490a68c 100755 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts @@ -230,7 +230,15 @@ <&clk IMX8MM_CLK_PCIE1_PHY>, <&pcie0_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <100000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_100M>, + <&clk IMX8MM_SYS_PLL2_250M>; ext_osc = <1>; + l1ss-disabled; status = "okay"; }; @@ -242,6 +250,13 @@ <&clk IMX8MM_CLK_PCIE1_PHY>, <&pcie0_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <100000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_100M>, + <&clk IMX8MM_SYS_PLL2_250M>; ext_osc = <1>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov2775.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov2775.dts new file mode 100755 index 00000000000000..671a40a2a67d0c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov2775.dts @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020-2021 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mp-evk.dts" + +&iomuxc { + pinctrl_csi1_pwn: csi1_pwn_grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x19 + >; + }; + + pinctrl_csi1_rst: csi1_rst_grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19 + >; + }; +}; + +&i2c2 { + /delete-node/ov5640_mipi@3c; + + basler_camera@36 { + compatible = "basler,basler-camera-vvcam", "basler-camera-vvcam"; + reg = <0x36>; + csi_id = <0x00>; + status = "okay"; + + port { + basler_ep_0: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <750000000>; + + max-lane-frequency = /bits/ 64 <750000000>; + max-pixel-frequency = /bits/ 64 <266000000>; + max-data-rate = /bits/ 64 <0>; + + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + }; +}; + +&i2c3 { + /delete-node/ov5640_mipi@3c; + + ov2775_1: ov2775_mipi@36 { + compatible = "ovti,ov2775"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1_pwn>, <&pinctrl_csi1_rst>, <&pinctrl_csi_mclk>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + pwn-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + + port { + ov2775_mipi_1_ep: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + max-pixel-frequency = /bits/ 64 <266000000>; + + remote-endpoint = <&mipi_csi1_ep>; + }; + }; + }; + +}; + +&mipi_csi_0 { + status = "okay"; + + port@0 { + mipi_csi0_ep: endpoint { + remote-endpoint = <&basler_ep_0>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; + +&mipi_csi_1 { + status = "okay"; + + port@1 { + mipi_csi1_ep: endpoint { + remote-endpoint = <&ov2775_mipi_1_ep>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; + +&isi_0 { + status = "disabled"; +}; + +&isi_1 { + status = "disabled"; +}; + +&isp_0 { + status = "okay"; +}; + +&isp_1 { + status = "okay"; +}; + +&dewarp { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov5640.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov5640.dts index 39497507801882..9460d2c5952b6f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov5640.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov5640.dts @@ -28,7 +28,12 @@ basler_ep_0: endpoint { data-lanes = <1 2 3 4>; clock-lanes = <0>; - link-frequencies = /bits/ 64 <248000000>; + link-frequencies = /bits/ 64 <750000000>; + + max-lane-frequency = /bits/ 64 <750000000>; + max-pixel-frequency = /bits/ 64 <500000000>; + max-data-rate = /bits/ 64 <0>; + remote-endpoint = <&mipi_csi0_ep>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-basler.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-basler.dts index 255d286fcd8ee3..133dd1403036fe 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk-basler.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-basler.dts @@ -29,7 +29,10 @@ basler_ep_0: endpoint { data-lanes = <1 2 3 4>; clock-lanes = <0>; - link-frequencies = /bits/ 64 <248000000>; + link-frequencies = /bits/ 64 <750000000>; + max-lane-frequency = /bits/ 64 <750000000>; + max-pixel-frequency = /bits/ 64 <500000000>; + max-data-rate = /bits/ 64 <0>; remote-endpoint = <&mipi_csi0_ep>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-basler.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-basler.dts new file mode 100755 index 00000000000000..b86e2eca4950e7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-basler.dts @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020-2021 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mp-evk.dts" + +&i2c2 { + /delete-node/ov5640_mipi@3c; + + basler_0: basler_camera_vvcam@36 { + compatible = "basler,basler-camera-vvcam", "basler-camera-vvcam"; + reg = <0x36>; + csi_id = <0x00>; + status = "okay"; + + port { + basler_ep_0: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <750000000>; + + max-lane-frequency = /bits/ 64 <750000000>; + max-pixel-frequency = /bits/ 64 <266000000>; + max-data-rate = /bits/ 64 <0>; + + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + /delete-node/ov5640_mipi@3c; + + basler_1: basler_camera_vvcam@36 { + compatible = "basler,basler-camera-vvcam", "basler-camera-vvcam"; + reg = <0x36>; + csi_id = <0x01>; + status = "okay"; + + port { + basler_ep_1: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <750000000>; + + max-lane-frequency = /bits/ 64 <750000000>; + max-pixel-frequency = /bits/ 64 <266000000>; + max-data-rate = /bits/ 64 <0>; + + remote-endpoint = <&mipi_csi1_ep>; + }; + }; + }; +}; + +&cameradev { + status = "okay"; +}; + +&isi_0 { + status = "disabled"; +}; + +&isi_1 { + status = "disabled"; +}; + +&isp_0 { + status = "okay"; +}; + +&isp_1 { + status = "okay"; +}; + +&dewarp { + status = "okay"; +}; + +&mipi_csi_0 { + status = "okay"; + clock-frequency = <266000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; + assigned-clock-rates = <266000000>; + + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&basler_ep_0>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; + +&mipi_csi_1 { + status = "okay"; + + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&basler_ep_1>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-ov2775.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-ov2775.dts index 6246158e06279c..5c1f3888ea634b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-ov2775.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-ov2775.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright 2020 NXP + * Copyright 2020-2021 NXP * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -39,6 +39,7 @@ ov2775_mipi_0_ep: endpoint { data-lanes = <1 2 3 4>; clock-lanes = <0>; + max-pixel-frequency = /bits/ 64 <266000000>; remote-endpoint = <&mipi_csi0_ep>; }; }; @@ -71,6 +72,7 @@ ov2775_mipi_1_ep: endpoint { data-lanes = <1 2 3 4>; clock-lanes = <0>; + max-pixel-frequency = /bits/ 64 <266000000>; remote-endpoint = <&mipi_csi1_ep>; }; }; @@ -103,6 +105,9 @@ &mipi_csi_0 { status = "okay"; + clock-frequency = <266000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; + assigned-clock-rates = <266000000>; port@0 { endpoint { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775-ov5640.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775-ov5640.dts index d035e5e5cf35b4..46edd382d8b212 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775-ov5640.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775-ov5640.dts @@ -53,6 +53,7 @@ ov2775_mipi_0_ep: endpoint { data-lanes = <1 2 3 4>; clock-lanes = <0>; + max-pixel-frequency = /bits/ 64 <266000000>; remote-endpoint = <&mipi_csi0_ep>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts index 0b1d83122317a3..e241e3646c9a5c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts @@ -41,6 +41,7 @@ ov2775_mipi_0_ep: endpoint { data-lanes = <1 2 3 4>; clock-lanes = <0>; + max-pixel-frequency = /bits/ 64 <500000000>; remote-endpoint = <&mipi_csi0_ep>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 4dfdf5908a0c86..c7e15842933f40 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -681,13 +681,15 @@ ext_osc = <1>; clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>, <&clk IMX8MP_CLK_PCIE_AUX>, - <&clk IMX8MP_CLK_PCIE_PHY>, + <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_CLK_PCIE_ROOT>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>, <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <500000000>, <10000000>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, <&clk IMX8MP_SYS_PLL2_50M>; + l1ss-disabled; status = "okay"; }; @@ -697,11 +699,12 @@ ext_osc = <1>; clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>, <&clk IMX8MP_CLK_PCIE_AUX>, - <&clk IMX8MP_CLK_PCIE_PHY>, + <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_CLK_PCIE_ROOT>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>, <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <500000000>, <10000000>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, <&clk IMX8MP_SYS_PLL2_50M>; status = "disabled"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h index a60017a18cd8d5..5f175e09879f52 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h +++ b/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h @@ -722,7 +722,7 @@ #define MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x214 0x474 0x000 0x5 0x0 #define MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x218 0x478 0x5BC 0x0 0x5 #define MX8MP_IOMUXC_I2C4_SCL__PWM2_OUT 0x218 0x478 0x000 0x1 0x0 -#define MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x218 0x478 0x5A0 0x2 0x0 +#define MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x218 0x478 0x5A0 0x12 0x0 #define MX8MP_IOMUXC_I2C4_SCL__ECSPI2_MISO 0x218 0x478 0x56C 0x3 0x2 #define MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x218 0x478 0x000 0x5 0x0 #define MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x21C 0x47C 0x5C0 0x0 0x5 diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index a0867c9feeb807..9cf497b1ad6985 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright 2019 NXP + * Copyright 2019-2021 NXP */ #include @@ -206,6 +206,12 @@ no-map; reg = <0 0x92400000 0 0x2000000>; }; + + /* used only by tuning tool, can be removed for normal case */ + isp0_reserved: isp0@94400000 { + no-map; + reg = <0 0x94400000 0 0x10000000>; + }; }; osc_32k: clock-osc-32k { @@ -1810,13 +1816,17 @@ compatible = "fsl,imx8mp-isp"; reg = <0x32e10000 0x10000>; interrupts = ; - clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>; - clock-names = "isp_root"; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "core", "axi", "ahb"; assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; assigned-clock-rates = <500000000>; power-domains = <&ispdwp_pd>; id = <0>; + gpr = <&mediamix_blk_ctl>; + memory-region = <&isp0_reserved>; status = "disabled"; }; @@ -1824,13 +1834,16 @@ compatible = "fsl,imx8mp-isp"; reg = <0x32e20000 0x10000>; interrupts = ; - clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>; - clock-names = "isp_root"; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "core", "axi", "ahb"; assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; assigned-clock-rates = <500000000>; power-domains = <&ispdwp_pd>; id = <1>; + gpr = <&mediamix_blk_ctl>; status = "disabled"; }; @@ -1838,6 +1851,15 @@ compatible = "fsl,imx8mp-dwe"; reg = <0x32e30000 0x10000>; interrupts = ; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "core", "axi", "ahb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + assigned-clock-rates = <500000000>, <200000000>; + power-domains = <&ispdwp_pd>; + id = <0>; status = "disabled"; }; @@ -1871,7 +1893,7 @@ <&clk IMX8MP_CLK_MEDIA_APB>; clock-names = "mipi_clk", "disp_axi", "disp_apb"; assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; assigned-clock-rates = <266000000>; bus-width = <4>; csi-gpr = <&mediamix_gasket1>; @@ -1887,10 +1909,8 @@ pcie_phy: pcie-phy@32f00000 { compatible = "fsl,imx8mp-pcie-phy"; reg = <0x0 0x32f00000 0x0 0x10000>; - clocks = <&clk IMX8MP_CLK_PCIE_PHY>; + clocks = <&clk IMX8MP_CLK_DUMMY>; clock-names = "phy"; - assigned-clocks = <&clk IMX8MP_CLK_PCIE_PHY>; - assigned-clock-parents = <&clk IMX8MP_CLK_24M>; #phy-cells = <0>; status = "disabled"; }; @@ -1940,6 +1960,7 @@ ranges = <0x81000000 0 0x00000000 0x0 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ 0x82000000 0 0x18000000 0x0 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ num-lanes = <1>; + num-viewport = <4>; interrupts = , ; /* eDMA */ interrupt-names = "msi", "dma"; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 29bbcffdbb151c..3d48c558b43bbb 100755 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -662,7 +662,16 @@ <&clk IMX8MQ_CLK_PCIE1_PHY>, <&pcie0_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&clk IMX8MQ_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <100000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS2_PLL_250M>; hard-wired = <1>; + vph-supply = <&vgen5_reg>; + l1ss-disabled; status = "okay"; }; @@ -676,6 +685,15 @@ <&clk IMX8MQ_CLK_PCIE2_PHY>, <&pcie1_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&clk IMX8MQ_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <100000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS2_PLL_250M>; + vph-supply = <&vgen5_reg>; + l1ss-disabled; status = "okay"; }; @@ -687,6 +705,13 @@ <&clk IMX8MQ_CLK_PCIE2_PHY>, <&pcie1_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&clk IMX8MQ_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <100000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS2_PLL_250M>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h index 68e8fa17297416..760321ac5f9476 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h +++ b/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h @@ -555,12 +555,12 @@ #define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0 #define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0 #define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0 +#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x12 0x0 #define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 #define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0 #define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0 #define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0 +#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x12 0x0 #define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 #define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0 #define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 18f33e67edad5e..d8e72a49c82acf 100755 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1443,8 +1443,9 @@ power-domains = <&pgc_pcie>; resets = <&src IMX8MQ_RESET_PCIEPHY>, <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, - <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; - reset-names = "pciephy", "apps", "turnoff"; + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "clkreq", "turnoff"; status = "disabled"; }; @@ -1473,8 +1474,9 @@ power-domains = <&pgc_pcie>; resets = <&src IMX8MQ_RESET_PCIEPHY2>, <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, - <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; - reset-names = "pciephy", "apps", "turnoff"; + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_CLK_REQ>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "clkreq", "turnoff"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-dp.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-dp.dts new file mode 100644 index 00000000000000..09a43342924303 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-dp.dts @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + * Oliver Brown + */ + /* Three displays enabled: DP, LVDS, and MIPI DSI */ + +/dts-v1/; + +#include "imx8qm-mek-rpmsg.dts" + +/ { + sound-hdmi-tx { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-hdmi-tx"; + audio-cpu = <&sai5>; + protocol = <1>; + hdmi-out; + }; + + sound-hdmi-arc { + compatible = "fsl,imx-audio-spdif"; + model = "imx-hdmi-arc"; + spdif-controller = <&spdif1>; + spdif-in; + spdif-out; + }; +}; + +&sai5 { + status = "okay"; +}; + +&sai5_lpcg { + status = "okay"; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&ldb2_phy { + status = "disabled"; +}; + +&ldb2 { + status = "disabled"; +}; + +&mipi0_dphy { + status = "disabled"; +}; + +&mipi0_dsi_host { + status = "disabled"; +}; + +&irqsteer_hdmi { + status = "okay"; +}; + +&hdmi_lpcg_i2c0 { + status = "okay"; +}; + +&hdmi_lpcg_lis_ipg { + status = "okay"; +}; + +&hdmi_lpcg_pwm_ipg { + status = "okay"; +}; + +&hdmi_lpcg_i2s { + status = "okay"; +}; + +&hdmi_lpcg_gpio_ipg { + status = "okay"; +}; + +&hdmi_lpcg_msi_hclk { + status = "okay"; +}; + +&hdmi_lpcg_pxl { + status = "okay"; +}; + +&hdmi_lpcg_phy { + status = "okay"; +}; + +&hdmi_lpcg_apb_mux_csr { + status = "okay"; +}; + +&hdmi_lpcg_apb_mux_ctrl { + status = "okay"; +}; + +&hdmi_lpcg_apb { + status = "okay"; +}; + +&hdmi { + compatible = "cdn,imx8qm-dp"; + firmware-name = "dpfw.bin"; + lane-mapping = <0x1b>; + status = "okay"; +}; + +&spdif1 { + status = "okay"; +}; + +&spdif1_lpcg { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi.dts index 10324988d63a00..fe434e68fdf1f8 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi.dts @@ -3,7 +3,7 @@ * Copyright 2019 NXP * Sandor Yu */ - /* HDMI Only driver, LVDS is disabled */ + /* Three display enabled: HDMI, LVDS, and MIPI DSI */ /dts-v1/; @@ -43,11 +43,7 @@ status = "disabled"; }; -&ldb2_phy { - status = "disabled"; -}; - -&ldb2 { +&mipi0_dphy { status = "disabled"; }; @@ -55,18 +51,6 @@ status = "disabled"; }; -&mipi1_dphy { - status = "disabled"; -}; - -&mipi1_dsi_host { - status = "disabled"; -}; - -&mipi1_dphy { - status = "disabled"; -}; - &irqsteer_hdmi { status = "okay"; }; diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 0f492603300df5..a60b9223a5f978 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -684,9 +684,6 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) imx_clk_init_on(np, clks); - clk_set_parent(clks[IMX8MM_CLK_PCIE1_CTRL], clks[IMX8MM_SYS_PLL2_250M]); - clk_set_parent(clks[IMX8MM_CLK_PCIE1_PHY], clks[IMX8MM_SYS_PLL2_100M]); - clk_set_parent(clks[IMX8MM_CLK_CSI1_CORE], clks[IMX8MM_SYS_PLL2_1000M]); clk_set_parent(clks[IMX8MM_CLK_CSI1_PHY_REF], clks[IMX8MM_SYS_PLL2_1000M]); clk_set_parent(clks[IMX8MM_CLK_CSI1_ESC], clks[IMX8MM_SYS_PLL1_800M]); diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index ca7f364a589806..a92cf772720a98 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -245,10 +245,6 @@ static const char *imx8mp_can2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_4 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char *imx8mp_pcie_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll2_500m", - "clk_ext1", "clk_ext2", "clk_ext3", - "clk_ext4", "sys_pll1_400m", }; - static const char *imx8mp_pcie_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m", "sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200m", }; @@ -701,7 +697,6 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) clks[IMX8MP_CLK_VPU_G2] = imx8m_clk_composite("vpu_g2", imx8mp_vpu_g2_sels, base + 0xa180); clks[IMX8MP_CLK_CAN1] = imx8m_clk_composite("can1", imx8mp_can1_sels, base + 0xa200); clks[IMX8MP_CLK_CAN2] = imx8m_clk_composite("can2", imx8mp_can2_sels, base + 0xa280); - clks[IMX8MP_CLK_PCIE_PHY] = imx8m_clk_composite("pcie_phy", imx8mp_pcie_phy_sels, base + 0xa380); clks[IMX8MP_CLK_PCIE_AUX] = imx8m_clk_composite("pcie_aux", imx8mp_pcie_aux_sels, base + 0xa400); clks[IMX8MP_CLK_I2C5] = imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, base + 0xa480); clks[IMX8MP_CLK_I2C6] = imx8m_clk_composite("i2c6", imx8mp_i2c6_sels, base + 0xa500); diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index 554ae69a127b96..299ae2f89945ed 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -118,12 +118,12 @@ static const char * const imx8mq_disp_dtrc_sels[] = {"osc_25m", "vpu_pll_out", " static const char * const imx8mq_disp_dc8000_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll_out", "audio_pll2_out", }; static const char * const imx8mq_pcie1_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m", - "sys1_pll_800m", "sys2_pll_500m", "sys2_pll_250m", "sys3_pll_out", }; + "sys1_pll_800m", "sys2_pll_500m", "sys2_pll_333m", "sys3_pll_out", }; static const char * const imx8mq_pcie1_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4", }; -static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_500m", "sys3_pll_out", +static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_50m", "sys3_pll_out", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", }; static const char * const imx8mq_dc_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll_out", "clk_ext4", }; diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c index a362a201e87363..4405dc19c6eb32 100644 --- a/drivers/crypto/caam/jr.c +++ b/drivers/crypto/caam/jr.c @@ -244,7 +244,7 @@ static irqreturn_t caam_jr_interrupt(int irq, void *st_dev) * tasklet if jobs done. */ irqstate = rd_reg32(&jrp->rregs->jrintstatus); - if (!irqstate) + if (!(irqstate & ~JRINT_ERR_HALT_MASK)) return IRQ_NONE; /* diff --git a/drivers/dma/pxp/pxp_device.c b/drivers/dma/pxp/pxp_device.c index 2504adf1ae4a35..f678c08833570f 100644 --- a/drivers/dma/pxp/pxp_device.c +++ b/drivers/dma/pxp/pxp_device.c @@ -770,17 +770,17 @@ static long pxp_device_ioctl(struct file *filp, switch (flush.type) { case CACHE_CLEAN: - dma_sync_single_for_device(NULL, obj->offset, + dma_sync_single_for_device(pxp_dev, obj->offset, obj->size, DMA_TO_DEVICE); break; case CACHE_INVALIDATE: - dma_sync_single_for_device(NULL, obj->offset, + dma_sync_single_for_device(pxp_dev, obj->offset, obj->size, DMA_FROM_DEVICE); break; case CACHE_FLUSH: - dma_sync_single_for_device(NULL, obj->offset, + dma_sync_single_for_device(pxp_dev, obj->offset, obj->size, DMA_TO_DEVICE); - dma_sync_single_for_device(NULL, obj->offset, + dma_sync_single_for_device(pxp_dev, obj->offset, obj->size, DMA_FROM_DEVICE); break; default: diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c index 26b53806a0c062..35446bde661774 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c +++ b/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c @@ -35,22 +35,16 @@ static ssize_t dp_aux_transfer(struct drm_dp_aux *aux, bool native = msg->request & (DP_AUX_NATIVE_WRITE & DP_AUX_NATIVE_READ); int ret; - /* Ignore address only message */ - if ((msg->size == 0) || (msg->buffer == NULL)) { - msg->reply = native ? - DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK; + /* Ignore address only message , for native */ + if ((native == true) && ((msg->size == 0) || (msg->buffer == NULL))) { + msg->reply = DP_AUX_NATIVE_REPLY_ACK; return msg->size; } - if (!native) { - dev_err(mhdp->dev, "%s: only native messages supported\n", __func__); - return -EINVAL; - } - /* msg sanity check */ if (msg->size > DP_AUX_MAX_PAYLOAD_BYTES) { dev_err(mhdp->dev, "%s: invalid msg: size(%zu), request(%x)\n", - __func__, msg->size, (unsigned int)msg->request); + __func__, msg->size, (unsigned int)msg->request); return -EINVAL; } @@ -72,12 +66,96 @@ static ssize_t dp_aux_transfer(struct drm_dp_aux *aux, } if (msg->request == DP_AUX_NATIVE_READ) { - ret = cdns_mhdp_dpcd_read(mhdp, msg->address, msg->buffer, msg->size); + ret = cdns_mhdp_dpcd_read(mhdp, msg->address, msg->buffer, + msg->size); if (ret < 0) return -EIO; msg->reply = DP_AUX_NATIVE_REPLY_ACK; return msg->size; } + + if (((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) + || ((msg->request & ~DP_AUX_I2C_MOT) == + DP_AUX_I2C_WRITE_STATUS_UPDATE)) { + + u8 i2c_status = 0u; + u16 respSize = 0u; + + ret = cdns_mhdp_i2c_write(mhdp, msg->address, + msg->buffer, + !!(msg->request & DP_AUX_I2C_MOT), + msg->size, &respSize); + + if (ret < 0) { + dev_err(aux->dev, "cdns_mhdp_i2c_write status %d\n", + ret); + return -EIO; + } + + ret = cdns_mhdp_get_last_i2c_status(mhdp, &i2c_status); + if (ret < 0) { + dev_err(aux->dev, + "cdns_mhdp_get_last_i2c_status status %d\n", + ret); + return -EIO; + } + + switch (i2c_status) { + case 0u: + msg->reply = DP_AUX_I2C_REPLY_ACK; + break; + case 1u: + msg->reply = DP_AUX_I2C_REPLY_NACK; + break; + case 2u: + msg->reply = DP_AUX_I2C_REPLY_DEFER; + break; + default: + msg->reply = DP_AUX_I2C_REPLY_NACK; + break; + } + + return respSize; + } + + if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_READ) { + + u8 i2c_status = 0u; + u16 respSize = 0u; + + ret = cdns_mhdp_i2c_read(mhdp, msg->address, msg->buffer, + msg->size, + !!(msg->request & DP_AUX_I2C_MOT), + &respSize); + if (ret < 0) + return -EIO; + + ret = cdns_mhdp_get_last_i2c_status(mhdp, &i2c_status); + + if (ret < 0) { + dev_err(aux->dev, + "cdns_mhdp_get_last_i2c_status ret %d\n", ret); + return -EIO; + } + + switch (i2c_status) { + case 0u: + msg->reply = DP_AUX_I2C_REPLY_ACK; + break; + case 1u: + msg->reply = DP_AUX_I2C_REPLY_NACK; + break; + case 2u: + msg->reply = DP_AUX_I2C_REPLY_DEFER; + break; + default: + msg->reply = DP_AUX_I2C_REPLY_NACK; + break; + } + + return respSize; + } + return 0; } @@ -506,6 +584,7 @@ static int __cdns_dp_probe(struct platform_device *pdev, static void __cdns_dp_remove(struct cdns_mhdp_device *mhdp) { + cdns_mhdp_plat_call(mhdp, power_off); dp_aux_destroy(mhdp); cdns_mhdp_unregister_audio_driver(mhdp->dev); } diff --git a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c index d308ec3388f964..07700e4948572d 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c +++ b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c @@ -663,6 +663,8 @@ static int __cdns_hdmi_probe(struct platform_device *pdev, static void __cdns_hdmi_remove(struct cdns_mhdp_device *mhdp) { + cdns_mhdp_plat_call(mhdp, power_off); + /* unregister cec driver */ #ifdef CONFIG_DRM_CDNS_HDMI_CEC cdns_mhdp_unregister_cec_driver(mhdp->dev); diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c index 9a105cded9e9de..1c1601b81d8319 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c @@ -55,6 +55,41 @@ int cdns_mhdp_dpcd_read(struct cdns_mhdp_device *mhdp, } EXPORT_SYMBOL(cdns_mhdp_dpcd_read); +int cdns_mhdp_i2c_read(struct cdns_mhdp_device *mhdp, u8 addr, u8 *data, + u16 len, u8 mot, u16 *respLength) +{ + u8 msg[5], reg[3]; + int ret; + + put_unaligned_be16(len, msg); + msg[2] = addr; + msg[3] = mot; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_I2C_READ, sizeof(msg), msg); + if (ret) + goto err_i2c_read; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, + DPTX_I2C_READ, + sizeof(reg) + len); + if (ret) + goto err_i2c_read; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); + if (ret) + goto err_i2c_read; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, data, len); + *respLength = (reg[0] << 8u) + reg[1]; + +err_i2c_read: + if (ret) + DRM_DEV_ERROR(mhdp->dev, "i2c read failed: %d\n", ret); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_i2c_read); + int cdns_mhdp_dpcd_write(struct cdns_mhdp_device *mhdp, u32 addr, u8 value) { u8 msg[6], reg[5]; @@ -88,6 +123,75 @@ int cdns_mhdp_dpcd_write(struct cdns_mhdp_device *mhdp, u32 addr, u8 value) } EXPORT_SYMBOL(cdns_mhdp_dpcd_write); +int cdns_mhdp_i2c_write(struct cdns_mhdp_device *mhdp, u8 addr, u8 *value, + u8 mot, u16 len, u16 *respLength) +{ + u8 msg[4+DP_AUX_MAX_PAYLOAD_BYTES], reg[3]; + int ret; + + put_unaligned_be16(len, msg); + msg[2] = addr; + msg[3] = mot; + memcpy(&msg[4], value, len); + + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_I2C_WRITE, sizeof(msg), msg); + if (ret) + goto err_i2c_write; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, + DPTX_I2C_WRITE, sizeof(reg)); + if (ret) + goto err_i2c_write; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); + if (ret) + goto err_i2c_write; + + if (addr != reg[2]) + ret = -EINVAL; + + *respLength = (reg[0]<<8u) + reg[1]; + +err_i2c_write: + if (ret) + DRM_DEV_ERROR(mhdp->dev, "i2c write failed: %d\n", ret); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_i2c_write); + + +int cdns_mhdp_get_last_i2c_status(struct cdns_mhdp_device *mhdp, u8 *resp) +{ + u8 status[1]; + int ret; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_GET_LAST_I2C_STATUS, 0, NULL); + if (ret) + goto err_get_i2c_status; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, + DPTX_GET_LAST_I2C_STATUS, + sizeof(status)); + if (ret) + goto err_get_i2c_status; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, status, sizeof(status)); + if (ret) + goto err_get_i2c_status; + + *resp = status[0]; + +err_get_i2c_status: + if (ret) + DRM_DEV_ERROR(mhdp->dev, "get i2c status failed: %d\n", + ret); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_get_last_i2c_status); + static int cdns_mhdp_training_start(struct cdns_mhdp_device *mhdp) { unsigned long timeout; diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index d2d2053428114f..73b006c2f946fa 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -761,37 +761,30 @@ static void dw_hdmi_gp_audio_enable(struct dw_hdmi *hdmi) case 32000: sample_freq = 0x03; org_sample_freq = 0x0C; - hdmi_writeb(hdmi, 0x31, HDMI_FC_AUDICONF1); break; case 44100: sample_freq = 0x00; org_sample_freq = 0x0F; - hdmi_writeb(hdmi, 0x32, HDMI_FC_AUDICONF1); break; case 48000: sample_freq = 0x02; org_sample_freq = 0x0D; - hdmi_writeb(hdmi, 0x33, HDMI_FC_AUDICONF1); break; case 88200: sample_freq = 0x08; org_sample_freq = 0x07; - hdmi_writeb(hdmi, 0x34, HDMI_FC_AUDICONF1); break; case 96000: sample_freq = 0x0A; org_sample_freq = 0x05; - hdmi_writeb(hdmi, 0x35, HDMI_FC_AUDICONF1); break; case 176400: sample_freq = 0x0C; org_sample_freq = 0x03; - hdmi_writeb(hdmi, 0x36, HDMI_FC_AUDICONF1); break; case 192000: sample_freq = 0x0E; org_sample_freq = 0x01; - hdmi_writeb(hdmi, 0x37, HDMI_FC_AUDICONF1); break; default: break; diff --git a/drivers/gpu/drm/imx/dw_hdmi-imx.c b/drivers/gpu/drm/imx/dw_hdmi-imx.c index 1c8d2ac0668fb5..0c54acd5214588 100644 --- a/drivers/gpu/drm/imx/dw_hdmi-imx.c +++ b/drivers/gpu/drm/imx/dw_hdmi-imx.c @@ -276,8 +276,11 @@ static int imx8mp_hdmi_phy_init(struct dw_hdmi *dw_hdmi, void *data, imx8mp_hdmi_pavi_powerup(); imx8mp_hdmi_pvi_enable(mode); - /* HDMI PHY power up */ regmap_read(hdmi->regmap, 0x200, &val); + /* HDMI PHY power off */ + val |= 0x8; + regmap_write(hdmi->regmap, 0x200, val); + /* HDMI PHY power on */ val &= ~0x8; /* Enable CEC */ val |= 0x2; diff --git a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx.h b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx.h index fc3247dada2d09..87b5e366b7e6c0 100644 --- a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx.h +++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx.h @@ -70,6 +70,7 @@ int cdns_mhdp_firmware_init_imx8qm(struct cdns_mhdp_device *mhdp); int cdns_mhdp_resume_imx8qm(struct cdns_mhdp_device *mhdp); int cdns_mhdp_suspend_imx8qm(struct cdns_mhdp_device *mhdp); int cdns_mhdp_power_on_imx8qm(struct cdns_mhdp_device *mhdp); +int cdns_mhdp_power_off_imx8qm(struct cdns_mhdp_device *mhdp); int cdns_mhdp_power_on_ls1028a(struct cdns_mhdp_device *mhdp); void cdns_mhdp_pclk_rate_ls1028a(struct cdns_mhdp_device *mhdp); #endif /* CDNS_MHDP_IMX_H_ */ diff --git a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c index f282e7d9df9c99..6173fda46403fc 100644 --- a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c +++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c @@ -373,6 +373,65 @@ static int imx8qm_ipg_clk_enable(struct imx_mhdp_device *imx_mhdp) return ret; } +static int imx8qm_ipg_clk_disable(struct imx_mhdp_device *imx_mhdp) +{ + int ret; + struct imx_hdp_clks *clks = &imx_mhdp->clks; + struct device *dev = imx_mhdp->mhdp.dev; + + ret = clk_prepare_enable(clks->clk_i2s_bypass); + if (ret < 0) { + dev_err(dev, "%s, pre clk i2s bypass error\n", __func__); + return ret; + } + ret = clk_prepare_enable(clks->lpcg_i2s); + if (ret < 0) { + dev_err(dev, "%s, pre clk i2s error\n", __func__); + return ret; + } + ret = clk_prepare_enable(clks->lpcg_apb_ctrl); + if (ret < 0) { + dev_err(dev, "%s, pre clk apb ctrl error\n", __func__); + return ret; + } + ret = clk_prepare_enable(clks->lpcg_apb_csr); + if (ret < 0) { + dev_err(dev, "%s, pre clk apb csr error\n", __func__); + return ret; + } + ret = clk_prepare_enable(clks->lpcg_msi); + if (ret < 0) { + dev_err(dev, "%s, pre clk msierror\n", __func__); + return ret; + } + ret = clk_prepare_enable(clks->lpcg_lis); + if (ret < 0) { + dev_err(dev, "%s, pre clk lis error\n", __func__); + return ret; + } + ret = clk_prepare_enable(clks->lpcg_apb); + if (ret < 0) { + dev_err(dev, "%s, pre clk apb error\n", __func__); + return ret; + } + ret = clk_prepare_enable(clks->clk_core); + if (ret < 0) { + dev_err(dev, "%s, pre clk core error\n", __func__); + return ret; + } + ret = clk_prepare_enable(clks->clk_ipg); + if (ret < 0) { + dev_err(dev, "%s, pre clk_ipg error\n", __func__); + return ret; + } + ret = clk_prepare_enable(clks->dig_pll); + if (ret < 0) { + dev_err(dev, "%s, pre dig pll error\n", __func__); + return ret; + } + return ret; +} + static void imx8qm_ipg_clk_set_rate(struct imx_mhdp_device *imx_mhdp) { struct imx_hdp_clks *clks = &imx_mhdp->clks; @@ -464,6 +523,7 @@ int cdns_mhdp_power_on_imx8qm(struct cdns_mhdp_device *mhdp) { struct imx_mhdp_device *imx_mhdp = container_of(mhdp, struct imx_mhdp_device, mhdp); + /* Power on PM Domains */ imx8qm_attach_pm_domains(imx_mhdp); @@ -487,6 +547,21 @@ int cdns_mhdp_power_on_imx8qm(struct cdns_mhdp_device *mhdp) return 0; } +int cdns_mhdp_power_off_imx8qm(struct cdns_mhdp_device *mhdp) +{ + struct imx_mhdp_device *imx_mhdp = + container_of(mhdp, struct imx_mhdp_device, mhdp); + + imx8qm_phy_reset(0); + imx8qm_pixel_clk_disable(imx_mhdp); + imx8qm_ipg_clk_disable(imx_mhdp); + + /* Power off PM Domains */ + imx8qm_detach_pm_domains(imx_mhdp); + + return 0; +} + void cdns_mhdp_plat_init_imx8qm(struct cdns_mhdp_device *mhdp) { struct imx_mhdp_device *imx_mhdp = diff --git a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c index 2b3e574d86be74..273275ed58314e 100644 --- a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c +++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c @@ -82,6 +82,7 @@ static struct cdns_plat_data imx8qm_hdmi_drv_data = { .phy_set = cdns_hdmi_phy_set_imx8qm, .phy_video_valid = cdns_hdmi_phy_video_valid_imx8qm, .power_on = cdns_mhdp_power_on_imx8qm, + .power_off = cdns_mhdp_power_off_imx8qm, .firmware_init = cdns_mhdp_firmware_init_imx8qm, .resume = cdns_mhdp_resume_imx8qm, .suspend = cdns_mhdp_suspend_imx8qm, @@ -98,6 +99,7 @@ static struct cdns_plat_data imx8qm_dp_drv_data = { .unbind = cdns_dp_unbind, .phy_set = cdns_dp_phy_set_imx8qm, .power_on = cdns_mhdp_power_on_imx8qm, + .power_off = cdns_mhdp_power_off_imx8qm, .firmware_init = cdns_mhdp_firmware_init_imx8qm, .resume = cdns_mhdp_resume_imx8qm, .suspend = cdns_mhdp_suspend_imx8qm, diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/Makefile b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/Makefile index 8ee9b932231f87..7892b3e6e288f7 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/Makefile +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/Makefile @@ -96,6 +96,11 @@ MODEXT = ko ccflags-y += -I$(M)/mlan ccflags-y += -DLINUX +CONFIG_IMX_SUPPORT=y +ifeq ($(CONFIG_IMX_SUPPORT),y) +ccflags-y += -DIMX_SUPPORT +endif + LD += -S ############################################################################# diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_11h.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_11h.c index 9f1869617a2182..027ba589d752f6 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_11h.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_11h.c @@ -1896,6 +1896,8 @@ t_void wlan_11h_init(mlan_adapter *adapter) pdfs_test->user_nop_period_sec = 0; pdfs_test->no_channel_change_on_radar = MFALSE; pdfs_test->fixed_new_channel_on_radar = 0; + pdfs_test->cac_restart = 0; + pdfs_test->millisec_dwell_time = 0; adapter->dfs53cfg = adapter->init_para.dfs53cfg; LEAVE(); @@ -2144,6 +2146,17 @@ t_bool wlan_11h_radar_detect_required(mlan_private *priv, t_u8 channel) return required; } +t_s32 wlan_11h_cancel_radar_detect(mlan_private *priv) +{ + t_s32 ret; + HostCmd_DS_CHAN_RPT_REQ chan_rpt_req; + memset(priv->adapter, &chan_rpt_req, 0x00, sizeof(chan_rpt_req)); + ret = wlan_prepare_cmd(priv, HostCmd_CMD_CHAN_REPORT_REQUEST, + HostCmd_ACT_GEN_SET, 0, (t_void *)MNULL, + (t_void *)&chan_rpt_req); + return ret; +} + /** * @brief Perform a radar measurement if required on given channel * @@ -2232,7 +2245,21 @@ t_s32 wlan_11h_issue_radar_detect(mlan_private *priv, priv->adapter->dfs_test_params .user_cac_period_msec; } - + if (priv->adapter->dfs_test_params.cac_restart) { + priv->adapter->dfs_test_params.chan = + chan_rpt_req.chan_desc.chanNum; + if (chan_rpt_req.millisec_dwell_time) + priv->adapter->dfs_test_params + .millisec_dwell_time = + chan_rpt_req.millisec_dwell_time; + else + chan_rpt_req.millisec_dwell_time = + priv->adapter->dfs_test_params + .millisec_dwell_time; + memcpy_ext(priv->adapter, + &priv->adapter->dfs_test_params.bandcfg, + &bandcfg, sizeof(bandcfg), sizeof(bandcfg)); + } PRINTM(MMSG, "11h: issuing DFS Radar check for channel=%d." " Please wait for response...\n", @@ -2598,7 +2625,7 @@ mlan_status wlan_11h_cmdresp_process(mlan_private *priv, priv->adapter->state_dfs.dfs_check_pending = MTRUE; if (resp->params.chan_rpt_req.millisec_dwell_time == 0) { - /* from wlan_11h_ioctl_dfs_cancel_chan_report */ + /* from wlan_11h_ioctl_dfs_chan_report */ priv->adapter->state_dfs.dfs_check_pending = MFALSE; priv->adapter->state_dfs.dfs_check_priv = MNULL; priv->adapter->state_dfs.dfs_check_channel = 0; @@ -2885,6 +2912,7 @@ mlan_status wlan_11h_ioctl_dfs_testing(pmlan_adapter pmadapter, pdfs_test_params->no_channel_change_on_radar; dfs_test->usr_fixed_new_chan = pdfs_test_params->fixed_new_channel_on_radar; + dfs_test->usr_cac_restart = pdfs_test_params->cac_restart; } else { pdfs_test_params->user_cac_period_msec = dfs_test->usr_cac_period_msec; @@ -2894,6 +2922,7 @@ mlan_status wlan_11h_ioctl_dfs_testing(pmlan_adapter pmadapter, dfs_test->usr_no_chan_change; pdfs_test_params->fixed_new_channel_on_radar = dfs_test->usr_fixed_new_chan; + pdfs_test_params->cac_restart = dfs_test->usr_cac_restart; } LEAVE(); @@ -2985,15 +3014,15 @@ mlan_status wlan_11h_ioctl_chan_switch_count(pmlan_adapter pmadapter, } /** - * @brief 802.11h DFS cancel chan report + * @brief 802.11h DFS chan report * * @param priv Pointer to mlan_private * @param pioctl_req Pointer to mlan_ioctl_req * * @return MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE */ -mlan_status wlan_11h_ioctl_dfs_cancel_chan_report(mlan_private *priv, - pmlan_ioctl_req pioctl_req) +mlan_status wlan_11h_ioctl_dfs_chan_report(mlan_private *priv, + pmlan_ioctl_req pioctl_req) { mlan_ds_11h_cfg *ds_11hcfg = MNULL; HostCmd_DS_CHAN_RPT_REQ *chan_rpt_req = MNULL; diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_11h.h b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_11h.h index 534ffd6a2f90c3..05766a99bb3571 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_11h.h +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_11h.h @@ -142,6 +142,7 @@ mlan_status wlan_11h_print_event_radar_detected(mlan_private *priv, mlan_event *pevent, t_u8 *radar_chan); +t_s32 wlan_11h_cancel_radar_detect(mlan_private *priv); /** Handler for DFS_TESTING IOCTL */ extern mlan_status wlan_11h_ioctl_dfs_testing(pmlan_adapter pmadapter, pmlan_ioctl_req pioctl_req); @@ -149,9 +150,8 @@ extern mlan_status wlan_11h_ioctl_get_channel_nop_info(pmlan_adapter pmadapter, pmlan_ioctl_req pioctl_req); -extern mlan_status -wlan_11h_ioctl_dfs_cancel_chan_report(mlan_private *priv, - pmlan_ioctl_req pioctl_req); +extern mlan_status wlan_11h_ioctl_dfs_chan_report(mlan_private *priv, + pmlan_ioctl_req pioctl_req); extern mlan_status wlan_11h_ioctl_chan_switch_count(pmlan_adapter pmadapter, pmlan_ioctl_req pioctl_req); diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_11n_aggr.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_11n_aggr.c index 1997523afb5de6..17cd78d02eb00a 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_11n_aggr.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_11n_aggr.c @@ -260,6 +260,13 @@ mlan_status wlan_11n_deaggregate_pkt(mlan_private *priv, pmlan_buffer pmbuf) pmbuf->use_count = wlan_11n_get_num_aggrpkts(data, total_pkt_len); + // rx_trace 7 + if (pmadapter->tp_state_on) + pmadapter->callbacks.moal_tp_accounting( + pmadapter->pmoal_handle, pmbuf, 7 /*RX_DROP_P3*/); + if (pmadapter->tp_state_drop_point == 7 /*RX_DROP_P3*/) + goto done; + while (total_pkt_len >= hdr_len) { prx_pkt = (RxPacketHdr_t *)data; /* Length will be in network format, change it to host */ @@ -445,7 +452,10 @@ int wlan_11n_aggregate_pkt(mlan_private *priv, raListTbl *pra_list, (pmlan_buffer)util_dequeue_list(pmadapter->pmoal_handle, &pra_list->buf_head, MNULL, MNULL); - + /* Collects TP statistics */ + if (pmadapter->tp_state_on && (pkt_size > sizeof(TxPD))) + pmadapter->callbacks.moal_tp_accounting( + pmadapter->pmoal_handle, pmbuf_src->pdesc, 3); pra_list->total_pkts--; /* decrement for every PDU taken from the list */ @@ -497,9 +507,18 @@ int wlan_11n_aggregate_pkt(mlan_private *priv, raListTbl *pra_list, pmbuf_aggr->pbuf = data - headroom; tx_param.next_pkt_len = ((pmbuf_src) ? pmbuf_src->data_len + sizeof(TxPD) : 0); + /* Collects TP statistics */ + if (pmadapter->tp_state_on) + pmadapter->callbacks.moal_tp_accounting(pmadapter->pmoal_handle, + pmbuf_aggr, 4); - ret = pmadapter->ops.host_to_card(priv, MLAN_TYPE_DATA, pmbuf_aggr, - &tx_param); + /* Drop Tx packets at drop point 4 */ + if (pmadapter->tp_state_drop_point == 4) { + wlan_write_data_complete(pmadapter, pmbuf_aggr, ret); + goto exit; + } else + ret = pmadapter->ops.host_to_card(priv, MLAN_TYPE_DATA, + pmbuf_aggr, &tx_param); switch (ret) { #ifdef USB case MLAN_STATUS_PRESOURCE: diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_cmdevt.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_cmdevt.c index ec27a4c3be22ab..6393ae6045f7d7 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_cmdevt.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_cmdevt.c @@ -2344,7 +2344,7 @@ t_void wlan_cancel_all_pending_cmd(pmlan_adapter pmadapter, t_u8 flag) MLAN_STATUS_FAILURE); } #endif - if (pmadapter->curr_cmd) { + if (pmadapter->curr_cmd && flag) { pcmd_node = pmadapter->curr_cmd; if (pcmd_node->pioctl_buf) { pioctl_buf = (mlan_ioctl_req *)pcmd_node->pioctl_buf; @@ -2354,10 +2354,8 @@ t_void wlan_cancel_all_pending_cmd(pmlan_adapter pmadapter, t_u8 flag) MLAN_STATUS_FAILURE); pcmd_node->pioctl_buf = MNULL; } - if (flag) { - pmadapter->curr_cmd = MNULL; - wlan_insert_cmd_to_free_q(pmadapter, pcmd_node); - } + pmadapter->curr_cmd = MNULL; + wlan_insert_cmd_to_free_q(pmadapter, pcmd_node); } /* Cancel all pending command */ diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_decl.h b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_decl.h index 9037910c11a9ca..7d0b75cc3c5470 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_decl.h +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_decl.h @@ -24,7 +24,7 @@ #define _MLAN_DECL_H_ /** MLAN release version */ -#define MLAN_RELEASE_VERSION "210" +#define MLAN_RELEASE_VERSION "215.p2" /** Re-define generic data types for MLAN/MOAL */ /** Signed char (1-byte) */ @@ -857,6 +857,23 @@ enum { SCAN_MODE_MANUAL = 0, SCAN_MODE_USER, }; +/** max cac time 10 minutes */ +#define MAX_CAC_DWELL_TIME 600000 +/** default cac time 60 seconds */ +#define DEF_CAC_DWELL_TIME 60000 +/** start freq for 5G */ +#define START_FREQ_11A_BAND 5000 +/** DFS state */ +typedef enum _dfs_state_t { + /** Channel can be used, CAC (Channel Availability Check) must be done + before using it */ + DFS_USABLE = 0, + /** Channel is not available, radar was detected */ + DFS_UNAVAILABLE = 1, + /** Channel is Available, CAC is done and is free of radar */ + DFS_AVAILABLE = 2, +} dfs_state_t; + typedef enum _dfs_w53_cfg_t { /** DFS W53 Default Fw Value */ DFS_W53_DEFAULT_FW = 0, @@ -1747,6 +1764,12 @@ typedef struct _mlan_callbacks { mlan_status (*moal_notify_hostcmd_complete)(t_void *pmoal_handle, t_u32 bss_index); #endif + void (*moal_tp_accounting)(t_void *pmoal_handle, t_void *buf, + t_u32 drop_point); + void (*moal_tp_accounting_rx_param)(t_void *pmoal_handle, + unsigned int type, + unsigned int rsvd1); + } mlan_callbacks, *pmlan_callbacks; /** Parameter unchanged, use MLAN default setting */ diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_fw.h b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_fw.h index cddbce4154def1..2011e2459f0762 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_fw.h +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_fw.h @@ -3533,6 +3533,29 @@ typedef MLAN_PACK_START struct _HostCmd_DS_802_11_GET_LOG { t_u64 rx_octets_in_ampdu_cnt; /** ampdu delimiter CRC error count */ t_u32 ampdu_delimiter_crc_error_cnt; + /** Rx Stuck Related Info*/ + /** Rx Stuck Issue count */ + t_u32 rx_stuck_issue_cnt[2]; + /** Rx Stuck Recovery count */ + t_u32 rx_stuck_recovery_cnt; + /** Rx Stuck TSF */ + t_u64 rx_stuck_tsf[2]; + /** Tx Watchdog Recovery Related Info */ + /** Tx Watchdog Recovery count */ + t_u32 tx_watchdog_recovery_cnt; + /** Tx Watchdog TSF */ + t_u64 tx_watchdog_tsf[2]; + /** Channel Switch Related Info */ + /** Channel Switch Announcement Sent */ + t_u32 channel_switch_ann_sent; + /** Channel Switch State */ + t_u32 channel_switch_state; + /** Register Class */ + t_u32 reg_class; + /** Channel Number */ + t_u32 channel_number; + /** Channel Switch Mode */ + t_u32 channel_switch_mode; } MLAN_PACK_END HostCmd_DS_802_11_GET_LOG; /* maln wifi rate */ diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_ioctl.h b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_ioctl.h index caaadb03ca53a7..2315b2a2b79ec7 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_ioctl.h +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_ioctl.h @@ -331,6 +331,7 @@ enum _mlan_ioctl_req_id { MLAN_OID_MISC_CFP_TABLE = 0x0020007A, MLAN_OID_MISC_RANGE_EXT = 0x0020007B, MLAN_OID_MISC_DOT11MC_UNASSOC_FTM_CFG = 0x0020007C, + MLAN_OID_MISC_TP_STATE = 0x0020007D, }; /** Sub command size */ @@ -1594,6 +1595,29 @@ typedef struct _mlan_ds_get_stats { t_u64 rx_octets_in_ampdu_cnt; /** ampdu delimiter CRC error count */ t_u32 ampdu_delimiter_crc_error_cnt; + /** Rx Stuck Related Info*/ + /** Rx Stuck Issue count */ + t_u32 rx_stuck_issue_cnt[2]; + /** Rx Stuck Recovery count */ + t_u32 rx_stuck_recovery_cnt; + /** Rx Stuck TSF */ + t_u64 rx_stuck_tsf[2]; + /** Tx Watchdog Recovery Related Info */ + /** Tx Watchdog Recovery count */ + t_u32 tx_watchdog_recovery_cnt; + /** Tx Watchdog TSF */ + t_u64 tx_watchdog_tsf[2]; + /** Channel Switch Related Info */ + /** Channel Switch Announcement Sent */ + t_u32 channel_switch_ann_sent; + /** Channel Switch State */ + t_u32 channel_switch_state; + /** Register Class */ + t_u32 reg_class; + /** Channel Number */ + t_u32 channel_number; + /** Channel Switch Mode */ + t_u32 channel_switch_mode; } mlan_ds_get_stats, *pmlan_ds_get_stats; /** Type definition of mlan_ds_uap_stats for MLAN_OID_GET_STATS */ @@ -4077,6 +4101,8 @@ typedef struct _mlan_ds_11h_dfs_testing { /** User-configured fixed channel to change to, 0 to use random channel */ t_u8 usr_fixed_new_chan; + /** User-configured cac restart */ + t_u8 usr_cac_restart; } mlan_ds_11h_dfs_testing, *pmlan_ds_11h_dfs_testing; /** Type definition of mlan_ds_11h_dfs_testing for MLAN_OID_11H_CHAN_NOP_INFO */ @@ -4347,6 +4373,16 @@ typedef struct _mlan_ds_misc_arb_cfg { t_u32 arb_mode; } mlan_ds_misc_arb_cfg; +/** Type definition of mlan_ds_misc_tp_state + * for MLAN_OID_MISC_TP_STATE + */ +typedef struct _mlan_ds_misc_tp_state { + /** TP account mode 0-disable 1-enable */ + t_u32 on; + /** Packet drop point */ + t_u32 drop_point; +} mlan_ds_misc_tp_state; + /** Type definition of mlan_ds_misc_country_code * for MLAN_OID_MISC_COUNTRY_CODE */ @@ -5099,6 +5135,7 @@ typedef struct _mlan_ds_misc_cfg { mlan_ds_misc_cfp_tbl cfp; t_u8 range_ext_mode; mlan_ds_misc_dot11mc_unassoc_ftm_cfg dot11mc_unassoc_ftm_cfg; + mlan_ds_misc_tp_state tp_state; } param; } mlan_ds_misc_cfg, *pmlan_ds_misc_cfg; diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_main.h b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_main.h index 5c4ff7136f11c2..2e3019f4746005 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_main.h +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_main.h @@ -440,9 +440,9 @@ extern t_void (*assert_callback)(t_void *pmoal_handle, t_u32 cond); #define MRVDRV_MAX_CFP_CODE_A 5 /** high rx pending packets */ -#define HIGH_RX_PENDING 100 +#define HIGH_RX_PENDING 1000 /** low rx pending packets */ -#define LOW_RX_PENDING 80 +#define LOW_RX_PENDING 800 /** Default region code */ #define MRVDRV_DEFAULT_REGION_CODE 0x10 @@ -1602,6 +1602,14 @@ typedef struct { t_bool no_channel_change_on_radar; /** user-configured new channel to change to on radar */ t_u8 fixed_new_channel_on_radar; + /** user-configured cac restart */ + t_u8 cac_restart; + /** cac channel */ + t_u8 chan; + /** band cfg */ + Band_Config_t bandcfg; + /** cac time */ + t_u32 millisec_dwell_time; } wlan_dfs_testing_settings_t; /** @@ -2658,6 +2666,10 @@ typedef struct _mlan_adapter { /** authenticator_priv */ pmlan_private authenticator_priv; #endif + /** TP accounting mode 1-enable 0-disable */ + t_u32 tp_state_on; + /** Packet drop point */ + t_u32 tp_state_drop_point; } mlan_adapter, *pmlan_adapter; /** Check if stream 2X2 enabled */ @@ -3362,6 +3374,8 @@ mlan_status wlan_misc_ioctl_range_ext(pmlan_adapter pmadapter, pmlan_ioctl_req pioctl_req); mlan_status wlan_misc_ioctl_arb_cfg(pmlan_adapter pmadapter, pmlan_ioctl_req pioctl_req); +mlan_status wlan_misc_ioctl_tp_state(pmlan_adapter pmadapter, + pmlan_ioctl_req pioctl_req); /* CFP related functions */ /** Region code index table */ extern t_u16 region_code_index[MRVDRV_MAX_REGION_CODE]; diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_pcie.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_pcie.c index 7d4977e52c5b80..51e55a90b73b7f 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_pcie.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_pcie.c @@ -1959,21 +1959,35 @@ static mlan_status wlan_pcie_process_recv_data(mlan_adapter *pmadapter) /* send buffer to host (which will free it) */ pmbuf->data_len = rx_len - PCIE_INTF_HEADER_LEN; pmbuf->data_offset += PCIE_INTF_HEADER_LEN; - PRINTM(MINFO, - "RECV DATA: Received packet from FW successfully\n"); - pmadapter->callbacks.moal_spin_lock( - pmadapter->pmoal_handle, - pmadapter->rx_data_queue.plock); - util_enqueue_list_tail(pmadapter->pmoal_handle, - &pmadapter->rx_data_queue, - (pmlan_linked_list)pmbuf, MNULL, - MNULL); - pmadapter->rx_pkts_queued++; - pmadapter->callbacks.moal_spin_unlock( - pmadapter->pmoal_handle, - pmadapter->rx_data_queue.plock); + // rx_trace 5 + if (pmadapter->tp_state_on) + pmadapter->callbacks.moal_tp_accounting( + pmadapter->pmoal_handle, pmbuf, + 5 /*RX_DROP_P1*/); + if (pmadapter->tp_state_drop_point == + 5 /*RX_DROP_P1*/) { + pmadapter->ops.data_complete(pmadapter, pmbuf, + ret); + } else { + PRINTM(MINFO, + "RECV DATA: Received packet from FW successfully\n"); + pmadapter->callbacks.moal_spin_lock( + pmadapter->pmoal_handle, + pmadapter->rx_data_queue.plock); + util_enqueue_list_tail( + pmadapter->pmoal_handle, + &pmadapter->rx_data_queue, + (pmlan_linked_list)pmbuf, MNULL, MNULL); + pmadapter->rx_pkts_queued++; + pmadapter->callbacks.moal_tp_accounting_rx_param( + pmadapter->pmoal_handle, 1, + pmadapter->rx_pkts_queued); + pmadapter->callbacks.moal_spin_unlock( + pmadapter->pmoal_handle, + pmadapter->rx_data_queue.plock); - pmadapter->data_received = MTRUE; + pmadapter->data_received = MTRUE; + } /* Create new buffer and attach it to Rx Ring */ pmbuf = wlan_alloc_mlan_buffer(pmadapter, MLAN_RX_DATA_BUF_SIZE, @@ -3463,6 +3477,8 @@ mlan_status wlan_process_pcie_int_status(mlan_adapter *pmadapter) pcie_ireg &= ~pmadapter->pcard_pcie->reg->host_intr_upld_rdy; PRINTM(MINFO, "Rx DATA\n"); + pmadapter->callbacks.moal_tp_accounting_rx_param( + pmadapter->pmoal_handle, 0, 0); ret = wlan_pcie_process_recv_data(pmadapter); if (ret) goto done; diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_shim.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_shim.c index 2859aa9e77e996..c5fc7f5085c76b 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_shim.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_shim.c @@ -1002,6 +1002,17 @@ mlan_status mlan_rx_process(t_void *pmlan_adapter, t_u8 *rx_pkts) pmadapter->callbacks.moal_spin_unlock( pmadapter->pmoal_handle, pmadapter->rx_data_queue.plock); + + // rx_trace 6 + if (pmadapter->tp_state_on) + pmadapter->callbacks.moal_tp_accounting( + pmadapter->pmoal_handle, pmbuf, + 6 /*RX_DROP_P2*/); + if (pmadapter->tp_state_drop_point == 6 /*RX_DROP_P2*/) { + pmadapter->ops.data_complete(pmadapter, pmbuf, ret); + goto rx_process_start; + } + if (pmadapter->delay_task_flag && (pmadapter->rx_pkts_queued < LOW_RX_PENDING)) { PRINTM(MEVENT, "Run\n"); @@ -1082,6 +1093,8 @@ mlan_status mlan_main_process(t_void *pmlan_adapter) #if defined(SDIO) || defined(PCIE) if (!IS_USB(pmadapter->card_type)) { if (pmadapter->rx_pkts_queued > HIGH_RX_PENDING) { + pcb->moal_tp_accounting_rx_param( + pmadapter->pmoal_handle, 2, 0); PRINTM(MEVENT, "Pause\n"); pmadapter->delay_task_flag = MTRUE; mlan_queue_rx_work(pmadapter); @@ -1318,10 +1331,22 @@ mlan_status mlan_send_packet(t_void *pmlan_adapter, pmlan_buffer pmbuf) PRINTM(MMSG, "wlan: Send EAPOL pkt to " MACSTR "\n", MAC2STR(pmbuf->pbuf + pmbuf->data_offset)); } - wlan_add_buf_bypass_txqueue(pmadapter, pmbuf); + if (pmadapter->tp_state_on) + pmadapter->callbacks.moal_tp_accounting( + pmadapter->pmoal_handle, pmbuf->pdesc, 2); + if (pmadapter->tp_state_drop_point == 2) + return 0; + else + wlan_add_buf_bypass_txqueue(pmadapter, pmbuf); } else { - /* Transmit the packet*/ - wlan_wmm_add_buf_txqueue(pmadapter, pmbuf); + if (pmadapter->tp_state_on) + pmadapter->callbacks.moal_tp_accounting( + pmadapter->pmoal_handle, pmbuf->pdesc, 2); + if (pmadapter->tp_state_drop_point == 2) + return 0; + else + /* Transmit the packet*/ + wlan_wmm_add_buf_txqueue(pmadapter, pmbuf); } LEAVE(); diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_sta_cmdresp.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_sta_cmdresp.c index 4cd48b8157679f..a7fee3788925a4 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_sta_cmdresp.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_sta_cmdresp.c @@ -593,6 +593,32 @@ static mlan_status wlan_ret_get_log(pmlan_private pmpriv, pget_info->param.stats.amsdu_tx_cnt = pmpriv->amsdu_tx_cnt; pget_info->param.stats.msdu_in_tx_amsdu_cnt = pmpriv->msdu_in_tx_amsdu_cnt; + pget_info->param.stats.rx_stuck_issue_cnt[0] = + wlan_le32_to_cpu(pget_log->rx_stuck_issue_cnt[0]); + pget_info->param.stats.rx_stuck_issue_cnt[1] = + wlan_le32_to_cpu(pget_log->rx_stuck_issue_cnt[1]); + pget_info->param.stats.rx_stuck_recovery_cnt = + wlan_le32_to_cpu(pget_log->rx_stuck_recovery_cnt); + pget_info->param.stats.rx_stuck_tsf[0] = + wlan_le64_to_cpu(pget_log->rx_stuck_tsf[0]); + pget_info->param.stats.rx_stuck_tsf[1] = + wlan_le64_to_cpu(pget_log->rx_stuck_tsf[1]); + pget_info->param.stats.tx_watchdog_recovery_cnt = + wlan_le32_to_cpu(pget_log->tx_watchdog_recovery_cnt); + pget_info->param.stats.tx_watchdog_tsf[0] = + wlan_le64_to_cpu(pget_log->tx_watchdog_tsf[0]); + pget_info->param.stats.tx_watchdog_tsf[1] = + wlan_le64_to_cpu(pget_log->tx_watchdog_tsf[1]); + pget_info->param.stats.channel_switch_ann_sent = + wlan_le32_to_cpu(pget_log->channel_switch_ann_sent); + pget_info->param.stats.channel_switch_state = + wlan_le32_to_cpu(pget_log->channel_switch_state); + pget_info->param.stats.reg_class = + wlan_le32_to_cpu(pget_log->reg_class); + pget_info->param.stats.channel_number = + wlan_le32_to_cpu(pget_log->channel_number); + pget_info->param.stats.channel_switch_mode = + wlan_le32_to_cpu(pget_log->channel_switch_mode); if (pmpriv->adapter->getlog_enable) { pget_info->param.stats.tx_frag_cnt = wlan_le32_to_cpu(pget_log->tx_frag_cnt); diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_sta_event.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_sta_event.c index 852f5d395a5a69..cc96e9ac7e12a0 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_sta_event.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_sta_event.c @@ -981,7 +981,7 @@ mlan_status wlan_ops_sta_process_event(t_void *priv) pevent->bss_index = pmpriv->bss_index; pevent->event_id = MLAN_EVENT_ID_SSU_DUMP_FILE; pevent->event_len = MLAN_SSU_BUF_SIZE; - *(t_u64 *)pevent->event_buf = (t_u64)pmadapter->ssu_buf->pbuf + + *(t_ptr *)pevent->event_buf = (t_ptr)pmadapter->ssu_buf->pbuf + pmadapter->ssu_buf->data_offset; wlan_recv_event(pmpriv, pevent->event_id, pevent); wlan_free_ssu_pcie_buf(pmadapter); diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_sta_ioctl.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_sta_ioctl.c index 6724a17f274206..c565144f04ac9e 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_sta_ioctl.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_sta_ioctl.c @@ -4806,6 +4806,29 @@ mlan_status wlan_misc_ioctl_arb_cfg(pmlan_adapter pmadapter, return ret; } +/** + * @brief Save tp accounting command configurations. + * + * @param pmadapter A pointer to mlan_adapter structure + * @param pioctl_req A pointer to ioctl request buffer + * + * @return MLAN_STATUS_PENDING --success, otherwise fail + */ +mlan_status wlan_misc_ioctl_tp_state(pmlan_adapter pmadapter, + pmlan_ioctl_req pioctl_req) +{ + mlan_ds_misc_cfg *pmisc = (mlan_ds_misc_cfg *)pioctl_req->pbuf; + mlan_status ret = MLAN_STATUS_SUCCESS; + + ENTER(); + + pmadapter->tp_state_on = pmisc->param.tp_state.on; + pmadapter->tp_state_drop_point = pmisc->param.tp_state.drop_point; + + LEAVE(); + return ret; +} + mlan_status wlan_misc_ioctl_get_sensor_temp(pmlan_adapter pmadapter, pmlan_ioctl_req pioctl_req) { @@ -5174,6 +5197,9 @@ static mlan_status wlan_misc_cfg_ioctl(pmlan_adapter pmadapter, case MLAN_OID_MISC_RANGE_EXT: status = wlan_misc_ioctl_range_ext(pmadapter, pioctl_req); break; + case MLAN_OID_MISC_TP_STATE: + status = wlan_misc_ioctl_tp_state(pmadapter, pioctl_req); + break; default: if (pioctl_req) pioctl_req->status_code = MLAN_ERROR_IOCTL_INVALID; diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_txrx.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_txrx.c index caf25708f98d94..a8c93d5322db57 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_txrx.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_txrx.c @@ -124,9 +124,15 @@ mlan_status wlan_process_tx(pmlan_private priv, pmlan_buffer pmbuf, if (GET_BSS_ROLE(priv) == MLAN_BSS_ROLE_STA) plocal_tx_pd = (TxPD *)(head_ptr + priv->intf_hr_len); #endif - - ret = pmadapter->ops.host_to_card(priv, MLAN_TYPE_DATA, pmbuf, - tx_param); + if (pmadapter->tp_state_on) + pmadapter->callbacks.moal_tp_accounting(pmadapter->pmoal_handle, + pmbuf, 4); + if (pmadapter->tp_state_drop_point == 4) + goto done; + else { + ret = pmadapter->ops.host_to_card(priv, MLAN_TYPE_DATA, pmbuf, + tx_param); + } done: switch (ret) { #ifdef USB diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_uap_cmdevent.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_uap_cmdevent.c index 86a6e72d1cffae..1f905eb56b33a4 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_uap_cmdevent.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_uap_cmdevent.c @@ -3142,6 +3142,32 @@ static mlan_status wlan_uap_ret_get_log(pmlan_private pmpriv, pget_info->param.stats.amsdu_tx_cnt = pmpriv->amsdu_tx_cnt; pget_info->param.stats.msdu_in_tx_amsdu_cnt = pmpriv->msdu_in_tx_amsdu_cnt; + pget_info->param.stats.rx_stuck_issue_cnt[0] = + wlan_le32_to_cpu(pget_log->rx_stuck_issue_cnt[0]); + pget_info->param.stats.rx_stuck_issue_cnt[1] = + wlan_le32_to_cpu(pget_log->rx_stuck_issue_cnt[1]); + pget_info->param.stats.rx_stuck_recovery_cnt = + wlan_le32_to_cpu(pget_log->rx_stuck_recovery_cnt); + pget_info->param.stats.rx_stuck_tsf[0] = + wlan_le64_to_cpu(pget_log->rx_stuck_tsf[0]); + pget_info->param.stats.rx_stuck_tsf[1] = + wlan_le64_to_cpu(pget_log->rx_stuck_tsf[1]); + pget_info->param.stats.tx_watchdog_recovery_cnt = + wlan_le32_to_cpu(pget_log->tx_watchdog_recovery_cnt); + pget_info->param.stats.tx_watchdog_tsf[0] = + wlan_le64_to_cpu(pget_log->tx_watchdog_tsf[0]); + pget_info->param.stats.tx_watchdog_tsf[1] = + wlan_le64_to_cpu(pget_log->tx_watchdog_tsf[1]); + pget_info->param.stats.channel_switch_ann_sent = + wlan_le32_to_cpu(pget_log->channel_switch_ann_sent); + pget_info->param.stats.channel_switch_state = + wlan_le32_to_cpu(pget_log->channel_switch_state); + pget_info->param.stats.reg_class = + wlan_le32_to_cpu(pget_log->reg_class); + pget_info->param.stats.channel_number = + wlan_le32_to_cpu(pget_log->channel_number); + pget_info->param.stats.channel_switch_mode = + wlan_le32_to_cpu(pget_log->channel_switch_mode); if (pmpriv->adapter->getlog_enable) { pget_info->param.stats.tx_frag_cnt = wlan_le32_to_cpu(pget_log->tx_frag_cnt); @@ -5225,7 +5251,16 @@ mlan_status wlan_ops_uap_process_event(t_void *priv) case EVENT_RADAR_DETECTED: PRINTM_NETINTF(MEVENT, pmpriv); PRINTM(MEVENT, "EVENT: Radar Detected\n"); - + if (pmpriv->adapter->dfs_test_params.cac_restart && + pmpriv->adapter->state_dfs.dfs_check_pending) { + wlan_11h_cancel_radar_detect(pmpriv); + wlan_11h_issue_radar_detect( + pmpriv, MNULL, + pmpriv->adapter->dfs_test_params.chan, + pmpriv->adapter->dfs_test_params.bandcfg); + pevent->event_id = 0; + break; + } /* Send as passthru first, this event can cause other events */ memset(pmadapter, event_buf, 0x00, MAX_EVENT_SIZE); pevent->bss_index = pmpriv->bss_index; @@ -5291,6 +5326,7 @@ mlan_status wlan_ops_uap_process_event(t_void *priv) case EVENT_CHANNEL_REPORT_RDY: PRINTM_NETINTF(MEVENT, pmpriv); PRINTM(MEVENT, "EVENT: Channel Report Ready\n"); + pmpriv->adapter->dfs_test_params.cac_restart = MFALSE; memset(pmadapter, event_buf, 0x00, MAX_EVENT_SIZE); /* Setup event buffer */ pevent->bss_index = pmpriv->bss_index; @@ -5304,7 +5340,6 @@ mlan_status wlan_ops_uap_process_event(t_void *priv) /* Handle / pass event data, and free buffer */ ret = wlan_11h_handle_event_chanrpt_ready(pmpriv, pevent, &channel); - if (pmpriv->intf_state_11h.is_11h_host) { *((t_u8 *)pevent->event_buf) = pmpriv->adapter->state_dfs.dfs_radar_found; diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_uap_ioctl.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_uap_ioctl.c index 8de4bd3d08aed4..2610627c123ba3 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_uap_ioctl.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_uap_ioctl.c @@ -2175,8 +2175,8 @@ mlan_status wlan_ops_uap_ioctl(t_void *adapter, pmlan_ioctl_req pioctl_req) status = wlan_11h_ioctl_get_channel_nop_info( pmadapter, pioctl_req); if (cfg11h->sub_command == MLAN_OID_11H_CHAN_REPORT_REQUEST) - status = wlan_11h_ioctl_dfs_cancel_chan_report( - pmpriv, pioctl_req); + status = wlan_11h_ioctl_dfs_chan_report(pmpriv, + pioctl_req); if (cfg11h->sub_command == MLAN_OID_11H_CHAN_SWITCH_COUNT) status = wlan_11h_ioctl_chan_switch_count(pmadapter, pioctl_req); diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_wmm.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_wmm.c index c9200b81672ec8..f32a1668709059 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_wmm.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_wmm.c @@ -1028,6 +1028,7 @@ static int wlan_dequeue_tx_packet(pmlan_adapter pmadapter) t_u8 ra[MLAN_MAC_ADDR_LENGTH]; int tid_del = 0; int tid = 0; + mlan_buffer *pmbuf = MNULL; ENTER(); @@ -1064,6 +1065,33 @@ static int wlan_dequeue_tx_packet(pmlan_adapter pmadapter) } if (ptr->del_ba_count >= DEL_BA_THRESHOLD) wlan_update_del_ba_count(priv, ptr); + if (pmadapter->tp_state_on) { + pmbuf = (pmlan_buffer)util_peek_list( + pmadapter->pmoal_handle, &ptr->buf_head, MNULL, MNULL); + if (pmbuf) { + pmadapter->callbacks.moal_tp_accounting( + pmadapter->pmoal_handle, pmbuf->pdesc, 3); + if (pmadapter->tp_state_drop_point == 3) { + pmbuf = (pmlan_buffer)util_dequeue_list( + pmadapter->pmoal_handle, &ptr->buf_head, + MNULL, MNULL); + PRINTM(MERROR, "Dequeuing the packet %p %p\n", + ptr, pmbuf); + priv->wmm.pkts_queued[ptrindex]--; + util_scalar_decrement(pmadapter->pmoal_handle, + &priv->wmm.tx_pkts_queued, + MNULL, MNULL); + ptr->total_pkts--; + pmadapter->callbacks.moal_spin_unlock( + pmadapter->pmoal_handle, + priv->wmm.ra_list_spinlock); + wlan_write_data_complete(pmadapter, pmbuf, + MLAN_STATUS_SUCCESS); + LEAVE(); + return MLAN_STATUS_SUCCESS; + } + } + } if (!ptr->is_11n_enabled || (ptr->ba_status || ptr->del_ba_count >= DEL_BA_THRESHOLD) #ifdef STA_SUPPORT diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/mlan_decl.h b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/mlan_decl.h index 9037910c11a9ca..7d0b75cc3c5470 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/mlan_decl.h +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/mlan_decl.h @@ -24,7 +24,7 @@ #define _MLAN_DECL_H_ /** MLAN release version */ -#define MLAN_RELEASE_VERSION "210" +#define MLAN_RELEASE_VERSION "215.p2" /** Re-define generic data types for MLAN/MOAL */ /** Signed char (1-byte) */ @@ -857,6 +857,23 @@ enum { SCAN_MODE_MANUAL = 0, SCAN_MODE_USER, }; +/** max cac time 10 minutes */ +#define MAX_CAC_DWELL_TIME 600000 +/** default cac time 60 seconds */ +#define DEF_CAC_DWELL_TIME 60000 +/** start freq for 5G */ +#define START_FREQ_11A_BAND 5000 +/** DFS state */ +typedef enum _dfs_state_t { + /** Channel can be used, CAC (Channel Availability Check) must be done + before using it */ + DFS_USABLE = 0, + /** Channel is not available, radar was detected */ + DFS_UNAVAILABLE = 1, + /** Channel is Available, CAC is done and is free of radar */ + DFS_AVAILABLE = 2, +} dfs_state_t; + typedef enum _dfs_w53_cfg_t { /** DFS W53 Default Fw Value */ DFS_W53_DEFAULT_FW = 0, @@ -1747,6 +1764,12 @@ typedef struct _mlan_callbacks { mlan_status (*moal_notify_hostcmd_complete)(t_void *pmoal_handle, t_u32 bss_index); #endif + void (*moal_tp_accounting)(t_void *pmoal_handle, t_void *buf, + t_u32 drop_point); + void (*moal_tp_accounting_rx_param)(t_void *pmoal_handle, + unsigned int type, + unsigned int rsvd1); + } mlan_callbacks, *pmlan_callbacks; /** Parameter unchanged, use MLAN default setting */ diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/mlan_ioctl.h b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/mlan_ioctl.h index caaadb03ca53a7..2315b2a2b79ec7 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/mlan_ioctl.h +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/mlan_ioctl.h @@ -331,6 +331,7 @@ enum _mlan_ioctl_req_id { MLAN_OID_MISC_CFP_TABLE = 0x0020007A, MLAN_OID_MISC_RANGE_EXT = 0x0020007B, MLAN_OID_MISC_DOT11MC_UNASSOC_FTM_CFG = 0x0020007C, + MLAN_OID_MISC_TP_STATE = 0x0020007D, }; /** Sub command size */ @@ -1594,6 +1595,29 @@ typedef struct _mlan_ds_get_stats { t_u64 rx_octets_in_ampdu_cnt; /** ampdu delimiter CRC error count */ t_u32 ampdu_delimiter_crc_error_cnt; + /** Rx Stuck Related Info*/ + /** Rx Stuck Issue count */ + t_u32 rx_stuck_issue_cnt[2]; + /** Rx Stuck Recovery count */ + t_u32 rx_stuck_recovery_cnt; + /** Rx Stuck TSF */ + t_u64 rx_stuck_tsf[2]; + /** Tx Watchdog Recovery Related Info */ + /** Tx Watchdog Recovery count */ + t_u32 tx_watchdog_recovery_cnt; + /** Tx Watchdog TSF */ + t_u64 tx_watchdog_tsf[2]; + /** Channel Switch Related Info */ + /** Channel Switch Announcement Sent */ + t_u32 channel_switch_ann_sent; + /** Channel Switch State */ + t_u32 channel_switch_state; + /** Register Class */ + t_u32 reg_class; + /** Channel Number */ + t_u32 channel_number; + /** Channel Switch Mode */ + t_u32 channel_switch_mode; } mlan_ds_get_stats, *pmlan_ds_get_stats; /** Type definition of mlan_ds_uap_stats for MLAN_OID_GET_STATS */ @@ -4077,6 +4101,8 @@ typedef struct _mlan_ds_11h_dfs_testing { /** User-configured fixed channel to change to, 0 to use random channel */ t_u8 usr_fixed_new_chan; + /** User-configured cac restart */ + t_u8 usr_cac_restart; } mlan_ds_11h_dfs_testing, *pmlan_ds_11h_dfs_testing; /** Type definition of mlan_ds_11h_dfs_testing for MLAN_OID_11H_CHAN_NOP_INFO */ @@ -4347,6 +4373,16 @@ typedef struct _mlan_ds_misc_arb_cfg { t_u32 arb_mode; } mlan_ds_misc_arb_cfg; +/** Type definition of mlan_ds_misc_tp_state + * for MLAN_OID_MISC_TP_STATE + */ +typedef struct _mlan_ds_misc_tp_state { + /** TP account mode 0-disable 1-enable */ + t_u32 on; + /** Packet drop point */ + t_u32 drop_point; +} mlan_ds_misc_tp_state; + /** Type definition of mlan_ds_misc_country_code * for MLAN_OID_MISC_COUNTRY_CODE */ @@ -5099,6 +5135,7 @@ typedef struct _mlan_ds_misc_cfg { mlan_ds_misc_cfp_tbl cfp; t_u8 range_ext_mode; mlan_ds_misc_dot11mc_unassoc_ftm_cfg dot11mc_unassoc_ftm_cfg; + mlan_ds_misc_tp_state tp_state; } param; } mlan_ds_misc_cfg, *pmlan_ds_misc_cfg; diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_cfg80211_util.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_cfg80211_util.c index 0e124c5950038a..464999f9bda2f4 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_cfg80211_util.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_cfg80211_util.c @@ -143,11 +143,9 @@ static const struct nla_policy woal_fw_roaming_policy[MRVL_WLAN_VENDOR_ATTR_FW_ROAMING_MAX + 1] = { [MRVL_WLAN_VENDOR_ATTR_FW_ROAMING_CONTROL] = {.type = NLA_U32}, [MRVL_WLAN_VENDOR_ATTR_FW_ROAMING_CONFIG_BSSID] = { - .type = NLA_BINARY, - .len = sizeof(int)}, + .type = NLA_BINARY}, [MRVL_WLAN_VENDOR_ATTR_FW_ROAMING_CONFIG_SSID] = { - .type = NLA_BINARY, - .len = sizeof(int)}, + .type = NLA_BINARY}, }; // clang-format on @@ -155,7 +153,7 @@ static const struct nla_policy woal_keep_alive_policy[MKEEP_ALIVE_ATTRIBUTE_MAX + 1] = { [MKEEP_ALIVE_ATTRIBUTE_ID] = {.type = NLA_U8}, [MKEEP_ALIVE_ATTRIBUTE_ETHER_TYPE] = {.type = NLA_U16}, - [MKEEP_ALIVE_ATTRIBUTE_IP_PKT] = {.type = NLA_BINARY, .len = 1}, + [MKEEP_ALIVE_ATTRIBUTE_IP_PKT] = {.type = NLA_BINARY}, [MKEEP_ALIVE_ATTRIBUTE_IP_PKT_LEN] = {.type = NLA_U16}, [MKEEP_ALIVE_ATTRIBUTE_SRC_MAC_ADDR] = {.type = NLA_STRING, .len = ETH_ALEN}, diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_eth_ioctl.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_eth_ioctl.c index d262fcd0a4b02a..60d229b2abbe0e 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_eth_ioctl.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_eth_ioctl.c @@ -1,3 +1,4 @@ + /** @file moal_eth_ioctl.c * * @brief This file contains private ioctl functions @@ -10320,7 +10321,7 @@ static int woal_priv_dfs_testing(moal_private *priv, t_u8 *respbuf, mlan_ioctl_req *req = NULL; mlan_ds_11h_cfg *ds_11hcfg = NULL; int ret = 0; - int data[4] = {0}; + int data[5] = {0}; int user_data_len = 0, header_len = 0; mlan_status status = MLAN_STATUS_SUCCESS; @@ -10347,14 +10348,14 @@ static int woal_priv_dfs_testing(moal_private *priv, t_u8 *respbuf, /* SET operation */ parse_arguments(respbuf + header_len, data, ARRAY_SIZE(data), &user_data_len); - if (user_data_len != 4) { + if (user_data_len != 5) { PRINTM(MERROR, "Invalid number of args!\n"); ret = -EINVAL; goto done; } - if ((unsigned)data[0] > 0xFFFFF) { + if ((unsigned)data[0] > 1800) { PRINTM(MERROR, - "The maximum user CAC is 1048575 msec (17 mins approx).\n"); + "The maximum user CAC is 1800 seconds (30 mins).\n"); ret = -EINVAL; goto done; } @@ -10369,6 +10370,12 @@ static int woal_priv_dfs_testing(moal_private *priv, t_u8 *respbuf, ret = -EINVAL; goto done; } + if ((unsigned)data[4] != 0 && ((unsigned)data[4] != 1)) { + PRINTM(MERROR, "CAC restart should be 0/1\n"); + ret = -EINVAL; + goto done; + } + ds_11hcfg->param.dfs_testing.usr_cac_period_msec = (t_u32)data[0] * 1000; ds_11hcfg->param.dfs_testing.usr_nop_period_sec = @@ -10376,6 +10383,8 @@ static int woal_priv_dfs_testing(moal_private *priv, t_u8 *respbuf, ds_11hcfg->param.dfs_testing.usr_no_chan_change = data[2] ? 1 : 0; ds_11hcfg->param.dfs_testing.usr_fixed_new_chan = (t_u8)data[3]; + ds_11hcfg->param.dfs_testing.usr_cac_restart = (t_u8)data[4]; + priv->phandle->cac_restart = (t_u8)data[4]; priv->phandle->cac_period_jiffies = (t_u32)data[0] * HZ / 1000; priv->phandle->usr_nop_period_sec = (t_u16)data[1]; req->action = MLAN_ACT_SET; @@ -10398,6 +10407,7 @@ static int woal_priv_dfs_testing(moal_private *priv, t_u8 *respbuf, data[1] = ds_11hcfg->param.dfs_testing.usr_nop_period_sec; data[2] = ds_11hcfg->param.dfs_testing.usr_no_chan_change; data[3] = ds_11hcfg->param.dfs_testing.usr_fixed_new_chan; + data[4] = ds_11hcfg->param.dfs_testing.usr_cac_restart; moal_memcpy_ext(priv->phandle, respbuf, (t_u8 *)data, sizeof(data), respbuflen); ret = sizeof(data); @@ -14823,6 +14833,150 @@ int woal_priv_arbcfg(moal_private *priv, t_u8 *respbuf, t_u32 respbuflen) LEAVE(); return ret; } + +/** + * @brief Timer function for TP state command. + * + * @param data pointer to a buffer + * + * @return N/A + */ +void woal_tp_acnt_timer_func(void *context) +{ + moal_handle *phandle = (moal_handle *)context; + int i = 0; + + if (phandle == NULL) + return; + PRINTM(MDATA, "####### CPU%d: tp acnt timer\n", smp_processor_id()); + /* Tx TP accounting */ + for (i = 0; i < MAX_TP_ACCOUNT_DROP_POINT_NUM; i++) { + phandle->tp_acnt.tx_bytes_rate[i] = + phandle->tp_acnt.tx_bytes[i] - + phandle->tp_acnt.tx_bytes_last[i]; + phandle->tp_acnt.tx_bytes_last[i] = + phandle->tp_acnt.tx_bytes[i]; + } + phandle->tp_acnt.tx_pending = atomic_read(&phandle->tx_pending); + /* Tx Interrupt accounting */ + phandle->tp_acnt.tx_intr_rate = + phandle->tp_acnt.tx_intr_cnt - phandle->tp_acnt.tx_intr_last; + phandle->tp_acnt.tx_intr_last = phandle->tp_acnt.tx_intr_cnt; + + /* Rx TP accounting */ + for (i = 0; i < MAX_TP_ACCOUNT_DROP_POINT_NUM; i++) { + phandle->tp_acnt.rx_bytes_rate[i] = + phandle->tp_acnt.rx_bytes[i] - + phandle->tp_acnt.rx_bytes_last[i]; + phandle->tp_acnt.rx_bytes_last[i] = + phandle->tp_acnt.rx_bytes[i]; + } + phandle->tp_acnt.rx_pending = atomic_read(&phandle->rx_pending); + // Interrupt accounting, RX + phandle->tp_acnt.rx_intr_rate = + phandle->tp_acnt.rx_intr_cnt - phandle->tp_acnt.rx_intr_last; + phandle->tp_acnt.rx_intr_last = phandle->tp_acnt.rx_intr_cnt; + + /* re-arm timer */ + woal_mod_timer(&phandle->tp_acnt.timer, 1000); +} + +/** + * @brief set tp state to mlan + * + * @param priv pointer to moal_private + * + * @return N/A + */ +void woal_set_tp_state(moal_private *priv) +{ + mlan_ioctl_req *req = NULL; + mlan_ds_misc_cfg *misc = NULL; + moal_handle *handle = priv->phandle; + mlan_status status = MLAN_STATUS_SUCCESS; + req = woal_alloc_mlan_ioctl_req(sizeof(mlan_ds_misc_cfg)); + if (req == NULL) + return; + /* Fill request buffer */ + misc = (mlan_ds_misc_cfg *)req->pbuf; + misc->sub_command = MLAN_OID_MISC_TP_STATE; + req->req_id = MLAN_IOCTL_MISC_CFG; + misc->param.tp_state.on = handle->tp_acnt.on; + misc->param.tp_state.drop_point = handle->tp_acnt.drop_point; + req->action = MLAN_ACT_SET; + /* Send IOCTL request to MLAN */ + status = woal_request_ioctl(priv, req, MOAL_IOCTL_WAIT); + if (status != MLAN_STATUS_PENDING) + kfree(req); + return; +} + +/** + * @brief Set/Get TP statistics. + * + * @param priv A pointer to moal_private structure + * @param respbuf A pointer to response buffer + * @param respbuflen Available length of response buffer + * + * @return Number of bytes written, negative for failure. + */ +int woal_priv_set_tp_state(moal_private *priv, t_u8 *respbuf, t_u32 respbuflen) +{ + moal_handle *handle = priv->phandle; + int ret = 0; + int data[2]; + int header_len = 0, user_data_len = 0; + + ENTER(); + + if (!respbuf) { + PRINTM(MERROR, "response buffer is not available!\n"); + ret = -EINVAL; + goto done; + } + header_len = strlen(CMD_NXP) + strlen(PRIV_CMD_TP_STATE); + user_data_len = strlen(respbuf) - header_len; + parse_arguments(respbuf + header_len, data, ARRAY_SIZE(data), + &user_data_len); + if (user_data_len > 2) { + PRINTM(MERROR, "Invalid number of args!\n"); + ret = -EINVAL; + goto done; + } + if (user_data_len) { + handle->tp_acnt.on = data[0]; + /* Enable TP statistics collection */ + if (data[0] == 1) { + handle->tp_acnt.drop_point = data[1]; + if (handle->is_tp_acnt_timer_set == MFALSE) { + woal_initialize_timer(&handle->tp_acnt.timer, + woal_tp_acnt_timer_func, + handle); + handle->is_tp_acnt_timer_set = MTRUE; + woal_mod_timer(&handle->tp_acnt.timer, 1000); + } + } else { + if (handle->is_tp_acnt_timer_set) { + woal_cancel_timer(&handle->tp_acnt.timer); + handle->is_tp_acnt_timer_set = MFALSE; + } + memset((void *)&handle->tp_acnt, 0, + sizeof(moal_tp_acnt_t)); + } + woal_set_tp_state(priv); + } + /* Get command results */ + if (user_data_len == 0) { + moal_memcpy_ext(handle, respbuf, (t_u8 *)(&handle->tp_acnt), + sizeof(handle->tp_acnt), respbuflen); + ret = sizeof(handle->tp_acnt); + } + +done: + LEAVE(); + return ret; +} + /** * @brief Set priv command for Android * @param dev A pointer to net_device structure @@ -15956,6 +16110,12 @@ int woal_android_priv_cmd(struct net_device *dev, struct ifreq *req) len = woal_priv_set_get_lpm(priv, buf, priv_cmd.total_len); goto handled; + } else if (strnicmp(buf + strlen(CMD_NXP), PRIV_CMD_TP_STATE, + strlen(PRIV_CMD_TP_STATE)) == 0) { + /* Set/Get TP accounting state */ + len = woal_priv_set_tp_state(priv, buf, + priv_cmd.total_len); + goto handled; } else { PRINTM(MERROR, "Unknown NXP PRIVATE command %s, ignored\n", diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_eth_ioctl.h b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_eth_ioctl.h index f27d269d1f17cc..57b203e833dd13 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_eth_ioctl.h +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_eth_ioctl.h @@ -670,4 +670,6 @@ typedef struct { /** chan_list */ wlan_ieee80211_chan chan_list[]; } __ATTRIB_PACK__ wlan_ieee80211_chan_list; + +#define PRIV_CMD_TP_STATE "tp_state" #endif /* _WOAL_ETH_PRIV_H_ */ diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_init.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_init.c index 077a6614dbc9fb..c57303951a04a1 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_init.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_init.c @@ -113,6 +113,7 @@ int shutdown_hs; /** SDIO slew rate */ int slew_rate = 3; #endif +int tx_work = 0; #if defined(STA_SUPPORT) /** 802.11d configuration */ @@ -1077,6 +1078,17 @@ static mlan_status parse_cfg_read_block(t_u8 *data, t_u32 size, PRINTM(MMSG, "napi %s\n", moal_extflg_isset(handle, EXT_NAPI) ? "on" : "off"); + } else if (strncmp(line, "tx_work", strlen("tx_work")) == 0) { + if (parse_line_read_int(line, &out_data) != + MLAN_STATUS_SUCCESS) + goto err; + if (out_data) + moal_extflg_set(handle, EXT_TX_WORK); + else + moal_extflg_clear(handle, EXT_TX_WORK); + PRINTM(MMSG, "tx_work %s\n", + moal_extflg_isset(handle, EXT_TX_WORK) ? "on" : + "off"); } #if CFG80211_VERSION_CODE >= KERNEL_VERSION(3, 14, 0) else if (strncmp(line, "dfs_offload", strlen("dfs_offload")) == @@ -1109,8 +1121,8 @@ static mlan_status parse_cfg_read_block(t_u8 *data, t_u32 size, PRINTM(MMSG, "reg domain set by driver=%s\n", moal_extflg_isset(handle, EXT_DISABLE_REGD_BY_DRIVER) ? - "disable" : - "enable"); + "enable" : + "disable"); } else if (strncmp(line, "reg_alpha2", strlen("reg_alpha2")) == 0) { if (parse_line_read_string(line, &out_str) != @@ -1146,8 +1158,8 @@ static mlan_status parse_cfg_read_block(t_u8 *data, t_u32 size, moal_extflg_clear(handle, EXT_BEACON_HINTS); PRINTM(MMSG, "beacon_hints=%s\n", moal_extflg_isset(handle, EXT_BEACON_HINTS) ? - "disable" : - "enable"); + "enable" : + "disable"); } #endif #endif @@ -1173,8 +1185,8 @@ static mlan_status parse_cfg_read_block(t_u8 *data, t_u32 size, moal_extflg_clear(handle, EXT_HOST_MLME); PRINTM(MMSG, "host_mlme=%s\n", moal_extflg_isset(handle, EXT_HOST_MLME) ? - "disable" : - "enable"); + "enable" : + "disable"); } #endif #endif @@ -1415,6 +1427,9 @@ static void woal_setup_module_param(moal_handle *handle, moal_mod_para *params) } if (napi) moal_extflg_set(handle, EXT_NAPI); + if (tx_work) + moal_extflg_set(handle, EXT_TX_WORK); + #if CFG80211_VERSION_CODE >= KERNEL_VERSION(3, 14, 0) if (dfs_offload) moal_extflg_set(handle, EXT_DFS_OFFLOAD); @@ -1622,6 +1637,12 @@ void woal_init_from_dev_tree(void) } } #endif + else if (!strncmp(prop->name, "tx_work", strlen("tx_work"))) { + if (!of_property_read_u32(dt_node, prop->name, &data)) { + PRINTM(MIOCTL, "tx_work=0x%x\n", data); + tx_work = data; + } + } #ifdef MFG_CMD_SUPPORT else if (!strncmp(prop->name, "mfg_mode", strlen("mfg_mode"))) { if (!of_property_read_u32(dt_node, prop->name, &data)) { @@ -2158,6 +2179,8 @@ MODULE_PARM_DESC( slew_rate, "0:has the slowest slew rate, then 01, then 02, and 03 has the highest slew rate"); #endif +module_param(tx_work, uint, 0660); +MODULE_PARM_DESC(tx_work, "1: Enable tx_work; 0: Disable tx_work"); module_param(dpd_data_cfg, charp, 0); MODULE_PARM_DESC(dpd_data_cfg, "DPD data file name"); module_param(init_cfg, charp, 0); diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_ioctl.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_ioctl.c index a6df8c052d6d4e..8cb4af25d096b7 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_ioctl.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_ioctl.c @@ -670,6 +670,8 @@ mlan_status woal_request_ioctl(moal_private *priv, mlan_ioctl_req *req, priv->phandle->cac_period_jiffies - (jiffies - priv->phandle->meas_start_jiffies); } + if (priv->phandle->cac_restart) + cac_left_jiffies = DEF_CAC_DWELL_TIME * HZ / 1000; if (cac_left_jiffies < 0) { /* Avoid driver hang in FW died during CAC measure * period */ diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_main.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_main.c index a4d5f0b8b919c8..2bd60785c8cbb6 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_main.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_main.c @@ -635,6 +635,8 @@ static mlan_callbacks woal_callbacks = { .moal_wait_hostcmd_complete = moal_wait_hostcmd_complete, .moal_notify_hostcmd_complete = moal_notify_hostcmd_complete, #endif + .moal_tp_accounting = moal_tp_accounting, + .moal_tp_accounting_rx_param = moal_tp_accounting_rx_param, }; int woal_open(struct net_device *dev); @@ -3731,6 +3733,7 @@ moal_private *woal_add_interface(moal_handle *handle, t_u8 bss_index, INIT_LIST_HEAD(&priv->tx_stat_queue); spin_lock_init(&priv->tx_stat_lock); + #ifdef STA_CFG80211 #ifdef STA_SUPPORT spin_lock_init(&priv->connect_lock); @@ -4329,7 +4332,11 @@ void woal_terminate_workqueue(moal_handle *handle) destroy_workqueue(handle->evt_workqueue); handle->evt_workqueue = NULL; } - + if (handle->tx_workqueue) { + flush_workqueue(handle->tx_workqueue); + destroy_workqueue(handle->tx_workqueue); + handle->tx_workqueue = NULL; + } LEAVE(); } @@ -5052,6 +5059,9 @@ void woal_flush_tx_stat_queue(moal_private *priv) } INIT_LIST_HEAD(&priv->tx_stat_queue); spin_unlock_irqrestore(&priv->tx_stat_lock, flags); + spin_lock_bh(&(priv->tx_q.lock)); + __skb_queue_purge(&priv->tx_q); + spin_unlock_bh(&(priv->tx_q.lock)); } /** @@ -5421,9 +5431,8 @@ int woal_process_tcp_ack(moal_private *priv, mlan_buffer *pmbuf) * * @return 0 --success */ -netdev_tx_t woal_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) +int woal_start_xmit(moal_private *priv, struct sk_buff *skb) { - moal_private *priv = (moal_private *)netdev_priv(dev); mlan_buffer *pmbuf = NULL; mlan_status status; struct sk_buff *new_skb = NULL; @@ -5433,14 +5442,7 @@ netdev_tx_t woal_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) int ret = 0; ENTER(); - PRINTM(MDATA, "%lu : %s (bss=%d): Data <= kernel\n", jiffies, dev->name, - priv->bss_index); - if (priv->phandle->surprise_removed == MTRUE) { - dev_kfree_skb_any(skb); - priv->stats.tx_dropped++; - goto done; - } priv->num_tx_timeout = 0; if (!skb->len || (skb->len > ETH_FRAME_LEN)) { PRINTM(MERROR, "Tx Error: Bad skb length %d : %d\n", skb->len, @@ -5529,6 +5531,50 @@ netdev_tx_t woal_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) return 0; } +/** + * @brief This function handles packet transmission + * + * @param skb A pointer to sk_buff structure + * @param dev A pointer to net_device structure + * + * @return 0 --success + */ +netdev_tx_t woal_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) +{ + moal_private *priv = (moal_private *)netdev_priv(dev); + ENTER(); + PRINTM(MDATA, "%lu : %s (bss=%d): Data <= kernel\n", jiffies, dev->name, + priv->bss_index); + + /* Collect TP statistics */ + if (priv->phandle->tp_acnt.on) + moal_tp_accounting(priv->phandle, skb, 1); + /* Drop Tx packets at drop point 1 */ + if (priv->phandle->tp_acnt.drop_point == 1) { + dev_kfree_skb_any(skb); + LEAVE(); + return 0; + } + if (priv->phandle->surprise_removed == MTRUE) { + dev_kfree_skb_any(skb); + priv->stats.tx_dropped++; + goto done; + } + if (moal_extflg_isset(priv->phandle, EXT_TX_WORK)) { + spin_lock_bh(&(priv->tx_q.lock)); + __skb_queue_tail(&(priv->tx_q), skb); + spin_unlock_bh(&(priv->tx_q.lock)); + + queue_work(priv->phandle->tx_workqueue, + &priv->phandle->tx_work); + goto done; + } + woal_start_xmit(priv, skb); +done: + LEAVE(); + return 0; +} + /** * @brief Convert ascii string to Hex integer * @@ -5793,6 +5839,7 @@ void woal_init_priv(moal_private *priv, t_u8 wait_option) } #endif + skb_queue_head_init(&priv->tx_q); memset(&priv->tx_protocols, 0, sizeof(dot11_protocol)); memset(&priv->rx_protocols, 0, sizeof(dot11_protocol)); priv->media_connected = MFALSE; @@ -6970,7 +7017,8 @@ t_void woal_store_ssu_dump(moal_handle *phandle, mlan_event *pmevent) return; } DBG_HEXDUMP(MEVT_D, "SSU addr", pmevent->event_buf, 8); - moal_memcpy_ext(phandle, &tmpbuf, pmevent->event_buf, 8, 8); + moal_memcpy_ext(phandle, &tmpbuf, pmevent->event_buf, sizeof(t_ptr), + sizeof(t_ptr)); PRINTM(MEVENT, "woal_store_ssu_dump: tmpbuf %p\n", tmpbuf); for (i = 0; i < pmevent->event_len / 4; i++) { if ((i + 1) % 8 == 0) @@ -8247,6 +8295,54 @@ t_void woal_rx_work_queue(struct work_struct *work) LEAVE(); } +/** + * @brief This function dequeue pkt from list + * + * @param list A pointer to struct sk_buff_head + * + * @return skb buffer + */ + +struct sk_buff *woal_skb_dequeue_spinlock(struct sk_buff_head *list) +{ + struct sk_buff *result; + + spin_lock_bh(&list->lock); + result = __skb_dequeue(list); + spin_unlock_bh(&list->lock); + return result; +} + +/** + * @brief This workqueue function handles rx_work_process + * + * @param work A pointer to work_struct + * + * @return N/A + */ +t_void woal_tx_work_handler(struct work_struct *work) +{ + moal_handle *handle = container_of(work, moal_handle, tx_work); + moal_private *priv = NULL; + int i = 0; + struct sk_buff *skb = NULL; + + ENTER(); + if (handle->surprise_removed == MTRUE) { + LEAVE(); + return; + } + + for (i = 0; i < MIN(handle->priv_num, MLAN_MAX_BSS_NUM); i++) { + priv = handle->priv[i]; + while ((skb = woal_skb_dequeue_spinlock(&priv->tx_q)) != NULL) { + woal_start_xmit(priv, skb); + } + } + + LEAVE(); +} + /** * @brief This workqueue function handles main_process * @@ -8535,6 +8631,26 @@ moal_handle *woal_add_card(void *card, struct device *dev, moal_if_ops *if_ops, napi_enable(&handle->napi_rx); } + if (moal_extflg_isset(handle, EXT_TX_WORK)) { + /* Create workqueue for tx process */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 14) + handle->tx_workqueue = create_workqueue("MOAL_TX_WORKQ"); +#else +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36) + handle->tx_workqueue = alloc_workqueue( + "MOAL_TX_WORK_QUEUE", + WQ_HIGHPRI | WQ_MEM_RECLAIM | WQ_UNBOUND, 1); +#else + handle->tx_workqueue = create_workqueue("MOAL_TX_WORK_QUEUE"); +#endif +#endif + if (!handle->tx_workqueue) { + woal_terminate_workqueue(handle); + goto err_kmalloc; + } + MLAN_INIT_WORK(&handle->tx_work, woal_tx_work_handler); + } + #ifdef REASSOCIATION PRINTM(MINFO, "Starting re-association thread...\n"); handle->reassoc_thread.handle = handle; @@ -8676,6 +8792,8 @@ mlan_status woal_remove_card(void *card) flush_workqueue(handle->evt_workqueue); if (handle->rx_workqueue) flush_workqueue(handle->rx_workqueue); + if (handle->tx_workqueue) + flush_workqueue(handle->tx_workqueue); if (moal_extflg_isset(handle, EXT_NAPI)) { napi_disable(&handle->napi_rx); @@ -8741,6 +8859,15 @@ mlan_status woal_remove_card(void *card) #endif #endif #endif + if (handle->tp_acnt.on) { + handle->tp_acnt.on = 0; + handle->tp_acnt.drop_point = 0; + if (handle->is_tp_acnt_timer_set) { + woal_cancel_timer(&handle->tp_acnt.timer); + handle->is_tp_acnt_timer_set = MFALSE; + } + } + /* Remove interface */ for (i = 0; i < MIN(MLAN_MAX_BSS_NUM, handle->priv_num); i++) woal_remove_interface(handle, i); diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_main.h b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_main.h index 8421ae6ec39f4a..5f9a2956b274cd 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_main.h +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_main.h @@ -1392,6 +1392,7 @@ struct _moal_private { #if CFG80211_VERSION_CODE > KERNEL_VERSION(2, 6, 29) atomic_t wmm_tx_pending[4]; #endif + struct sk_buff_head tx_q; /** per interface extra headroom */ t_u16 extra_tx_head_len; /** TX status spin lock */ @@ -1552,6 +1553,7 @@ enum ext_mod_params { EXT_HOST_MLME, #endif #endif + EXT_TX_WORK, EXT_MAX_PARAM, }; @@ -1640,6 +1642,46 @@ typedef struct _moal_mod_para { int dfs53cfg; } moal_mod_para; +void woal_tp_acnt_timer_func(void *context); +void woal_set_tp_state(moal_private *priv); +#define MAX_TP_ACCOUNT_DROP_POINT_NUM 5 +#define RX_DROP_P1 (MAX_TP_ACCOUNT_DROP_POINT_NUM) +#define RX_DROP_P2 (MAX_TP_ACCOUNT_DROP_POINT_NUM + 1) +#define RX_DROP_P3 (MAX_TP_ACCOUNT_DROP_POINT_NUM + 2) +#define RX_DROP_P4 (MAX_TP_ACCOUNT_DROP_POINT_NUM + 3) +#define RX_DROP_P5 (MAX_TP_ACCOUNT_DROP_POINT_NUM + 4) +typedef struct _moal_tp_acnt_t { + /* TX accounting */ + unsigned long tx_packets[MAX_TP_ACCOUNT_DROP_POINT_NUM]; + unsigned long tx_packets_last[MAX_TP_ACCOUNT_DROP_POINT_NUM]; + unsigned long tx_packets_rate[MAX_TP_ACCOUNT_DROP_POINT_NUM]; + unsigned long tx_bytes[MAX_TP_ACCOUNT_DROP_POINT_NUM]; + unsigned long tx_bytes_last[MAX_TP_ACCOUNT_DROP_POINT_NUM]; + unsigned long tx_bytes_rate[MAX_TP_ACCOUNT_DROP_POINT_NUM]; + unsigned long tx_intr_cnt; + unsigned long tx_intr_last; + unsigned long tx_intr_rate; + unsigned long tx_pending; + /** RX accounting */ + unsigned long rx_packets[MAX_TP_ACCOUNT_DROP_POINT_NUM]; + unsigned long rx_packets_last[MAX_TP_ACCOUNT_DROP_POINT_NUM]; + unsigned long rx_packets_rate[MAX_TP_ACCOUNT_DROP_POINT_NUM]; + unsigned long rx_bytes[MAX_TP_ACCOUNT_DROP_POINT_NUM]; + unsigned long rx_bytes_last[MAX_TP_ACCOUNT_DROP_POINT_NUM]; + unsigned long rx_bytes_rate[MAX_TP_ACCOUNT_DROP_POINT_NUM]; + unsigned long rx_intr_cnt; + unsigned long rx_intr_last; + unsigned long rx_intr_rate; + unsigned long rx_pending; + unsigned long rx_paused_cnt; + /* TP account mode 0-disable 1-enable */ + unsigned int on; + /* drop point */ + unsigned int drop_point; + /* periodic timer */ + moal_drv_timer timer; +} moal_tp_acnt_t; + /** Handle data structure for MOAL */ struct _moal_handle { /** MLAN adapter structure */ @@ -1778,6 +1820,10 @@ struct _moal_handle { spinlock_t evt_lock; /** event queue */ struct list_head evt_queue; + /** tx workqueue */ + struct workqueue_struct *tx_workqueue; + /** tx work */ + struct work_struct tx_work; /** remain on channel flag */ t_u8 remain_on_channel; /** bss index for remain on channel */ @@ -1870,6 +1916,8 @@ struct _moal_handle { #endif /** cac period length, valid only when dfs testing is enabled */ long cac_period_jiffies; + /** cac restart*/ + t_u8 cac_restart; /** handle index - for multiple card supports */ t_u8 handle_idx; #if defined(USB) @@ -1987,6 +2035,11 @@ struct _moal_handle { t_u8 rf_test_mode; /** pointer to rf test mode data struct */ struct rf_test_mode_data *rf_data; + /** TP accounting parameters */ + moal_tp_acnt_t tp_acnt; + BOOLEAN is_tp_acnt_timer_set; + + t_u8 request_pm; }; /** diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_pcie.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_pcie.c index 95364ff20ffb84..ee820768d5b03b 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_pcie.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_pcie.c @@ -35,13 +35,15 @@ Change log: #endif #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 70) +#ifdef IMX_SUPPORT #include #endif +#endif + /******************************************************** Local Variables ********************************************************/ #define DRV_NAME "NXP mdriver PCIe" - #if LINUX_VERSION_CODE <= KERNEL_VERSION(5, 6, 0) #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35) static struct pm_qos_request woal_pcie_pm_qos_req; @@ -128,6 +130,37 @@ static moal_if_ops pcie_ops; /******************************************************** Local Functions ********************************************************/ + +void woal_request_pmqos_busfreq_high() +{ +#if LINUX_VERSION_CODE <= KERNEL_VERSION(5, 6, 0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35) + pm_qos_add_request(&woal_pcie_pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 0); +#endif +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 70) +#ifdef IMX_SUPPORT + request_bus_freq(BUS_FREQ_HIGH); +#endif +#endif +} + +void woal_release_pmqos_busfreq_high() +{ +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 70) +#ifdef IMX_SUPPORT + release_bus_freq(BUS_FREQ_HIGH); +#endif +#endif + +#if LINUX_VERSION_CODE <= KERNEL_VERSION(5, 6, 0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35) + pm_qos_remove_request(&woal_pcie_pm_qos_req); +#endif +#endif +} + static mlan_status woal_pcie_preinit(struct pci_dev *pdev); /** @brief This function updates the card types @@ -572,6 +605,8 @@ static int woal_pcie_suspend(struct pci_dev *pdev, pm_message_t state) flush_workqueue(handle->evt_workqueue); if (handle->rx_workqueue) flush_workqueue(handle->rx_workqueue); + if (handle->tx_workqueue) + flush_workqueue(handle->tx_workqueue); pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); pci_save_state(pdev); pci_set_power_state(pdev, pci_choose_state(pdev, state)); @@ -1348,23 +1383,9 @@ mlan_status woal_pcie_bus_register(void) mlan_status ret = MLAN_STATUS_SUCCESS; ENTER(); -#if LINUX_VERSION_CODE <= KERNEL_VERSION(5, 6, 0) -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35) - pm_qos_add_request(&woal_pcie_pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 0); -#endif -#endif - -#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 70) - request_bus_freq(BUS_FREQ_HIGH); -#endif /* API registers the NXP PCIE driver */ if (pci_register_driver(&wlan_pcie)) { PRINTM(MFATAL, "PCIE Driver Registration Failed \n"); -#if LINUX_VERSION_CODE <= KERNEL_VERSION(5, 6, 0) -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35) - pm_qos_remove_request(&woal_pcie_pm_qos_req); -#endif -#endif ret = MLAN_STATUS_FAILURE; } @@ -1381,16 +1402,8 @@ void woal_pcie_bus_unregister(void) { ENTER(); -#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 70) - release_bus_freq(BUS_FREQ_HIGH); -#endif /* PCIE Driver Unregistration */ pci_unregister_driver(&wlan_pcie); -#if LINUX_VERSION_CODE <= KERNEL_VERSION(5, 6, 0) -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35) - pm_qos_remove_request(&woal_pcie_pm_qos_req); -#endif -#endif LEAVE(); } diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_pcie.h b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_pcie.h index ae22f4d0134123..1f3fd7196b8384 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_pcie.h +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_pcie.h @@ -139,4 +139,10 @@ typedef struct _pcie_service_card { mlan_status woal_pcie_bus_register(void); /** Unregister from bus driver function */ void woal_pcie_bus_unregister(void); + +/* pmqos busfreq request handler*/ +void woal_request_pmqos_busfreq_high(void); +/* pmqos busfreq release handler*/ +void woal_release_pmqos_busfreq_high(void); + #endif /* _MOAL_PCIE_H_ */ diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_proc.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_proc.c index 1d1898c32b05b4..d60ae7f64b4d5a 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_proc.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_proc.c @@ -270,6 +270,56 @@ static int woal_info_proc_read(struct seq_file *sfp, void *data) ustats.rsna_4way_hshk_failures); } #endif /* UAP_SUPPORT */ + seq_printf(sfp, "=== tp_acnt.on:%d drop_point:%d ===\n", + handle->tp_acnt.on, handle->tp_acnt.drop_point); + seq_printf(sfp, "====Tx accounting====\n"); + for (i = 0; i < MAX_TP_ACCOUNT_DROP_POINT_NUM; i++) { + seq_printf(sfp, "[%d] Tx packets : %lu\n", i, + handle->tp_acnt.tx_packets[i]); + seq_printf(sfp, "[%d] Tx packets last: %lu\n", i, + handle->tp_acnt.tx_packets_last[i]); + seq_printf(sfp, "[%d] Tx packets rate: %lu\n", i, + handle->tp_acnt.tx_packets_rate[i]); + seq_printf(sfp, "[%d] Tx bytes : %lu\n", i, + handle->tp_acnt.tx_bytes[i]); + seq_printf(sfp, "[%d] Tx bytes last : %lu\n", i, + handle->tp_acnt.tx_bytes_last[i]); + seq_printf(sfp, "[%d] Tx bytes rate : %luMbps\n", i, + handle->tp_acnt.tx_bytes_rate[i] * 8 / 1024 / 1024); + } + seq_printf(sfp, "Tx intr cnt : %lu\n", + handle->tp_acnt.tx_intr_cnt); + seq_printf(sfp, "Tx intr last : %lu\n", + handle->tp_acnt.tx_intr_last); + seq_printf(sfp, "Tx intr rate : %lu\n", + handle->tp_acnt.tx_intr_rate); + seq_printf(sfp, "Tx pending : %lu\n", + handle->tp_acnt.tx_pending); + seq_printf(sfp, "====Rx accounting====\n"); + for (i = 0; i < MAX_TP_ACCOUNT_DROP_POINT_NUM; i++) { + seq_printf(sfp, "[%d] Rx packets : %lu\n", i, + handle->tp_acnt.rx_packets[i]); + seq_printf(sfp, "[%d] Rx packets last: %lu\n", i, + handle->tp_acnt.rx_packets_last[i]); + seq_printf(sfp, "[%d] Rx packets rate: %lu\n", i, + handle->tp_acnt.rx_packets_rate[i]); + seq_printf(sfp, "[%d] Rx bytes : %lu\n", i, + handle->tp_acnt.rx_bytes[i]); + seq_printf(sfp, "[%d] Rx bytes last : %lu\n", i, + handle->tp_acnt.rx_bytes_last[i]); + seq_printf(sfp, "[%d] Rx bytes rate : %luMbps\n", i, + handle->tp_acnt.rx_bytes_rate[i] * 8 / 1024 / 1024); + } + seq_printf(sfp, "Rx intr cnt : %lu\n", + handle->tp_acnt.rx_intr_cnt); + seq_printf(sfp, "Rx intr last : %lu\n", + handle->tp_acnt.rx_intr_last); + seq_printf(sfp, "Rx intr rate : %lu\n", + handle->tp_acnt.rx_intr_rate); + seq_printf(sfp, "Rx pending : %lu\n", + handle->tp_acnt.rx_pending); + seq_printf(sfp, "Rx pause : %lu\n", + handle->tp_acnt.rx_paused_cnt); exit: LEAVE(); MODULE_PUT; @@ -482,6 +532,33 @@ static ssize_t woal_config_write(struct file *f, const char __user *buf, PRINTM(MMSG, "Request fw_reload=%d\n", config_data); woal_request_fw_reload(handle, config_data); } + if (!strncmp(databuf, "drop_point=", strlen("drop_point="))) { + line += strlen("drop_point") + 1; + config_data = (t_u32)woal_string_to_number(line); + if (config_data) { + handle->tp_acnt.on = 1; + handle->tp_acnt.drop_point = config_data; + if (handle->is_tp_acnt_timer_set == MFALSE) { + woal_initialize_timer(&handle->tp_acnt.timer, + woal_tp_acnt_timer_func, + handle); + handle->is_tp_acnt_timer_set = MTRUE; + woal_mod_timer(&handle->tp_acnt.timer, 1000); + } + } else { + if (handle->is_tp_acnt_timer_set) { + woal_cancel_timer(&handle->tp_acnt.timer); + handle->is_tp_acnt_timer_set = MFALSE; + } + memset((void *)&handle->tp_acnt, 0, + sizeof(moal_tp_acnt_t)); + } + priv = woal_get_priv(handle, MLAN_BSS_ROLE_ANY); + if (priv) + woal_set_tp_state(priv); + PRINTM(MMSG, "on=%d drop_point=%d\n", handle->tp_acnt.on, + handle->tp_acnt.drop_point); + } if (!strncmp(databuf, "rf_test_mode", strlen("rf_test_mode"))) { line += strlen("rf_test_mode") + 1; config_data = (t_u32)woal_string_to_number(line); diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_shim.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_shim.c index 2effd85a423830..ff3b593e9c1c33 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_shim.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_shim.c @@ -614,6 +614,68 @@ mlan_status moal_spin_lock(t_void *pmoal_handle, t_void *plock) } } +/** + * @brief This function collects TP statistics. + * + * @param pmoal_handle Pointer to the MOAL context + * @param buf pointer to the buffer of a packet + * @param drop_point Drop pointer user set + * + * @return N/A + */ +void moal_tp_accounting(t_void *pmoal_handle, void *buf, t_u32 drop_point) +{ + struct sk_buff *skb = NULL; + moal_handle *handle = (moal_handle *)pmoal_handle; + pmlan_buffer pmbuf = (pmlan_buffer)buf; + + if (drop_point < MAX_TP_ACCOUNT_DROP_POINT_NUM) { + if (drop_point == 4) { + handle->tp_acnt.tx_bytes[drop_point] += pmbuf->data_len; + } else { + skb = (struct sk_buff *)buf; + handle->tp_acnt.tx_bytes[drop_point] += skb->len; + } + handle->tp_acnt.tx_packets[drop_point]++; + } else if (drop_point <= RX_DROP_P5) { + t_u16 rx_len = 0; + if (drop_point == RX_DROP_P1 || drop_point == RX_DROP_P2) + rx_len = pmbuf->data_len - + *((t_u16 *)(pmbuf->pbuf + pmbuf->data_offset) + + 2); // remove rx_pkt_offset + else if (drop_point == RX_DROP_P3) // aggr pkt + rx_len = pmbuf->data_len; + else if (drop_point == RX_DROP_P4) { // before to kernel + skb = (struct sk_buff *)buf; + rx_len = skb->len; + } + handle->tp_acnt + .rx_bytes[drop_point - MAX_TP_ACCOUNT_DROP_POINT_NUM] += + rx_len; + handle->tp_acnt.rx_packets[drop_point - + MAX_TP_ACCOUNT_DROP_POINT_NUM]++; + } +} + +void moal_tp_accounting_rx_param(t_void *pmoal_handle, unsigned int type, + unsigned int rsvd1) +{ + moal_handle *phandle = (moal_handle *)pmoal_handle; + switch (type) { + case 0: // Rx interrupt + phandle->tp_acnt.rx_intr_cnt++; + break; + case 1: // rx_pkts_queued + phandle->tp_acnt.rx_pending = rsvd1; + break; + case 2: // paused + phandle->tp_acnt.rx_paused_cnt++; + break; + default: + break; + } +} + /** * @brief Request a spin_unlock * @@ -1357,8 +1419,13 @@ mlan_status moal_recv_packet(t_void *pmoal_handle, pmlan_buffer pmbuf) sizeof(dot11_rxcontrol), sizeof(dot11_rxcontrol)); } - - if (in_interrupt()) + // rx_trace 8 + if (priv->phandle->tp_acnt.on) + moal_tp_accounting(handle, skb, RX_DROP_P4); + if (priv->phandle->tp_acnt.drop_point == RX_DROP_P4) { + status = MLAN_STATUS_PENDING; + dev_kfree_skb(skb); + } else if (in_interrupt()) netif_rx(skb); else { if (atomic_read(&handle->rx_pending) > @@ -1374,6 +1441,56 @@ mlan_status moal_recv_packet(t_void *pmoal_handle, pmlan_buffer pmbuf) return status; } +/** + * @brief This function checks media_connected state for + * BSS types UAP/STA/P2P_GO/GC + * + * @param pmoal_handle Pointer to the MOAL context + * + */ +int woal_check_media_connected(t_void *pmoal_handle) +{ + int i; + moal_handle *pmhandle = (moal_handle *)pmoal_handle; + moal_private *pmpriv = NULL; + for (i = 0; i < pmhandle->priv_num && (pmpriv = pmhandle->priv[i]); + i++) { + if ((pmpriv->media_connected == MTRUE)) { + return MTRUE; + } + } + return MFALSE; +} + +/** + * @brief This function checks connect and disconnect + * events for BSS types UAP/STA/P2P_GO/GC + * + * @param pmoal_handle Pointer to the MOAL context + * + */ +void moal_connection_status_check_pmqos(t_void *pmoal_handle) +{ + moal_handle *pmhandle = (moal_handle *)pmoal_handle; + if ((woal_check_media_connected(pmoal_handle) == MTRUE)) { + if ((pmhandle->request_pm == MFALSE)) { + pmhandle->request_pm = MTRUE; +#ifdef PCIE + if (IS_PCIE(pmhandle->card_type)) + woal_request_pmqos_busfreq_high(); +#endif + } + } else { + if (pmhandle->request_pm == MTRUE) { + pmhandle->request_pm = MFALSE; +#ifdef PCIE + if (IS_PCIE(pmhandle->card_type)) + woal_release_pmqos_busfreq_high(); +#endif + } + } +} + /** * @brief This function handles event receive * @@ -1511,7 +1628,7 @@ mlan_status moal_recv_event(t_void *pmoal_handle, pmlan_event pmevent) if (!netif_carrier_ok(priv->netdev)) netif_carrier_on(priv->netdev); woal_wake_queue(priv->netdev); - + moal_connection_status_check_pmqos(pmoal_handle); break; case MLAN_EVENT_ID_DRV_ASSOC_SUCC_LOGGER: @@ -1680,6 +1797,7 @@ mlan_status moal_recv_event(t_void *pmoal_handle, pmlan_event pmevent) priv->rate_index = AUTO_RATE; } #endif /* REASSOCIATION */ + moal_connection_status_check_pmqos(pmoal_handle); break; case MLAN_EVENT_ID_FW_MIC_ERR_UNI: @@ -2384,11 +2502,13 @@ mlan_status moal_recv_event(t_void *pmoal_handle, pmlan_event pmevent) woal_wake_queue(priv->netdev); woal_broadcast_event(priv, pmevent->event_buf, pmevent->event_len); + moal_connection_status_check_pmqos(pmoal_handle); break; case MLAN_EVENT_ID_UAP_FW_BSS_IDLE: priv->media_connected = MFALSE; woal_broadcast_event(priv, pmevent->event_buf, pmevent->event_len); + moal_connection_status_check_pmqos(pmoal_handle); break; case MLAN_EVENT_ID_UAP_FW_MIC_COUNTERMEASURES: { t_u16 status = 0; diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_shim.h b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_shim.h index e692a083095a47..ddcf9c075c8e7f 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_shim.h +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_shim.h @@ -116,5 +116,7 @@ mlan_status moal_free_timer(t_void *pmoal_handle, t_void *ptimer); mlan_status moal_start_timer(t_void *pmoal_handle, t_void *ptimer, t_u8 periodic, t_u32 msec); mlan_status moal_stop_timer(t_void *pmoal_handle, t_void *ptimer); - +void moal_tp_accounting(t_void *pmoal_handle, void *buf, t_u32 drop_point); +void moal_tp_accounting_rx_param(t_void *pmoal_handle, unsigned int type, + unsigned int rsvd1); #endif /*_MOAL_H */ diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_uap.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_uap.c index a1d30c32adcd2f..34e66cf8321a6d 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_uap.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_uap.c @@ -1009,6 +1009,8 @@ static int woal_uap_dfs_testing(struct net_device *dev, struct ifreq *req) param.no_chan_change; cfg11h->param.dfs_testing.usr_fixed_new_chan = param.fixed_new_chan; + cfg11h->param.dfs_testing.usr_cac_restart = param.cac_restart; + priv->phandle->cac_restart = param.cac_restart; priv->phandle->cac_period_jiffies = param.usr_cac_period * HZ / 1000; priv->user_cac_period_msec = @@ -1029,6 +1031,7 @@ static int woal_uap_dfs_testing(struct net_device *dev, struct ifreq *req) cfg11h->param.dfs_testing.usr_no_chan_change; param.fixed_new_chan = cfg11h->param.dfs_testing.usr_fixed_new_chan; + param.cac_restart = cfg11h->param.dfs_testing.usr_cac_restart; } /* Copy to user */ if (copy_to_user(req->ifr_data, ¶m, sizeof(param))) { diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_uap.h b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_uap.h index d8182c1561b33b..b60dfefeed02df 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_uap.h +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_uap.h @@ -495,6 +495,8 @@ typedef struct _dfs_testing_param { t_u8 no_chan_change; /** fixed channel to change to on radar */ t_u8 fixed_new_chan; + /** CAC restart */ + t_u8 cac_restart; } dfs_testing_para; /** Channel switch count config */ diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 3bcea629748809..9ade93c3868b15 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -46,6 +46,7 @@ #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9) #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10) #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11) +#define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12) #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8) #define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000 #define IMX8_HSIO_PCIEB_BASE_ADDR 0x5f010000 @@ -141,8 +142,10 @@ struct imx6_pcie { u32 hsio_cfg; u32 ext_osc; u32 local_addr; + u32 l1ss_clkreq; int link_gen; struct regulator *vpcie; + struct regulator *vph; void __iomem *phy_base; void __iomem *hsmix_base; @@ -1595,6 +1598,17 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) imx6_pcie_grp_offset(imx6_pcie), IMX8MQ_GPR_PCIE_REF_USE_PAD, IMX8MQ_GPR_PCIE_REF_USE_PAD); + /* + * Regarding to the datasheet, the PCIE_VPH is suggested + * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the + * VREG_BYPASS should be cleared to zero. + */ + if (imx6_pcie->vph && + regulator_get_voltage(imx6_pcie->vph) > 3000000) + regmap_update_bits(imx6_pcie->iomuxc_gpr, + imx6_pcie_grp_offset(imx6_pcie), + IMX8MQ_GPR_PCIE_VREG_BYPASS, + 0); break; case IMX8MP: case IMX8MP_EP: @@ -1888,6 +1902,8 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) regulator_disable(imx6_pcie->vpcie); if (imx6_pcie->epdev_on != NULL) regulator_disable(imx6_pcie->epdev_on); + if (gpio_is_valid(imx6_pcie->dis_gpio)) + gpio_set_value_cansleep(imx6_pcie->dis_gpio, 0); } return ret; @@ -1915,8 +1931,6 @@ static int imx6_pcie_host_init(struct pcie_port *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); - if (gpio_is_valid(imx6_pcie->dis_gpio)) - gpio_set_value_cansleep(imx6_pcie->dis_gpio, 1); dw_pcie_setup_rc(pp); pci_imx_set_msi_en(pp); if (imx6_pcie_establish_link(imx6_pcie)) @@ -2202,6 +2216,26 @@ static struct attribute_group imx_pcie_attrgroup = { .attrs = imx_pcie_rc_attrs, }; +static void imx6_pcie_clkreq_enable(struct imx6_pcie *imx6_pcie) +{ + /* + * If the L1SS is supported, disable the over ride after link up. + * Let the the CLK_REQ# controlled by HW L1SS automatically. + */ + switch (imx6_pcie->drvdata->variant) { + case IMX8MQ: + case IMX8MM: + case IMX8MP: + regmap_update_bits(imx6_pcie->iomuxc_gpr, + imx6_pcie_grp_offset(imx6_pcie), + IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, + 0); + break; + default: + break; + }; +} + #ifdef CONFIG_PM_SLEEP static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) { @@ -2332,6 +2366,8 @@ static int imx6_pcie_resume_noirq(struct device *dev) ret = imx6_pcie_establish_link(imx6_pcie); if (ret < 0) dev_info(dev, "pcie link is down after resume.\n"); + if (imx6_pcie->l1ss_clkreq) + imx6_pcie_clkreq_enable(imx6_pcie); } return 0; @@ -2354,7 +2390,7 @@ static int imx6_pcie_probe(struct platform_device *pdev) void __iomem *iomem; struct regmap_config regconfig = imx6_pcie_regconfig; int ret; - u32 reg, val; + u32 val; imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL); if (!imx6_pcie) @@ -2423,6 +2459,10 @@ static int imx6_pcie_probe(struct platform_device *pdev) imx6_pcie->ext_osc = 0; if (of_property_read_u32(node, "local-addr", &imx6_pcie->local_addr)) imx6_pcie->local_addr = 0; + if (of_property_read_bool(node, "l1ss-disabled")) + imx6_pcie->l1ss_clkreq = 0; + else + imx6_pcie->l1ss_clkreq = 1; /* Fetch GPIOs */ imx6_pcie->clkreq_gpio = of_get_named_gpio(node, "clkreq-gpio", 0); @@ -2658,6 +2698,13 @@ static int imx6_pcie_probe(struct platform_device *pdev) imx6_pcie->vpcie = NULL; } + imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph"); + if (IS_ERR(imx6_pcie->vph)) { + if (PTR_ERR(imx6_pcie->vph) != -ENODEV) + return PTR_ERR(imx6_pcie->vph); + imx6_pcie->vph = NULL; + } + platform_set_drvdata(pdev, imx6_pcie); ret = imx6_pcie_attach_pd(dev); @@ -2669,6 +2716,8 @@ static int imx6_pcie_probe(struct platform_device *pdev) dev_err(dev, "failed to enable the epdev_on regulator\n"); goto err_ret; } + if (gpio_is_valid(imx6_pcie->dis_gpio)) + gpio_set_value_cansleep(imx6_pcie->dis_gpio, 1); imx6_pcie_assert_core_reset(imx6_pcie); imx6_pcie_init_phy(imx6_pcie); @@ -2699,45 +2748,6 @@ static int imx6_pcie_probe(struct platform_device *pdev) } pci_imx_set_msi_en(&imx6_pcie->pci->pp); - /* - * If the L1SS is enabled, disable the over ride after link up. - * Let the the CLK_REQ# controlled by HW L1SS automatically. - */ - ret = imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_L1SS; - if (IS_ENABLED(CONFIG_PCIEASPM_POWER_SUPERSAVE) && (ret > 0)) { - switch (imx6_pcie->drvdata->variant) { - case IMX8MQ: - case IMX8MM: - case IMX8MP: - case IMX8MQ_EP: - case IMX8MM_EP: - case IMX8MP_EP: - regmap_update_bits(imx6_pcie->iomuxc_gpr, - imx6_pcie_grp_offset(imx6_pcie), - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, - 0); - break; - case IMX8QXP: - case IMX8QXP_EP: - regmap_update_bits(imx6_pcie->iomuxc_gpr, - IMX8QM_CSR_MISC_OFFSET, - IMX8QM_MISC_CLKREQ_OVERRIDE_EN_1, - 0); - break; - case IMX8QM: - case IMX8QM_EP: - if (imx6_pcie->controller_id) - reg = IMX8QM_MISC_CLKREQ_OVERRIDE_EN_1; - else - reg = IMX8QM_MISC_CLKREQ_OVERRIDE_EN_0; - regmap_update_bits(imx6_pcie->iomuxc_gpr, - IMX8QM_CSR_MISC_OFFSET, - reg, 0); - break; - default: - break; - }; - } break; case DW_PCIE_EP_TYPE: if (!IS_ENABLED(CONFIG_PCI_IMX_EP)) @@ -2932,6 +2942,58 @@ static void imx6_pcie_quirk(struct pci_dev *dev) DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, 0xabcd, PCI_CLASS_BRIDGE_PCI, 8, imx6_pcie_quirk); +static void imx6_pcie_l1ss_quirk(struct pci_dev *dev) +{ + u32 reg, rc_l1sub, ep_l1sub, header; + int ttl, ret; + int pos = PCI_CFG_SPACE_SIZE; + struct pci_bus *bus = dev->bus; + struct pcie_port *pp = bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); + + /* Return directly, if the L1SS is not supported by RC */ + if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_L1SS)) + return; + + /* Make sure the L1SS is not force disabled. */ + if (imx6_pcie->l1ss_clkreq == 0) + return; + + reg = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); + rc_l1sub = dw_pcie_readl_dbi(pci, reg + PCI_L1SS_CAP); + + /* minimum 8 bytes per capability */ + ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; + ret = dw_pcie_read(pp->va_cfg0_base + pos, 4, &header); + /* + * If we have no capabilities, this is indicated by cap ID, + * cap version and next pointer all being 0. + */ + if (header == 0) + return; + + while (ttl-- > 0) { + if (PCI_EXT_CAP_ID(header) == PCI_EXT_CAP_ID_L1SS && pos != 0) + break; + + pos = PCI_EXT_CAP_NEXT(header); + if (pos < PCI_CFG_SPACE_SIZE) + break; + + ret = dw_pcie_read(pp->va_cfg0_base + pos, 4, &header); + } + ret = dw_pcie_read(pp->va_cfg0_base + pos + PCI_L1SS_CAP, 4, &ep_l1sub); + + if ((rc_l1sub && ep_l1sub) && PCI_L1SS_CAP_L1_PM_SS) { + imx6_pcie->l1ss_clkreq = 1; + imx6_pcie_clkreq_enable(imx6_pcie); + } else { + imx6_pcie->l1ss_clkreq = 0; + } +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SYNOPSYS, 0xabcd, imx6_pcie_l1ss_quirk); + static int __init imx6_pcie_init(void) { #ifdef CONFIG_ARM diff --git a/drivers/phy/freescale/phy-fsl-imx8-pcie.c b/drivers/phy/freescale/phy-fsl-imx8-pcie.c index 7cabfdbeba4a0c..2b2e8ec532530e 100644 --- a/drivers/phy/freescale/phy-fsl-imx8-pcie.c +++ b/drivers/phy/freescale/phy-fsl-imx8-pcie.c @@ -62,6 +62,7 @@ #define IMX8MP_PCIE_PHY_TRSV_REG206 0x738 #define LN0_TG_RX_SIGVAL_LBF_DELAY 0x4 +static int imx8_pcie_phy_tuned; struct imx8_pcie_phy { struct phy *phy; struct clk *clk; @@ -135,34 +136,36 @@ static int imx8_pcie_phy_cal(struct phy *phy) * Fine tune the parameters of the PHY, let PCIe link up to GEN3 * between two EVK boards in the EP/RC validation system. */ - writel(LN0_OVRD_TX_DRV_LVL, - imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG001); - writel(LN0_OVRD_TX_DRV_PST_LVL_G1, - imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG005); - writel(LN0_OVRD_TX_DRV_PST_LVL_G2, - imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG006); - writel(LN0_OVRD_TX_DRV_PST_LVL_G3, - imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG007); - writel(LN0_OVRD_TX_DRV_PRE_LVL_G1, - imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG009); - writel(LN0_OVRD_RX_CTLE_RS1_G1, - imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG059); - writel(LN0_OVRD_RX_CTLE_RS1_G2_G3, - imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG060); - writel(LN0_ANA_RX_CTLE_IBLEED, - imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG069); - writel(LN0_OVRD_RX_RTERM_VCM_EN, - imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG107); - writel(LN0_ANA_OVRD_RX_SQHS_DIFN_OC, - imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG109); - writel(LN0_ANA_OVRD_RX_SQHS_DIFP_OC, - imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG110); - writel(LN0_RX_CDR_FBB_FINE_G1_G2, - imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG158); - writel(LN0_RX_CDR_FBB_FINE_G3_G4, - imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG159); - writel(LN0_TG_RX_SIGVAL_LBF_DELAY, - imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG206); + if (imx8_pcie_phy_tuned) { + writel(LN0_OVRD_TX_DRV_LVL, + imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG001); + writel(LN0_OVRD_TX_DRV_PST_LVL_G1, + imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG005); + writel(LN0_OVRD_TX_DRV_PST_LVL_G2, + imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG006); + writel(LN0_OVRD_TX_DRV_PST_LVL_G3, + imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG007); + writel(LN0_OVRD_TX_DRV_PRE_LVL_G1, + imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG009); + writel(LN0_OVRD_RX_CTLE_RS1_G1, + imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG059); + writel(LN0_OVRD_RX_CTLE_RS1_G2_G3, + imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG060); + writel(LN0_ANA_RX_CTLE_IBLEED, + imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG069); + writel(LN0_OVRD_RX_RTERM_VCM_EN, + imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG107); + writel(LN0_ANA_OVRD_RX_SQHS_DIFN_OC, + imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG109); + writel(LN0_ANA_OVRD_RX_SQHS_DIFP_OC, + imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG110); + writel(LN0_RX_CDR_FBB_FINE_G1_G2, + imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG158); + writel(LN0_RX_CDR_FBB_FINE_G3_G4, + imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG159); + writel(LN0_TG_RX_SIGVAL_LBF_DELAY, + imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG206); + } writel(PLL_ANA_LPF_R_SEL_FINE_0_4, imx8_phy->base + IMX8MP_PCIE_PHY_CMN_REG020); @@ -198,6 +201,17 @@ static struct phy_ops imx8_pcie_phy_ops = { .owner = THIS_MODULE, }; +static int __init imx8_pcie_phy_fine_tune(char *str) +{ + if (!strcmp(str, "yes")) { + pr_info("i.MX PCIe PHY is fine tuned in EP/RC SYS.\n"); + imx8_pcie_phy_tuned = 1; + } + return 1; +} + +__setup("pcie_phy_tuned=", imx8_pcie_phy_fine_tune); + static int imx8_pcie_phy_probe(struct platform_device *pdev) { u32 val = 0; diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c index d58e3329a91a46..5947cba737f88c 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -31,8 +31,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { { 22250000, { 0x00, 0xD1, 0x4B, 0xF1, 0x89, 0x88, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x00, 0x15, 0x25, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -40,8 +40,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 23750000, { 0x00, 0xD1, 0x50, 0xF1, 0x86, 0x85, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x00, 0x03, 0x25, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -49,8 +49,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 24000000, { 0x00, 0xD1, 0x50, 0xF0, 0x00, 0x00, 0x80, 0x00, 0x4F, 0x30, 0x33, 0x65, 0x00, 0x01, 0x25, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -58,8 +58,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 24024000, { 0x00, 0xD1, 0x50, 0xF1, 0x99, 0x02, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x00, 0x00, 0x25, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -67,8 +67,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 25175000, { 0x00, 0xD1, 0x54, 0xFC, 0xCC, 0x91, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x00, 0xF5, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -76,8 +76,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 25200000, { 0x00, 0xD1, 0x54, 0xF0, 0x00, 0x00, 0x80, 0x00, 0x4F, 0x30, 0x33, 0x65, 0x00, 0xF4, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -85,8 +85,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 26750000, { 0x00, 0xD1, 0x5A, 0xF2, 0x89, 0x88, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x00, 0xE6, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -94,8 +94,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 27000000, { 0x00, 0xD1, 0x5A, 0xF0, 0x00, 0x00, 0x80, 0x00, 0x4F, 0x30, 0x33, 0x65, 0x00, 0xE4, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -103,8 +103,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 27027000, { 0x00, 0xD1, 0x5A, 0xF2, 0xFD, 0x0C, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x00, 0xE4, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -112,8 +112,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 29500000, { 0x00, 0xD1, 0x62, 0xF4, 0x95, 0x08, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x00, 0xD1, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -121,8 +121,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 30750000, { 0x00, 0xD1, 0x66, 0xF4, 0x82, 0x01, 0x88, 0x45, 0x4F, 0x30, 0x33, 0x65, 0x00, 0xC8, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -130,8 +130,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 30888000, { 0x00, 0xD1, 0x66, 0xF4, 0x99, 0x18, 0x88, 0x45, 0x4F, 0x30, 0x33, 0x65, 0x00, 0xC7, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -139,8 +139,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 33750000, { 0x00, 0xD1, 0x70, 0xF4, 0x82, 0x01, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x00, 0xB7, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -148,8 +148,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 35000000, { 0x00, 0xD1, 0x58, 0xB8, 0x8B, 0x88, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x00, 0xB0, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8B, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8B, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -157,8 +157,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 36000000, { 0x00, 0xD1, 0x5A, 0xB0, 0x00, 0x00, 0x80, 0x00, 0x4F, 0x30, 0x33, 0x65, 0x00, 0xAB, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8B, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8B, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -166,8 +166,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 36036000, { 0x00, 0xD1, 0x5A, 0xB2, 0xFD, 0x0C, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x00, 0xAB, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8B, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8B, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -175,8 +175,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 40000000, { 0x00, 0xD1, 0x64, 0xB0, 0x00, 0x00, 0x80, 0x00, 0x4F, 0x30, 0x33, 0x65, 0x00, 0x9A, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8B, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8B, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -184,8 +184,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 43200000, { 0x00, 0xD1, 0x5A, 0x90, 0x00, 0x00, 0x80, 0x00, 0x4F, 0x30, 0x33, 0x65, 0x00, 0x8F, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x89, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x89, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -193,8 +193,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 43243200, { 0x00, 0xD1, 0x5A, 0x92, 0xFD, 0x0C, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x00, 0x8F, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x89, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x89, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -202,8 +202,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 44500000, { 0x00, 0xD1, 0x5C, 0x92, 0x98, 0x11, 0x84, 0x41, 0x4F, 0x30, 0x33, 0x65, 0x00, 0x8B, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x89, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x89, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -211,8 +211,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 47000000, { 0x00, 0xD1, 0x62, 0x94, 0x95, 0x82, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x00, 0x83, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x89, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x89, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -220,8 +220,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 47500000, { 0x00, 0xD1, 0x63, 0x96, 0xA1, 0x82, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x00, 0x82, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x89, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x89, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -229,8 +229,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 50349650, { 0x00, 0xD1, 0x54, 0x7C, 0xC3, 0x8F, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x10, 0xF5, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x87, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x87, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -238,8 +238,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 50400000, { 0x00, 0xD1, 0x54, 0x70, 0x00, 0x00, 0x80, 0x00, 0x4F, 0x30, 0x33, 0x65, 0x10, 0xF4, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x87, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x87, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -247,8 +247,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 53250000, { 0x00, 0xD1, 0x58, 0x72, 0x84, 0x03, 0x82, 0x41, 0x4F, 0x30, 0x33, 0x65, 0x10, 0xE7, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x87, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x87, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -256,8 +256,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 53500000, { 0x00, 0xD1, 0x5A, 0x72, 0x89, 0x88, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x10, 0xE6, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x87, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x87, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -265,8 +265,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 54000000, { 0x00, 0xD1, 0x5A, 0x70, 0x00, 0x00, 0x80, 0x00, 0x4F, 0x30, 0x33, 0x65, 0x10, 0xE4, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x87, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x87, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -274,8 +274,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 54054000, { 0x00, 0xD1, 0x5A, 0x72, 0xFD, 0x0C, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x10, 0xE4, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x87, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x87, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -283,8 +283,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 59000000, { 0x00, 0xD1, 0x62, 0x74, 0x95, 0x08, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x10, 0xD1, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x87, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x87, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -292,8 +292,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 59340659, { 0x00, 0xD1, 0x62, 0x74, 0xDB, 0x52, 0x88, 0x47, 0x4F, 0x30, 0x33, 0x65, 0x10, 0xD0, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x87, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x87, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -301,8 +301,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 59400000, { 0x00, 0xD1, 0x63, 0x70, 0x00, 0x00, 0x80, 0x00, 0x4F, 0x30, 0x33, 0x65, 0x10, 0xCF, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x87, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x87, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -310,8 +310,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 61500000, { 0x00, 0xD1, 0x66, 0x74, 0x82, 0x01, 0x88, 0x45, 0x4F, 0x30, 0x33, 0x65, 0x10, 0xC8, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x87, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x87, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -319,8 +319,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 63500000, { 0x00, 0xD1, 0x69, 0x74, 0x89, 0x08, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x10, 0xC2, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x87, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x87, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -328,8 +328,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 67500000, { 0x00, 0xD1, 0x54, 0x52, 0x87, 0x03, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x10, 0xB7, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -337,8 +337,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 70000000, { 0x00, 0xD1, 0x58, 0x58, 0x8B, 0x88, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x10, 0xB0, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -346,8 +346,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 72000000, { 0x00, 0xD1, 0x5A, 0x50, 0x00, 0x00, 0x80, 0x00, 0x4F, 0x30, 0x33, 0x65, 0x10, 0xAB, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -355,8 +355,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 72072000, { 0x00, 0xD1, 0x5A, 0x52, 0xFD, 0x0C, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x10, 0xAB, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -364,8 +364,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 74176000, { 0x00, 0xD1, 0x5D, 0x58, 0xDB, 0xA2, 0x88, 0x41, 0x4F, 0x30, 0x33, 0x65, 0x10, 0xA6, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -373,8 +373,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 74250000, { 0x00, 0xD1, 0x5C, 0x52, 0x90, 0x0D, 0x84, 0x41, 0x4F, 0x30, 0x33, 0x65, 0x10, 0xA6, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -382,8 +382,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 78500000, { 0x00, 0xD1, 0x62, 0x54, 0x87, 0x01, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x10, 0x9D, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -391,8 +391,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 80000000, { 0x00, 0xD1, 0x64, 0x50, 0x00, 0x00, 0x80, 0x00, 0x4F, 0x30, 0x33, 0x65, 0x10, 0x9A, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -400,8 +400,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 82000000, { 0x00, 0xD1, 0x66, 0x54, 0x82, 0x01, 0x88, 0x45, 0x4F, 0x30, 0x33, 0x65, 0x10, 0x96, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -409,8 +409,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 82500000, { 0x00, 0xD1, 0x67, 0x54, 0x88, 0x01, 0x90, 0x49, 0x4F, 0x30, 0x33, 0x65, 0x10, 0x95, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -418,8 +418,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 89000000, { 0x00, 0xD1, 0x70, 0x54, 0x84, 0x83, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x10, 0x8B, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -427,8 +427,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 90000000, { 0x00, 0xD1, 0x70, 0x54, 0x82, 0x01, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x10, 0x89, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -436,8 +436,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 94000000, { 0x00, 0xD1, 0x4E, 0x32, 0xA7, 0x10, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x10, 0x83, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -445,8 +445,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 95000000, { 0x00, 0xD1, 0x50, 0x31, 0x86, 0x85, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x10, 0x82, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -454,8 +454,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 98901099, { 0x00, 0xD1, 0x52, 0x3A, 0xDB, 0x4C, 0x88, 0x47, 0x4F, 0x30, 0x33, 0x65, 0x10, 0x7D, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -463,8 +463,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 99000000, { 0x00, 0xD1, 0x52, 0x32, 0x82, 0x01, 0x88, 0x47, 0x4F, 0x30, 0x33, 0x65, 0x10, 0x7D, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -472,8 +472,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 100699300, { 0x00, 0xD1, 0x54, 0x3C, 0xC3, 0x8F, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x20, 0xF5, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -481,8 +481,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 100800000, { 0x00, 0xD1, 0x54, 0x30, 0x00, 0x00, 0x80, 0x00, 0x4F, 0x30, 0x33, 0x65, 0x20, 0xF4, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -490,8 +490,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 102500000, { 0x00, 0xD1, 0x55, 0x32, 0x8C, 0x05, 0x90, 0x4B, 0x4F, 0x30, 0x33, 0x65, 0x20, 0xF0, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -499,8 +499,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 104750000, { 0x00, 0xD1, 0x57, 0x32, 0x98, 0x07, 0x90, 0x49, 0x4F, 0x30, 0x33, 0x65, 0x20, 0xEB, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -508,8 +508,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 106500000, { 0x00, 0xD1, 0x58, 0x32, 0x84, 0x03, 0x82, 0x41, 0x4F, 0x30, 0x33, 0x65, 0x20, 0xE7, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -517,8 +517,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 107000000, { 0x00, 0xD1, 0x5A, 0x32, 0x89, 0x88, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x20, 0xE6, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -526,8 +526,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 108000000, { 0x00, 0xD1, 0x5A, 0x30, 0x00, 0x00, 0x80, 0x00, 0x4F, 0x30, 0x33, 0x65, 0x20, 0xE4, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -535,8 +535,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 108108000, { 0x00, 0xD1, 0x5A, 0x32, 0xFD, 0x0C, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x20, 0xE4, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -544,8 +544,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 118000000, { 0x00, 0xD1, 0x62, 0x34, 0x95, 0x08, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x20, 0xD1, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -553,8 +553,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 118800000, { 0x00, 0xD1, 0x63, 0x30, 0x00, 0x00, 0x80, 0x00, 0x4F, 0x30, 0x33, 0x65, 0x20, 0xCF, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -562,8 +562,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 123000000, { 0x00, 0xD1, 0x66, 0x34, 0x82, 0x01, 0x88, 0x45, 0x4F, 0x30, 0x33, 0x65, 0x20, 0xC8, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -571,8 +571,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 127000000, { 0x00, 0xD1, 0x69, 0x34, 0x89, 0x08, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x20, 0xC2, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -580,8 +580,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 135000000, { 0x00, 0xD1, 0x70, 0x34, 0x82, 0x01, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x20, 0xB7, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -589,8 +589,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 135580000, { 0x00, 0xD1, 0x71, 0x39, 0xE9, 0x82, 0x9C, 0x5B, 0x4F, 0x30, 0x33, 0x65, 0x20, 0xB6, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -598,8 +598,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 137520000, { 0x00, 0xD1, 0x72, 0x38, 0x99, 0x10, 0x85, 0x41, 0x4F, 0x30, 0x33, 0x65, 0x20, 0xB3, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -607,8 +607,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 138750000, { 0x00, 0xD1, 0x73, 0x35, 0x88, 0x05, 0x90, 0x4D, 0x4F, 0x30, 0x33, 0x65, 0x20, 0xB2, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -616,8 +616,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 140000000, { 0x00, 0xD1, 0x75, 0x36, 0xA7, 0x90, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x20, 0xB0, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -625,8 +625,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 144000000, { 0x00, 0xD1, 0x78, 0x30, 0x00, 0x00, 0x80, 0x00, 0x4F, 0x30, 0x33, 0x65, 0x20, 0xAB, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -634,17 +634,17 @@ const struct phy_config samsung_phy_pll_cfg[] = { 148352000, { 0x00, 0xD1, 0x7B, 0x35, 0xDB, 0x39, 0x90, 0x45, 0x4F, 0x30, 0x33, 0x65, 0x20, 0xA6, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, }, { 148500000, { 0x00, 0xD1, 0x7B, 0x35, 0x84, 0x03, 0x90, 0x45, 0x4F, 0x30, 0x33, 0x65, 0x20, 0xA6, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -652,8 +652,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 154000000, { 0x00, 0xD1, 0x40, 0x18, 0x83, 0x01, 0x00, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x20, 0xA0, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -661,8 +661,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 157000000, { 0x00, 0xD1, 0x41, 0x11, 0xA7, 0x14, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x20, 0x9D, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -670,8 +670,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 160000000, { 0x00, 0xD1, 0x42, 0x12, 0xA1, 0x20, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x20, 0x9A, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -679,8 +679,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 162000000, { 0x00, 0xD1, 0x43, 0x18, 0x8B, 0x08, 0x96, 0x55, 0x4F, 0x30, 0x33, 0x65, 0x20, 0x98, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -688,8 +688,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 164000000, { 0x00, 0xD1, 0x45, 0x11, 0x83, 0x82, 0x90, 0x4B, 0x4F, 0x30, 0x33, 0x65, 0x20, 0x96, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -697,8 +697,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 165000000, { 0x00, 0xD1, 0x45, 0x11, 0x84, 0x81, 0x90, 0x4B, 0x4F, 0x30, 0x33, 0x65, 0x20, 0x95, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -706,8 +706,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 180000000, { 0x00, 0xD1, 0x4B, 0x10, 0x00, 0x00, 0x80, 0x00, 0x4F, 0x30, 0x33, 0x65, 0x20, 0x89, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -715,8 +715,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 185625000, { 0x00, 0xD1, 0x4E, 0x12, 0x9A, 0x95, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x20, 0x85, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -724,8 +724,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 188000000, { 0x00, 0xD1, 0x4E, 0x12, 0xA7, 0x10, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x20, 0x83, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -733,8 +733,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 198000000, { 0x00, 0xD1, 0x52, 0x12, 0x82, 0x01, 0x88, 0x47, 0x4F, 0x30, 0x33, 0x65, 0x20, 0x7D, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -742,8 +742,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 205000000, { 0x00, 0xD1, 0x55, 0x12, 0x8C, 0x05, 0x90, 0x4B, 0x4F, 0x30, 0x33, 0x65, 0x30, 0xF0, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -751,8 +751,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 209500000, { 0x00, 0xD1, 0x57, 0x12, 0x98, 0x07, 0x90, 0x49, 0x4F, 0x30, 0x33, 0x65, 0x30, 0xEB, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -760,8 +760,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 213000000, { 0x00, 0xD1, 0x58, 0x12, 0x84, 0x03, 0x82, 0x41, 0x4F, 0x30, 0x33, 0x65, 0x30, 0xE7, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -769,8 +769,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 216000000, { 0x00, 0xD1, 0x5A, 0x10, 0x00, 0x00, 0x80, 0x00, 0x4F, 0x30, 0x33, 0x65, 0x30, 0xE4, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -778,8 +778,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 216216000, { 0x00, 0xD1, 0x5A, 0x12, 0xFD, 0x0C, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x30, 0xE4, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -787,8 +787,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 237600000, { 0x00, 0xD1, 0x63, 0x10, 0x00, 0x00, 0x80, 0x00, 0x4F, 0x30, 0x33, 0x65, 0x30, 0xCF, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -796,8 +796,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 254000000, { 0x00, 0xD1, 0x69, 0x14, 0x89, 0x08, 0x80, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x30, 0xC2, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -805,8 +805,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 277500000, { 0x00, 0xD1, 0x73, 0x15, 0x88, 0x05, 0x90, 0x4D, 0x4F, 0x30, 0x33, 0x65, 0x30, 0xB2, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -814,8 +814,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 288000000, { 0x00, 0xD1, 0x78, 0x10, 0x00, 0x00, 0x80, 0x00, 0x4F, 0x30, 0x33, 0x65, 0x30, 0xAB, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -823,8 +823,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 297000000, { 0x00, 0xD1, 0x7B, 0x15, 0x84, 0x03, 0x90, 0x45, 0x4F, 0x30, 0x33, 0x65, 0x30, 0xA6, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -832,8 +832,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 165000000, { 0x00, 0xD1, 0x45, 0x11, 0x84, 0x81, 0x90, 0x4B, 0x4F, 0x30, 0x33, 0x65, 0x20, 0x95, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -841,8 +841,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 185625000, { 0x00, 0xD1, 0x4E, 0x12, 0xB4, 0x95, 0x88, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x20, 0x85, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -850,8 +850,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 198000000, { 0x00, 0xD1, 0x52, 0x12, 0x84, 0x01, 0x88, 0x47, 0x4F, 0x30, 0x33, 0x65, 0x20, 0x7D, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -859,8 +859,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 90000000, { 0x00, 0xD1, 0x4B, 0x32, 0x84, 0x00, 0x88, 0x40, 0x4F, 0x30, 0x33, 0x65, 0x10, 0x89, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, @@ -868,8 +868,8 @@ const struct phy_config samsung_phy_pll_cfg[] = { 99000000, { 0x00, 0xD1, 0x52, 0x32, 0x84, 0x01, 0x88, 0x47, 0x4F, 0x30, 0x33, 0x65, 0x10, 0x7D, 0x24, 0x80, - 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x3A, - 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, diff --git a/drivers/remoteproc/imx_rproc.c b/drivers/remoteproc/imx_rproc.c index 3af7227f2c3039..6d913ab149f039 100644 --- a/drivers/remoteproc/imx_rproc.c +++ b/drivers/remoteproc/imx_rproc.c @@ -1134,6 +1134,8 @@ static int imx_rproc_probe(struct platform_device *pdev) spin_lock_init(&priv->mu_lock); + INIT_DELAYED_WORK(&(priv->rproc_work), imx_rproc_vq_work); + ret = imx_rproc_xtr_mbox_init(rproc); if (ret) { if (ret == -EPROBE_DEFER) @@ -1157,8 +1159,6 @@ static int imx_rproc_probe(struct platform_device *pdev) goto err_put_rproc; } - INIT_DELAYED_WORK(&(priv->rproc_work), imx_rproc_vq_work); - ret = imx_rproc_db_channel_init(rproc); if (ret) goto err_put_mbox; diff --git a/drivers/staging/media/imx/imx8-mipi-csi2-sam.c b/drivers/staging/media/imx/imx8-mipi-csi2-sam.c index 4d489677975311..b10abd0d1a046c 100644 --- a/drivers/staging/media/imx/imx8-mipi-csi2-sam.c +++ b/drivers/staging/media/imx/imx8-mipi-csi2-sam.c @@ -1277,7 +1277,7 @@ static int csis_ioc_qcap(struct v4l2_subdev *dev, void *args) { struct csi_state *state = mipi_sd_to_csi_state(dev); struct v4l2_capability *cap = (struct v4l2_capability *)args; - strcpy((char *)cap->driver, "csi_samsung_subdev"); + strcpy((char *)cap->driver, "csi_sam_subdev"); cap->bus_info[0] = state->index; return 0; } diff --git a/drivers/watchdog/imx7ulp_wdt.c b/drivers/watchdog/imx7ulp_wdt.c index 014f497ea0dc7f..b8ac0cb04d2f16 100644 --- a/drivers/watchdog/imx7ulp_wdt.c +++ b/drivers/watchdog/imx7ulp_wdt.c @@ -179,9 +179,13 @@ static int imx7ulp_wdt_init(void __iomem *base, unsigned int timeout) int ret; local_irq_disable(); + + mb(); /* unlock the wdog for reconfiguration */ writel_relaxed(UNLOCK_SEQ0, base + WDOG_CNT); writel_relaxed(UNLOCK_SEQ1, base + WDOG_CNT); + mb(); + ret = imx7ulp_wdt_wait(base, WDOG_CS_ULK); if (ret) goto init_out; diff --git a/include/drm/bridge/cdns-mhdp.h b/include/drm/bridge/cdns-mhdp.h index 6bfd82a3d9a2ce..86314543fbca55 100755 --- a/include/drm/bridge/cdns-mhdp.h +++ b/include/drm/bridge/cdns-mhdp.h @@ -376,6 +376,11 @@ #define DPTX_FORCE_LANES 0x10 #define DPTX_HPD_STATE 0x11 #define DPTX_ADJUST_LT 0x12 +#define DPTX_I2C_READ 0x15 +#define DPTX_I2C_WRITE 0x16 +#define DPTX_GET_LAST_I2C_STATUS 0x17 + + /* HDMI TX opcode */ #define HDMI_TX_READ 0x00 @@ -734,6 +739,12 @@ u32 cdns_mhdp_get_event(struct cdns_mhdp_device *mhdp); int cdns_mhdp_dpcd_write(struct cdns_mhdp_device *mhdp, u32 addr, u8 value); int cdns_mhdp_dpcd_read(struct cdns_mhdp_device *mhdp, u32 addr, u8 *data, u16 len); + +int cdns_mhdp_get_last_i2c_status(struct cdns_mhdp_device *mhdp, u8 *resp); +int cdns_mhdp_i2c_write(struct cdns_mhdp_device *mhdp, u8 addr, + u8 *value, u8 mot, u16 len, u16 *respLength); +int cdns_mhdp_i2c_read(struct cdns_mhdp_device *mhdp, u8 addr, u8 *data, + u16 len, u8 mot, u16 *respLength); int cdns_mhdp_get_edid_block(void *mhdp, u8 *edid, unsigned int block, size_t length); int cdns_mhdp_train_link(struct cdns_mhdp_device *mhdp);