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Merge branch 'main' into main
2 parents aec9120 + a9e1f66 commit 1e05c67

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18 files changed

+180
-116
lines changed

18 files changed

+180
-116
lines changed

‎portable/CCS/ARM_CM3/port.c‎

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -52,8 +52,9 @@
5252
#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
5353
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
5454

55-
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
56-
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
55+
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
56+
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
57+
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
5758

5859
/* Constants required to check the validity of an interrupt priority. */
5960
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
@@ -239,6 +240,14 @@ BaseType_t xPortStartScheduler( void )
239240
/* Use the same mask on the maximum system call priority. */
240241
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
241242

243+
/* Check that the maximum system call priority is nonzero after
244+
* accounting for the number of priority bits supported by the
245+
* hardware. A priority of 0 is invalid because setting the BASEPRI
246+
* register to 0 unmasks all interrupts, and interrupts with priority 0
247+
* cannot be masked using BASEPRI.
248+
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
249+
configASSERT( ucMaxSysCallPriority );
250+
242251
/* Calculate the maximum acceptable priority group value for the number
243252
* of bits read back. */
244253
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;

‎portable/CCS/ARM_CM4F/port.c‎

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -56,8 +56,9 @@
5656
#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
5757
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
5858

59-
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
60-
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
59+
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
60+
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
61+
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
6162

6263
/* Constants required to check the validity of an interrupt priority. */
6364
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
@@ -258,6 +259,14 @@ BaseType_t xPortStartScheduler( void )
258259
/* Use the same mask on the maximum system call priority. */
259260
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
260261

262+
/* Check that the maximum system call priority is nonzero after
263+
* accounting for the number of priority bits supported by the
264+
* hardware. A priority of 0 is invalid because setting the BASEPRI
265+
* register to 0 unmasks all interrupts, and interrupts with priority 0
266+
* cannot be masked using BASEPRI.
267+
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
268+
configASSERT( ucMaxSysCallPriority );
269+
261270
/* Calculate the maximum acceptable priority group value for the number
262271
* of bits read back. */
263272
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;

‎portable/GCC/ARM_CM3/port.c‎

Lines changed: 11 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -34,13 +34,6 @@
3434
#include "FreeRTOS.h"
3535
#include "task.h"
3636

37-
/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
38-
* defined. The value should also ensure backward compatibility.
39-
* FreeRTOS.org versions prior to V4.4.0 did not include this definition. */
40-
#ifndef configKERNEL_INTERRUPT_PRIORITY
41-
#define configKERNEL_INTERRUPT_PRIORITY 255
42-
#endif
43-
4437
/* Constants required to manipulate the core. Registers first... */
4538
#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
4639
#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
@@ -55,8 +48,9 @@
5548
#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
5649
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
5750

58-
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
59-
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
51+
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
52+
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
53+
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
6054

6155
/* Constants required to check the validity of an interrupt priority. */
6256
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
@@ -265,10 +259,6 @@ static void prvPortStartFirstTask( void )
265259
*/
266260
BaseType_t xPortStartScheduler( void )
267261
{
268-
/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
269-
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
270-
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
271-
272262
#if ( configASSERT_DEFINED == 1 )
273263
{
274264
volatile uint32_t ulOriginalPriority;
@@ -293,6 +283,14 @@ BaseType_t xPortStartScheduler( void )
293283
/* Use the same mask on the maximum system call priority. */
294284
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
295285

286+
/* Check that the maximum system call priority is nonzero after
287+
* accounting for the number of priority bits supported by the
288+
* hardware. A priority of 0 is invalid because setting the BASEPRI
289+
* register to 0 unmasks all interrupts, and interrupts with priority 0
290+
* cannot be masked using BASEPRI.
291+
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
292+
configASSERT( ucMaxSysCallPriority );
293+
296294
/* Calculate the maximum acceptable priority group value for the number
297295
* of bits read back. */
298296
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;

‎portable/GCC/ARM_CM3_MPU/port.c‎

Lines changed: 11 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -83,8 +83,9 @@
8383
/* Constants required to access and manipulate the SysTick. */
8484
#define portNVIC_SYSTICK_INT ( 0x00000002UL )
8585
#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
86-
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
87-
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
86+
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
87+
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
88+
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
8889
#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
8990

9091
/* Constants required to set up the initial stack. */
@@ -381,10 +382,6 @@ static void prvRestoreContextOfFirstTask( void )
381382
*/
382383
BaseType_t xPortStartScheduler( void )
383384
{
384-
/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See
385-
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
386-
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
387-
388385
#if ( configASSERT_DEFINED == 1 )
389386
{
390387
volatile uint32_t ulOriginalPriority;
@@ -409,6 +406,14 @@ BaseType_t xPortStartScheduler( void )
409406
/* Use the same mask on the maximum system call priority. */
410407
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
411408

409+
/* Check that the maximum system call priority is nonzero after
410+
* accounting for the number of priority bits supported by the
411+
* hardware. A priority of 0 is invalid because setting the BASEPRI
412+
* register to 0 unmasks all interrupts, and interrupts with priority 0
413+
* cannot be masked using BASEPRI.
414+
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
415+
configASSERT( ucMaxSysCallPriority );
416+
412417
/* Calculate the maximum acceptable priority group value for the number
413418
* of bits read back. */
414419
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;

‎portable/GCC/ARM_CM4F/port.c‎

Lines changed: 11 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -58,8 +58,9 @@
5858
#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
5959
#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
6060

61-
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
62-
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
61+
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
62+
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
63+
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
6364

6465
/* Constants required to check the validity of an interrupt priority. */
6566
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
@@ -295,10 +296,6 @@ static void prvPortStartFirstTask( void )
295296
*/
296297
BaseType_t xPortStartScheduler( void )
297298
{
298-
/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
299-
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
300-
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
301-
302299
/* This port can be used on all revisions of the Cortex-M7 core other than
303300
* the r0p1 parts. r0p1 parts should use the port from the
304301
* /source/portable/GCC/ARM_CM7/r0p1 directory. */
@@ -329,6 +326,14 @@ BaseType_t xPortStartScheduler( void )
329326
/* Use the same mask on the maximum system call priority. */
330327
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
331328

329+
/* Check that the maximum system call priority is nonzero after
330+
* accounting for the number of priority bits supported by the
331+
* hardware. A priority of 0 is invalid because setting the BASEPRI
332+
* register to 0 unmasks all interrupts, and interrupts with priority 0
333+
* cannot be masked using BASEPRI.
334+
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
335+
configASSERT( ucMaxSysCallPriority );
336+
332337
/* Calculate the maximum acceptable priority group value for the number
333338
* of bits read back. */
334339
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;

‎portable/GCC/ARM_CM4_MPU/port.c‎

Lines changed: 11 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -93,8 +93,9 @@
9393
/* Constants required to access and manipulate the SysTick. */
9494
#define portNVIC_SYSTICK_INT ( 0x00000002UL )
9595
#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
96-
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
97-
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
96+
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
97+
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
98+
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
9899
#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
99100

100101
/* Constants required to manipulate the VFP. */
@@ -412,10 +413,6 @@ static void prvRestoreContextOfFirstTask( void )
412413
*/
413414
BaseType_t xPortStartScheduler( void )
414415
{
415-
/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See
416-
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
417-
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
418-
419416
/* Errata 837070 workaround must only be enabled on Cortex-M7 r0p0
420417
* and r0p1 cores. */
421418
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
@@ -452,6 +449,14 @@ BaseType_t xPortStartScheduler( void )
452449
/* Use the same mask on the maximum system call priority. */
453450
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
454451

452+
/* Check that the maximum system call priority is nonzero after
453+
* accounting for the number of priority bits supported by the
454+
* hardware. A priority of 0 is invalid because setting the BASEPRI
455+
* register to 0 unmasks all interrupts, and interrupts with priority 0
456+
* cannot be masked using BASEPRI.
457+
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
458+
configASSERT( ucMaxSysCallPriority );
459+
455460
/* Calculate the maximum acceptable priority group value for the number
456461
* of bits read back. */
457462
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;

‎portable/GCC/ARM_CM7/r0p1/port.c‎

Lines changed: 11 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -52,8 +52,9 @@
5252
#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
5353
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
5454

55-
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
56-
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
55+
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
56+
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
57+
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
5758

5859
/* Constants required to check the validity of an interrupt priority. */
5960
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
@@ -289,10 +290,6 @@ static void prvPortStartFirstTask( void )
289290
*/
290291
BaseType_t xPortStartScheduler( void )
291292
{
292-
/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
293-
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
294-
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
295-
296293
#if ( configASSERT_DEFINED == 1 )
297294
{
298295
volatile uint32_t ulOriginalPriority;
@@ -317,6 +314,14 @@ BaseType_t xPortStartScheduler( void )
317314
/* Use the same mask on the maximum system call priority. */
318315
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
319316

317+
/* Check that the maximum system call priority is nonzero after
318+
* accounting for the number of priority bits supported by the
319+
* hardware. A priority of 0 is invalid because setting the BASEPRI
320+
* register to 0 unmasks all interrupts, and interrupts with priority 0
321+
* cannot be masked using BASEPRI.
322+
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
323+
configASSERT( ucMaxSysCallPriority );
324+
320325
/* Calculate the maximum acceptable priority group value for the number
321326
* of bits read back. */
322327
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;

‎portable/IAR/ARM_CM0/port.c‎

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -56,13 +56,6 @@
5656
/* Constants required to set up the initial stack. */
5757
#define portINITIAL_XPSR ( 0x01000000 )
5858

59-
/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
60-
* defined. The value 255 should also ensure backward compatibility.
61-
* FreeRTOS.org versions prior to V4.3.0 did not include this definition. */
62-
#ifndef configKERNEL_INTERRUPT_PRIORITY
63-
#define configKERNEL_INTERRUPT_PRIORITY 0
64-
#endif
65-
6659
/* Each task maintains its own interrupt status in the critical nesting
6760
* variable. */
6861
static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;

‎portable/IAR/ARM_CM3/port.c‎

Lines changed: 11 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -55,8 +55,9 @@
5555
#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
5656
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
5757

58-
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
59-
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
58+
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
59+
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
60+
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
6061

6162
/* Constants required to check the validity of an interrupt priority. */
6263
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
@@ -86,13 +87,6 @@
8687
* have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
8788
#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
8889

89-
/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
90-
* defined. The value 255 should also ensure backward compatibility.
91-
* FreeRTOS.org versions prior to V4.3.0 did not include this definition. */
92-
#ifndef configKERNEL_INTERRUPT_PRIORITY
93-
#define configKERNEL_INTERRUPT_PRIORITY 255
94-
#endif
95-
9690
/* Let the user override the default SysTick clock rate. If defined by the
9791
* user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
9892
* configuration register. */
@@ -214,10 +208,6 @@ static void prvTaskExitError( void )
214208
*/
215209
BaseType_t xPortStartScheduler( void )
216210
{
217-
/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
218-
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
219-
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
220-
221211
#if ( configASSERT_DEFINED == 1 )
222212
{
223213
volatile uint32_t ulOriginalPriority;
@@ -242,6 +232,14 @@ BaseType_t xPortStartScheduler( void )
242232
/* Use the same mask on the maximum system call priority. */
243233
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
244234

235+
/* Check that the maximum system call priority is nonzero after
236+
* accounting for the number of priority bits supported by the
237+
* hardware. A priority of 0 is invalid because setting the BASEPRI
238+
* register to 0 unmasks all interrupts, and interrupts with priority 0
239+
* cannot be masked using BASEPRI.
240+
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
241+
configASSERT( ucMaxSysCallPriority );
242+
245243
/* Calculate the maximum acceptable priority group value for the number
246244
* of bits read back. */
247245
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;

‎portable/IAR/ARM_CM4F/port.c‎

Lines changed: 11 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -65,8 +65,9 @@
6565
#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
6666
#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
6767

68-
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
69-
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
68+
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
69+
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
70+
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
7071

7172
/* Constants required to check the validity of an interrupt priority. */
7273
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
@@ -239,10 +240,6 @@ static void prvTaskExitError( void )
239240
*/
240241
BaseType_t xPortStartScheduler( void )
241242
{
242-
/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
243-
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
244-
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
245-
246243
/* This port can be used on all revisions of the Cortex-M7 core other than
247244
* the r0p1 parts. r0p1 parts should use the port from the
248245
* /source/portable/GCC/ARM_CM7/r0p1 directory. */
@@ -273,6 +270,14 @@ BaseType_t xPortStartScheduler( void )
273270
/* Use the same mask on the maximum system call priority. */
274271
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
275272

273+
/* Check that the maximum system call priority is nonzero after
274+
* accounting for the number of priority bits supported by the
275+
* hardware. A priority of 0 is invalid because setting the BASEPRI
276+
* register to 0 unmasks all interrupts, and interrupts with priority 0
277+
* cannot be masked using BASEPRI.
278+
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
279+
configASSERT( ucMaxSysCallPriority );
280+
276281
/* Calculate the maximum acceptable priority group value for the number
277282
* of bits read back. */
278283
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;

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