Apio Build

Contents

• Usage
• Description
• Options
• Examples

Usage

apio build [OPTIONS]

Description

Synthesize the bitstream: generates a .bin file from the verilog sources and constaint file

Required package: oss-cad-suite

Options

Flag	Long Flag	Description
-b	--board	Select a specific board
	--fpga	Select a specific FPGA
	--size --type --pack	Select a specific FPGA size, type and pack
-p	--project-dir	Set the target directory for the project.
-v	--verbose	Show the entire output of the command
	--verbose-yosys	Show the yosys output of the command
	--verbose-pnr	Show the pnr output of the command
	--top-module str	Set the top level module (w/o .v ending) for build

Examples

1. Process the ledon example

Before executing the command, these are the files in the current directory:

$ ls
apio.ini  info  ledon_tb.gtkw  ledon_tb.v  ledon.v  pinout.pcf

Build the project:

apio build

It is build for the board specified in the apio.ini file:

These are the new files created. The hardware.bin file contains the bitstream

$ ls
apio.ini      hardware.bin   info           ledon_tb.v  pinout.pcf
hardware.asc  hardware.json  ledon_tb.gtkw  ledon.v

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