Asynchronous serial transmitter unit

Introduction

Asynchronous serial transmitter unit for the Icestick board

Baudrates: 300, 600, 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200
Clock frequency: 12Mhz
Start bits: 1
Data bits: 8
Parity: None
Stop bits: 1
Description language: Verilog
Toolchain: Opensource: Yosys, Arachne-pnr, Icestorm project

Serial packages consist of three parts: the start bit, the 8-bit data and the stop bit

Example of the serial transmission of the K character (ASCII 0x4B: Binary: 01001011)

The serial transmitter is encapsulated in the uart-tx entity

The transmitter unit has 4 inputs and 2 outputs:

Inputs:
- clk: System clock (12MHz in the ICEstick board)
- rstn: Active low. When rstn is 0, the serial unit is reset (synchronous reset)
- start: Start the transmission. When it is a 1, the character from the input data is captured and the transmission begins
- data: 8-bit data to transmit
Outputs:
- tx: Serial output. The data is sent as a serial package. It is connected to the transmission line
- ready: Transmitter status. When ready is 1, the unit is ready to transmit. A new character can be sent. when it is 0, the unit is busy transmitting the previous character.

The step for transmitting a character are the following:

After that, the unit clears the ready signal and start transmitting the character

The implementation of the transmitter is shown in the given block diagram

It consist of the following parts:

Data register (8 bits): For storing the data to be sent
Shift register (10 bits): For storing the serial package and sending its bits one by one. When it is loaded with a new character to transmit (8 bits), the two bits less significant are initialized with the binary value 01 (a start bit and a idle bit). When transmitting, the less significant line is sent to the transmission line and then the register is shift right. A 1 is introduced in the most significant bit