Asynchronous serial receiver unit

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Introduction

Asynchronous serial receiver unit for the Icestick board, synthetized with Opensource Icestorm tools

Features

• Baudrates: 300, 600, 300, 600, 1200, 4800, 9600, 19200, 38400, 115200
• Clock frequency: 12Mhz
• Start bits: 1
• Data bits: 8
• Parity: None
• Stop bits: 1
• Description language: Verilog
• Toolchain: Opensource: Yosys, Arachne-pnr, Icestorm project

Serial packages

Serial packages consist of three parts: the start bit, the 8-bit data and the stop bit

Example of the serial package for the K character (ASCII 0x4B: Binary: 01001011)

UART-RX details

The serial receiver is encapsulated in the uart-rx entity

Ports

The receiver unit has 3 inputs and 2 outputs:

• Inputs:

  • clk: System clock (12MHz in the ICEstick board)
  • rstn: Active low. When rstn is 0, the serial unit is reset (synchronous reset)
  • rx: Serial input. The serial packages are received from this input

• Outputs:

  • data: 8-bit data to transmit
  • rcv: Character received. When a new character is received, a pulse of duration 1 clock cycle is emitted, so that it can be used for capturing the data.

Chronogram

The step for receiving a character are the following:

1. Wait until the rcv signal is 1. It will remains 1 only during 1 system clock cycle
2. Capture the character (8 bits) from the data output
3. Repeat the process