UART RX Requires 2 stop bits

[newhouseb]

I don't see this documented anywhere, and I lost a bit of time to it: sending to the UART RX module requires two stop bits, rather than (the more common) one stop bit.

If you send with one stop bit, every other byte will be dropped. I believe this is because the state machine at the end of a byte is incorrect, but I haven't had a chance to grasp what the code is doing well enough to fix it. Let's look at some examples of the echo example using the pyserial python package.

>>> import serial
>>> ser = serial.Serial('/dev/ttyUSB0', 115200, timeout=1)
>>> ser.write(b'12345678'*8)
64
>>> ser.read(64)
b'13571357135713571357135713571357'

Looking at this on a logic analyzer:

If instead, you specify two stop bits, everything works.

>>> ser = serial.Serial('/dev/ttyUSB0', 115200, timeout=1, stopbits=serial.STOPBITS_TWO)
>>> ser.write(b'12345678'*8)
64
>>> ser.read(64)
b'1234567812345678123456781234567812345678123456781234567812345678'

Note, that you wouldn't see this if you were typing into a serial terminal by hand because unless you are a superhero your fingers can't move that fast.

[Obijuan]

I can confirm that this is a bug! (good caught!) I have been able to reproduce it. Thank you very much

[Obijuan]

Fixed in the latest stdio icestudio module
https://github.com/FPGAwars/Collection-stdio