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As stated on the X440 documentation page, the TRIG IN/OUT
port is not supported with the default FPGA images. I also asked on the mailing list, but since nobody replied, it seems that this feature has not been used so far. Since I am not capable of implementing this feature myself, I would like to suggest it here and support you to the best of my abilities.
Since the product is advertised with this feature and cannot yet be used, we would like to make a suggestion as to how the port could be used sensibly.
We have a usecase for the input or output of a trigger in connection with the replay block:
output a trigger whenever the replay starts over from the start address.
when a trigger arrives, restart the replay of the data from the DRAM.
Setup Details
Base FPGA: X4_1600
Connections: Both radios are used as outputs with a dual MCR and connected with appropriate band pass filters and a power combiner to an R&S FSW where we want to record the signal. With this setup we want to characterize the radio for later pre equalization.
On the radio, we store a waveform on both DRAM banks.
The goal is to start recording at the same time as the signal is transmitted. This can be achieved either by using an external trigger generator to trigger the X440 and the FSW, or by triggering the FSW from the X440.
Expected Behavior
output a trigger whenever the replay starts over from the start address.
when a trigger arrives, restart the replay of the data from the DRAM.
Actual Behaviour
Not implemented.
Additional Information
The proposal is tailored to our intended use and I am open to discussing this feature further so that it can fulfill the widest possible application purpose.
The text was updated successfully, but these errors were encountered:
Issue Description
As stated on the X440 documentation page, the TRIG IN/OUT
port is not supported with the default FPGA images. I also asked on the mailing list, but since nobody replied, it seems that this feature has not been used so far. Since I am not capable of implementing this feature myself, I would like to suggest it here and support you to the best of my abilities.
Since the product is advertised with this feature and cannot yet be used, we would like to make a suggestion as to how the port could be used sensibly.
We have a usecase for the input or output of a trigger in connection with the replay block:
Setup Details
Base FPGA: X4_1600
Connections: Both radios are used as outputs with a dual MCR and connected with appropriate band pass filters and a power combiner to an R&S FSW where we want to record the signal. With this setup we want to characterize the radio for later pre equalization.
On the radio, we store a waveform on both DRAM banks.
The goal is to start recording at the same time as the signal is transmitted. This can be achieved either by using an external trigger generator to trigger the X440 and the FSW, or by triggering the FSW from the X440.
Expected Behavior
Actual Behaviour
Not implemented.
Additional Information
The proposal is tailored to our intended use and I am open to discussing this feature further so that it can fulfill the widest possible application purpose.
The text was updated successfully, but these errors were encountered: