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cpu6.c
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cpu6.c
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/*
* In the SRAM bank the registers are laid out as
*
* 0x0E H (seems to hold PC on IPL changes but otherwise not)
* (possibly PC is cached in the CPU)
* 0x0C G
* 0x0A S
* 0x08 Z
* 0x06 Y
* 0x04 X
* 0x02 B
* 0x00 A
*
* (see monitor 84C3)
*/
#include <assert.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include "cbin.h"
#include "cpu6.h"
#include "disassemble.h"
static uint8_t cpu_ipl = 0; /* IPL 0-15 */
static uint8_t cpu_mmu = 0; /* MMU tag 0-7 */
static uint16_t pc;
static uint16_t exec_pc; /* PC at instruction fetch */
static uint8_t op;
static uint8_t alu_out;
static uint8_t switches = 0xF0;
static uint8_t int_enable;
static unsigned halted;
static unsigned pending_ipl_mask = 0;
#define BS1 0x01
#define BS2 0x02
#define BS3 0x04
#define BS4 0x08
static uint16_t dma_addr;
static uint16_t dma_count;
static uint8_t dma_mode;
static uint8_t dma_enable;
static uint8_t dma_mystery; /* We don't know what this reg on the AM2901 is
about */
/* SRAM on the CPU card */
static uint8_t cpu_sram[256];
static uint8_t mmu[8][32];
// Standing in for some internal microcode state
static unsigned twobit_cached_reg = 0;
static void mmu_mem_write8(uint16_t addr, uint8_t val);
static uint32_t mmu_map(uint16_t addr);
static void logic_flags16(unsigned r);
/*
* DMA engine guesswork
*/
int dma_read_cycle(uint8_t byte)
{
if (dma_enable == 0)
return 1;
/* DMA is done when it incs to 0 */
if (++dma_count == 0) {
dma_enable = 0;
return 1;
}
if (dma_enable) {
/* fprintf(stderr, "%04X: DMA %04X <- %02X\n", dma_count, dma_addr, byte); */
mem_write8(dma_addr++, byte);
}
return 0;
}
int dma_write_active(void)
{
if (dma_enable == 1)
return 1;
return 0;
}
uint8_t dma_write_cycle(void)
{
uint8_t r;
if (dma_enable == 0) {
fprintf(stderr, "DMA write cycle with no DMA\n");
exit(1);
}
r = mmu_mem_read8(dma_addr++);
dma_count++;
if (dma_count == 0)
dma_enable = 0;
return r;
}
uint16_t cpu6_dma_count(void) {
return ~dma_count;
}
void cpu6_dma_write(uint8_t byte) {
/* DMA is done when it incs to 0 */
if (dma_enable == 0) {
return;
}
if (dma_enable) {
mem_write8(dma_addr++, byte);
}
if (++dma_count == 0xffff) {
dma_enable = 0;
}
}
/*
* When packed into C, the flags live in the upper 4 bits of the low byte
*/
#define ALU_L 0x10
#define ALU_F 0x20
#define ALU_M 0x40
#define ALU_V 0x80
/*
* System memory access
*
* For the moment we assume the accesses occur in address order.
*
* For a more serious emulation there are some lurking horrors here.
* Not only do we need to know the order of the accesses but we need
* to know the logic of the postinc/predec operators and how a fault
* is handled half way through an access.
*/
uint8_t mmu_mem_read8(uint16_t addr)
{
if (addr < 0x0100)
return cpu_sram[addr];
return mem_read8(mmu_map(addr));
}
uint8_t mmu_mem_read8_debug(uint16_t addr)
{
if (addr < 0x0100)
return cpu_sram[addr];
return mem_read8_debug(mmu_map(addr));
}
static void mmu_mem_write8(uint16_t addr, uint8_t val)
{
if (addr < 0x0100)
cpu_sram[addr] = val;
else
mem_write8(mmu_map(addr), val);
}
static uint16_t mmu_mem_read16(uint16_t addr)
{
uint16_t r = mmu_mem_read8(addr) << 8;
r |= mmu_mem_read8(addr + 1);
return r;
}
static void mmu_mem_write16(uint16_t addr, uint16_t val)
{
mmu_mem_write8(addr, val >> 8);
mmu_mem_write8(addr + 1, val);
}
/*
* We know from the start address that the processor microsteps begin
* inc pc
* load opcode from (pc)
*
* however it's not clear this is observable or matters for the moment
* because the cases that seem to matter like branches appear to do
*
* inc pc
* load opcode
* inc pc
* load offset
* add offset
*
* and then the inc of pc before the next instruction works. What
* does need a hard look here is the behaviour of X.
*/
uint8_t fetch(void)
{
/* Do the pc++ after so that tracing is right */
uint8_t r = mmu_mem_read8(pc);
pc++;
return r;
}
uint16_t fetch16(void)
{
uint16_t r;
r = mmu_mem_read8(pc) << 8;
pc++;
r |= mmu_mem_read8(pc);
pc++;
return r;
}
uint16_t fetch_literal(unsigned length)
{
uint16_t addr = pc;
pc += length;
return addr;
}
static uint8_t reg_read(uint8_t r)
{
return mmu_mem_read8((cpu_ipl << 4) | r);
}
static void reg_write(uint8_t r, uint8_t v)
{
mmu_mem_write8((cpu_ipl << 4) | r, v);
}
/*
* This needs some updating if CPU6 behaves like CPU4. On the EE200
* a word register specified with an odd value gives you the upper byte
* twice.
*/
static uint16_t regpair_addr(uint8_t r)
{
return r + (cpu_ipl << 4);
}
static uint16_t regpair_read(uint8_t r)
{
if (r > 15) {
fprintf(stderr, "Bad regpair encoding %02X %02X %04X\n",
op, r, exec_pc);
exit(1);
}
return (reg_read((r | 1) ^ 1) << 8) | reg_read((r ^ 1));
}
static void regpair_write(uint8_t r, uint16_t v)
{
if (r > 15) {
fprintf(stderr, "Bad regpair encoding %02X %04X\n", op,
exec_pc);
exit(1);
}
reg_write((r | 1) ^ 1, v >> 8);
reg_write((r ^ 1), v);
}
/*
* Stack helpers
*/
void push(uint16_t val)
{
uint16_t addr = regpair_read(S);
addr -= 2;
mmu_mem_write16(addr, val);
regpair_write(S, addr);
}
uint16_t pop(void)
{
uint16_t addr = regpair_read(S);
uint16_t d = mmu_mem_read16(addr);
regpair_write(S, addr + 2);
return d;
}
void pushbyte(uint8_t val)
{
uint16_t addr = regpair_read(S);
addr -= 1;
mmu_mem_write8(addr, val);
regpair_write(S, addr);
}
uint8_t popbyte(void)
{
uint16_t addr = regpair_read(S);
uint8_t d = mmu_mem_read8(addr);
regpair_write(S, addr + 1);
return d;
}
static uint16_t get_twobit(unsigned mode, unsigned idx, unsigned len) {
uint16_t addr = 0;
unsigned regs;
unsigned thismode = mode;
if (idx == 0)
thismode = mode >> 2;
switch (thismode & 0x3) {
case 0:
// EA <- PC
addr = fetch16();
//fprintf(stderr, "%x EA <- (PC) = %04x\n", idx, addr);
break;
case 1:
// EA <- imm8/imm16 + r1 + r2
//fprintf(stderr, "%x EA <- ", idx);
regs = fetch();
addr = (regs & 0x10) ? fetch16() : fetch(); // if r1 is odd, do imm16
//fprintf(stderr, "%04x", addr);
addr += regpair_read((regs >> 4) & 0xe);
//fprintf(stderr, " + (%x) %04x", (regs >> 4) & 0xe, regpair_read((regs >> 4) & 0xe));
if ((regs & 0xe) != 0) { // ignore r2 if it's A
addr += regpair_read(regs & 0xe);
//fprintf(stderr, " + (%x) %04x", regs & 0xe, regpair_read(regs & 0xe));
}
//fprintf(stderr, " = %04x", addr);
break;
case 2:
// EA <- R
// This mode is complicated because it tries to merge two mode 2s into a single byte
if (idx == 1 && mode == 0xa) {
// previous twobit already fetched our regbyte
regs = twobit_cached_reg;
} else {
twobit_cached_reg = regs = fetch();
}
if (idx == 0)
regs >>= 4;
addr = regpair_read(regs & 0xe);
//fprintf(stderr, "%x EA <- reg(%x) = %04x\n", idx, regs & 0xe, addr);
break;
case 3:
// EA <- (literal)
addr = fetch_literal(len);
//fprintf(stderr, "%x EA <- (imm)*0x%02x = %04x\n", idx, len+1, addr);
break;
}
return addr;
}
/*
* The MMU
*
* The MMU is a 256 byte 'fast' SRAM. The bus is wired for 2K physical
* pages with the MMU providing the upper bits. The MMU is indexed by
* 3 lines. Diag pretty much requires line 0 is the low bit of the IPL
* but the other two are a mystery so might be more IPL lines or a DMA
* enable line or similar.
*
* There does not appear to be any kind of pass-through mode, instead
* microcode initializes the MMU for IPL0 at boot.
*/
static uint32_t mmu_map(uint16_t addr)
{
/* fprintf(stderr, "MMU %X is [%X] -> %X\n", addr, addr >> 11, (mmu[(addr >> 11)] << 11) |(addr & 0x7FF)); */
/* FIXME: add tag in to shift bank */
return (mmu[cpu_mmu][(addr >> 11)] << 11) + (addr & 0x07FF);
}
/*
* MMU read/write operations
*
* 2E sssrmmnn
*
* s - sub-op
* r - read; 0 = write to mmu, 1 = read from mmu
* m - opn1 twobit address mode
* n - mem twobit address mode
*/
static int mmu_transfer_op(void)
{
unsigned subop = fetch();
// While opn1 is commonly an immediate, it can actually use any
// addressing mode
uint8_t opn1 = mmu_mem_read8(get_twobit(subop, 0, 1));
// opn1 is in the format xxxxxbbb
uint8_t base = opn1 & 0x7; // b - page table base
uint8_t x = opn1 >> 3; // x - meaning depends on subop
uint8_t offset = 0;
unsigned len, val;
switch (subop & 0xe0) {
case 0x00: // WPF/RPF - transfer x entries at offset 0
len = x + 1;
break;
case 0x20: // WPF1/RPF1 - transfer 1 entry at offset x
len = 1;
offset = x;
break;
case 0x40: // WPF32/RPF32 - transfer (32-x) entries at offset x
offset = x;
len = 32 - x;
break;
default:
// microcode suggests these are illegal (will trap)
fprintf(stderr, "%04X: Illegal 2E op %02X\n", cpu6_pc(), op);
return 0;
}
// There is no way to bypass the MMU, so entries are always
// transferred to/from virtual addresses
// The microcode might have a requirement for this to not be implicit
uint16_t addr = get_twobit(subop, 1, len);
switch(subop & 0x10) {
case 0x00:
while(len--) {
assert(base < 8 && offset < 0x20);
mmu[base][offset++] = mmu_mem_read8(addr++);
}
break;
case 0x10:
while(len--) {
assert(base < 8 && offset < 0x20);
val = mmu[base][offset++];
mmu_mem_write8(addr++, val);
// We know this has some flag effects because 8130 relies upon it setting
// presumably Z to exit
logic_flags16(val);
}
break;
}
return 0;
}
static uint8_t block_op_getLen(int inst, int op) {
if ((op & 0xF0) == 0x00) // binload doesn't take a length
return 0;
if (inst == 0x47) {
// 47 instructions take a literal
return fetch();
} else {
// 67 instructions take the length in AL
// We aren't 100% sure that this takes AL instead of A
// But code that needs a 16bit memcpy seems to use F7 instead
return reg_read(AL);
}
}
static void cbin_load_segment(uint16_t sa, uint16_t load_offset, unsigned trace)
{
uint8_t type = mmu_mem_read8(sa);
uint8_t len = mmu_mem_read8(sa + 1);
uint16_t addr = mmu_mem_read16(sa + 2);
uint8_t checksum = type + len + (addr >> 8) + (addr & 0xFF);
uint8_t expected;
if (trace)
fprintf(stderr, "%04X: cbin section @ %04X type %08X length %u addr %04X load_offset %04X\n",
cpu6_pc(), sa, type, len, addr, load_offset);
sa += 4;
alu_out &= ~ALU_L;
switch (type)
{
case CBIN_DATA:
for (int i = 0; i < len; i++) {
uint8_t val = mmu_mem_read8(sa++);
mmu_mem_write8(load_offset + addr + i, val);
checksum += val;
}
break;
case CBIN_FIXUPS:
// Apply fixups
if (len % 2 == 1){
fprintf(stderr, "%04X: loadseg: FIXUPS record must have even length; have %u\n", cpu6_pc(), len);
alu_out |= ALU_F;
} else {
uint16_t offset = load_offset + addr;
for (size_t i = 0; i < len; i += 2) {
uint16_t fixup_addr = mmu_mem_read16(sa);
uint16_t fixup_val = mmu_mem_read16(fixup_addr + load_offset);
mmu_mem_write16(fixup_addr + load_offset, fixup_val + offset);
checksum += (fixup_addr >> 8) + (fixup_addr & 0xFF);
sa += 2;
}
}
break;
default:
fprintf(stderr, "%04X: unknown cbin segment type %02x\n", cpu6_pc(), type);
alu_out |= ALU_F;
}
checksum = 0x0100 - checksum;
expected = mmu_mem_read8(sa++);
if (checksum != expected) {
fprintf(stderr, "%04X: loadseg checksum error: %08X vs %08X\n",
cpu6_pc(), checksum, expected);
alu_out |= ALU_F;
}
// According to sjsoftware, this instruction always provides these values
// in A and Z regardless of instruction operands
regpair_write(A, load_offset + addr);
regpair_write(Z, sa);
}
/*
* Block/String operations
*
* 47 ssssmmnn - Take length as byte immediate
* 67 ssssmmnn - Take length as AL
*
* s = sub-op
* m = src address mode
* n = dst address mode
*
* Not all sub-ops take a length.
* Some sub-ops take additional args, as immediate or implicit reg
*/
static int block_op(int inst, unsigned trace)
{
unsigned op = fetch();
unsigned am = op & 0x0F;
unsigned dst_len = block_op_getLen(inst, op) + 1;
unsigned src_len = dst_len;
uint16_t sa, da;
uint8_t chr;
// clear the fault flag
alu_out &= ~ALU_F;
// memset only reads the source once
if ((op & 0xF0) == 0x90)
src_len = 1;
// memchr takes an extra "chr" operand
if ((op & 0xF0) == 0x20) {
if (inst == 0x47) {
chr = fetch();
} else {
// This gets it's chr from somewhere else. Probally a register?
fprintf(stderr, "Unsupported 67 2x memchr at %x\n", exec_pc);
exit(-1);
}
}
sa = get_twobit(am, 0, src_len);
da = get_twobit(am, 1, dst_len);
switch(op & 0xF0) {
case 0x00:
// Load a segment of a binary file
// [sa] = destination offset
// da = a pointer to a segment
cbin_load_segment(da, mmu_mem_read16(sa), trace);
return 0;
case 0x20:
// copies bytes from src to dst, stopping if a byte matches chr
// appears to be combined memcpy/memchr/strcpy
// It's possible it might also stop when chr is 0, which would
// change it's behavior to a combined strcpy/strchr/strlen
while(dst_len--) {
uint8_t val = mmu_mem_read8(sa);
mmu_mem_write8(da, val);
if (val == chr) { // Match
regpair_write(Y, sa);
regpair_write(Z, da);
return 0;
}
sa++;
da++;
};
// No match
alu_out |= ALU_F;
return 0;
case 0x40:
while(dst_len--) {
mmu_mem_write8(da++, mmu_mem_read8(sa++));
};
return 0;
case 0x60:
// Complete Guess, but this might be OR
while(dst_len--) {
uint8_t val = mmu_mem_read8(da++) | mmu_mem_read8(sa++);
mmu_mem_write8(da, val);
};
return 0;
case 0x70:
// Complete Guess, but this might be AND
while(dst_len--) {
uint8_t val = mmu_mem_read8(da++) & mmu_mem_read8(sa++);
mmu_mem_write8(da, val);
};
return 0;
case 0x80:
alu_out |= ALU_V;
while (dst_len--) {
if(mmu_mem_read8(da++) !=
mmu_mem_read8(sa++)) {
alu_out &= ~ALU_V;
break;
}
}
return 0;
case 0x90: /* memset */
chr = mmu_mem_read8(sa);
while (dst_len--) {
mmu_mem_write8(da++, chr);
}
return 0;
default:
fprintf(stderr, "%04X: Unknown block xfer %02X\n", cpu6_pc(), op);
exit(1);
}
}
/* F7 - a 16bit memcpy instruction
*
* Args
* A - Length
* B - Source
* Y - Dest
*
* Appears to leave all registers unmodified?
*/
static int memcpy16(void) {
uint16_t len = regpair_read(A);
uint16_t sa = regpair_read(B);
uint16_t da = regpair_read(Y);
do {
mmu_mem_write8(da++, mmu_mem_read8(sa++));
} while(len--);
return 0;
}
static void sub_flags(uint8_t r, uint8_t a, uint8_t b);
static int bignum_sub(int a_len, int b_len, uint64_t a_addr, uint16_t b_addr, int write_back) {
// b = a - b
if (a_len > b_len) {
// No idea what it should do here. Trap? overflow and set the FAULT flag?
fprintf(stderr, "unsupported SUBBIG at %04X\n", exec_pc);
exit(-1);
}
// For debugging
uint64_t result_big = 0;
int shift = 0;
uint64_t a_big = 0;
uint64_t b_big = 0;
// Roughly the microcode state
uint32_t borrow = 0; // Probally just the link flag on real hardware
uint8_t zero_acc = 0; // will collect any one bits
uint8_t a_val = 0;
uint8_t b_val = 0;
uint8_t result = 0;
for (a_len--, b_len--; b_len >= 0; b_len--, a_len--) {
if (a_len >= 0) {
a_val = mmu_mem_read8(a_addr + a_len);
} else {
a_val = ((int8_t)a_val) >> 8; // sign extend previous byte
}
b_val = mmu_mem_read8(b_addr + b_len);
a_big |= a_val << shift;
b_big |= b_val << shift;
result = b_val - a_val - borrow;
result_big |= result << shift;
shift += 8;
//fprintf(stderr, "%i %i | %02x - %02x - %02x = %04x;", b_len, a_len, b_val, a_val, borrow, result & 0xff);
zero_acc |= (result != 0);
borrow = (a_val > b_val);
//fprintf(stderr, " borrow = %x;\n", borrow);
if (write_back)
mmu_mem_write8(b_addr + b_len, result);
}
//fprintf(stderr, "%s %lx - %lx == %lx\n", write_back ? "SUBBIG" : "CMPBIG", b_big, a_big, result_big);
sub_flags(result | zero_acc, a_val, b_val);
alu_out &= ~ALU_L;
if (borrow == 0)
alu_out |= ALU_L;
return 0;
}
/* Various microcode math routines which operate on arbitrary width integers
*
* 46 llllkkkk ssssmmnn
*
* l - size of a operand (typically)
* k - size of b operand
* s - subop
* m - a address mode
* n - b address mode
*
* Valid sizes are 1 to 16 bytes
* Some subops may take extra arguments via implicit registers
*/
static int bignum_op(void) {
unsigned sizes = fetch();
unsigned a_size = (sizes >> 4) + 1;
unsigned b_size = (sizes & 0xf) + 1;
unsigned mode = fetch();
if ((mode >> 4) == 9) {
// bignum to Ascii
// I have no idea how the actual microcode routine works, so here is an approximation
// that works upto 64bits
// Doesn't handle cases where buffer hasn't been memset to 0xc0
unsigned dest_width = reg_read(AL);
unsigned base = a_size + 1;
if (b_size > 8) {
fprintf(stderr, "%i byte baseconv too big for our modern 64bit machines\n", b_size);
exit(1);
}
uint16_t dst_addr = get_twobit(mode, 0, dest_width);
uint16_t src_addr = get_twobit(mode, 1, b_size);
// Convert to little endian
unsigned long long num = 0;
for (int i=0; i < b_size; i++) {
num = num << 8 | mmu_mem_read8(src_addr+i);
}
char buffer[32];
if (base == 10) {
snprintf(buffer, sizeof(buffer), "%llu", num);
} else if (base == 16) {
snprintf(buffer, sizeof(buffer), "%llX", num);
} else {
fprintf(stderr, "baseconv, unsupported base %i\n", base);
exit(1);
}
// I'm kind of guessing here, but it seems to do this?
unsigned actual_width = strlen(buffer);
if (actual_width > dest_width) {
alu_out = ALU_F;
return 0;
}
alu_out = 0;
for (int i=0; i<actual_width; i++) {
mmu_mem_write8(dst_addr+i, buffer[i] | 0x80);
}
// apparently A needs to be updated to point after string
regpair_write(A, dst_addr + actual_width);
return 0;
}
if ((mode >> 4) == 8) {
// ASCII to bignum
// I'm not sure how the actual microcode routine works, so here is an approximation
// that works upto 64 bits.
unsigned src_width = reg_read(AL);
if (b_size > 8 || src_width > 31) {
fprintf(stderr, "%i byte ascii-to-bignum is too big for our modern 64bit machines\n", b_size);
exit(1);
}
uint16_t src_addr = get_twobit(mode, 0, src_width);
uint16_t dst_addr = get_twobit(mode, 1, b_size);
// Copy string out
char buffer[32];
for (int i=0; i < src_width; i++) {
buffer[i] = mmu_mem_read8(src_addr+i) & 0x7f;
}
buffer[src_width] = '\0';
char* end_ptr = &buffer[src_width];
uint64_t result = strtol(buffer, &end_ptr, a_size + 1);
if (end_ptr == NULL) {
alu_out = ALU_F;
return 0;
}
alu_out = 0;
// Guessing that this might set some flags?
if (result == 0)
alu_out |= ALU_V;
if (((int64_t)result) < 0)
alu_out |= ALU_M;
for (int i = b_size-1; i >= 0; i--) {
mmu_mem_write8(dst_addr + i, result & 0xff);
result >>= 8;
}
return 0;
}
uint16_t a_addr = get_twobit(mode, 0, a_size);
uint16_t b_addr = get_twobit(mode, 1, b_size);
switch (mode >> 4) {
case 1: // SUBBIG
return bignum_sub(a_size, b_size, a_addr, b_addr, 1);
case 2: // CMPBIG
return bignum_sub(a_size, b_size, a_addr, b_addr, 0);
default:
fprintf(stderr, "Unsupported 46 Bignum op %i\n", mode >> 4);
exit(1);
}
}
/*
* Load flags
* F not touched
* L not touched
* M cleared then set if MSB of operand
*/
static void ldflags(unsigned r)
{
alu_out &= ~(ALU_M | ALU_V);
if (r & 0x80)
alu_out |= ALU_M;
if ((r & 0xFF) == 0)
alu_out |= ALU_V;
}
/*
* The docs simply say that F is set if the sign of the destination
* register changes.
*
* V - set according to value being zero or non zero
* M - set on result being negative
* F - set according to overflow rules
*
* L is set only by add so done in add
*/
static void arith_flags(unsigned r, uint8_t a, uint8_t b)
{
alu_out &= ~(ALU_F | ALU_M | ALU_V);
if ((r & 0xFF) == 0)
alu_out |= ALU_V;
if (r & 0x80)
alu_out |= ALU_M;
/* if ((r ^ d) & 0x80)
alu_out |= ALU_F; */
/* Overflow for addition is (!r & x & m) | (r & !x & !m) */
if (r & 0x80) {
if (!((a | b) & 0x80))
alu_out |= ALU_F;
} else {
if (a & b & 0x80)
alu_out |= ALU_F;
}
}
/*
* Subtract is similar but the overflow rule probably differs and
* L is a borrow not a carry
*/
static void sub_flags(uint8_t r, uint8_t a, uint8_t b)
{
alu_out &= ~(ALU_F | ALU_M | ALU_V);
if ((r & 0xFF) == 0)
alu_out |= ALU_V;
if (r & 0x80)
alu_out |= ALU_M;
if (a & 0x80) {
if (!((b | r) & 0x80))
alu_out |= ALU_F;;
} else {
if (b & r & 0x80)
alu_out |= ALU_F;;
}
}
/*
* Logical operations
* M is set if there is a 1 in the MSB of the source register
* (or dest register for double register ops)
* TODO: before or after operation ?
*/
static void logic_flags(unsigned r)
{
alu_out &= ~(ALU_M | ALU_V);
if (r & 0x80)
alu_out |= ALU_M;
if (!(r & 0xFF))
alu_out |= ALU_V;
}
/*
* Shift
* L is the bit shifted out
* M is set as with logic
* V is set if result is zero
* Left shift/rotate: F is xor of L and M after shift
*
*/
static void shift_flags(unsigned c, unsigned r)
{
alu_out &= ~(ALU_L | ALU_M | ALU_V);
if ((r & 0xFF) == 0)
alu_out |= ALU_V;
if (c)
alu_out |= ALU_L;
if (r & 0x80)
alu_out |= ALU_M;
}
/*
* Load flags
* F not touched
* L not touched
* M cleared then set if MSB of operand
*/
static void ldflags16(unsigned r)
{
alu_out &= ~(ALU_M | ALU_V);
if (r & 0x8000)
alu_out |= ALU_M;
if ((r & 0xFFFF) == 0)
alu_out |= ALU_V;
}
/*
* The docs simply say that F is set if the sign of the destination
* register changes.
*
* V - set according to value being zero or non zero
* M - set on result being negative
* F - set according to overflow rules
*
* L is set only by add so done in add
*/
static void arith_flags16(unsigned r, uint16_t a, uint16_t b)
{
alu_out &= ~(ALU_F | ALU_M | ALU_V);
if ((r & 0xFFFF) == 0)
alu_out |= ALU_V;
if (r & 0x8000)
alu_out |= ALU_M;
/* If the result is negative but both inputs were positive then
we overflowed */
/* if ((r ^ d) & 0x8000)
alu_out |= ALU_F; */
/* Overflow for addition is (!r & x & m) | (r & !x & !m) */
if (r & 0x8000) {
if (!((a | b) & 0x8000))
alu_out |= ALU_F;
} else {
if (a & b & 0x8000)
alu_out |= ALU_F;
}
}
/*
* Subtract is similar but the overflow rule probably differs and
* L is a borrow not a carry
*/
static void sub_flags16(uint16_t r, uint16_t a, uint16_t b)
{
alu_out &= ~(ALU_F | ALU_M | ALU_V);
if ((r & 0xFFFF) == 0)
alu_out |= ALU_V;
if (r & 0x8000)
alu_out |= ALU_M;
if (a & 0x8000) {
if (!((b | r) & 0x8000))
alu_out |= ALU_F;;
} else {
if (b & r & 0x8000)
alu_out |= ALU_F;;
}
}
/*
* Logical operations
* M is set if there is a 1 in the MSB of the source register
* (or dest register for double register ops)
* TODO: before or after operation ?
*/
static void logic_flags16(unsigned r)
{