Examples

In order to demonstrate the functionality of PROLEAD, we provide some selected examples in the examples folder. Each example is structured as follows:

1. The rtl folder contains the rtl code in VHDL or Verilog.
2. The gate folder contains the resulting gate level netlist which is given as an input to PROLEAD.
3. The results directory which is further divided into normal_mode and compact_mode directories contains the used config.set file which encompasses all evaluation settings. In addition, we created an execution script run.sh for each test case. To execute the script, just navigate into the respective folder and run ./run.sh. Moreover, results contains all reports generated by PROLEAD. The main report is given as Report.dat and builds the starting point for interpreting the results. More information regarding the interpretation of results is given under Results.

We summarize the evaluation results in the following table. We remark that the configuration can be slightly different compared to the paper. Note that different configurations may lead to different runtimes and memory requirements. Moreover, runtimes can be different when using another machine. All examples were performed in a Ubuntu 20.04 subsystem on a Windows 10 server with 512GB RAM and by using at most 48 cores.

Design	Reference	Order	Secure	RAM (Compact)	Time (Compact)	RAM (Normal)	Time (Normal)
TI, PRESENT S-box, Uniform	[PMK+11]	1	Yes	3.8GB	30.6sec	4.0GB	0.1sec
TI, PRESENT S-box, Not uniform	[EGMP17]	1	No	3.5GB	0.1sec	3.5GB	0.1sec
TI, AES S-Box	[MPL+11]	1	Yes	6.3GB	6.6min	37.3GB	3.6min
DOM, AES S-Box	[GMK16]	1	Yes	6.3GB	6.2min	12.4GB	2.1min
DOM, AES S-Box	[GMK16]	2	Yes	8.4GB	3.9h	492.9GB	3.7h
CMS, AES S-Box	[CRB+16]	1	Yes	6.3GB	8.7min	38.4GB	4.1min
CMS, AES S-Box	[CRB+16]	2	Yes	8.8GB	4.8h	504.3GB	5.4h
TI, nibble-serial PRESENT-80	[PMK+11]	1	Yes	36.9GB	49.4min	5.6GB	2.3min
TI, nibble-serial PRESENT-80	[EGMP17]	1	No	3.7GB	1.2sec	3.9GB	4.9sec