From 0affa17038a14a83d55094aa694cd956fc4187f7 Mon Sep 17 00:00:00 2001 From: fcarreiro Date: Wed, 11 Sep 2024 12:44:00 +0000 Subject: [PATCH 1/5] feat(avm)!: variants for CAST opcode --- avm-transpiler/src/opcodes.rs | 6 ++++-- avm-transpiler/src/transpile.rs | 10 ++++++++-- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/avm-transpiler/src/opcodes.rs b/avm-transpiler/src/opcodes.rs index 0ac140b2d3c4..f3fdd14dc6ca 100644 --- a/avm-transpiler/src/opcodes.rs +++ b/avm-transpiler/src/opcodes.rs @@ -31,7 +31,8 @@ pub enum AvmOpcode { SHL_16, SHR_8, SHR_16, - CAST, + CAST_8, + CAST_16, // Execution environment ADDRESS, STORAGEADDRESS, @@ -133,7 +134,8 @@ impl AvmOpcode { AvmOpcode::SHR_8 => "SHR_8", AvmOpcode::SHR_16 => "SHR_16", // Compute - Type Conversions - AvmOpcode::CAST => "CAST", + AvmOpcode::CAST_8 => "CAST_8", + AvmOpcode::CAST_16 => "CAST_16", // Execution Environment AvmOpcode::ADDRESS => "ADDRESS", diff --git a/avm-transpiler/src/transpile.rs b/avm-transpiler/src/transpile.rs index 9cf34dd66c94..c0cb28c9f0da 100644 --- a/avm-transpiler/src/transpile.rs +++ b/avm-transpiler/src/transpile.rs @@ -823,6 +823,12 @@ fn generate_cast_instruction( destination_indirect: bool, dst_tag: AvmTypeTag, ) -> AvmInstruction { + let bits_needed = bits_needed_for(&source).max(bits_needed_for(&destination)); + let avm_opcode = match bits_needed { + 8 => AvmOpcode::CAST_8, + 16 => AvmOpcode::CAST_16, + _ => panic!("CAST only supports 8 and 16 bit encodings, needed {}", bits_needed), + }; let mut indirect_flags = ALL_DIRECT; if source_indirect { indirect_flags |= ZEROTH_OPERAND_INDIRECT; @@ -831,10 +837,10 @@ fn generate_cast_instruction( indirect_flags |= FIRST_OPERAND_INDIRECT; } AvmInstruction { - opcode: AvmOpcode::CAST, + opcode: avm_opcode, indirect: Some(indirect_flags), tag: Some(dst_tag), - operands: vec![AvmOperand::U32 { value: source }, AvmOperand::U32 { value: destination }], + operands: vec![make_operand(bits_needed, &source), make_operand(bits_needed, &destination)], } } From c624f03e6a3db05e2aa5983980c8436df437d9ac Mon Sep 17 00:00:00 2001 From: fcarreiro Date: Wed, 11 Sep 2024 12:50:06 +0000 Subject: [PATCH 2/5] simulator side cast + not --- yarn-project/simulator/src/avm/avm_gas.ts | 12 +++++++---- .../simulator/src/avm/opcodes/bitwise.test.ts | 14 ++++++------- .../simulator/src/avm/opcodes/bitwise.ts | 2 +- .../src/avm/opcodes/instruction_impl.ts | 20 +++++++++++++------ .../simulator/src/avm/opcodes/memory.test.ts | 14 ++++++------- .../simulator/src/avm/opcodes/memory.ts | 2 +- .../serialization/bytecode_serialization.ts | 6 ++++-- .../instruction_serialization.ts | 6 ++++-- 8 files changed, 46 insertions(+), 30 deletions(-) diff --git a/yarn-project/simulator/src/avm/avm_gas.ts b/yarn-project/simulator/src/avm/avm_gas.ts index d325aa5a3279..01140e99d326 100644 --- a/yarn-project/simulator/src/avm/avm_gas.ts +++ b/yarn-project/simulator/src/avm/avm_gas.ts @@ -79,12 +79,14 @@ const BaseGasCosts: Record = { [Opcode.OR_16]: makeCost(c.AVM_OR_BASE_L2_GAS, 0), [Opcode.XOR_8]: makeCost(c.AVM_XOR_BASE_L2_GAS, 0), [Opcode.XOR_16]: makeCost(c.AVM_XOR_BASE_L2_GAS, 0), - [Opcode.NOT]: makeCost(c.AVM_NOT_BASE_L2_GAS, 0), + [Opcode.NOT_8]: makeCost(c.AVM_NOT_BASE_L2_GAS, 0), + [Opcode.NOT_16]: makeCost(c.AVM_NOT_BASE_L2_GAS, 0), [Opcode.SHL_8]: makeCost(c.AVM_SHL_BASE_L2_GAS, 0), [Opcode.SHL_16]: makeCost(c.AVM_SHL_BASE_L2_GAS, 0), [Opcode.SHR_8]: makeCost(c.AVM_SHR_BASE_L2_GAS, 0), [Opcode.SHR_16]: makeCost(c.AVM_SHR_BASE_L2_GAS, 0), - [Opcode.CAST]: makeCost(c.AVM_CAST_BASE_L2_GAS, 0), + [Opcode.CAST_8]: makeCost(c.AVM_CAST_BASE_L2_GAS, 0), + [Opcode.CAST_16]: makeCost(c.AVM_CAST_BASE_L2_GAS, 0), [Opcode.ADDRESS]: makeCost(c.AVM_ADDRESS_BASE_L2_GAS, 0), [Opcode.STORAGEADDRESS]: makeCost(c.AVM_STORAGEADDRESS_BASE_L2_GAS, 0), [Opcode.SENDER]: makeCost(c.AVM_SENDER_BASE_L2_GAS, 0), @@ -164,12 +166,14 @@ const DynamicGasCosts: Record = { [Opcode.OR_16]: makeCost(c.AVM_OR_DYN_L2_GAS, 0), [Opcode.XOR_8]: makeCost(c.AVM_XOR_DYN_L2_GAS, 0), [Opcode.XOR_16]: makeCost(c.AVM_XOR_DYN_L2_GAS, 0), - [Opcode.NOT]: makeCost(c.AVM_NOT_DYN_L2_GAS, 0), + [Opcode.NOT_8]: makeCost(c.AVM_NOT_DYN_L2_GAS, 0), + [Opcode.NOT_16]: makeCost(c.AVM_NOT_DYN_L2_GAS, 0), [Opcode.SHL_8]: makeCost(c.AVM_SHL_DYN_L2_GAS, 0), [Opcode.SHL_16]: makeCost(c.AVM_SHL_DYN_L2_GAS, 0), [Opcode.SHR_8]: makeCost(c.AVM_SHR_DYN_L2_GAS, 0), [Opcode.SHR_16]: makeCost(c.AVM_SHR_DYN_L2_GAS, 0), - [Opcode.CAST]: makeCost(c.AVM_CAST_DYN_L2_GAS, 0), + [Opcode.CAST_8]: makeCost(c.AVM_CAST_DYN_L2_GAS, 0), + [Opcode.CAST_16]: makeCost(c.AVM_CAST_DYN_L2_GAS, 0), [Opcode.ADDRESS]: makeCost(c.AVM_ADDRESS_DYN_L2_GAS, 0), [Opcode.STORAGEADDRESS]: makeCost(c.AVM_STORAGEADDRESS_DYN_L2_GAS, 0), [Opcode.SENDER]: makeCost(c.AVM_SENDER_DYN_L2_GAS, 0), diff --git a/yarn-project/simulator/src/avm/opcodes/bitwise.test.ts b/yarn-project/simulator/src/avm/opcodes/bitwise.test.ts index ff6b355fa718..2741110d7231 100644 --- a/yarn-project/simulator/src/avm/opcodes/bitwise.test.ts +++ b/yarn-project/simulator/src/avm/opcodes/bitwise.test.ts @@ -363,20 +363,20 @@ describe('Bitwise instructions', () => { describe('NOT', () => { it('Should (de)serialize correctly', () => { const buf = Buffer.from([ - Not.opcode, // opcode + Opcode.NOT_16, // opcode 0x01, // indirect TypeTag.UINT64, // inTag - ...Buffer.from('12345678', 'hex'), // aOffset - ...Buffer.from('3456789a', 'hex'), // dstOffset + ...Buffer.from('1234', 'hex'), // aOffset + ...Buffer.from('3456', 'hex'), // dstOffset ]); const inst = new Not( /*indirect=*/ 0x01, /*inTag=*/ TypeTag.UINT64, - /*aOffset=*/ 0x12345678, - /*dstOffset=*/ 0x3456789a, - ); + /*aOffset=*/ 0x1234, + /*dstOffset=*/ 0x3456, + ).as(Opcode.NOT_16, Not.wireFormat16); - expect(Not.deserialize(buf)).toEqual(inst); + expect(Not.as(Not.wireFormat16).deserialize(buf)).toEqual(inst); expect(inst.serialize()).toEqual(buf); }); diff --git a/yarn-project/simulator/src/avm/opcodes/bitwise.ts b/yarn-project/simulator/src/avm/opcodes/bitwise.ts index 7ead46b1bee7..eb377631766e 100644 --- a/yarn-project/simulator/src/avm/opcodes/bitwise.ts +++ b/yarn-project/simulator/src/avm/opcodes/bitwise.ts @@ -87,7 +87,7 @@ export class Shr extends ThreeOperandBitwiseInstruction { export class Not extends TwoOperandInstruction { static readonly type: string = 'NOT'; - static readonly opcode = Opcode.NOT; + static readonly opcode = Opcode.NOT_8; constructor(indirect: number, inTag: number, aOffset: number, dstOffset: number) { super(indirect, inTag, aOffset, dstOffset); diff --git a/yarn-project/simulator/src/avm/opcodes/instruction_impl.ts b/yarn-project/simulator/src/avm/opcodes/instruction_impl.ts index 01166d42314d..86e042f44c18 100644 --- a/yarn-project/simulator/src/avm/opcodes/instruction_impl.ts +++ b/yarn-project/simulator/src/avm/opcodes/instruction_impl.ts @@ -5,12 +5,19 @@ import { Addressing } from './addressing_mode.js'; import { Instruction } from './instruction.js'; /** Wire format that informs deserialization for instructions with two operands. */ -export const TwoOperandWireFormat = [ +export const TwoOperandWireFormat8 = [ OperandType.UINT8, OperandType.UINT8, OperandType.UINT8, - OperandType.UINT32, - OperandType.UINT32, + OperandType.UINT8, + OperandType.UINT8, +]; +export const TwoOperandWireFormat16 = [ + OperandType.UINT8, + OperandType.UINT8, + OperandType.UINT8, + OperandType.UINT16, + OperandType.UINT16, ]; /** Wire format that informs deserialization for instructions with three operands. */ @@ -33,11 +40,12 @@ export const ThreeOperandWireFormat16 = [ /** * Covers (de)serialization for an instruction with: - * indirect, inTag, and two UINT32s. + * indirect, inTag, and two operands. */ export abstract class TwoOperandInstruction extends Instruction { // Informs (de)serialization. See Instruction.deserialize. - static readonly wireFormat: OperandType[] = TwoOperandWireFormat; + static readonly wireFormat8: OperandType[] = TwoOperandWireFormat8; + static readonly wireFormat16: OperandType[] = TwoOperandWireFormat16; constructor( protected indirect: number, @@ -51,7 +59,7 @@ export abstract class TwoOperandInstruction extends Instruction { /** * Covers (de)serialization for an instruction with: - * indirect, inTag, and three UINT32s. + * indirect, inTag, and three operands. */ export abstract class ThreeOperandInstruction extends Instruction { static readonly wireFormat8: OperandType[] = ThreeOperandWireFormat8; diff --git a/yarn-project/simulator/src/avm/opcodes/memory.test.ts b/yarn-project/simulator/src/avm/opcodes/memory.test.ts index 99967748062b..74bce1ee5896 100644 --- a/yarn-project/simulator/src/avm/opcodes/memory.test.ts +++ b/yarn-project/simulator/src/avm/opcodes/memory.test.ts @@ -161,20 +161,20 @@ describe('Memory instructions', () => { describe('CAST', () => { it('Should deserialize correctly', () => { const buf = Buffer.from([ - Cast.opcode, // opcode + Opcode.CAST_16, // opcode 0x01, // indirect TypeTag.FIELD, // dstTag - ...Buffer.from('12345678', 'hex'), // aOffset - ...Buffer.from('3456789a', 'hex'), // dstOffset + ...Buffer.from('1234', 'hex'), // aOffset + ...Buffer.from('3456', 'hex'), // dstOffset ]); const inst = new Cast( /*indirect=*/ 0x01, /*dstTag=*/ TypeTag.FIELD, - /*aOffset=*/ 0x12345678, - /*dstOffset=*/ 0x3456789a, - ); + /*aOffset=*/ 0x1234, + /*dstOffset=*/ 0x3456, + ).as(Opcode.CAST_16, Cast.wireFormat16); - expect(Cast.deserialize(buf)).toEqual(inst); + expect(Cast.as(Cast.wireFormat16).deserialize(buf)).toEqual(inst); expect(inst.serialize()).toEqual(buf); }); diff --git a/yarn-project/simulator/src/avm/opcodes/memory.ts b/yarn-project/simulator/src/avm/opcodes/memory.ts index 66a04494af27..b96e94662284 100644 --- a/yarn-project/simulator/src/avm/opcodes/memory.ts +++ b/yarn-project/simulator/src/avm/opcodes/memory.ts @@ -123,7 +123,7 @@ export class CMov extends Instruction { export class Cast extends TwoOperandInstruction { static readonly type: string = 'CAST'; - static readonly opcode = Opcode.CAST; + static readonly opcode = Opcode.CAST_8; constructor(indirect: number, dstTag: number, srcOffset: number, dstOffset: number) { super(indirect, dstTag, srcOffset, dstOffset); diff --git a/yarn-project/simulator/src/avm/serialization/bytecode_serialization.ts b/yarn-project/simulator/src/avm/serialization/bytecode_serialization.ts index 37618116ff40..24f2a8ed6ed5 100644 --- a/yarn-project/simulator/src/avm/serialization/bytecode_serialization.ts +++ b/yarn-project/simulator/src/avm/serialization/bytecode_serialization.ts @@ -96,12 +96,14 @@ const INSTRUCTION_SET = () => [Opcode.OR_16, Or.as(Or.wireFormat16).deserialize], [Opcode.XOR_8, Xor.as(Xor.wireFormat8).deserialize], [Opcode.XOR_16, Xor.as(Xor.wireFormat16).deserialize], - [Not.opcode, Instruction.deserialize.bind(Not)], + [Opcode.NOT_8, Not.as(Not.wireFormat8).deserialize], + [Opcode.NOT_16, Not.as(Not.wireFormat8).deserialize], [Opcode.SHL_8, Shl.as(Shl.wireFormat8).deserialize], [Opcode.SHL_16, Shl.as(Shl.wireFormat16).deserialize], [Opcode.SHR_8, Shr.as(Shr.wireFormat8).deserialize], [Opcode.SHR_16, Shr.as(Shr.wireFormat16).deserialize], - [Cast.opcode, Instruction.deserialize.bind(Cast)], + [Opcode.CAST_8, Cast.as(Cast.wireFormat8).deserialize], + [Opcode.CAST_16, Cast.as(Cast.wireFormat16).deserialize], [Address.opcode, Instruction.deserialize.bind(Address)], [StorageAddress.opcode, Instruction.deserialize.bind(StorageAddress)], [Sender.opcode, Instruction.deserialize.bind(Sender)], diff --git a/yarn-project/simulator/src/avm/serialization/instruction_serialization.ts b/yarn-project/simulator/src/avm/serialization/instruction_serialization.ts index 277b9d797a6b..140a586f5ec2 100644 --- a/yarn-project/simulator/src/avm/serialization/instruction_serialization.ts +++ b/yarn-project/simulator/src/avm/serialization/instruction_serialization.ts @@ -30,12 +30,14 @@ export enum Opcode { OR_16, XOR_8, XOR_16, - NOT, + NOT_8, + NOT_16, SHL_8, SHL_16, SHR_8, SHR_16, - CAST, + CAST_8, + CAST_16, // Execution environment ADDRESS, STORAGEADDRESS, From 725d8d2a3e59fbff1a0712739d4fee1988c5cafe Mon Sep 17 00:00:00 2001 From: fcarreiro Date: Wed, 11 Sep 2024 14:13:25 +0000 Subject: [PATCH 3/5] cpp side --- .../vm/avm/tests/execution.test.cpp | 60 +++++++++---------- .../barretenberg/vm/avm/trace/alu_trace.cpp | 15 ++--- .../vm/avm/trace/deserialization.cpp | 6 +- .../barretenberg/vm/avm/trace/execution.cpp | 24 ++++++-- .../barretenberg/vm/avm/trace/fixed_gas.cpp | 6 +- .../src/barretenberg/vm/avm/trace/opcode.cpp | 12 ++-- .../src/barretenberg/vm/avm/trace/opcode.hpp | 6 +- .../src/barretenberg/vm/avm/trace/trace.cpp | 4 +- 8 files changed, 78 insertions(+), 55 deletions(-) diff --git a/barretenberg/cpp/src/barretenberg/vm/avm/tests/execution.test.cpp b/barretenberg/cpp/src/barretenberg/vm/avm/tests/execution.test.cpp index 00b53ce7d93a..bb6302e86626 100644 --- a/barretenberg/cpp/src/barretenberg/vm/avm/tests/execution.test.cpp +++ b/barretenberg/cpp/src/barretenberg/vm/avm/tests/execution.test.cpp @@ -730,11 +730,11 @@ TEST_F(AvmExecutionTests, setAndCastOpcodes) "02" // U16 "B813" // val 47123 "0011" // dst_offset 17 - + to_hex(OpCode::CAST) + // opcode CAST + + to_hex(OpCode::CAST_8) + // opcode CAST "00" // Indirect flag "01" // U8 - "00000011" // addr a - "00000012" // addr casted a + "11" // addr a + "12" // addr casted a + to_hex(OpCode::RETURN) + // opcode RETURN "00" // Indirect flag "00000000" // ret offset 0 @@ -747,12 +747,12 @@ TEST_F(AvmExecutionTests, setAndCastOpcodes) // SUB EXPECT_THAT(instructions.at(1), - AllOf(Field(&Instruction::op_code, OpCode::CAST), + AllOf(Field(&Instruction::op_code, OpCode::CAST_8), Field(&Instruction::operands, ElementsAre(VariantWith(0), VariantWith(AvmMemoryTag::U8), - VariantWith(17), - VariantWith(18))))); + VariantWith(17), + VariantWith(18))))); auto trace = gen_trace_from_instr(instructions); @@ -1238,16 +1238,16 @@ TEST_F(AvmExecutionTests, embeddedCurveAddOpCode) "00000000" // cd_offset "00000001" // copy_size "00000000" // dst_offset - + to_hex(OpCode::CAST) + // opcode CAST inf to U8 + + to_hex(OpCode::CAST_8) + // opcode CAST inf to U8 "00" // Indirect flag "01" // U8 tag field - "00000002" // a_is_inf - "00000002" // a_is_inf - + to_hex(OpCode::CAST) + // opcode CAST inf to U8 + "02" // a_is_inf + "02" // a_is_inf + + to_hex(OpCode::CAST_8) + // opcode CAST inf to U8 "00" // Indirect flag "01" // U8 tag field - "00000005" // b_is_inf - "00000005" // b_is_inf + "05" // b_is_inf + "05" // b_is_inf + to_hex(OpCode::SET_8) + // opcode SET for direct src_length "00" // Indirect flag "03" // U32 @@ -1314,16 +1314,16 @@ TEST_F(AvmExecutionTests, msmOpCode) "00000000" // cd_offset 0 "00000001" // copy_size (10 elements) "00000000" // dst_offset 0 - + to_hex(OpCode::CAST) + // opcode CAST inf to U8 + + to_hex(OpCode::CAST_8) + // opcode CAST inf to U8 "00" // Indirect flag "01" // U8 tag field - "00000002" // a_is_inf - "00000002" // - + to_hex(OpCode::CAST) + // opcode CAST inf to U8 + "02" // a_is_inf + "02" // + + to_hex(OpCode::CAST_8) + // opcode CAST inf to U8 "00" // Indirect flag "01" // U8 tag field - "00000005" // b_is_inf - "00000005" // + "05" // b_is_inf + "05" // + to_hex(OpCode::SET_8) + // opcode SET for length "00" // Indirect flag "03" // U32 @@ -1758,11 +1758,11 @@ TEST_F(AvmExecutionTests, kernelOutputEmitOpcodes) "01" // value 1 "01" // dst_offset 1 // Cast set to field - + to_hex(OpCode::CAST) + // opcode CAST + + to_hex(OpCode::CAST_8) + // opcode CAST "00" // Indirect flag "06" // tag field - "00000001" // dst 1 - "00000001" // dst 1 + "01" // dst 1 + "01" // dst 1 + to_hex(OpCode::EMITNOTEHASH) + // opcode EMITNOTEHASH "00" // Indirect flag "00000001" // src offset 1 @@ -1859,11 +1859,11 @@ TEST_F(AvmExecutionTests, kernelOutputStorageLoadOpcodeSimple) "03" // U32 "09" // value 9 "01" // dst_offset 1 - + to_hex(OpCode::CAST) + // opcode CAST (Cast set to field) + + to_hex(OpCode::CAST_8) + // opcode CAST (Cast set to field) "00" // Indirect flag "06" // tag field - "00000001" // dst 1 - "00000001" // dst 1 + "01" // dst 1 + "01" // dst 1 + to_hex(OpCode::SLOAD) + // opcode SLOAD "00" // Indirect flag "00000001" // slot offset 1 @@ -1972,11 +1972,11 @@ TEST_F(AvmExecutionTests, kernelOutputStorageOpcodes) "09" // value 9 "01" // dst_offset 1 // Cast set to field - + to_hex(OpCode::CAST) + // opcode CAST + + to_hex(OpCode::CAST_8) + // opcode CAST "00" // Indirect flag "06" // tag field - "00000001" // dst 1 - "00000001" // dst 1 + "01" // dst 1 + "01" // dst 1 + to_hex(OpCode::SLOAD) + // opcode SLOAD "00" // Indirect flag "00000001" // slot offset 1 @@ -2047,11 +2047,11 @@ TEST_F(AvmExecutionTests, kernelOutputHashExistsOpcodes) "01" // value 1 "01" // dst_offset 1 // Cast set to field - + to_hex(OpCode::CAST) + // opcode CAST + + to_hex(OpCode::CAST_8) + // opcode CAST "00" // Indirect flag "06" // tag field - "00000001" // dst 1 - "00000001" // dst 1 + "01" // dst 1 + "01" // dst 1 + to_hex(OpCode::NOTEHASHEXISTS) + // opcode NOTEHASHEXISTS "00" // Indirect flag "00000001" // slot offset 1 diff --git a/barretenberg/cpp/src/barretenberg/vm/avm/trace/alu_trace.cpp b/barretenberg/cpp/src/barretenberg/vm/avm/trace/alu_trace.cpp index b305c233b854..a4111e0b6c77 100644 --- a/barretenberg/cpp/src/barretenberg/vm/avm/trace/alu_trace.cpp +++ b/barretenberg/cpp/src/barretenberg/vm/avm/trace/alu_trace.cpp @@ -425,7 +425,7 @@ FF AvmAluTraceBuilder::op_not(FF const& a, AvmMemoryTag in_tag, uint32_t const c alu_trace.push_back(AvmAluTraceBuilder::AluTraceEntry{ .alu_clk = clk, - .opcode = OpCode::NOT, + .opcode = OpCode::NOT_8, // FIXME: take into account all opcodes. .tag = in_tag, .alu_ia = a, .alu_ic = c, @@ -585,7 +585,7 @@ FF AvmAluTraceBuilder::op_cast(FF const& a, AvmMemoryTag in_tag, uint32_t clk) } alu_trace.push_back(AvmAluTraceBuilder::AluTraceEntry{ .alu_clk = clk, - .opcode = OpCode::CAST, + .opcode = OpCode::CAST_8, // FIXME: take into account all opcodes. .tag = in_tag, .alu_ia = a, .alu_ic = c, @@ -618,9 +618,10 @@ bool AvmAluTraceBuilder::is_range_check_required() const bool AvmAluTraceBuilder::is_alu_row_enabled(const AvmAluTraceBuilder::AluTraceEntry& r) { return (r.opcode == OpCode::ADD_8 || r.opcode == OpCode::SUB_8 || r.opcode == OpCode::MUL_8 || - r.opcode == OpCode::EQ_8 || r.opcode == OpCode::NOT || r.opcode == OpCode::LT_8 || - r.opcode == OpCode::LTE_8 || r.opcode == OpCode::SHR_8 || r.opcode == OpCode::SHL_8 || - r.opcode == OpCode::CAST || r.opcode == OpCode::DIV_8); + r.opcode == OpCode::EQ_8 || r.opcode == OpCode::NOT_8 || r.opcode == OpCode::NOT_16 || + r.opcode == OpCode::LT_8 || r.opcode == OpCode::LTE_8 || r.opcode == OpCode::SHR_8 || + r.opcode == OpCode::SHL_8 || r.opcode == OpCode::CAST_8 || r.opcode == OpCode::CAST_8 || + r.opcode == OpCode::CAST_16 || r.opcode == OpCode::DIV_8); } /** @@ -640,11 +641,11 @@ void AvmAluTraceBuilder::finalize(std::vector>& main_trace) dest.alu_op_add = FF(src.opcode == OpCode::ADD_8 || src.opcode == OpCode::ADD_16 ? 1 : 0); dest.alu_op_sub = FF(src.opcode == OpCode::SUB_8 || src.opcode == OpCode::SUB_16 ? 1 : 0); dest.alu_op_mul = FF(src.opcode == OpCode::MUL_8 || src.opcode == OpCode::MUL_16 ? 1 : 0); - dest.alu_op_not = FF(src.opcode == OpCode::NOT ? 1 : 0); + dest.alu_op_not = FF(src.opcode == OpCode::NOT_8 || src.opcode == OpCode::NOT_16 ? 1 : 0); dest.alu_op_eq = FF(src.opcode == OpCode::EQ_8 || src.opcode == OpCode::EQ_16 ? 1 : 0); dest.alu_op_lt = FF(src.opcode == OpCode::LT_8 || src.opcode == OpCode::LT_16 ? 1 : 0); dest.alu_op_lte = FF(src.opcode == OpCode::LTE_8 || src.opcode == OpCode::LTE_16 ? 1 : 0); - dest.alu_op_cast = FF(src.opcode == OpCode::CAST ? 1 : 0); + dest.alu_op_cast = FF(src.opcode == OpCode::CAST_8 || src.opcode == OpCode::CAST_16 ? 1 : 0); dest.alu_op_shr = FF(src.opcode == OpCode::SHR_8 || src.opcode == OpCode::SHR_16 ? 1 : 0); dest.alu_op_shl = FF(src.opcode == OpCode::SHL_8 || src.opcode == OpCode::SHL_16 ? 1 : 0); dest.alu_op_div = FF(src.opcode == OpCode::DIV_8 || src.opcode == OpCode::DIV_16 ? 1 : 0); diff --git a/barretenberg/cpp/src/barretenberg/vm/avm/trace/deserialization.cpp b/barretenberg/cpp/src/barretenberg/vm/avm/trace/deserialization.cpp index d5793f7d9a52..115f965b7c4f 100644 --- a/barretenberg/cpp/src/barretenberg/vm/avm/trace/deserialization.cpp +++ b/barretenberg/cpp/src/barretenberg/vm/avm/trace/deserialization.cpp @@ -66,13 +66,15 @@ const std::unordered_map> OPCODE_WIRE_FORMAT = { OpCode::OR_16, three_operand_format16 }, { OpCode::XOR_8, three_operand_format8 }, { OpCode::XOR_16, three_operand_format16 }, - { OpCode::NOT, { OperandType::INDIRECT, OperandType::TAG, OperandType::UINT8, OperandType::UINT8 } }, + { OpCode::NOT_8, { OperandType::INDIRECT, OperandType::TAG, OperandType::UINT8, OperandType::UINT8 } }, + { OpCode::NOT_16, { OperandType::INDIRECT, OperandType::TAG, OperandType::UINT16, OperandType::UINT16 } }, { OpCode::SHL_8, three_operand_format8 }, { OpCode::SHL_16, three_operand_format16 }, { OpCode::SHR_8, three_operand_format8 }, { OpCode::SHR_16, three_operand_format16 }, // Compute - Type Conversions - { OpCode::CAST, { OperandType::INDIRECT, OperandType::TAG, OperandType::UINT32, OperandType::UINT32 } }, + { OpCode::CAST_8, { OperandType::INDIRECT, OperandType::TAG, OperandType::UINT8, OperandType::UINT8 } }, + { OpCode::CAST_16, { OperandType::INDIRECT, OperandType::TAG, OperandType::UINT16, OperandType::UINT16 } }, // Execution Environment - Globals { OpCode::ADDRESS, getter_format }, diff --git a/barretenberg/cpp/src/barretenberg/vm/avm/trace/execution.cpp b/barretenberg/cpp/src/barretenberg/vm/avm/trace/execution.cpp index eabc14ae0734..ff9384f333ec 100644 --- a/barretenberg/cpp/src/barretenberg/vm/avm/trace/execution.cpp +++ b/barretenberg/cpp/src/barretenberg/vm/avm/trace/execution.cpp @@ -556,10 +556,16 @@ std::vector Execution::gen_trace(std::vector const& instructio std::get(inst.operands.at(4)), std::get(inst.operands.at(1))); break; - case OpCode::NOT: + case OpCode::NOT_8: trace_builder.op_not(std::get(inst.operands.at(0)), - std::get(inst.operands.at(2)), - std::get(inst.operands.at(3)), + std::get(inst.operands.at(2)), + std::get(inst.operands.at(3)), + std::get(inst.operands.at(1))); + break; + case OpCode::NOT_16: + trace_builder.op_not(std::get(inst.operands.at(0)), + std::get(inst.operands.at(2)), + std::get(inst.operands.at(3)), std::get(inst.operands.at(1))); break; case OpCode::SHL_8: @@ -592,10 +598,16 @@ std::vector Execution::gen_trace(std::vector const& instructio break; // Compute - Type Conversions - case OpCode::CAST: + case OpCode::CAST_8: trace_builder.op_cast(std::get(inst.operands.at(0)), - std::get(inst.operands.at(2)), - std::get(inst.operands.at(3)), + std::get(inst.operands.at(2)), + std::get(inst.operands.at(3)), + std::get(inst.operands.at(1))); + break; + case OpCode::CAST_16: + trace_builder.op_cast(std::get(inst.operands.at(0)), + std::get(inst.operands.at(2)), + std::get(inst.operands.at(3)), std::get(inst.operands.at(1))); break; diff --git a/barretenberg/cpp/src/barretenberg/vm/avm/trace/fixed_gas.cpp b/barretenberg/cpp/src/barretenberg/vm/avm/trace/fixed_gas.cpp index ba61d8efc499..cf34e1d46919 100644 --- a/barretenberg/cpp/src/barretenberg/vm/avm/trace/fixed_gas.cpp +++ b/barretenberg/cpp/src/barretenberg/vm/avm/trace/fixed_gas.cpp @@ -40,12 +40,14 @@ const std::unordered_map GAS_COST_TABLE = { { OpCode::OR_16, make_cost(AVM_OR_BASE_L2_GAS, 0, AVM_OR_DYN_L2_GAS, 0) }, { OpCode::XOR_8, make_cost(AVM_XOR_BASE_L2_GAS, 0, AVM_XOR_DYN_L2_GAS, 0) }, { OpCode::XOR_16, make_cost(AVM_XOR_BASE_L2_GAS, 0, AVM_XOR_DYN_L2_GAS, 0) }, - { OpCode::NOT, make_cost(AVM_NOT_BASE_L2_GAS, 0, AVM_NOT_DYN_L2_GAS, 0) }, + { OpCode::NOT_8, make_cost(AVM_NOT_BASE_L2_GAS, 0, AVM_NOT_DYN_L2_GAS, 0) }, + { OpCode::NOT_16, make_cost(AVM_NOT_BASE_L2_GAS, 0, AVM_NOT_DYN_L2_GAS, 0) }, { OpCode::SHL_8, make_cost(AVM_SHL_BASE_L2_GAS, 0, AVM_SHL_DYN_L2_GAS, 0) }, { OpCode::SHL_16, make_cost(AVM_SHL_BASE_L2_GAS, 0, AVM_SHL_DYN_L2_GAS, 0) }, { OpCode::SHR_8, make_cost(AVM_SHR_BASE_L2_GAS, 0, AVM_SHR_DYN_L2_GAS, 0) }, { OpCode::SHR_16, make_cost(AVM_SHR_BASE_L2_GAS, 0, AVM_SHR_DYN_L2_GAS, 0) }, - { OpCode::CAST, make_cost(AVM_CAST_BASE_L2_GAS, 0, AVM_CAST_DYN_L2_GAS, 0) }, + { OpCode::CAST_8, make_cost(AVM_CAST_BASE_L2_GAS, 0, AVM_CAST_DYN_L2_GAS, 0) }, + { OpCode::CAST_16, make_cost(AVM_CAST_BASE_L2_GAS, 0, AVM_CAST_DYN_L2_GAS, 0) }, { OpCode::ADDRESS, make_cost(AVM_ADDRESS_BASE_L2_GAS, 0, AVM_ADDRESS_DYN_L2_GAS, 0) }, { OpCode::STORAGEADDRESS, make_cost(AVM_STORAGEADDRESS_BASE_L2_GAS, 0, AVM_STORAGEADDRESS_DYN_L2_GAS, 0) }, { OpCode::SENDER, make_cost(AVM_SENDER_BASE_L2_GAS, 0, AVM_SENDER_DYN_L2_GAS, 0) }, diff --git a/barretenberg/cpp/src/barretenberg/vm/avm/trace/opcode.cpp b/barretenberg/cpp/src/barretenberg/vm/avm/trace/opcode.cpp index 4e71de41b396..5eece456d0db 100644 --- a/barretenberg/cpp/src/barretenberg/vm/avm/trace/opcode.cpp +++ b/barretenberg/cpp/src/barretenberg/vm/avm/trace/opcode.cpp @@ -69,8 +69,10 @@ std::string to_string(OpCode opcode) return "XOR_8"; case OpCode::XOR_16: return "XOR_16"; - case OpCode::NOT: - return "NOT"; + case OpCode::NOT_8: + return "NOT_8"; + case OpCode::NOT_16: + return "NOT_16"; case OpCode::SHL_8: return "SHL_8"; case OpCode::SHL_16: @@ -80,8 +82,10 @@ std::string to_string(OpCode opcode) case OpCode::SHR_16: return "SHR_16"; // Compute - Type Conversions - case OpCode::CAST: - return "CAST"; + case OpCode::CAST_8: + return "CAST_8"; + case OpCode::CAST_16: + return "CAST_16"; // Execution Environment case OpCode::ADDRESS: return "ADDRESS"; diff --git a/barretenberg/cpp/src/barretenberg/vm/avm/trace/opcode.hpp b/barretenberg/cpp/src/barretenberg/vm/avm/trace/opcode.hpp index 5237a6db1706..a60469864fd6 100644 --- a/barretenberg/cpp/src/barretenberg/vm/avm/trace/opcode.hpp +++ b/barretenberg/cpp/src/barretenberg/vm/avm/trace/opcode.hpp @@ -43,12 +43,14 @@ enum class OpCode : uint8_t { OR_16, XOR_8, XOR_16, - NOT, + NOT_8, + NOT_16, SHL_8, SHL_16, SHR_8, SHR_16, - CAST, + CAST_8, + CAST_16, // Execution Environment ADDRESS, diff --git a/barretenberg/cpp/src/barretenberg/vm/avm/trace/trace.cpp b/barretenberg/cpp/src/barretenberg/vm/avm/trace/trace.cpp index 459f790f8aee..0be9049ffe04 100644 --- a/barretenberg/cpp/src/barretenberg/vm/avm/trace/trace.cpp +++ b/barretenberg/cpp/src/barretenberg/vm/avm/trace/trace.cpp @@ -1014,7 +1014,7 @@ void AvmTraceBuilder::op_not(uint8_t indirect, uint32_t a_offset, uint32_t dst_o auto write_c = constrained_write_to_memory(call_ptr, clk, resolved_c, c, in_tag, in_tag, IntermRegister::IC); // Constrain gas cost - gas_trace_builder.constrain_gas(clk, OpCode::NOT); + gas_trace_builder.constrain_gas(clk, OpCode::NOT_8); main_trace.push_back(Row{ .main_clk = clk, @@ -1193,7 +1193,7 @@ void AvmTraceBuilder::op_cast(uint8_t indirect, uint32_t a_offset, uint32_t dst_ mem_trace_builder.write_into_memory(call_ptr, clk, IntermRegister::IC, direct_dst_offset, c, memEntry.tag, dst_tag); // Constrain gas cost - gas_trace_builder.constrain_gas(clk, OpCode::CAST); + gas_trace_builder.constrain_gas(clk, OpCode::CAST_8); main_trace.push_back(Row{ .main_clk = clk, From bd8b17b50eaaa9d7b2285f7857caff322e8fed38 Mon Sep 17 00:00:00 2001 From: fcarreiro Date: Wed, 11 Sep 2024 17:26:42 +0000 Subject: [PATCH 4/5] fix ts serialization --- .../simulator/src/avm/serialization/bytecode_serialization.ts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yarn-project/simulator/src/avm/serialization/bytecode_serialization.ts b/yarn-project/simulator/src/avm/serialization/bytecode_serialization.ts index 24f2a8ed6ed5..da4ded884237 100644 --- a/yarn-project/simulator/src/avm/serialization/bytecode_serialization.ts +++ b/yarn-project/simulator/src/avm/serialization/bytecode_serialization.ts @@ -97,7 +97,7 @@ const INSTRUCTION_SET = () => [Opcode.XOR_8, Xor.as(Xor.wireFormat8).deserialize], [Opcode.XOR_16, Xor.as(Xor.wireFormat16).deserialize], [Opcode.NOT_8, Not.as(Not.wireFormat8).deserialize], - [Opcode.NOT_16, Not.as(Not.wireFormat8).deserialize], + [Opcode.NOT_16, Not.as(Not.wireFormat16).deserialize], [Opcode.SHL_8, Shl.as(Shl.wireFormat8).deserialize], [Opcode.SHL_16, Shl.as(Shl.wireFormat16).deserialize], [Opcode.SHR_8, Shr.as(Shr.wireFormat8).deserialize], From 8c93d6816686f948c5338247708977dadbe2ff5e Mon Sep 17 00:00:00 2001 From: fcarreiro Date: Wed, 11 Sep 2024 17:55:35 +0000 Subject: [PATCH 5/5] fix rs opcode list --- avm-transpiler/src/opcodes.rs | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/avm-transpiler/src/opcodes.rs b/avm-transpiler/src/opcodes.rs index f3fdd14dc6ca..93d1a3ba7eaf 100644 --- a/avm-transpiler/src/opcodes.rs +++ b/avm-transpiler/src/opcodes.rs @@ -26,7 +26,8 @@ pub enum AvmOpcode { OR_16, XOR_8, XOR_16, - NOT, + NOT_8, + NOT_16, SHL_8, SHL_16, SHR_8, @@ -128,7 +129,8 @@ impl AvmOpcode { AvmOpcode::OR_16 => "OR_16", AvmOpcode::XOR_8 => "XOR_8", AvmOpcode::XOR_16 => "XOR_16", - AvmOpcode::NOT => "NOT", + AvmOpcode::NOT_8 => "NOT_8", + AvmOpcode::NOT_16 => "NOT_16", AvmOpcode::SHL_8 => "SHL_8", AvmOpcode::SHL_16 => "SHL_16", AvmOpcode::SHR_8 => "SHR_8",