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Merge pull request #6 from AUDIY/Release_v1
Release v1
2 parents d59cb9f + 29ccf76 commit d238e8c

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17 files changed

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‎01_DPRAM_CONT/DPRAM_CONT.v

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*
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* Simple Dual Port RAM Controller to operate as Ring-Buffer.
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*
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* Version: 0.23
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* Version: 1.00
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* Author : AUDIY
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* Date : 2023/12/23
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* Date : 2025/01/20
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*
1010
* Port
1111
* Input

‎01_DPRAM_CONT/DPRAM_CONT_TB.v

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*
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* Test Bench for DPRAM_CONT.v
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*
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* Version: 0.23
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* Version: 1.00
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* Author : AUDIY
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* Date : 2023/12/23
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* Date : 2025/01/20
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*
1010
* License
1111
--------------------------------------------------------------------------------

‎02_DATA_BUFFER/DATA_BUFFER.v

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*
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* Input DATA Buffer with RAM
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*
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* Version: 0.13
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* Version: 1.00
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* Author : AUDIY
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* Date : 2023/12/23
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* Date : 2025/01/20
99
*
1010
* Port
1111
* Input

‎02_DATA_BUFFER/DATA_BUFFER_TB.v

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*
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* Test bench for DATA_BUFFER.v
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*
6-
* Version: 0.12
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* Version: 1.00
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* Author : AUDIY
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* Date : 2023/12/23
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* Date : 2025/01/20
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*
1010
* License
1111
--------------------------------------------------------------------------------

‎02_DATA_BUFFER/SDPRAM_SINGLECLK.v

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@@ -3,9 +3,9 @@
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*
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* Simple Dual-Port RAM (Single Clock)
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*
6-
* Version: 0.11
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* Version: 1.00
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* Author : AUDIY
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* Date : 2023/12/21
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* Date : 2025/01/20
99
*
1010
* Port
1111
* Input

‎03_SPROM_CONT/SPROM_CONT.v

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@@ -3,9 +3,9 @@
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*
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* Single Port ROM Controller to Output Filter Coefficients.
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*
6-
* Version: 0.18
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* Version: 1.00
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* Author : AUDIY
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* Date : 2023/12/23
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* Date : 2025/01/20
99
*
1010
* Port
1111
* Input

‎03_SPROM_CONT/SPROM_CONT_TB.v

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*
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* Test Bench for SPROM_CONT.v
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*
6-
* Version: 0.18
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* Version: 1.00
77
* Author : AUDIY
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* Date : 2023/12/23
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* Date : 2025/01/20
99
*
1010
* License
1111
--------------------------------------------------------------------------------

‎04_FIR_COEF/FIR_COEF.v

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@@ -3,9 +3,9 @@
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*
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* FIR Coefficients ROM.
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*
6-
* Version: 0.16
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* Version: 1.00
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* Author : AUDIY
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* Date : 2023/12/23
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* Date : 2025/01/20
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*
1010
* Port
1111
* Input

‎04_FIR_COEF/FIR_COEF_TB.v

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@@ -3,9 +3,9 @@
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*
44
* Test Bench for FIR_COEF.v
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*
6-
* Version: 0.15
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* Version: 1.00
77
* Author : AUDIY
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* Date : 2023/12/23
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* Date : 2025/01/20
99
*
1010
* License
1111
--------------------------------------------------------------------------------

‎04_FIR_COEF/SPROM.v

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*
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* Single-Port ROM
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*
6-
* Version: 0.10
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* Version: 1.00
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* Author : AUDIY
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* Date : 2023/12/10
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* Date : 2025/01/20
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*
1010
* Port
1111
* Input

‎05_MULT/MULT.v

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@@ -3,9 +3,9 @@
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*
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* PCM DATA & Digital Filter Multiplier w/ input & output register.
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*
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* Version: 0.15
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* Version: 1.00
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* Author : AUDIY
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* Date : 2023/12/23
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* Date : 2025/01/20
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*
1010
* Port
1111
* Input

‎05_MULT/MULT_TB.v

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*
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* Test Bench for MULT.v
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*
6-
* Version: 0.15
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* Version: 1.00
77
* Author : AUDIY
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* Date : 2023/12/23
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* Date : 2025/01/20
99
*
1010
* License
1111
--------------------------------------------------------------------------------

‎06_ADD/ADD.v

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*
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* Multiplied Data Integrator w/ input & output register.
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*
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* Version: 0.16
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* Version: 1.00
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* Author : AUDIY
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* Date : 2023/12/23
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* Date : 2025/01/20
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*
1010
* Port
1111
* Input

‎06_ADD/ADD_TB.v

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*
44
* Test Bench for ADD.v
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*
6-
* Version: 0.16
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* Version: 1.00
77
* Author : AUDIY
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* Date : 2023/12/23
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* Date : 2025/01/20
99
*
1010
* License
1111
--------------------------------------------------------------------------------

‎07_FIR_x2/FIR_x2.v

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*
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* Oversampling FIR Filter Module (Oversampling Ratio: x2)
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*
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* Version: 0.16
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* Version: 1.00
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* Author : AUDIY
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* Date : 2023/12/23
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* Date : 2025/01/20
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*
1010
* Port
1111
* Input

‎07_FIR_x2/FIR_x2_TB.v

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*
44
* Test Bench for FIR_x2.v
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*
6-
* Version: 0.16
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* Version: 1.00
77
* Author : AUDIY
8-
* Date : 2023/12/23
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* Date : 2025/01/20
99
*
1010
* License
1111
--------------------------------------------------------------------------------

‎README.md

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@@ -24,6 +24,7 @@ https://audio-diy.hatenablog.com/entry/FIR_x2_howtouse
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2. FIR filter length must be equals to (MCLK_I frequency)/(Sampling frequency)
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3. Test benches are used on Questa - Intel FPGA Starter Edition. So there are no stop command in them.
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4. This project includes asynchronous design now. The author will try to make this completely synchronous design.
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5. When you use in vivado, memory file(.hex) should be changed to data file(.data).
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## Verified Devices
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1. Efinix T20F256I4 on Trion T20 BGA256 Development Kit( https://www.efinixinc.com/products-devkits-triont20.html )

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