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Merge pull request #1 from AUDIY/Chang_Copyright_Notice_to_2025
Chang copyright notice to 2025
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‎01_DPRAM_CONT/DPRAM_CONT.v

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| Copyright AUDIY 2023. |
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‎01_DPRAM_CONT/DPRAM_CONT_TB.v

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‎02_DATA_BUFFER/DATA_BUFFER.v

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‎02_DATA_BUFFER/DATA_BUFFER_TB.v

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‎02_DATA_BUFFER/SDPRAM_SINGLECLK.v

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// Assertion #1: When both of WENABLE_I and RENABLE_I returns 1'b1, RADDR_I and WADDR_I must be different.
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// psl assert always ((WENABLE_I & RENABLE_I == 1'b1) -> (WADDR_I != RADDR_I)) @(posedge CLK_I);
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endmodule
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endmodule

‎03_SPROM_CONT/SPROM_CONT.v

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‎03_SPROM_CONT/SPROM_CONT_TB.v

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‎04_FIR_COEF/FIR_COEF.v

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‎04_FIR_COEF/FIR_COEF_TB.v

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‎04_FIR_COEF/SPROM.v

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end
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endgenerate
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endmodule
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endmodule

‎05_MULT/MULT.v

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‎05_MULT/MULT_TB.v

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‎06_ADD/ADD.v

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‎06_ADD/ADD_TB.v

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‎07_FIR_x2/FIR_x2.v

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‎07_FIR_x2/FIR_x2_TB.v

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‎README.md

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4. Oversample_x2_Tang_Primer_20K.gar for Tang Primer 20K & Gowin EDA v1.9.8.11 Education ( https://github.com/AUDIY/FIR_x2/tree/main/10_Example/04_Tang_Primer_20K )
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## License
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Copyright AUDIY 2023.
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This source describes Open Hardware and is licensed under the CERN-OHL-W v2
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