Fix CPU memory access patterns

[DirtyHairy]

In it's current incarnation, the CPU does not emulate memory access correctly. In particular, several writes / reads can happen in a single cycle. The most importand cases are treated correctly (loads and stores happen in the last cycle), but some VCS ROMs are glitched (most prominently Pole Position).

Fixing this will require to turn each instruction into a full state machine. As a first step, it would be enough to turn address decoding into state machines, fully implement the most critical instructions (JSR, RTS, PHA, PHP, etc.) and wrap the others.